From 5cf807e432f3a9f338e1444e260e7227f70d864d Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Fri, 9 Jan 2026 08:24:13 +0000 Subject: [PATCH] Adds two new Tier 3 targets - `aarch64v8r-unknown-none` and `aarch64v8r-unknown-none-softfloat`. The existing `aarch64-unknown-none` target assumes Armv8.0-A as a baseline. However, Arm recently released the Arm Cortex-R82 processor which is the first to implement the Armv8-R AArch64 mode architecture. This architecture is similar to Armv8-A AArch64, however it has a different set of mandatory features, and is based off of Armv8.4. It is largely unrelated to the existing Armv8-R architecture target (`armv8r-none-eabihf`), which only operates in AArch32 mode. The second `aarch64v8r-unknown-none-softfloat` target allows for possible Armv8-R AArch64 CPUs with no FPU, or for use-cases where FPU register stacking is not desired. As with the existing `aarch64-unknown-none` target we have coupled FPU support and Neon support together - there is no 'has FPU but does not have NEON' target proposed even though the architecture technically allows for it. This PR was developed by Ferrous Systems on behalf of Arm. Arm is the owner of these changes. --- compiler/rustc_target/src/spec/mod.rs | 2 + .../spec/targets/aarch64v8r_unknown_none.rs | 37 +++++ .../aarch64v8r_unknown_none_softfloat.rs | 36 +++++ src/bootstrap/src/core/sanity.rs | 2 + src/doc/rustc/src/SUMMARY.md | 1 + src/doc/rustc/src/platform-support.md | 2 + .../aarch64v8r-unknown-none.md | 84 +++++++++++ .../platform-support/armv8r-none-eabihf.md | 3 + src/tools/tidy/src/target_specific_tests.rs | 2 +- tests/assembly-llvm/targets/targets-elf.rs | 6 + tests/codegen-llvm/aarch64v8r-softfloat.rs | 45 ++++++ .../sanitizer/kasan-emits-instrumentation.rs | 4 +- .../kcfi/add-cfi-normalize-integers-flag.rs | 4 +- .../sanitizer/kcfi/add-kcfi-flag.rs | 4 +- .../sanitizer/kcfi/add-kcfi-offset-flag.rs | 4 +- ...t-kcfi-operand-bundle-attr-sanitize-off.rs | 4 +- ...rand-bundle-itanium-cxx-abi-generalized.rs | 4 +- ...-itanium-cxx-abi-normalized-generalized.rs | 4 +- ...erand-bundle-itanium-cxx-abi-normalized.rs | 4 +- ...mit-kcfi-operand-bundle-itanium-cxx-abi.rs | 4 +- .../kcfi/emit-kcfi-operand-bundle.rs | 4 +- .../kcfi/emit-type-metadata-trait-objects.rs | 4 +- .../sanitizer/kcfi/fn-ptr-reify-shim.rs | 4 +- .../sanitizer/kcfi/naked-function.rs | 4 +- .../sanitizer/sanitize-off-asan-kasan.rs | 4 +- tests/ui/asm/aarch64v8r.rs | 140 ++++++++++++++++++ 26 files changed, 401 insertions(+), 15 deletions(-) create mode 100644 compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs create mode 100644 compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs create mode 100644 src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md create mode 100644 tests/codegen-llvm/aarch64v8r-softfloat.rs create mode 100644 tests/ui/asm/aarch64v8r.rs diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index ef475630d4943..107fc2aef104e 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -1704,6 +1704,8 @@ supported_targets! { ("aarch64-unknown-none-softfloat", aarch64_unknown_none_softfloat), ("aarch64_be-unknown-none-softfloat", aarch64_be_unknown_none_softfloat), ("aarch64-unknown-nuttx", aarch64_unknown_nuttx), + ("aarch64v8r-unknown-none", aarch64v8r_unknown_none), + ("aarch64v8r-unknown-none-softfloat", aarch64v8r_unknown_none_softfloat), ("x86_64-fortanix-unknown-sgx", x86_64_fortanix_unknown_sgx), diff --git a/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs new file mode 100644 index 0000000000000..8f8bbb4a41caf --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs @@ -0,0 +1,37 @@ +use crate::spec::{ + Arch, Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, SanitizerSet, StackProbeType, Target, + TargetMetadata, TargetOptions, +}; + +pub(crate) fn target() -> Target { + let opts = TargetOptions { + // based off the aarch64-unknown-none target at time of addition + linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), + linker: Some("rust-lld".into()), + supported_sanitizers: SanitizerSet::KCFI | SanitizerSet::KERNELADDRESS, + relocation_model: RelocModel::Static, + disable_redzone: true, + max_atomic_width: Some(128), + stack_probes: StackProbeType::Inline, + panic_strategy: PanicStrategy::Abort, + default_uwtable: true, + + // deviations from aarch64-unknown-none: `+v8a` -> `+v8r`; `+v8r` implies `+neon` + features: "+v8r,+strict-align".into(), + ..Default::default() + }; + Target { + llvm_target: "aarch64-unknown-none".into(), + metadata: TargetMetadata { + description: Some("Bare Armv8-R AArch64, hardfloat".into()), + tier: Some(3), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 64, + // $ clang-21 -S -emit-llvm -target aarch64 -mcpu=cortex-r82 stub.c + data_layout: "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32".into(), + arch: Arch::AArch64, + options: opts, + } +} diff --git a/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs new file mode 100644 index 0000000000000..63f518873c609 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs @@ -0,0 +1,36 @@ +use crate::spec::{ + Abi, Arch, Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, SanitizerSet, StackProbeType, + Target, TargetMetadata, TargetOptions, +}; + +pub(crate) fn target() -> Target { + let opts = TargetOptions { + abi: Abi::SoftFloat, + linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), + linker: Some("rust-lld".into()), + relocation_model: RelocModel::Static, + disable_redzone: true, + max_atomic_width: Some(128), + supported_sanitizers: SanitizerSet::KCFI | SanitizerSet::KERNELADDRESS, + stack_probes: StackProbeType::Inline, + panic_strategy: PanicStrategy::Abort, + default_uwtable: true, + + // deviations from aarch64-unknown-none: `+v8a` -> `+v8r` + features: "+v8r,+strict-align,-neon".into(), + ..Default::default() + }; + Target { + llvm_target: "aarch64-unknown-none".into(), + metadata: TargetMetadata { + description: Some("Bare Armv8-R AArch64, softfloat".into()), + tier: Some(3), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 64, + data_layout: "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32".into(), + arch: Arch::AArch64, + options: opts, + } +} diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs index 607b9a384d196..0f88e42e1219a 100644 --- a/src/bootstrap/src/core/sanity.rs +++ b/src/bootstrap/src/core/sanity.rs @@ -38,6 +38,8 @@ pub struct Finder { const STAGE0_MISSING_TARGETS: &[&str] = &[ // just a dummy comment so the list doesn't get onelined "x86_64-unknown-linux-gnuasan", + "aarch64v8r-unknown-none", + "aarch64v8r-unknown-none-softfloat", ]; /// Minimum version threshold for libstdc++ required when using prebuilt LLVM diff --git a/src/doc/rustc/src/SUMMARY.md b/src/doc/rustc/src/SUMMARY.md index 8ceeff2c9685e..ac7ccd626f701 100644 --- a/src/doc/rustc/src/SUMMARY.md +++ b/src/doc/rustc/src/SUMMARY.md @@ -50,6 +50,7 @@ - [aarch64-unknown-linux-gnu](platform-support/aarch64-unknown-linux-gnu.md) - [aarch64-unknown-linux-musl](platform-support/aarch64-unknown-linux-musl.md) - [aarch64-unknown-none*](platform-support/aarch64-unknown-none.md) + - [aarch64v8r-unknown-none*](platform-support/aarch64v8r-unknown-none.md) - [aarch64_be-unknown-none-softfloat](platform-support/aarch64_be-unknown-none-softfloat.md) - [aarch64_be-unknown-linux-musl](platform-support/aarch64_be-unknown-linux-musl.md) - [amdgcn-amd-amdhsa](platform-support/amdgcn-amd-amdhsa.md) diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md index 889f96f5fefab..66dc5902179b2 100644 --- a/src/doc/rustc/src/platform-support.md +++ b/src/doc/rustc/src/platform-support.md @@ -274,6 +274,8 @@ target | std | host | notes [`aarch64-unknown-trusty`](platform-support/trusty.md) | ✓ | | [`aarch64-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | ✓ | | [`aarch64-wrs-vxworks`](platform-support/vxworks.md) | ✓ | | ARM64 VxWorks OS +[`aarch64v8r-unknown-none`](platform-support/aarch64v8r-unknown-none.md) | * | | Bare Armv8-R in AArch64 mode, hardfloat +[`aarch64v8r-unknown-none-softfloat`](platform-support/aarch64v8r-unknown-none.md) | * | | Bare Armv8-R in AArch64 mode, softfloat [`aarch64_be-unknown-hermit`](platform-support/hermit.md) | ✓ | | ARM64 Hermit (big-endian) `aarch64_be-unknown-linux-gnu` | ✓ | ✓ | ARM64 Linux (big-endian) `aarch64_be-unknown-linux-gnu_ilp32` | ✓ | ✓ | ARM64 Linux (big-endian, ILP32 ABI) diff --git a/src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md b/src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md new file mode 100644 index 0000000000000..9e232b3205162 --- /dev/null +++ b/src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md @@ -0,0 +1,84 @@ +# `aarch64v8r-unknown-none` and `aarch64v8r-unknown-none-softfloat` + +* **Tier: 3** +* **Library Support:** core and alloc (bare-metal, `#![no_std]`) + +Bare-metal target for CPUs in the Armv8-R architecture family, running in +AArch64 mode. Processors in this family include the +[Arm Cortex-R82][cortex-r82]. + +For Armv8-R CPUs running in AArch32 mode (such as the Arm Cortex-R52), see +[`armv8r-none-eabihf`](armv8r-none-eabihf.md) instead. + +[cortex-r82]: https://developer.arm.com/processors/Cortex-R82 + +## Target maintainers + +- [Rust Embedded Devices Working Group Arm Team] +- [@rust-lang/arm-maintainers][arm_maintainers] ([rust@arm.com][arm_email]) + +[Rust Embedded Devices Working Group Arm Team]: https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team +[arm_maintainers]: https://github.com/rust-lang/team/blob/master/teams/arm-maintainers.toml +[arm_email]: mailto:rust@arm.com + +## Target CPU and Target Feature options + +Unlike AArch64 v8-A processors, not all AArch64 v8-R processors include an FPU +(that is, not all Armv8-R AArch64 processors implement the optional Armv8 +`FEAT_FP` extension). If you do not have an FPU, or have an FPU but wish to use +a soft-float ABI anyway, you should use the `aarch64v8r-unknown-none-softfloat` +target. If you wish to use the standard hard-float Arm AArch64 calling +convention, and you have an FPU, you can use the `aarch64v8r-unknown-none` +target. + +When using the `aarch64v8r-unknown-none` target, the minimum floating-point +features assumed are the Advanced SIMD features (`FEAT_AdvSIMD`, or `+neon`), +the implementation of which is branded Arm NEON. + +If your processor supports a different set of floating-point features than the +default expectations then these should also be enabled or disabled as needed +with [`-C target-feature=(+/-)`][target-feature]. However, note that currently +Rust does not support building hard-float AArch64 targets with Advanced SIMD +support disabled. It is also possible to tell Rust (or LLVM) that you have a +specific model of Arm processor, using the [`-Ctarget-cpu`][target-cpu] option. +Doing so may change the default set of target-features enabled. + +[target-feature]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-feature +[target-cpu]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-cpu + +## Requirements + +These targets are cross-compiled and use static linking. + +By default, the `lld` linker included with Rust will be used; however, you may +want to use the GNU linker instead. This can be obtained for Windows/Mac/Linux +from the [Arm Developer Website][arm-gnu-toolchain], or possibly from your OS's +package manager. To use it, add the following to your `.cargo/config.toml`: + +```toml +[target.aarch64-unknown-none] +linker = "aarch64-none-elf-ld" +``` + +The GNU linker can also be used by specifying `aarch64-none-elf-gcc` as the +linker. This is needed when using GCC's link time optimization. + +These targets don't provide a linker script, so you'll need to bring your own +according to the specific device you are using. Pass +`-Clink-arg=-Tyour_script.ld` as a rustc argument to make the linker use +`your_script.ld` during linking. + +[arm-gnu-toolchain]: https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain + +## Cross-compilation toolchains and C code + +This target supports C code compiled with the `aarch64-none-elf` target +triple and a suitable `-march` or `-mcpu` flag. + +## Start-up and Low-Level Code + +The [Rust Embedded Devices Working Group Arm Team] maintain the +[`aarch64-cpu`] crate, which may be useful for writing bare-metal code using +this target. + +[`aarch64-cpu`]: https://docs.rs/aarch64-cpu diff --git a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md index 369e86dbfc7e8..f26db6f3547b8 100644 --- a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md +++ b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md @@ -12,6 +12,9 @@ and [Cortex-R52+][cortex-r52-plus]. See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all `arm-none-eabi` targets. +For Armv8-R CPUs running in AArch64 mode (such as the Arm Cortex-R82), see +[`aarch64v8r-unknown-none`](aarch64v8r-unknown-none.md) instead. + [cortex-r52]: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52 [cortex-r52-plus]: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52-plus diff --git a/src/tools/tidy/src/target_specific_tests.rs b/src/tools/tidy/src/target_specific_tests.rs index 11138de5de764..ea365527a8cdf 100644 --- a/src/tools/tidy/src/target_specific_tests.rs +++ b/src/tools/tidy/src/target_specific_tests.rs @@ -98,7 +98,7 @@ fn arch_to_llvm_component(arch: &str) -> String { // enough for the purpose of this tidy check. match arch { "amdgcn" => "amdgpu".into(), - "aarch64_be" | "arm64_32" | "arm64e" | "arm64ec" => "aarch64".into(), + "aarch64v8r" | "aarch64_be" | "arm64_32" | "arm64e" | "arm64ec" => "aarch64".into(), "i386" | "i586" | "i686" | "x86" | "x86_64" | "x86_64h" => "x86".into(), "loongarch32" | "loongarch64" => "loongarch".into(), "nvptx64" => "nvptx".into(), diff --git a/tests/assembly-llvm/targets/targets-elf.rs b/tests/assembly-llvm/targets/targets-elf.rs index 0eced9df3c46d..5cf3c4ecb6c33 100644 --- a/tests/assembly-llvm/targets/targets-elf.rs +++ b/tests/assembly-llvm/targets/targets-elf.rs @@ -67,6 +67,12 @@ //@ revisions: aarch64_unknown_none_softfloat //@ [aarch64_unknown_none_softfloat] compile-flags: --target aarch64-unknown-none-softfloat //@ [aarch64_unknown_none_softfloat] needs-llvm-components: aarch64 +//@ revisions: aarch64v8r_unknown_none +//@ [aarch64v8r_unknown_none] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r_unknown_none] needs-llvm-components: aarch64 +//@ revisions: aarch64v8r_unknown_none_softfloat +//@ [aarch64v8r_unknown_none_softfloat] compile-flags: --target aarch64v8r-unknown-none-softfloat +//@ [aarch64v8r_unknown_none_softfloat] needs-llvm-components: aarch64 //@ revisions: aarch64_unknown_nto_qnx700 //@ [aarch64_unknown_nto_qnx700] compile-flags: --target aarch64-unknown-nto-qnx700 //@ [aarch64_unknown_nto_qnx700] needs-llvm-components: aarch64 diff --git a/tests/codegen-llvm/aarch64v8r-softfloat.rs b/tests/codegen-llvm/aarch64v8r-softfloat.rs new file mode 100644 index 0000000000000..5ccda4f3a0aec --- /dev/null +++ b/tests/codegen-llvm/aarch64v8r-softfloat.rs @@ -0,0 +1,45 @@ +//@ add-minicore +//@ compile-flags: --target aarch64v8r-unknown-none-softfloat -Zmerge-functions=disabled +//@ needs-llvm-components: aarch64 +#![crate_type = "lib"] +#![feature(no_core, lang_items)] +#![no_core] + +extern crate minicore; +use minicore::*; + +// CHECK: i64 @pass_f64_C(i64 {{[^,]*}}) +#[no_mangle] +extern "C" fn pass_f64_C(x: f64) -> f64 { + x +} + +// CHECK: i64 @pass_f32_pair_C(i64 {{[^,]*}}) +#[no_mangle] +extern "C" fn pass_f32_pair_C(x: (f32, f32)) -> (f32, f32) { + x +} + +// CHECK: [2 x i64] @pass_f64_pair_C([2 x i64] {{[^,]*}}) +#[no_mangle] +extern "C" fn pass_f64_pair_C(x: (f64, f64)) -> (f64, f64) { + x +} + +// CHECK: i64 @pass_f64_Rust(i64 {{[^,]*}}) +#[no_mangle] +fn pass_f64_Rust(x: f64) -> f64 { + x +} + +// CHECK: i64 @pass_f32_pair_Rust(i64 {{[^,]*}}) +#[no_mangle] +fn pass_f32_pair_Rust(x: (f32, f32)) -> (f32, f32) { + x +} + +// CHECK: void @pass_f64_pair_Rust(ptr {{.*}}%{{[^ ]+}}, ptr {{.*}}%{{[^ ]+}}) +#[no_mangle] +fn pass_f64_pair_Rust(x: (f64, f64)) -> (f64, f64) { + x +} diff --git a/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs b/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs index da0c976d8a53d..f0135cdd00115 100644 --- a/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs +++ b/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs @@ -2,9 +2,11 @@ //@ add-minicore //@ compile-flags: -Zsanitizer=kernel-address -Copt-level=0 -//@ revisions: aarch64 riscv64imac riscv64gc x86_64 +//@ revisions: aarch64 aarch64v8r riscv64imac riscv64gc x86_64 //@[aarch64] compile-flags: --target aarch64-unknown-none //@[aarch64] needs-llvm-components: aarch64 +//@[aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@[aarch64v8r] needs-llvm-components: aarch64 //@[riscv64imac] compile-flags: --target riscv64imac-unknown-none-elf //@[riscv64imac] needs-llvm-components: riscv //@[riscv64gc] compile-flags: --target riscv64gc-unknown-none-elf diff --git a/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs b/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs index 24c5d1be1d60b..53b8c605eb73b 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs @@ -1,9 +1,11 @@ // Verifies that "cfi-normalize-integers" module flag is added. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Zsanitizer-cfi-normalize-integers diff --git a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs index 53b1a3f2d74a5..9058d5b5cfcb9 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs @@ -1,9 +1,11 @@ // Verifies that "kcfi" module flag is added. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi diff --git a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs index 82747351e0281..6574302033c82 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs @@ -1,9 +1,11 @@ // Verifies that "kcfi-offset" module flag is added. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Z patchable-function-entry=4,3 diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs index ee4928053cf9e..eb9ab6b8f90cb 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs @@ -1,9 +1,11 @@ // Verifies that KCFI operand bundles are omitted. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0 diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs index 9b861c08ac955..f934a3bfcee76 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs @@ -1,9 +1,11 @@ // Verifies that generalized KCFI type metadata for functions are emitted. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Zsanitizer-cfi-generalize-pointers diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs index c2410aa9f4d82..b72b6d7ce308e 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs @@ -1,9 +1,11 @@ // Verifies that normalized and generalized KCFI type metadata for functions are emitted. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Zsanitizer-cfi-normalize-integers -Zsanitizer-cfi-generalize-pointers diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs index fbad335286cb1..064ab53a18561 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs @@ -1,9 +1,11 @@ // Verifies that normalized KCFI type metadata for functions are emitted. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Zsanitizer-cfi-normalize-integers diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs index 6c7a8194ec4eb..8410286e49dbf 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs @@ -1,9 +1,11 @@ // Verifies that KCFI type metadata for functions are emitted. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0 diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs index e22a210f3dfb8..3494854bcffd3 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs @@ -1,9 +1,11 @@ // Verifies that KCFI operand bundles are emitted. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0 diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs index 3312f12f68850..4510e70cbc350 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs @@ -1,9 +1,11 @@ // Verifies that type metadata identifiers for trait objects are emitted correctly. // //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64v8r aarch64 x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0 diff --git a/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs b/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs index 676b2af8c8f1d..8cfb6a57a4a97 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs @@ -1,7 +1,9 @@ //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Cno-prepopulate-passes -Copt-level=0 diff --git a/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs b/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs index 830689780dce5..6b9d11b192b33 100644 --- a/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs +++ b/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs @@ -1,7 +1,9 @@ //@ add-minicore -//@ revisions: aarch64 x86_64 +//@ revisions: aarch64 aarch64v8r x86_64 //@ [aarch64] compile-flags: --target aarch64-unknown-none //@ [aarch64] needs-llvm-components: aarch64 +//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@ [aarch64v8r] needs-llvm-components: aarch64 //@ [x86_64] compile-flags: --target x86_64-unknown-none //@ [x86_64] needs-llvm-components: x86 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Cno-prepopulate-passes -Copt-level=0 diff --git a/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs b/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs index c5df311efae09..cef4a650e4775 100644 --- a/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs +++ b/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs @@ -3,9 +3,11 @@ // //@ add-minicore //@ compile-flags: -Zsanitizer=kernel-address -Ctarget-feature=-crt-static -Copt-level=0 -//@ revisions: aarch64 riscv64imac riscv64gc x86_64 +//@ revisions: aarch64 aarch64v8r riscv64imac riscv64gc x86_64 //@[aarch64] compile-flags: --target aarch64-unknown-none //@[aarch64] needs-llvm-components: aarch64 +//@[aarch64v8r] compile-flags: --target aarch64v8r-unknown-none +//@[aarch64v8r] needs-llvm-components: aarch64 //@[riscv64imac] compile-flags: --target riscv64imac-unknown-none-elf //@[riscv64imac] needs-llvm-components: riscv //@[riscv64gc] compile-flags: --target riscv64gc-unknown-none-elf diff --git a/tests/ui/asm/aarch64v8r.rs b/tests/ui/asm/aarch64v8r.rs new file mode 100644 index 0000000000000..6b582bb730f07 --- /dev/null +++ b/tests/ui/asm/aarch64v8r.rs @@ -0,0 +1,140 @@ +// Codegen test of mandatory Armv8-R AArch64 extensions + +//@ add-minicore +//@ revisions: hf sf +//@ [hf] compile-flags: --target aarch64v8r-unknown-none +//@ [hf] needs-llvm-components: aarch64 +//@ [sf] compile-flags: --target aarch64v8r-unknown-none-softfloat +//@ [sf] needs-llvm-components: aarch64 +//@ build-pass +//@ ignore-backends: gcc + +#![feature(no_core)] +#![no_core] +#![no_main] +#![crate_type = "rlib"] +#![deny(dead_code)] // ensures we call all private functions from the public one + +extern crate minicore; +use minicore::*; + +/* # Mandatory extensions + * + * A comment indicates that the extension has no associated assembly instruction and cannot be + * codegen tested + * + * ## References: + * + * - Arm Architecture Reference Manual for R-profile AArch64 architecture (DDI 0628) -- has the + * list of mandatory extensions + * - Arm Architecture Reference Manual for A-profile architecture (ARM DDI 0487) -- has the + * mapping from features to instructions + * - Feature names in A-profile architecture (109697_0100_02_en Version 1.0) -- overview of + * what each extension mean + * */ +pub fn mandatory_extensions() { + /* ## ARMv8.0 */ + feat_aa64(); + // FEAT_AA64EL0 + // FEAT_AA64EL1 + // FEAT_AA64EL2 + feat_crc32(); + // FEAT_EL0 + // FEAT_EL1 + // FEAT_EL2 + // FEAT_IVIPT + + /* ## ARMv8.1 */ + // FEAT_HPDS + feat_lse(); + feat_pan(); + + /* ## ARMv8.2 */ + feat_asmv8p2(); + feat_dpb(); + // FEAT_Debugv8p2 + // FEAT_PAN2 + feat_ras(); + // FEAT_TTCNP + feat_uao(); + // FEAT_XNX + + /* ## ARMv8.3 */ + feat_lrcpc(); + feat_pauth(); + + /* ## ARMv8.4 */ + feat_dit(); + // FEAT_Debugv8p4 + feat_flagm(); + // FEAT_IDST + feat_lrcpc2(); + // FEAT_LSE2 + // FEAT_S2FWB + feat_tlbios(); + feat_tlbirange(); + // FEAT_TTL +} + +fn feat_aa64() { + // CurrentEL register only present when FEAT_AA64 is implemented + unsafe { asm!("mrs x0, CurrentEL") } +} + +fn feat_crc32() { + // instruction is present when FEAT_CRC32 is implemented + unsafe { asm!("crc32b w0, w1, w2") } +} + +fn feat_lse() { + // instruction is present when FEAT_LSE is implemented + unsafe { asm!("casp w0, w1, w2, w3, [x4]") } +} + +fn feat_pan() { + unsafe { asm!("mrs x0, PAN") } +} + +fn feat_asmv8p2() { + unsafe { asm!("BFC w0, #0, #1") } +} + +fn feat_dpb() { + unsafe { asm!("DC CVAP, x0") } +} + +fn feat_ras() { + unsafe { asm!("ESB") } +} + +fn feat_uao() { + unsafe { asm!("mrs x0, UAO") } +} + +fn feat_lrcpc() { + unsafe { asm!("ldaprb w0, [x1]") } +} + +fn feat_pauth() { + unsafe { asm!("xpacd x0") } +} + +fn feat_dit() { + unsafe { asm!("mrs x0, DIT") } +} + +fn feat_flagm() { + unsafe { asm!("cfinv") } +} + +fn feat_lrcpc2() { + unsafe { asm!("stlurb w0, [x1]") } +} + +fn feat_tlbios() { + unsafe { asm!("tlbi VMALLE1OS") } +} + +fn feat_tlbirange() { + unsafe { asm!("tlbi RVAE1IS, x0") } +}