diff --git a/docs/CL_DMA.md b/docs/CL_DMA.md
new file mode 100644
index 00000000..541f1c7f
--- /dev/null
+++ b/docs/CL_DMA.md
@@ -0,0 +1,268 @@
+## Summary
+
+| Name                                    | Offset   |   Length | Description                                                                                             |
+|:----------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------------------------------|
+| dma.[`INTR_STATE`](#intr_state)         | 0x0      |        4 | Interrupt State Register                                                                                |
+| dma.[`INTR_ENABLE`](#intr_enable)       | 0x4      |        4 | Interrupt Enable Register                                                                               |
+| dma.[`INTR_TEST`](#intr_test)           | 0x8      |        4 | Interrupt Test Register                                                                                 |
+| dma.[`ALERT_TEST`](#alert_test)         | 0xc      |        4 | Alert Test Register                                                                                     |
+| dma.[`CMD`](#cmd)                       | 0x10     |        4 | ?                                                                                                       |
+| dma.[`TID`](#tid)                       | 0x14     |        4 | Transfer identifier value bitfield.                                                                     |
+| dma.[`TCDM_ADDR`](#tcdm_addr)           | 0x18     |        4 | Transfer L1 base address configuration bitfield.                                                        |
+| dma.[`EXT_ADDR`](#ext_addr)             | 0x1c     |        4 | Transfer L2 base address configuration bitfield.                                                        |
+| dma.[`EXT_COUNT_2D`](#ext_count_2d)     | 0x20     |        4 | EXT 2D transfer conut value configuration bitfield.                                                     |
+| dma.[`EXT_STRIDE_2D`](#ext_stride_2d)   | 0x24     |        4 | EXT 2D transfer stride value configuration bitfield.                                                    |
+| dma.[`TCDM_COUNT_2D`](#tcdm_count_2d)   | 0x28     |        4 | TCDM 2D transfer conut value configuration bitfield.                                                    |
+| dma.[`TCDM_STRIDE_2D`](#tcdm_stride_2d) | 0x2c     |        4 | TCDM 2D transfer stride value configuration bitfield.                                                   |
+| dma.[`STATUS`](#status)                 | 0x30     |        4 | ?                                                                                                       |
+| dma.[`TID_FREE`](#tid_free)             | 0x34     |        4 | Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dma_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "dma_chunk_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                               |
+|:------:|:------:|:-------:|:---------------|:--------------------------------------------------------------------------|
+|  31:3  |        |         |                | Reserved                                                                  |
+|   2    |   ro   |   0x0   | dma_error      | DMA error has occurred. DMA_STATUS.error_code register shows the details. |
+|   1    |   ro   |   0x0   | dma_chunk_done | Indicates the transfer of a single chunk has been completed.              |
+|   0    |   ro   |   0x0   | dma_done       | DMA operation has been completed.                                         |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dma_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dma_chunk_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                              |
+|:------:|:------:|:-------:|:---------------|:-------------------------------------------------------------------------|
+|  31:3  |        |         |                | Reserved                                                                 |
+|   2    |   rw   |   0x0   | dma_error      | Enable interrupt when [`INTR_STATE.dma_error`](#intr_state) is set.      |
+|   1    |   rw   |   0x0   | dma_chunk_done | Enable interrupt when [`INTR_STATE.dma_chunk_done`](#intr_state) is set. |
+|   0    |   rw   |   0x0   | dma_done       | Enable interrupt when [`INTR_STATE.dma_done`](#intr_state) is set.       |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dma_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "dma_chunk_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                       |
+|:------:|:------:|:-------:|:---------------|:------------------------------------------------------------------|
+|  31:3  |        |         |                | Reserved                                                          |
+|   2    |   wo   |   0x0   | dma_error      | Write 1 to force [`INTR_STATE.dma_error`](#intr_state) to 1.      |
+|   1    |   wo   |   0x0   | dma_chunk_done | Write 1 to force [`INTR_STATE.dma_chunk_done`](#intr_state) to 1. |
+|   0    |   wo   |   0x0   | dma_done       | Write 1 to force [`INTR_STATE.dma_done`](#intr_state) to 1.       |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CMD
+?
+?
+?
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LEN", "bits": 17, "attr": ["wo"], "rotate": 0}, {"name": "TYPE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "INC", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "EXT_2D", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ELE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ILE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "BLE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TCDM_2D", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                                                                     |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:24  |        |         |         | Reserved                                                                                                                                                                                                        |
+|   23   |   wo   |   0x0   | TCDM_2D | Transfer type configuration bitfield: -1'b0: linear transfer in TCDM interface -1'b1: 2D transfer in TCDM interface                                                                                             |
+|   22   |   wo   |   0x0   | BLE     | Transfer event or interrupt broadcast configuration bitfield: 1'b0: event or interrupt is routed to the cluster core who initiated the transfer. 1'b1: event or interrupt are broadcasted to all cluster cores. |
+|   21   |   wo   |   0x0   | ILE     | Transfer interrupt generation configuration bitfield: -1'b0: disabled. -1'b1: enabled.                                                                                                                          |
+|   20   |   wo   |   0x0   | ELE     | Transfer event generation configuration bitfield: -1'b0: disabled. -1'b1: enabled.                                                                                                                              |
+|   19   |   wo   |   0x0   | EXT_2D  | Transfer type configuration bitfield: -1'b0: linear transfer in EXT interface. -1'b1: 2D transfer in EXT interface.                                                                                             |
+|   18   |   wo   |   0x0   | INC     | Transfer incremental configuration bitfield: -1'b0: non incremental. -1'b1: incremental.                                                                                                                        |
+|   17   |   wo   |   0x0   | TYPE    | Transfer direction configuration bitfield: -1'b0: L1 to L2 -1'b1: L2 to L1                                                                                                                                      |
+|  16:0  |   wo   |   0x0   | LEN     | Transfer length in bytes configuration bitfield.                                                                                                                                                                |
+
+## TID
+Transfer identifier value bitfield.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "get_tid", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                         |
+|:------:|:------:|:-------:|:--------|:------------------------------------|
+|  31:4  |        |         |         | Reserved                            |
+|  3:0   |   ro   |   0x0   | get_tid | Transfer identifier value bitfield. |
+
+## TCDM_ADDR
+Transfer L1 base address configuration bitfield.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tcdm_addr", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                      |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------|
+|  31:0  |   wo   |   0x0   | tcdm_addr | Transfer L1 base address configuration bitfield. |
+
+## EXT_ADDR
+Transfer L2 base address configuration bitfield.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ext_addr", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                      |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------|
+|  31:0  |   wo   |   0x0   | ext_addr | Transfer L2 base address configuration bitfield. |
+
+## EXT_COUNT_2D
+EXT 2D transfer conut value configuration bitfield.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ext_count_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                                         |
+|:------:|:------:|:-------:|:-------------|:----------------------------------------------------|
+|  31:0  |   wo   |   0x0   | ext_count_2D | EXT 2D transfer conut value configuration bitfield. |
+
+## EXT_STRIDE_2D
+EXT 2D transfer stride value configuration bitfield.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ext_stride_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                          |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------------------------|
+|  31:0  |   wo   |   0x0   | ext_stride_2D | EXT 2D transfer stride value configuration bitfield. |
+
+## TCDM_COUNT_2D
+TCDM 2D transfer conut value configuration bitfield.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tcdm_count_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                          |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------------------------|
+|  31:0  |   wo   |   0x0   | tcdm_count_2D | TCDM 2D transfer conut value configuration bitfield. |
+
+## TCDM_STRIDE_2D
+TCDM 2D transfer stride value configuration bitfield.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tcdm_stride_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                           |
+|:------:|:------:|:-------:|:---------------|:------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | tcdm_stride_2D | TCDM 2D transfer stride value configuration bitfield. |
+
+## STATUS
+?
+?
+?
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TID_TR", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "TID_ALLOC", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                               |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:16  |   ro   |   0x0   | TID_ALLOC | Transfer status bitfield: - TID_TR[i]=1'b0 means that transfer allocator with TID i-16 is free. - TID_TR[i]=1'b1 means that transfer allocator with TID i-16 is reserved. |
+|  15:0  |   ro   |   0x0   | TID_TR    | Transfer status bitfield: TID_TR[i]=1'b1 means that transfer with TID i is active.                                                                                        |
+
+## TID_FREE
+Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tid_free", "bits": 16, "attr": ["wo"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                             |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------------------------------------|
+| 31:16  |        |         |          | Reserved                                                                                                |
+|  15:0  |   wo   |   0x0   | tid_free | Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i. |
+
diff --git a/docs/carfield.md b/docs/carfield.md
new file mode 100644
index 00000000..d4e1fa9e
--- /dev/null
+++ b/docs/carfield.md
@@ -0,0 +1,1126 @@
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                            |
+|:-----------------------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| carfield.[`VERSION0`](#version0)                                             | 0x0      |        4 | Cheshire sha256 commit                                                 |
+| carfield.[`VERSION1`](#version1)                                             | 0x4      |        4 | Safety Island sha256 commit                                            |
+| carfield.[`VERSION2`](#version2)                                             | 0x8      |        4 | Security Island sha256 commit                                          |
+| carfield.[`VERSION3`](#version3)                                             | 0xc      |        4 | PULP Cluster sha256 commit                                             |
+| carfield.[`VERSION4`](#version4)                                             | 0x10     |        4 | Spatz CLuster sha256 commit                                            |
+| carfield.[`JEDEC_IDCODE`](#jedec_idcode)                                     | 0x14     |        4 | JEDEC ID CODE -TODO assign-                                            |
+| carfield.[`GENERIC_SCRATCH0`](#generic_scratch0)                             | 0x18     |        4 | Scratch                                                                |
+| carfield.[`GENERIC_SCRATCH1`](#generic_scratch1)                             | 0x1c     |        4 | Scratch                                                                |
+| carfield.[`HOST_RST`](#host_rst)                                             | 0x20     |        4 | Host Domain reset -active high, inverted in HW-                        |
+| carfield.[`PERIPH_RST`](#periph_rst)                                         | 0x24     |        4 | Periph Domain reset -active high, inverted in HW-                      |
+| carfield.[`SAFETY_ISLAND_RST`](#safety_island_rst)                           | 0x28     |        4 | Safety Island reset -active high, inverted in HW-                      |
+| carfield.[`SECURITY_ISLAND_RST`](#security_island_rst)                       | 0x2c     |        4 | Security Island reset -active high, inverted in HW-                    |
+| carfield.[`PULP_CLUSTER_RST`](#pulp_cluster_rst)                             | 0x30     |        4 | PULP Cluster reset -active high, inverted in HW-                       |
+| carfield.[`SPATZ_CLUSTER_RST`](#spatz_cluster_rst)                           | 0x34     |        4 | Spatz Cluster reset -active high, inverted in HW-                      |
+| carfield.[`L2_RST`](#l2_rst)                                                 | 0x38     |        4 | L2 reset -active high, inverted in HW-                                 |
+| carfield.[`PERIPH_ISOLATE`](#periph_isolate)                                 | 0x3c     |        4 | Periph Domain  AXI isolate                                             |
+| carfield.[`SAFETY_ISLAND_ISOLATE`](#safety_island_isolate)                   | 0x40     |        4 | Safety Island AXI isolate                                              |
+| carfield.[`SECURITY_ISLAND_ISOLATE`](#security_island_isolate)               | 0x44     |        4 | Security Island AXI isolate                                            |
+| carfield.[`PULP_CLUSTER_ISOLATE`](#pulp_cluster_isolate)                     | 0x48     |        4 | PULP Cluster AXI isolate                                               |
+| carfield.[`SPATZ_CLUSTER_ISOLATE`](#spatz_cluster_isolate)                   | 0x4c     |        4 | Spatz Cluster AXI isolate                                              |
+| carfield.[`L2_ISOLATE`](#l2_isolate)                                         | 0x50     |        4 | L2 AXI isolate                                                         |
+| carfield.[`PERIPH_ISOLATE_STATUS`](#periph_isolate_status)                   | 0x54     |        4 | Periph Domain AXI isolate status                                       |
+| carfield.[`SAFETY_ISLAND_ISOLATE_STATUS`](#safety_island_isolate_status)     | 0x58     |        4 | Safety Island AXI isolate status                                       |
+| carfield.[`SECURITY_ISLAND_ISOLATE_STATUS`](#security_island_isolate_status) | 0x5c     |        4 | Security Island AXI isolate status                                     |
+| carfield.[`PULP_CLUSTER_ISOLATE_STATUS`](#pulp_cluster_isolate_status)       | 0x60     |        4 | PULP Cluster AXI isolate status                                        |
+| carfield.[`SPATZ_CLUSTER_ISOLATE_STATUS`](#spatz_cluster_isolate_status)     | 0x64     |        4 | Spatz Cluster AXI isolate status                                       |
+| carfield.[`L2_ISOLATE_STATUS`](#l2_isolate_status)                           | 0x68     |        4 | L2 AXI isolate status                                                  |
+| carfield.[`PERIPH_CLK_EN`](#periph_clk_en)                                   | 0x6c     |        4 | Periph Domain clk gate enable                                          |
+| carfield.[`SAFETY_ISLAND_CLK_EN`](#safety_island_clk_en)                     | 0x70     |        4 | Safety Island clk gate enable                                          |
+| carfield.[`SECURITY_ISLAND_CLK_EN`](#security_island_clk_en)                 | 0x74     |        4 | Security Island clk gate enable                                        |
+| carfield.[`PULP_CLUSTER_CLK_EN`](#pulp_cluster_clk_en)                       | 0x78     |        4 | PULP Cluster clk gate enable                                           |
+| carfield.[`SPATZ_CLUSTER_CLK_EN`](#spatz_cluster_clk_en)                     | 0x7c     |        4 | Spatz Cluster clk gate enable                                          |
+| carfield.[`L2_CLK_EN`](#l2_clk_en)                                           | 0x80     |        4 | Shared L2 memory clk gate enable                                       |
+| carfield.[`PERIPH_CLK_SEL`](#periph_clk_sel)                                 | 0x84     |        4 | Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SAFETY_ISLAND_CLK_SEL`](#safety_island_clk_sel)                   | 0x88     |        4 | Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SECURITY_ISLAND_CLK_SEL`](#security_island_clk_sel)               | 0x8c     |        4 | Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) |
+| carfield.[`PULP_CLUSTER_CLK_SEL`](#pulp_cluster_clk_sel)                     | 0x90     |        4 | PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)    |
+| carfield.[`SPATZ_CLUSTER_CLK_SEL`](#spatz_cluster_clk_sel)                   | 0x94     |        4 | Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`L2_CLK_SEL`](#l2_clk_sel)                                         | 0x98     |        4 | L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)       |
+| carfield.[`PERIPH_CLK_DIV_VALUE`](#periph_clk_div_value)                     | 0x9c     |        4 | Periph Domain clk divider value                                        |
+| carfield.[`SAFETY_ISLAND_CLK_DIV_VALUE`](#safety_island_clk_div_value)       | 0xa0     |        4 | Safety Island clk divider value                                        |
+| carfield.[`SECURITY_ISLAND_CLK_DIV_VALUE`](#security_island_clk_div_value)   | 0xa4     |        4 | Security Island clk divider value                                      |
+| carfield.[`PULP_CLUSTER_CLK_DIV_VALUE`](#pulp_cluster_clk_div_value)         | 0xa8     |        4 | PULP Cluster clk divider value                                         |
+| carfield.[`SPATZ_CLUSTER_CLK_DIV_VALUE`](#spatz_cluster_clk_div_value)       | 0xac     |        4 | Spatz Cluster clk divider value                                        |
+| carfield.[`L2_CLK_DIV_VALUE`](#l2_clk_div_value)                             | 0xb0     |        4 | L2 Memory clk divider value                                            |
+| carfield.[`HOST_FETCH_ENABLE`](#host_fetch_enable)                           | 0xb4     |        4 | Host Domain fetch enable                                               |
+| carfield.[`SAFETY_ISLAND_FETCH_ENABLE`](#safety_island_fetch_enable)         | 0xb8     |        4 | Safety Island fetch enable                                             |
+| carfield.[`SECURITY_ISLAND_FETCH_ENABLE`](#security_island_fetch_enable)     | 0xbc     |        4 | Security Island fetch enable                                           |
+| carfield.[`PULP_CLUSTER_FETCH_ENABLE`](#pulp_cluster_fetch_enable)           | 0xc0     |        4 | PULP Cluster fetch enable                                              |
+| carfield.[`SPATZ_CLUSTER_DEBUG_REQ`](#spatz_cluster_debug_req)               | 0xc4     |        4 | Spatz Cluster debug req                                                |
+| carfield.[`HOST_BOOT_ADDR`](#host_boot_addr)                                 | 0xc8     |        4 | Host boot address                                                      |
+| carfield.[`SAFETY_ISLAND_BOOT_ADDR`](#safety_island_boot_addr)               | 0xcc     |        4 | Safety Island boot address                                             |
+| carfield.[`SECURITY_ISLAND_BOOT_ADDR`](#security_island_boot_addr)           | 0xd0     |        4 | Security Island boot address                                           |
+| carfield.[`PULP_CLUSTER_BOOT_ADDR`](#pulp_cluster_boot_addr)                 | 0xd4     |        4 | PULP Cluster boot address                                              |
+| carfield.[`SPATZ_CLUSTER_BOOT_ADDR`](#spatz_cluster_boot_addr)               | 0xd8     |        4 | Spatz Cluster boot address                                             |
+| carfield.[`PULP_CLUSTER_BOOT_ENABLE`](#pulp_cluster_boot_enable)             | 0xdc     |        4 | PULP Cluster boot enable                                               |
+| carfield.[`SPATZ_CLUSTER_BUSY`](#spatz_cluster_busy)                         | 0xe0     |        4 | Spatz Cluster busy                                                     |
+| carfield.[`PULP_CLUSTER_BUSY`](#pulp_cluster_busy)                           | 0xe4     |        4 | PULP Cluster busy                                                      |
+| carfield.[`PULP_CLUSTER_EOC`](#pulp_cluster_eoc)                             | 0xe8     |        4 | PULP Cluster end of computation                                        |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_EN`](#eth_rgmii_phy_clk_div_en)             | 0xec     |        4 | Ethernet RGMII PHY clock divider enable bit                            |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_VALUE`](#eth_rgmii_phy_clk_div_value)       | 0xf0     |        4 | Ethernet RGMII PHY clock divider value                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_EN`](#eth_mdio_clk_div_en)                       | 0xf4     |        4 | Ethernet MDIO clock divider enable bit                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_VALUE`](#eth_mdio_clk_div_value)                 | 0xf8     |        4 | Ethernet MDIO clock divider value                                      |
+
+## VERSION0
+Cheshire sha256 commit
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION0", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION0 |               |
+
+## VERSION1
+Safety Island sha256 commit
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION1", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION1 |               |
+
+## VERSION2
+Security Island sha256 commit
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION2", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION2 |               |
+
+## VERSION3
+PULP Cluster sha256 commit
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION3", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION3 |               |
+
+## VERSION4
+Spatz CLuster sha256 commit
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION4", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION4 |               |
+
+## JEDEC_IDCODE
+JEDEC ID CODE -TODO assign-
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "JEDEC_IDCODE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description   |
+|:------:|:------:|:-------:|:-------------|:--------------|
+|  31:0  |   rw   |   0x0   | JEDEC_IDCODE |               |
+
+## GENERIC_SCRATCH0
+Scratch
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH0 |               |
+
+## GENERIC_SCRATCH1
+Scratch
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH1 |               |
+
+## HOST_RST
+Host Domain reset -active high, inverted in HW-
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_RST", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:1  |        |         |          | Reserved      |
+|   0    |   ro   |   0x0   | HOST_RST |               |
+
+## PERIPH_RST
+Periph Domain reset -active high, inverted in HW-
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_RST |               |
+
+## SAFETY_ISLAND_RST
+Safety Island reset -active high, inverted in HW-
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_RST |               |
+
+## SECURITY_ISLAND_RST
+Security Island reset -active high, inverted in HW-
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_RST |               |
+
+## PULP_CLUSTER_RST
+PULP Cluster reset -active high, inverted in HW-
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_RST |               |
+
+## SPATZ_CLUSTER_RST
+Spatz Cluster reset -active high, inverted in HW-
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_RST |               |
+
+## L2_RST
+L2 reset -active high, inverted in HW-
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:1  |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | L2_RST |               |
+
+## PERIPH_ISOLATE
+Periph Domain  AXI isolate
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:1  |        |         |                | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE |               |
+
+## SAFETY_ISLAND_ISOLATE
+Safety Island AXI isolate
+- Offset: `0x40`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SAFETY_ISLAND_ISOLATE |               |
+
+## SECURITY_ISLAND_ISOLATE
+Security Island AXI isolate
+- Offset: `0x44`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   rw   |   0x1   | SECURITY_ISLAND_ISOLATE |               |
+
+## PULP_CLUSTER_ISOLATE
+PULP Cluster AXI isolate
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x1   | PULP_CLUSTER_ISOLATE |               |
+
+## SPATZ_CLUSTER_ISOLATE
+Spatz Cluster AXI isolate
+- Offset: `0x4c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SPATZ_CLUSTER_ISOLATE |               |
+
+## L2_ISOLATE
+L2 AXI isolate
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE |               |
+
+## PERIPH_ISOLATE_STATUS
+Periph Domain AXI isolate status
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE_STATUS |               |
+
+## SAFETY_ISLAND_ISOLATE_STATUS
+Safety Island AXI isolate status
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_ISOLATE_STATUS |               |
+
+## SECURITY_ISLAND_ISOLATE_STATUS
+Security Island AXI isolate status
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                           | Description   |
+|:------:|:------:|:-------:|:-------------------------------|:--------------|
+|  31:1  |        |         |                                | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_ISOLATE_STATUS |               |
+
+## PULP_CLUSTER_ISOLATE_STATUS
+PULP Cluster AXI isolate status
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+|  31:1  |        |         |                             | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_ISOLATE_STATUS |               |
+
+## SPATZ_CLUSTER_ISOLATE_STATUS
+Spatz Cluster AXI isolate status
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_ISOLATE_STATUS |               |
+
+## L2_ISOLATE_STATUS
+L2 AXI isolate status
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE_STATUS |               |
+
+## PERIPH_CLK_EN
+Periph Domain clk gate enable
+- Offset: `0x6c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x1   | PERIPH_CLK_EN |               |
+
+## SAFETY_ISLAND_CLK_EN
+Safety Island clk gate enable
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_CLK_EN |               |
+
+## SECURITY_ISLAND_CLK_EN
+Security Island clk gate enable
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+|  31:1  |        |         |                        | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_CLK_EN |               |
+
+## PULP_CLUSTER_CLK_EN
+PULP Cluster clk gate enable
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_CLK_EN |               |
+
+## SPATZ_CLUSTER_CLK_EN
+Spatz Cluster clk gate enable
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_CLK_EN |               |
+
+## L2_CLK_EN
+Shared L2 memory clk gate enable
+- Offset: `0x80`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:1  |        |         |           | Reserved      |
+|   0    |   rw   |   0x1   | L2_CLK_EN |               |
+
+## PERIPH_CLK_SEL
+Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x84`
+- Reset default: `0x2`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:2  |        |         |                | Reserved      |
+|  1:0   |   rw   |   0x2   | PERIPH_CLK_SEL |               |
+
+## SAFETY_ISLAND_CLK_SEL
+Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x88`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SAFETY_ISLAND_CLK_SEL |               |
+
+## SECURITY_ISLAND_CLK_SEL
+Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x8c`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x1   | SECURITY_ISLAND_CLK_SEL |               |
+
+## PULP_CLUSTER_CLK_SEL
+PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x90`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:2  |        |         |                      | Reserved      |
+|  1:0   |   rw   |   0x1   | PULP_CLUSTER_CLK_SEL |               |
+
+## SPATZ_CLUSTER_CLK_SEL
+Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x94`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SPATZ_CLUSTER_CLK_SEL |               |
+
+## L2_CLK_SEL
+L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x98`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:2  |        |         |            | Reserved      |
+|  1:0   |   rw   |   0x1   | L2_CLK_SEL |               |
+
+## PERIPH_CLK_DIV_VALUE
+Periph Domain clk divider value
+- Offset: `0x9c`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+| 31:24  |        |         |                      | Reserved      |
+|  23:0  |   rw   |   0x1   | PERIPH_CLK_DIV_VALUE |               |
+
+## SAFETY_ISLAND_CLK_DIV_VALUE
+Safety Island clk divider value
+- Offset: `0xa0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SAFETY_ISLAND_CLK_DIV_VALUE |               |
+
+## SECURITY_ISLAND_CLK_DIV_VALUE
+Security Island clk divider value
+- Offset: `0xa4`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          | Description   |
+|:------:|:------:|:-------:|:------------------------------|:--------------|
+| 31:24  |        |         |                               | Reserved      |
+|  23:0  |   rw   |   0x1   | SECURITY_ISLAND_CLK_DIV_VALUE |               |
+
+## PULP_CLUSTER_CLK_DIV_VALUE
+PULP Cluster clk divider value
+- Offset: `0xa8`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+| 31:24  |        |         |                            | Reserved      |
+|  23:0  |   rw   |   0x1   | PULP_CLUSTER_CLK_DIV_VALUE |               |
+
+## SPATZ_CLUSTER_CLK_DIV_VALUE
+Spatz Cluster clk divider value
+- Offset: `0xac`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SPATZ_CLUSTER_CLK_DIV_VALUE |               |
+
+## L2_CLK_DIV_VALUE
+L2 Memory clk divider value
+- Offset: `0xb0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:24  |        |         |                  | Reserved      |
+|  23:0  |   rw   |   0x1   | L2_CLK_DIV_VALUE |               |
+
+## HOST_FETCH_ENABLE
+Host Domain fetch enable
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_FETCH_ENABLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | HOST_FETCH_ENABLE |               |
+
+## SAFETY_ISLAND_FETCH_ENABLE
+Safety Island fetch enable
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+|  31:1  |        |         |                            | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_FETCH_ENABLE |               |
+
+## SECURITY_ISLAND_FETCH_ENABLE
+Security Island fetch enable
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_FETCH_ENABLE |               |
+
+## PULP_CLUSTER_FETCH_ENABLE
+PULP Cluster fetch enable
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|  31:1  |        |         |                           | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_FETCH_ENABLE |               |
+
+## SPATZ_CLUSTER_DEBUG_REQ
+Spatz Cluster debug req
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_DEBUG_REQ", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x0   | SPATZ_CLUSTER_DEBUG_REQ |               |
+
+## HOST_BOOT_ADDR
+Host boot address
+- Offset: `0xc8`
+- Reset default: `0x1000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:0  |   rw   | 0x1000  | HOST_BOOT_ADDR |               |
+
+## SAFETY_ISLAND_BOOT_ADDR
+Safety Island boot address
+- Offset: `0xcc`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SAFETY_ISLAND_BOOT_ADDR |               |
+
+## SECURITY_ISLAND_BOOT_ADDR
+Security Island boot address
+- Offset: `0xd0`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                      | Description   |
+|:------:|:------:|:----------:|:--------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SECURITY_ISLAND_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ADDR
+PULP Cluster boot address
+- Offset: `0xd4`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                   | Description   |
+|:------:|:------:|:----------:|:-----------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | PULP_CLUSTER_BOOT_ADDR |               |
+
+## SPATZ_CLUSTER_BOOT_ADDR
+Spatz Cluster boot address
+- Offset: `0xd8`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SPATZ_CLUSTER_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ENABLE
+PULP Cluster boot enable
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_BOOT_ENABLE |               |
+
+## SPATZ_CLUSTER_BUSY
+Spatz Cluster busy
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:1  |        |         |                    | Reserved      |
+|   0    |   ro   |   0x0   | SPATZ_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_BUSY
+PULP Cluster busy
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_EOC
+PULP Cluster end of computation
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_EOC", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_EOC |               |
+
+## ETH_RGMII_PHY_CLK_DIV_EN
+Ethernet RGMII PHY clock divider enable bit
+- Offset: `0xec`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x1   | ETH_RGMII_PHY_CLK_DIV_EN |               |
+
+## ETH_RGMII_PHY_CLK_DIV_VALUE
+Ethernet RGMII PHY clock divider value
+- Offset: `0xf0`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:20  |        |         |                             | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_RGMII_PHY_CLK_DIV_VALUE |               |
+
+## ETH_MDIO_CLK_DIV_EN
+Ethernet MDIO clock divider enable bit
+- Offset: `0xf4`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x1   | ETH_MDIO_CLK_DIV_EN |               |
+
+## ETH_MDIO_CLK_DIV_VALUE
+Ethernet MDIO clock divider value
+- Offset: `0xf8`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:20  |        |         |                        | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_MDIO_CLK_DIV_VALUE |               |
+
diff --git a/docs/carfield_regs.md b/docs/carfield_regs.md
new file mode 100644
index 00000000..d4e1fa9e
--- /dev/null
+++ b/docs/carfield_regs.md
@@ -0,0 +1,1126 @@
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                            |
+|:-----------------------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| carfield.[`VERSION0`](#version0)                                             | 0x0      |        4 | Cheshire sha256 commit                                                 |
+| carfield.[`VERSION1`](#version1)                                             | 0x4      |        4 | Safety Island sha256 commit                                            |
+| carfield.[`VERSION2`](#version2)                                             | 0x8      |        4 | Security Island sha256 commit                                          |
+| carfield.[`VERSION3`](#version3)                                             | 0xc      |        4 | PULP Cluster sha256 commit                                             |
+| carfield.[`VERSION4`](#version4)                                             | 0x10     |        4 | Spatz CLuster sha256 commit                                            |
+| carfield.[`JEDEC_IDCODE`](#jedec_idcode)                                     | 0x14     |        4 | JEDEC ID CODE -TODO assign-                                            |
+| carfield.[`GENERIC_SCRATCH0`](#generic_scratch0)                             | 0x18     |        4 | Scratch                                                                |
+| carfield.[`GENERIC_SCRATCH1`](#generic_scratch1)                             | 0x1c     |        4 | Scratch                                                                |
+| carfield.[`HOST_RST`](#host_rst)                                             | 0x20     |        4 | Host Domain reset -active high, inverted in HW-                        |
+| carfield.[`PERIPH_RST`](#periph_rst)                                         | 0x24     |        4 | Periph Domain reset -active high, inverted in HW-                      |
+| carfield.[`SAFETY_ISLAND_RST`](#safety_island_rst)                           | 0x28     |        4 | Safety Island reset -active high, inverted in HW-                      |
+| carfield.[`SECURITY_ISLAND_RST`](#security_island_rst)                       | 0x2c     |        4 | Security Island reset -active high, inverted in HW-                    |
+| carfield.[`PULP_CLUSTER_RST`](#pulp_cluster_rst)                             | 0x30     |        4 | PULP Cluster reset -active high, inverted in HW-                       |
+| carfield.[`SPATZ_CLUSTER_RST`](#spatz_cluster_rst)                           | 0x34     |        4 | Spatz Cluster reset -active high, inverted in HW-                      |
+| carfield.[`L2_RST`](#l2_rst)                                                 | 0x38     |        4 | L2 reset -active high, inverted in HW-                                 |
+| carfield.[`PERIPH_ISOLATE`](#periph_isolate)                                 | 0x3c     |        4 | Periph Domain  AXI isolate                                             |
+| carfield.[`SAFETY_ISLAND_ISOLATE`](#safety_island_isolate)                   | 0x40     |        4 | Safety Island AXI isolate                                              |
+| carfield.[`SECURITY_ISLAND_ISOLATE`](#security_island_isolate)               | 0x44     |        4 | Security Island AXI isolate                                            |
+| carfield.[`PULP_CLUSTER_ISOLATE`](#pulp_cluster_isolate)                     | 0x48     |        4 | PULP Cluster AXI isolate                                               |
+| carfield.[`SPATZ_CLUSTER_ISOLATE`](#spatz_cluster_isolate)                   | 0x4c     |        4 | Spatz Cluster AXI isolate                                              |
+| carfield.[`L2_ISOLATE`](#l2_isolate)                                         | 0x50     |        4 | L2 AXI isolate                                                         |
+| carfield.[`PERIPH_ISOLATE_STATUS`](#periph_isolate_status)                   | 0x54     |        4 | Periph Domain AXI isolate status                                       |
+| carfield.[`SAFETY_ISLAND_ISOLATE_STATUS`](#safety_island_isolate_status)     | 0x58     |        4 | Safety Island AXI isolate status                                       |
+| carfield.[`SECURITY_ISLAND_ISOLATE_STATUS`](#security_island_isolate_status) | 0x5c     |        4 | Security Island AXI isolate status                                     |
+| carfield.[`PULP_CLUSTER_ISOLATE_STATUS`](#pulp_cluster_isolate_status)       | 0x60     |        4 | PULP Cluster AXI isolate status                                        |
+| carfield.[`SPATZ_CLUSTER_ISOLATE_STATUS`](#spatz_cluster_isolate_status)     | 0x64     |        4 | Spatz Cluster AXI isolate status                                       |
+| carfield.[`L2_ISOLATE_STATUS`](#l2_isolate_status)                           | 0x68     |        4 | L2 AXI isolate status                                                  |
+| carfield.[`PERIPH_CLK_EN`](#periph_clk_en)                                   | 0x6c     |        4 | Periph Domain clk gate enable                                          |
+| carfield.[`SAFETY_ISLAND_CLK_EN`](#safety_island_clk_en)                     | 0x70     |        4 | Safety Island clk gate enable                                          |
+| carfield.[`SECURITY_ISLAND_CLK_EN`](#security_island_clk_en)                 | 0x74     |        4 | Security Island clk gate enable                                        |
+| carfield.[`PULP_CLUSTER_CLK_EN`](#pulp_cluster_clk_en)                       | 0x78     |        4 | PULP Cluster clk gate enable                                           |
+| carfield.[`SPATZ_CLUSTER_CLK_EN`](#spatz_cluster_clk_en)                     | 0x7c     |        4 | Spatz Cluster clk gate enable                                          |
+| carfield.[`L2_CLK_EN`](#l2_clk_en)                                           | 0x80     |        4 | Shared L2 memory clk gate enable                                       |
+| carfield.[`PERIPH_CLK_SEL`](#periph_clk_sel)                                 | 0x84     |        4 | Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SAFETY_ISLAND_CLK_SEL`](#safety_island_clk_sel)                   | 0x88     |        4 | Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SECURITY_ISLAND_CLK_SEL`](#security_island_clk_sel)               | 0x8c     |        4 | Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) |
+| carfield.[`PULP_CLUSTER_CLK_SEL`](#pulp_cluster_clk_sel)                     | 0x90     |        4 | PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)    |
+| carfield.[`SPATZ_CLUSTER_CLK_SEL`](#spatz_cluster_clk_sel)                   | 0x94     |        4 | Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`L2_CLK_SEL`](#l2_clk_sel)                                         | 0x98     |        4 | L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)       |
+| carfield.[`PERIPH_CLK_DIV_VALUE`](#periph_clk_div_value)                     | 0x9c     |        4 | Periph Domain clk divider value                                        |
+| carfield.[`SAFETY_ISLAND_CLK_DIV_VALUE`](#safety_island_clk_div_value)       | 0xa0     |        4 | Safety Island clk divider value                                        |
+| carfield.[`SECURITY_ISLAND_CLK_DIV_VALUE`](#security_island_clk_div_value)   | 0xa4     |        4 | Security Island clk divider value                                      |
+| carfield.[`PULP_CLUSTER_CLK_DIV_VALUE`](#pulp_cluster_clk_div_value)         | 0xa8     |        4 | PULP Cluster clk divider value                                         |
+| carfield.[`SPATZ_CLUSTER_CLK_DIV_VALUE`](#spatz_cluster_clk_div_value)       | 0xac     |        4 | Spatz Cluster clk divider value                                        |
+| carfield.[`L2_CLK_DIV_VALUE`](#l2_clk_div_value)                             | 0xb0     |        4 | L2 Memory clk divider value                                            |
+| carfield.[`HOST_FETCH_ENABLE`](#host_fetch_enable)                           | 0xb4     |        4 | Host Domain fetch enable                                               |
+| carfield.[`SAFETY_ISLAND_FETCH_ENABLE`](#safety_island_fetch_enable)         | 0xb8     |        4 | Safety Island fetch enable                                             |
+| carfield.[`SECURITY_ISLAND_FETCH_ENABLE`](#security_island_fetch_enable)     | 0xbc     |        4 | Security Island fetch enable                                           |
+| carfield.[`PULP_CLUSTER_FETCH_ENABLE`](#pulp_cluster_fetch_enable)           | 0xc0     |        4 | PULP Cluster fetch enable                                              |
+| carfield.[`SPATZ_CLUSTER_DEBUG_REQ`](#spatz_cluster_debug_req)               | 0xc4     |        4 | Spatz Cluster debug req                                                |
+| carfield.[`HOST_BOOT_ADDR`](#host_boot_addr)                                 | 0xc8     |        4 | Host boot address                                                      |
+| carfield.[`SAFETY_ISLAND_BOOT_ADDR`](#safety_island_boot_addr)               | 0xcc     |        4 | Safety Island boot address                                             |
+| carfield.[`SECURITY_ISLAND_BOOT_ADDR`](#security_island_boot_addr)           | 0xd0     |        4 | Security Island boot address                                           |
+| carfield.[`PULP_CLUSTER_BOOT_ADDR`](#pulp_cluster_boot_addr)                 | 0xd4     |        4 | PULP Cluster boot address                                              |
+| carfield.[`SPATZ_CLUSTER_BOOT_ADDR`](#spatz_cluster_boot_addr)               | 0xd8     |        4 | Spatz Cluster boot address                                             |
+| carfield.[`PULP_CLUSTER_BOOT_ENABLE`](#pulp_cluster_boot_enable)             | 0xdc     |        4 | PULP Cluster boot enable                                               |
+| carfield.[`SPATZ_CLUSTER_BUSY`](#spatz_cluster_busy)                         | 0xe0     |        4 | Spatz Cluster busy                                                     |
+| carfield.[`PULP_CLUSTER_BUSY`](#pulp_cluster_busy)                           | 0xe4     |        4 | PULP Cluster busy                                                      |
+| carfield.[`PULP_CLUSTER_EOC`](#pulp_cluster_eoc)                             | 0xe8     |        4 | PULP Cluster end of computation                                        |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_EN`](#eth_rgmii_phy_clk_div_en)             | 0xec     |        4 | Ethernet RGMII PHY clock divider enable bit                            |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_VALUE`](#eth_rgmii_phy_clk_div_value)       | 0xf0     |        4 | Ethernet RGMII PHY clock divider value                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_EN`](#eth_mdio_clk_div_en)                       | 0xf4     |        4 | Ethernet MDIO clock divider enable bit                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_VALUE`](#eth_mdio_clk_div_value)                 | 0xf8     |        4 | Ethernet MDIO clock divider value                                      |
+
+## VERSION0
+Cheshire sha256 commit
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION0", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION0 |               |
+
+## VERSION1
+Safety Island sha256 commit
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION1", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION1 |               |
+
+## VERSION2
+Security Island sha256 commit
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION2", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION2 |               |
+
+## VERSION3
+PULP Cluster sha256 commit
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION3", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION3 |               |
+
+## VERSION4
+Spatz CLuster sha256 commit
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION4", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION4 |               |
+
+## JEDEC_IDCODE
+JEDEC ID CODE -TODO assign-
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "JEDEC_IDCODE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description   |
+|:------:|:------:|:-------:|:-------------|:--------------|
+|  31:0  |   rw   |   0x0   | JEDEC_IDCODE |               |
+
+## GENERIC_SCRATCH0
+Scratch
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH0 |               |
+
+## GENERIC_SCRATCH1
+Scratch
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH1 |               |
+
+## HOST_RST
+Host Domain reset -active high, inverted in HW-
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_RST", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:1  |        |         |          | Reserved      |
+|   0    |   ro   |   0x0   | HOST_RST |               |
+
+## PERIPH_RST
+Periph Domain reset -active high, inverted in HW-
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_RST |               |
+
+## SAFETY_ISLAND_RST
+Safety Island reset -active high, inverted in HW-
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_RST |               |
+
+## SECURITY_ISLAND_RST
+Security Island reset -active high, inverted in HW-
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_RST |               |
+
+## PULP_CLUSTER_RST
+PULP Cluster reset -active high, inverted in HW-
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_RST |               |
+
+## SPATZ_CLUSTER_RST
+Spatz Cluster reset -active high, inverted in HW-
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_RST |               |
+
+## L2_RST
+L2 reset -active high, inverted in HW-
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:1  |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | L2_RST |               |
+
+## PERIPH_ISOLATE
+Periph Domain  AXI isolate
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:1  |        |         |                | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE |               |
+
+## SAFETY_ISLAND_ISOLATE
+Safety Island AXI isolate
+- Offset: `0x40`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SAFETY_ISLAND_ISOLATE |               |
+
+## SECURITY_ISLAND_ISOLATE
+Security Island AXI isolate
+- Offset: `0x44`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   rw   |   0x1   | SECURITY_ISLAND_ISOLATE |               |
+
+## PULP_CLUSTER_ISOLATE
+PULP Cluster AXI isolate
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x1   | PULP_CLUSTER_ISOLATE |               |
+
+## SPATZ_CLUSTER_ISOLATE
+Spatz Cluster AXI isolate
+- Offset: `0x4c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SPATZ_CLUSTER_ISOLATE |               |
+
+## L2_ISOLATE
+L2 AXI isolate
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE |               |
+
+## PERIPH_ISOLATE_STATUS
+Periph Domain AXI isolate status
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE_STATUS |               |
+
+## SAFETY_ISLAND_ISOLATE_STATUS
+Safety Island AXI isolate status
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_ISOLATE_STATUS |               |
+
+## SECURITY_ISLAND_ISOLATE_STATUS
+Security Island AXI isolate status
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                           | Description   |
+|:------:|:------:|:-------:|:-------------------------------|:--------------|
+|  31:1  |        |         |                                | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_ISOLATE_STATUS |               |
+
+## PULP_CLUSTER_ISOLATE_STATUS
+PULP Cluster AXI isolate status
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+|  31:1  |        |         |                             | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_ISOLATE_STATUS |               |
+
+## SPATZ_CLUSTER_ISOLATE_STATUS
+Spatz Cluster AXI isolate status
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_ISOLATE_STATUS |               |
+
+## L2_ISOLATE_STATUS
+L2 AXI isolate status
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE_STATUS |               |
+
+## PERIPH_CLK_EN
+Periph Domain clk gate enable
+- Offset: `0x6c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x1   | PERIPH_CLK_EN |               |
+
+## SAFETY_ISLAND_CLK_EN
+Safety Island clk gate enable
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_CLK_EN |               |
+
+## SECURITY_ISLAND_CLK_EN
+Security Island clk gate enable
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+|  31:1  |        |         |                        | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_CLK_EN |               |
+
+## PULP_CLUSTER_CLK_EN
+PULP Cluster clk gate enable
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_CLK_EN |               |
+
+## SPATZ_CLUSTER_CLK_EN
+Spatz Cluster clk gate enable
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_CLK_EN |               |
+
+## L2_CLK_EN
+Shared L2 memory clk gate enable
+- Offset: `0x80`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:1  |        |         |           | Reserved      |
+|   0    |   rw   |   0x1   | L2_CLK_EN |               |
+
+## PERIPH_CLK_SEL
+Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x84`
+- Reset default: `0x2`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:2  |        |         |                | Reserved      |
+|  1:0   |   rw   |   0x2   | PERIPH_CLK_SEL |               |
+
+## SAFETY_ISLAND_CLK_SEL
+Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x88`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SAFETY_ISLAND_CLK_SEL |               |
+
+## SECURITY_ISLAND_CLK_SEL
+Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x8c`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x1   | SECURITY_ISLAND_CLK_SEL |               |
+
+## PULP_CLUSTER_CLK_SEL
+PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x90`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:2  |        |         |                      | Reserved      |
+|  1:0   |   rw   |   0x1   | PULP_CLUSTER_CLK_SEL |               |
+
+## SPATZ_CLUSTER_CLK_SEL
+Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x94`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SPATZ_CLUSTER_CLK_SEL |               |
+
+## L2_CLK_SEL
+L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x98`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:2  |        |         |            | Reserved      |
+|  1:0   |   rw   |   0x1   | L2_CLK_SEL |               |
+
+## PERIPH_CLK_DIV_VALUE
+Periph Domain clk divider value
+- Offset: `0x9c`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+| 31:24  |        |         |                      | Reserved      |
+|  23:0  |   rw   |   0x1   | PERIPH_CLK_DIV_VALUE |               |
+
+## SAFETY_ISLAND_CLK_DIV_VALUE
+Safety Island clk divider value
+- Offset: `0xa0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SAFETY_ISLAND_CLK_DIV_VALUE |               |
+
+## SECURITY_ISLAND_CLK_DIV_VALUE
+Security Island clk divider value
+- Offset: `0xa4`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          | Description   |
+|:------:|:------:|:-------:|:------------------------------|:--------------|
+| 31:24  |        |         |                               | Reserved      |
+|  23:0  |   rw   |   0x1   | SECURITY_ISLAND_CLK_DIV_VALUE |               |
+
+## PULP_CLUSTER_CLK_DIV_VALUE
+PULP Cluster clk divider value
+- Offset: `0xa8`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+| 31:24  |        |         |                            | Reserved      |
+|  23:0  |   rw   |   0x1   | PULP_CLUSTER_CLK_DIV_VALUE |               |
+
+## SPATZ_CLUSTER_CLK_DIV_VALUE
+Spatz Cluster clk divider value
+- Offset: `0xac`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SPATZ_CLUSTER_CLK_DIV_VALUE |               |
+
+## L2_CLK_DIV_VALUE
+L2 Memory clk divider value
+- Offset: `0xb0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:24  |        |         |                  | Reserved      |
+|  23:0  |   rw   |   0x1   | L2_CLK_DIV_VALUE |               |
+
+## HOST_FETCH_ENABLE
+Host Domain fetch enable
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_FETCH_ENABLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | HOST_FETCH_ENABLE |               |
+
+## SAFETY_ISLAND_FETCH_ENABLE
+Safety Island fetch enable
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+|  31:1  |        |         |                            | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_FETCH_ENABLE |               |
+
+## SECURITY_ISLAND_FETCH_ENABLE
+Security Island fetch enable
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_FETCH_ENABLE |               |
+
+## PULP_CLUSTER_FETCH_ENABLE
+PULP Cluster fetch enable
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|  31:1  |        |         |                           | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_FETCH_ENABLE |               |
+
+## SPATZ_CLUSTER_DEBUG_REQ
+Spatz Cluster debug req
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_DEBUG_REQ", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x0   | SPATZ_CLUSTER_DEBUG_REQ |               |
+
+## HOST_BOOT_ADDR
+Host boot address
+- Offset: `0xc8`
+- Reset default: `0x1000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:0  |   rw   | 0x1000  | HOST_BOOT_ADDR |               |
+
+## SAFETY_ISLAND_BOOT_ADDR
+Safety Island boot address
+- Offset: `0xcc`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SAFETY_ISLAND_BOOT_ADDR |               |
+
+## SECURITY_ISLAND_BOOT_ADDR
+Security Island boot address
+- Offset: `0xd0`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                      | Description   |
+|:------:|:------:|:----------:|:--------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SECURITY_ISLAND_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ADDR
+PULP Cluster boot address
+- Offset: `0xd4`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                   | Description   |
+|:------:|:------:|:----------:|:-----------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | PULP_CLUSTER_BOOT_ADDR |               |
+
+## SPATZ_CLUSTER_BOOT_ADDR
+Spatz Cluster boot address
+- Offset: `0xd8`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SPATZ_CLUSTER_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ENABLE
+PULP Cluster boot enable
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_BOOT_ENABLE |               |
+
+## SPATZ_CLUSTER_BUSY
+Spatz Cluster busy
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:1  |        |         |                    | Reserved      |
+|   0    |   ro   |   0x0   | SPATZ_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_BUSY
+PULP Cluster busy
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_EOC
+PULP Cluster end of computation
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_EOC", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_EOC |               |
+
+## ETH_RGMII_PHY_CLK_DIV_EN
+Ethernet RGMII PHY clock divider enable bit
+- Offset: `0xec`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x1   | ETH_RGMII_PHY_CLK_DIV_EN |               |
+
+## ETH_RGMII_PHY_CLK_DIV_VALUE
+Ethernet RGMII PHY clock divider value
+- Offset: `0xf0`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:20  |        |         |                             | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_RGMII_PHY_CLK_DIV_VALUE |               |
+
+## ETH_MDIO_CLK_DIV_EN
+Ethernet MDIO clock divider enable bit
+- Offset: `0xf4`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x1   | ETH_MDIO_CLK_DIV_EN |               |
+
+## ETH_MDIO_CLK_DIV_VALUE
+Ethernet MDIO clock divider value
+- Offset: `0xf8`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:20  |        |         |                        | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_MDIO_CLK_DIV_VALUE |               |
+
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+# Carfield IP Documentation
+
+- [axi_dma_config](#axi_dma_config)
+- [axi_llc](#axi_llc)
+- [axi_realm](#axi_realm)
+- [can_bus](#can_bus)
+- [carfield_regs](#carfield_regs)
+- [cheshire](#cheshire)
+- [clic](#clic)
+- [clint](#clint)
+- [ethernet](#ethernet)
+- [fp_cluster](#fp_cluster)
+- [gpio](#gpio)
+- [gp_timer1_system_timer](#gp_timer1_system_timer)
+- [gp_timer2_advanced_timer](#gp_timer2_advanced_timer)
+- [hyperbus](#hyperbus)
+- [i2c](#i2c)
+- [irq_router](#irq_router)
+- [l2_ecc_config](#l2_ecc_config)
+- [mailbox](#mailbox)
+- [plic](#plic)
+- [safety_island](#safety_island)
+- [serial_link](#serial_link)
+- [spim](#spim)
+- [tagger](#tagger)
+- [uart](#uart)
+- [unbent](#unbent)
+- [vga](#vga)
+- [watchdog_timer](#watchdog_timer)
+
+
+## axi_dma_config
+
+
+
+### idma_desc64_frontend_doc.md
+
+## Summary
+
+| Name                                  | Offset   |   Length | Description                                                         |
+|:--------------------------------------|:---------|---------:|:--------------------------------------------------------------------|
+| idma_desc64.[`desc_addr`](#desc_addr) | 0x0      |        8 | This register specifies the bus address at which the first transfer |
+| idma_desc64.[`status`](#status)       | 0x8      |        8 | This register contains status information for the DMA.              |
+
+## desc_addr
+This register specifies the bus address at which the first transfer
+descriptor can be found. A write to this register starts the transfer.
+- Offset: `0x0`
+- Reset default: `0xffffffffffffffff`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "desc_addr", "bits": 64, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |       Reset        | Name      | Description   |
+|:------:|:------:|:------------------:|:----------|:--------------|
+|  63:0  |   wo   | 0xffffffffffffffff | desc_addr |               |
+
+## status
+This register contains status information for the DMA.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "fifo_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 62}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  63:2  |        |         |           | Reserved                                                                                                                                                     |
+|   1    |   ro   |   0x0   | fifo_full | If this bit is set, the buffers of the DMA are full. Any further submissions via the desc_addr register may overwrite previously submitted jobs or get lost. |
+|   0    |   ro   |   0x0   | busy      | The DMA is busy                                                                                                                                              |
+
+
+
+
+
+### idma_reg32_2d_frontend_doc.md
+
+## Summary
+
+| Name                                                         | Offset   |   Length | Description                                                            |
+|:-------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg32_2d_frontend.[`src_addr`](#src_addr)               | 0x0      |        4 | Source Address                                                         |
+| idma_reg32_2d_frontend.[`dst_addr`](#dst_addr)               | 0x4      |        4 | Destination Address                                                    |
+| idma_reg32_2d_frontend.[`num_bytes`](#num_bytes)             | 0x8      |        4 | Number of bytes                                                        |
+| idma_reg32_2d_frontend.[`conf`](#conf)                       | 0xc      |        4 | Configuration Register for DMA settings                                |
+| idma_reg32_2d_frontend.[`stride_src`](#stride_src)           | 0x10     |        4 | Source Stride                                                          |
+| idma_reg32_2d_frontend.[`stride_dst`](#stride_dst)           | 0x14     |        4 | Destination Stride                                                     |
+| idma_reg32_2d_frontend.[`num_repetitions`](#num_repetitions) | 0x18     |        4 | Number of 2D repetitions                                               |
+| idma_reg32_2d_frontend.[`status`](#status)                   | 0x1c     |        4 | DMA Status                                                             |
+| idma_reg32_2d_frontend.[`next_id`](#next_id)                 | 0x20     |        4 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg32_2d_frontend.[`done`](#done)                       | 0x24     |        4 | Get ID of finished transactions.                                       |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  31:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  31:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  31:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "twod", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  31:4  |        |         |           | Reserved         |
+|   3    |   rw   |   0x0   | twod      | 2D transfer      |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## stride_src
+Source Stride
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_src", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   rw   |   0x0   | stride_src | Source Stride |
+
+## stride_dst
+Destination Stride
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_dst", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description        |
+|:------:|:------:|:-------:|:-----------|:-------------------|
+|  31:0  |   rw   |   0x0   | stride_dst | Destination Stride |
+
+## num_repetitions
+Number of 2D repetitions
+- Offset: `0x18`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_repetitions", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description              |
+|:------:|:------:|:-------:|:----------------|:-------------------------|
+|  31:0  |   rw   |   0x1   | num_repetitions | Number of 2D repetitions |
+
+## status
+DMA Status
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+| 31:16  |        |         |        | Reserved      |
+|  15:0  |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  31:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
+
+
+
+
+### idma_reg64_2d_frontend_doc.md
+
+## Summary
+
+| Name                                                         | Offset   |   Length | Description                                                            |
+|:-------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg64_2d_frontend.[`src_addr`](#src_addr)               | 0x0      |        8 | Source Address                                                         |
+| idma_reg64_2d_frontend.[`dst_addr`](#dst_addr)               | 0x8      |        8 | Destination Address                                                    |
+| idma_reg64_2d_frontend.[`num_bytes`](#num_bytes)             | 0x10     |        8 | Number of bytes                                                        |
+| idma_reg64_2d_frontend.[`conf`](#conf)                       | 0x18     |        8 | Configuration Register for DMA settings                                |
+| idma_reg64_2d_frontend.[`status`](#status)                   | 0x20     |        8 | DMA Status                                                             |
+| idma_reg64_2d_frontend.[`next_id`](#next_id)                 | 0x28     |        8 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg64_2d_frontend.[`done`](#done)                       | 0x30     |        8 | Get ID of finished transactions.                                       |
+| idma_reg64_2d_frontend.[`stride_src`](#stride_src)           | 0x38     |        8 | Source Stride                                                          |
+| idma_reg64_2d_frontend.[`stride_dst`](#stride_dst)           | 0x40     |        8 | Destination Stride                                                     |
+| idma_reg64_2d_frontend.[`num_repetitions`](#num_repetitions) | 0x48     |        8 | Number of 2D repetitions                                               |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  63:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  63:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  63:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 61}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  63:3  |        |         |           | Reserved         |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## status
+DMA Status
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  63:1  |        |         |        | Reserved      |
+|   0    |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  63:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  63:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
+## stride_src
+Source Stride
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_src", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  63:0  |   rw   |   0x0   | stride_src | Source Stride |
+
+## stride_dst
+Destination Stride
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_dst", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description        |
+|:------:|:------:|:-------:|:-----------|:-------------------|
+|  63:0  |   rw   |   0x0   | stride_dst | Destination Stride |
+
+## num_repetitions
+Number of 2D repetitions
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_repetitions", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description              |
+|:------:|:------:|:-------:|:----------------|:-------------------------|
+|  63:0  |   rw   |   0x0   | num_repetitions | Number of 2D repetitions |
+
+
+
+
+
+### idma_reg64_frontend_doc.md
+
+## Summary
+
+| Name                                          | Offset   |   Length | Description                                                            |
+|:----------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg64_frontend.[`src_addr`](#src_addr)   | 0x0      |        8 | Source Address                                                         |
+| idma_reg64_frontend.[`dst_addr`](#dst_addr)   | 0x8      |        8 | Destination Address                                                    |
+| idma_reg64_frontend.[`num_bytes`](#num_bytes) | 0x10     |        8 | Number of bytes                                                        |
+| idma_reg64_frontend.[`conf`](#conf)           | 0x18     |        8 | Configuration Register for DMA settings                                |
+| idma_reg64_frontend.[`status`](#status)       | 0x20     |        8 | DMA Status                                                             |
+| idma_reg64_frontend.[`next_id`](#next_id)     | 0x28     |        8 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg64_frontend.[`done`](#done)           | 0x30     |        8 | Get ID of finished transactions.                                       |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  63:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  63:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  63:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 61}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  63:3  |        |         |           | Reserved         |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## status
+DMA Status
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  63:1  |        |         |        | Reserved      |
+|   0    |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  63:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  63:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
+
+
+
+
+## axi_llc
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                          | Offset   |   Length | Description                                       |
+|:----------------------------------------------|:---------|---------:|:--------------------------------------------------|
+| axi_llc.[`CFG_SPM_LOW`](#cfg_spm_low)         | 0x0      |        4 | SPM Configuration (lower 32 bit)                  |
+| axi_llc.[`CFG_SPM_HIGH`](#cfg_spm_high)       | 0x4      |        4 | SPM Configuration (upper 32 bit)                  |
+| axi_llc.[`CFG_FLUSH_LOW`](#cfg_flush_low)     | 0x8      |        4 | Flush Configuration (lower 32 bit)                |
+| axi_llc.[`CFG_FLUSH_HIGH`](#cfg_flush_high)   | 0xc      |        4 | Flush Configuration (upper 32 bit)                |
+| axi_llc.[`COMMIT_CFG`](#commit_cfg)           | 0x10     |        4 | Commit the configuration                          |
+| axi_llc.[`FLUSHED_LOW`](#flushed_low)         | 0x18     |        4 | Flushed Flag (lower 32 bit)                       |
+| axi_llc.[`FLUSHED_HIGH`](#flushed_high)       | 0x1c     |        4 | Flushed Flag (upper 32 bit)                       |
+| axi_llc.[`BIST_OUT_LOW`](#bist_out_low)       | 0x20     |        4 | Tag Storage BIST Result (lower 32 bit)            |
+| axi_llc.[`BIST_OUT_HIGH`](#bist_out_high)     | 0x24     |        4 | Tag Storage BIST Result (upper 32 bit)            |
+| axi_llc.[`SET_ASSO_LOW`](#set_asso_low)       | 0x28     |        4 | Instantiated Set-Associativity (lower 32 bit)     |
+| axi_llc.[`SET_ASSO_HIGH`](#set_asso_high)     | 0x2c     |        4 | Instantiated Set-Associativity (upper 32 bit)     |
+| axi_llc.[`NUM_LINES_LOW`](#num_lines_low)     | 0x30     |        4 | Instantiated Number of Cache-Lines (lower 32 bit) |
+| axi_llc.[`NUM_LINES_HIGH`](#num_lines_high)   | 0x34     |        4 | Instantiated Number of Cache-Lines (upper 32 bit) |
+| axi_llc.[`NUM_BLOCKS_LOW`](#num_blocks_low)   | 0x38     |        4 | Instantiated Number of Blocks (lower 32 bit)      |
+| axi_llc.[`NUM_BLOCKS_HIGH`](#num_blocks_high) | 0x3c     |        4 | Instantiated Number of Blocks (upper 32 bit)      |
+| axi_llc.[`VERSION_LOW`](#version_low)         | 0x40     |        4 | AXI LLC Version (lower 32 bit)                    |
+| axi_llc.[`VERSION_HIGH`](#version_high)       | 0x44     |        4 | AXI LLC Version (upper 32 bit)                    |
+| axi_llc.[`BIST_STATUS`](#bist_status)         | 0x48     |        4 | Status register of the BIST                       |
+
+## CFG_SPM_LOW
+SPM Configuration (lower 32 bit)
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | low    | lower 32 bit  |
+
+## CFG_SPM_HIGH
+SPM Configuration (upper 32 bit)
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | high   | upper 32 bit  |
+
+## CFG_FLUSH_LOW
+Flush Configuration (lower 32 bit)
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | low    | lower 32 bit  |
+
+## CFG_FLUSH_HIGH
+Flush Configuration (upper 32 bit)
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | high   | upper 32 bit  |
+
+## COMMIT_CFG
+Commit the configuration
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "commit", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description          |
+|:------:|:------:|:-------:|:-------|:---------------------|
+|  31:1  |        |         |        | Reserved             |
+|   0    |  rw1s  |   0x0   | commit | commit configuration |
+
+## FLUSHED_LOW
+Flushed Flag (lower 32 bit)
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## FLUSHED_HIGH
+Flushed Flag (upper 32 bit)
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## BIST_OUT_LOW
+Tag Storage BIST Result (lower 32 bit)
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## BIST_OUT_HIGH
+Tag Storage BIST Result (upper 32 bit)
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## SET_ASSO_LOW
+Instantiated Set-Associativity (lower 32 bit)
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## SET_ASSO_HIGH
+Instantiated Set-Associativity (upper 32 bit)
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## NUM_LINES_LOW
+Instantiated Number of Cache-Lines (lower 32 bit)
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## NUM_LINES_HIGH
+Instantiated Number of Cache-Lines (upper 32 bit)
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## NUM_BLOCKS_LOW
+Instantiated Number of Blocks (lower 32 bit)
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## NUM_BLOCKS_HIGH
+Instantiated Number of Blocks (upper 32 bit)
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## VERSION_LOW
+AXI LLC Version (lower 32 bit)
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## VERSION_HIGH
+AXI LLC Version (upper 32 bit)
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## BIST_STATUS
+Status register of the BIST
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                 |
+|:------:|:------:|:-------:|:-------|:----------------------------|
+|  31:1  |        |         |        | Reserved                    |
+|   0    |   ro   |   0x0   | done   | BIST successfully completed |
+
+
+
+
+
+## axi_realm
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                    | Offset   |   Length | Description                                |
+|:--------------------------------------------------------|:---------|---------:|:-------------------------------------------|
+| axi_rt.[`major_version`](#major_version)                | 0x0      |        4 | Value of the major_version.                |
+| axi_rt.[`minor_version`](#minor_version)                | 0x4      |        4 | Value of the minor_version.                |
+| axi_rt.[`patch_version`](#patch_version)                | 0x8      |        4 | Value of the patch_version.                |
+| axi_rt.[`rt_enable`](#rt_enable)                        | 0xc      |        4 | Enable RT feature on master                |
+| axi_rt.[`rt_bypassed`](#rt_bypassed)                    | 0x10     |        4 | Is the RT inactive?                        |
+| axi_rt.[`len_limit_0`](#len_limit_0)                    | 0x14     |        4 | Fragmentation of the bursts in beats.      |
+| axi_rt.[`len_limit_1`](#len_limit_1)                    | 0x18     |        4 | Fragmentation of the bursts in beats.      |
+| axi_rt.[`imtu_enable`](#imtu_enable)                    | 0x1c     |        4 | Enables the IMTU.                          |
+| axi_rt.[`imtu_abort`](#imtu_abort)                      | 0x20     |        4 | Resets both the period and the budget.     |
+| axi_rt.[`start_addr_sub_low_0`](#start_addr_sub_low)    | 0x24     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_1`](#start_addr_sub_low)    | 0x28     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_2`](#start_addr_sub_low)    | 0x2c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_3`](#start_addr_sub_low)    | 0x30     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_4`](#start_addr_sub_low)    | 0x34     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_5`](#start_addr_sub_low)    | 0x38     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_6`](#start_addr_sub_low)    | 0x3c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_7`](#start_addr_sub_low)    | 0x40     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_8`](#start_addr_sub_low)    | 0x44     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_9`](#start_addr_sub_low)    | 0x48     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_10`](#start_addr_sub_low)   | 0x4c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_11`](#start_addr_sub_low)   | 0x50     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_12`](#start_addr_sub_low)   | 0x54     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_13`](#start_addr_sub_low)   | 0x58     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_14`](#start_addr_sub_low)   | 0x5c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_15`](#start_addr_sub_low)   | 0x60     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_high_0`](#start_addr_sub_high)  | 0x64     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_1`](#start_addr_sub_high)  | 0x68     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_2`](#start_addr_sub_high)  | 0x6c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_3`](#start_addr_sub_high)  | 0x70     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_4`](#start_addr_sub_high)  | 0x74     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_5`](#start_addr_sub_high)  | 0x78     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_6`](#start_addr_sub_high)  | 0x7c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_7`](#start_addr_sub_high)  | 0x80     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_8`](#start_addr_sub_high)  | 0x84     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_9`](#start_addr_sub_high)  | 0x88     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_10`](#start_addr_sub_high) | 0x8c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_11`](#start_addr_sub_high) | 0x90     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_12`](#start_addr_sub_high) | 0x94     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_13`](#start_addr_sub_high) | 0x98     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_14`](#start_addr_sub_high) | 0x9c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_15`](#start_addr_sub_high) | 0xa0     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`end_addr_sub_low_0`](#end_addr_sub_low)        | 0xa4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_1`](#end_addr_sub_low)        | 0xa8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_2`](#end_addr_sub_low)        | 0xac     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_3`](#end_addr_sub_low)        | 0xb0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_4`](#end_addr_sub_low)        | 0xb4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_5`](#end_addr_sub_low)        | 0xb8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_6`](#end_addr_sub_low)        | 0xbc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_7`](#end_addr_sub_low)        | 0xc0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_8`](#end_addr_sub_low)        | 0xc4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_9`](#end_addr_sub_low)        | 0xc8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_10`](#end_addr_sub_low)       | 0xcc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_11`](#end_addr_sub_low)       | 0xd0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_12`](#end_addr_sub_low)       | 0xd4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_13`](#end_addr_sub_low)       | 0xd8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_14`](#end_addr_sub_low)       | 0xdc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_15`](#end_addr_sub_low)       | 0xe0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_high_0`](#end_addr_sub_high)      | 0xe4     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_1`](#end_addr_sub_high)      | 0xe8     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_2`](#end_addr_sub_high)      | 0xec     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_3`](#end_addr_sub_high)      | 0xf0     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_4`](#end_addr_sub_high)      | 0xf4     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_5`](#end_addr_sub_high)      | 0xf8     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_6`](#end_addr_sub_high)      | 0xfc     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_7`](#end_addr_sub_high)      | 0x100    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_8`](#end_addr_sub_high)      | 0x104    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_9`](#end_addr_sub_high)      | 0x108    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_10`](#end_addr_sub_high)     | 0x10c    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_11`](#end_addr_sub_high)     | 0x110    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_12`](#end_addr_sub_high)     | 0x114    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_13`](#end_addr_sub_high)     | 0x118    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_14`](#end_addr_sub_high)     | 0x11c    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_15`](#end_addr_sub_high)     | 0x120    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`write_budget_0`](#write_budget)                | 0x124    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_1`](#write_budget)                | 0x128    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_2`](#write_budget)                | 0x12c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_3`](#write_budget)                | 0x130    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_4`](#write_budget)                | 0x134    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_5`](#write_budget)                | 0x138    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_6`](#write_budget)                | 0x13c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_7`](#write_budget)                | 0x140    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_8`](#write_budget)                | 0x144    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_9`](#write_budget)                | 0x148    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_10`](#write_budget)               | 0x14c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_11`](#write_budget)               | 0x150    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_12`](#write_budget)               | 0x154    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_13`](#write_budget)               | 0x158    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_14`](#write_budget)               | 0x15c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_15`](#write_budget)               | 0x160    |        4 | The budget for writes.                     |
+| axi_rt.[`read_budget_0`](#read_budget)                  | 0x164    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_1`](#read_budget)                  | 0x168    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_2`](#read_budget)                  | 0x16c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_3`](#read_budget)                  | 0x170    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_4`](#read_budget)                  | 0x174    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_5`](#read_budget)                  | 0x178    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_6`](#read_budget)                  | 0x17c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_7`](#read_budget)                  | 0x180    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_8`](#read_budget)                  | 0x184    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_9`](#read_budget)                  | 0x188    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_10`](#read_budget)                 | 0x18c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_11`](#read_budget)                 | 0x190    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_12`](#read_budget)                 | 0x194    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_13`](#read_budget)                 | 0x198    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_14`](#read_budget)                 | 0x19c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_15`](#read_budget)                 | 0x1a0    |        4 | The budget for reads.                      |
+| axi_rt.[`write_period_0`](#write_period)                | 0x1a4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_1`](#write_period)                | 0x1a8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_2`](#write_period)                | 0x1ac    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_3`](#write_period)                | 0x1b0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_4`](#write_period)                | 0x1b4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_5`](#write_period)                | 0x1b8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_6`](#write_period)                | 0x1bc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_7`](#write_period)                | 0x1c0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_8`](#write_period)                | 0x1c4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_9`](#write_period)                | 0x1c8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_10`](#write_period)               | 0x1cc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_11`](#write_period)               | 0x1d0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_12`](#write_period)               | 0x1d4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_13`](#write_period)               | 0x1d8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_14`](#write_period)               | 0x1dc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_15`](#write_period)               | 0x1e0    |        4 | The period for writes.                     |
+| axi_rt.[`read_period_0`](#read_period)                  | 0x1e4    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_1`](#read_period)                  | 0x1e8    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_2`](#read_period)                  | 0x1ec    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_3`](#read_period)                  | 0x1f0    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_4`](#read_period)                  | 0x1f4    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_5`](#read_period)                  | 0x1f8    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_6`](#read_period)                  | 0x1fc    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_7`](#read_period)                  | 0x200    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_8`](#read_period)                  | 0x204    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_9`](#read_period)                  | 0x208    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_10`](#read_period)                 | 0x20c    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_11`](#read_period)                 | 0x210    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_12`](#read_period)                 | 0x214    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_13`](#read_period)                 | 0x218    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_14`](#read_period)                 | 0x21c    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_15`](#read_period)                 | 0x220    |        4 | The period for reads.                      |
+| axi_rt.[`write_budget_left_0`](#write_budget_left)      | 0x224    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_1`](#write_budget_left)      | 0x228    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_2`](#write_budget_left)      | 0x22c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_3`](#write_budget_left)      | 0x230    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_4`](#write_budget_left)      | 0x234    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_5`](#write_budget_left)      | 0x238    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_6`](#write_budget_left)      | 0x23c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_7`](#write_budget_left)      | 0x240    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_8`](#write_budget_left)      | 0x244    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_9`](#write_budget_left)      | 0x248    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_10`](#write_budget_left)     | 0x24c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_11`](#write_budget_left)     | 0x250    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_12`](#write_budget_left)     | 0x254    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_13`](#write_budget_left)     | 0x258    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_14`](#write_budget_left)     | 0x25c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_15`](#write_budget_left)     | 0x260    |        4 | The budget left for writes.                |
+| axi_rt.[`read_budget_left_0`](#read_budget_left)        | 0x264    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_1`](#read_budget_left)        | 0x268    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_2`](#read_budget_left)        | 0x26c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_3`](#read_budget_left)        | 0x270    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_4`](#read_budget_left)        | 0x274    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_5`](#read_budget_left)        | 0x278    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_6`](#read_budget_left)        | 0x27c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_7`](#read_budget_left)        | 0x280    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_8`](#read_budget_left)        | 0x284    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_9`](#read_budget_left)        | 0x288    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_10`](#read_budget_left)       | 0x28c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_11`](#read_budget_left)       | 0x290    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_12`](#read_budget_left)       | 0x294    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_13`](#read_budget_left)       | 0x298    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_14`](#read_budget_left)       | 0x29c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_15`](#read_budget_left)       | 0x2a0    |        4 | The budget left for reads.                 |
+| axi_rt.[`write_period_left_0`](#write_period_left)      | 0x2a4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_1`](#write_period_left)      | 0x2a8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_2`](#write_period_left)      | 0x2ac    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_3`](#write_period_left)      | 0x2b0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_4`](#write_period_left)      | 0x2b4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_5`](#write_period_left)      | 0x2b8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_6`](#write_period_left)      | 0x2bc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_7`](#write_period_left)      | 0x2c0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_8`](#write_period_left)      | 0x2c4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_9`](#write_period_left)      | 0x2c8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_10`](#write_period_left)     | 0x2cc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_11`](#write_period_left)     | 0x2d0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_12`](#write_period_left)     | 0x2d4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_13`](#write_period_left)     | 0x2d8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_14`](#write_period_left)     | 0x2dc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_15`](#write_period_left)     | 0x2e0    |        4 | The period left for writes.                |
+| axi_rt.[`read_period_left_0`](#read_period_left)        | 0x2e4    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_1`](#read_period_left)        | 0x2e8    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_2`](#read_period_left)        | 0x2ec    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_3`](#read_period_left)        | 0x2f0    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_4`](#read_period_left)        | 0x2f4    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_5`](#read_period_left)        | 0x2f8    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_6`](#read_period_left)        | 0x2fc    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_7`](#read_period_left)        | 0x300    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_8`](#read_period_left)        | 0x304    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_9`](#read_period_left)        | 0x308    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_10`](#read_period_left)       | 0x30c    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_11`](#read_period_left)       | 0x310    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_12`](#read_period_left)       | 0x314    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_13`](#read_period_left)       | 0x318    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_14`](#read_period_left)       | 0x31c    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_15`](#read_period_left)       | 0x320    |        4 | The period left for reads.                 |
+| axi_rt.[`isolate`](#isolate)                            | 0x324    |        4 | Is the interface requested to be isolated? |
+| axi_rt.[`isolated`](#isolated)                          | 0x328    |        4 | Is the interface isolated?                 |
+| axi_rt.[`num_managers`](#num_managers)                  | 0x32c    |        4 | Value of the num_managers parameter.       |
+| axi_rt.[`addr_width`](#addr_width)                      | 0x330    |        4 | Value of the addr_width parameter.         |
+| axi_rt.[`data_width`](#data_width)                      | 0x334    |        4 | Value of the data_width parameter.         |
+| axi_rt.[`id_width`](#id_width)                          | 0x338    |        4 | Value of the id_width parameter.           |
+| axi_rt.[`user_width`](#user_width)                      | 0x33c    |        4 | Value of the user_width parameter.         |
+| axi_rt.[`num_pending`](#num_pending)                    | 0x340    |        4 | Value of the num_pending parameter.        |
+| axi_rt.[`w_buffer_depth`](#w_buffer_depth)              | 0x344    |        4 | Value of the w_buffer_depth parameter.     |
+| axi_rt.[`num_addr_regions`](#num_addr_regions)          | 0x348    |        4 | Value of the num_addr_regions parameter.   |
+| axi_rt.[`period_width`](#period_width)                  | 0x34c    |        4 | Value of the period_width parameter.       |
+| axi_rt.[`budget_width`](#budget_width)                  | 0x350    |        4 | Value of the budget_width parameter.       |
+| axi_rt.[`max_num_managers`](#max_num_managers)          | 0x354    |        4 | Value of the max_num_managers parameter.   |
+
+## major_version
+Value of the major_version.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "major_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | major_version | Value of the major_version. |
+
+## minor_version
+Value of the minor_version.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "minor_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | minor_version | Value of the minor_version. |
+
+## patch_version
+Value of the patch_version.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "patch_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | patch_version | Value of the patch_version. |
+
+## rt_enable
+Enable RT feature on master
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                 |
+|:------:|:------:|:-------:|:---------|:----------------------------|
+|  31:8  |        |         |          | Reserved                    |
+|   7    |   wo   |   0x0   | enable_7 | Enable RT feature on master |
+|   6    |   wo   |   0x0   | enable_6 | Enable RT feature on master |
+|   5    |   wo   |   0x0   | enable_5 | Enable RT feature on master |
+|   4    |   wo   |   0x0   | enable_4 | Enable RT feature on master |
+|   3    |   wo   |   0x0   | enable_3 | Enable RT feature on master |
+|   2    |   wo   |   0x0   | enable_2 | Enable RT feature on master |
+|   1    |   wo   |   0x0   | enable_1 | Enable RT feature on master |
+|   0    |   wo   |   0x0   | enable_0 | Enable RT feature on master |
+
+## rt_bypassed
+Is the RT inactive?
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypassed_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description         |
+|:------:|:------:|:-------:|:-----------|:--------------------|
+|  31:8  |        |         |            | Reserved            |
+|   7    |   ro   |    x    | bypassed_7 | Is the RT inactive? |
+|   6    |   ro   |    x    | bypassed_6 | Is the RT inactive? |
+|   5    |   ro   |    x    | bypassed_5 | Is the RT inactive? |
+|   4    |   ro   |    x    | bypassed_4 | Is the RT inactive? |
+|   3    |   ro   |    x    | bypassed_3 | Is the RT inactive? |
+|   2    |   ro   |    x    | bypassed_2 | Is the RT inactive? |
+|   1    |   ro   |    x    | bypassed_1 | Is the RT inactive? |
+|   0    |   ro   |    x    | bypassed_0 | Is the RT inactive? |
+
+## len_limit_0
+Fragmentation of the bursts in beats.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "len_0", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_1", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_2", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_3", "bits": 8, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------|
+| 31:24  |   wo   |   0x0   | len_3  | Fragmentation of the bursts in beats. |
+| 23:16  |   wo   |   0x0   | len_2  | Fragmentation of the bursts in beats. |
+|  15:8  |   wo   |   0x0   | len_1  | Fragmentation of the bursts in beats. |
+|  7:0   |   wo   |   0x0   | len_0  | Fragmentation of the bursts in beats. |
+
+## len_limit_1
+Fragmentation of the bursts in beats.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "len_4", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_5", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_6", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_7", "bits": 8, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description    |
+|:------:|:------:|:-------:|:-------|:---------------|
+| 31:24  |   wo   |   0x0   | len_7  | For len_limit1 |
+| 23:16  |   wo   |   0x0   | len_6  | For len_limit1 |
+|  15:8  |   wo   |   0x0   | len_5  | For len_limit1 |
+|  7:0   |   wo   |   0x0   | len_4  | For len_limit1 |
+
+## imtu_enable
+Enables the IMTU.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description       |
+|:------:|:------:|:-------:|:---------|:------------------|
+|  31:8  |        |         |          | Reserved          |
+|   7    |   wo   |   0x0   | enable_7 | Enables the IMTU. |
+|   6    |   wo   |   0x0   | enable_6 | Enables the IMTU. |
+|   5    |   wo   |   0x0   | enable_5 | Enables the IMTU. |
+|   4    |   wo   |   0x0   | enable_4 | Enables the IMTU. |
+|   3    |   wo   |   0x0   | enable_3 | Enables the IMTU. |
+|   2    |   wo   |   0x0   | enable_2 | Enables the IMTU. |
+|   1    |   wo   |   0x0   | enable_1 | Enables the IMTU. |
+|   0    |   wo   |   0x0   | enable_0 | Enables the IMTU. |
+
+## imtu_abort
+Resets both the period and the budget.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "abort_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                            |
+|:------:|:------:|:-------:|:--------|:---------------------------------------|
+|  31:8  |        |         |         | Reserved                               |
+|   7    |   wo   |   0x0   | abort_7 | Resets both the period and the budget. |
+|   6    |   wo   |   0x0   | abort_6 | Resets both the period and the budget. |
+|   5    |   wo   |   0x0   | abort_5 | Resets both the period and the budget. |
+|   4    |   wo   |   0x0   | abort_4 | Resets both the period and the budget. |
+|   3    |   wo   |   0x0   | abort_3 | Resets both the period and the budget. |
+|   2    |   wo   |   0x0   | abort_2 | Resets both the period and the budget. |
+|   1    |   wo   |   0x0   | abort_1 | Resets both the period and the budget. |
+|   0    |   wo   |   0x0   | abort_0 | Resets both the period and the budget. |
+
+## start_addr_sub_low
+The lower 32bit of the start address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                  | Offset   |
+|:----------------------|:---------|
+| start_addr_sub_low_0  | 0x24     |
+| start_addr_sub_low_1  | 0x28     |
+| start_addr_sub_low_2  | 0x2c     |
+| start_addr_sub_low_3  | 0x30     |
+| start_addr_sub_low_4  | 0x34     |
+| start_addr_sub_low_5  | 0x38     |
+| start_addr_sub_low_6  | 0x3c     |
+| start_addr_sub_low_7  | 0x40     |
+| start_addr_sub_low_8  | 0x44     |
+| start_addr_sub_low_9  | 0x48     |
+| start_addr_sub_low_10 | 0x4c     |
+| start_addr_sub_low_11 | 0x50     |
+| start_addr_sub_low_12 | 0x54     |
+| start_addr_sub_low_13 | 0x58     |
+| start_addr_sub_low_14 | 0x5c     |
+| start_addr_sub_low_15 | 0x60     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                           |
+|:------:|:------:|:-------:|:-------------|:--------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The lower 32bit of the start address. |
+
+## start_addr_sub_high
+The higher 32bit of the start address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                   | Offset   |
+|:-----------------------|:---------|
+| start_addr_sub_high_0  | 0x64     |
+| start_addr_sub_high_1  | 0x68     |
+| start_addr_sub_high_2  | 0x6c     |
+| start_addr_sub_high_3  | 0x70     |
+| start_addr_sub_high_4  | 0x74     |
+| start_addr_sub_high_5  | 0x78     |
+| start_addr_sub_high_6  | 0x7c     |
+| start_addr_sub_high_7  | 0x80     |
+| start_addr_sub_high_8  | 0x84     |
+| start_addr_sub_high_9  | 0x88     |
+| start_addr_sub_high_10 | 0x8c     |
+| start_addr_sub_high_11 | 0x90     |
+| start_addr_sub_high_12 | 0x94     |
+| start_addr_sub_high_13 | 0x98     |
+| start_addr_sub_high_14 | 0x9c     |
+| start_addr_sub_high_15 | 0xa0     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                            |
+|:------:|:------:|:-------:|:-------------|:---------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The higher 32bit of the start address. |
+
+## end_addr_sub_low
+The lower 32bit of the end address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| end_addr_sub_low_0  | 0xa4     |
+| end_addr_sub_low_1  | 0xa8     |
+| end_addr_sub_low_2  | 0xac     |
+| end_addr_sub_low_3  | 0xb0     |
+| end_addr_sub_low_4  | 0xb4     |
+| end_addr_sub_low_5  | 0xb8     |
+| end_addr_sub_low_6  | 0xbc     |
+| end_addr_sub_low_7  | 0xc0     |
+| end_addr_sub_low_8  | 0xc4     |
+| end_addr_sub_low_9  | 0xc8     |
+| end_addr_sub_low_10 | 0xcc     |
+| end_addr_sub_low_11 | 0xd0     |
+| end_addr_sub_low_12 | 0xd4     |
+| end_addr_sub_low_13 | 0xd8     |
+| end_addr_sub_low_14 | 0xdc     |
+| end_addr_sub_low_15 | 0xe0     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                         |
+|:------:|:------:|:-------:|:-------------|:------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The lower 32bit of the end address. |
+
+## end_addr_sub_high
+The higher 32bit of the end address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| end_addr_sub_high_0  | 0xe4     |
+| end_addr_sub_high_1  | 0xe8     |
+| end_addr_sub_high_2  | 0xec     |
+| end_addr_sub_high_3  | 0xf0     |
+| end_addr_sub_high_4  | 0xf4     |
+| end_addr_sub_high_5  | 0xf8     |
+| end_addr_sub_high_6  | 0xfc     |
+| end_addr_sub_high_7  | 0x100    |
+| end_addr_sub_high_8  | 0x104    |
+| end_addr_sub_high_9  | 0x108    |
+| end_addr_sub_high_10 | 0x10c    |
+| end_addr_sub_high_11 | 0x110    |
+| end_addr_sub_high_12 | 0x114    |
+| end_addr_sub_high_13 | 0x118    |
+| end_addr_sub_high_14 | 0x11c    |
+| end_addr_sub_high_15 | 0x120    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The higher 32bit of the end address. |
+
+## write_budget
+The budget for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name            | Offset   |
+|:----------------|:---------|
+| write_budget_0  | 0x124    |
+| write_budget_1  | 0x128    |
+| write_budget_2  | 0x12c    |
+| write_budget_3  | 0x130    |
+| write_budget_4  | 0x134    |
+| write_budget_5  | 0x138    |
+| write_budget_6  | 0x13c    |
+| write_budget_7  | 0x140    |
+| write_budget_8  | 0x144    |
+| write_budget_9  | 0x148    |
+| write_budget_10 | 0x14c    |
+| write_budget_11 | 0x150    |
+| write_budget_12 | 0x154    |
+| write_budget_13 | 0x158    |
+| write_budget_14 | 0x15c    |
+| write_budget_15 | 0x160    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description            |
+|:------:|:------:|:-------:|:-------------|:-----------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The budget for writes. |
+
+## read_budget
+The budget for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| read_budget_0  | 0x164    |
+| read_budget_1  | 0x168    |
+| read_budget_2  | 0x16c    |
+| read_budget_3  | 0x170    |
+| read_budget_4  | 0x174    |
+| read_budget_5  | 0x178    |
+| read_budget_6  | 0x17c    |
+| read_budget_7  | 0x180    |
+| read_budget_8  | 0x184    |
+| read_budget_9  | 0x188    |
+| read_budget_10 | 0x18c    |
+| read_budget_11 | 0x190    |
+| read_budget_12 | 0x194    |
+| read_budget_13 | 0x198    |
+| read_budget_14 | 0x19c    |
+| read_budget_15 | 0x1a0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description           |
+|:------:|:------:|:-------:|:------------|:----------------------|
+|  31:0  |   wo   |   0x0   | read_budget | The budget for reads. |
+
+## write_period
+The period for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name            | Offset   |
+|:----------------|:---------|
+| write_period_0  | 0x1a4    |
+| write_period_1  | 0x1a8    |
+| write_period_2  | 0x1ac    |
+| write_period_3  | 0x1b0    |
+| write_period_4  | 0x1b4    |
+| write_period_5  | 0x1b8    |
+| write_period_6  | 0x1bc    |
+| write_period_7  | 0x1c0    |
+| write_period_8  | 0x1c4    |
+| write_period_9  | 0x1c8    |
+| write_period_10 | 0x1cc    |
+| write_period_11 | 0x1d0    |
+| write_period_12 | 0x1d4    |
+| write_period_13 | 0x1d8    |
+| write_period_14 | 0x1dc    |
+| write_period_15 | 0x1e0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_period", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description            |
+|:------:|:------:|:-------:|:-------------|:-----------------------|
+|  31:0  |   wo   |   0x0   | write_period | The period for writes. |
+
+## read_period
+The period for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| read_period_0  | 0x1e4    |
+| read_period_1  | 0x1e8    |
+| read_period_2  | 0x1ec    |
+| read_period_3  | 0x1f0    |
+| read_period_4  | 0x1f4    |
+| read_period_5  | 0x1f8    |
+| read_period_6  | 0x1fc    |
+| read_period_7  | 0x200    |
+| read_period_8  | 0x204    |
+| read_period_9  | 0x208    |
+| read_period_10 | 0x20c    |
+| read_period_11 | 0x210    |
+| read_period_12 | 0x214    |
+| read_period_13 | 0x218    |
+| read_period_14 | 0x21c    |
+| read_period_15 | 0x220    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_period", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description           |
+|:------:|:------:|:-------:|:------------|:----------------------|
+|  31:0  |   wo   |   0x0   | read_period | The period for reads. |
+
+## write_budget_left
+The budget left for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| write_budget_left_0  | 0x224    |
+| write_budget_left_1  | 0x228    |
+| write_budget_left_2  | 0x22c    |
+| write_budget_left_3  | 0x230    |
+| write_budget_left_4  | 0x234    |
+| write_budget_left_5  | 0x238    |
+| write_budget_left_6  | 0x23c    |
+| write_budget_left_7  | 0x240    |
+| write_budget_left_8  | 0x244    |
+| write_budget_left_9  | 0x248    |
+| write_budget_left_10 | 0x24c    |
+| write_budget_left_11 | 0x250    |
+| write_budget_left_12 | 0x254    |
+| write_budget_left_13 | 0x258    |
+| write_budget_left_14 | 0x25c    |
+| write_budget_left_15 | 0x260    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                 |
+|:------:|:------:|:-------:|:------------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | write_budget_left | The budget left for writes. |
+
+## read_budget_left
+The budget left for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| read_budget_left_0  | 0x264    |
+| read_budget_left_1  | 0x268    |
+| read_budget_left_2  | 0x26c    |
+| read_budget_left_3  | 0x270    |
+| read_budget_left_4  | 0x274    |
+| read_budget_left_5  | 0x278    |
+| read_budget_left_6  | 0x27c    |
+| read_budget_left_7  | 0x280    |
+| read_budget_left_8  | 0x284    |
+| read_budget_left_9  | 0x288    |
+| read_budget_left_10 | 0x28c    |
+| read_budget_left_11 | 0x290    |
+| read_budget_left_12 | 0x294    |
+| read_budget_left_13 | 0x298    |
+| read_budget_left_14 | 0x29c    |
+| read_budget_left_15 | 0x2a0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_budget_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------|
+|  31:0  |   ro   |   0x0   | read_budget_left | The budget left for reads. |
+
+## write_period_left
+The period left for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| write_period_left_0  | 0x2a4    |
+| write_period_left_1  | 0x2a8    |
+| write_period_left_2  | 0x2ac    |
+| write_period_left_3  | 0x2b0    |
+| write_period_left_4  | 0x2b4    |
+| write_period_left_5  | 0x2b8    |
+| write_period_left_6  | 0x2bc    |
+| write_period_left_7  | 0x2c0    |
+| write_period_left_8  | 0x2c4    |
+| write_period_left_9  | 0x2c8    |
+| write_period_left_10 | 0x2cc    |
+| write_period_left_11 | 0x2d0    |
+| write_period_left_12 | 0x2d4    |
+| write_period_left_13 | 0x2d8    |
+| write_period_left_14 | 0x2dc    |
+| write_period_left_15 | 0x2e0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_period_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                 |
+|:------:|:------:|:-------:|:------------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | write_period_left | The period left for writes. |
+
+## read_period_left
+The period left for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| read_period_left_0  | 0x2e4    |
+| read_period_left_1  | 0x2e8    |
+| read_period_left_2  | 0x2ec    |
+| read_period_left_3  | 0x2f0    |
+| read_period_left_4  | 0x2f4    |
+| read_period_left_5  | 0x2f8    |
+| read_period_left_6  | 0x2fc    |
+| read_period_left_7  | 0x300    |
+| read_period_left_8  | 0x304    |
+| read_period_left_9  | 0x308    |
+| read_period_left_10 | 0x30c    |
+| read_period_left_11 | 0x310    |
+| read_period_left_12 | 0x314    |
+| read_period_left_13 | 0x318    |
+| read_period_left_14 | 0x31c    |
+| read_period_left_15 | 0x320    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_period_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------|
+|  31:0  |   ro   |   0x0   | read_period_left | The period left for reads. |
+
+## isolate
+Is the interface requested to be isolated?
+- Offset: `0x324`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "isolate_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------|
+|  31:8  |        |         |           | Reserved                                   |
+|   7    |   ro   |    x    | isolate_7 | Is the interface requested to be isolated? |
+|   6    |   ro   |    x    | isolate_6 | Is the interface requested to be isolated? |
+|   5    |   ro   |    x    | isolate_5 | Is the interface requested to be isolated? |
+|   4    |   ro   |    x    | isolate_4 | Is the interface requested to be isolated? |
+|   3    |   ro   |    x    | isolate_3 | Is the interface requested to be isolated? |
+|   2    |   ro   |    x    | isolate_2 | Is the interface requested to be isolated? |
+|   1    |   ro   |    x    | isolate_1 | Is the interface requested to be isolated? |
+|   0    |   ro   |    x    | isolate_0 | Is the interface requested to be isolated? |
+
+## isolated
+Is the interface isolated?
+- Offset: `0x328`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "isolated_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                |
+|:------:|:------:|:-------:|:-----------|:---------------------------|
+|  31:8  |        |         |            | Reserved                   |
+|   7    |   ro   |    x    | isolated_7 | Is the interface isolated? |
+|   6    |   ro   |    x    | isolated_6 | Is the interface isolated? |
+|   5    |   ro   |    x    | isolated_5 | Is the interface isolated? |
+|   4    |   ro   |    x    | isolated_4 | Is the interface isolated? |
+|   3    |   ro   |    x    | isolated_3 | Is the interface isolated? |
+|   2    |   ro   |    x    | isolated_2 | Is the interface isolated? |
+|   1    |   ro   |    x    | isolated_1 | Is the interface isolated? |
+|   0    |   ro   |    x    | isolated_0 | Is the interface isolated? |
+
+## num_managers
+Value of the num_managers parameter.
+- Offset: `0x32c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_managers", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | num_managers | Value of the num_managers parameter. |
+
+## addr_width
+Value of the addr_width parameter.
+- Offset: `0x330`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "addr_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | addr_width | Value of the addr_width parameter. |
+
+## data_width
+Value of the data_width parameter.
+- Offset: `0x334`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | data_width | Value of the data_width parameter. |
+
+## id_width
+Value of the id_width parameter.
+- Offset: `0x338`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "id_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                      |
+|:------:|:------:|:-------:|:---------|:---------------------------------|
+|  31:0  |   ro   |    x    | id_width | Value of the id_width parameter. |
+
+## user_width
+Value of the user_width parameter.
+- Offset: `0x33c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "user_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | user_width | Value of the user_width parameter. |
+
+## num_pending
+Value of the num_pending parameter.
+- Offset: `0x340`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_pending", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                         |
+|:------:|:------:|:-------:|:------------|:------------------------------------|
+|  31:0  |   ro   |    x    | num_pending | Value of the num_pending parameter. |
+
+## w_buffer_depth
+Value of the w_buffer_depth parameter.
+- Offset: `0x344`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "w_buffer_depth", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                            |
+|:------:|:------:|:-------:|:---------------|:---------------------------------------|
+|  31:0  |   ro   |    x    | w_buffer_depth | Value of the w_buffer_depth parameter. |
+
+## num_addr_regions
+Value of the num_addr_regions parameter.
+- Offset: `0x348`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_addr_regions", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                              |
+|:------:|:------:|:-------:|:-----------------|:-----------------------------------------|
+|  31:0  |   ro   |    x    | num_addr_regions | Value of the num_addr_regions parameter. |
+
+## period_width
+Value of the period_width parameter.
+- Offset: `0x34c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "period_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | period_width | Value of the period_width parameter. |
+
+## budget_width
+Value of the budget_width parameter.
+- Offset: `0x350`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "budget_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | budget_width | Value of the budget_width parameter. |
+
+## max_num_managers
+Value of the max_num_managers parameter.
+- Offset: `0x354`
+- Reset default: `0x8`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "max_num_managers", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                              |
+|:------:|:------:|:-------:|:-----------------|:-----------------------------------------|
+|  31:0  |   ro   |   0x8   | max_num_managers | Value of the max_num_managers parameter. |
+
+
+
+
+
+## can_bus
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                                                                          | Offset   |   Length | Description                                                                    |
+|:--------------------------------------------------------------------------------------------------------------|:---------|---------:|:-------------------------------------------------------------------------------|
+| can_bus.[`ahb_ifc_hsel_valid`](#ahb_ifc_hsel_valid)                                                           | 0x0      |        4 | Auto-extracted signal hsel_valid from ahb_ifc.vhd                              |
+| can_bus.[`ahb_ifc_write_acc_d`](#ahb_ifc_write_acc_d)                                                         | 0x4      |        4 | Auto-extracted signal write_acc_d from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_write_acc_q`](#ahb_ifc_write_acc_q)                                                         | 0x8      |        4 | Auto-extracted signal write_acc_q from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_haddr_q`](#ahb_ifc_haddr_q)                                                                 | 0xc      |        4 | Auto-extracted signal haddr_q from ahb_ifc.vhd                                 |
+| can_bus.[`ahb_ifc_h_ready_raw`](#ahb_ifc_h_ready_raw)                                                         | 0x10     |        4 | Auto-extracted signal h_ready_raw from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_sbe_d`](#ahb_ifc_sbe_d)                                                                     | 0x14     |        4 | Auto-extracted signal sbe_d from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_sbe_q`](#ahb_ifc_sbe_q)                                                                     | 0x18     |        4 | Auto-extracted signal sbe_q from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_swr_i`](#ahb_ifc_swr_i)                                                                     | 0x1c     |        4 | Auto-extracted signal swr_i from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_srd_i`](#ahb_ifc_srd_i)                                                                     | 0x20     |        4 | Auto-extracted signal srd_i from ahb_ifc.vhd                                   |
+| can_bus.[`bit_destuffing_discard_stuff_bit`](#bit_destuffing_discard_stuff_bit)                               | 0x24     |        4 | Auto-extracted signal discard_stuff_bit from bit_destuffing.vhd                |
+| can_bus.[`bit_destuffing_non_fix_to_fix_chng`](#bit_destuffing_non_fix_to_fix_chng)                           | 0x28     |        4 | Auto-extracted signal non_fix_to_fix_chng from bit_destuffing.vhd              |
+| can_bus.[`bit_destuffing_stuff_lvl_reached`](#bit_destuffing_stuff_lvl_reached)                               | 0x2c     |        4 | Auto-extracted signal stuff_lvl_reached from bit_destuffing.vhd                |
+| can_bus.[`bit_destuffing_stuff_rule_violate`](#bit_destuffing_stuff_rule_violate)                             | 0x30     |        4 | Auto-extracted signal stuff_rule_violate from bit_destuffing.vhd               |
+| can_bus.[`bit_destuffing_enable_prev`](#bit_destuffing_enable_prev)                                           | 0x34     |        4 | Auto-extracted signal enable_prev from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_fixed_prev_q`](#bit_destuffing_fixed_prev_q)                                         | 0x38     |        4 | Auto-extracted signal fixed_prev_q from bit_destuffing.vhd                     |
+| can_bus.[`bit_destuffing_fixed_prev_d`](#bit_destuffing_fixed_prev_d)                                         | 0x3c     |        4 | Auto-extracted signal fixed_prev_d from bit_destuffing.vhd                     |
+| can_bus.[`bit_destuffing_same_bits_erase`](#bit_destuffing_same_bits_erase)                                   | 0x40     |        4 | Auto-extracted signal same_bits_erase from bit_destuffing.vhd                  |
+| can_bus.[`bit_destuffing_destuffed_q`](#bit_destuffing_destuffed_q)                                           | 0x44     |        4 | Auto-extracted signal destuffed_q from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_destuffed_d`](#bit_destuffing_destuffed_d)                                           | 0x48     |        4 | Auto-extracted signal destuffed_d from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_stuff_err_q`](#bit_destuffing_stuff_err_q)                                           | 0x4c     |        4 | Auto-extracted signal stuff_err_q from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_stuff_err_d`](#bit_destuffing_stuff_err_d)                                           | 0x50     |        4 | Auto-extracted signal stuff_err_d from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_prev_val_q`](#bit_destuffing_prev_val_q)                                             | 0x54     |        4 | Auto-extracted signal prev_val_q from bit_destuffing.vhd                       |
+| can_bus.[`bit_destuffing_prev_val_d`](#bit_destuffing_prev_val_d)                                             | 0x58     |        4 | Auto-extracted signal prev_val_d from bit_destuffing.vhd                       |
+| can_bus.[`bit_err_detector_bit_err_d`](#bit_err_detector_bit_err_d)                                           | 0x5c     |        4 | Auto-extracted signal bit_err_d from bit_err_detector.vhd                      |
+| can_bus.[`bit_err_detector_bit_err_q`](#bit_err_detector_bit_err_q)                                           | 0x60     |        4 | Auto-extracted signal bit_err_q from bit_err_detector.vhd                      |
+| can_bus.[`bit_err_detector_bit_err_ssp_capt_d`](#bit_err_detector_bit_err_ssp_capt_d)                         | 0x64     |        4 | Auto-extracted signal bit_err_ssp_capt_d from bit_err_detector.vhd             |
+| can_bus.[`bit_err_detector_bit_err_ssp_capt_q`](#bit_err_detector_bit_err_ssp_capt_q)                         | 0x68     |        4 | Auto-extracted signal bit_err_ssp_capt_q from bit_err_detector.vhd             |
+| can_bus.[`bit_err_detector_bit_err_ssp_valid`](#bit_err_detector_bit_err_ssp_valid)                           | 0x6c     |        4 | Auto-extracted signal bit_err_ssp_valid from bit_err_detector.vhd              |
+| can_bus.[`bit_err_detector_bit_err_ssp_condition`](#bit_err_detector_bit_err_ssp_condition)                   | 0x70     |        4 | Auto-extracted signal bit_err_ssp_condition from bit_err_detector.vhd          |
+| can_bus.[`bit_err_detector_bit_err_norm_valid`](#bit_err_detector_bit_err_norm_valid)                         | 0x74     |        4 | Auto-extracted signal bit_err_norm_valid from bit_err_detector.vhd             |
+| can_bus.[`bit_filter_masked_input`](#bit_filter_masked_input)                                                 | 0x78     |        4 | Auto-extracted signal masked_input from bit_filter.vhd                         |
+| can_bus.[`bit_filter_masked_value`](#bit_filter_masked_value)                                                 | 0x7c     |        4 | Auto-extracted signal masked_value from bit_filter.vhd                         |
+| can_bus.[`bit_segment_meter_sel_tseg1`](#bit_segment_meter_sel_tseg1)                                         | 0x80     |        4 | Auto-extracted signal sel_tseg1 from bit_segment_meter.vhd                     |
+| can_bus.[`bit_segment_meter_exp_seg_length_ce`](#bit_segment_meter_exp_seg_length_ce)                         | 0x84     |        4 | Auto-extracted signal exp_seg_length_ce from bit_segment_meter.vhd             |
+| can_bus.[`bit_segment_meter_phase_err_mt_sjw`](#bit_segment_meter_phase_err_mt_sjw)                           | 0x88     |        4 | Auto-extracted signal phase_err_mt_sjw from bit_segment_meter.vhd              |
+| can_bus.[`bit_segment_meter_phase_err_eq_sjw`](#bit_segment_meter_phase_err_eq_sjw)                           | 0x8c     |        4 | Auto-extracted signal phase_err_eq_sjw from bit_segment_meter.vhd              |
+| can_bus.[`bit_segment_meter_exit_ph2_immediate`](#bit_segment_meter_exit_ph2_immediate)                       | 0x90     |        4 | Auto-extracted signal exit_ph2_immediate from bit_segment_meter.vhd            |
+| can_bus.[`bit_segment_meter_exit_segm_regular`](#bit_segment_meter_exit_segm_regular)                         | 0x94     |        4 | Auto-extracted signal exit_segm_regular from bit_segment_meter.vhd             |
+| can_bus.[`bit_segment_meter_exit_segm_regular_tseg1`](#bit_segment_meter_exit_segm_regular_tseg1)             | 0x98     |        4 | Auto-extracted signal exit_segm_regular_tseg1 from bit_segment_meter.vhd       |
+| can_bus.[`bit_segment_meter_exit_segm_regular_tseg2`](#bit_segment_meter_exit_segm_regular_tseg2)             | 0x9c     |        4 | Auto-extracted signal exit_segm_regular_tseg2 from bit_segment_meter.vhd       |
+| can_bus.[`bit_segment_meter_sjw_mt_zero`](#bit_segment_meter_sjw_mt_zero)                                     | 0xa0     |        4 | Auto-extracted signal sjw_mt_zero from bit_segment_meter.vhd                   |
+| can_bus.[`bit_segment_meter_use_basic_segm_length`](#bit_segment_meter_use_basic_segm_length)                 | 0xa4     |        4 | Auto-extracted signal use_basic_segm_length from bit_segment_meter.vhd         |
+| can_bus.[`bit_segment_meter_phase_err_sjw_by_one`](#bit_segment_meter_phase_err_sjw_by_one)                   | 0xa8     |        4 | Auto-extracted signal phase_err_sjw_by_one from bit_segment_meter.vhd          |
+| can_bus.[`bit_segment_meter_shorten_tseg1_after_tseg2`](#bit_segment_meter_shorten_tseg1_after_tseg2)         | 0xac     |        4 | Auto-extracted signal shorten_tseg1_after_tseg2 from bit_segment_meter.vhd     |
+| can_bus.[`bit_stuffing_data_out_i`](#bit_stuffing_data_out_i)                                                 | 0xb0     |        4 | Auto-extracted signal data_out_i from bit_stuffing.vhd                         |
+| can_bus.[`bit_stuffing_data_halt_q`](#bit_stuffing_data_halt_q)                                               | 0xb4     |        4 | Auto-extracted signal data_halt_q from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_data_halt_d`](#bit_stuffing_data_halt_d)                                               | 0xb8     |        4 | Auto-extracted signal data_halt_d from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_fixed_reg_q`](#bit_stuffing_fixed_reg_q)                                               | 0xbc     |        4 | Auto-extracted signal fixed_reg_q from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_fixed_reg_d`](#bit_stuffing_fixed_reg_d)                                               | 0xc0     |        4 | Auto-extracted signal fixed_reg_d from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_enable_prev`](#bit_stuffing_enable_prev)                                               | 0xc4     |        4 | Auto-extracted signal enable_prev from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_non_fix_to_fix_chng`](#bit_stuffing_non_fix_to_fix_chng)                               | 0xc8     |        4 | Auto-extracted signal non_fix_to_fix_chng from bit_stuffing.vhd                |
+| can_bus.[`bit_stuffing_stuff_lvl_reached`](#bit_stuffing_stuff_lvl_reached)                                   | 0xcc     |        4 | Auto-extracted signal stuff_lvl_reached from bit_stuffing.vhd                  |
+| can_bus.[`bit_stuffing_same_bits_rst_trig`](#bit_stuffing_same_bits_rst_trig)                                 | 0xd0     |        4 | Auto-extracted signal same_bits_rst_trig from bit_stuffing.vhd                 |
+| can_bus.[`bit_stuffing_same_bits_rst`](#bit_stuffing_same_bits_rst)                                           | 0xd4     |        4 | Auto-extracted signal same_bits_rst from bit_stuffing.vhd                      |
+| can_bus.[`bit_stuffing_insert_stuff_bit`](#bit_stuffing_insert_stuff_bit)                                     | 0xd8     |        4 | Auto-extracted signal insert_stuff_bit from bit_stuffing.vhd                   |
+| can_bus.[`bit_stuffing_data_out_d_ena`](#bit_stuffing_data_out_d_ena)                                         | 0xdc     |        4 | Auto-extracted signal data_out_d_ena from bit_stuffing.vhd                     |
+| can_bus.[`bit_stuffing_data_out_d`](#bit_stuffing_data_out_d)                                                 | 0xe0     |        4 | Auto-extracted signal data_out_d from bit_stuffing.vhd                         |
+| can_bus.[`bit_stuffing_data_out_ce`](#bit_stuffing_data_out_ce)                                               | 0xe4     |        4 | Auto-extracted signal data_out_ce from bit_stuffing.vhd                        |
+| can_bus.[`bit_time_cfg_capture_drv_tq_nbt`](#bit_time_cfg_capture_drv_tq_nbt)                                 | 0xe8     |        4 | Auto-extracted signal drv_tq_nbt from bit_time_cfg_capture.vhd                 |
+| can_bus.[`bit_time_cfg_capture_drv_prs_nbt`](#bit_time_cfg_capture_drv_prs_nbt)                               | 0xec     |        4 | Auto-extracted signal drv_prs_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph1_nbt`](#bit_time_cfg_capture_drv_ph1_nbt)                               | 0xf0     |        4 | Auto-extracted signal drv_ph1_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph2_nbt`](#bit_time_cfg_capture_drv_ph2_nbt)                               | 0xf4     |        4 | Auto-extracted signal drv_ph2_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_sjw_nbt`](#bit_time_cfg_capture_drv_sjw_nbt)                               | 0xf8     |        4 | Auto-extracted signal drv_sjw_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_tq_dbt`](#bit_time_cfg_capture_drv_tq_dbt)                                 | 0xfc     |        4 | Auto-extracted signal drv_tq_dbt from bit_time_cfg_capture.vhd                 |
+| can_bus.[`bit_time_cfg_capture_drv_prs_dbt`](#bit_time_cfg_capture_drv_prs_dbt)                               | 0x100    |        4 | Auto-extracted signal drv_prs_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph1_dbt`](#bit_time_cfg_capture_drv_ph1_dbt)                               | 0x104    |        4 | Auto-extracted signal drv_ph1_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph2_dbt`](#bit_time_cfg_capture_drv_ph2_dbt)                               | 0x108    |        4 | Auto-extracted signal drv_ph2_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_sjw_dbt`](#bit_time_cfg_capture_drv_sjw_dbt)                               | 0x10c    |        4 | Auto-extracted signal drv_sjw_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_tseg1_nbt_d`](#bit_time_cfg_capture_tseg1_nbt_d)                               | 0x110    |        4 | Auto-extracted signal tseg1_nbt_d from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_tseg1_dbt_d`](#bit_time_cfg_capture_tseg1_dbt_d)                               | 0x114    |        4 | Auto-extracted signal tseg1_dbt_d from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ena`](#bit_time_cfg_capture_drv_ena)                                       | 0x118    |        4 | Auto-extracted signal drv_ena from bit_time_cfg_capture.vhd                    |
+| can_bus.[`bit_time_cfg_capture_drv_ena_reg`](#bit_time_cfg_capture_drv_ena_reg)                               | 0x11c    |        4 | Auto-extracted signal drv_ena_reg from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ena_reg_2`](#bit_time_cfg_capture_drv_ena_reg_2)                           | 0x120    |        4 | Auto-extracted signal drv_ena_reg_2 from bit_time_cfg_capture.vhd              |
+| can_bus.[`bit_time_cfg_capture_capture`](#bit_time_cfg_capture_capture)                                       | 0x124    |        4 | Auto-extracted signal capture from bit_time_cfg_capture.vhd                    |
+| can_bus.[`bit_time_counters_tq_counter_d`](#bit_time_counters_tq_counter_d)                                   | 0x128    |        4 | Auto-extracted signal tq_counter_d from bit_time_counters.vhd                  |
+| can_bus.[`bit_time_counters_tq_counter_q`](#bit_time_counters_tq_counter_q)                                   | 0x12c    |        4 | Auto-extracted signal tq_counter_q from bit_time_counters.vhd                  |
+| can_bus.[`bit_time_counters_tq_counter_ce`](#bit_time_counters_tq_counter_ce)                                 | 0x130    |        4 | Auto-extracted signal tq_counter_ce from bit_time_counters.vhd                 |
+| can_bus.[`bit_time_counters_tq_counter_allow`](#bit_time_counters_tq_counter_allow)                           | 0x134    |        4 | Auto-extracted signal tq_counter_allow from bit_time_counters.vhd              |
+| can_bus.[`bit_time_counters_tq_edge_i`](#bit_time_counters_tq_edge_i)                                         | 0x138    |        4 | Auto-extracted signal tq_edge_i from bit_time_counters.vhd                     |
+| can_bus.[`bit_time_counters_segm_counter_d`](#bit_time_counters_segm_counter_d)                               | 0x13c    |        4 | Auto-extracted signal segm_counter_d from bit_time_counters.vhd                |
+| can_bus.[`bit_time_counters_segm_counter_q`](#bit_time_counters_segm_counter_q)                               | 0x140    |        4 | Auto-extracted signal segm_counter_q from bit_time_counters.vhd                |
+| can_bus.[`bit_time_counters_segm_counter_ce`](#bit_time_counters_segm_counter_ce)                             | 0x144    |        4 | Auto-extracted signal segm_counter_ce from bit_time_counters.vhd               |
+| can_bus.[`bit_time_fsm_bt_fsm_ce`](#bit_time_fsm_bt_fsm_ce)                                                   | 0x148    |        4 | Auto-extracted signal bt_fsm_ce from bit_time_fsm.vhd                          |
+| can_bus.[`bus_sampling_drv_ena`](#bus_sampling_drv_ena)                                                       | 0x14c    |        4 | Auto-extracted signal drv_ena from bus_sampling.vhd                            |
+| can_bus.[`bus_sampling_drv_ssp_offset`](#bus_sampling_drv_ssp_offset)                                         | 0x150    |        4 | Auto-extracted signal drv_ssp_offset from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_drv_ssp_delay_select`](#bus_sampling_drv_ssp_delay_select)                             | 0x154    |        4 | Auto-extracted signal drv_ssp_delay_select from bus_sampling.vhd               |
+| can_bus.[`bus_sampling_data_rx_synced`](#bus_sampling_data_rx_synced)                                         | 0x158    |        4 | Auto-extracted signal data_rx_synced from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_prev_Sample`](#bus_sampling_prev_sample)                                               | 0x15c    |        4 | Auto-extracted signal prev_Sample from bus_sampling.vhd                        |
+| can_bus.[`bus_sampling_sample_sec_i`](#bus_sampling_sample_sec_i)                                             | 0x160    |        4 | Auto-extracted signal sample_sec_i from bus_sampling.vhd                       |
+| can_bus.[`bus_sampling_data_tx_delayed`](#bus_sampling_data_tx_delayed)                                       | 0x164    |        4 | Auto-extracted signal data_tx_delayed from bus_sampling.vhd                    |
+| can_bus.[`bus_sampling_edge_rx_valid`](#bus_sampling_edge_rx_valid)                                           | 0x168    |        4 | Auto-extracted signal edge_rx_valid from bus_sampling.vhd                      |
+| can_bus.[`bus_sampling_edge_tx_valid`](#bus_sampling_edge_tx_valid)                                           | 0x16c    |        4 | Auto-extracted signal edge_tx_valid from bus_sampling.vhd                      |
+| can_bus.[`bus_sampling_ssp_delay`](#bus_sampling_ssp_delay)                                                   | 0x170    |        4 | Auto-extracted signal ssp_delay from bus_sampling.vhd                          |
+| can_bus.[`bus_sampling_tx_trigger_q`](#bus_sampling_tx_trigger_q)                                             | 0x174    |        4 | Auto-extracted signal tx_trigger_q from bus_sampling.vhd                       |
+| can_bus.[`bus_sampling_tx_trigger_ssp`](#bus_sampling_tx_trigger_ssp)                                         | 0x178    |        4 | Auto-extracted signal tx_trigger_ssp from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_shift_regs_res_d`](#bus_sampling_shift_regs_res_d)                                     | 0x17c    |        4 | Auto-extracted signal shift_regs_res_d from bus_sampling.vhd                   |
+| can_bus.[`bus_sampling_shift_regs_res_q`](#bus_sampling_shift_regs_res_q)                                     | 0x180    |        4 | Auto-extracted signal shift_regs_res_q from bus_sampling.vhd                   |
+| can_bus.[`bus_sampling_shift_regs_res_q_scan`](#bus_sampling_shift_regs_res_q_scan)                           | 0x184    |        4 | Auto-extracted signal shift_regs_res_q_scan from bus_sampling.vhd              |
+| can_bus.[`bus_sampling_ssp_enable`](#bus_sampling_ssp_enable)                                                 | 0x188    |        4 | Auto-extracted signal ssp_enable from bus_sampling.vhd                         |
+| can_bus.[`bus_traffic_counters_tx_ctr_i`](#bus_traffic_counters_tx_ctr_i)                                     | 0x18c    |        4 | Auto-extracted signal tx_ctr_i from bus_traffic_counters.vhd                   |
+| can_bus.[`bus_traffic_counters_rx_ctr_i`](#bus_traffic_counters_rx_ctr_i)                                     | 0x190    |        4 | Auto-extracted signal rx_ctr_i from bus_traffic_counters.vhd                   |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_d`](#bus_traffic_counters_tx_ctr_rst_n_d)                         | 0x194    |        4 | Auto-extracted signal tx_ctr_rst_n_d from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_q`](#bus_traffic_counters_tx_ctr_rst_n_q)                         | 0x198    |        4 | Auto-extracted signal tx_ctr_rst_n_q from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_q_scan`](#bus_traffic_counters_tx_ctr_rst_n_q_scan)               | 0x19c    |        4 | Auto-extracted signal tx_ctr_rst_n_q_scan from bus_traffic_counters.vhd        |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_d`](#bus_traffic_counters_rx_ctr_rst_n_d)                         | 0x1a0    |        4 | Auto-extracted signal rx_ctr_rst_n_d from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_q`](#bus_traffic_counters_rx_ctr_rst_n_q)                         | 0x1a4    |        4 | Auto-extracted signal rx_ctr_rst_n_q from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_q_scan`](#bus_traffic_counters_rx_ctr_rst_n_q_scan)               | 0x1a8    |        4 | Auto-extracted signal rx_ctr_rst_n_q_scan from bus_traffic_counters.vhd        |
+| can_bus.[`can_apb_tb_s_apb_paddr`](#can_apb_tb_s_apb_paddr)                                                   | 0x1ac    |        4 | Auto-extracted signal s_apb_paddr from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_penable`](#can_apb_tb_s_apb_penable)                                               | 0x1b0    |        4 | Auto-extracted signal s_apb_penable from can_apb_tb.vhd                        |
+| can_bus.[`can_apb_tb_s_apb_pprot`](#can_apb_tb_s_apb_pprot)                                                   | 0x1b4    |        4 | Auto-extracted signal s_apb_pprot from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_prdata`](#can_apb_tb_s_apb_prdata)                                                 | 0x1b8    |        4 | Auto-extracted signal s_apb_prdata from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_pready`](#can_apb_tb_s_apb_pready)                                                 | 0x1bc    |        4 | Auto-extracted signal s_apb_pready from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_psel`](#can_apb_tb_s_apb_psel)                                                     | 0x1c0    |        4 | Auto-extracted signal s_apb_psel from can_apb_tb.vhd                           |
+| can_bus.[`can_apb_tb_s_apb_pslverr`](#can_apb_tb_s_apb_pslverr)                                               | 0x1c4    |        4 | Auto-extracted signal s_apb_pslverr from can_apb_tb.vhd                        |
+| can_bus.[`can_apb_tb_s_apb_pstrb`](#can_apb_tb_s_apb_pstrb)                                                   | 0x1c8    |        4 | Auto-extracted signal s_apb_pstrb from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_pwdata`](#can_apb_tb_s_apb_pwdata)                                                 | 0x1cc    |        4 | Auto-extracted signal s_apb_pwdata from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_pwrite`](#can_apb_tb_s_apb_pwrite)                                                 | 0x1d0    |        4 | Auto-extracted signal s_apb_pwrite from can_apb_tb.vhd                         |
+| can_bus.[`can_core_drv_clr_rx_ctr`](#can_core_drv_clr_rx_ctr)                                                 | 0x1d4    |        4 | Auto-extracted signal drv_clr_rx_ctr from can_core.vhd                         |
+| can_bus.[`can_core_drv_clr_tx_ctr`](#can_core_drv_clr_tx_ctr)                                                 | 0x1d8    |        4 | Auto-extracted signal drv_clr_tx_ctr from can_core.vhd                         |
+| can_bus.[`can_core_drv_bus_mon_ena`](#can_core_drv_bus_mon_ena)                                               | 0x1dc    |        4 | Auto-extracted signal drv_bus_mon_ena from can_core.vhd                        |
+| can_bus.[`can_core_drv_ena`](#can_core_drv_ena)                                                               | 0x1e0    |        4 | Auto-extracted signal drv_ena from can_core.vhd                                |
+| can_bus.[`can_core_rec_ident_i`](#can_core_rec_ident_i)                                                       | 0x1e4    |        4 | Auto-extracted signal rec_ident_i from can_core.vhd                            |
+| can_bus.[`can_core_rec_dlc_i`](#can_core_rec_dlc_i)                                                           | 0x1e8    |        4 | Auto-extracted signal rec_dlc_i from can_core.vhd                              |
+| can_bus.[`can_core_rec_ident_type_i`](#can_core_rec_ident_type_i)                                             | 0x1ec    |        4 | Auto-extracted signal rec_ident_type_i from can_core.vhd                       |
+| can_bus.[`can_core_rec_frame_type_i`](#can_core_rec_frame_type_i)                                             | 0x1f0    |        4 | Auto-extracted signal rec_frame_type_i from can_core.vhd                       |
+| can_bus.[`can_core_rec_is_rtr_i`](#can_core_rec_is_rtr_i)                                                     | 0x1f4    |        4 | Auto-extracted signal rec_is_rtr_i from can_core.vhd                           |
+| can_bus.[`can_core_rec_brs_i`](#can_core_rec_brs_i)                                                           | 0x1f8    |        4 | Auto-extracted signal rec_brs_i from can_core.vhd                              |
+| can_bus.[`can_core_rec_esi_i`](#can_core_rec_esi_i)                                                           | 0x1fc    |        4 | Auto-extracted signal rec_esi_i from can_core.vhd                              |
+| can_bus.[`can_core_alc`](#can_core_alc)                                                                       | 0x200    |        4 | Auto-extracted signal alc from can_core.vhd                                    |
+| can_bus.[`can_core_erc_capture`](#can_core_erc_capture)                                                       | 0x204    |        4 | Auto-extracted signal erc_capture from can_core.vhd                            |
+| can_bus.[`can_core_is_transmitter`](#can_core_is_transmitter)                                                 | 0x208    |        4 | Auto-extracted signal is_transmitter from can_core.vhd                         |
+| can_bus.[`can_core_is_receiver`](#can_core_is_receiver)                                                       | 0x20c    |        4 | Auto-extracted signal is_receiver from can_core.vhd                            |
+| can_bus.[`can_core_is_idle`](#can_core_is_idle)                                                               | 0x210    |        4 | Auto-extracted signal is_idle from can_core.vhd                                |
+| can_bus.[`can_core_arbitration_lost_i`](#can_core_arbitration_lost_i)                                         | 0x214    |        4 | Auto-extracted signal arbitration_lost_i from can_core.vhd                     |
+| can_bus.[`can_core_set_transmitter`](#can_core_set_transmitter)                                               | 0x218    |        4 | Auto-extracted signal set_transmitter from can_core.vhd                        |
+| can_bus.[`can_core_set_receiver`](#can_core_set_receiver)                                                     | 0x21c    |        4 | Auto-extracted signal set_receiver from can_core.vhd                           |
+| can_bus.[`can_core_set_idle`](#can_core_set_idle)                                                             | 0x220    |        4 | Auto-extracted signal set_idle from can_core.vhd                               |
+| can_bus.[`can_core_is_err_active`](#can_core_is_err_active)                                                   | 0x224    |        4 | Auto-extracted signal is_err_active from can_core.vhd                          |
+| can_bus.[`can_core_is_err_passive`](#can_core_is_err_passive)                                                 | 0x228    |        4 | Auto-extracted signal is_err_passive from can_core.vhd                         |
+| can_bus.[`can_core_is_bus_off_i`](#can_core_is_bus_off_i)                                                     | 0x22c    |        4 | Auto-extracted signal is_bus_off_i from can_core.vhd                           |
+| can_bus.[`can_core_err_detected_i`](#can_core_err_detected_i)                                                 | 0x230    |        4 | Auto-extracted signal err_detected_i from can_core.vhd                         |
+| can_bus.[`can_core_primary_err`](#can_core_primary_err)                                                       | 0x234    |        4 | Auto-extracted signal primary_err from can_core.vhd                            |
+| can_bus.[`can_core_act_err_ovr_flag`](#can_core_act_err_ovr_flag)                                             | 0x238    |        4 | Auto-extracted signal act_err_ovr_flag from can_core.vhd                       |
+| can_bus.[`can_core_err_delim_late`](#can_core_err_delim_late)                                                 | 0x23c    |        4 | Auto-extracted signal err_delim_late from can_core.vhd                         |
+| can_bus.[`can_core_set_err_active`](#can_core_set_err_active)                                                 | 0x240    |        4 | Auto-extracted signal set_err_active from can_core.vhd                         |
+| can_bus.[`can_core_err_ctrs_unchanged`](#can_core_err_ctrs_unchanged)                                         | 0x244    |        4 | Auto-extracted signal err_ctrs_unchanged from can_core.vhd                     |
+| can_bus.[`can_core_stuff_enable`](#can_core_stuff_enable)                                                     | 0x248    |        4 | Auto-extracted signal stuff_enable from can_core.vhd                           |
+| can_bus.[`can_core_destuff_enable`](#can_core_destuff_enable)                                                 | 0x24c    |        4 | Auto-extracted signal destuff_enable from can_core.vhd                         |
+| can_bus.[`can_core_fixed_stuff`](#can_core_fixed_stuff)                                                       | 0x250    |        4 | Auto-extracted signal fixed_stuff from can_core.vhd                            |
+| can_bus.[`can_core_tx_frame_no_sof`](#can_core_tx_frame_no_sof)                                               | 0x254    |        4 | Auto-extracted signal tx_frame_no_sof from can_core.vhd                        |
+| can_bus.[`can_core_stuff_length`](#can_core_stuff_length)                                                     | 0x258    |        4 | Auto-extracted signal stuff_length from can_core.vhd                           |
+| can_bus.[`can_core_dst_ctr`](#can_core_dst_ctr)                                                               | 0x25c    |        4 | Auto-extracted signal dst_ctr from can_core.vhd                                |
+| can_bus.[`can_core_bst_ctr`](#can_core_bst_ctr)                                                               | 0x260    |        4 | Auto-extracted signal bst_ctr from can_core.vhd                                |
+| can_bus.[`can_core_stuff_err`](#can_core_stuff_err)                                                           | 0x264    |        4 | Auto-extracted signal stuff_err from can_core.vhd                              |
+| can_bus.[`can_core_crc_enable`](#can_core_crc_enable)                                                         | 0x268    |        4 | Auto-extracted signal crc_enable from can_core.vhd                             |
+| can_bus.[`can_core_crc_spec_enable`](#can_core_crc_spec_enable)                                               | 0x26c    |        4 | Auto-extracted signal crc_spec_enable from can_core.vhd                        |
+| can_bus.[`can_core_crc_calc_from_rx`](#can_core_crc_calc_from_rx)                                             | 0x270    |        4 | Auto-extracted signal crc_calc_from_rx from can_core.vhd                       |
+| can_bus.[`can_core_crc_15`](#can_core_crc_15)                                                                 | 0x274    |        4 | Auto-extracted signal crc_15 from can_core.vhd                                 |
+| can_bus.[`can_core_crc_17`](#can_core_crc_17)                                                                 | 0x278    |        4 | Auto-extracted signal crc_17 from can_core.vhd                                 |
+| can_bus.[`can_core_crc_21`](#can_core_crc_21)                                                                 | 0x27c    |        4 | Auto-extracted signal crc_21 from can_core.vhd                                 |
+| can_bus.[`can_core_sp_control_i`](#can_core_sp_control_i)                                                     | 0x280    |        4 | Auto-extracted signal sp_control_i from can_core.vhd                           |
+| can_bus.[`can_core_sp_control_q`](#can_core_sp_control_q)                                                     | 0x284    |        4 | Auto-extracted signal sp_control_q from can_core.vhd                           |
+| can_bus.[`can_core_sync_control_i`](#can_core_sync_control_i)                                                 | 0x288    |        4 | Auto-extracted signal sync_control_i from can_core.vhd                         |
+| can_bus.[`can_core_ssp_reset_i`](#can_core_ssp_reset_i)                                                       | 0x28c    |        4 | Auto-extracted signal ssp_reset_i from can_core.vhd                            |
+| can_bus.[`can_core_tran_delay_meas_i`](#can_core_tran_delay_meas_i)                                           | 0x290    |        4 | Auto-extracted signal tran_delay_meas_i from can_core.vhd                      |
+| can_bus.[`can_core_tran_valid_i`](#can_core_tran_valid_i)                                                     | 0x294    |        4 | Auto-extracted signal tran_valid_i from can_core.vhd                           |
+| can_bus.[`can_core_rec_valid_i`](#can_core_rec_valid_i)                                                       | 0x298    |        4 | Auto-extracted signal rec_valid_i from can_core.vhd                            |
+| can_bus.[`can_core_br_shifted_i`](#can_core_br_shifted_i)                                                     | 0x29c    |        4 | Auto-extracted signal br_shifted_i from can_core.vhd                           |
+| can_bus.[`can_core_fcs_changed_i`](#can_core_fcs_changed_i)                                                   | 0x2a0    |        4 | Auto-extracted signal fcs_changed_i from can_core.vhd                          |
+| can_bus.[`can_core_err_warning_limit_i`](#can_core_err_warning_limit_i)                                       | 0x2a4    |        4 | Auto-extracted signal err_warning_limit_i from can_core.vhd                    |
+| can_bus.[`can_core_tx_err_ctr`](#can_core_tx_err_ctr)                                                         | 0x2a8    |        4 | Auto-extracted signal tx_err_ctr from can_core.vhd                             |
+| can_bus.[`can_core_rx_err_ctr`](#can_core_rx_err_ctr)                                                         | 0x2ac    |        4 | Auto-extracted signal rx_err_ctr from can_core.vhd                             |
+| can_bus.[`can_core_norm_err_ctr`](#can_core_norm_err_ctr)                                                     | 0x2b0    |        4 | Auto-extracted signal norm_err_ctr from can_core.vhd                           |
+| can_bus.[`can_core_data_err_ctr`](#can_core_data_err_ctr)                                                     | 0x2b4    |        4 | Auto-extracted signal data_err_ctr from can_core.vhd                           |
+| can_bus.[`can_core_pc_tx_trigger`](#can_core_pc_tx_trigger)                                                   | 0x2b8    |        4 | Auto-extracted signal pc_tx_trigger from can_core.vhd                          |
+| can_bus.[`can_core_pc_rx_trigger`](#can_core_pc_rx_trigger)                                                   | 0x2bc    |        4 | Auto-extracted signal pc_rx_trigger from can_core.vhd                          |
+| can_bus.[`can_core_pc_tx_data_nbs`](#can_core_pc_tx_data_nbs)                                                 | 0x2c0    |        4 | Auto-extracted signal pc_tx_data_nbs from can_core.vhd                         |
+| can_bus.[`can_core_pc_rx_data_nbs`](#can_core_pc_rx_data_nbs)                                                 | 0x2c4    |        4 | Auto-extracted signal pc_rx_data_nbs from can_core.vhd                         |
+| can_bus.[`can_core_crc_data_tx_wbs`](#can_core_crc_data_tx_wbs)                                               | 0x2c8    |        4 | Auto-extracted signal crc_data_tx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_tx_nbs`](#can_core_crc_data_tx_nbs)                                               | 0x2cc    |        4 | Auto-extracted signal crc_data_tx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_rx_wbs`](#can_core_crc_data_rx_wbs)                                               | 0x2d0    |        4 | Auto-extracted signal crc_data_rx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_rx_nbs`](#can_core_crc_data_rx_nbs)                                               | 0x2d4    |        4 | Auto-extracted signal crc_data_rx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_tx_wbs`](#can_core_crc_trig_tx_wbs)                                               | 0x2d8    |        4 | Auto-extracted signal crc_trig_tx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_tx_nbs`](#can_core_crc_trig_tx_nbs)                                               | 0x2dc    |        4 | Auto-extracted signal crc_trig_tx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_rx_wbs`](#can_core_crc_trig_rx_wbs)                                               | 0x2e0    |        4 | Auto-extracted signal crc_trig_rx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_rx_nbs`](#can_core_crc_trig_rx_nbs)                                               | 0x2e4    |        4 | Auto-extracted signal crc_trig_rx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_bst_data_in`](#can_core_bst_data_in)                                                       | 0x2e8    |        4 | Auto-extracted signal bst_data_in from can_core.vhd                            |
+| can_bus.[`can_core_bst_data_out`](#can_core_bst_data_out)                                                     | 0x2ec    |        4 | Auto-extracted signal bst_data_out from can_core.vhd                           |
+| can_bus.[`can_core_bst_trigger`](#can_core_bst_trigger)                                                       | 0x2f0    |        4 | Auto-extracted signal bst_trigger from can_core.vhd                            |
+| can_bus.[`can_core_data_halt`](#can_core_data_halt)                                                           | 0x2f4    |        4 | Auto-extracted signal data_halt from can_core.vhd                              |
+| can_bus.[`can_core_bds_data_in`](#can_core_bds_data_in)                                                       | 0x2f8    |        4 | Auto-extracted signal bds_data_in from can_core.vhd                            |
+| can_bus.[`can_core_bds_data_out`](#can_core_bds_data_out)                                                     | 0x2fc    |        4 | Auto-extracted signal bds_data_out from can_core.vhd                           |
+| can_bus.[`can_core_bds_trigger`](#can_core_bds_trigger)                                                       | 0x300    |        4 | Auto-extracted signal bds_trigger from can_core.vhd                            |
+| can_bus.[`can_core_destuffed`](#can_core_destuffed)                                                           | 0x304    |        4 | Auto-extracted signal destuffed from can_core.vhd                              |
+| can_bus.[`can_core_tx_ctr`](#can_core_tx_ctr)                                                                 | 0x308    |        4 | Auto-extracted signal tx_ctr from can_core.vhd                                 |
+| can_bus.[`can_core_rx_ctr`](#can_core_rx_ctr)                                                                 | 0x30c    |        4 | Auto-extracted signal rx_ctr from can_core.vhd                                 |
+| can_bus.[`can_core_tx_data_wbs_i`](#can_core_tx_data_wbs_i)                                                   | 0x310    |        4 | Auto-extracted signal tx_data_wbs_i from can_core.vhd                          |
+| can_bus.[`can_core_lpb_dominant`](#can_core_lpb_dominant)                                                     | 0x314    |        4 | Auto-extracted signal lpb_dominant from can_core.vhd                           |
+| can_bus.[`can_core_form_err`](#can_core_form_err)                                                             | 0x318    |        4 | Auto-extracted signal form_err from can_core.vhd                               |
+| can_bus.[`can_core_ack_err`](#can_core_ack_err)                                                               | 0x31c    |        4 | Auto-extracted signal ack_err from can_core.vhd                                |
+| can_bus.[`can_core_crc_err`](#can_core_crc_err)                                                               | 0x320    |        4 | Auto-extracted signal crc_err from can_core.vhd                                |
+| can_bus.[`can_core_is_arbitration`](#can_core_is_arbitration)                                                 | 0x324    |        4 | Auto-extracted signal is_arbitration from can_core.vhd                         |
+| can_bus.[`can_core_is_control`](#can_core_is_control)                                                         | 0x328    |        4 | Auto-extracted signal is_control from can_core.vhd                             |
+| can_bus.[`can_core_is_data`](#can_core_is_data)                                                               | 0x32c    |        4 | Auto-extracted signal is_data from can_core.vhd                                |
+| can_bus.[`can_core_is_stuff_count`](#can_core_is_stuff_count)                                                 | 0x330    |        4 | Auto-extracted signal is_stuff_count from can_core.vhd                         |
+| can_bus.[`can_core_is_crc`](#can_core_is_crc)                                                                 | 0x334    |        4 | Auto-extracted signal is_crc from can_core.vhd                                 |
+| can_bus.[`can_core_is_crc_delim`](#can_core_is_crc_delim)                                                     | 0x338    |        4 | Auto-extracted signal is_crc_delim from can_core.vhd                           |
+| can_bus.[`can_core_is_ack_field`](#can_core_is_ack_field)                                                     | 0x33c    |        4 | Auto-extracted signal is_ack_field from can_core.vhd                           |
+| can_bus.[`can_core_is_ack_delim`](#can_core_is_ack_delim)                                                     | 0x340    |        4 | Auto-extracted signal is_ack_delim from can_core.vhd                           |
+| can_bus.[`can_core_is_eof`](#can_core_is_eof)                                                                 | 0x344    |        4 | Auto-extracted signal is_eof from can_core.vhd                                 |
+| can_bus.[`can_core_is_err_frm`](#can_core_is_err_frm)                                                         | 0x348    |        4 | Auto-extracted signal is_err_frm from can_core.vhd                             |
+| can_bus.[`can_core_is_intermission`](#can_core_is_intermission)                                               | 0x34c    |        4 | Auto-extracted signal is_intermission from can_core.vhd                        |
+| can_bus.[`can_core_is_suspend`](#can_core_is_suspend)                                                         | 0x350    |        4 | Auto-extracted signal is_suspend from can_core.vhd                             |
+| can_bus.[`can_core_is_overload_i`](#can_core_is_overload_i)                                                   | 0x354    |        4 | Auto-extracted signal is_overload_i from can_core.vhd                          |
+| can_bus.[`can_core_is_sof`](#can_core_is_sof)                                                                 | 0x358    |        4 | Auto-extracted signal is_sof from can_core.vhd                                 |
+| can_bus.[`can_core_sof_pulse_i`](#can_core_sof_pulse_i)                                                       | 0x35c    |        4 | Auto-extracted signal sof_pulse_i from can_core.vhd                            |
+| can_bus.[`can_core_load_init_vect`](#can_core_load_init_vect)                                                 | 0x360    |        4 | Auto-extracted signal load_init_vect from can_core.vhd                         |
+| can_bus.[`can_core_retr_ctr_i`](#can_core_retr_ctr_i)                                                         | 0x364    |        4 | Auto-extracted signal retr_ctr_i from can_core.vhd                             |
+| can_bus.[`can_core_decrement_rec`](#can_core_decrement_rec)                                                   | 0x368    |        4 | Auto-extracted signal decrement_rec from can_core.vhd                          |
+| can_bus.[`can_core_bit_err_after_ack_err`](#can_core_bit_err_after_ack_err)                                   | 0x36c    |        4 | Auto-extracted signal bit_err_after_ack_err from can_core.vhd                  |
+| can_bus.[`can_core_is_pexs`](#can_core_is_pexs)                                                               | 0x370    |        4 | Auto-extracted signal is_pexs from can_core.vhd                                |
+| can_bus.[`can_crc_drv_fd_type`](#can_crc_drv_fd_type)                                                         | 0x374    |        4 | Auto-extracted signal drv_fd_type from can_crc.vhd                             |
+| can_bus.[`can_crc_init_vect_15`](#can_crc_init_vect_15)                                                       | 0x378    |        4 | Auto-extracted signal init_vect_15 from can_crc.vhd                            |
+| can_bus.[`can_crc_init_vect_17`](#can_crc_init_vect_17)                                                       | 0x37c    |        4 | Auto-extracted signal init_vect_17 from can_crc.vhd                            |
+| can_bus.[`can_crc_init_vect_21`](#can_crc_init_vect_21)                                                       | 0x380    |        4 | Auto-extracted signal init_vect_21 from can_crc.vhd                            |
+| can_bus.[`can_crc_crc_17_21_data_in`](#can_crc_crc_17_21_data_in)                                             | 0x384    |        4 | Auto-extracted signal crc_17_21_data_in from can_crc.vhd                       |
+| can_bus.[`can_crc_crc_17_21_trigger`](#can_crc_crc_17_21_trigger)                                             | 0x388    |        4 | Auto-extracted signal crc_17_21_trigger from can_crc.vhd                       |
+| can_bus.[`can_crc_crc_15_data_in`](#can_crc_crc_15_data_in)                                                   | 0x38c    |        4 | Auto-extracted signal crc_15_data_in from can_crc.vhd                          |
+| can_bus.[`can_crc_crc_15_trigger`](#can_crc_crc_15_trigger)                                                   | 0x390    |        4 | Auto-extracted signal crc_15_trigger from can_crc.vhd                          |
+| can_bus.[`can_crc_crc_ena_15`](#can_crc_crc_ena_15)                                                           | 0x394    |        4 | Auto-extracted signal crc_ena_15 from can_crc.vhd                              |
+| can_bus.[`can_crc_crc_ena_17_21`](#can_crc_crc_ena_17_21)                                                     | 0x398    |        4 | Auto-extracted signal crc_ena_17_21 from can_crc.vhd                           |
+| can_bus.[`can_top_ahb_ctu_can_data_in`](#can_top_ahb_ctu_can_data_in)                                         | 0x39c    |        4 | Auto-extracted signal ctu_can_data_in from can_top_ahb.vhd                     |
+| can_bus.[`can_top_ahb_ctu_can_data_out`](#can_top_ahb_ctu_can_data_out)                                       | 0x3a0    |        4 | Auto-extracted signal ctu_can_data_out from can_top_ahb.vhd                    |
+| can_bus.[`can_top_ahb_ctu_can_adress`](#can_top_ahb_ctu_can_adress)                                           | 0x3a4    |        4 | Auto-extracted signal ctu_can_adress from can_top_ahb.vhd                      |
+| can_bus.[`can_top_ahb_ctu_can_scs`](#can_top_ahb_ctu_can_scs)                                                 | 0x3a8    |        4 | Auto-extracted signal ctu_can_scs from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_srd`](#can_top_ahb_ctu_can_srd)                                                 | 0x3ac    |        4 | Auto-extracted signal ctu_can_srd from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_swr`](#can_top_ahb_ctu_can_swr)                                                 | 0x3b0    |        4 | Auto-extracted signal ctu_can_swr from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_sbe`](#can_top_ahb_ctu_can_sbe)                                                 | 0x3b4    |        4 | Auto-extracted signal ctu_can_sbe from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_res_n_out_i`](#can_top_ahb_res_n_out_i)                                                 | 0x3b8    |        4 | Auto-extracted signal res_n_out_i from can_top_ahb.vhd                         |
+| can_bus.[`can_top_apb_reg_data_in`](#can_top_apb_reg_data_in)                                                 | 0x3bc    |        4 | Auto-extracted signal reg_data_in from can_top_apb.vhd                         |
+| can_bus.[`can_top_apb_reg_data_out`](#can_top_apb_reg_data_out)                                               | 0x3c0    |        4 | Auto-extracted signal reg_data_out from can_top_apb.vhd                        |
+| can_bus.[`can_top_apb_reg_addr`](#can_top_apb_reg_addr)                                                       | 0x3c4    |        4 | Auto-extracted signal reg_addr from can_top_apb.vhd                            |
+| can_bus.[`can_top_apb_reg_be`](#can_top_apb_reg_be)                                                           | 0x3c8    |        4 | Auto-extracted signal reg_be from can_top_apb.vhd                              |
+| can_bus.[`can_top_apb_reg_rden`](#can_top_apb_reg_rden)                                                       | 0x3cc    |        4 | Auto-extracted signal reg_rden from can_top_apb.vhd                            |
+| can_bus.[`can_top_apb_reg_wren`](#can_top_apb_reg_wren)                                                       | 0x3d0    |        4 | Auto-extracted signal reg_wren from can_top_apb.vhd                            |
+| can_bus.[`can_top_level_drv_bus`](#can_top_level_drv_bus)                                                     | 0x3d4    |        4 | Auto-extracted signal drv_bus from can_top_level.vhd                           |
+| can_bus.[`can_top_level_stat_bus`](#can_top_level_stat_bus)                                                   | 0x3d8    |        4 | Auto-extracted signal stat_bus from can_top_level.vhd                          |
+| can_bus.[`can_top_level_res_n_sync`](#can_top_level_res_n_sync)                                               | 0x3dc    |        4 | Auto-extracted signal res_n_sync from can_top_level.vhd                        |
+| can_bus.[`can_top_level_res_core_n`](#can_top_level_res_core_n)                                               | 0x3e0    |        4 | Auto-extracted signal res_core_n from can_top_level.vhd                        |
+| can_bus.[`can_top_level_res_soft_n`](#can_top_level_res_soft_n)                                               | 0x3e4    |        4 | Auto-extracted signal res_soft_n from can_top_level.vhd                        |
+| can_bus.[`can_top_level_sp_control`](#can_top_level_sp_control)                                               | 0x3e8    |        4 | Auto-extracted signal sp_control from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rx_buf_size`](#can_top_level_rx_buf_size)                                             | 0x3ec    |        4 | Auto-extracted signal rx_buf_size from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_full`](#can_top_level_rx_full)                                                     | 0x3f0    |        4 | Auto-extracted signal rx_full from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rx_empty`](#can_top_level_rx_empty)                                                   | 0x3f4    |        4 | Auto-extracted signal rx_empty from can_top_level.vhd                          |
+| can_bus.[`can_top_level_rx_frame_count`](#can_top_level_rx_frame_count)                                       | 0x3f8    |        4 | Auto-extracted signal rx_frame_count from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rx_mem_free`](#can_top_level_rx_mem_free)                                             | 0x3fc    |        4 | Auto-extracted signal rx_mem_free from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_read_pointer`](#can_top_level_rx_read_pointer)                                     | 0x400    |        4 | Auto-extracted signal rx_read_pointer from can_top_level.vhd                   |
+| can_bus.[`can_top_level_rx_write_pointer`](#can_top_level_rx_write_pointer)                                   | 0x404    |        4 | Auto-extracted signal rx_write_pointer from can_top_level.vhd                  |
+| can_bus.[`can_top_level_rx_data_overrun`](#can_top_level_rx_data_overrun)                                     | 0x408    |        4 | Auto-extracted signal rx_data_overrun from can_top_level.vhd                   |
+| can_bus.[`can_top_level_rx_read_buff`](#can_top_level_rx_read_buff)                                           | 0x40c    |        4 | Auto-extracted signal rx_read_buff from can_top_level.vhd                      |
+| can_bus.[`can_top_level_rx_mof`](#can_top_level_rx_mof)                                                       | 0x410    |        4 | Auto-extracted signal rx_mof from can_top_level.vhd                            |
+| can_bus.[`can_top_level_txtb_port_a_data`](#can_top_level_txtb_port_a_data)                                   | 0x414    |        4 | Auto-extracted signal txtb_port_a_data from can_top_level.vhd                  |
+| can_bus.[`can_top_level_txtb_port_a_address`](#can_top_level_txtb_port_a_address)                             | 0x418    |        4 | Auto-extracted signal txtb_port_a_address from can_top_level.vhd               |
+| can_bus.[`can_top_level_txtb_port_a_cs`](#can_top_level_txtb_port_a_cs)                                       | 0x41c    |        4 | Auto-extracted signal txtb_port_a_cs from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_port_a_be`](#can_top_level_txtb_port_a_be)                                       | 0x420    |        4 | Auto-extracted signal txtb_port_a_be from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_sw_cmd_index`](#can_top_level_txtb_sw_cmd_index)                                 | 0x424    |        4 | Auto-extracted signal txtb_sw_cmd_index from can_top_level.vhd                 |
+| can_bus.[`can_top_level_txt_buf_failed_bof`](#can_top_level_txt_buf_failed_bof)                               | 0x428    |        4 | Auto-extracted signal txt_buf_failed_bof from can_top_level.vhd                |
+| can_bus.[`can_top_level_int_vector`](#can_top_level_int_vector)                                               | 0x42c    |        4 | Auto-extracted signal int_vector from can_top_level.vhd                        |
+| can_bus.[`can_top_level_int_ena`](#can_top_level_int_ena)                                                     | 0x430    |        4 | Auto-extracted signal int_ena from can_top_level.vhd                           |
+| can_bus.[`can_top_level_int_mask`](#can_top_level_int_mask)                                                   | 0x434    |        4 | Auto-extracted signal int_mask from can_top_level.vhd                          |
+| can_bus.[`can_top_level_rec_ident`](#can_top_level_rec_ident)                                                 | 0x438    |        4 | Auto-extracted signal rec_ident from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rec_dlc`](#can_top_level_rec_dlc)                                                     | 0x43c    |        4 | Auto-extracted signal rec_dlc from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rec_ident_type`](#can_top_level_rec_ident_type)                                       | 0x440    |        4 | Auto-extracted signal rec_ident_type from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rec_frame_type`](#can_top_level_rec_frame_type)                                       | 0x444    |        4 | Auto-extracted signal rec_frame_type from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rec_is_rtr`](#can_top_level_rec_is_rtr)                                               | 0x448    |        4 | Auto-extracted signal rec_is_rtr from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rec_brs`](#can_top_level_rec_brs)                                                     | 0x44c    |        4 | Auto-extracted signal rec_brs from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rec_esi`](#can_top_level_rec_esi)                                                     | 0x450    |        4 | Auto-extracted signal rec_esi from can_top_level.vhd                           |
+| can_bus.[`can_top_level_store_data_word`](#can_top_level_store_data_word)                                     | 0x454    |        4 | Auto-extracted signal store_data_word from can_top_level.vhd                   |
+| can_bus.[`can_top_level_sof_pulse`](#can_top_level_sof_pulse)                                                 | 0x458    |        4 | Auto-extracted signal sof_pulse from can_top_level.vhd                         |
+| can_bus.[`can_top_level_store_metadata`](#can_top_level_store_metadata)                                       | 0x45c    |        4 | Auto-extracted signal store_metadata from can_top_level.vhd                    |
+| can_bus.[`can_top_level_store_data`](#can_top_level_store_data)                                               | 0x460    |        4 | Auto-extracted signal store_data from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rec_valid`](#can_top_level_rec_valid)                                                 | 0x464    |        4 | Auto-extracted signal rec_valid from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rec_abort`](#can_top_level_rec_abort)                                                 | 0x468    |        4 | Auto-extracted signal rec_abort from can_top_level.vhd                         |
+| can_bus.[`can_top_level_store_metadata_f`](#can_top_level_store_metadata_f)                                   | 0x46c    |        4 | Auto-extracted signal store_metadata_f from can_top_level.vhd                  |
+| can_bus.[`can_top_level_store_data_f`](#can_top_level_store_data_f)                                           | 0x470    |        4 | Auto-extracted signal store_data_f from can_top_level.vhd                      |
+| can_bus.[`can_top_level_rec_valid_f`](#can_top_level_rec_valid_f)                                             | 0x474    |        4 | Auto-extracted signal rec_valid_f from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rec_abort_f`](#can_top_level_rec_abort_f)                                             | 0x478    |        4 | Auto-extracted signal rec_abort_f from can_top_level.vhd                       |
+| can_bus.[`can_top_level_txtb_hw_cmd_int`](#can_top_level_txtb_hw_cmd_int)                                     | 0x47c    |        4 | Auto-extracted signal txtb_hw_cmd_int from can_top_level.vhd                   |
+| can_bus.[`can_top_level_is_bus_off`](#can_top_level_is_bus_off)                                               | 0x480    |        4 | Auto-extracted signal is_bus_off from can_top_level.vhd                        |
+| can_bus.[`can_top_level_txtb_available`](#can_top_level_txtb_available)                                       | 0x484    |        4 | Auto-extracted signal txtb_available from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_port_b_clk_en`](#can_top_level_txtb_port_b_clk_en)                               | 0x488    |        4 | Auto-extracted signal txtb_port_b_clk_en from can_top_level.vhd                |
+| can_bus.[`can_top_level_tran_dlc`](#can_top_level_tran_dlc)                                                   | 0x48c    |        4 | Auto-extracted signal tran_dlc from can_top_level.vhd                          |
+| can_bus.[`can_top_level_tran_is_rtr`](#can_top_level_tran_is_rtr)                                             | 0x490    |        4 | Auto-extracted signal tran_is_rtr from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tran_ident_type`](#can_top_level_tran_ident_type)                                     | 0x494    |        4 | Auto-extracted signal tran_ident_type from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_frame_type`](#can_top_level_tran_frame_type)                                     | 0x498    |        4 | Auto-extracted signal tran_frame_type from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_brs`](#can_top_level_tran_brs)                                                   | 0x49c    |        4 | Auto-extracted signal tran_brs from can_top_level.vhd                          |
+| can_bus.[`can_top_level_tran_identifier`](#can_top_level_tran_identifier)                                     | 0x4a0    |        4 | Auto-extracted signal tran_identifier from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_word`](#can_top_level_tran_word)                                                 | 0x4a4    |        4 | Auto-extracted signal tran_word from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tran_frame_valid`](#can_top_level_tran_frame_valid)                                   | 0x4a8    |        4 | Auto-extracted signal tran_frame_valid from can_top_level.vhd                  |
+| can_bus.[`can_top_level_txtb_changed`](#can_top_level_txtb_changed)                                           | 0x4ac    |        4 | Auto-extracted signal txtb_changed from can_top_level.vhd                      |
+| can_bus.[`can_top_level_txtb_clk_en`](#can_top_level_txtb_clk_en)                                             | 0x4b0    |        4 | Auto-extracted signal txtb_clk_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_err_detected`](#can_top_level_err_detected)                                           | 0x4b4    |        4 | Auto-extracted signal err_detected from can_top_level.vhd                      |
+| can_bus.[`can_top_level_fcs_changed`](#can_top_level_fcs_changed)                                             | 0x4b8    |        4 | Auto-extracted signal fcs_changed from can_top_level.vhd                       |
+| can_bus.[`can_top_level_err_warning_limit`](#can_top_level_err_warning_limit)                                 | 0x4bc    |        4 | Auto-extracted signal err_warning_limit from can_top_level.vhd                 |
+| can_bus.[`can_top_level_arbitration_lost`](#can_top_level_arbitration_lost)                                   | 0x4c0    |        4 | Auto-extracted signal arbitration_lost from can_top_level.vhd                  |
+| can_bus.[`can_top_level_tran_valid`](#can_top_level_tran_valid)                                               | 0x4c4    |        4 | Auto-extracted signal tran_valid from can_top_level.vhd                        |
+| can_bus.[`can_top_level_br_shifted`](#can_top_level_br_shifted)                                               | 0x4c8    |        4 | Auto-extracted signal br_shifted from can_top_level.vhd                        |
+| can_bus.[`can_top_level_is_overload`](#can_top_level_is_overload)                                             | 0x4cc    |        4 | Auto-extracted signal is_overload from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_triggers`](#can_top_level_rx_triggers)                                             | 0x4d0    |        4 | Auto-extracted signal rx_triggers from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tx_trigger`](#can_top_level_tx_trigger)                                               | 0x4d4    |        4 | Auto-extracted signal tx_trigger from can_top_level.vhd                        |
+| can_bus.[`can_top_level_sync_control`](#can_top_level_sync_control)                                           | 0x4d8    |        4 | Auto-extracted signal sync_control from can_top_level.vhd                      |
+| can_bus.[`can_top_level_no_pos_resync`](#can_top_level_no_pos_resync)                                         | 0x4dc    |        4 | Auto-extracted signal no_pos_resync from can_top_level.vhd                     |
+| can_bus.[`can_top_level_nbt_ctrs_en`](#can_top_level_nbt_ctrs_en)                                             | 0x4e0    |        4 | Auto-extracted signal nbt_ctrs_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_dbt_ctrs_en`](#can_top_level_dbt_ctrs_en)                                             | 0x4e4    |        4 | Auto-extracted signal dbt_ctrs_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_trv_delay`](#can_top_level_trv_delay)                                                 | 0x4e8    |        4 | Auto-extracted signal trv_delay from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rx_data_wbs`](#can_top_level_rx_data_wbs)                                             | 0x4ec    |        4 | Auto-extracted signal rx_data_wbs from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tx_data_wbs`](#can_top_level_tx_data_wbs)                                             | 0x4f0    |        4 | Auto-extracted signal tx_data_wbs from can_top_level.vhd                       |
+| can_bus.[`can_top_level_ssp_reset`](#can_top_level_ssp_reset)                                                 | 0x4f4    |        4 | Auto-extracted signal ssp_reset from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tran_delay_meas`](#can_top_level_tran_delay_meas)                                     | 0x4f8    |        4 | Auto-extracted signal tran_delay_meas from can_top_level.vhd                   |
+| can_bus.[`can_top_level_bit_err`](#can_top_level_bit_err)                                                     | 0x4fc    |        4 | Auto-extracted signal bit_err from can_top_level.vhd                           |
+| can_bus.[`can_top_level_sample_sec`](#can_top_level_sample_sec)                                               | 0x500    |        4 | Auto-extracted signal sample_sec from can_top_level.vhd                        |
+| can_bus.[`can_top_level_btmc_reset`](#can_top_level_btmc_reset)                                               | 0x504    |        4 | Auto-extracted signal btmc_reset from can_top_level.vhd                        |
+| can_bus.[`can_top_level_dbt_measure_start`](#can_top_level_dbt_measure_start)                                 | 0x508    |        4 | Auto-extracted signal dbt_measure_start from can_top_level.vhd                 |
+| can_bus.[`can_top_level_gen_first_ssp`](#can_top_level_gen_first_ssp)                                         | 0x50c    |        4 | Auto-extracted signal gen_first_ssp from can_top_level.vhd                     |
+| can_bus.[`can_top_level_sync_edge`](#can_top_level_sync_edge)                                                 | 0x510    |        4 | Auto-extracted signal sync_edge from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tq_edge`](#can_top_level_tq_edge)                                                     | 0x514    |        4 | Auto-extracted signal tq_edge from can_top_level.vhd                           |
+| can_bus.[`can_top_level_tst_rdata_rx_buf`](#can_top_level_tst_rdata_rx_buf)                                   | 0x518    |        4 | Auto-extracted signal tst_rdata_rx_buf from can_top_level.vhd                  |
+| can_bus.[`clk_gate_clk_en_q`](#clk_gate_clk_en_q)                                                             | 0x51c    |        4 | Auto-extracted signal clk_en_q from clk_gate.vhd                               |
+| can_bus.[`control_counter_ctrl_ctr_ce`](#control_counter_ctrl_ctr_ce)                                         | 0x520    |        4 | Auto-extracted signal ctrl_ctr_ce from control_counter.vhd                     |
+| can_bus.[`control_counter_compl_ctr_ce`](#control_counter_compl_ctr_ce)                                       | 0x524    |        4 | Auto-extracted signal compl_ctr_ce from control_counter.vhd                    |
+| can_bus.[`control_registers_reg_map_reg_sel`](#control_registers_reg_map_reg_sel)                             | 0x528    |        4 | Auto-extracted signal reg_sel from control_registers_reg_map.vhd               |
+| can_bus.[`control_registers_reg_map_read_data_mux_in`](#control_registers_reg_map_read_data_mux_in)           | 0x52c    |        4 | Auto-extracted signal read_data_mux_in from control_registers_reg_map.vhd      |
+| can_bus.[`control_registers_reg_map_read_data_mask_n`](#control_registers_reg_map_read_data_mask_n)           | 0x530    |        4 | Auto-extracted signal read_data_mask_n from control_registers_reg_map.vhd      |
+| can_bus.[`control_registers_reg_map_read_mux_ena`](#control_registers_reg_map_read_mux_ena)                   | 0x534    |        4 | Auto-extracted signal read_mux_ena from control_registers_reg_map.vhd          |
+| can_bus.[`crc_calc_crc_q`](#crc_calc_crc_q)                                                                   | 0x538    |        4 | Auto-extracted signal crc_q from crc_calc.vhd                                  |
+| can_bus.[`crc_calc_crc_nxt`](#crc_calc_crc_nxt)                                                               | 0x53c    |        4 | Auto-extracted signal crc_nxt from crc_calc.vhd                                |
+| can_bus.[`crc_calc_crc_shift`](#crc_calc_crc_shift)                                                           | 0x540    |        4 | Auto-extracted signal crc_shift from crc_calc.vhd                              |
+| can_bus.[`crc_calc_crc_shift_n_xor`](#crc_calc_crc_shift_n_xor)                                               | 0x544    |        4 | Auto-extracted signal crc_shift_n_xor from crc_calc.vhd                        |
+| can_bus.[`crc_calc_crc_d`](#crc_calc_crc_d)                                                                   | 0x548    |        4 | Auto-extracted signal crc_d from crc_calc.vhd                                  |
+| can_bus.[`crc_calc_crc_ce`](#crc_calc_crc_ce)                                                                 | 0x54c    |        4 | Auto-extracted signal crc_ce from crc_calc.vhd                                 |
+| can_bus.[`data_edge_detector_rx_data_prev`](#data_edge_detector_rx_data_prev)                                 | 0x550    |        4 | Auto-extracted signal rx_data_prev from data_edge_detector.vhd                 |
+| can_bus.[`data_edge_detector_tx_data_prev`](#data_edge_detector_tx_data_prev)                                 | 0x554    |        4 | Auto-extracted signal tx_data_prev from data_edge_detector.vhd                 |
+| can_bus.[`data_edge_detector_rx_data_sync_prev`](#data_edge_detector_rx_data_sync_prev)                       | 0x558    |        4 | Auto-extracted signal rx_data_sync_prev from data_edge_detector.vhd            |
+| can_bus.[`data_edge_detector_rx_edge_i`](#data_edge_detector_rx_edge_i)                                       | 0x55c    |        4 | Auto-extracted signal rx_edge_i from data_edge_detector.vhd                    |
+| can_bus.[`data_edge_detector_tx_edge_i`](#data_edge_detector_tx_edge_i)                                       | 0x560    |        4 | Auto-extracted signal tx_edge_i from data_edge_detector.vhd                    |
+| can_bus.[`data_mux_sel_data`](#data_mux_sel_data)                                                             | 0x564    |        4 | Auto-extracted signal sel_data from data_mux.vhd                               |
+| can_bus.[`data_mux_saturated_data`](#data_mux_saturated_data)                                                 | 0x568    |        4 | Auto-extracted signal saturated_data from data_mux.vhd                         |
+| can_bus.[`data_mux_masked_data`](#data_mux_masked_data)                                                       | 0x56c    |        4 | Auto-extracted signal masked_data from data_mux.vhd                            |
+| can_bus.[`dlc_decoder_data_len_8_to_64`](#dlc_decoder_data_len_8_to_64)                                       | 0x570    |        4 | Auto-extracted signal data_len_8_to_64 from dlc_decoder.vhd                    |
+| can_bus.[`dlc_decoder_data_len_can_2_0`](#dlc_decoder_data_len_can_2_0)                                       | 0x574    |        4 | Auto-extracted signal data_len_can_2_0 from dlc_decoder.vhd                    |
+| can_bus.[`dlc_decoder_data_len_can_fd`](#dlc_decoder_data_len_can_fd)                                         | 0x578    |        4 | Auto-extracted signal data_len_can_fd from dlc_decoder.vhd                     |
+| can_bus.[`endian_swapper_swapped`](#endian_swapper_swapped)                                                   | 0x57c    |        4 | Auto-extracted signal swapped from endian_swapper.vhd                          |
+| can_bus.[`err_counters_tx_err_ctr_ce`](#err_counters_tx_err_ctr_ce)                                           | 0x580    |        4 | Auto-extracted signal tx_err_ctr_ce from err_counters.vhd                      |
+| can_bus.[`err_counters_rx_err_ctr_ce`](#err_counters_rx_err_ctr_ce)                                           | 0x584    |        4 | Auto-extracted signal rx_err_ctr_ce from err_counters.vhd                      |
+| can_bus.[`err_counters_modif_tx_ctr`](#err_counters_modif_tx_ctr)                                             | 0x588    |        4 | Auto-extracted signal modif_tx_ctr from err_counters.vhd                       |
+| can_bus.[`err_counters_modif_rx_ctr`](#err_counters_modif_rx_ctr)                                             | 0x58c    |        4 | Auto-extracted signal modif_rx_ctr from err_counters.vhd                       |
+| can_bus.[`err_counters_nom_err_ctr_ce`](#err_counters_nom_err_ctr_ce)                                         | 0x590    |        4 | Auto-extracted signal nom_err_ctr_ce from err_counters.vhd                     |
+| can_bus.[`err_counters_data_err_ctr_ce`](#err_counters_data_err_ctr_ce)                                       | 0x594    |        4 | Auto-extracted signal data_err_ctr_ce from err_counters.vhd                    |
+| can_bus.[`err_counters_res_err_ctrs_d`](#err_counters_res_err_ctrs_d)                                         | 0x598    |        4 | Auto-extracted signal res_err_ctrs_d from err_counters.vhd                     |
+| can_bus.[`err_counters_res_err_ctrs_q`](#err_counters_res_err_ctrs_q)                                         | 0x59c    |        4 | Auto-extracted signal res_err_ctrs_q from err_counters.vhd                     |
+| can_bus.[`err_counters_res_err_ctrs_q_scan`](#err_counters_res_err_ctrs_q_scan)                               | 0x5a0    |        4 | Auto-extracted signal res_err_ctrs_q_scan from err_counters.vhd                |
+| can_bus.[`err_detector_err_frm_req_i`](#err_detector_err_frm_req_i)                                           | 0x5a4    |        4 | Auto-extracted signal err_frm_req_i from err_detector.vhd                      |
+| can_bus.[`err_detector_err_type_d`](#err_detector_err_type_d)                                                 | 0x5a8    |        4 | Auto-extracted signal err_type_d from err_detector.vhd                         |
+| can_bus.[`err_detector_err_type_q`](#err_detector_err_type_q)                                                 | 0x5ac    |        4 | Auto-extracted signal err_type_q from err_detector.vhd                         |
+| can_bus.[`err_detector_err_pos_q`](#err_detector_err_pos_q)                                                   | 0x5b0    |        4 | Auto-extracted signal err_pos_q from err_detector.vhd                          |
+| can_bus.[`err_detector_form_err_i`](#err_detector_form_err_i)                                                 | 0x5b4    |        4 | Auto-extracted signal form_err_i from err_detector.vhd                         |
+| can_bus.[`err_detector_crc_match_c`](#err_detector_crc_match_c)                                               | 0x5b8    |        4 | Auto-extracted signal crc_match_c from err_detector.vhd                        |
+| can_bus.[`err_detector_crc_match_d`](#err_detector_crc_match_d)                                               | 0x5bc    |        4 | Auto-extracted signal crc_match_d from err_detector.vhd                        |
+| can_bus.[`err_detector_crc_match_q`](#err_detector_crc_match_q)                                               | 0x5c0    |        4 | Auto-extracted signal crc_match_q from err_detector.vhd                        |
+| can_bus.[`err_detector_dst_ctr_grey`](#err_detector_dst_ctr_grey)                                             | 0x5c4    |        4 | Auto-extracted signal dst_ctr_grey from err_detector.vhd                       |
+| can_bus.[`err_detector_dst_parity`](#err_detector_dst_parity)                                                 | 0x5c8    |        4 | Auto-extracted signal dst_parity from err_detector.vhd                         |
+| can_bus.[`err_detector_stuff_count_check`](#err_detector_stuff_count_check)                                   | 0x5cc    |        4 | Auto-extracted signal stuff_count_check from err_detector.vhd                  |
+| can_bus.[`err_detector_crc_15_ok`](#err_detector_crc_15_ok)                                                   | 0x5d0    |        4 | Auto-extracted signal crc_15_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_crc_17_ok`](#err_detector_crc_17_ok)                                                   | 0x5d4    |        4 | Auto-extracted signal crc_17_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_crc_21_ok`](#err_detector_crc_21_ok)                                                   | 0x5d8    |        4 | Auto-extracted signal crc_21_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_stuff_count_ok`](#err_detector_stuff_count_ok)                                         | 0x5dc    |        4 | Auto-extracted signal stuff_count_ok from err_detector.vhd                     |
+| can_bus.[`err_detector_rx_crc_15`](#err_detector_rx_crc_15)                                                   | 0x5e0    |        4 | Auto-extracted signal rx_crc_15 from err_detector.vhd                          |
+| can_bus.[`err_detector_rx_crc_17`](#err_detector_rx_crc_17)                                                   | 0x5e4    |        4 | Auto-extracted signal rx_crc_17 from err_detector.vhd                          |
+| can_bus.[`err_detector_rx_crc_21`](#err_detector_rx_crc_21)                                                   | 0x5e8    |        4 | Auto-extracted signal rx_crc_21 from err_detector.vhd                          |
+| can_bus.[`fault_confinement_drv_ewl`](#fault_confinement_drv_ewl)                                             | 0x5ec    |        4 | Auto-extracted signal drv_ewl from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_erp`](#fault_confinement_drv_erp)                                             | 0x5f0    |        4 | Auto-extracted signal drv_erp from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_ctr_val`](#fault_confinement_drv_ctr_val)                                     | 0x5f4    |        4 | Auto-extracted signal drv_ctr_val from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_drv_ctr_sel`](#fault_confinement_drv_ctr_sel)                                     | 0x5f8    |        4 | Auto-extracted signal drv_ctr_sel from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_drv_ena`](#fault_confinement_drv_ena)                                             | 0x5fc    |        4 | Auto-extracted signal drv_ena from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_tx_err_ctr_i`](#fault_confinement_tx_err_ctr_i)                                   | 0x600    |        4 | Auto-extracted signal tx_err_ctr_i from fault_confinement.vhd                  |
+| can_bus.[`fault_confinement_rx_err_ctr_i`](#fault_confinement_rx_err_ctr_i)                                   | 0x604    |        4 | Auto-extracted signal rx_err_ctr_i from fault_confinement.vhd                  |
+| can_bus.[`fault_confinement_inc_one`](#fault_confinement_inc_one)                                             | 0x608    |        4 | Auto-extracted signal inc_one from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_inc_eight`](#fault_confinement_inc_eight)                                         | 0x60c    |        4 | Auto-extracted signal inc_eight from fault_confinement.vhd                     |
+| can_bus.[`fault_confinement_dec_one`](#fault_confinement_dec_one)                                             | 0x610    |        4 | Auto-extracted signal dec_one from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_rom_ena`](#fault_confinement_drv_rom_ena)                                     | 0x614    |        4 | Auto-extracted signal drv_rom_ena from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_erp`](#fault_confinement_fsm_tx_err_ctr_mt_erp)                 | 0x618    |        4 | Auto-extracted signal tx_err_ctr_mt_erp from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_rx_err_ctr_mt_erp`](#fault_confinement_fsm_rx_err_ctr_mt_erp)                 | 0x61c    |        4 | Auto-extracted signal rx_err_ctr_mt_erp from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_ewl`](#fault_confinement_fsm_tx_err_ctr_mt_ewl)                 | 0x620    |        4 | Auto-extracted signal tx_err_ctr_mt_ewl from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_rx_err_ctr_mt_ewl`](#fault_confinement_fsm_rx_err_ctr_mt_ewl)                 | 0x624    |        4 | Auto-extracted signal rx_err_ctr_mt_ewl from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_255`](#fault_confinement_fsm_tx_err_ctr_mt_255)                 | 0x628    |        4 | Auto-extracted signal tx_err_ctr_mt_255 from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_err_warning_limit_d`](#fault_confinement_fsm_err_warning_limit_d)             | 0x62c    |        4 | Auto-extracted signal err_warning_limit_d from fault_confinement_fsm.vhd       |
+| can_bus.[`fault_confinement_fsm_err_warning_limit_q`](#fault_confinement_fsm_err_warning_limit_q)             | 0x630    |        4 | Auto-extracted signal err_warning_limit_q from fault_confinement_fsm.vhd       |
+| can_bus.[`fault_confinement_fsm_fc_fsm_res_d`](#fault_confinement_fsm_fc_fsm_res_d)                           | 0x634    |        4 | Auto-extracted signal fc_fsm_res_d from fault_confinement_fsm.vhd              |
+| can_bus.[`fault_confinement_fsm_fc_fsm_res_q`](#fault_confinement_fsm_fc_fsm_res_q)                           | 0x638    |        4 | Auto-extracted signal fc_fsm_res_q from fault_confinement_fsm.vhd              |
+| can_bus.[`fault_confinement_rules_inc_one_i`](#fault_confinement_rules_inc_one_i)                             | 0x63c    |        4 | Auto-extracted signal inc_one_i from fault_confinement_rules.vhd               |
+| can_bus.[`fault_confinement_rules_inc_eight_i`](#fault_confinement_rules_inc_eight_i)                         | 0x640    |        4 | Auto-extracted signal inc_eight_i from fault_confinement_rules.vhd             |
+| can_bus.[`frame_filters_drv_filter_A_mask`](#frame_filters_drv_filter_a_mask)                                 | 0x644    |        4 | Auto-extracted signal drv_filter_A_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_A_ctrl`](#frame_filters_drv_filter_a_ctrl)                                 | 0x648    |        4 | Auto-extracted signal drv_filter_A_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_A_bits`](#frame_filters_drv_filter_a_bits)                                 | 0x64c    |        4 | Auto-extracted signal drv_filter_A_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_A_valid`](#frame_filters_int_filter_a_valid)                               | 0x650    |        4 | Auto-extracted signal int_filter_A_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_B_mask`](#frame_filters_drv_filter_b_mask)                                 | 0x654    |        4 | Auto-extracted signal drv_filter_B_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_B_ctrl`](#frame_filters_drv_filter_b_ctrl)                                 | 0x658    |        4 | Auto-extracted signal drv_filter_B_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_B_bits`](#frame_filters_drv_filter_b_bits)                                 | 0x65c    |        4 | Auto-extracted signal drv_filter_B_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_B_valid`](#frame_filters_int_filter_b_valid)                               | 0x660    |        4 | Auto-extracted signal int_filter_B_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_C_mask`](#frame_filters_drv_filter_c_mask)                                 | 0x664    |        4 | Auto-extracted signal drv_filter_C_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_C_ctrl`](#frame_filters_drv_filter_c_ctrl)                                 | 0x668    |        4 | Auto-extracted signal drv_filter_C_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_C_bits`](#frame_filters_drv_filter_c_bits)                                 | 0x66c    |        4 | Auto-extracted signal drv_filter_C_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_C_valid`](#frame_filters_int_filter_c_valid)                               | 0x670    |        4 | Auto-extracted signal int_filter_C_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_ran_ctrl`](#frame_filters_drv_filter_ran_ctrl)                             | 0x674    |        4 | Auto-extracted signal drv_filter_ran_ctrl from frame_filters.vhd               |
+| can_bus.[`frame_filters_drv_filter_ran_lo_th`](#frame_filters_drv_filter_ran_lo_th)                           | 0x678    |        4 | Auto-extracted signal drv_filter_ran_lo_th from frame_filters.vhd              |
+| can_bus.[`frame_filters_drv_filter_ran_hi_th`](#frame_filters_drv_filter_ran_hi_th)                           | 0x67c    |        4 | Auto-extracted signal drv_filter_ran_hi_th from frame_filters.vhd              |
+| can_bus.[`frame_filters_int_filter_ran_valid`](#frame_filters_int_filter_ran_valid)                           | 0x680    |        4 | Auto-extracted signal int_filter_ran_valid from frame_filters.vhd              |
+| can_bus.[`frame_filters_drv_filters_ena`](#frame_filters_drv_filters_ena)                                     | 0x684    |        4 | Auto-extracted signal drv_filters_ena from frame_filters.vhd                   |
+| can_bus.[`frame_filters_int_data_type`](#frame_filters_int_data_type)                                         | 0x688    |        4 | Auto-extracted signal int_data_type from frame_filters.vhd                     |
+| can_bus.[`frame_filters_int_data_ctrl`](#frame_filters_int_data_ctrl)                                         | 0x68c    |        4 | Auto-extracted signal int_data_ctrl from frame_filters.vhd                     |
+| can_bus.[`frame_filters_filter_A_enable`](#frame_filters_filter_a_enable)                                     | 0x690    |        4 | Auto-extracted signal filter_A_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_B_enable`](#frame_filters_filter_b_enable)                                     | 0x694    |        4 | Auto-extracted signal filter_B_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_C_enable`](#frame_filters_filter_c_enable)                                     | 0x698    |        4 | Auto-extracted signal filter_C_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_range_enable`](#frame_filters_filter_range_enable)                             | 0x69c    |        4 | Auto-extracted signal filter_range_enable from frame_filters.vhd               |
+| can_bus.[`frame_filters_filter_result`](#frame_filters_filter_result)                                         | 0x6a0    |        4 | Auto-extracted signal filter_result from frame_filters.vhd                     |
+| can_bus.[`frame_filters_ident_valid_d`](#frame_filters_ident_valid_d)                                         | 0x6a4    |        4 | Auto-extracted signal ident_valid_d from frame_filters.vhd                     |
+| can_bus.[`frame_filters_ident_valid_q`](#frame_filters_ident_valid_q)                                         | 0x6a8    |        4 | Auto-extracted signal ident_valid_q from frame_filters.vhd                     |
+| can_bus.[`frame_filters_drv_drop_remote_frames`](#frame_filters_drv_drop_remote_frames)                       | 0x6ac    |        4 | Auto-extracted signal drv_drop_remote_frames from frame_filters.vhd            |
+| can_bus.[`frame_filters_drop_rtr_frame`](#frame_filters_drop_rtr_frame)                                       | 0x6b0    |        4 | Auto-extracted signal drop_rtr_frame from frame_filters.vhd                    |
+| can_bus.[`inf_ram_wrapper_int_read_data`](#inf_ram_wrapper_int_read_data)                                     | 0x6b4    |        4 | Auto-extracted signal int_read_data from inf_ram_wrapper.vhd                   |
+| can_bus.[`inf_ram_wrapper_byte_we`](#inf_ram_wrapper_byte_we)                                                 | 0x6b8    |        4 | Auto-extracted signal byte_we from inf_ram_wrapper.vhd                         |
+| can_bus.[`int_manager_drv_int_vect_clr`](#int_manager_drv_int_vect_clr)                                       | 0x6bc    |        4 | Auto-extracted signal drv_int_vect_clr from int_manager.vhd                    |
+| can_bus.[`int_manager_drv_int_ena_set`](#int_manager_drv_int_ena_set)                                         | 0x6c0    |        4 | Auto-extracted signal drv_int_ena_set from int_manager.vhd                     |
+| can_bus.[`int_manager_drv_int_ena_clr`](#int_manager_drv_int_ena_clr)                                         | 0x6c4    |        4 | Auto-extracted signal drv_int_ena_clr from int_manager.vhd                     |
+| can_bus.[`int_manager_drv_int_mask_set`](#int_manager_drv_int_mask_set)                                       | 0x6c8    |        4 | Auto-extracted signal drv_int_mask_set from int_manager.vhd                    |
+| can_bus.[`int_manager_drv_int_mask_clr`](#int_manager_drv_int_mask_clr)                                       | 0x6cc    |        4 | Auto-extracted signal drv_int_mask_clr from int_manager.vhd                    |
+| can_bus.[`int_manager_int_ena_i`](#int_manager_int_ena_i)                                                     | 0x6d0    |        4 | Auto-extracted signal int_ena_i from int_manager.vhd                           |
+| can_bus.[`int_manager_int_mask_i`](#int_manager_int_mask_i)                                                   | 0x6d4    |        4 | Auto-extracted signal int_mask_i from int_manager.vhd                          |
+| can_bus.[`int_manager_int_vect_i`](#int_manager_int_vect_i)                                                   | 0x6d8    |        4 | Auto-extracted signal int_vect_i from int_manager.vhd                          |
+| can_bus.[`int_manager_int_input_active`](#int_manager_int_input_active)                                       | 0x6dc    |        4 | Auto-extracted signal int_input_active from int_manager.vhd                    |
+| can_bus.[`int_manager_int_i`](#int_manager_int_i)                                                             | 0x6e0    |        4 | Auto-extracted signal int_i from int_manager.vhd                               |
+| can_bus.[`int_module_int_mask_i`](#int_module_int_mask_i)                                                     | 0x6e4    |        4 | Auto-extracted signal int_mask_i from int_module.vhd                           |
+| can_bus.[`int_module_int_ena_i`](#int_module_int_ena_i)                                                       | 0x6e8    |        4 | Auto-extracted signal int_ena_i from int_module.vhd                            |
+| can_bus.[`int_module_int_mask_load`](#int_module_int_mask_load)                                               | 0x6ec    |        4 | Auto-extracted signal int_mask_load from int_module.vhd                        |
+| can_bus.[`int_module_int_mask_next`](#int_module_int_mask_next)                                               | 0x6f0    |        4 | Auto-extracted signal int_mask_next from int_module.vhd                        |
+| can_bus.[`memory_reg_reg_value_r`](#memory_reg_reg_value_r)                                                   | 0x6f4    |        4 | Auto-extracted signal reg_value_r from memory_reg.vhd                          |
+| can_bus.[`memory_reg_wr_select`](#memory_reg_wr_select)                                                       | 0x6f8    |        4 | Auto-extracted signal wr_select from memory_reg.vhd                            |
+| can_bus.[`memory_reg_wr_select_expanded`](#memory_reg_wr_select_expanded)                                     | 0x6fc    |        4 | Auto-extracted signal wr_select_expanded from memory_reg.vhd                   |
+| can_bus.[`memory_registers_status_comb`](#memory_registers_status_comb)                                       | 0x700    |        4 | Auto-extracted signal status_comb from memory_registers.vhd                    |
+| can_bus.[`memory_registers_can_core_cs`](#memory_registers_can_core_cs)                                       | 0x704    |        4 | Auto-extracted signal can_core_cs from memory_registers.vhd                    |
+| can_bus.[`memory_registers_control_registers_cs`](#memory_registers_control_registers_cs)                     | 0x708    |        4 | Auto-extracted signal control_registers_cs from memory_registers.vhd           |
+| can_bus.[`memory_registers_control_registers_cs_reg`](#memory_registers_control_registers_cs_reg)             | 0x70c    |        4 | Auto-extracted signal control_registers_cs_reg from memory_registers.vhd       |
+| can_bus.[`memory_registers_test_registers_cs`](#memory_registers_test_registers_cs)                           | 0x710    |        4 | Auto-extracted signal test_registers_cs from memory_registers.vhd              |
+| can_bus.[`memory_registers_test_registers_cs_reg`](#memory_registers_test_registers_cs_reg)                   | 0x714    |        4 | Auto-extracted signal test_registers_cs_reg from memory_registers.vhd          |
+| can_bus.[`memory_registers_control_registers_rdata`](#memory_registers_control_registers_rdata)               | 0x718    |        4 | Auto-extracted signal control_registers_rdata from memory_registers.vhd        |
+| can_bus.[`memory_registers_test_registers_rdata`](#memory_registers_test_registers_rdata)                     | 0x71c    |        4 | Auto-extracted signal test_registers_rdata from memory_registers.vhd           |
+| can_bus.[`memory_registers_is_err_active`](#memory_registers_is_err_active)                                   | 0x720    |        4 | Auto-extracted signal is_err_active from memory_registers.vhd                  |
+| can_bus.[`memory_registers_is_err_passive`](#memory_registers_is_err_passive)                                 | 0x724    |        4 | Auto-extracted signal is_err_passive from memory_registers.vhd                 |
+| can_bus.[`memory_registers_is_bus_off`](#memory_registers_is_bus_off)                                         | 0x728    |        4 | Auto-extracted signal is_bus_off from memory_registers.vhd                     |
+| can_bus.[`memory_registers_is_transmitter`](#memory_registers_is_transmitter)                                 | 0x72c    |        4 | Auto-extracted signal is_transmitter from memory_registers.vhd                 |
+| can_bus.[`memory_registers_is_receiver`](#memory_registers_is_receiver)                                       | 0x730    |        4 | Auto-extracted signal is_receiver from memory_registers.vhd                    |
+| can_bus.[`memory_registers_is_idle`](#memory_registers_is_idle)                                               | 0x734    |        4 | Auto-extracted signal is_idle from memory_registers.vhd                        |
+| can_bus.[`memory_registers_reg_lock_1_active`](#memory_registers_reg_lock_1_active)                           | 0x738    |        4 | Auto-extracted signal reg_lock_1_active from memory_registers.vhd              |
+| can_bus.[`memory_registers_reg_lock_2_active`](#memory_registers_reg_lock_2_active)                           | 0x73c    |        4 | Auto-extracted signal reg_lock_2_active from memory_registers.vhd              |
+| can_bus.[`memory_registers_soft_res_q_n`](#memory_registers_soft_res_q_n)                                     | 0x740    |        4 | Auto-extracted signal soft_res_q_n from memory_registers.vhd                   |
+| can_bus.[`memory_registers_ewl_padded`](#memory_registers_ewl_padded)                                         | 0x744    |        4 | Auto-extracted signal ewl_padded from memory_registers.vhd                     |
+| can_bus.[`memory_registers_control_regs_clk_en`](#memory_registers_control_regs_clk_en)                       | 0x748    |        4 | Auto-extracted signal control_regs_clk_en from memory_registers.vhd            |
+| can_bus.[`memory_registers_test_regs_clk_en`](#memory_registers_test_regs_clk_en)                             | 0x74c    |        4 | Auto-extracted signal test_regs_clk_en from memory_registers.vhd               |
+| can_bus.[`memory_registers_clk_control_regs`](#memory_registers_clk_control_regs)                             | 0x750    |        4 | Auto-extracted signal clk_control_regs from memory_registers.vhd               |
+| can_bus.[`memory_registers_clk_test_regs`](#memory_registers_clk_test_regs)                                   | 0x754    |        4 | Auto-extracted signal clk_test_regs from memory_registers.vhd                  |
+| can_bus.[`memory_registers_rx_buf_mode`](#memory_registers_rx_buf_mode)                                       | 0x758    |        4 | Auto-extracted signal rx_buf_mode from memory_registers.vhd                    |
+| can_bus.[`memory_registers_rx_move_cmd`](#memory_registers_rx_move_cmd)                                       | 0x75c    |        4 | Auto-extracted signal rx_move_cmd from memory_registers.vhd                    |
+| can_bus.[`memory_registers_ctr_pres_sel_q`](#memory_registers_ctr_pres_sel_q)                                 | 0x760    |        4 | Auto-extracted signal ctr_pres_sel_q from memory_registers.vhd                 |
+| can_bus.[`operation_control_drv_ena`](#operation_control_drv_ena)                                             | 0x764    |        4 | Auto-extracted signal drv_ena from operation_control.vhd                       |
+| can_bus.[`operation_control_go_to_off`](#operation_control_go_to_off)                                         | 0x768    |        4 | Auto-extracted signal go_to_off from operation_control.vhd                     |
+| can_bus.[`prescaler_drv_ena`](#prescaler_drv_ena)                                                             | 0x76c    |        4 | Auto-extracted signal drv_ena from prescaler.vhd                               |
+| can_bus.[`prescaler_tseg1_nbt`](#prescaler_tseg1_nbt)                                                         | 0x770    |        4 | Auto-extracted signal tseg1_nbt from prescaler.vhd                             |
+| can_bus.[`prescaler_tseg2_nbt`](#prescaler_tseg2_nbt)                                                         | 0x774    |        4 | Auto-extracted signal tseg2_nbt from prescaler.vhd                             |
+| can_bus.[`prescaler_brp_nbt`](#prescaler_brp_nbt)                                                             | 0x778    |        4 | Auto-extracted signal brp_nbt from prescaler.vhd                               |
+| can_bus.[`prescaler_sjw_nbt`](#prescaler_sjw_nbt)                                                             | 0x77c    |        4 | Auto-extracted signal sjw_nbt from prescaler.vhd                               |
+| can_bus.[`prescaler_tseg1_dbt`](#prescaler_tseg1_dbt)                                                         | 0x780    |        4 | Auto-extracted signal tseg1_dbt from prescaler.vhd                             |
+| can_bus.[`prescaler_tseg2_dbt`](#prescaler_tseg2_dbt)                                                         | 0x784    |        4 | Auto-extracted signal tseg2_dbt from prescaler.vhd                             |
+| can_bus.[`prescaler_brp_dbt`](#prescaler_brp_dbt)                                                             | 0x788    |        4 | Auto-extracted signal brp_dbt from prescaler.vhd                               |
+| can_bus.[`prescaler_sjw_dbt`](#prescaler_sjw_dbt)                                                             | 0x78c    |        4 | Auto-extracted signal sjw_dbt from prescaler.vhd                               |
+| can_bus.[`prescaler_segment_end`](#prescaler_segment_end)                                                     | 0x790    |        4 | Auto-extracted signal segment_end from prescaler.vhd                           |
+| can_bus.[`prescaler_h_sync_valid`](#prescaler_h_sync_valid)                                                   | 0x794    |        4 | Auto-extracted signal h_sync_valid from prescaler.vhd                          |
+| can_bus.[`prescaler_is_tseg1`](#prescaler_is_tseg1)                                                           | 0x798    |        4 | Auto-extracted signal is_tseg1 from prescaler.vhd                              |
+| can_bus.[`prescaler_is_tseg2`](#prescaler_is_tseg2)                                                           | 0x79c    |        4 | Auto-extracted signal is_tseg2 from prescaler.vhd                              |
+| can_bus.[`prescaler_resync_edge_valid`](#prescaler_resync_edge_valid)                                         | 0x7a0    |        4 | Auto-extracted signal resync_edge_valid from prescaler.vhd                     |
+| can_bus.[`prescaler_h_sync_edge_valid`](#prescaler_h_sync_edge_valid)                                         | 0x7a4    |        4 | Auto-extracted signal h_sync_edge_valid from prescaler.vhd                     |
+| can_bus.[`prescaler_segm_counter_nbt`](#prescaler_segm_counter_nbt)                                           | 0x7a8    |        4 | Auto-extracted signal segm_counter_nbt from prescaler.vhd                      |
+| can_bus.[`prescaler_segm_counter_dbt`](#prescaler_segm_counter_dbt)                                           | 0x7ac    |        4 | Auto-extracted signal segm_counter_dbt from prescaler.vhd                      |
+| can_bus.[`prescaler_exit_segm_req_nbt`](#prescaler_exit_segm_req_nbt)                                         | 0x7b0    |        4 | Auto-extracted signal exit_segm_req_nbt from prescaler.vhd                     |
+| can_bus.[`prescaler_exit_segm_req_dbt`](#prescaler_exit_segm_req_dbt)                                         | 0x7b4    |        4 | Auto-extracted signal exit_segm_req_dbt from prescaler.vhd                     |
+| can_bus.[`prescaler_tq_edge_nbt`](#prescaler_tq_edge_nbt)                                                     | 0x7b8    |        4 | Auto-extracted signal tq_edge_nbt from prescaler.vhd                           |
+| can_bus.[`prescaler_tq_edge_dbt`](#prescaler_tq_edge_dbt)                                                     | 0x7bc    |        4 | Auto-extracted signal tq_edge_dbt from prescaler.vhd                           |
+| can_bus.[`prescaler_rx_trig_req`](#prescaler_rx_trig_req)                                                     | 0x7c0    |        4 | Auto-extracted signal rx_trig_req from prescaler.vhd                           |
+| can_bus.[`prescaler_tx_trig_req`](#prescaler_tx_trig_req)                                                     | 0x7c4    |        4 | Auto-extracted signal tx_trig_req from prescaler.vhd                           |
+| can_bus.[`prescaler_start_edge`](#prescaler_start_edge)                                                       | 0x7c8    |        4 | Auto-extracted signal start_edge from prescaler.vhd                            |
+| can_bus.[`prescaler_bt_ctr_clear`](#prescaler_bt_ctr_clear)                                                   | 0x7cc    |        4 | Auto-extracted signal bt_ctr_clear from prescaler.vhd                          |
+| can_bus.[`priority_decoder_l0_valid`](#priority_decoder_l0_valid)                                             | 0x7d0    |        4 | Auto-extracted signal l0_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l1_valid`](#priority_decoder_l1_valid)                                             | 0x7d4    |        4 | Auto-extracted signal l1_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l1_winner`](#priority_decoder_l1_winner)                                           | 0x7d8    |        4 | Auto-extracted signal l1_winner from priority_decoder.vhd                      |
+| can_bus.[`priority_decoder_l2_valid`](#priority_decoder_l2_valid)                                             | 0x7dc    |        4 | Auto-extracted signal l2_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l2_winner`](#priority_decoder_l2_winner)                                           | 0x7e0    |        4 | Auto-extracted signal l2_winner from priority_decoder.vhd                      |
+| can_bus.[`priority_decoder_l3_valid`](#priority_decoder_l3_valid)                                             | 0x7e4    |        4 | Auto-extracted signal l3_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l3_winner`](#priority_decoder_l3_winner)                                           | 0x7e8    |        4 | Auto-extracted signal l3_winner from priority_decoder.vhd                      |
+| can_bus.[`protocol_control_drv_can_fd_ena`](#protocol_control_drv_can_fd_ena)                                 | 0x7ec    |        4 | Auto-extracted signal drv_can_fd_ena from protocol_control.vhd                 |
+| can_bus.[`protocol_control_drv_bus_mon_ena`](#protocol_control_drv_bus_mon_ena)                               | 0x7f0    |        4 | Auto-extracted signal drv_bus_mon_ena from protocol_control.vhd                |
+| can_bus.[`protocol_control_drv_retr_lim_ena`](#protocol_control_drv_retr_lim_ena)                             | 0x7f4    |        4 | Auto-extracted signal drv_retr_lim_ena from protocol_control.vhd               |
+| can_bus.[`protocol_control_drv_retr_th`](#protocol_control_drv_retr_th)                                       | 0x7f8    |        4 | Auto-extracted signal drv_retr_th from protocol_control.vhd                    |
+| can_bus.[`protocol_control_drv_self_test_ena`](#protocol_control_drv_self_test_ena)                           | 0x7fc    |        4 | Auto-extracted signal drv_self_test_ena from protocol_control.vhd              |
+| can_bus.[`protocol_control_drv_ack_forb`](#protocol_control_drv_ack_forb)                                     | 0x800    |        4 | Auto-extracted signal drv_ack_forb from protocol_control.vhd                   |
+| can_bus.[`protocol_control_drv_ena`](#protocol_control_drv_ena)                                               | 0x804    |        4 | Auto-extracted signal drv_ena from protocol_control.vhd                        |
+| can_bus.[`protocol_control_drv_fd_type`](#protocol_control_drv_fd_type)                                       | 0x808    |        4 | Auto-extracted signal drv_fd_type from protocol_control.vhd                    |
+| can_bus.[`protocol_control_drv_int_loopback_ena`](#protocol_control_drv_int_loopback_ena)                     | 0x80c    |        4 | Auto-extracted signal drv_int_loopback_ena from protocol_control.vhd           |
+| can_bus.[`protocol_control_drv_bus_off_reset`](#protocol_control_drv_bus_off_reset)                           | 0x810    |        4 | Auto-extracted signal drv_bus_off_reset from protocol_control.vhd              |
+| can_bus.[`protocol_control_drv_ssp_delay_select`](#protocol_control_drv_ssp_delay_select)                     | 0x814    |        4 | Auto-extracted signal drv_ssp_delay_select from protocol_control.vhd           |
+| can_bus.[`protocol_control_drv_pex`](#protocol_control_drv_pex)                                               | 0x818    |        4 | Auto-extracted signal drv_pex from protocol_control.vhd                        |
+| can_bus.[`protocol_control_drv_cpexs`](#protocol_control_drv_cpexs)                                           | 0x81c    |        4 | Auto-extracted signal drv_cpexs from protocol_control.vhd                      |
+| can_bus.[`protocol_control_tran_word_swapped`](#protocol_control_tran_word_swapped)                           | 0x820    |        4 | Auto-extracted signal tran_word_swapped from protocol_control.vhd              |
+| can_bus.[`protocol_control_err_frm_req`](#protocol_control_err_frm_req)                                       | 0x824    |        4 | Auto-extracted signal err_frm_req from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_load_base_id`](#protocol_control_tx_load_base_id)                               | 0x828    |        4 | Auto-extracted signal tx_load_base_id from protocol_control.vhd                |
+| can_bus.[`protocol_control_tx_load_ext_id`](#protocol_control_tx_load_ext_id)                                 | 0x82c    |        4 | Auto-extracted signal tx_load_ext_id from protocol_control.vhd                 |
+| can_bus.[`protocol_control_tx_load_dlc`](#protocol_control_tx_load_dlc)                                       | 0x830    |        4 | Auto-extracted signal tx_load_dlc from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_load_data_word`](#protocol_control_tx_load_data_word)                           | 0x834    |        4 | Auto-extracted signal tx_load_data_word from protocol_control.vhd              |
+| can_bus.[`protocol_control_tx_load_stuff_count`](#protocol_control_tx_load_stuff_count)                       | 0x838    |        4 | Auto-extracted signal tx_load_stuff_count from protocol_control.vhd            |
+| can_bus.[`protocol_control_tx_load_crc`](#protocol_control_tx_load_crc)                                       | 0x83c    |        4 | Auto-extracted signal tx_load_crc from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_shift_ena`](#protocol_control_tx_shift_ena)                                     | 0x840    |        4 | Auto-extracted signal tx_shift_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_tx_dominant`](#protocol_control_tx_dominant)                                       | 0x844    |        4 | Auto-extracted signal tx_dominant from protocol_control.vhd                    |
+| can_bus.[`protocol_control_rx_clear`](#protocol_control_rx_clear)                                             | 0x848    |        4 | Auto-extracted signal rx_clear from protocol_control.vhd                       |
+| can_bus.[`protocol_control_rx_store_base_id`](#protocol_control_rx_store_base_id)                             | 0x84c    |        4 | Auto-extracted signal rx_store_base_id from protocol_control.vhd               |
+| can_bus.[`protocol_control_rx_store_ext_id`](#protocol_control_rx_store_ext_id)                               | 0x850    |        4 | Auto-extracted signal rx_store_ext_id from protocol_control.vhd                |
+| can_bus.[`protocol_control_rx_store_ide`](#protocol_control_rx_store_ide)                                     | 0x854    |        4 | Auto-extracted signal rx_store_ide from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_rtr`](#protocol_control_rx_store_rtr)                                     | 0x858    |        4 | Auto-extracted signal rx_store_rtr from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_edl`](#protocol_control_rx_store_edl)                                     | 0x85c    |        4 | Auto-extracted signal rx_store_edl from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_dlc`](#protocol_control_rx_store_dlc)                                     | 0x860    |        4 | Auto-extracted signal rx_store_dlc from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_esi`](#protocol_control_rx_store_esi)                                     | 0x864    |        4 | Auto-extracted signal rx_store_esi from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_brs`](#protocol_control_rx_store_brs)                                     | 0x868    |        4 | Auto-extracted signal rx_store_brs from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_stuff_count`](#protocol_control_rx_store_stuff_count)                     | 0x86c    |        4 | Auto-extracted signal rx_store_stuff_count from protocol_control.vhd           |
+| can_bus.[`protocol_control_rx_shift_ena`](#protocol_control_rx_shift_ena)                                     | 0x870    |        4 | Auto-extracted signal rx_shift_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_shift_in_sel`](#protocol_control_rx_shift_in_sel)                               | 0x874    |        4 | Auto-extracted signal rx_shift_in_sel from protocol_control.vhd                |
+| can_bus.[`protocol_control_rec_is_rtr_i`](#protocol_control_rec_is_rtr_i)                                     | 0x878    |        4 | Auto-extracted signal rec_is_rtr_i from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rec_dlc_d`](#protocol_control_rec_dlc_d)                                           | 0x87c    |        4 | Auto-extracted signal rec_dlc_d from protocol_control.vhd                      |
+| can_bus.[`protocol_control_rec_dlc_q`](#protocol_control_rec_dlc_q)                                           | 0x880    |        4 | Auto-extracted signal rec_dlc_q from protocol_control.vhd                      |
+| can_bus.[`protocol_control_rec_frame_type_i`](#protocol_control_rec_frame_type_i)                             | 0x884    |        4 | Auto-extracted signal rec_frame_type_i from protocol_control.vhd               |
+| can_bus.[`protocol_control_ctrl_ctr_pload`](#protocol_control_ctrl_ctr_pload)                                 | 0x888    |        4 | Auto-extracted signal ctrl_ctr_pload from protocol_control.vhd                 |
+| can_bus.[`protocol_control_ctrl_ctr_pload_val`](#protocol_control_ctrl_ctr_pload_val)                         | 0x88c    |        4 | Auto-extracted signal ctrl_ctr_pload_val from protocol_control.vhd             |
+| can_bus.[`protocol_control_ctrl_ctr_ena`](#protocol_control_ctrl_ctr_ena)                                     | 0x890    |        4 | Auto-extracted signal ctrl_ctr_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_ctrl_ctr_zero`](#protocol_control_ctrl_ctr_zero)                                   | 0x894    |        4 | Auto-extracted signal ctrl_ctr_zero from protocol_control.vhd                  |
+| can_bus.[`protocol_control_ctrl_ctr_one`](#protocol_control_ctrl_ctr_one)                                     | 0x898    |        4 | Auto-extracted signal ctrl_ctr_one from protocol_control.vhd                   |
+| can_bus.[`protocol_control_ctrl_counted_byte`](#protocol_control_ctrl_counted_byte)                           | 0x89c    |        4 | Auto-extracted signal ctrl_counted_byte from protocol_control.vhd              |
+| can_bus.[`protocol_control_ctrl_counted_byte_index`](#protocol_control_ctrl_counted_byte_index)               | 0x8a0    |        4 | Auto-extracted signal ctrl_counted_byte_index from protocol_control.vhd        |
+| can_bus.[`protocol_control_ctrl_ctr_mem_index`](#protocol_control_ctrl_ctr_mem_index)                         | 0x8a4    |        4 | Auto-extracted signal ctrl_ctr_mem_index from protocol_control.vhd             |
+| can_bus.[`protocol_control_compl_ctr_ena`](#protocol_control_compl_ctr_ena)                                   | 0x8a8    |        4 | Auto-extracted signal compl_ctr_ena from protocol_control.vhd                  |
+| can_bus.[`protocol_control_reinteg_ctr_clr`](#protocol_control_reinteg_ctr_clr)                               | 0x8ac    |        4 | Auto-extracted signal reinteg_ctr_clr from protocol_control.vhd                |
+| can_bus.[`protocol_control_reinteg_ctr_enable`](#protocol_control_reinteg_ctr_enable)                         | 0x8b0    |        4 | Auto-extracted signal reinteg_ctr_enable from protocol_control.vhd             |
+| can_bus.[`protocol_control_reinteg_ctr_expired`](#protocol_control_reinteg_ctr_expired)                       | 0x8b4    |        4 | Auto-extracted signal reinteg_ctr_expired from protocol_control.vhd            |
+| can_bus.[`protocol_control_retr_ctr_clear`](#protocol_control_retr_ctr_clear)                                 | 0x8b8    |        4 | Auto-extracted signal retr_ctr_clear from protocol_control.vhd                 |
+| can_bus.[`protocol_control_retr_ctr_add`](#protocol_control_retr_ctr_add)                                     | 0x8bc    |        4 | Auto-extracted signal retr_ctr_add from protocol_control.vhd                   |
+| can_bus.[`protocol_control_retr_limit_reached`](#protocol_control_retr_limit_reached)                         | 0x8c0    |        4 | Auto-extracted signal retr_limit_reached from protocol_control.vhd             |
+| can_bus.[`protocol_control_form_err_i`](#protocol_control_form_err_i)                                         | 0x8c4    |        4 | Auto-extracted signal form_err_i from protocol_control.vhd                     |
+| can_bus.[`protocol_control_ack_err_i`](#protocol_control_ack_err_i)                                           | 0x8c8    |        4 | Auto-extracted signal ack_err_i from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_check`](#protocol_control_crc_check)                                           | 0x8cc    |        4 | Auto-extracted signal crc_check from protocol_control.vhd                      |
+| can_bus.[`protocol_control_bit_err_arb`](#protocol_control_bit_err_arb)                                       | 0x8d0    |        4 | Auto-extracted signal bit_err_arb from protocol_control.vhd                    |
+| can_bus.[`protocol_control_crc_match`](#protocol_control_crc_match)                                           | 0x8d4    |        4 | Auto-extracted signal crc_match from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_err_i`](#protocol_control_crc_err_i)                                           | 0x8d8    |        4 | Auto-extracted signal crc_err_i from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_clear_match_flag`](#protocol_control_crc_clear_match_flag)                     | 0x8dc    |        4 | Auto-extracted signal crc_clear_match_flag from protocol_control.vhd           |
+| can_bus.[`protocol_control_crc_src`](#protocol_control_crc_src)                                               | 0x8e0    |        4 | Auto-extracted signal crc_src from protocol_control.vhd                        |
+| can_bus.[`protocol_control_err_pos`](#protocol_control_err_pos)                                               | 0x8e4    |        4 | Auto-extracted signal err_pos from protocol_control.vhd                        |
+| can_bus.[`protocol_control_is_arbitration_i`](#protocol_control_is_arbitration_i)                             | 0x8e8    |        4 | Auto-extracted signal is_arbitration_i from protocol_control.vhd               |
+| can_bus.[`protocol_control_bit_err_enable`](#protocol_control_bit_err_enable)                                 | 0x8ec    |        4 | Auto-extracted signal bit_err_enable from protocol_control.vhd                 |
+| can_bus.[`protocol_control_tx_data_nbs_i`](#protocol_control_tx_data_nbs_i)                                   | 0x8f0    |        4 | Auto-extracted signal tx_data_nbs_i from protocol_control.vhd                  |
+| can_bus.[`protocol_control_rx_crc`](#protocol_control_rx_crc)                                                 | 0x8f4    |        4 | Auto-extracted signal rx_crc from protocol_control.vhd                         |
+| can_bus.[`protocol_control_rx_stuff_count`](#protocol_control_rx_stuff_count)                                 | 0x8f8    |        4 | Auto-extracted signal rx_stuff_count from protocol_control.vhd                 |
+| can_bus.[`protocol_control_fixed_stuff_i`](#protocol_control_fixed_stuff_i)                                   | 0x8fc    |        4 | Auto-extracted signal fixed_stuff_i from protocol_control.vhd                  |
+| can_bus.[`protocol_control_arbitration_lost_i`](#protocol_control_arbitration_lost_i)                         | 0x900    |        4 | Auto-extracted signal arbitration_lost_i from protocol_control.vhd             |
+| can_bus.[`protocol_control_alc_id_field`](#protocol_control_alc_id_field)                                     | 0x904    |        4 | Auto-extracted signal alc_id_field from protocol_control.vhd                   |
+| can_bus.[`protocol_control_drv_rom_ena`](#protocol_control_drv_rom_ena)                                       | 0x908    |        4 | Auto-extracted signal drv_rom_ena from protocol_control.vhd                    |
+| can_bus.[`protocol_control_fsm_state_reg_ce`](#protocol_control_fsm_state_reg_ce)                             | 0x90c    |        4 | Auto-extracted signal state_reg_ce from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_no_data_transmitter`](#protocol_control_fsm_no_data_transmitter)               | 0x910    |        4 | Auto-extracted signal no_data_transmitter from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_no_data_receiver`](#protocol_control_fsm_no_data_receiver)                     | 0x914    |        4 | Auto-extracted signal no_data_receiver from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_no_data_field`](#protocol_control_fsm_no_data_field)                           | 0x918    |        4 | Auto-extracted signal no_data_field from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_ctrl_ctr_pload_i`](#protocol_control_fsm_ctrl_ctr_pload_i)                     | 0x91c    |        4 | Auto-extracted signal ctrl_ctr_pload_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_ctrl_ctr_pload_unaliged`](#protocol_control_fsm_ctrl_ctr_pload_unaliged)       | 0x920    |        4 | Auto-extracted signal ctrl_ctr_pload_unaliged from protocol_control_fsm.vhd    |
+| can_bus.[`protocol_control_fsm_crc_use_21`](#protocol_control_fsm_crc_use_21)                                 | 0x924    |        4 | Auto-extracted signal crc_use_21 from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_crc_use_17`](#protocol_control_fsm_crc_use_17)                                 | 0x928    |        4 | Auto-extracted signal crc_use_17 from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_crc_src_i`](#protocol_control_fsm_crc_src_i)                                   | 0x92c    |        4 | Auto-extracted signal crc_src_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_crc_length_i`](#protocol_control_fsm_crc_length_i)                             | 0x930    |        4 | Auto-extracted signal crc_length_i from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_tran_data_length`](#protocol_control_fsm_tran_data_length)                     | 0x934    |        4 | Auto-extracted signal tran_data_length from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_rec_data_length`](#protocol_control_fsm_rec_data_length)                       | 0x938    |        4 | Auto-extracted signal rec_data_length from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_rec_data_length_c`](#protocol_control_fsm_rec_data_length_c)                   | 0x93c    |        4 | Auto-extracted signal rec_data_length_c from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_data_length_c`](#protocol_control_fsm_data_length_c)                           | 0x940    |        4 | Auto-extracted signal data_length_c from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_data_length_shifted_c`](#protocol_control_fsm_data_length_shifted_c)           | 0x944    |        4 | Auto-extracted signal data_length_shifted_c from protocol_control_fsm.vhd      |
+| can_bus.[`protocol_control_fsm_data_length_bits_c`](#protocol_control_fsm_data_length_bits_c)                 | 0x948    |        4 | Auto-extracted signal data_length_bits_c from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_is_fd_frame`](#protocol_control_fsm_is_fd_frame)                               | 0x94c    |        4 | Auto-extracted signal is_fd_frame from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_frame_start`](#protocol_control_fsm_frame_start)                               | 0x950    |        4 | Auto-extracted signal frame_start from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_tx_frame_ready`](#protocol_control_fsm_tx_frame_ready)                         | 0x954    |        4 | Auto-extracted signal tx_frame_ready from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_ide_is_arbitration`](#protocol_control_fsm_ide_is_arbitration)                 | 0x958    |        4 | Auto-extracted signal ide_is_arbitration from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_arbitration_lost_condition`](#protocol_control_fsm_arbitration_lost_condition) | 0x95c    |        4 | Auto-extracted signal arbitration_lost_condition from protocol_control_fsm.vhd |
+| can_bus.[`protocol_control_fsm_arbitration_lost_i`](#protocol_control_fsm_arbitration_lost_i)                 | 0x960    |        4 | Auto-extracted signal arbitration_lost_i from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_tx_failed`](#protocol_control_fsm_tx_failed)                                   | 0x964    |        4 | Auto-extracted signal tx_failed from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_store_metadata_d`](#protocol_control_fsm_store_metadata_d)                     | 0x968    |        4 | Auto-extracted signal store_metadata_d from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_store_data_d`](#protocol_control_fsm_store_data_d)                             | 0x96c    |        4 | Auto-extracted signal store_data_d from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_rec_valid_d`](#protocol_control_fsm_rec_valid_d)                               | 0x970    |        4 | Auto-extracted signal rec_valid_d from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_rec_abort_d`](#protocol_control_fsm_rec_abort_d)                               | 0x974    |        4 | Auto-extracted signal rec_abort_d from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_go_to_suspend`](#protocol_control_fsm_go_to_suspend)                           | 0x978    |        4 | Auto-extracted signal go_to_suspend from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_go_to_stuff_count`](#protocol_control_fsm_go_to_stuff_count)                   | 0x97c    |        4 | Auto-extracted signal go_to_stuff_count from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_store_base_id_i`](#protocol_control_fsm_rx_store_base_id_i)                 | 0x980    |        4 | Auto-extracted signal rx_store_base_id_i from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_rx_store_ext_id_i`](#protocol_control_fsm_rx_store_ext_id_i)                   | 0x984    |        4 | Auto-extracted signal rx_store_ext_id_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_store_ide_i`](#protocol_control_fsm_rx_store_ide_i)                         | 0x988    |        4 | Auto-extracted signal rx_store_ide_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_rtr_i`](#protocol_control_fsm_rx_store_rtr_i)                         | 0x98c    |        4 | Auto-extracted signal rx_store_rtr_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_edl_i`](#protocol_control_fsm_rx_store_edl_i)                         | 0x990    |        4 | Auto-extracted signal rx_store_edl_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_dlc_i`](#protocol_control_fsm_rx_store_dlc_i)                         | 0x994    |        4 | Auto-extracted signal rx_store_dlc_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_esi_i`](#protocol_control_fsm_rx_store_esi_i)                         | 0x998    |        4 | Auto-extracted signal rx_store_esi_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_brs_i`](#protocol_control_fsm_rx_store_brs_i)                         | 0x99c    |        4 | Auto-extracted signal rx_store_brs_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_stuff_count_i`](#protocol_control_fsm_rx_store_stuff_count_i)         | 0x9a0    |        4 | Auto-extracted signal rx_store_stuff_count_i from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_rx_clear_i`](#protocol_control_fsm_rx_clear_i)                                 | 0x9a4    |        4 | Auto-extracted signal rx_clear_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_tx_load_base_id_i`](#protocol_control_fsm_tx_load_base_id_i)                   | 0x9a8    |        4 | Auto-extracted signal tx_load_base_id_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_load_ext_id_i`](#protocol_control_fsm_tx_load_ext_id_i)                     | 0x9ac    |        4 | Auto-extracted signal tx_load_ext_id_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_tx_load_dlc_i`](#protocol_control_fsm_tx_load_dlc_i)                           | 0x9b0    |        4 | Auto-extracted signal tx_load_dlc_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_tx_load_data_word_i`](#protocol_control_fsm_tx_load_data_word_i)               | 0x9b4    |        4 | Auto-extracted signal tx_load_data_word_i from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_tx_load_stuff_count_i`](#protocol_control_fsm_tx_load_stuff_count_i)           | 0x9b8    |        4 | Auto-extracted signal tx_load_stuff_count_i from protocol_control_fsm.vhd      |
+| can_bus.[`protocol_control_fsm_tx_load_crc_i`](#protocol_control_fsm_tx_load_crc_i)                           | 0x9bc    |        4 | Auto-extracted signal tx_load_crc_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_tx_shift_ena_i`](#protocol_control_fsm_tx_shift_ena_i)                         | 0x9c0    |        4 | Auto-extracted signal tx_shift_ena_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_form_err_i`](#protocol_control_fsm_form_err_i)                                 | 0x9c4    |        4 | Auto-extracted signal form_err_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_ack_err_i`](#protocol_control_fsm_ack_err_i)                                   | 0x9c8    |        4 | Auto-extracted signal ack_err_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_ack_err_flag`](#protocol_control_fsm_ack_err_flag)                             | 0x9cc    |        4 | Auto-extracted signal ack_err_flag from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_ack_err_flag_clr`](#protocol_control_fsm_ack_err_flag_clr)                     | 0x9d0    |        4 | Auto-extracted signal ack_err_flag_clr from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_crc_err_i`](#protocol_control_fsm_crc_err_i)                                   | 0x9d4    |        4 | Auto-extracted signal crc_err_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_bit_err_arb_i`](#protocol_control_fsm_bit_err_arb_i)                           | 0x9d8    |        4 | Auto-extracted signal bit_err_arb_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_switch_data`](#protocol_control_fsm_sp_control_switch_data)         | 0x9dc    |        4 | Auto-extracted signal sp_control_switch_data from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_sp_control_switch_nominal`](#protocol_control_fsm_sp_control_switch_nominal)   | 0x9e0    |        4 | Auto-extracted signal sp_control_switch_nominal from protocol_control_fsm.vhd  |
+| can_bus.[`protocol_control_fsm_switch_to_ssp`](#protocol_control_fsm_switch_to_ssp)                           | 0x9e4    |        4 | Auto-extracted signal switch_to_ssp from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_ce`](#protocol_control_fsm_sp_control_ce)                           | 0x9e8    |        4 | Auto-extracted signal sp_control_ce from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_d`](#protocol_control_fsm_sp_control_d)                             | 0x9ec    |        4 | Auto-extracted signal sp_control_d from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_sp_control_q_i`](#protocol_control_fsm_sp_control_q_i)                         | 0x9f0    |        4 | Auto-extracted signal sp_control_q_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_ssp_reset_i`](#protocol_control_fsm_ssp_reset_i)                               | 0x9f4    |        4 | Auto-extracted signal ssp_reset_i from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_sync_control_d`](#protocol_control_fsm_sync_control_d)                         | 0x9f8    |        4 | Auto-extracted signal sync_control_d from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_sync_control_q`](#protocol_control_fsm_sync_control_q)                         | 0x9fc    |        4 | Auto-extracted signal sync_control_q from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_perform_hsync`](#protocol_control_fsm_perform_hsync)                           | 0xa00    |        4 | Auto-extracted signal perform_hsync from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_primary_err_i`](#protocol_control_fsm_primary_err_i)                           | 0xa04    |        4 | Auto-extracted signal primary_err_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_err_delim_late_i`](#protocol_control_fsm_err_delim_late_i)                     | 0xa08    |        4 | Auto-extracted signal err_delim_late_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_set_err_active_i`](#protocol_control_fsm_set_err_active_i)                     | 0xa0c    |        4 | Auto-extracted signal set_err_active_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_set_transmitter_i`](#protocol_control_fsm_set_transmitter_i)                   | 0xa10    |        4 | Auto-extracted signal set_transmitter_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_set_receiver_i`](#protocol_control_fsm_set_receiver_i)                         | 0xa14    |        4 | Auto-extracted signal set_receiver_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_set_idle_i`](#protocol_control_fsm_set_idle_i)                                 | 0xa18    |        4 | Auto-extracted signal set_idle_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_first_err_delim_d`](#protocol_control_fsm_first_err_delim_d)                   | 0xa1c    |        4 | Auto-extracted signal first_err_delim_d from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_first_err_delim_q`](#protocol_control_fsm_first_err_delim_q)                   | 0xa20    |        4 | Auto-extracted signal first_err_delim_q from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_stuff_enable_set`](#protocol_control_fsm_stuff_enable_set)                     | 0xa24    |        4 | Auto-extracted signal stuff_enable_set from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_stuff_enable_clear`](#protocol_control_fsm_stuff_enable_clear)                 | 0xa28    |        4 | Auto-extracted signal stuff_enable_clear from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_destuff_enable_set`](#protocol_control_fsm_destuff_enable_set)                 | 0xa2c    |        4 | Auto-extracted signal destuff_enable_set from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_destuff_enable_clear`](#protocol_control_fsm_destuff_enable_clear)             | 0xa30    |        4 | Auto-extracted signal destuff_enable_clear from protocol_control_fsm.vhd       |
+| can_bus.[`protocol_control_fsm_bit_err_disable`](#protocol_control_fsm_bit_err_disable)                       | 0xa34    |        4 | Auto-extracted signal bit_err_disable from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_bit_err_disable_receiver`](#protocol_control_fsm_bit_err_disable_receiver)     | 0xa38    |        4 | Auto-extracted signal bit_err_disable_receiver from protocol_control_fsm.vhd   |
+| can_bus.[`protocol_control_fsm_sof_pulse_i`](#protocol_control_fsm_sof_pulse_i)                               | 0xa3c    |        4 | Auto-extracted signal sof_pulse_i from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_compl_ctr_ena_i`](#protocol_control_fsm_compl_ctr_ena_i)                       | 0xa40    |        4 | Auto-extracted signal compl_ctr_ena_i from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_tick_state_reg`](#protocol_control_fsm_tick_state_reg)                         | 0xa44    |        4 | Auto-extracted signal tick_state_reg from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_br_shifted_i`](#protocol_control_fsm_br_shifted_i)                             | 0xa48    |        4 | Auto-extracted signal br_shifted_i from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_is_arbitration_i`](#protocol_control_fsm_is_arbitration_i)                     | 0xa4c    |        4 | Auto-extracted signal is_arbitration_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_crc_spec_enable_i`](#protocol_control_fsm_crc_spec_enable_i)                   | 0xa50    |        4 | Auto-extracted signal crc_spec_enable_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_load_init_vect_i`](#protocol_control_fsm_load_init_vect_i)                     | 0xa54    |        4 | Auto-extracted signal load_init_vect_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_drv_bus_off_reset_q`](#protocol_control_fsm_drv_bus_off_reset_q)               | 0xa58    |        4 | Auto-extracted signal drv_bus_off_reset_q from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_retr_ctr_clear_i`](#protocol_control_fsm_retr_ctr_clear_i)                     | 0xa5c    |        4 | Auto-extracted signal retr_ctr_clear_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_i`](#protocol_control_fsm_retr_ctr_add_i)                         | 0xa60    |        4 | Auto-extracted signal retr_ctr_add_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_decrement_rec_i`](#protocol_control_fsm_decrement_rec_i)                       | 0xa64    |        4 | Auto-extracted signal decrement_rec_i from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_block`](#protocol_control_fsm_retr_ctr_add_block)                 | 0xa68    |        4 | Auto-extracted signal retr_ctr_add_block from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_block_clr`](#protocol_control_fsm_retr_ctr_add_block_clr)         | 0xa6c    |        4 | Auto-extracted signal retr_ctr_add_block_clr from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_block_txtb_unlock`](#protocol_control_fsm_block_txtb_unlock)                   | 0xa70    |        4 | Auto-extracted signal block_txtb_unlock from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_frame_no_sof_d`](#protocol_control_fsm_tx_frame_no_sof_d)                   | 0xa74    |        4 | Auto-extracted signal tx_frame_no_sof_d from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_frame_no_sof_q`](#protocol_control_fsm_tx_frame_no_sof_q)                   | 0xa78    |        4 | Auto-extracted signal tx_frame_no_sof_q from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_ctrl_signal_upd`](#protocol_control_fsm_ctrl_signal_upd)                       | 0xa7c    |        4 | Auto-extracted signal ctrl_signal_upd from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_clr_bus_off_rst_flg`](#protocol_control_fsm_clr_bus_off_rst_flg)               | 0xa80    |        4 | Auto-extracted signal clr_bus_off_rst_flg from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_pex_on_fdf_enable`](#protocol_control_fsm_pex_on_fdf_enable)                   | 0xa84    |        4 | Auto-extracted signal pex_on_fdf_enable from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_pex_on_res_enable`](#protocol_control_fsm_pex_on_res_enable)                   | 0xa88    |        4 | Auto-extracted signal pex_on_res_enable from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_data_nbs_prev`](#protocol_control_fsm_rx_data_nbs_prev)                     | 0xa8c    |        4 | Auto-extracted signal rx_data_nbs_prev from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_pexs_set`](#protocol_control_fsm_pexs_set)                                     | 0xa90    |        4 | Auto-extracted signal pexs_set from protocol_control_fsm.vhd                   |
+| can_bus.[`protocol_control_fsm_tran_frame_type_i`](#protocol_control_fsm_tran_frame_type_i)                   | 0xa94    |        4 | Auto-extracted signal tran_frame_type_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_txtb_clk_en_d`](#protocol_control_fsm_txtb_clk_en_d)                           | 0xa98    |        4 | Auto-extracted signal txtb_clk_en_d from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_txtb_clk_en_q`](#protocol_control_fsm_txtb_clk_en_q)                           | 0xa9c    |        4 | Auto-extracted signal txtb_clk_en_q from protocol_control_fsm.vhd              |
+| can_bus.[`reintegration_counter_reinteg_ctr_ce`](#reintegration_counter_reinteg_ctr_ce)                       | 0xaa0    |        4 | Auto-extracted signal reinteg_ctr_ce from reintegration_counter.vhd            |
+| can_bus.[`retransmitt_counter_retr_ctr_ce`](#retransmitt_counter_retr_ctr_ce)                                 | 0xaa4    |        4 | Auto-extracted signal retr_ctr_ce from retransmitt_counter.vhd                 |
+| can_bus.[`rst_sync_rff`](#rst_sync_rff)                                                                       | 0xaa8    |        4 | Auto-extracted signal rff from rst_sync.vhd                                    |
+| can_bus.[`rx_buffer_drv_erase_rx`](#rx_buffer_drv_erase_rx)                                                   | 0xaac    |        4 | Auto-extracted signal drv_erase_rx from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_drv_read_start`](#rx_buffer_drv_read_start)                                               | 0xab0    |        4 | Auto-extracted signal drv_read_start from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_drv_clr_ovr`](#rx_buffer_drv_clr_ovr)                                                     | 0xab4    |        4 | Auto-extracted signal drv_clr_ovr from rx_buffer.vhd                           |
+| can_bus.[`rx_buffer_drv_rtsopt`](#rx_buffer_drv_rtsopt)                                                       | 0xab8    |        4 | Auto-extracted signal drv_rtsopt from rx_buffer.vhd                            |
+| can_bus.[`rx_buffer_read_pointer`](#rx_buffer_read_pointer)                                                   | 0xabc    |        4 | Auto-extracted signal read_pointer from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_read_pointer_inc_1`](#rx_buffer_read_pointer_inc_1)                                       | 0xac0    |        4 | Auto-extracted signal read_pointer_inc_1 from rx_buffer.vhd                    |
+| can_bus.[`rx_buffer_write_pointer`](#rx_buffer_write_pointer)                                                 | 0xac4    |        4 | Auto-extracted signal write_pointer from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_write_pointer_raw`](#rx_buffer_write_pointer_raw)                                         | 0xac8    |        4 | Auto-extracted signal write_pointer_raw from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_write_pointer_ts`](#rx_buffer_write_pointer_ts)                                           | 0xacc    |        4 | Auto-extracted signal write_pointer_ts from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_rx_mem_free_i`](#rx_buffer_rx_mem_free_i)                                                 | 0xad0    |        4 | Auto-extracted signal rx_mem_free_i from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_memory_write_data`](#rx_buffer_memory_write_data)                                         | 0xad4    |        4 | Auto-extracted signal memory_write_data from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_data_overrun_flg`](#rx_buffer_data_overrun_flg)                                           | 0xad8    |        4 | Auto-extracted signal data_overrun_flg from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_data_overrun_i`](#rx_buffer_data_overrun_i)                                               | 0xadc    |        4 | Auto-extracted signal data_overrun_i from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_overrun_condition`](#rx_buffer_overrun_condition)                                         | 0xae0    |        4 | Auto-extracted signal overrun_condition from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_rx_empty_i`](#rx_buffer_rx_empty_i)                                                       | 0xae4    |        4 | Auto-extracted signal rx_empty_i from rx_buffer.vhd                            |
+| can_bus.[`rx_buffer_is_free_word`](#rx_buffer_is_free_word)                                                   | 0xae8    |        4 | Auto-extracted signal is_free_word from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_commit_rx_frame`](#rx_buffer_commit_rx_frame)                                             | 0xaec    |        4 | Auto-extracted signal commit_rx_frame from rx_buffer.vhd                       |
+| can_bus.[`rx_buffer_commit_overrun_abort`](#rx_buffer_commit_overrun_abort)                                   | 0xaf0    |        4 | Auto-extracted signal commit_overrun_abort from rx_buffer.vhd                  |
+| can_bus.[`rx_buffer_read_increment`](#rx_buffer_read_increment)                                               | 0xaf4    |        4 | Auto-extracted signal read_increment from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_write_raw_OK`](#rx_buffer_write_raw_ok)                                                   | 0xaf8    |        4 | Auto-extracted signal write_raw_OK from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_write_raw_intent`](#rx_buffer_write_raw_intent)                                           | 0xafc    |        4 | Auto-extracted signal write_raw_intent from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_write_ts`](#rx_buffer_write_ts)                                                           | 0xb00    |        4 | Auto-extracted signal write_ts from rx_buffer.vhd                              |
+| can_bus.[`rx_buffer_stored_ts`](#rx_buffer_stored_ts)                                                         | 0xb04    |        4 | Auto-extracted signal stored_ts from rx_buffer.vhd                             |
+| can_bus.[`rx_buffer_data_selector`](#rx_buffer_data_selector)                                                 | 0xb08    |        4 | Auto-extracted signal data_selector from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_store_ts_wr_ptr`](#rx_buffer_store_ts_wr_ptr)                                             | 0xb0c    |        4 | Auto-extracted signal store_ts_wr_ptr from rx_buffer.vhd                       |
+| can_bus.[`rx_buffer_inc_ts_wr_ptr`](#rx_buffer_inc_ts_wr_ptr)                                                 | 0xb10    |        4 | Auto-extracted signal inc_ts_wr_ptr from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_reset_overrun_flag`](#rx_buffer_reset_overrun_flag)                                       | 0xb14    |        4 | Auto-extracted signal reset_overrun_flag from rx_buffer.vhd                    |
+| can_bus.[`rx_buffer_frame_form_w`](#rx_buffer_frame_form_w)                                                   | 0xb18    |        4 | Auto-extracted signal frame_form_w from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_timestamp_capture`](#rx_buffer_timestamp_capture)                                         | 0xb1c    |        4 | Auto-extracted signal timestamp_capture from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_timestamp_capture_ce`](#rx_buffer_timestamp_capture_ce)                                   | 0xb20    |        4 | Auto-extracted signal timestamp_capture_ce from rx_buffer.vhd                  |
+| can_bus.[`rx_buffer_RAM_write`](#rx_buffer_ram_write)                                                         | 0xb24    |        4 | Auto-extracted signal RAM_write from rx_buffer.vhd                             |
+| can_bus.[`rx_buffer_RAM_data_out`](#rx_buffer_ram_data_out)                                                   | 0xb28    |        4 | Auto-extracted signal RAM_data_out from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_RAM_write_address`](#rx_buffer_ram_write_address)                                         | 0xb2c    |        4 | Auto-extracted signal RAM_write_address from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_RAM_read_address`](#rx_buffer_ram_read_address)                                           | 0xb30    |        4 | Auto-extracted signal RAM_read_address from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_rx_buf_res_n_d`](#rx_buffer_rx_buf_res_n_d)                                               | 0xb34    |        4 | Auto-extracted signal rx_buf_res_n_d from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_rx_buf_res_n_q`](#rx_buffer_rx_buf_res_n_q)                                               | 0xb38    |        4 | Auto-extracted signal rx_buf_res_n_q from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_rx_buf_res_n_q_scan`](#rx_buffer_rx_buf_res_n_q_scan)                                     | 0xb3c    |        4 | Auto-extracted signal rx_buf_res_n_q_scan from rx_buffer.vhd                   |
+| can_bus.[`rx_buffer_rx_buf_ram_clk_en`](#rx_buffer_rx_buf_ram_clk_en)                                         | 0xb40    |        4 | Auto-extracted signal rx_buf_ram_clk_en from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_clk_ram`](#rx_buffer_clk_ram)                                                             | 0xb44    |        4 | Auto-extracted signal clk_ram from rx_buffer.vhd                               |
+| can_bus.[`rx_buffer_fsm_rx_fsm_ce`](#rx_buffer_fsm_rx_fsm_ce)                                                 | 0xb48    |        4 | Auto-extracted signal rx_fsm_ce from rx_buffer_fsm.vhd                         |
+| can_bus.[`rx_buffer_fsm_cmd_join`](#rx_buffer_fsm_cmd_join)                                                   | 0xb4c    |        4 | Auto-extracted signal cmd_join from rx_buffer_fsm.vhd                          |
+| can_bus.[`rx_buffer_pointers_write_pointer_raw_ce`](#rx_buffer_pointers_write_pointer_raw_ce)                 | 0xb50    |        4 | Auto-extracted signal write_pointer_raw_ce from rx_buffer_pointers.vhd         |
+| can_bus.[`rx_buffer_pointers_write_pointer_ts_ce`](#rx_buffer_pointers_write_pointer_ts_ce)                   | 0xb54    |        4 | Auto-extracted signal write_pointer_ts_ce from rx_buffer_pointers.vhd          |
+| can_bus.[`rx_buffer_ram_port_a_address_i`](#rx_buffer_ram_port_a_address_i)                                   | 0xb58    |        4 | Auto-extracted signal port_a_address_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_a_write_i`](#rx_buffer_ram_port_a_write_i)                                       | 0xb5c    |        4 | Auto-extracted signal port_a_write_i from rx_buffer_ram.vhd                    |
+| can_bus.[`rx_buffer_ram_port_a_data_in_i`](#rx_buffer_ram_port_a_data_in_i)                                   | 0xb60    |        4 | Auto-extracted signal port_a_data_in_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_b_address_i`](#rx_buffer_ram_port_b_address_i)                                   | 0xb64    |        4 | Auto-extracted signal port_b_address_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_b_data_out_i`](#rx_buffer_ram_port_b_data_out_i)                                 | 0xb68    |        4 | Auto-extracted signal port_b_data_out_i from rx_buffer_ram.vhd                 |
+| can_bus.[`rx_buffer_ram_tst_ena`](#rx_buffer_ram_tst_ena)                                                     | 0xb6c    |        4 | Auto-extracted signal tst_ena from rx_buffer_ram.vhd                           |
+| can_bus.[`rx_buffer_ram_tst_addr`](#rx_buffer_ram_tst_addr)                                                   | 0xb70    |        4 | Auto-extracted signal tst_addr from rx_buffer_ram.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_d`](#rx_shift_reg_res_n_i_d)                                                   | 0xb74    |        4 | Auto-extracted signal res_n_i_d from rx_shift_reg.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_q`](#rx_shift_reg_res_n_i_q)                                                   | 0xb78    |        4 | Auto-extracted signal res_n_i_q from rx_shift_reg.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_q_scan`](#rx_shift_reg_res_n_i_q_scan)                                         | 0xb7c    |        4 | Auto-extracted signal res_n_i_q_scan from rx_shift_reg.vhd                     |
+| can_bus.[`rx_shift_reg_rx_shift_reg_q`](#rx_shift_reg_rx_shift_reg_q)                                         | 0xb80    |        4 | Auto-extracted signal rx_shift_reg_q from rx_shift_reg.vhd                     |
+| can_bus.[`rx_shift_reg_rx_shift_cmd`](#rx_shift_reg_rx_shift_cmd)                                             | 0xb84    |        4 | Auto-extracted signal rx_shift_cmd from rx_shift_reg.vhd                       |
+| can_bus.[`rx_shift_reg_rx_shift_in_sel_demuxed`](#rx_shift_reg_rx_shift_in_sel_demuxed)                       | 0xb88    |        4 | Auto-extracted signal rx_shift_in_sel_demuxed from rx_shift_reg.vhd            |
+| can_bus.[`rx_shift_reg_rec_is_rtr_i`](#rx_shift_reg_rec_is_rtr_i)                                             | 0xb8c    |        4 | Auto-extracted signal rec_is_rtr_i from rx_shift_reg.vhd                       |
+| can_bus.[`rx_shift_reg_rec_frame_type_i`](#rx_shift_reg_rec_frame_type_i)                                     | 0xb90    |        4 | Auto-extracted signal rec_frame_type_i from rx_shift_reg.vhd                   |
+| can_bus.[`sample_mux_sample`](#sample_mux_sample)                                                             | 0xb94    |        4 | Auto-extracted signal sample from sample_mux.vhd                               |
+| can_bus.[`sample_mux_prev_sample_d`](#sample_mux_prev_sample_d)                                               | 0xb98    |        4 | Auto-extracted signal prev_sample_d from sample_mux.vhd                        |
+| can_bus.[`sample_mux_prev_sample_q`](#sample_mux_prev_sample_q)                                               | 0xb9c    |        4 | Auto-extracted signal prev_sample_q from sample_mux.vhd                        |
+| can_bus.[`segment_end_detector_req_input`](#segment_end_detector_req_input)                                   | 0xba0    |        4 | Auto-extracted signal req_input from segment_end_detector.vhd                  |
+| can_bus.[`segment_end_detector_segm_end_req_capt_d`](#segment_end_detector_segm_end_req_capt_d)               | 0xba4    |        4 | Auto-extracted signal segm_end_req_capt_d from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_segm_end_req_capt_q`](#segment_end_detector_segm_end_req_capt_q)               | 0xba8    |        4 | Auto-extracted signal segm_end_req_capt_q from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_segm_end_req_capt_ce`](#segment_end_detector_segm_end_req_capt_ce)             | 0xbac    |        4 | Auto-extracted signal segm_end_req_capt_ce from segment_end_detector.vhd       |
+| can_bus.[`segment_end_detector_segm_end_req_capt_clr`](#segment_end_detector_segm_end_req_capt_clr)           | 0xbb0    |        4 | Auto-extracted signal segm_end_req_capt_clr from segment_end_detector.vhd      |
+| can_bus.[`segment_end_detector_segm_end_req_capt_dq`](#segment_end_detector_segm_end_req_capt_dq)             | 0xbb4    |        4 | Auto-extracted signal segm_end_req_capt_dq from segment_end_detector.vhd       |
+| can_bus.[`segment_end_detector_segm_end_nbt_valid`](#segment_end_detector_segm_end_nbt_valid)                 | 0xbb8    |        4 | Auto-extracted signal segm_end_nbt_valid from segment_end_detector.vhd         |
+| can_bus.[`segment_end_detector_segm_end_dbt_valid`](#segment_end_detector_segm_end_dbt_valid)                 | 0xbbc    |        4 | Auto-extracted signal segm_end_dbt_valid from segment_end_detector.vhd         |
+| can_bus.[`segment_end_detector_segm_end_nbt_dbt_valid`](#segment_end_detector_segm_end_nbt_dbt_valid)         | 0xbc0    |        4 | Auto-extracted signal segm_end_nbt_dbt_valid from segment_end_detector.vhd     |
+| can_bus.[`segment_end_detector_tseg1_end_req_valid`](#segment_end_detector_tseg1_end_req_valid)               | 0xbc4    |        4 | Auto-extracted signal tseg1_end_req_valid from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_tseg2_end_req_valid`](#segment_end_detector_tseg2_end_req_valid)               | 0xbc8    |        4 | Auto-extracted signal tseg2_end_req_valid from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_h_sync_valid_i`](#segment_end_detector_h_sync_valid_i)                         | 0xbcc    |        4 | Auto-extracted signal h_sync_valid_i from segment_end_detector.vhd             |
+| can_bus.[`segment_end_detector_segment_end_i`](#segment_end_detector_segment_end_i)                           | 0xbd0    |        4 | Auto-extracted signal segment_end_i from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_nbt_tq_active`](#segment_end_detector_nbt_tq_active)                           | 0xbd4    |        4 | Auto-extracted signal nbt_tq_active from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_dbt_tq_active`](#segment_end_detector_dbt_tq_active)                           | 0xbd8    |        4 | Auto-extracted signal dbt_tq_active from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_bt_ctr_clear_i`](#segment_end_detector_bt_ctr_clear_i)                         | 0xbdc    |        4 | Auto-extracted signal bt_ctr_clear_i from segment_end_detector.vhd             |
+| can_bus.[`shift_reg_shift_regs`](#shift_reg_shift_regs)                                                       | 0xbe0    |        4 | Auto-extracted signal shift_regs from shift_reg.vhd                            |
+| can_bus.[`shift_reg_next_shift_reg_val`](#shift_reg_next_shift_reg_val)                                       | 0xbe4    |        4 | Auto-extracted signal next_shift_reg_val from shift_reg.vhd                    |
+| can_bus.[`shift_reg_byte_shift_reg_in`](#shift_reg_byte_shift_reg_in)                                         | 0xbe8    |        4 | Auto-extracted signal shift_reg_in from shift_reg_byte.vhd                     |
+| can_bus.[`shift_reg_preload_shift_regs`](#shift_reg_preload_shift_regs)                                       | 0xbec    |        4 | Auto-extracted signal shift_regs from shift_reg_preload.vhd                    |
+| can_bus.[`shift_reg_preload_next_shift_reg_val`](#shift_reg_preload_next_shift_reg_val)                       | 0xbf0    |        4 | Auto-extracted signal next_shift_reg_val from shift_reg_preload.vhd            |
+| can_bus.[`sig_sync_rff`](#sig_sync_rff)                                                                       | 0xbf4    |        4 | Auto-extracted signal rff from sig_sync.vhd                                    |
+| can_bus.[`ssp_generator_btmc_d`](#ssp_generator_btmc_d)                                                       | 0xbf8    |        4 | Auto-extracted signal btmc_d from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_btmc_q`](#ssp_generator_btmc_q)                                                       | 0xbfc    |        4 | Auto-extracted signal btmc_q from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_btmc_add`](#ssp_generator_btmc_add)                                                   | 0xc00    |        4 | Auto-extracted signal btmc_add from ssp_generator.vhd                          |
+| can_bus.[`ssp_generator_btmc_ce`](#ssp_generator_btmc_ce)                                                     | 0xc04    |        4 | Auto-extracted signal btmc_ce from ssp_generator.vhd                           |
+| can_bus.[`ssp_generator_btmc_meas_running_d`](#ssp_generator_btmc_meas_running_d)                             | 0xc08    |        4 | Auto-extracted signal btmc_meas_running_d from ssp_generator.vhd               |
+| can_bus.[`ssp_generator_btmc_meas_running_q`](#ssp_generator_btmc_meas_running_q)                             | 0xc0c    |        4 | Auto-extracted signal btmc_meas_running_q from ssp_generator.vhd               |
+| can_bus.[`ssp_generator_sspc_d`](#ssp_generator_sspc_d)                                                       | 0xc10    |        4 | Auto-extracted signal sspc_d from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_sspc_q`](#ssp_generator_sspc_q)                                                       | 0xc14    |        4 | Auto-extracted signal sspc_q from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_sspc_ce`](#ssp_generator_sspc_ce)                                                     | 0xc18    |        4 | Auto-extracted signal sspc_ce from ssp_generator.vhd                           |
+| can_bus.[`ssp_generator_sspc_expired`](#ssp_generator_sspc_expired)                                           | 0xc1c    |        4 | Auto-extracted signal sspc_expired from ssp_generator.vhd                      |
+| can_bus.[`ssp_generator_sspc_threshold`](#ssp_generator_sspc_threshold)                                       | 0xc20    |        4 | Auto-extracted signal sspc_threshold from ssp_generator.vhd                    |
+| can_bus.[`ssp_generator_sspc_add`](#ssp_generator_sspc_add)                                                   | 0xc24    |        4 | Auto-extracted signal sspc_add from ssp_generator.vhd                          |
+| can_bus.[`ssp_generator_first_ssp_d`](#ssp_generator_first_ssp_d)                                             | 0xc28    |        4 | Auto-extracted signal first_ssp_d from ssp_generator.vhd                       |
+| can_bus.[`ssp_generator_first_ssp_q`](#ssp_generator_first_ssp_q)                                             | 0xc2c    |        4 | Auto-extracted signal first_ssp_q from ssp_generator.vhd                       |
+| can_bus.[`ssp_generator_sspc_ena_d`](#ssp_generator_sspc_ena_d)                                               | 0xc30    |        4 | Auto-extracted signal sspc_ena_d from ssp_generator.vhd                        |
+| can_bus.[`ssp_generator_sspc_ena_q`](#ssp_generator_sspc_ena_q)                                               | 0xc34    |        4 | Auto-extracted signal sspc_ena_q from ssp_generator.vhd                        |
+| can_bus.[`ssp_generator_ssp_delay_padded`](#ssp_generator_ssp_delay_padded)                                   | 0xc38    |        4 | Auto-extracted signal ssp_delay_padded from ssp_generator.vhd                  |
+| can_bus.[`synchronisation_checker_resync_edge`](#synchronisation_checker_resync_edge)                         | 0xc3c    |        4 | Auto-extracted signal resync_edge from synchronisation_checker.vhd             |
+| can_bus.[`synchronisation_checker_h_sync_edge`](#synchronisation_checker_h_sync_edge)                         | 0xc40    |        4 | Auto-extracted signal h_sync_edge from synchronisation_checker.vhd             |
+| can_bus.[`synchronisation_checker_h_or_re_sync_edge`](#synchronisation_checker_h_or_re_sync_edge)             | 0xc44    |        4 | Auto-extracted signal h_or_re_sync_edge from synchronisation_checker.vhd       |
+| can_bus.[`synchronisation_checker_sync_flag`](#synchronisation_checker_sync_flag)                             | 0xc48    |        4 | Auto-extracted signal sync_flag from synchronisation_checker.vhd               |
+| can_bus.[`synchronisation_checker_sync_flag_ce`](#synchronisation_checker_sync_flag_ce)                       | 0xc4c    |        4 | Auto-extracted signal sync_flag_ce from synchronisation_checker.vhd            |
+| can_bus.[`synchronisation_checker_sync_flag_nxt`](#synchronisation_checker_sync_flag_nxt)                     | 0xc50    |        4 | Auto-extracted signal sync_flag_nxt from synchronisation_checker.vhd           |
+| can_bus.[`test_registers_reg_map_reg_sel`](#test_registers_reg_map_reg_sel)                                   | 0xc54    |        4 | Auto-extracted signal reg_sel from test_registers_reg_map.vhd                  |
+| can_bus.[`test_registers_reg_map_read_data_mux_in`](#test_registers_reg_map_read_data_mux_in)                 | 0xc58    |        4 | Auto-extracted signal read_data_mux_in from test_registers_reg_map.vhd         |
+| can_bus.[`test_registers_reg_map_read_data_mask_n`](#test_registers_reg_map_read_data_mask_n)                 | 0xc5c    |        4 | Auto-extracted signal read_data_mask_n from test_registers_reg_map.vhd         |
+| can_bus.[`test_registers_reg_map_read_mux_ena`](#test_registers_reg_map_read_mux_ena)                         | 0xc60    |        4 | Auto-extracted signal read_mux_ena from test_registers_reg_map.vhd             |
+| can_bus.[`trigger_generator_rx_trig_req_q`](#trigger_generator_rx_trig_req_q)                                 | 0xc64    |        4 | Auto-extracted signal rx_trig_req_q from trigger_generator.vhd                 |
+| can_bus.[`trigger_generator_tx_trig_req_flag_d`](#trigger_generator_tx_trig_req_flag_d)                       | 0xc68    |        4 | Auto-extracted signal tx_trig_req_flag_d from trigger_generator.vhd            |
+| can_bus.[`trigger_generator_tx_trig_req_flag_q`](#trigger_generator_tx_trig_req_flag_q)                       | 0xc6c    |        4 | Auto-extracted signal tx_trig_req_flag_q from trigger_generator.vhd            |
+| can_bus.[`trigger_generator_tx_trig_req_flag_dq`](#trigger_generator_tx_trig_req_flag_dq)                     | 0xc70    |        4 | Auto-extracted signal tx_trig_req_flag_dq from trigger_generator.vhd           |
+| can_bus.[`trigger_mux_tx_trigger_q`](#trigger_mux_tx_trigger_q)                                               | 0xc74    |        4 | Auto-extracted signal tx_trigger_q from trigger_mux.vhd                        |
+| can_bus.[`trv_delay_meas_trv_meas_progress_d`](#trv_delay_meas_trv_meas_progress_d)                           | 0xc78    |        4 | Auto-extracted signal trv_meas_progress_d from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_meas_progress_q`](#trv_delay_meas_trv_meas_progress_q)                           | 0xc7c    |        4 | Auto-extracted signal trv_meas_progress_q from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_meas_progress_del`](#trv_delay_meas_trv_meas_progress_del)                       | 0xc80    |        4 | Auto-extracted signal trv_meas_progress_del from trv_delay_meas.vhd            |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_q`](#trv_delay_meas_trv_delay_ctr_q)                                   | 0xc84    |        4 | Auto-extracted signal trv_delay_ctr_q from trv_delay_meas.vhd                  |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_d`](#trv_delay_meas_trv_delay_ctr_d)                                   | 0xc88    |        4 | Auto-extracted signal trv_delay_ctr_d from trv_delay_meas.vhd                  |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_add`](#trv_delay_meas_trv_delay_ctr_add)                               | 0xc8c    |        4 | Auto-extracted signal trv_delay_ctr_add from trv_delay_meas.vhd                |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_q_padded`](#trv_delay_meas_trv_delay_ctr_q_padded)                     | 0xc90    |        4 | Auto-extracted signal trv_delay_ctr_q_padded from trv_delay_meas.vhd           |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_d`](#trv_delay_meas_trv_delay_ctr_rst_d)                           | 0xc94    |        4 | Auto-extracted signal trv_delay_ctr_rst_d from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_q`](#trv_delay_meas_trv_delay_ctr_rst_q)                           | 0xc98    |        4 | Auto-extracted signal trv_delay_ctr_rst_q from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_q_scan`](#trv_delay_meas_trv_delay_ctr_rst_q_scan)                 | 0xc9c    |        4 | Auto-extracted signal trv_delay_ctr_rst_q_scan from trv_delay_meas.vhd         |
+| can_bus.[`trv_delay_meas_ssp_shadow_ce`](#trv_delay_meas_ssp_shadow_ce)                                       | 0xca0    |        4 | Auto-extracted signal ssp_shadow_ce from trv_delay_meas.vhd                    |
+| can_bus.[`trv_delay_meas_ssp_delay_raw`](#trv_delay_meas_ssp_delay_raw)                                       | 0xca4    |        4 | Auto-extracted signal ssp_delay_raw from trv_delay_meas.vhd                    |
+| can_bus.[`trv_delay_meas_ssp_delay_saturated`](#trv_delay_meas_ssp_delay_saturated)                           | 0xca8    |        4 | Auto-extracted signal ssp_delay_saturated from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_sum`](#trv_delay_meas_trv_delay_sum)                                       | 0xcac    |        4 | Auto-extracted signal trv_delay_sum from trv_delay_meas.vhd                    |
+| can_bus.[`tx_arbitrator_select_buf_avail`](#tx_arbitrator_select_buf_avail)                                   | 0xcb0    |        4 | Auto-extracted signal select_buf_avail from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_txtb_selected_input`](#tx_arbitrator_txtb_selected_input)                             | 0xcb4    |        4 | Auto-extracted signal txtb_selected_input from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_txtb_timestamp`](#tx_arbitrator_txtb_timestamp)                                       | 0xcb8    |        4 | Auto-extracted signal txtb_timestamp from tx_arbitrator.vhd                    |
+| can_bus.[`tx_arbitrator_timestamp_valid`](#tx_arbitrator_timestamp_valid)                                     | 0xcbc    |        4 | Auto-extracted signal timestamp_valid from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_select_index_changed`](#tx_arbitrator_select_index_changed)                           | 0xcc0    |        4 | Auto-extracted signal select_index_changed from tx_arbitrator.vhd              |
+| can_bus.[`tx_arbitrator_validated_buffer`](#tx_arbitrator_validated_buffer)                                   | 0xcc4    |        4 | Auto-extracted signal validated_buffer from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_ts_low_internal`](#tx_arbitrator_ts_low_internal)                                     | 0xcc8    |        4 | Auto-extracted signal ts_low_internal from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_tran_dlc_dbl_buf`](#tx_arbitrator_tran_dlc_dbl_buf)                                   | 0xccc    |        4 | Auto-extracted signal tran_dlc_dbl_buf from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_tran_is_rtr_dbl_buf`](#tx_arbitrator_tran_is_rtr_dbl_buf)                             | 0xcd0    |        4 | Auto-extracted signal tran_is_rtr_dbl_buf from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_ident_type_dbl_buf`](#tx_arbitrator_tran_ident_type_dbl_buf)                     | 0xcd4    |        4 | Auto-extracted signal tran_ident_type_dbl_buf from tx_arbitrator.vhd           |
+| can_bus.[`tx_arbitrator_tran_frame_type_dbl_buf`](#tx_arbitrator_tran_frame_type_dbl_buf)                     | 0xcd8    |        4 | Auto-extracted signal tran_frame_type_dbl_buf from tx_arbitrator.vhd           |
+| can_bus.[`tx_arbitrator_tran_brs_dbl_buf`](#tx_arbitrator_tran_brs_dbl_buf)                                   | 0xcdc    |        4 | Auto-extracted signal tran_brs_dbl_buf from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_tran_dlc_com`](#tx_arbitrator_tran_dlc_com)                                           | 0xce0    |        4 | Auto-extracted signal tran_dlc_com from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_tran_is_rtr_com`](#tx_arbitrator_tran_is_rtr_com)                                     | 0xce4    |        4 | Auto-extracted signal tran_is_rtr_com from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_tran_ident_type_com`](#tx_arbitrator_tran_ident_type_com)                             | 0xce8    |        4 | Auto-extracted signal tran_ident_type_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_frame_type_com`](#tx_arbitrator_tran_frame_type_com)                             | 0xcec    |        4 | Auto-extracted signal tran_frame_type_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_brs_com`](#tx_arbitrator_tran_brs_com)                                           | 0xcf0    |        4 | Auto-extracted signal tran_brs_com from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_tran_frame_valid_com`](#tx_arbitrator_tran_frame_valid_com)                           | 0xcf4    |        4 | Auto-extracted signal tran_frame_valid_com from tx_arbitrator.vhd              |
+| can_bus.[`tx_arbitrator_tran_identifier_com`](#tx_arbitrator_tran_identifier_com)                             | 0xcf8    |        4 | Auto-extracted signal tran_identifier_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_load_ts_lw_addr`](#tx_arbitrator_load_ts_lw_addr)                                     | 0xcfc    |        4 | Auto-extracted signal load_ts_lw_addr from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_load_ts_uw_addr`](#tx_arbitrator_load_ts_uw_addr)                                     | 0xd00    |        4 | Auto-extracted signal load_ts_uw_addr from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_load_ffmt_w_addr`](#tx_arbitrator_load_ffmt_w_addr)                                   | 0xd04    |        4 | Auto-extracted signal load_ffmt_w_addr from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_load_ident_w_addr`](#tx_arbitrator_load_ident_w_addr)                                 | 0xd08    |        4 | Auto-extracted signal load_ident_w_addr from tx_arbitrator.vhd                 |
+| can_bus.[`tx_arbitrator_store_ts_l_w`](#tx_arbitrator_store_ts_l_w)                                           | 0xd0c    |        4 | Auto-extracted signal store_ts_l_w from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_store_md_w`](#tx_arbitrator_store_md_w)                                               | 0xd10    |        4 | Auto-extracted signal store_md_w from tx_arbitrator.vhd                        |
+| can_bus.[`tx_arbitrator_store_ident_w`](#tx_arbitrator_store_ident_w)                                         | 0xd14    |        4 | Auto-extracted signal store_ident_w from tx_arbitrator.vhd                     |
+| can_bus.[`tx_arbitrator_buffer_md_w`](#tx_arbitrator_buffer_md_w)                                             | 0xd18    |        4 | Auto-extracted signal buffer_md_w from tx_arbitrator.vhd                       |
+| can_bus.[`tx_arbitrator_store_last_txtb_index`](#tx_arbitrator_store_last_txtb_index)                         | 0xd1c    |        4 | Auto-extracted signal store_last_txtb_index from tx_arbitrator.vhd             |
+| can_bus.[`tx_arbitrator_frame_valid_com_set`](#tx_arbitrator_frame_valid_com_set)                             | 0xd20    |        4 | Auto-extracted signal frame_valid_com_set from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_frame_valid_com_clear`](#tx_arbitrator_frame_valid_com_clear)                         | 0xd24    |        4 | Auto-extracted signal frame_valid_com_clear from tx_arbitrator.vhd             |
+| can_bus.[`tx_arbitrator_tx_arb_locked`](#tx_arbitrator_tx_arb_locked)                                         | 0xd28    |        4 | Auto-extracted signal tx_arb_locked from tx_arbitrator.vhd                     |
+| can_bus.[`tx_arbitrator_txtb_meta_clk_en`](#tx_arbitrator_txtb_meta_clk_en)                                   | 0xd2c    |        4 | Auto-extracted signal txtb_meta_clk_en from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_drv_tttm_ena`](#tx_arbitrator_drv_tttm_ena)                                           | 0xd30    |        4 | Auto-extracted signal drv_tttm_ena from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_fsm_tx_arb_fsm_ce`](#tx_arbitrator_fsm_tx_arb_fsm_ce)                                 | 0xd34    |        4 | Auto-extracted signal tx_arb_fsm_ce from tx_arbitrator_fsm.vhd                 |
+| can_bus.[`tx_arbitrator_fsm_fsm_wait_state_d`](#tx_arbitrator_fsm_fsm_wait_state_d)                           | 0xd38    |        4 | Auto-extracted signal fsm_wait_state_d from tx_arbitrator_fsm.vhd              |
+| can_bus.[`tx_arbitrator_fsm_fsm_wait_state_q`](#tx_arbitrator_fsm_fsm_wait_state_q)                           | 0xd3c    |        4 | Auto-extracted signal fsm_wait_state_q from tx_arbitrator_fsm.vhd              |
+| can_bus.[`tx_data_cache_tx_cache_mem`](#tx_data_cache_tx_cache_mem)                                           | 0xd40    |        4 | Auto-extracted signal tx_cache_mem from tx_data_cache.vhd                      |
+| can_bus.[`tx_shift_reg_tx_sr_output`](#tx_shift_reg_tx_sr_output)                                             | 0xd44    |        4 | Auto-extracted signal tx_sr_output from tx_shift_reg.vhd                       |
+| can_bus.[`tx_shift_reg_tx_sr_ce`](#tx_shift_reg_tx_sr_ce)                                                     | 0xd48    |        4 | Auto-extracted signal tx_sr_ce from tx_shift_reg.vhd                           |
+| can_bus.[`tx_shift_reg_tx_sr_pload`](#tx_shift_reg_tx_sr_pload)                                               | 0xd4c    |        4 | Auto-extracted signal tx_sr_pload from tx_shift_reg.vhd                        |
+| can_bus.[`tx_shift_reg_tx_sr_pload_val`](#tx_shift_reg_tx_sr_pload_val)                                       | 0xd50    |        4 | Auto-extracted signal tx_sr_pload_val from tx_shift_reg.vhd                    |
+| can_bus.[`tx_shift_reg_tx_base_id`](#tx_shift_reg_tx_base_id)                                                 | 0xd54    |        4 | Auto-extracted signal tx_base_id from tx_shift_reg.vhd                         |
+| can_bus.[`tx_shift_reg_tx_ext_id`](#tx_shift_reg_tx_ext_id)                                                   | 0xd58    |        4 | Auto-extracted signal tx_ext_id from tx_shift_reg.vhd                          |
+| can_bus.[`tx_shift_reg_tx_crc`](#tx_shift_reg_tx_crc)                                                         | 0xd5c    |        4 | Auto-extracted signal tx_crc from tx_shift_reg.vhd                             |
+| can_bus.[`tx_shift_reg_bst_ctr_grey`](#tx_shift_reg_bst_ctr_grey)                                             | 0xd60    |        4 | Auto-extracted signal bst_ctr_grey from tx_shift_reg.vhd                       |
+| can_bus.[`tx_shift_reg_bst_parity`](#tx_shift_reg_bst_parity)                                                 | 0xd64    |        4 | Auto-extracted signal bst_parity from tx_shift_reg.vhd                         |
+| can_bus.[`tx_shift_reg_stuff_count`](#tx_shift_reg_stuff_count)                                               | 0xd68    |        4 | Auto-extracted signal stuff_count from tx_shift_reg.vhd                        |
+| can_bus.[`txt_buffer_txtb_user_accessible`](#txt_buffer_txtb_user_accessible)                                 | 0xd6c    |        4 | Auto-extracted signal txtb_user_accessible from txt_buffer.vhd                 |
+| can_bus.[`txt_buffer_hw_cbs`](#txt_buffer_hw_cbs)                                                             | 0xd70    |        4 | Auto-extracted signal hw_cbs from txt_buffer.vhd                               |
+| can_bus.[`txt_buffer_sw_cbs`](#txt_buffer_sw_cbs)                                                             | 0xd74    |        4 | Auto-extracted signal sw_cbs from txt_buffer.vhd                               |
+| can_bus.[`txt_buffer_txtb_unmask_data_ram`](#txt_buffer_txtb_unmask_data_ram)                                 | 0xd78    |        4 | Auto-extracted signal txtb_unmask_data_ram from txt_buffer.vhd                 |
+| can_bus.[`txt_buffer_txtb_port_b_data_i`](#txt_buffer_txtb_port_b_data_i)                                     | 0xd7c    |        4 | Auto-extracted signal txtb_port_b_data_i from txt_buffer.vhd                   |
+| can_bus.[`txt_buffer_ram_write`](#txt_buffer_ram_write)                                                       | 0xd80    |        4 | Auto-extracted signal ram_write from txt_buffer.vhd                            |
+| can_bus.[`txt_buffer_ram_read_address`](#txt_buffer_ram_read_address)                                         | 0xd84    |        4 | Auto-extracted signal ram_read_address from txt_buffer.vhd                     |
+| can_bus.[`txt_buffer_txtb_ram_clk_en`](#txt_buffer_txtb_ram_clk_en)                                           | 0xd88    |        4 | Auto-extracted signal txtb_ram_clk_en from txt_buffer.vhd                      |
+| can_bus.[`txt_buffer_clk_ram`](#txt_buffer_clk_ram)                                                           | 0xd8c    |        4 | Auto-extracted signal clk_ram from txt_buffer.vhd                              |
+| can_bus.[`txt_buffer_fsm_abort_applied`](#txt_buffer_fsm_abort_applied)                                       | 0xd90    |        4 | Auto-extracted signal abort_applied from txt_buffer_fsm.vhd                    |
+| can_bus.[`txt_buffer_fsm_txt_fsm_ce`](#txt_buffer_fsm_txt_fsm_ce)                                             | 0xd94    |        4 | Auto-extracted signal txt_fsm_ce from txt_buffer_fsm.vhd                       |
+| can_bus.[`txt_buffer_fsm_go_to_failed`](#txt_buffer_fsm_go_to_failed)                                         | 0xd98    |        4 | Auto-extracted signal go_to_failed from txt_buffer_fsm.vhd                     |
+| can_bus.[`txt_buffer_fsm_transient_state`](#txt_buffer_fsm_transient_state)                                   | 0xd9c    |        4 | Auto-extracted signal transient_state from txt_buffer_fsm.vhd                  |
+| can_bus.[`txt_buffer_ram_port_a_address_i`](#txt_buffer_ram_port_a_address_i)                                 | 0xda0    |        4 | Auto-extracted signal port_a_address_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_a_write_i`](#txt_buffer_ram_port_a_write_i)                                     | 0xda4    |        4 | Auto-extracted signal port_a_write_i from txt_buffer_ram.vhd                   |
+| can_bus.[`txt_buffer_ram_port_a_data_in_i`](#txt_buffer_ram_port_a_data_in_i)                                 | 0xda8    |        4 | Auto-extracted signal port_a_data_in_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_b_address_i`](#txt_buffer_ram_port_b_address_i)                                 | 0xdac    |        4 | Auto-extracted signal port_b_address_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_b_data_out_i`](#txt_buffer_ram_port_b_data_out_i)                               | 0xdb0    |        4 | Auto-extracted signal port_b_data_out_i from txt_buffer_ram.vhd                |
+| can_bus.[`txt_buffer_ram_tst_ena`](#txt_buffer_ram_tst_ena)                                                   | 0xdb4    |        4 | Auto-extracted signal tst_ena from txt_buffer_ram.vhd                          |
+| can_bus.[`txt_buffer_ram_tst_addr`](#txt_buffer_ram_tst_addr)                                                 | 0xdb8    |        4 | Auto-extracted signal tst_addr from txt_buffer_ram.vhd                         |
+| can_bus.[`access_signaler_be_active`](#access_signaler_be_active)                                             | 0xdbc    |        4 | Auto-extracted signal be_active from access_signaler.vhd                       |
+| can_bus.[`access_signaler_access_in`](#access_signaler_access_in)                                             | 0xdc0    |        4 | Auto-extracted signal access_in from access_signaler.vhd                       |
+| can_bus.[`access_signaler_access_active`](#access_signaler_access_active)                                     | 0xdc4    |        4 | Auto-extracted signal access_active from access_signaler.vhd                   |
+| can_bus.[`access_signaler_access_active_reg`](#access_signaler_access_active_reg)                             | 0xdc8    |        4 | Auto-extracted signal access_active_reg from access_signaler.vhd               |
+| can_bus.[`address_decoder_addr_dec_i`](#address_decoder_addr_dec_i)                                           | 0xdcc    |        4 | Auto-extracted signal addr_dec_i from address_decoder.vhd                      |
+| can_bus.[`address_decoder_addr_dec_enabled_i`](#address_decoder_addr_dec_enabled_i)                           | 0xdd0    |        4 | Auto-extracted signal addr_dec_enabled_i from address_decoder.vhd              |
+
+## ahb_ifc_hsel_valid
+Auto-extracted signal hsel_valid from ahb_ifc.vhd
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_write_acc_d
+Auto-extracted signal write_acc_d from ahb_ifc.vhd
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_write_acc_q
+Auto-extracted signal write_acc_q from ahb_ifc.vhd
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_haddr_q
+Auto-extracted signal haddr_q from ahb_ifc.vhd
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_h_ready_raw
+Auto-extracted signal h_ready_raw from ahb_ifc.vhd
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_sbe_d
+Auto-extracted signal sbe_d from ahb_ifc.vhd
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_sbe_q
+Auto-extracted signal sbe_q from ahb_ifc.vhd
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_swr_i
+Auto-extracted signal swr_i from ahb_ifc.vhd
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_srd_i
+Auto-extracted signal srd_i from ahb_ifc.vhd
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_discard_stuff_bit
+Auto-extracted signal discard_stuff_bit from bit_destuffing.vhd
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_non_fix_to_fix_chng
+Auto-extracted signal non_fix_to_fix_chng from bit_destuffing.vhd
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_lvl_reached
+Auto-extracted signal stuff_lvl_reached from bit_destuffing.vhd
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_rule_violate
+Auto-extracted signal stuff_rule_violate from bit_destuffing.vhd
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_enable_prev
+Auto-extracted signal enable_prev from bit_destuffing.vhd
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_fixed_prev_q
+Auto-extracted signal fixed_prev_q from bit_destuffing.vhd
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_fixed_prev_d
+Auto-extracted signal fixed_prev_d from bit_destuffing.vhd
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_same_bits_erase
+Auto-extracted signal same_bits_erase from bit_destuffing.vhd
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_destuffed_q
+Auto-extracted signal destuffed_q from bit_destuffing.vhd
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_destuffed_d
+Auto-extracted signal destuffed_d from bit_destuffing.vhd
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_err_q
+Auto-extracted signal stuff_err_q from bit_destuffing.vhd
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_err_d
+Auto-extracted signal stuff_err_d from bit_destuffing.vhd
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_prev_val_q
+Auto-extracted signal prev_val_q from bit_destuffing.vhd
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_prev_val_d
+Auto-extracted signal prev_val_d from bit_destuffing.vhd
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_d
+Auto-extracted signal bit_err_d from bit_err_detector.vhd
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_q
+Auto-extracted signal bit_err_q from bit_err_detector.vhd
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_capt_d
+Auto-extracted signal bit_err_ssp_capt_d from bit_err_detector.vhd
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_capt_q
+Auto-extracted signal bit_err_ssp_capt_q from bit_err_detector.vhd
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_valid
+Auto-extracted signal bit_err_ssp_valid from bit_err_detector.vhd
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_condition
+Auto-extracted signal bit_err_ssp_condition from bit_err_detector.vhd
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_norm_valid
+Auto-extracted signal bit_err_norm_valid from bit_err_detector.vhd
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_filter_masked_input
+Auto-extracted signal masked_input from bit_filter.vhd
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_filter_masked_value
+Auto-extracted signal masked_value from bit_filter.vhd
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_sel_tseg1
+Auto-extracted signal sel_tseg1 from bit_segment_meter.vhd
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exp_seg_length_ce
+Auto-extracted signal exp_seg_length_ce from bit_segment_meter.vhd
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_mt_sjw
+Auto-extracted signal phase_err_mt_sjw from bit_segment_meter.vhd
+- Offset: `0x88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_eq_sjw
+Auto-extracted signal phase_err_eq_sjw from bit_segment_meter.vhd
+- Offset: `0x8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_ph2_immediate
+Auto-extracted signal exit_ph2_immediate from bit_segment_meter.vhd
+- Offset: `0x90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular
+Auto-extracted signal exit_segm_regular from bit_segment_meter.vhd
+- Offset: `0x94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular_tseg1
+Auto-extracted signal exit_segm_regular_tseg1 from bit_segment_meter.vhd
+- Offset: `0x98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular_tseg2
+Auto-extracted signal exit_segm_regular_tseg2 from bit_segment_meter.vhd
+- Offset: `0x9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_sjw_mt_zero
+Auto-extracted signal sjw_mt_zero from bit_segment_meter.vhd
+- Offset: `0xa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_use_basic_segm_length
+Auto-extracted signal use_basic_segm_length from bit_segment_meter.vhd
+- Offset: `0xa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_sjw_by_one
+Auto-extracted signal phase_err_sjw_by_one from bit_segment_meter.vhd
+- Offset: `0xa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_shorten_tseg1_after_tseg2
+Auto-extracted signal shorten_tseg1_after_tseg2 from bit_segment_meter.vhd
+- Offset: `0xac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_i
+Auto-extracted signal data_out_i from bit_stuffing.vhd
+- Offset: `0xb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_halt_q
+Auto-extracted signal data_halt_q from bit_stuffing.vhd
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_halt_d
+Auto-extracted signal data_halt_d from bit_stuffing.vhd
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_fixed_reg_q
+Auto-extracted signal fixed_reg_q from bit_stuffing.vhd
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_fixed_reg_d
+Auto-extracted signal fixed_reg_d from bit_stuffing.vhd
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_enable_prev
+Auto-extracted signal enable_prev from bit_stuffing.vhd
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_non_fix_to_fix_chng
+Auto-extracted signal non_fix_to_fix_chng from bit_stuffing.vhd
+- Offset: `0xc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_stuff_lvl_reached
+Auto-extracted signal stuff_lvl_reached from bit_stuffing.vhd
+- Offset: `0xcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_same_bits_rst_trig
+Auto-extracted signal same_bits_rst_trig from bit_stuffing.vhd
+- Offset: `0xd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_same_bits_rst
+Auto-extracted signal same_bits_rst from bit_stuffing.vhd
+- Offset: `0xd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_insert_stuff_bit
+Auto-extracted signal insert_stuff_bit from bit_stuffing.vhd
+- Offset: `0xd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_d_ena
+Auto-extracted signal data_out_d_ena from bit_stuffing.vhd
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_d
+Auto-extracted signal data_out_d from bit_stuffing.vhd
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_ce
+Auto-extracted signal data_out_ce from bit_stuffing.vhd
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_tq_nbt
+Auto-extracted signal drv_tq_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_prs_nbt
+Auto-extracted signal drv_prs_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph1_nbt
+Auto-extracted signal drv_ph1_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph2_nbt
+Auto-extracted signal drv_ph2_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_sjw_nbt
+Auto-extracted signal drv_sjw_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_tq_dbt
+Auto-extracted signal drv_tq_dbt from bit_time_cfg_capture.vhd
+- Offset: `0xfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_prs_dbt
+Auto-extracted signal drv_prs_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x100`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph1_dbt
+Auto-extracted signal drv_ph1_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x104`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph2_dbt
+Auto-extracted signal drv_ph2_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x108`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_sjw_dbt
+Auto-extracted signal drv_sjw_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x10c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_tseg1_nbt_d
+Auto-extracted signal tseg1_nbt_d from bit_time_cfg_capture.vhd
+- Offset: `0x110`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_tseg1_dbt_d
+Auto-extracted signal tseg1_dbt_d from bit_time_cfg_capture.vhd
+- Offset: `0x114`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena
+Auto-extracted signal drv_ena from bit_time_cfg_capture.vhd
+- Offset: `0x118`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena_reg
+Auto-extracted signal drv_ena_reg from bit_time_cfg_capture.vhd
+- Offset: `0x11c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena_reg_2
+Auto-extracted signal drv_ena_reg_2 from bit_time_cfg_capture.vhd
+- Offset: `0x120`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_capture
+Auto-extracted signal capture from bit_time_cfg_capture.vhd
+- Offset: `0x124`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_d
+Auto-extracted signal tq_counter_d from bit_time_counters.vhd
+- Offset: `0x128`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_q
+Auto-extracted signal tq_counter_q from bit_time_counters.vhd
+- Offset: `0x12c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_ce
+Auto-extracted signal tq_counter_ce from bit_time_counters.vhd
+- Offset: `0x130`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_allow
+Auto-extracted signal tq_counter_allow from bit_time_counters.vhd
+- Offset: `0x134`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_edge_i
+Auto-extracted signal tq_edge_i from bit_time_counters.vhd
+- Offset: `0x138`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_d
+Auto-extracted signal segm_counter_d from bit_time_counters.vhd
+- Offset: `0x13c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_q
+Auto-extracted signal segm_counter_q from bit_time_counters.vhd
+- Offset: `0x140`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_ce
+Auto-extracted signal segm_counter_ce from bit_time_counters.vhd
+- Offset: `0x144`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_fsm_bt_fsm_ce
+Auto-extracted signal bt_fsm_ce from bit_time_fsm.vhd
+- Offset: `0x148`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ena
+Auto-extracted signal drv_ena from bus_sampling.vhd
+- Offset: `0x14c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ssp_offset
+Auto-extracted signal drv_ssp_offset from bus_sampling.vhd
+- Offset: `0x150`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ssp_delay_select
+Auto-extracted signal drv_ssp_delay_select from bus_sampling.vhd
+- Offset: `0x154`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_data_rx_synced
+Auto-extracted signal data_rx_synced from bus_sampling.vhd
+- Offset: `0x158`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_prev_Sample
+Auto-extracted signal prev_Sample from bus_sampling.vhd
+- Offset: `0x15c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_sample_sec_i
+Auto-extracted signal sample_sec_i from bus_sampling.vhd
+- Offset: `0x160`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_data_tx_delayed
+Auto-extracted signal data_tx_delayed from bus_sampling.vhd
+- Offset: `0x164`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_edge_rx_valid
+Auto-extracted signal edge_rx_valid from bus_sampling.vhd
+- Offset: `0x168`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_edge_tx_valid
+Auto-extracted signal edge_tx_valid from bus_sampling.vhd
+- Offset: `0x16c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_ssp_delay
+Auto-extracted signal ssp_delay from bus_sampling.vhd
+- Offset: `0x170`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_tx_trigger_q
+Auto-extracted signal tx_trigger_q from bus_sampling.vhd
+- Offset: `0x174`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_tx_trigger_ssp
+Auto-extracted signal tx_trigger_ssp from bus_sampling.vhd
+- Offset: `0x178`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_d
+Auto-extracted signal shift_regs_res_d from bus_sampling.vhd
+- Offset: `0x17c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_q
+Auto-extracted signal shift_regs_res_q from bus_sampling.vhd
+- Offset: `0x180`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_q_scan
+Auto-extracted signal shift_regs_res_q_scan from bus_sampling.vhd
+- Offset: `0x184`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_ssp_enable
+Auto-extracted signal ssp_enable from bus_sampling.vhd
+- Offset: `0x188`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_i
+Auto-extracted signal tx_ctr_i from bus_traffic_counters.vhd
+- Offset: `0x18c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_i
+Auto-extracted signal rx_ctr_i from bus_traffic_counters.vhd
+- Offset: `0x190`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_d
+Auto-extracted signal tx_ctr_rst_n_d from bus_traffic_counters.vhd
+- Offset: `0x194`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_q
+Auto-extracted signal tx_ctr_rst_n_q from bus_traffic_counters.vhd
+- Offset: `0x198`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_q_scan
+Auto-extracted signal tx_ctr_rst_n_q_scan from bus_traffic_counters.vhd
+- Offset: `0x19c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_d
+Auto-extracted signal rx_ctr_rst_n_d from bus_traffic_counters.vhd
+- Offset: `0x1a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_q
+Auto-extracted signal rx_ctr_rst_n_q from bus_traffic_counters.vhd
+- Offset: `0x1a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_q_scan
+Auto-extracted signal rx_ctr_rst_n_q_scan from bus_traffic_counters.vhd
+- Offset: `0x1a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_paddr
+Auto-extracted signal s_apb_paddr from can_apb_tb.vhd
+- Offset: `0x1ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_penable
+Auto-extracted signal s_apb_penable from can_apb_tb.vhd
+- Offset: `0x1b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pprot
+Auto-extracted signal s_apb_pprot from can_apb_tb.vhd
+- Offset: `0x1b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_prdata
+Auto-extracted signal s_apb_prdata from can_apb_tb.vhd
+- Offset: `0x1b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pready
+Auto-extracted signal s_apb_pready from can_apb_tb.vhd
+- Offset: `0x1bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_psel
+Auto-extracted signal s_apb_psel from can_apb_tb.vhd
+- Offset: `0x1c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pslverr
+Auto-extracted signal s_apb_pslverr from can_apb_tb.vhd
+- Offset: `0x1c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pstrb
+Auto-extracted signal s_apb_pstrb from can_apb_tb.vhd
+- Offset: `0x1c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pwdata
+Auto-extracted signal s_apb_pwdata from can_apb_tb.vhd
+- Offset: `0x1cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pwrite
+Auto-extracted signal s_apb_pwrite from can_apb_tb.vhd
+- Offset: `0x1d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_clr_rx_ctr
+Auto-extracted signal drv_clr_rx_ctr from can_core.vhd
+- Offset: `0x1d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_clr_tx_ctr
+Auto-extracted signal drv_clr_tx_ctr from can_core.vhd
+- Offset: `0x1d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_bus_mon_ena
+Auto-extracted signal drv_bus_mon_ena from can_core.vhd
+- Offset: `0x1dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_ena
+Auto-extracted signal drv_ena from can_core.vhd
+- Offset: `0x1e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_ident_i
+Auto-extracted signal rec_ident_i from can_core.vhd
+- Offset: `0x1e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_dlc_i
+Auto-extracted signal rec_dlc_i from can_core.vhd
+- Offset: `0x1e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_ident_type_i
+Auto-extracted signal rec_ident_type_i from can_core.vhd
+- Offset: `0x1ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from can_core.vhd
+- Offset: `0x1f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from can_core.vhd
+- Offset: `0x1f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_brs_i
+Auto-extracted signal rec_brs_i from can_core.vhd
+- Offset: `0x1f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_esi_i
+Auto-extracted signal rec_esi_i from can_core.vhd
+- Offset: `0x1fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_alc
+Auto-extracted signal alc from can_core.vhd
+- Offset: `0x200`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_erc_capture
+Auto-extracted signal erc_capture from can_core.vhd
+- Offset: `0x204`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_transmitter
+Auto-extracted signal is_transmitter from can_core.vhd
+- Offset: `0x208`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_receiver
+Auto-extracted signal is_receiver from can_core.vhd
+- Offset: `0x20c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_idle
+Auto-extracted signal is_idle from can_core.vhd
+- Offset: `0x210`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from can_core.vhd
+- Offset: `0x214`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_transmitter
+Auto-extracted signal set_transmitter from can_core.vhd
+- Offset: `0x218`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_receiver
+Auto-extracted signal set_receiver from can_core.vhd
+- Offset: `0x21c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_idle
+Auto-extracted signal set_idle from can_core.vhd
+- Offset: `0x220`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_active
+Auto-extracted signal is_err_active from can_core.vhd
+- Offset: `0x224`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_passive
+Auto-extracted signal is_err_passive from can_core.vhd
+- Offset: `0x228`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_bus_off_i
+Auto-extracted signal is_bus_off_i from can_core.vhd
+- Offset: `0x22c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_detected_i
+Auto-extracted signal err_detected_i from can_core.vhd
+- Offset: `0x230`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_primary_err
+Auto-extracted signal primary_err from can_core.vhd
+- Offset: `0x234`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_act_err_ovr_flag
+Auto-extracted signal act_err_ovr_flag from can_core.vhd
+- Offset: `0x238`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_delim_late
+Auto-extracted signal err_delim_late from can_core.vhd
+- Offset: `0x23c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_err_active
+Auto-extracted signal set_err_active from can_core.vhd
+- Offset: `0x240`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_ctrs_unchanged
+Auto-extracted signal err_ctrs_unchanged from can_core.vhd
+- Offset: `0x244`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_enable
+Auto-extracted signal stuff_enable from can_core.vhd
+- Offset: `0x248`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_destuff_enable
+Auto-extracted signal destuff_enable from can_core.vhd
+- Offset: `0x24c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_fixed_stuff
+Auto-extracted signal fixed_stuff from can_core.vhd
+- Offset: `0x250`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_frame_no_sof
+Auto-extracted signal tx_frame_no_sof from can_core.vhd
+- Offset: `0x254`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_length
+Auto-extracted signal stuff_length from can_core.vhd
+- Offset: `0x258`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_dst_ctr
+Auto-extracted signal dst_ctr from can_core.vhd
+- Offset: `0x25c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_ctr
+Auto-extracted signal bst_ctr from can_core.vhd
+- Offset: `0x260`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_err
+Auto-extracted signal stuff_err from can_core.vhd
+- Offset: `0x264`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_enable
+Auto-extracted signal crc_enable from can_core.vhd
+- Offset: `0x268`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_spec_enable
+Auto-extracted signal crc_spec_enable from can_core.vhd
+- Offset: `0x26c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_calc_from_rx
+Auto-extracted signal crc_calc_from_rx from can_core.vhd
+- Offset: `0x270`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_15
+Auto-extracted signal crc_15 from can_core.vhd
+- Offset: `0x274`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_17
+Auto-extracted signal crc_17 from can_core.vhd
+- Offset: `0x278`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_21
+Auto-extracted signal crc_21 from can_core.vhd
+- Offset: `0x27c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sp_control_i
+Auto-extracted signal sp_control_i from can_core.vhd
+- Offset: `0x280`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sp_control_q
+Auto-extracted signal sp_control_q from can_core.vhd
+- Offset: `0x284`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sync_control_i
+Auto-extracted signal sync_control_i from can_core.vhd
+- Offset: `0x288`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_ssp_reset_i
+Auto-extracted signal ssp_reset_i from can_core.vhd
+- Offset: `0x28c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tran_delay_meas_i
+Auto-extracted signal tran_delay_meas_i from can_core.vhd
+- Offset: `0x290`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tran_valid_i
+Auto-extracted signal tran_valid_i from can_core.vhd
+- Offset: `0x294`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_valid_i
+Auto-extracted signal rec_valid_i from can_core.vhd
+- Offset: `0x298`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_br_shifted_i
+Auto-extracted signal br_shifted_i from can_core.vhd
+- Offset: `0x29c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_fcs_changed_i
+Auto-extracted signal fcs_changed_i from can_core.vhd
+- Offset: `0x2a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_warning_limit_i
+Auto-extracted signal err_warning_limit_i from can_core.vhd
+- Offset: `0x2a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_err_ctr
+Auto-extracted signal tx_err_ctr from can_core.vhd
+- Offset: `0x2a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rx_err_ctr
+Auto-extracted signal rx_err_ctr from can_core.vhd
+- Offset: `0x2ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_norm_err_ctr
+Auto-extracted signal norm_err_ctr from can_core.vhd
+- Offset: `0x2b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_data_err_ctr
+Auto-extracted signal data_err_ctr from can_core.vhd
+- Offset: `0x2b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_tx_trigger
+Auto-extracted signal pc_tx_trigger from can_core.vhd
+- Offset: `0x2b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_rx_trigger
+Auto-extracted signal pc_rx_trigger from can_core.vhd
+- Offset: `0x2bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_tx_data_nbs
+Auto-extracted signal pc_tx_data_nbs from can_core.vhd
+- Offset: `0x2c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_rx_data_nbs
+Auto-extracted signal pc_rx_data_nbs from can_core.vhd
+- Offset: `0x2c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_tx_wbs
+Auto-extracted signal crc_data_tx_wbs from can_core.vhd
+- Offset: `0x2c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_tx_nbs
+Auto-extracted signal crc_data_tx_nbs from can_core.vhd
+- Offset: `0x2cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_rx_wbs
+Auto-extracted signal crc_data_rx_wbs from can_core.vhd
+- Offset: `0x2d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_rx_nbs
+Auto-extracted signal crc_data_rx_nbs from can_core.vhd
+- Offset: `0x2d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_tx_wbs
+Auto-extracted signal crc_trig_tx_wbs from can_core.vhd
+- Offset: `0x2d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_tx_nbs
+Auto-extracted signal crc_trig_tx_nbs from can_core.vhd
+- Offset: `0x2dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_rx_wbs
+Auto-extracted signal crc_trig_rx_wbs from can_core.vhd
+- Offset: `0x2e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_rx_nbs
+Auto-extracted signal crc_trig_rx_nbs from can_core.vhd
+- Offset: `0x2e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_data_in
+Auto-extracted signal bst_data_in from can_core.vhd
+- Offset: `0x2e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_data_out
+Auto-extracted signal bst_data_out from can_core.vhd
+- Offset: `0x2ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_trigger
+Auto-extracted signal bst_trigger from can_core.vhd
+- Offset: `0x2f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_data_halt
+Auto-extracted signal data_halt from can_core.vhd
+- Offset: `0x2f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_data_in
+Auto-extracted signal bds_data_in from can_core.vhd
+- Offset: `0x2f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_data_out
+Auto-extracted signal bds_data_out from can_core.vhd
+- Offset: `0x2fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_trigger
+Auto-extracted signal bds_trigger from can_core.vhd
+- Offset: `0x300`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_destuffed
+Auto-extracted signal destuffed from can_core.vhd
+- Offset: `0x304`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_ctr
+Auto-extracted signal tx_ctr from can_core.vhd
+- Offset: `0x308`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rx_ctr
+Auto-extracted signal rx_ctr from can_core.vhd
+- Offset: `0x30c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_data_wbs_i
+Auto-extracted signal tx_data_wbs_i from can_core.vhd
+- Offset: `0x310`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_lpb_dominant
+Auto-extracted signal lpb_dominant from can_core.vhd
+- Offset: `0x314`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_form_err
+Auto-extracted signal form_err from can_core.vhd
+- Offset: `0x318`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_ack_err
+Auto-extracted signal ack_err from can_core.vhd
+- Offset: `0x31c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_err
+Auto-extracted signal crc_err from can_core.vhd
+- Offset: `0x320`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_arbitration
+Auto-extracted signal is_arbitration from can_core.vhd
+- Offset: `0x324`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_control
+Auto-extracted signal is_control from can_core.vhd
+- Offset: `0x328`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_data
+Auto-extracted signal is_data from can_core.vhd
+- Offset: `0x32c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_stuff_count
+Auto-extracted signal is_stuff_count from can_core.vhd
+- Offset: `0x330`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_crc
+Auto-extracted signal is_crc from can_core.vhd
+- Offset: `0x334`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_crc_delim
+Auto-extracted signal is_crc_delim from can_core.vhd
+- Offset: `0x338`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_ack_field
+Auto-extracted signal is_ack_field from can_core.vhd
+- Offset: `0x33c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_ack_delim
+Auto-extracted signal is_ack_delim from can_core.vhd
+- Offset: `0x340`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_eof
+Auto-extracted signal is_eof from can_core.vhd
+- Offset: `0x344`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_frm
+Auto-extracted signal is_err_frm from can_core.vhd
+- Offset: `0x348`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_intermission
+Auto-extracted signal is_intermission from can_core.vhd
+- Offset: `0x34c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_suspend
+Auto-extracted signal is_suspend from can_core.vhd
+- Offset: `0x350`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_overload_i
+Auto-extracted signal is_overload_i from can_core.vhd
+- Offset: `0x354`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_sof
+Auto-extracted signal is_sof from can_core.vhd
+- Offset: `0x358`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sof_pulse_i
+Auto-extracted signal sof_pulse_i from can_core.vhd
+- Offset: `0x35c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_load_init_vect
+Auto-extracted signal load_init_vect from can_core.vhd
+- Offset: `0x360`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_retr_ctr_i
+Auto-extracted signal retr_ctr_i from can_core.vhd
+- Offset: `0x364`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_decrement_rec
+Auto-extracted signal decrement_rec from can_core.vhd
+- Offset: `0x368`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bit_err_after_ack_err
+Auto-extracted signal bit_err_after_ack_err from can_core.vhd
+- Offset: `0x36c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_pexs
+Auto-extracted signal is_pexs from can_core.vhd
+- Offset: `0x370`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_drv_fd_type
+Auto-extracted signal drv_fd_type from can_crc.vhd
+- Offset: `0x374`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_15
+Auto-extracted signal init_vect_15 from can_crc.vhd
+- Offset: `0x378`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_17
+Auto-extracted signal init_vect_17 from can_crc.vhd
+- Offset: `0x37c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_21
+Auto-extracted signal init_vect_21 from can_crc.vhd
+- Offset: `0x380`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_17_21_data_in
+Auto-extracted signal crc_17_21_data_in from can_crc.vhd
+- Offset: `0x384`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_17_21_trigger
+Auto-extracted signal crc_17_21_trigger from can_crc.vhd
+- Offset: `0x388`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_15_data_in
+Auto-extracted signal crc_15_data_in from can_crc.vhd
+- Offset: `0x38c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_15_trigger
+Auto-extracted signal crc_15_trigger from can_crc.vhd
+- Offset: `0x390`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_ena_15
+Auto-extracted signal crc_ena_15 from can_crc.vhd
+- Offset: `0x394`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_ena_17_21
+Auto-extracted signal crc_ena_17_21 from can_crc.vhd
+- Offset: `0x398`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_data_in
+Auto-extracted signal ctu_can_data_in from can_top_ahb.vhd
+- Offset: `0x39c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_data_out
+Auto-extracted signal ctu_can_data_out from can_top_ahb.vhd
+- Offset: `0x3a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_adress
+Auto-extracted signal ctu_can_adress from can_top_ahb.vhd
+- Offset: `0x3a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_scs
+Auto-extracted signal ctu_can_scs from can_top_ahb.vhd
+- Offset: `0x3a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_srd
+Auto-extracted signal ctu_can_srd from can_top_ahb.vhd
+- Offset: `0x3ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_swr
+Auto-extracted signal ctu_can_swr from can_top_ahb.vhd
+- Offset: `0x3b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_sbe
+Auto-extracted signal ctu_can_sbe from can_top_ahb.vhd
+- Offset: `0x3b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_res_n_out_i
+Auto-extracted signal res_n_out_i from can_top_ahb.vhd
+- Offset: `0x3b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_data_in
+Auto-extracted signal reg_data_in from can_top_apb.vhd
+- Offset: `0x3bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_data_out
+Auto-extracted signal reg_data_out from can_top_apb.vhd
+- Offset: `0x3c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_addr
+Auto-extracted signal reg_addr from can_top_apb.vhd
+- Offset: `0x3c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_be
+Auto-extracted signal reg_be from can_top_apb.vhd
+- Offset: `0x3c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_rden
+Auto-extracted signal reg_rden from can_top_apb.vhd
+- Offset: `0x3cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_wren
+Auto-extracted signal reg_wren from can_top_apb.vhd
+- Offset: `0x3d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_drv_bus
+Auto-extracted signal drv_bus from can_top_level.vhd
+- Offset: `0x3d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_stat_bus
+Auto-extracted signal stat_bus from can_top_level.vhd
+- Offset: `0x3d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_n_sync
+Auto-extracted signal res_n_sync from can_top_level.vhd
+- Offset: `0x3dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_core_n
+Auto-extracted signal res_core_n from can_top_level.vhd
+- Offset: `0x3e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_soft_n
+Auto-extracted signal res_soft_n from can_top_level.vhd
+- Offset: `0x3e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sp_control
+Auto-extracted signal sp_control from can_top_level.vhd
+- Offset: `0x3e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_buf_size
+Auto-extracted signal rx_buf_size from can_top_level.vhd
+- Offset: `0x3ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_full
+Auto-extracted signal rx_full from can_top_level.vhd
+- Offset: `0x3f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_empty
+Auto-extracted signal rx_empty from can_top_level.vhd
+- Offset: `0x3f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_frame_count
+Auto-extracted signal rx_frame_count from can_top_level.vhd
+- Offset: `0x3f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_mem_free
+Auto-extracted signal rx_mem_free from can_top_level.vhd
+- Offset: `0x3fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_read_pointer
+Auto-extracted signal rx_read_pointer from can_top_level.vhd
+- Offset: `0x400`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_write_pointer
+Auto-extracted signal rx_write_pointer from can_top_level.vhd
+- Offset: `0x404`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_data_overrun
+Auto-extracted signal rx_data_overrun from can_top_level.vhd
+- Offset: `0x408`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_read_buff
+Auto-extracted signal rx_read_buff from can_top_level.vhd
+- Offset: `0x40c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_mof
+Auto-extracted signal rx_mof from can_top_level.vhd
+- Offset: `0x410`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_data
+Auto-extracted signal txtb_port_a_data from can_top_level.vhd
+- Offset: `0x414`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_address
+Auto-extracted signal txtb_port_a_address from can_top_level.vhd
+- Offset: `0x418`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_cs
+Auto-extracted signal txtb_port_a_cs from can_top_level.vhd
+- Offset: `0x41c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_be
+Auto-extracted signal txtb_port_a_be from can_top_level.vhd
+- Offset: `0x420`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_sw_cmd_index
+Auto-extracted signal txtb_sw_cmd_index from can_top_level.vhd
+- Offset: `0x424`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txt_buf_failed_bof
+Auto-extracted signal txt_buf_failed_bof from can_top_level.vhd
+- Offset: `0x428`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_vector
+Auto-extracted signal int_vector from can_top_level.vhd
+- Offset: `0x42c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_ena
+Auto-extracted signal int_ena from can_top_level.vhd
+- Offset: `0x430`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_mask
+Auto-extracted signal int_mask from can_top_level.vhd
+- Offset: `0x434`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_ident
+Auto-extracted signal rec_ident from can_top_level.vhd
+- Offset: `0x438`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_dlc
+Auto-extracted signal rec_dlc from can_top_level.vhd
+- Offset: `0x43c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_ident_type
+Auto-extracted signal rec_ident_type from can_top_level.vhd
+- Offset: `0x440`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_frame_type
+Auto-extracted signal rec_frame_type from can_top_level.vhd
+- Offset: `0x444`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_is_rtr
+Auto-extracted signal rec_is_rtr from can_top_level.vhd
+- Offset: `0x448`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_brs
+Auto-extracted signal rec_brs from can_top_level.vhd
+- Offset: `0x44c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_esi
+Auto-extracted signal rec_esi from can_top_level.vhd
+- Offset: `0x450`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data_word
+Auto-extracted signal store_data_word from can_top_level.vhd
+- Offset: `0x454`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sof_pulse
+Auto-extracted signal sof_pulse from can_top_level.vhd
+- Offset: `0x458`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_metadata
+Auto-extracted signal store_metadata from can_top_level.vhd
+- Offset: `0x45c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data
+Auto-extracted signal store_data from can_top_level.vhd
+- Offset: `0x460`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_valid
+Auto-extracted signal rec_valid from can_top_level.vhd
+- Offset: `0x464`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_abort
+Auto-extracted signal rec_abort from can_top_level.vhd
+- Offset: `0x468`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_metadata_f
+Auto-extracted signal store_metadata_f from can_top_level.vhd
+- Offset: `0x46c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data_f
+Auto-extracted signal store_data_f from can_top_level.vhd
+- Offset: `0x470`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_valid_f
+Auto-extracted signal rec_valid_f from can_top_level.vhd
+- Offset: `0x474`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_abort_f
+Auto-extracted signal rec_abort_f from can_top_level.vhd
+- Offset: `0x478`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_hw_cmd_int
+Auto-extracted signal txtb_hw_cmd_int from can_top_level.vhd
+- Offset: `0x47c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_is_bus_off
+Auto-extracted signal is_bus_off from can_top_level.vhd
+- Offset: `0x480`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_available
+Auto-extracted signal txtb_available from can_top_level.vhd
+- Offset: `0x484`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_b_clk_en
+Auto-extracted signal txtb_port_b_clk_en from can_top_level.vhd
+- Offset: `0x488`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_dlc
+Auto-extracted signal tran_dlc from can_top_level.vhd
+- Offset: `0x48c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_is_rtr
+Auto-extracted signal tran_is_rtr from can_top_level.vhd
+- Offset: `0x490`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_ident_type
+Auto-extracted signal tran_ident_type from can_top_level.vhd
+- Offset: `0x494`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_frame_type
+Auto-extracted signal tran_frame_type from can_top_level.vhd
+- Offset: `0x498`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_brs
+Auto-extracted signal tran_brs from can_top_level.vhd
+- Offset: `0x49c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_identifier
+Auto-extracted signal tran_identifier from can_top_level.vhd
+- Offset: `0x4a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_word
+Auto-extracted signal tran_word from can_top_level.vhd
+- Offset: `0x4a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_frame_valid
+Auto-extracted signal tran_frame_valid from can_top_level.vhd
+- Offset: `0x4a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_changed
+Auto-extracted signal txtb_changed from can_top_level.vhd
+- Offset: `0x4ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_clk_en
+Auto-extracted signal txtb_clk_en from can_top_level.vhd
+- Offset: `0x4b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_err_detected
+Auto-extracted signal err_detected from can_top_level.vhd
+- Offset: `0x4b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_fcs_changed
+Auto-extracted signal fcs_changed from can_top_level.vhd
+- Offset: `0x4b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_err_warning_limit
+Auto-extracted signal err_warning_limit from can_top_level.vhd
+- Offset: `0x4bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_arbitration_lost
+Auto-extracted signal arbitration_lost from can_top_level.vhd
+- Offset: `0x4c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_valid
+Auto-extracted signal tran_valid from can_top_level.vhd
+- Offset: `0x4c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_br_shifted
+Auto-extracted signal br_shifted from can_top_level.vhd
+- Offset: `0x4c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_is_overload
+Auto-extracted signal is_overload from can_top_level.vhd
+- Offset: `0x4cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_triggers
+Auto-extracted signal rx_triggers from can_top_level.vhd
+- Offset: `0x4d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tx_trigger
+Auto-extracted signal tx_trigger from can_top_level.vhd
+- Offset: `0x4d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sync_control
+Auto-extracted signal sync_control from can_top_level.vhd
+- Offset: `0x4d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_no_pos_resync
+Auto-extracted signal no_pos_resync from can_top_level.vhd
+- Offset: `0x4dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_nbt_ctrs_en
+Auto-extracted signal nbt_ctrs_en from can_top_level.vhd
+- Offset: `0x4e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_dbt_ctrs_en
+Auto-extracted signal dbt_ctrs_en from can_top_level.vhd
+- Offset: `0x4e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_trv_delay
+Auto-extracted signal trv_delay from can_top_level.vhd
+- Offset: `0x4e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_data_wbs
+Auto-extracted signal rx_data_wbs from can_top_level.vhd
+- Offset: `0x4ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tx_data_wbs
+Auto-extracted signal tx_data_wbs from can_top_level.vhd
+- Offset: `0x4f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_ssp_reset
+Auto-extracted signal ssp_reset from can_top_level.vhd
+- Offset: `0x4f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_delay_meas
+Auto-extracted signal tran_delay_meas from can_top_level.vhd
+- Offset: `0x4f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_bit_err
+Auto-extracted signal bit_err from can_top_level.vhd
+- Offset: `0x4fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sample_sec
+Auto-extracted signal sample_sec from can_top_level.vhd
+- Offset: `0x500`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_btmc_reset
+Auto-extracted signal btmc_reset from can_top_level.vhd
+- Offset: `0x504`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_dbt_measure_start
+Auto-extracted signal dbt_measure_start from can_top_level.vhd
+- Offset: `0x508`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_gen_first_ssp
+Auto-extracted signal gen_first_ssp from can_top_level.vhd
+- Offset: `0x50c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sync_edge
+Auto-extracted signal sync_edge from can_top_level.vhd
+- Offset: `0x510`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tq_edge
+Auto-extracted signal tq_edge from can_top_level.vhd
+- Offset: `0x514`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tst_rdata_rx_buf
+Auto-extracted signal tst_rdata_rx_buf from can_top_level.vhd
+- Offset: `0x518`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## clk_gate_clk_en_q
+Auto-extracted signal clk_en_q from clk_gate.vhd
+- Offset: `0x51c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_counter_ctrl_ctr_ce
+Auto-extracted signal ctrl_ctr_ce from control_counter.vhd
+- Offset: `0x520`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_counter_compl_ctr_ce
+Auto-extracted signal compl_ctr_ce from control_counter.vhd
+- Offset: `0x524`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_reg_sel
+Auto-extracted signal reg_sel from control_registers_reg_map.vhd
+- Offset: `0x528`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_data_mux_in
+Auto-extracted signal read_data_mux_in from control_registers_reg_map.vhd
+- Offset: `0x52c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_data_mask_n
+Auto-extracted signal read_data_mask_n from control_registers_reg_map.vhd
+- Offset: `0x530`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_mux_ena
+Auto-extracted signal read_mux_ena from control_registers_reg_map.vhd
+- Offset: `0x534`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_q
+Auto-extracted signal crc_q from crc_calc.vhd
+- Offset: `0x538`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_nxt
+Auto-extracted signal crc_nxt from crc_calc.vhd
+- Offset: `0x53c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_shift
+Auto-extracted signal crc_shift from crc_calc.vhd
+- Offset: `0x540`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_shift_n_xor
+Auto-extracted signal crc_shift_n_xor from crc_calc.vhd
+- Offset: `0x544`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_d
+Auto-extracted signal crc_d from crc_calc.vhd
+- Offset: `0x548`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_ce
+Auto-extracted signal crc_ce from crc_calc.vhd
+- Offset: `0x54c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_data_prev
+Auto-extracted signal rx_data_prev from data_edge_detector.vhd
+- Offset: `0x550`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_tx_data_prev
+Auto-extracted signal tx_data_prev from data_edge_detector.vhd
+- Offset: `0x554`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_data_sync_prev
+Auto-extracted signal rx_data_sync_prev from data_edge_detector.vhd
+- Offset: `0x558`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_edge_i
+Auto-extracted signal rx_edge_i from data_edge_detector.vhd
+- Offset: `0x55c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_tx_edge_i
+Auto-extracted signal tx_edge_i from data_edge_detector.vhd
+- Offset: `0x560`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_sel_data
+Auto-extracted signal sel_data from data_mux.vhd
+- Offset: `0x564`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_saturated_data
+Auto-extracted signal saturated_data from data_mux.vhd
+- Offset: `0x568`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_masked_data
+Auto-extracted signal masked_data from data_mux.vhd
+- Offset: `0x56c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_8_to_64
+Auto-extracted signal data_len_8_to_64 from dlc_decoder.vhd
+- Offset: `0x570`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_can_2_0
+Auto-extracted signal data_len_can_2_0 from dlc_decoder.vhd
+- Offset: `0x574`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_can_fd
+Auto-extracted signal data_len_can_fd from dlc_decoder.vhd
+- Offset: `0x578`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## endian_swapper_swapped
+Auto-extracted signal swapped from endian_swapper.vhd
+- Offset: `0x57c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_tx_err_ctr_ce
+Auto-extracted signal tx_err_ctr_ce from err_counters.vhd
+- Offset: `0x580`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_rx_err_ctr_ce
+Auto-extracted signal rx_err_ctr_ce from err_counters.vhd
+- Offset: `0x584`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_modif_tx_ctr
+Auto-extracted signal modif_tx_ctr from err_counters.vhd
+- Offset: `0x588`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_modif_rx_ctr
+Auto-extracted signal modif_rx_ctr from err_counters.vhd
+- Offset: `0x58c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_nom_err_ctr_ce
+Auto-extracted signal nom_err_ctr_ce from err_counters.vhd
+- Offset: `0x590`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_data_err_ctr_ce
+Auto-extracted signal data_err_ctr_ce from err_counters.vhd
+- Offset: `0x594`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_d
+Auto-extracted signal res_err_ctrs_d from err_counters.vhd
+- Offset: `0x598`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_q
+Auto-extracted signal res_err_ctrs_q from err_counters.vhd
+- Offset: `0x59c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_q_scan
+Auto-extracted signal res_err_ctrs_q_scan from err_counters.vhd
+- Offset: `0x5a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_frm_req_i
+Auto-extracted signal err_frm_req_i from err_detector.vhd
+- Offset: `0x5a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_type_d
+Auto-extracted signal err_type_d from err_detector.vhd
+- Offset: `0x5a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_type_q
+Auto-extracted signal err_type_q from err_detector.vhd
+- Offset: `0x5ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_pos_q
+Auto-extracted signal err_pos_q from err_detector.vhd
+- Offset: `0x5b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_form_err_i
+Auto-extracted signal form_err_i from err_detector.vhd
+- Offset: `0x5b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_c
+Auto-extracted signal crc_match_c from err_detector.vhd
+- Offset: `0x5b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_d
+Auto-extracted signal crc_match_d from err_detector.vhd
+- Offset: `0x5bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_q
+Auto-extracted signal crc_match_q from err_detector.vhd
+- Offset: `0x5c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_dst_ctr_grey
+Auto-extracted signal dst_ctr_grey from err_detector.vhd
+- Offset: `0x5c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_dst_parity
+Auto-extracted signal dst_parity from err_detector.vhd
+- Offset: `0x5c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_stuff_count_check
+Auto-extracted signal stuff_count_check from err_detector.vhd
+- Offset: `0x5cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_15_ok
+Auto-extracted signal crc_15_ok from err_detector.vhd
+- Offset: `0x5d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_17_ok
+Auto-extracted signal crc_17_ok from err_detector.vhd
+- Offset: `0x5d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_21_ok
+Auto-extracted signal crc_21_ok from err_detector.vhd
+- Offset: `0x5d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_stuff_count_ok
+Auto-extracted signal stuff_count_ok from err_detector.vhd
+- Offset: `0x5dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_15
+Auto-extracted signal rx_crc_15 from err_detector.vhd
+- Offset: `0x5e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_17
+Auto-extracted signal rx_crc_17 from err_detector.vhd
+- Offset: `0x5e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_21
+Auto-extracted signal rx_crc_21 from err_detector.vhd
+- Offset: `0x5e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ewl
+Auto-extracted signal drv_ewl from fault_confinement.vhd
+- Offset: `0x5ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_erp
+Auto-extracted signal drv_erp from fault_confinement.vhd
+- Offset: `0x5f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ctr_val
+Auto-extracted signal drv_ctr_val from fault_confinement.vhd
+- Offset: `0x5f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ctr_sel
+Auto-extracted signal drv_ctr_sel from fault_confinement.vhd
+- Offset: `0x5f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ena
+Auto-extracted signal drv_ena from fault_confinement.vhd
+- Offset: `0x5fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_tx_err_ctr_i
+Auto-extracted signal tx_err_ctr_i from fault_confinement.vhd
+- Offset: `0x600`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rx_err_ctr_i
+Auto-extracted signal rx_err_ctr_i from fault_confinement.vhd
+- Offset: `0x604`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_inc_one
+Auto-extracted signal inc_one from fault_confinement.vhd
+- Offset: `0x608`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_inc_eight
+Auto-extracted signal inc_eight from fault_confinement.vhd
+- Offset: `0x60c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_dec_one
+Auto-extracted signal dec_one from fault_confinement.vhd
+- Offset: `0x610`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_rom_ena
+Auto-extracted signal drv_rom_ena from fault_confinement.vhd
+- Offset: `0x614`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_erp
+Auto-extracted signal tx_err_ctr_mt_erp from fault_confinement_fsm.vhd
+- Offset: `0x618`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_rx_err_ctr_mt_erp
+Auto-extracted signal rx_err_ctr_mt_erp from fault_confinement_fsm.vhd
+- Offset: `0x61c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_ewl
+Auto-extracted signal tx_err_ctr_mt_ewl from fault_confinement_fsm.vhd
+- Offset: `0x620`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_rx_err_ctr_mt_ewl
+Auto-extracted signal rx_err_ctr_mt_ewl from fault_confinement_fsm.vhd
+- Offset: `0x624`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_255
+Auto-extracted signal tx_err_ctr_mt_255 from fault_confinement_fsm.vhd
+- Offset: `0x628`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_err_warning_limit_d
+Auto-extracted signal err_warning_limit_d from fault_confinement_fsm.vhd
+- Offset: `0x62c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_err_warning_limit_q
+Auto-extracted signal err_warning_limit_q from fault_confinement_fsm.vhd
+- Offset: `0x630`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_fc_fsm_res_d
+Auto-extracted signal fc_fsm_res_d from fault_confinement_fsm.vhd
+- Offset: `0x634`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_fc_fsm_res_q
+Auto-extracted signal fc_fsm_res_q from fault_confinement_fsm.vhd
+- Offset: `0x638`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rules_inc_one_i
+Auto-extracted signal inc_one_i from fault_confinement_rules.vhd
+- Offset: `0x63c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rules_inc_eight_i
+Auto-extracted signal inc_eight_i from fault_confinement_rules.vhd
+- Offset: `0x640`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_mask
+Auto-extracted signal drv_filter_A_mask from frame_filters.vhd
+- Offset: `0x644`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_ctrl
+Auto-extracted signal drv_filter_A_ctrl from frame_filters.vhd
+- Offset: `0x648`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_bits
+Auto-extracted signal drv_filter_A_bits from frame_filters.vhd
+- Offset: `0x64c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_A_valid
+Auto-extracted signal int_filter_A_valid from frame_filters.vhd
+- Offset: `0x650`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_mask
+Auto-extracted signal drv_filter_B_mask from frame_filters.vhd
+- Offset: `0x654`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_ctrl
+Auto-extracted signal drv_filter_B_ctrl from frame_filters.vhd
+- Offset: `0x658`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_bits
+Auto-extracted signal drv_filter_B_bits from frame_filters.vhd
+- Offset: `0x65c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_B_valid
+Auto-extracted signal int_filter_B_valid from frame_filters.vhd
+- Offset: `0x660`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_mask
+Auto-extracted signal drv_filter_C_mask from frame_filters.vhd
+- Offset: `0x664`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_ctrl
+Auto-extracted signal drv_filter_C_ctrl from frame_filters.vhd
+- Offset: `0x668`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_bits
+Auto-extracted signal drv_filter_C_bits from frame_filters.vhd
+- Offset: `0x66c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_C_valid
+Auto-extracted signal int_filter_C_valid from frame_filters.vhd
+- Offset: `0x670`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_ctrl
+Auto-extracted signal drv_filter_ran_ctrl from frame_filters.vhd
+- Offset: `0x674`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_lo_th
+Auto-extracted signal drv_filter_ran_lo_th from frame_filters.vhd
+- Offset: `0x678`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_hi_th
+Auto-extracted signal drv_filter_ran_hi_th from frame_filters.vhd
+- Offset: `0x67c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_ran_valid
+Auto-extracted signal int_filter_ran_valid from frame_filters.vhd
+- Offset: `0x680`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filters_ena
+Auto-extracted signal drv_filters_ena from frame_filters.vhd
+- Offset: `0x684`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_data_type
+Auto-extracted signal int_data_type from frame_filters.vhd
+- Offset: `0x688`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_data_ctrl
+Auto-extracted signal int_data_ctrl from frame_filters.vhd
+- Offset: `0x68c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_A_enable
+Auto-extracted signal filter_A_enable from frame_filters.vhd
+- Offset: `0x690`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_B_enable
+Auto-extracted signal filter_B_enable from frame_filters.vhd
+- Offset: `0x694`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_C_enable
+Auto-extracted signal filter_C_enable from frame_filters.vhd
+- Offset: `0x698`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_range_enable
+Auto-extracted signal filter_range_enable from frame_filters.vhd
+- Offset: `0x69c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_result
+Auto-extracted signal filter_result from frame_filters.vhd
+- Offset: `0x6a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_ident_valid_d
+Auto-extracted signal ident_valid_d from frame_filters.vhd
+- Offset: `0x6a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_ident_valid_q
+Auto-extracted signal ident_valid_q from frame_filters.vhd
+- Offset: `0x6a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_drop_remote_frames
+Auto-extracted signal drv_drop_remote_frames from frame_filters.vhd
+- Offset: `0x6ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drop_rtr_frame
+Auto-extracted signal drop_rtr_frame from frame_filters.vhd
+- Offset: `0x6b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## inf_ram_wrapper_int_read_data
+Auto-extracted signal int_read_data from inf_ram_wrapper.vhd
+- Offset: `0x6b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## inf_ram_wrapper_byte_we
+Auto-extracted signal byte_we from inf_ram_wrapper.vhd
+- Offset: `0x6b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_vect_clr
+Auto-extracted signal drv_int_vect_clr from int_manager.vhd
+- Offset: `0x6bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_ena_set
+Auto-extracted signal drv_int_ena_set from int_manager.vhd
+- Offset: `0x6c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_ena_clr
+Auto-extracted signal drv_int_ena_clr from int_manager.vhd
+- Offset: `0x6c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_mask_set
+Auto-extracted signal drv_int_mask_set from int_manager.vhd
+- Offset: `0x6c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_mask_clr
+Auto-extracted signal drv_int_mask_clr from int_manager.vhd
+- Offset: `0x6cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_ena_i
+Auto-extracted signal int_ena_i from int_manager.vhd
+- Offset: `0x6d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_mask_i
+Auto-extracted signal int_mask_i from int_manager.vhd
+- Offset: `0x6d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_vect_i
+Auto-extracted signal int_vect_i from int_manager.vhd
+- Offset: `0x6d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_input_active
+Auto-extracted signal int_input_active from int_manager.vhd
+- Offset: `0x6dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_i
+Auto-extracted signal int_i from int_manager.vhd
+- Offset: `0x6e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_i
+Auto-extracted signal int_mask_i from int_module.vhd
+- Offset: `0x6e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_ena_i
+Auto-extracted signal int_ena_i from int_module.vhd
+- Offset: `0x6e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_load
+Auto-extracted signal int_mask_load from int_module.vhd
+- Offset: `0x6ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_next
+Auto-extracted signal int_mask_next from int_module.vhd
+- Offset: `0x6f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_reg_value_r
+Auto-extracted signal reg_value_r from memory_reg.vhd
+- Offset: `0x6f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_wr_select
+Auto-extracted signal wr_select from memory_reg.vhd
+- Offset: `0x6f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_wr_select_expanded
+Auto-extracted signal wr_select_expanded from memory_reg.vhd
+- Offset: `0x6fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_status_comb
+Auto-extracted signal status_comb from memory_registers.vhd
+- Offset: `0x700`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_can_core_cs
+Auto-extracted signal can_core_cs from memory_registers.vhd
+- Offset: `0x704`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_cs
+Auto-extracted signal control_registers_cs from memory_registers.vhd
+- Offset: `0x708`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_cs_reg
+Auto-extracted signal control_registers_cs_reg from memory_registers.vhd
+- Offset: `0x70c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_cs
+Auto-extracted signal test_registers_cs from memory_registers.vhd
+- Offset: `0x710`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_cs_reg
+Auto-extracted signal test_registers_cs_reg from memory_registers.vhd
+- Offset: `0x714`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_rdata
+Auto-extracted signal control_registers_rdata from memory_registers.vhd
+- Offset: `0x718`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_rdata
+Auto-extracted signal test_registers_rdata from memory_registers.vhd
+- Offset: `0x71c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_err_active
+Auto-extracted signal is_err_active from memory_registers.vhd
+- Offset: `0x720`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_err_passive
+Auto-extracted signal is_err_passive from memory_registers.vhd
+- Offset: `0x724`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_bus_off
+Auto-extracted signal is_bus_off from memory_registers.vhd
+- Offset: `0x728`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_transmitter
+Auto-extracted signal is_transmitter from memory_registers.vhd
+- Offset: `0x72c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_receiver
+Auto-extracted signal is_receiver from memory_registers.vhd
+- Offset: `0x730`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_idle
+Auto-extracted signal is_idle from memory_registers.vhd
+- Offset: `0x734`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_reg_lock_1_active
+Auto-extracted signal reg_lock_1_active from memory_registers.vhd
+- Offset: `0x738`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_reg_lock_2_active
+Auto-extracted signal reg_lock_2_active from memory_registers.vhd
+- Offset: `0x73c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_soft_res_q_n
+Auto-extracted signal soft_res_q_n from memory_registers.vhd
+- Offset: `0x740`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_ewl_padded
+Auto-extracted signal ewl_padded from memory_registers.vhd
+- Offset: `0x744`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_regs_clk_en
+Auto-extracted signal control_regs_clk_en from memory_registers.vhd
+- Offset: `0x748`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_regs_clk_en
+Auto-extracted signal test_regs_clk_en from memory_registers.vhd
+- Offset: `0x74c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_clk_control_regs
+Auto-extracted signal clk_control_regs from memory_registers.vhd
+- Offset: `0x750`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_clk_test_regs
+Auto-extracted signal clk_test_regs from memory_registers.vhd
+- Offset: `0x754`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_rx_buf_mode
+Auto-extracted signal rx_buf_mode from memory_registers.vhd
+- Offset: `0x758`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_rx_move_cmd
+Auto-extracted signal rx_move_cmd from memory_registers.vhd
+- Offset: `0x75c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_ctr_pres_sel_q
+Auto-extracted signal ctr_pres_sel_q from memory_registers.vhd
+- Offset: `0x760`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## operation_control_drv_ena
+Auto-extracted signal drv_ena from operation_control.vhd
+- Offset: `0x764`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## operation_control_go_to_off
+Auto-extracted signal go_to_off from operation_control.vhd
+- Offset: `0x768`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_drv_ena
+Auto-extracted signal drv_ena from prescaler.vhd
+- Offset: `0x76c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg1_nbt
+Auto-extracted signal tseg1_nbt from prescaler.vhd
+- Offset: `0x770`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg2_nbt
+Auto-extracted signal tseg2_nbt from prescaler.vhd
+- Offset: `0x774`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_brp_nbt
+Auto-extracted signal brp_nbt from prescaler.vhd
+- Offset: `0x778`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_sjw_nbt
+Auto-extracted signal sjw_nbt from prescaler.vhd
+- Offset: `0x77c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg1_dbt
+Auto-extracted signal tseg1_dbt from prescaler.vhd
+- Offset: `0x780`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg2_dbt
+Auto-extracted signal tseg2_dbt from prescaler.vhd
+- Offset: `0x784`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_brp_dbt
+Auto-extracted signal brp_dbt from prescaler.vhd
+- Offset: `0x788`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_sjw_dbt
+Auto-extracted signal sjw_dbt from prescaler.vhd
+- Offset: `0x78c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segment_end
+Auto-extracted signal segment_end from prescaler.vhd
+- Offset: `0x790`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_h_sync_valid
+Auto-extracted signal h_sync_valid from prescaler.vhd
+- Offset: `0x794`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_is_tseg1
+Auto-extracted signal is_tseg1 from prescaler.vhd
+- Offset: `0x798`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_is_tseg2
+Auto-extracted signal is_tseg2 from prescaler.vhd
+- Offset: `0x79c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_resync_edge_valid
+Auto-extracted signal resync_edge_valid from prescaler.vhd
+- Offset: `0x7a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_h_sync_edge_valid
+Auto-extracted signal h_sync_edge_valid from prescaler.vhd
+- Offset: `0x7a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segm_counter_nbt
+Auto-extracted signal segm_counter_nbt from prescaler.vhd
+- Offset: `0x7a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segm_counter_dbt
+Auto-extracted signal segm_counter_dbt from prescaler.vhd
+- Offset: `0x7ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_exit_segm_req_nbt
+Auto-extracted signal exit_segm_req_nbt from prescaler.vhd
+- Offset: `0x7b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_exit_segm_req_dbt
+Auto-extracted signal exit_segm_req_dbt from prescaler.vhd
+- Offset: `0x7b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tq_edge_nbt
+Auto-extracted signal tq_edge_nbt from prescaler.vhd
+- Offset: `0x7b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tq_edge_dbt
+Auto-extracted signal tq_edge_dbt from prescaler.vhd
+- Offset: `0x7bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_rx_trig_req
+Auto-extracted signal rx_trig_req from prescaler.vhd
+- Offset: `0x7c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tx_trig_req
+Auto-extracted signal tx_trig_req from prescaler.vhd
+- Offset: `0x7c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_start_edge
+Auto-extracted signal start_edge from prescaler.vhd
+- Offset: `0x7c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_bt_ctr_clear
+Auto-extracted signal bt_ctr_clear from prescaler.vhd
+- Offset: `0x7cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l0_valid
+Auto-extracted signal l0_valid from priority_decoder.vhd
+- Offset: `0x7d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l1_valid
+Auto-extracted signal l1_valid from priority_decoder.vhd
+- Offset: `0x7d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l1_winner
+Auto-extracted signal l1_winner from priority_decoder.vhd
+- Offset: `0x7d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l2_valid
+Auto-extracted signal l2_valid from priority_decoder.vhd
+- Offset: `0x7dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l2_winner
+Auto-extracted signal l2_winner from priority_decoder.vhd
+- Offset: `0x7e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l3_valid
+Auto-extracted signal l3_valid from priority_decoder.vhd
+- Offset: `0x7e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l3_winner
+Auto-extracted signal l3_winner from priority_decoder.vhd
+- Offset: `0x7e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_can_fd_ena
+Auto-extracted signal drv_can_fd_ena from protocol_control.vhd
+- Offset: `0x7ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_bus_mon_ena
+Auto-extracted signal drv_bus_mon_ena from protocol_control.vhd
+- Offset: `0x7f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_retr_lim_ena
+Auto-extracted signal drv_retr_lim_ena from protocol_control.vhd
+- Offset: `0x7f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_retr_th
+Auto-extracted signal drv_retr_th from protocol_control.vhd
+- Offset: `0x7f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_self_test_ena
+Auto-extracted signal drv_self_test_ena from protocol_control.vhd
+- Offset: `0x7fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ack_forb
+Auto-extracted signal drv_ack_forb from protocol_control.vhd
+- Offset: `0x800`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ena
+Auto-extracted signal drv_ena from protocol_control.vhd
+- Offset: `0x804`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_fd_type
+Auto-extracted signal drv_fd_type from protocol_control.vhd
+- Offset: `0x808`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_int_loopback_ena
+Auto-extracted signal drv_int_loopback_ena from protocol_control.vhd
+- Offset: `0x80c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_bus_off_reset
+Auto-extracted signal drv_bus_off_reset from protocol_control.vhd
+- Offset: `0x810`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ssp_delay_select
+Auto-extracted signal drv_ssp_delay_select from protocol_control.vhd
+- Offset: `0x814`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_pex
+Auto-extracted signal drv_pex from protocol_control.vhd
+- Offset: `0x818`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_cpexs
+Auto-extracted signal drv_cpexs from protocol_control.vhd
+- Offset: `0x81c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tran_word_swapped
+Auto-extracted signal tran_word_swapped from protocol_control.vhd
+- Offset: `0x820`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_err_frm_req
+Auto-extracted signal err_frm_req from protocol_control.vhd
+- Offset: `0x824`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_base_id
+Auto-extracted signal tx_load_base_id from protocol_control.vhd
+- Offset: `0x828`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_ext_id
+Auto-extracted signal tx_load_ext_id from protocol_control.vhd
+- Offset: `0x82c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_dlc
+Auto-extracted signal tx_load_dlc from protocol_control.vhd
+- Offset: `0x830`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_data_word
+Auto-extracted signal tx_load_data_word from protocol_control.vhd
+- Offset: `0x834`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_stuff_count
+Auto-extracted signal tx_load_stuff_count from protocol_control.vhd
+- Offset: `0x838`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_crc
+Auto-extracted signal tx_load_crc from protocol_control.vhd
+- Offset: `0x83c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_shift_ena
+Auto-extracted signal tx_shift_ena from protocol_control.vhd
+- Offset: `0x840`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_dominant
+Auto-extracted signal tx_dominant from protocol_control.vhd
+- Offset: `0x844`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_clear
+Auto-extracted signal rx_clear from protocol_control.vhd
+- Offset: `0x848`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_base_id
+Auto-extracted signal rx_store_base_id from protocol_control.vhd
+- Offset: `0x84c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_ext_id
+Auto-extracted signal rx_store_ext_id from protocol_control.vhd
+- Offset: `0x850`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_ide
+Auto-extracted signal rx_store_ide from protocol_control.vhd
+- Offset: `0x854`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_rtr
+Auto-extracted signal rx_store_rtr from protocol_control.vhd
+- Offset: `0x858`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_edl
+Auto-extracted signal rx_store_edl from protocol_control.vhd
+- Offset: `0x85c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_dlc
+Auto-extracted signal rx_store_dlc from protocol_control.vhd
+- Offset: `0x860`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_esi
+Auto-extracted signal rx_store_esi from protocol_control.vhd
+- Offset: `0x864`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_brs
+Auto-extracted signal rx_store_brs from protocol_control.vhd
+- Offset: `0x868`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_stuff_count
+Auto-extracted signal rx_store_stuff_count from protocol_control.vhd
+- Offset: `0x86c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_shift_ena
+Auto-extracted signal rx_shift_ena from protocol_control.vhd
+- Offset: `0x870`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_shift_in_sel
+Auto-extracted signal rx_shift_in_sel from protocol_control.vhd
+- Offset: `0x874`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from protocol_control.vhd
+- Offset: `0x878`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_dlc_d
+Auto-extracted signal rec_dlc_d from protocol_control.vhd
+- Offset: `0x87c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_dlc_q
+Auto-extracted signal rec_dlc_q from protocol_control.vhd
+- Offset: `0x880`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from protocol_control.vhd
+- Offset: `0x884`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_pload
+Auto-extracted signal ctrl_ctr_pload from protocol_control.vhd
+- Offset: `0x888`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_pload_val
+Auto-extracted signal ctrl_ctr_pload_val from protocol_control.vhd
+- Offset: `0x88c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_ena
+Auto-extracted signal ctrl_ctr_ena from protocol_control.vhd
+- Offset: `0x890`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_zero
+Auto-extracted signal ctrl_ctr_zero from protocol_control.vhd
+- Offset: `0x894`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_one
+Auto-extracted signal ctrl_ctr_one from protocol_control.vhd
+- Offset: `0x898`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_counted_byte
+Auto-extracted signal ctrl_counted_byte from protocol_control.vhd
+- Offset: `0x89c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_counted_byte_index
+Auto-extracted signal ctrl_counted_byte_index from protocol_control.vhd
+- Offset: `0x8a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_mem_index
+Auto-extracted signal ctrl_ctr_mem_index from protocol_control.vhd
+- Offset: `0x8a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_compl_ctr_ena
+Auto-extracted signal compl_ctr_ena from protocol_control.vhd
+- Offset: `0x8a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_clr
+Auto-extracted signal reinteg_ctr_clr from protocol_control.vhd
+- Offset: `0x8ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_enable
+Auto-extracted signal reinteg_ctr_enable from protocol_control.vhd
+- Offset: `0x8b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_expired
+Auto-extracted signal reinteg_ctr_expired from protocol_control.vhd
+- Offset: `0x8b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_ctr_clear
+Auto-extracted signal retr_ctr_clear from protocol_control.vhd
+- Offset: `0x8b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_ctr_add
+Auto-extracted signal retr_ctr_add from protocol_control.vhd
+- Offset: `0x8bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_limit_reached
+Auto-extracted signal retr_limit_reached from protocol_control.vhd
+- Offset: `0x8c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_form_err_i
+Auto-extracted signal form_err_i from protocol_control.vhd
+- Offset: `0x8c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ack_err_i
+Auto-extracted signal ack_err_i from protocol_control.vhd
+- Offset: `0x8c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_check
+Auto-extracted signal crc_check from protocol_control.vhd
+- Offset: `0x8cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_bit_err_arb
+Auto-extracted signal bit_err_arb from protocol_control.vhd
+- Offset: `0x8d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_match
+Auto-extracted signal crc_match from protocol_control.vhd
+- Offset: `0x8d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_err_i
+Auto-extracted signal crc_err_i from protocol_control.vhd
+- Offset: `0x8d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_clear_match_flag
+Auto-extracted signal crc_clear_match_flag from protocol_control.vhd
+- Offset: `0x8dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_src
+Auto-extracted signal crc_src from protocol_control.vhd
+- Offset: `0x8e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_err_pos
+Auto-extracted signal err_pos from protocol_control.vhd
+- Offset: `0x8e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_is_arbitration_i
+Auto-extracted signal is_arbitration_i from protocol_control.vhd
+- Offset: `0x8e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_bit_err_enable
+Auto-extracted signal bit_err_enable from protocol_control.vhd
+- Offset: `0x8ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_data_nbs_i
+Auto-extracted signal tx_data_nbs_i from protocol_control.vhd
+- Offset: `0x8f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_crc
+Auto-extracted signal rx_crc from protocol_control.vhd
+- Offset: `0x8f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_stuff_count
+Auto-extracted signal rx_stuff_count from protocol_control.vhd
+- Offset: `0x8f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fixed_stuff_i
+Auto-extracted signal fixed_stuff_i from protocol_control.vhd
+- Offset: `0x8fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from protocol_control.vhd
+- Offset: `0x900`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_alc_id_field
+Auto-extracted signal alc_id_field from protocol_control.vhd
+- Offset: `0x904`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_rom_ena
+Auto-extracted signal drv_rom_ena from protocol_control.vhd
+- Offset: `0x908`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_state_reg_ce
+Auto-extracted signal state_reg_ce from protocol_control_fsm.vhd
+- Offset: `0x90c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_transmitter
+Auto-extracted signal no_data_transmitter from protocol_control_fsm.vhd
+- Offset: `0x910`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_receiver
+Auto-extracted signal no_data_receiver from protocol_control_fsm.vhd
+- Offset: `0x914`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_field
+Auto-extracted signal no_data_field from protocol_control_fsm.vhd
+- Offset: `0x918`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_ctr_pload_i
+Auto-extracted signal ctrl_ctr_pload_i from protocol_control_fsm.vhd
+- Offset: `0x91c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_ctr_pload_unaliged
+Auto-extracted signal ctrl_ctr_pload_unaliged from protocol_control_fsm.vhd
+- Offset: `0x920`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_use_21
+Auto-extracted signal crc_use_21 from protocol_control_fsm.vhd
+- Offset: `0x924`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_use_17
+Auto-extracted signal crc_use_17 from protocol_control_fsm.vhd
+- Offset: `0x928`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_src_i
+Auto-extracted signal crc_src_i from protocol_control_fsm.vhd
+- Offset: `0x92c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_length_i
+Auto-extracted signal crc_length_i from protocol_control_fsm.vhd
+- Offset: `0x930`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tran_data_length
+Auto-extracted signal tran_data_length from protocol_control_fsm.vhd
+- Offset: `0x934`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_data_length
+Auto-extracted signal rec_data_length from protocol_control_fsm.vhd
+- Offset: `0x938`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_data_length_c
+Auto-extracted signal rec_data_length_c from protocol_control_fsm.vhd
+- Offset: `0x93c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_c
+Auto-extracted signal data_length_c from protocol_control_fsm.vhd
+- Offset: `0x940`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_shifted_c
+Auto-extracted signal data_length_shifted_c from protocol_control_fsm.vhd
+- Offset: `0x944`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_bits_c
+Auto-extracted signal data_length_bits_c from protocol_control_fsm.vhd
+- Offset: `0x948`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_is_fd_frame
+Auto-extracted signal is_fd_frame from protocol_control_fsm.vhd
+- Offset: `0x94c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_frame_start
+Auto-extracted signal frame_start from protocol_control_fsm.vhd
+- Offset: `0x950`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_ready
+Auto-extracted signal tx_frame_ready from protocol_control_fsm.vhd
+- Offset: `0x954`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ide_is_arbitration
+Auto-extracted signal ide_is_arbitration from protocol_control_fsm.vhd
+- Offset: `0x958`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_arbitration_lost_condition
+Auto-extracted signal arbitration_lost_condition from protocol_control_fsm.vhd
+- Offset: `0x95c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from protocol_control_fsm.vhd
+- Offset: `0x960`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_failed
+Auto-extracted signal tx_failed from protocol_control_fsm.vhd
+- Offset: `0x964`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_store_metadata_d
+Auto-extracted signal store_metadata_d from protocol_control_fsm.vhd
+- Offset: `0x968`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_store_data_d
+Auto-extracted signal store_data_d from protocol_control_fsm.vhd
+- Offset: `0x96c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_valid_d
+Auto-extracted signal rec_valid_d from protocol_control_fsm.vhd
+- Offset: `0x970`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_abort_d
+Auto-extracted signal rec_abort_d from protocol_control_fsm.vhd
+- Offset: `0x974`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_go_to_suspend
+Auto-extracted signal go_to_suspend from protocol_control_fsm.vhd
+- Offset: `0x978`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_go_to_stuff_count
+Auto-extracted signal go_to_stuff_count from protocol_control_fsm.vhd
+- Offset: `0x97c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_base_id_i
+Auto-extracted signal rx_store_base_id_i from protocol_control_fsm.vhd
+- Offset: `0x980`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_ext_id_i
+Auto-extracted signal rx_store_ext_id_i from protocol_control_fsm.vhd
+- Offset: `0x984`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_ide_i
+Auto-extracted signal rx_store_ide_i from protocol_control_fsm.vhd
+- Offset: `0x988`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_rtr_i
+Auto-extracted signal rx_store_rtr_i from protocol_control_fsm.vhd
+- Offset: `0x98c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_edl_i
+Auto-extracted signal rx_store_edl_i from protocol_control_fsm.vhd
+- Offset: `0x990`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_dlc_i
+Auto-extracted signal rx_store_dlc_i from protocol_control_fsm.vhd
+- Offset: `0x994`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_esi_i
+Auto-extracted signal rx_store_esi_i from protocol_control_fsm.vhd
+- Offset: `0x998`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_brs_i
+Auto-extracted signal rx_store_brs_i from protocol_control_fsm.vhd
+- Offset: `0x99c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_stuff_count_i
+Auto-extracted signal rx_store_stuff_count_i from protocol_control_fsm.vhd
+- Offset: `0x9a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_clear_i
+Auto-extracted signal rx_clear_i from protocol_control_fsm.vhd
+- Offset: `0x9a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_base_id_i
+Auto-extracted signal tx_load_base_id_i from protocol_control_fsm.vhd
+- Offset: `0x9a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_ext_id_i
+Auto-extracted signal tx_load_ext_id_i from protocol_control_fsm.vhd
+- Offset: `0x9ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_dlc_i
+Auto-extracted signal tx_load_dlc_i from protocol_control_fsm.vhd
+- Offset: `0x9b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_data_word_i
+Auto-extracted signal tx_load_data_word_i from protocol_control_fsm.vhd
+- Offset: `0x9b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_stuff_count_i
+Auto-extracted signal tx_load_stuff_count_i from protocol_control_fsm.vhd
+- Offset: `0x9b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_crc_i
+Auto-extracted signal tx_load_crc_i from protocol_control_fsm.vhd
+- Offset: `0x9bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_shift_ena_i
+Auto-extracted signal tx_shift_ena_i from protocol_control_fsm.vhd
+- Offset: `0x9c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_form_err_i
+Auto-extracted signal form_err_i from protocol_control_fsm.vhd
+- Offset: `0x9c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_i
+Auto-extracted signal ack_err_i from protocol_control_fsm.vhd
+- Offset: `0x9c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_flag
+Auto-extracted signal ack_err_flag from protocol_control_fsm.vhd
+- Offset: `0x9cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_flag_clr
+Auto-extracted signal ack_err_flag_clr from protocol_control_fsm.vhd
+- Offset: `0x9d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_err_i
+Auto-extracted signal crc_err_i from protocol_control_fsm.vhd
+- Offset: `0x9d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_arb_i
+Auto-extracted signal bit_err_arb_i from protocol_control_fsm.vhd
+- Offset: `0x9d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_switch_data
+Auto-extracted signal sp_control_switch_data from protocol_control_fsm.vhd
+- Offset: `0x9dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_switch_nominal
+Auto-extracted signal sp_control_switch_nominal from protocol_control_fsm.vhd
+- Offset: `0x9e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_switch_to_ssp
+Auto-extracted signal switch_to_ssp from protocol_control_fsm.vhd
+- Offset: `0x9e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_ce
+Auto-extracted signal sp_control_ce from protocol_control_fsm.vhd
+- Offset: `0x9e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_d
+Auto-extracted signal sp_control_d from protocol_control_fsm.vhd
+- Offset: `0x9ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_q_i
+Auto-extracted signal sp_control_q_i from protocol_control_fsm.vhd
+- Offset: `0x9f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ssp_reset_i
+Auto-extracted signal ssp_reset_i from protocol_control_fsm.vhd
+- Offset: `0x9f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sync_control_d
+Auto-extracted signal sync_control_d from protocol_control_fsm.vhd
+- Offset: `0x9f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sync_control_q
+Auto-extracted signal sync_control_q from protocol_control_fsm.vhd
+- Offset: `0x9fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_perform_hsync
+Auto-extracted signal perform_hsync from protocol_control_fsm.vhd
+- Offset: `0xa00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_primary_err_i
+Auto-extracted signal primary_err_i from protocol_control_fsm.vhd
+- Offset: `0xa04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_err_delim_late_i
+Auto-extracted signal err_delim_late_i from protocol_control_fsm.vhd
+- Offset: `0xa08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_err_active_i
+Auto-extracted signal set_err_active_i from protocol_control_fsm.vhd
+- Offset: `0xa0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_transmitter_i
+Auto-extracted signal set_transmitter_i from protocol_control_fsm.vhd
+- Offset: `0xa10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_receiver_i
+Auto-extracted signal set_receiver_i from protocol_control_fsm.vhd
+- Offset: `0xa14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_idle_i
+Auto-extracted signal set_idle_i from protocol_control_fsm.vhd
+- Offset: `0xa18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_first_err_delim_d
+Auto-extracted signal first_err_delim_d from protocol_control_fsm.vhd
+- Offset: `0xa1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_first_err_delim_q
+Auto-extracted signal first_err_delim_q from protocol_control_fsm.vhd
+- Offset: `0xa20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_stuff_enable_set
+Auto-extracted signal stuff_enable_set from protocol_control_fsm.vhd
+- Offset: `0xa24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_stuff_enable_clear
+Auto-extracted signal stuff_enable_clear from protocol_control_fsm.vhd
+- Offset: `0xa28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_destuff_enable_set
+Auto-extracted signal destuff_enable_set from protocol_control_fsm.vhd
+- Offset: `0xa2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_destuff_enable_clear
+Auto-extracted signal destuff_enable_clear from protocol_control_fsm.vhd
+- Offset: `0xa30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_disable
+Auto-extracted signal bit_err_disable from protocol_control_fsm.vhd
+- Offset: `0xa34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_disable_receiver
+Auto-extracted signal bit_err_disable_receiver from protocol_control_fsm.vhd
+- Offset: `0xa38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sof_pulse_i
+Auto-extracted signal sof_pulse_i from protocol_control_fsm.vhd
+- Offset: `0xa3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_compl_ctr_ena_i
+Auto-extracted signal compl_ctr_ena_i from protocol_control_fsm.vhd
+- Offset: `0xa40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tick_state_reg
+Auto-extracted signal tick_state_reg from protocol_control_fsm.vhd
+- Offset: `0xa44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_br_shifted_i
+Auto-extracted signal br_shifted_i from protocol_control_fsm.vhd
+- Offset: `0xa48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_is_arbitration_i
+Auto-extracted signal is_arbitration_i from protocol_control_fsm.vhd
+- Offset: `0xa4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_spec_enable_i
+Auto-extracted signal crc_spec_enable_i from protocol_control_fsm.vhd
+- Offset: `0xa50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_load_init_vect_i
+Auto-extracted signal load_init_vect_i from protocol_control_fsm.vhd
+- Offset: `0xa54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_drv_bus_off_reset_q
+Auto-extracted signal drv_bus_off_reset_q from protocol_control_fsm.vhd
+- Offset: `0xa58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_clear_i
+Auto-extracted signal retr_ctr_clear_i from protocol_control_fsm.vhd
+- Offset: `0xa5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_i
+Auto-extracted signal retr_ctr_add_i from protocol_control_fsm.vhd
+- Offset: `0xa60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_decrement_rec_i
+Auto-extracted signal decrement_rec_i from protocol_control_fsm.vhd
+- Offset: `0xa64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_block
+Auto-extracted signal retr_ctr_add_block from protocol_control_fsm.vhd
+- Offset: `0xa68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_block_clr
+Auto-extracted signal retr_ctr_add_block_clr from protocol_control_fsm.vhd
+- Offset: `0xa6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_block_txtb_unlock
+Auto-extracted signal block_txtb_unlock from protocol_control_fsm.vhd
+- Offset: `0xa70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_no_sof_d
+Auto-extracted signal tx_frame_no_sof_d from protocol_control_fsm.vhd
+- Offset: `0xa74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_no_sof_q
+Auto-extracted signal tx_frame_no_sof_q from protocol_control_fsm.vhd
+- Offset: `0xa78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_signal_upd
+Auto-extracted signal ctrl_signal_upd from protocol_control_fsm.vhd
+- Offset: `0xa7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_clr_bus_off_rst_flg
+Auto-extracted signal clr_bus_off_rst_flg from protocol_control_fsm.vhd
+- Offset: `0xa80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pex_on_fdf_enable
+Auto-extracted signal pex_on_fdf_enable from protocol_control_fsm.vhd
+- Offset: `0xa84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pex_on_res_enable
+Auto-extracted signal pex_on_res_enable from protocol_control_fsm.vhd
+- Offset: `0xa88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_data_nbs_prev
+Auto-extracted signal rx_data_nbs_prev from protocol_control_fsm.vhd
+- Offset: `0xa8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pexs_set
+Auto-extracted signal pexs_set from protocol_control_fsm.vhd
+- Offset: `0xa90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tran_frame_type_i
+Auto-extracted signal tran_frame_type_i from protocol_control_fsm.vhd
+- Offset: `0xa94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_txtb_clk_en_d
+Auto-extracted signal txtb_clk_en_d from protocol_control_fsm.vhd
+- Offset: `0xa98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_txtb_clk_en_q
+Auto-extracted signal txtb_clk_en_q from protocol_control_fsm.vhd
+- Offset: `0xa9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## reintegration_counter_reinteg_ctr_ce
+Auto-extracted signal reinteg_ctr_ce from reintegration_counter.vhd
+- Offset: `0xaa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## retransmitt_counter_retr_ctr_ce
+Auto-extracted signal retr_ctr_ce from retransmitt_counter.vhd
+- Offset: `0xaa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rst_sync_rff
+Auto-extracted signal rff from rst_sync.vhd
+- Offset: `0xaa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_erase_rx
+Auto-extracted signal drv_erase_rx from rx_buffer.vhd
+- Offset: `0xaac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_read_start
+Auto-extracted signal drv_read_start from rx_buffer.vhd
+- Offset: `0xab0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_clr_ovr
+Auto-extracted signal drv_clr_ovr from rx_buffer.vhd
+- Offset: `0xab4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_rtsopt
+Auto-extracted signal drv_rtsopt from rx_buffer.vhd
+- Offset: `0xab8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_pointer
+Auto-extracted signal read_pointer from rx_buffer.vhd
+- Offset: `0xabc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_pointer_inc_1
+Auto-extracted signal read_pointer_inc_1 from rx_buffer.vhd
+- Offset: `0xac0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer
+Auto-extracted signal write_pointer from rx_buffer.vhd
+- Offset: `0xac4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer_raw
+Auto-extracted signal write_pointer_raw from rx_buffer.vhd
+- Offset: `0xac8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer_ts
+Auto-extracted signal write_pointer_ts from rx_buffer.vhd
+- Offset: `0xacc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_mem_free_i
+Auto-extracted signal rx_mem_free_i from rx_buffer.vhd
+- Offset: `0xad0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_memory_write_data
+Auto-extracted signal memory_write_data from rx_buffer.vhd
+- Offset: `0xad4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_overrun_flg
+Auto-extracted signal data_overrun_flg from rx_buffer.vhd
+- Offset: `0xad8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_overrun_i
+Auto-extracted signal data_overrun_i from rx_buffer.vhd
+- Offset: `0xadc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_overrun_condition
+Auto-extracted signal overrun_condition from rx_buffer.vhd
+- Offset: `0xae0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_empty_i
+Auto-extracted signal rx_empty_i from rx_buffer.vhd
+- Offset: `0xae4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_is_free_word
+Auto-extracted signal is_free_word from rx_buffer.vhd
+- Offset: `0xae8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_commit_rx_frame
+Auto-extracted signal commit_rx_frame from rx_buffer.vhd
+- Offset: `0xaec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_commit_overrun_abort
+Auto-extracted signal commit_overrun_abort from rx_buffer.vhd
+- Offset: `0xaf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_increment
+Auto-extracted signal read_increment from rx_buffer.vhd
+- Offset: `0xaf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_raw_OK
+Auto-extracted signal write_raw_OK from rx_buffer.vhd
+- Offset: `0xaf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_raw_intent
+Auto-extracted signal write_raw_intent from rx_buffer.vhd
+- Offset: `0xafc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_ts
+Auto-extracted signal write_ts from rx_buffer.vhd
+- Offset: `0xb00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_stored_ts
+Auto-extracted signal stored_ts from rx_buffer.vhd
+- Offset: `0xb04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_selector
+Auto-extracted signal data_selector from rx_buffer.vhd
+- Offset: `0xb08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_store_ts_wr_ptr
+Auto-extracted signal store_ts_wr_ptr from rx_buffer.vhd
+- Offset: `0xb0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_inc_ts_wr_ptr
+Auto-extracted signal inc_ts_wr_ptr from rx_buffer.vhd
+- Offset: `0xb10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_reset_overrun_flag
+Auto-extracted signal reset_overrun_flag from rx_buffer.vhd
+- Offset: `0xb14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_frame_form_w
+Auto-extracted signal frame_form_w from rx_buffer.vhd
+- Offset: `0xb18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_timestamp_capture
+Auto-extracted signal timestamp_capture from rx_buffer.vhd
+- Offset: `0xb1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_timestamp_capture_ce
+Auto-extracted signal timestamp_capture_ce from rx_buffer.vhd
+- Offset: `0xb20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_write
+Auto-extracted signal RAM_write from rx_buffer.vhd
+- Offset: `0xb24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_data_out
+Auto-extracted signal RAM_data_out from rx_buffer.vhd
+- Offset: `0xb28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_write_address
+Auto-extracted signal RAM_write_address from rx_buffer.vhd
+- Offset: `0xb2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_read_address
+Auto-extracted signal RAM_read_address from rx_buffer.vhd
+- Offset: `0xb30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_d
+Auto-extracted signal rx_buf_res_n_d from rx_buffer.vhd
+- Offset: `0xb34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_q
+Auto-extracted signal rx_buf_res_n_q from rx_buffer.vhd
+- Offset: `0xb38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_q_scan
+Auto-extracted signal rx_buf_res_n_q_scan from rx_buffer.vhd
+- Offset: `0xb3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_ram_clk_en
+Auto-extracted signal rx_buf_ram_clk_en from rx_buffer.vhd
+- Offset: `0xb40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_clk_ram
+Auto-extracted signal clk_ram from rx_buffer.vhd
+- Offset: `0xb44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_fsm_rx_fsm_ce
+Auto-extracted signal rx_fsm_ce from rx_buffer_fsm.vhd
+- Offset: `0xb48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_fsm_cmd_join
+Auto-extracted signal cmd_join from rx_buffer_fsm.vhd
+- Offset: `0xb4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_pointers_write_pointer_raw_ce
+Auto-extracted signal write_pointer_raw_ce from rx_buffer_pointers.vhd
+- Offset: `0xb50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_pointers_write_pointer_ts_ce
+Auto-extracted signal write_pointer_ts_ce from rx_buffer_pointers.vhd
+- Offset: `0xb54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_address_i
+Auto-extracted signal port_a_address_i from rx_buffer_ram.vhd
+- Offset: `0xb58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_write_i
+Auto-extracted signal port_a_write_i from rx_buffer_ram.vhd
+- Offset: `0xb5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_data_in_i
+Auto-extracted signal port_a_data_in_i from rx_buffer_ram.vhd
+- Offset: `0xb60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_b_address_i
+Auto-extracted signal port_b_address_i from rx_buffer_ram.vhd
+- Offset: `0xb64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_b_data_out_i
+Auto-extracted signal port_b_data_out_i from rx_buffer_ram.vhd
+- Offset: `0xb68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_tst_ena
+Auto-extracted signal tst_ena from rx_buffer_ram.vhd
+- Offset: `0xb6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_tst_addr
+Auto-extracted signal tst_addr from rx_buffer_ram.vhd
+- Offset: `0xb70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_d
+Auto-extracted signal res_n_i_d from rx_shift_reg.vhd
+- Offset: `0xb74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_q
+Auto-extracted signal res_n_i_q from rx_shift_reg.vhd
+- Offset: `0xb78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_q_scan
+Auto-extracted signal res_n_i_q_scan from rx_shift_reg.vhd
+- Offset: `0xb7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_reg_q
+Auto-extracted signal rx_shift_reg_q from rx_shift_reg.vhd
+- Offset: `0xb80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_cmd
+Auto-extracted signal rx_shift_cmd from rx_shift_reg.vhd
+- Offset: `0xb84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_in_sel_demuxed
+Auto-extracted signal rx_shift_in_sel_demuxed from rx_shift_reg.vhd
+- Offset: `0xb88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from rx_shift_reg.vhd
+- Offset: `0xb8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from rx_shift_reg.vhd
+- Offset: `0xb90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_sample
+Auto-extracted signal sample from sample_mux.vhd
+- Offset: `0xb94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_prev_sample_d
+Auto-extracted signal prev_sample_d from sample_mux.vhd
+- Offset: `0xb98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_prev_sample_q
+Auto-extracted signal prev_sample_q from sample_mux.vhd
+- Offset: `0xb9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_req_input
+Auto-extracted signal req_input from segment_end_detector.vhd
+- Offset: `0xba0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_d
+Auto-extracted signal segm_end_req_capt_d from segment_end_detector.vhd
+- Offset: `0xba4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_q
+Auto-extracted signal segm_end_req_capt_q from segment_end_detector.vhd
+- Offset: `0xba8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_ce
+Auto-extracted signal segm_end_req_capt_ce from segment_end_detector.vhd
+- Offset: `0xbac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_clr
+Auto-extracted signal segm_end_req_capt_clr from segment_end_detector.vhd
+- Offset: `0xbb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_dq
+Auto-extracted signal segm_end_req_capt_dq from segment_end_detector.vhd
+- Offset: `0xbb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_nbt_valid
+Auto-extracted signal segm_end_nbt_valid from segment_end_detector.vhd
+- Offset: `0xbb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_dbt_valid
+Auto-extracted signal segm_end_dbt_valid from segment_end_detector.vhd
+- Offset: `0xbbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_nbt_dbt_valid
+Auto-extracted signal segm_end_nbt_dbt_valid from segment_end_detector.vhd
+- Offset: `0xbc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_tseg1_end_req_valid
+Auto-extracted signal tseg1_end_req_valid from segment_end_detector.vhd
+- Offset: `0xbc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_tseg2_end_req_valid
+Auto-extracted signal tseg2_end_req_valid from segment_end_detector.vhd
+- Offset: `0xbc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_h_sync_valid_i
+Auto-extracted signal h_sync_valid_i from segment_end_detector.vhd
+- Offset: `0xbcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segment_end_i
+Auto-extracted signal segment_end_i from segment_end_detector.vhd
+- Offset: `0xbd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_nbt_tq_active
+Auto-extracted signal nbt_tq_active from segment_end_detector.vhd
+- Offset: `0xbd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_dbt_tq_active
+Auto-extracted signal dbt_tq_active from segment_end_detector.vhd
+- Offset: `0xbd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_bt_ctr_clear_i
+Auto-extracted signal bt_ctr_clear_i from segment_end_detector.vhd
+- Offset: `0xbdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_shift_regs
+Auto-extracted signal shift_regs from shift_reg.vhd
+- Offset: `0xbe0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_next_shift_reg_val
+Auto-extracted signal next_shift_reg_val from shift_reg.vhd
+- Offset: `0xbe4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_byte_shift_reg_in
+Auto-extracted signal shift_reg_in from shift_reg_byte.vhd
+- Offset: `0xbe8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_preload_shift_regs
+Auto-extracted signal shift_regs from shift_reg_preload.vhd
+- Offset: `0xbec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_preload_next_shift_reg_val
+Auto-extracted signal next_shift_reg_val from shift_reg_preload.vhd
+- Offset: `0xbf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sig_sync_rff
+Auto-extracted signal rff from sig_sync.vhd
+- Offset: `0xbf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_d
+Auto-extracted signal btmc_d from ssp_generator.vhd
+- Offset: `0xbf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_q
+Auto-extracted signal btmc_q from ssp_generator.vhd
+- Offset: `0xbfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_add
+Auto-extracted signal btmc_add from ssp_generator.vhd
+- Offset: `0xc00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_ce
+Auto-extracted signal btmc_ce from ssp_generator.vhd
+- Offset: `0xc04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_meas_running_d
+Auto-extracted signal btmc_meas_running_d from ssp_generator.vhd
+- Offset: `0xc08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_meas_running_q
+Auto-extracted signal btmc_meas_running_q from ssp_generator.vhd
+- Offset: `0xc0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_d
+Auto-extracted signal sspc_d from ssp_generator.vhd
+- Offset: `0xc10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_q
+Auto-extracted signal sspc_q from ssp_generator.vhd
+- Offset: `0xc14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ce
+Auto-extracted signal sspc_ce from ssp_generator.vhd
+- Offset: `0xc18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_expired
+Auto-extracted signal sspc_expired from ssp_generator.vhd
+- Offset: `0xc1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_threshold
+Auto-extracted signal sspc_threshold from ssp_generator.vhd
+- Offset: `0xc20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_add
+Auto-extracted signal sspc_add from ssp_generator.vhd
+- Offset: `0xc24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_first_ssp_d
+Auto-extracted signal first_ssp_d from ssp_generator.vhd
+- Offset: `0xc28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_first_ssp_q
+Auto-extracted signal first_ssp_q from ssp_generator.vhd
+- Offset: `0xc2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ena_d
+Auto-extracted signal sspc_ena_d from ssp_generator.vhd
+- Offset: `0xc30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ena_q
+Auto-extracted signal sspc_ena_q from ssp_generator.vhd
+- Offset: `0xc34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_ssp_delay_padded
+Auto-extracted signal ssp_delay_padded from ssp_generator.vhd
+- Offset: `0xc38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_resync_edge
+Auto-extracted signal resync_edge from synchronisation_checker.vhd
+- Offset: `0xc3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_h_sync_edge
+Auto-extracted signal h_sync_edge from synchronisation_checker.vhd
+- Offset: `0xc40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_h_or_re_sync_edge
+Auto-extracted signal h_or_re_sync_edge from synchronisation_checker.vhd
+- Offset: `0xc44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag
+Auto-extracted signal sync_flag from synchronisation_checker.vhd
+- Offset: `0xc48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag_ce
+Auto-extracted signal sync_flag_ce from synchronisation_checker.vhd
+- Offset: `0xc4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag_nxt
+Auto-extracted signal sync_flag_nxt from synchronisation_checker.vhd
+- Offset: `0xc50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_reg_sel
+Auto-extracted signal reg_sel from test_registers_reg_map.vhd
+- Offset: `0xc54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_data_mux_in
+Auto-extracted signal read_data_mux_in from test_registers_reg_map.vhd
+- Offset: `0xc58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_data_mask_n
+Auto-extracted signal read_data_mask_n from test_registers_reg_map.vhd
+- Offset: `0xc5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_mux_ena
+Auto-extracted signal read_mux_ena from test_registers_reg_map.vhd
+- Offset: `0xc60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_rx_trig_req_q
+Auto-extracted signal rx_trig_req_q from trigger_generator.vhd
+- Offset: `0xc64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_d
+Auto-extracted signal tx_trig_req_flag_d from trigger_generator.vhd
+- Offset: `0xc68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_q
+Auto-extracted signal tx_trig_req_flag_q from trigger_generator.vhd
+- Offset: `0xc6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_dq
+Auto-extracted signal tx_trig_req_flag_dq from trigger_generator.vhd
+- Offset: `0xc70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_mux_tx_trigger_q
+Auto-extracted signal tx_trigger_q from trigger_mux.vhd
+- Offset: `0xc74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_d
+Auto-extracted signal trv_meas_progress_d from trv_delay_meas.vhd
+- Offset: `0xc78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_q
+Auto-extracted signal trv_meas_progress_q from trv_delay_meas.vhd
+- Offset: `0xc7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_del
+Auto-extracted signal trv_meas_progress_del from trv_delay_meas.vhd
+- Offset: `0xc80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_q
+Auto-extracted signal trv_delay_ctr_q from trv_delay_meas.vhd
+- Offset: `0xc84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_d
+Auto-extracted signal trv_delay_ctr_d from trv_delay_meas.vhd
+- Offset: `0xc88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_add
+Auto-extracted signal trv_delay_ctr_add from trv_delay_meas.vhd
+- Offset: `0xc8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_q_padded
+Auto-extracted signal trv_delay_ctr_q_padded from trv_delay_meas.vhd
+- Offset: `0xc90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_d
+Auto-extracted signal trv_delay_ctr_rst_d from trv_delay_meas.vhd
+- Offset: `0xc94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_q
+Auto-extracted signal trv_delay_ctr_rst_q from trv_delay_meas.vhd
+- Offset: `0xc98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_q_scan
+Auto-extracted signal trv_delay_ctr_rst_q_scan from trv_delay_meas.vhd
+- Offset: `0xc9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_shadow_ce
+Auto-extracted signal ssp_shadow_ce from trv_delay_meas.vhd
+- Offset: `0xca0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_delay_raw
+Auto-extracted signal ssp_delay_raw from trv_delay_meas.vhd
+- Offset: `0xca4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_delay_saturated
+Auto-extracted signal ssp_delay_saturated from trv_delay_meas.vhd
+- Offset: `0xca8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_sum
+Auto-extracted signal trv_delay_sum from trv_delay_meas.vhd
+- Offset: `0xcac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_select_buf_avail
+Auto-extracted signal select_buf_avail from tx_arbitrator.vhd
+- Offset: `0xcb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_selected_input
+Auto-extracted signal txtb_selected_input from tx_arbitrator.vhd
+- Offset: `0xcb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_timestamp
+Auto-extracted signal txtb_timestamp from tx_arbitrator.vhd
+- Offset: `0xcb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_timestamp_valid
+Auto-extracted signal timestamp_valid from tx_arbitrator.vhd
+- Offset: `0xcbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_select_index_changed
+Auto-extracted signal select_index_changed from tx_arbitrator.vhd
+- Offset: `0xcc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_validated_buffer
+Auto-extracted signal validated_buffer from tx_arbitrator.vhd
+- Offset: `0xcc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_ts_low_internal
+Auto-extracted signal ts_low_internal from tx_arbitrator.vhd
+- Offset: `0xcc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_dlc_dbl_buf
+Auto-extracted signal tran_dlc_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xccc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_is_rtr_dbl_buf
+Auto-extracted signal tran_is_rtr_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_ident_type_dbl_buf
+Auto-extracted signal tran_ident_type_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_type_dbl_buf
+Auto-extracted signal tran_frame_type_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_brs_dbl_buf
+Auto-extracted signal tran_brs_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_dlc_com
+Auto-extracted signal tran_dlc_com from tx_arbitrator.vhd
+- Offset: `0xce0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_is_rtr_com
+Auto-extracted signal tran_is_rtr_com from tx_arbitrator.vhd
+- Offset: `0xce4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_ident_type_com
+Auto-extracted signal tran_ident_type_com from tx_arbitrator.vhd
+- Offset: `0xce8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_type_com
+Auto-extracted signal tran_frame_type_com from tx_arbitrator.vhd
+- Offset: `0xcec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_brs_com
+Auto-extracted signal tran_brs_com from tx_arbitrator.vhd
+- Offset: `0xcf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_valid_com
+Auto-extracted signal tran_frame_valid_com from tx_arbitrator.vhd
+- Offset: `0xcf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_identifier_com
+Auto-extracted signal tran_identifier_com from tx_arbitrator.vhd
+- Offset: `0xcf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ts_lw_addr
+Auto-extracted signal load_ts_lw_addr from tx_arbitrator.vhd
+- Offset: `0xcfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ts_uw_addr
+Auto-extracted signal load_ts_uw_addr from tx_arbitrator.vhd
+- Offset: `0xd00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ffmt_w_addr
+Auto-extracted signal load_ffmt_w_addr from tx_arbitrator.vhd
+- Offset: `0xd04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ident_w_addr
+Auto-extracted signal load_ident_w_addr from tx_arbitrator.vhd
+- Offset: `0xd08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_ts_l_w
+Auto-extracted signal store_ts_l_w from tx_arbitrator.vhd
+- Offset: `0xd0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_md_w
+Auto-extracted signal store_md_w from tx_arbitrator.vhd
+- Offset: `0xd10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_ident_w
+Auto-extracted signal store_ident_w from tx_arbitrator.vhd
+- Offset: `0xd14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_buffer_md_w
+Auto-extracted signal buffer_md_w from tx_arbitrator.vhd
+- Offset: `0xd18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_last_txtb_index
+Auto-extracted signal store_last_txtb_index from tx_arbitrator.vhd
+- Offset: `0xd1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_frame_valid_com_set
+Auto-extracted signal frame_valid_com_set from tx_arbitrator.vhd
+- Offset: `0xd20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_frame_valid_com_clear
+Auto-extracted signal frame_valid_com_clear from tx_arbitrator.vhd
+- Offset: `0xd24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tx_arb_locked
+Auto-extracted signal tx_arb_locked from tx_arbitrator.vhd
+- Offset: `0xd28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_meta_clk_en
+Auto-extracted signal txtb_meta_clk_en from tx_arbitrator.vhd
+- Offset: `0xd2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_drv_tttm_ena
+Auto-extracted signal drv_tttm_ena from tx_arbitrator.vhd
+- Offset: `0xd30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_tx_arb_fsm_ce
+Auto-extracted signal tx_arb_fsm_ce from tx_arbitrator_fsm.vhd
+- Offset: `0xd34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_fsm_wait_state_d
+Auto-extracted signal fsm_wait_state_d from tx_arbitrator_fsm.vhd
+- Offset: `0xd38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_fsm_wait_state_q
+Auto-extracted signal fsm_wait_state_q from tx_arbitrator_fsm.vhd
+- Offset: `0xd3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_data_cache_tx_cache_mem
+Auto-extracted signal tx_cache_mem from tx_data_cache.vhd
+- Offset: `0xd40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_output
+Auto-extracted signal tx_sr_output from tx_shift_reg.vhd
+- Offset: `0xd44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_ce
+Auto-extracted signal tx_sr_ce from tx_shift_reg.vhd
+- Offset: `0xd48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_pload
+Auto-extracted signal tx_sr_pload from tx_shift_reg.vhd
+- Offset: `0xd4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_pload_val
+Auto-extracted signal tx_sr_pload_val from tx_shift_reg.vhd
+- Offset: `0xd50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_base_id
+Auto-extracted signal tx_base_id from tx_shift_reg.vhd
+- Offset: `0xd54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_ext_id
+Auto-extracted signal tx_ext_id from tx_shift_reg.vhd
+- Offset: `0xd58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_crc
+Auto-extracted signal tx_crc from tx_shift_reg.vhd
+- Offset: `0xd5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_bst_ctr_grey
+Auto-extracted signal bst_ctr_grey from tx_shift_reg.vhd
+- Offset: `0xd60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_bst_parity
+Auto-extracted signal bst_parity from tx_shift_reg.vhd
+- Offset: `0xd64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_stuff_count
+Auto-extracted signal stuff_count from tx_shift_reg.vhd
+- Offset: `0xd68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_user_accessible
+Auto-extracted signal txtb_user_accessible from txt_buffer.vhd
+- Offset: `0xd6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_hw_cbs
+Auto-extracted signal hw_cbs from txt_buffer.vhd
+- Offset: `0xd70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_sw_cbs
+Auto-extracted signal sw_cbs from txt_buffer.vhd
+- Offset: `0xd74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_unmask_data_ram
+Auto-extracted signal txtb_unmask_data_ram from txt_buffer.vhd
+- Offset: `0xd78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_port_b_data_i
+Auto-extracted signal txtb_port_b_data_i from txt_buffer.vhd
+- Offset: `0xd7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_write
+Auto-extracted signal ram_write from txt_buffer.vhd
+- Offset: `0xd80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_read_address
+Auto-extracted signal ram_read_address from txt_buffer.vhd
+- Offset: `0xd84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_ram_clk_en
+Auto-extracted signal txtb_ram_clk_en from txt_buffer.vhd
+- Offset: `0xd88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_clk_ram
+Auto-extracted signal clk_ram from txt_buffer.vhd
+- Offset: `0xd8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_abort_applied
+Auto-extracted signal abort_applied from txt_buffer_fsm.vhd
+- Offset: `0xd90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_txt_fsm_ce
+Auto-extracted signal txt_fsm_ce from txt_buffer_fsm.vhd
+- Offset: `0xd94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_go_to_failed
+Auto-extracted signal go_to_failed from txt_buffer_fsm.vhd
+- Offset: `0xd98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_transient_state
+Auto-extracted signal transient_state from txt_buffer_fsm.vhd
+- Offset: `0xd9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_address_i
+Auto-extracted signal port_a_address_i from txt_buffer_ram.vhd
+- Offset: `0xda0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_write_i
+Auto-extracted signal port_a_write_i from txt_buffer_ram.vhd
+- Offset: `0xda4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_data_in_i
+Auto-extracted signal port_a_data_in_i from txt_buffer_ram.vhd
+- Offset: `0xda8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_b_address_i
+Auto-extracted signal port_b_address_i from txt_buffer_ram.vhd
+- Offset: `0xdac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_b_data_out_i
+Auto-extracted signal port_b_data_out_i from txt_buffer_ram.vhd
+- Offset: `0xdb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_tst_ena
+Auto-extracted signal tst_ena from txt_buffer_ram.vhd
+- Offset: `0xdb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_tst_addr
+Auto-extracted signal tst_addr from txt_buffer_ram.vhd
+- Offset: `0xdb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_be_active
+Auto-extracted signal be_active from access_signaler.vhd
+- Offset: `0xdbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_in
+Auto-extracted signal access_in from access_signaler.vhd
+- Offset: `0xdc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_active
+Auto-extracted signal access_active from access_signaler.vhd
+- Offset: `0xdc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_active_reg
+Auto-extracted signal access_active_reg from access_signaler.vhd
+- Offset: `0xdc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## address_decoder_addr_dec_i
+Auto-extracted signal addr_dec_i from address_decoder.vhd
+- Offset: `0xdcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## address_decoder_addr_dec_enabled_i
+Auto-extracted signal addr_dec_enabled_i from address_decoder.vhd
+- Offset: `0xdd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+
+
+
+
+## carfield_regs
+
+
+
+### carfield_regs.md
+
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                            |
+|:-----------------------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| carfield.[`VERSION0`](#version0)                                             | 0x0      |        4 | Cheshire sha256 commit                                                 |
+| carfield.[`VERSION1`](#version1)                                             | 0x4      |        4 | Safety Island sha256 commit                                            |
+| carfield.[`VERSION2`](#version2)                                             | 0x8      |        4 | Security Island sha256 commit                                          |
+| carfield.[`VERSION3`](#version3)                                             | 0xc      |        4 | PULP Cluster sha256 commit                                             |
+| carfield.[`VERSION4`](#version4)                                             | 0x10     |        4 | Spatz CLuster sha256 commit                                            |
+| carfield.[`JEDEC_IDCODE`](#jedec_idcode)                                     | 0x14     |        4 | JEDEC ID CODE -TODO assign-                                            |
+| carfield.[`GENERIC_SCRATCH0`](#generic_scratch0)                             | 0x18     |        4 | Scratch                                                                |
+| carfield.[`GENERIC_SCRATCH1`](#generic_scratch1)                             | 0x1c     |        4 | Scratch                                                                |
+| carfield.[`HOST_RST`](#host_rst)                                             | 0x20     |        4 | Host Domain reset -active high, inverted in HW-                        |
+| carfield.[`PERIPH_RST`](#periph_rst)                                         | 0x24     |        4 | Periph Domain reset -active high, inverted in HW-                      |
+| carfield.[`SAFETY_ISLAND_RST`](#safety_island_rst)                           | 0x28     |        4 | Safety Island reset -active high, inverted in HW-                      |
+| carfield.[`SECURITY_ISLAND_RST`](#security_island_rst)                       | 0x2c     |        4 | Security Island reset -active high, inverted in HW-                    |
+| carfield.[`PULP_CLUSTER_RST`](#pulp_cluster_rst)                             | 0x30     |        4 | PULP Cluster reset -active high, inverted in HW-                       |
+| carfield.[`SPATZ_CLUSTER_RST`](#spatz_cluster_rst)                           | 0x34     |        4 | Spatz Cluster reset -active high, inverted in HW-                      |
+| carfield.[`L2_RST`](#l2_rst)                                                 | 0x38     |        4 | L2 reset -active high, inverted in HW-                                 |
+| carfield.[`PERIPH_ISOLATE`](#periph_isolate)                                 | 0x3c     |        4 | Periph Domain  AXI isolate                                             |
+| carfield.[`SAFETY_ISLAND_ISOLATE`](#safety_island_isolate)                   | 0x40     |        4 | Safety Island AXI isolate                                              |
+| carfield.[`SECURITY_ISLAND_ISOLATE`](#security_island_isolate)               | 0x44     |        4 | Security Island AXI isolate                                            |
+| carfield.[`PULP_CLUSTER_ISOLATE`](#pulp_cluster_isolate)                     | 0x48     |        4 | PULP Cluster AXI isolate                                               |
+| carfield.[`SPATZ_CLUSTER_ISOLATE`](#spatz_cluster_isolate)                   | 0x4c     |        4 | Spatz Cluster AXI isolate                                              |
+| carfield.[`L2_ISOLATE`](#l2_isolate)                                         | 0x50     |        4 | L2 AXI isolate                                                         |
+| carfield.[`PERIPH_ISOLATE_STATUS`](#periph_isolate_status)                   | 0x54     |        4 | Periph Domain AXI isolate status                                       |
+| carfield.[`SAFETY_ISLAND_ISOLATE_STATUS`](#safety_island_isolate_status)     | 0x58     |        4 | Safety Island AXI isolate status                                       |
+| carfield.[`SECURITY_ISLAND_ISOLATE_STATUS`](#security_island_isolate_status) | 0x5c     |        4 | Security Island AXI isolate status                                     |
+| carfield.[`PULP_CLUSTER_ISOLATE_STATUS`](#pulp_cluster_isolate_status)       | 0x60     |        4 | PULP Cluster AXI isolate status                                        |
+| carfield.[`SPATZ_CLUSTER_ISOLATE_STATUS`](#spatz_cluster_isolate_status)     | 0x64     |        4 | Spatz Cluster AXI isolate status                                       |
+| carfield.[`L2_ISOLATE_STATUS`](#l2_isolate_status)                           | 0x68     |        4 | L2 AXI isolate status                                                  |
+| carfield.[`PERIPH_CLK_EN`](#periph_clk_en)                                   | 0x6c     |        4 | Periph Domain clk gate enable                                          |
+| carfield.[`SAFETY_ISLAND_CLK_EN`](#safety_island_clk_en)                     | 0x70     |        4 | Safety Island clk gate enable                                          |
+| carfield.[`SECURITY_ISLAND_CLK_EN`](#security_island_clk_en)                 | 0x74     |        4 | Security Island clk gate enable                                        |
+| carfield.[`PULP_CLUSTER_CLK_EN`](#pulp_cluster_clk_en)                       | 0x78     |        4 | PULP Cluster clk gate enable                                           |
+| carfield.[`SPATZ_CLUSTER_CLK_EN`](#spatz_cluster_clk_en)                     | 0x7c     |        4 | Spatz Cluster clk gate enable                                          |
+| carfield.[`L2_CLK_EN`](#l2_clk_en)                                           | 0x80     |        4 | Shared L2 memory clk gate enable                                       |
+| carfield.[`PERIPH_CLK_SEL`](#periph_clk_sel)                                 | 0x84     |        4 | Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SAFETY_ISLAND_CLK_SEL`](#safety_island_clk_sel)                   | 0x88     |        4 | Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SECURITY_ISLAND_CLK_SEL`](#security_island_clk_sel)               | 0x8c     |        4 | Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) |
+| carfield.[`PULP_CLUSTER_CLK_SEL`](#pulp_cluster_clk_sel)                     | 0x90     |        4 | PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)    |
+| carfield.[`SPATZ_CLUSTER_CLK_SEL`](#spatz_cluster_clk_sel)                   | 0x94     |        4 | Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`L2_CLK_SEL`](#l2_clk_sel)                                         | 0x98     |        4 | L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)       |
+| carfield.[`PERIPH_CLK_DIV_VALUE`](#periph_clk_div_value)                     | 0x9c     |        4 | Periph Domain clk divider value                                        |
+| carfield.[`SAFETY_ISLAND_CLK_DIV_VALUE`](#safety_island_clk_div_value)       | 0xa0     |        4 | Safety Island clk divider value                                        |
+| carfield.[`SECURITY_ISLAND_CLK_DIV_VALUE`](#security_island_clk_div_value)   | 0xa4     |        4 | Security Island clk divider value                                      |
+| carfield.[`PULP_CLUSTER_CLK_DIV_VALUE`](#pulp_cluster_clk_div_value)         | 0xa8     |        4 | PULP Cluster clk divider value                                         |
+| carfield.[`SPATZ_CLUSTER_CLK_DIV_VALUE`](#spatz_cluster_clk_div_value)       | 0xac     |        4 | Spatz Cluster clk divider value                                        |
+| carfield.[`L2_CLK_DIV_VALUE`](#l2_clk_div_value)                             | 0xb0     |        4 | L2 Memory clk divider value                                            |
+| carfield.[`HOST_FETCH_ENABLE`](#host_fetch_enable)                           | 0xb4     |        4 | Host Domain fetch enable                                               |
+| carfield.[`SAFETY_ISLAND_FETCH_ENABLE`](#safety_island_fetch_enable)         | 0xb8     |        4 | Safety Island fetch enable                                             |
+| carfield.[`SECURITY_ISLAND_FETCH_ENABLE`](#security_island_fetch_enable)     | 0xbc     |        4 | Security Island fetch enable                                           |
+| carfield.[`PULP_CLUSTER_FETCH_ENABLE`](#pulp_cluster_fetch_enable)           | 0xc0     |        4 | PULP Cluster fetch enable                                              |
+| carfield.[`SPATZ_CLUSTER_DEBUG_REQ`](#spatz_cluster_debug_req)               | 0xc4     |        4 | Spatz Cluster debug req                                                |
+| carfield.[`HOST_BOOT_ADDR`](#host_boot_addr)                                 | 0xc8     |        4 | Host boot address                                                      |
+| carfield.[`SAFETY_ISLAND_BOOT_ADDR`](#safety_island_boot_addr)               | 0xcc     |        4 | Safety Island boot address                                             |
+| carfield.[`SECURITY_ISLAND_BOOT_ADDR`](#security_island_boot_addr)           | 0xd0     |        4 | Security Island boot address                                           |
+| carfield.[`PULP_CLUSTER_BOOT_ADDR`](#pulp_cluster_boot_addr)                 | 0xd4     |        4 | PULP Cluster boot address                                              |
+| carfield.[`SPATZ_CLUSTER_BOOT_ADDR`](#spatz_cluster_boot_addr)               | 0xd8     |        4 | Spatz Cluster boot address                                             |
+| carfield.[`PULP_CLUSTER_BOOT_ENABLE`](#pulp_cluster_boot_enable)             | 0xdc     |        4 | PULP Cluster boot enable                                               |
+| carfield.[`SPATZ_CLUSTER_BUSY`](#spatz_cluster_busy)                         | 0xe0     |        4 | Spatz Cluster busy                                                     |
+| carfield.[`PULP_CLUSTER_BUSY`](#pulp_cluster_busy)                           | 0xe4     |        4 | PULP Cluster busy                                                      |
+| carfield.[`PULP_CLUSTER_EOC`](#pulp_cluster_eoc)                             | 0xe8     |        4 | PULP Cluster end of computation                                        |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_EN`](#eth_rgmii_phy_clk_div_en)             | 0xec     |        4 | Ethernet RGMII PHY clock divider enable bit                            |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_VALUE`](#eth_rgmii_phy_clk_div_value)       | 0xf0     |        4 | Ethernet RGMII PHY clock divider value                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_EN`](#eth_mdio_clk_div_en)                       | 0xf4     |        4 | Ethernet MDIO clock divider enable bit                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_VALUE`](#eth_mdio_clk_div_value)                 | 0xf8     |        4 | Ethernet MDIO clock divider value                                      |
+
+## VERSION0
+Cheshire sha256 commit
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION0", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION0 |               |
+
+## VERSION1
+Safety Island sha256 commit
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION1", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION1 |               |
+
+## VERSION2
+Security Island sha256 commit
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION2", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION2 |               |
+
+## VERSION3
+PULP Cluster sha256 commit
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION3", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION3 |               |
+
+## VERSION4
+Spatz CLuster sha256 commit
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION4", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION4 |               |
+
+## JEDEC_IDCODE
+JEDEC ID CODE -TODO assign-
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "JEDEC_IDCODE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description   |
+|:------:|:------:|:-------:|:-------------|:--------------|
+|  31:0  |   rw   |   0x0   | JEDEC_IDCODE |               |
+
+## GENERIC_SCRATCH0
+Scratch
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH0 |               |
+
+## GENERIC_SCRATCH1
+Scratch
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH1 |               |
+
+## HOST_RST
+Host Domain reset -active high, inverted in HW-
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_RST", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:1  |        |         |          | Reserved      |
+|   0    |   ro   |   0x0   | HOST_RST |               |
+
+## PERIPH_RST
+Periph Domain reset -active high, inverted in HW-
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_RST |               |
+
+## SAFETY_ISLAND_RST
+Safety Island reset -active high, inverted in HW-
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_RST |               |
+
+## SECURITY_ISLAND_RST
+Security Island reset -active high, inverted in HW-
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_RST |               |
+
+## PULP_CLUSTER_RST
+PULP Cluster reset -active high, inverted in HW-
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_RST |               |
+
+## SPATZ_CLUSTER_RST
+Spatz Cluster reset -active high, inverted in HW-
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_RST |               |
+
+## L2_RST
+L2 reset -active high, inverted in HW-
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:1  |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | L2_RST |               |
+
+## PERIPH_ISOLATE
+Periph Domain  AXI isolate
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:1  |        |         |                | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE |               |
+
+## SAFETY_ISLAND_ISOLATE
+Safety Island AXI isolate
+- Offset: `0x40`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SAFETY_ISLAND_ISOLATE |               |
+
+## SECURITY_ISLAND_ISOLATE
+Security Island AXI isolate
+- Offset: `0x44`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   rw   |   0x1   | SECURITY_ISLAND_ISOLATE |               |
+
+## PULP_CLUSTER_ISOLATE
+PULP Cluster AXI isolate
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x1   | PULP_CLUSTER_ISOLATE |               |
+
+## SPATZ_CLUSTER_ISOLATE
+Spatz Cluster AXI isolate
+- Offset: `0x4c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SPATZ_CLUSTER_ISOLATE |               |
+
+## L2_ISOLATE
+L2 AXI isolate
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE |               |
+
+## PERIPH_ISOLATE_STATUS
+Periph Domain AXI isolate status
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE_STATUS |               |
+
+## SAFETY_ISLAND_ISOLATE_STATUS
+Safety Island AXI isolate status
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_ISOLATE_STATUS |               |
+
+## SECURITY_ISLAND_ISOLATE_STATUS
+Security Island AXI isolate status
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                           | Description   |
+|:------:|:------:|:-------:|:-------------------------------|:--------------|
+|  31:1  |        |         |                                | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_ISOLATE_STATUS |               |
+
+## PULP_CLUSTER_ISOLATE_STATUS
+PULP Cluster AXI isolate status
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+|  31:1  |        |         |                             | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_ISOLATE_STATUS |               |
+
+## SPATZ_CLUSTER_ISOLATE_STATUS
+Spatz Cluster AXI isolate status
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_ISOLATE_STATUS |               |
+
+## L2_ISOLATE_STATUS
+L2 AXI isolate status
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE_STATUS |               |
+
+## PERIPH_CLK_EN
+Periph Domain clk gate enable
+- Offset: `0x6c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x1   | PERIPH_CLK_EN |               |
+
+## SAFETY_ISLAND_CLK_EN
+Safety Island clk gate enable
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_CLK_EN |               |
+
+## SECURITY_ISLAND_CLK_EN
+Security Island clk gate enable
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+|  31:1  |        |         |                        | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_CLK_EN |               |
+
+## PULP_CLUSTER_CLK_EN
+PULP Cluster clk gate enable
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_CLK_EN |               |
+
+## SPATZ_CLUSTER_CLK_EN
+Spatz Cluster clk gate enable
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_CLK_EN |               |
+
+## L2_CLK_EN
+Shared L2 memory clk gate enable
+- Offset: `0x80`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:1  |        |         |           | Reserved      |
+|   0    |   rw   |   0x1   | L2_CLK_EN |               |
+
+## PERIPH_CLK_SEL
+Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x84`
+- Reset default: `0x2`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:2  |        |         |                | Reserved      |
+|  1:0   |   rw   |   0x2   | PERIPH_CLK_SEL |               |
+
+## SAFETY_ISLAND_CLK_SEL
+Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x88`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SAFETY_ISLAND_CLK_SEL |               |
+
+## SECURITY_ISLAND_CLK_SEL
+Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x8c`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x1   | SECURITY_ISLAND_CLK_SEL |               |
+
+## PULP_CLUSTER_CLK_SEL
+PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x90`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:2  |        |         |                      | Reserved      |
+|  1:0   |   rw   |   0x1   | PULP_CLUSTER_CLK_SEL |               |
+
+## SPATZ_CLUSTER_CLK_SEL
+Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x94`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SPATZ_CLUSTER_CLK_SEL |               |
+
+## L2_CLK_SEL
+L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x98`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:2  |        |         |            | Reserved      |
+|  1:0   |   rw   |   0x1   | L2_CLK_SEL |               |
+
+## PERIPH_CLK_DIV_VALUE
+Periph Domain clk divider value
+- Offset: `0x9c`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+| 31:24  |        |         |                      | Reserved      |
+|  23:0  |   rw   |   0x1   | PERIPH_CLK_DIV_VALUE |               |
+
+## SAFETY_ISLAND_CLK_DIV_VALUE
+Safety Island clk divider value
+- Offset: `0xa0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SAFETY_ISLAND_CLK_DIV_VALUE |               |
+
+## SECURITY_ISLAND_CLK_DIV_VALUE
+Security Island clk divider value
+- Offset: `0xa4`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          | Description   |
+|:------:|:------:|:-------:|:------------------------------|:--------------|
+| 31:24  |        |         |                               | Reserved      |
+|  23:0  |   rw   |   0x1   | SECURITY_ISLAND_CLK_DIV_VALUE |               |
+
+## PULP_CLUSTER_CLK_DIV_VALUE
+PULP Cluster clk divider value
+- Offset: `0xa8`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+| 31:24  |        |         |                            | Reserved      |
+|  23:0  |   rw   |   0x1   | PULP_CLUSTER_CLK_DIV_VALUE |               |
+
+## SPATZ_CLUSTER_CLK_DIV_VALUE
+Spatz Cluster clk divider value
+- Offset: `0xac`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SPATZ_CLUSTER_CLK_DIV_VALUE |               |
+
+## L2_CLK_DIV_VALUE
+L2 Memory clk divider value
+- Offset: `0xb0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:24  |        |         |                  | Reserved      |
+|  23:0  |   rw   |   0x1   | L2_CLK_DIV_VALUE |               |
+
+## HOST_FETCH_ENABLE
+Host Domain fetch enable
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_FETCH_ENABLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | HOST_FETCH_ENABLE |               |
+
+## SAFETY_ISLAND_FETCH_ENABLE
+Safety Island fetch enable
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+|  31:1  |        |         |                            | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_FETCH_ENABLE |               |
+
+## SECURITY_ISLAND_FETCH_ENABLE
+Security Island fetch enable
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_FETCH_ENABLE |               |
+
+## PULP_CLUSTER_FETCH_ENABLE
+PULP Cluster fetch enable
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|  31:1  |        |         |                           | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_FETCH_ENABLE |               |
+
+## SPATZ_CLUSTER_DEBUG_REQ
+Spatz Cluster debug req
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_DEBUG_REQ", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x0   | SPATZ_CLUSTER_DEBUG_REQ |               |
+
+## HOST_BOOT_ADDR
+Host boot address
+- Offset: `0xc8`
+- Reset default: `0x1000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:0  |   rw   | 0x1000  | HOST_BOOT_ADDR |               |
+
+## SAFETY_ISLAND_BOOT_ADDR
+Safety Island boot address
+- Offset: `0xcc`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SAFETY_ISLAND_BOOT_ADDR |               |
+
+## SECURITY_ISLAND_BOOT_ADDR
+Security Island boot address
+- Offset: `0xd0`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                      | Description   |
+|:------:|:------:|:----------:|:--------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SECURITY_ISLAND_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ADDR
+PULP Cluster boot address
+- Offset: `0xd4`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                   | Description   |
+|:------:|:------:|:----------:|:-----------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | PULP_CLUSTER_BOOT_ADDR |               |
+
+## SPATZ_CLUSTER_BOOT_ADDR
+Spatz Cluster boot address
+- Offset: `0xd8`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SPATZ_CLUSTER_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ENABLE
+PULP Cluster boot enable
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_BOOT_ENABLE |               |
+
+## SPATZ_CLUSTER_BUSY
+Spatz Cluster busy
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:1  |        |         |                    | Reserved      |
+|   0    |   ro   |   0x0   | SPATZ_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_BUSY
+PULP Cluster busy
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_EOC
+PULP Cluster end of computation
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_EOC", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_EOC |               |
+
+## ETH_RGMII_PHY_CLK_DIV_EN
+Ethernet RGMII PHY clock divider enable bit
+- Offset: `0xec`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x1   | ETH_RGMII_PHY_CLK_DIV_EN |               |
+
+## ETH_RGMII_PHY_CLK_DIV_VALUE
+Ethernet RGMII PHY clock divider value
+- Offset: `0xf0`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:20  |        |         |                             | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_RGMII_PHY_CLK_DIV_VALUE |               |
+
+## ETH_MDIO_CLK_DIV_EN
+Ethernet MDIO clock divider enable bit
+- Offset: `0xf4`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x1   | ETH_MDIO_CLK_DIV_EN |               |
+
+## ETH_MDIO_CLK_DIV_VALUE
+Ethernet MDIO clock divider value
+- Offset: `0xf8`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:20  |        |         |                        | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_MDIO_CLK_DIV_VALUE |               |
+
+
+
+
+
+## cheshire
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                       | Offset   |   Length | Description                                        |
+|:-------------------------------------------|:---------|---------:|:---------------------------------------------------|
+| cheshire.[`scratch_0`](#scratch)           | 0x0      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_1`](#scratch)           | 0x4      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_2`](#scratch)           | 0x8      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_3`](#scratch)           | 0xc      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_4`](#scratch)           | 0x10     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_5`](#scratch)           | 0x14     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_6`](#scratch)           | 0x18     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_7`](#scratch)           | 0x1c     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_8`](#scratch)           | 0x20     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_9`](#scratch)           | 0x24     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_10`](#scratch)          | 0x28     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_11`](#scratch)          | 0x2c     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_12`](#scratch)          | 0x30     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_13`](#scratch)          | 0x34     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_14`](#scratch)          | 0x38     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_15`](#scratch)          | 0x3c     |        4 | Registers for use by software                      |
+| cheshire.[`boot_mode`](#boot_mode)         | 0x40     |        4 | Method to load boot code (connected to input pins) |
+| cheshire.[`rtc_freq`](#rtc_freq)           | 0x44     |        4 | Frequency (Hz) configured for RTC                  |
+| cheshire.[`platform_rom`](#platform_rom)   | 0x48     |        4 | Address of platform ROM                            |
+| cheshire.[`num_int_harts`](#num_int_harts) | 0x4c     |        4 | Number of internal harts                           |
+| cheshire.[`hw_features`](#hw_features)     | 0x50     |        4 | Specifies which hardware features are available    |
+| cheshire.[`llc_size`](#llc_size)           | 0x54     |        4 | Total size of LLC in bytes                         |
+| cheshire.[`vga_params`](#vga_params)       | 0x58     |        4 | VGA hardware parameters                            |
+
+## scratch
+Registers for use by software
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name       | Offset   |
+|:-----------|:---------|
+| scratch_0  | 0x0      |
+| scratch_1  | 0x4      |
+| scratch_2  | 0x8      |
+| scratch_3  | 0xc      |
+| scratch_4  | 0x10     |
+| scratch_5  | 0x14     |
+| scratch_6  | 0x18     |
+| scratch_7  | 0x1c     |
+| scratch_8  | 0x20     |
+| scratch_9  | 0x24     |
+| scratch_10 | 0x28     |
+| scratch_11 | 0x2c     |
+| scratch_12 | 0x30     |
+| scratch_13 | 0x34     |
+| scratch_14 | 0x38     |
+| scratch_15 | 0x3c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "scratch", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                   |
+|:------:|:------:|:-------:|:--------|:------------------------------|
+|  31:0  |   rw   |   0x0   | scratch | Registers for use by software |
+
+## boot_mode
+Method to load boot code (connected to input pins)
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "boot_mode", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+|  31:2  |        |         | Reserved                           |
+|  1:0   |   ro   |    x    | [boot_mode](#boot_mode--boot_mode) |
+
+### boot_mode . boot_mode
+Method to load boot code (connected to input pins)
+
+| Value   | Name          | Description                          |
+|:--------|:--------------|:-------------------------------------|
+| 0x0     | passive       | Wait for external preload and launch |
+| 0x1     | spi_sdcard    | Boot from SD Card in SPI mode        |
+| 0x2     | spi_s25fs512s | Boot from S25FS512S SPI NOR flash    |
+| 0x3     | i2c_24xx1025  | Boot from 24xx1025 I2C EEPROM        |
+
+
+## rtc_freq
+Frequency (Hz) configured for RTC
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ref_freq", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------|
+|  31:0  |   ro   |    x    | ref_freq | Frequency (Hz) configured for RTC |
+
+## platform_rom
+Address of platform ROM
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "platform_rom", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description             |
+|:------:|:------:|:-------:|:-------------|:------------------------|
+|  31:0  |   ro   |    x    | platform_rom | Address of platform ROM |
+
+## num_int_harts
+Number of internal harts
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_harts", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description              |
+|:------:|:------:|:-------:|:----------|:-------------------------|
+|  31:0  |   ro   |    x    | num_harts | Number of internal harts |
+
+## hw_features
+Specifies which hardware features are available
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootrom", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "llc", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "uart", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "spi_host", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "i2c", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "gpio", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "dma", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "serial_link", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "vga", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "axirt", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "clic", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "irq_router", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bus_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                      |
+|:------:|:------:|:-------:|:------------|:---------------------------------|
+| 31:13  |        |         |             | Reserved                         |
+|   12   |   ro   |    x    | bus_err     | Whether UNBENT is available      |
+|   11   |   ro   |    x    | irq_router  | Whether IRQ router is available  |
+|   10   |   ro   |    x    | clic        | Whether CLIC is available        |
+|   9    |   ro   |    x    | axirt       | Whether AXI RT is available      |
+|   8    |   ro   |    x    | vga         | Whether VGA is available         |
+|   7    |   ro   |    x    | serial_link | Whether serial link is available |
+|   6    |   ro   |    x    | dma         | Whether DMA is available         |
+|   5    |   ro   |    x    | gpio        | Whether GPIO is available        |
+|   4    |   ro   |    x    | i2c         | Whether I2C is available         |
+|   3    |   ro   |    x    | spi_host    | Whether SPI host is available    |
+|   2    |   ro   |    x    | uart        | Whether UART is available        |
+|   1    |   ro   |    x    | llc         | Whether LLC is available         |
+|   0    |   ro   |    x    | bootrom     | Whether boot ROM is available    |
+
+## llc_size
+Total size of LLC in bytes
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "llc_size", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                |
+|:------:|:------:|:-------:|:---------|:---------------------------|
+|  31:0  |   ro   |    x    | llc_size | Total size of LLC in bytes |
+
+## vga_params
+VGA hardware parameters
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "red_width", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "green_width", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "blue_width", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description         |
+|:------:|:------:|:-------:|:------------|:--------------------|
+| 31:24  |        |         |             | Reserved            |
+| 23:16  |   ro   |    x    | blue_width  | Blue channel width  |
+|  15:8  |   ro   |    x    | green_width | Green channel width |
+|  7:0   |   ro   |    x    | red_width   | Red channel width   |
+
+
+
+
+
+## clic
+
+
+
+### clicint_registers.md
+
+## Summary
+
+| Name                          | Offset   |   Length | Description                                           |
+|:------------------------------|:---------|---------:|:------------------------------------------------------|
+| CLICINT.[`CLICINT`](#clicint) | 0x0      |        4 | CLIC interrupt pending, enable, attribute and control |
+
+## CLICINT
+CLIC interrupt pending, enable, attribute and control
+- Offset: `0x0`
+- Reset default: `0xc00000`
+- Reset mask: `0xffc70101`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "IE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "ATTR_SHV", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ATTR_TRIG", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "ATTR_MODE", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "CTL", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                  |
+|:------:|:------:|:-------:|:----------|:---------------------------------------------|
+| 31:24  |   rw   |   0x0   | CTL       | interrupt control for interrupt              |
+| 23:22  |   rw   |   0x3   | ATTR_MODE | privilege mode of this interrupt             |
+| 21:19  |        |         |           | Reserved                                     |
+| 18:17  |   rw   |   0x0   | ATTR_TRIG | specify trigger type for this interrupt      |
+|   16   |   rw   |   0x0   | ATTR_SHV  | enable hardware vectoring for this interrupt |
+|  15:9  |        |         |           | Reserved                                     |
+|   8    |   rw   |   0x0   | IE        | interrupt enable for interrupt               |
+|  7:1   |        |         |           | Reserved                                     |
+|   0    |   rw   |   0x0   | IP        | interrupt pending for interrupt              |
+
+
+
+
+
+### clictv_registers.md
+
+## Summary
+
+| Name                             | Offset   |   Length | Description                   |
+|:---------------------------------|:---------|---------:|:------------------------------|
+| CLICINTV.[`CLICINTV`](#clicintv) | 0x0      |        4 | CLIC interrupt virtualization |
+
+## CLICINTV
+CLIC interrupt virtualization
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xfdfdfdfd`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "V0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID0", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID1", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID2", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID3", "bits": 6, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:26  |   rw   |   0x0   | VSID3  | interrupt VS id                |
+|   25   |        |         |        | Reserved                       |
+|   24   |   rw   |   0x0   | V3     | interrupt delegated to VS-mode |
+| 23:18  |   rw   |   0x0   | VSID2  | interrupt VS id                |
+|   17   |        |         |        | Reserved                       |
+|   16   |   rw   |   0x0   | V2     | interrupt delegated to VS-mode |
+| 15:10  |   rw   |   0x0   | VSID1  | interrupt VS id                |
+|   9    |        |         |        | Reserved                       |
+|   8    |   rw   |   0x0   | V1     | interrupt delegated to VS-mode |
+|  7:2   |   rw   |   0x0   | VSID0  | interrupt VS id                |
+|   1    |        |         |        | Reserved                       |
+|   0    |   rw   |   0x0   | V0     | interrupt delegated to VS-mode |
+
+
+
+
+
+### clicvs_registers.md
+
+## Summary
+
+| Name                       | Offset   |   Length | Description                      |
+|:---------------------------|:---------|---------:|:---------------------------------|
+| CLICVS.[`vsprio`](#vsprio) | 0x0      |        4 | CLIC virtual supervisor priority |
+
+## vsprio
+CLIC virtual supervisor priority
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1010101`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "prio0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+| 31:25  |        |         |        | Reserved      |
+|   24   |   rw   |   0x0   | prio3  | VS3 priority  |
+| 23:17  |        |         |        | Reserved      |
+|   16   |   rw   |   0x0   | prio2  | VS2 priority  |
+|  15:9  |        |         |        | Reserved      |
+|   8    |   rw   |   0x0   | prio1  | VS1 priority  |
+|  7:1   |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | prio0  | VS0 priority  |
+
+
+
+
+
+### mclic_registers.md
+
+## Summary
+
+| Name                                    | Offset   |   Length | Description                            |
+|:----------------------------------------|:---------|---------:|:---------------------------------------|
+| MCLIC.[`MCLICCFG`](#mcliccfg)           | 0x0      |        4 | CLIC configuration                     |
+| MCLIC.[`CLICMNXTICONF`](#clicmnxticonf) | 0x4      |        4 | CLIC enable mnxti irq forwarding logic |
+
+## MCLICCFG
+CLIC configuration
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xff0f003f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "mnlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "nmbits", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 10}, {"name": "snlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 4}, {"name": "unlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 4, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                      |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------|
+| 31:28  |   ro   |   0x0   | reserved | reserved                                         |
+| 27:24  |   rw   |   0x0   | unlbits  | number of privilege mode bits in user mode       |
+| 23:20  |        |         |          | Reserved                                         |
+| 19:16  |   rw   |   0x0   | snlbits  | number of privilege mode bits in supervisor mode |
+|  15:6  |        |         |          | Reserved                                         |
+|  5:4   |   rw   |   0x0   | nmbits   | number of privilege mode bits                    |
+|  3:0   |   rw   |   0x0   | mnlbits  | number of interrupt level bits in machine mode   |
+
+## CLICMNXTICONF
+CLIC enable mnxti irq forwarding logic
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CLICMNXTICONF", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x0   | CLICMNXTICONF |               |
+
+
+
+
+
+## clint
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                      | Offset   |   Length | Description                        |
+|:------------------------------------------|:---------|---------:|:-----------------------------------|
+| CLINT.[`MSIP_0`](#msip)                   | 0x0      |        4 | Machine Software Interrupt Pending |
+| CLINT.[`MSIP_1`](#msip)                   | 0x4      |        4 | Machine Software Interrupt Pending |
+| CLINT.[`MTIMECMP_LOW0`](#mtimecmp_low0)   | 0x4000   |        4 | Machine Timer Compare for Core 0   |
+| CLINT.[`MTIMECMP_HIGH0`](#mtimecmp_high0) | 0x4004   |        4 | Machine Timer Compare for Core 0   |
+| CLINT.[`MTIMECMP_LOW1`](#mtimecmp_low1)   | 0x4008   |        4 | Machine Timer Compare for Core 1   |
+| CLINT.[`MTIMECMP_HIGH1`](#mtimecmp_high1) | 0x400c   |        4 | Machine Timer Compare for Core 1   |
+| CLINT.[`MTIME_LOW`](#mtime_low)           | 0xbff8   |        4 | Timer Register Low                 |
+| CLINT.[`MTIME_HIGH`](#mtime_high)         | 0xbffc   |        4 | Timer Register High                |
+
+## MSIP
+Machine Software Interrupt Pending
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name   | Offset   |
+|:-------|:---------|
+| MSIP_0 | 0x0      |
+| MSIP_1 | 0x4      |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "P", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RSVD", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:1  |   ro   |   0x0   | RSVD   | Reserved                           |
+|   0    |   rw   |   0x0   | P      | Machine Software Interrupt Pending |
+
+## MTIMECMP_LOW0
+Machine Timer Compare for Core 0
+- Offset: `0x4000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                       |
+|:------:|:------:|:-------:|:-------------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_LOW | Machine Time Compare (Low) Core 0 |
+
+## MTIMECMP_HIGH0
+Machine Timer Compare for Core 0
+- Offset: `0x4004`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                        |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_HIGH | Machine Time Compare (High) Core 0 |
+
+## MTIMECMP_LOW1
+Machine Timer Compare for Core 1
+- Offset: `0x4008`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                       |
+|:------:|:------:|:-------:|:-------------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_LOW | Machine Time Compare (Low) Core 1 |
+
+## MTIMECMP_HIGH1
+Machine Timer Compare for Core 1
+- Offset: `0x400c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                        |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_HIGH | Machine Time Compare (High) Core 1 |
+
+## MTIME_LOW
+Timer Register Low
+- Offset: `0xbff8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIME_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description        |
+|:------:|:------:|:-------:|:----------|:-------------------|
+|  31:0  |   rw   |   0x0   | MTIME_LOW | Machine Time (Low) |
+
+## MTIME_HIGH
+Timer Register High
+- Offset: `0xbffc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIME_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description         |
+|:------:|:------:|:-------:|:-----------|:--------------------|
+|  31:0  |   rw   |   0x0   | MTIME_HIGH | Machine Time (High) |
+
+
+
+
+
+## ethernet
+
+
+
+### registers.md
+
+## Summary
+
+| Name                              | Offset   |   Length | Description                                                                                |
+|:----------------------------------|:---------|---------:|:-------------------------------------------------------------------------------------------|
+| eth_framing.[`CONFIG0`](#config0) | 0x0      |        4 | Configures the lower 4 bytes of the devices MAC address                                    |
+| eth_framing.[`CONFIG1`](#config1) | 0x4      |        4 | Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface |
+| eth_framing.[`CONFIG2`](#config2) | 0x8      |        4 | The FCS TX status                                                                          |
+| eth_framing.[`CONFIG3`](#config3) | 0xc      |        4 | The FCS RX status                                                                          |
+
+## CONFIG0
+Configures the lower 4 bytes of the devices MAC address
+- Offset: `0x0`
+- Reset default: `0x890702`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "lower_mac_address", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset   | Name              | Description                             |
+|:------:|:------:|:--------:|:------------------|:----------------------------------------|
+|  31:0  |   rw   | 0x890702 | lower_mac_address | Lower 32 bit of the devices MAC address |
+
+## CONFIG1
+Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface
+- Offset: `0x4`
+- Reset default: `0x2301`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "upper_mac_address", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "promiscuous", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdclk", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdio_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdio_oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                             |
+|:------:|:------:|:-------:|:------------------|:----------------------------------------|
+| 31:20  |        |         |                   | Reserved                                |
+|   19   |   rw   |   0x0   | phy_mdio_oe       | MDIO output enable                      |
+|   18   |   rw   |   0x0   | phy_mdio_o        | MDIO output                             |
+|   17   |   rw   |   0x0   | phy_mdclk         | MDIO clock                              |
+|   16   |   rw   |   0x0   | promiscuous       | promiscuous flag                        |
+|  15:0  |   rw   | 0x2301  | upper_mac_address | Upper 16 bit of the devices MAC address |
+
+## CONFIG2
+The FCS TX status
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_fcs_reg", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   ro   |   0x0   | tx_fcs_reg | FCS TX status |
+
+## CONFIG3
+The FCS RX status
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rx_fcs_reg", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   ro   |   0x0   | rx_fcs_reg | FCS RX status |
+
+
+
+
+
+## fp_cluster
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                                                         |
+|:-----------------------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------|
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_0`](#perf_counter_enable)     | 0x0      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_1`](#perf_counter_enable)     | 0x8      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_0`](#hart_select)                     | 0x10     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_1`](#hart_select)                     | 0x18     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_0`](#perf_counter)                   | 0x20     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`PERF_COUNTER_1`](#perf_counter)                   | 0x28     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`CL_CLINT_SET`](#cl_clint_set)                     | 0x30     |        8 | Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt     |
+| spatz_cluster_peripheral.[`CL_CLINT_CLEAR`](#cl_clint_clear)                 | 0x38     |        8 | Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt |
+| spatz_cluster_peripheral.[`HW_BARRIER`](#hw_barrier)                         | 0x40     |        8 | Hardware barrier register. Loads to this register will block until all cores have                   |
+| spatz_cluster_peripheral.[`ICACHE_PREFETCH_ENABLE`](#icache_prefetch_enable) | 0x48     |        8 | Controls prefetching of the instruction cache.                                                      |
+| spatz_cluster_peripheral.[`SPATZ_STATUS`](#spatz_status)                     | 0x50     |        8 | Sets the status of the Spatz cluster.                                                               |
+| spatz_cluster_peripheral.[`CLUSTER_BOOT_CONTROL`](#cluster_boot_control)     | 0x58     |        8 | Controls the cluster boot process.                                                                  |
+
+## PERF_COUNTER_ENABLE
+Enable particular performance counter and start tracking.
+- Reset default: `0x0`
+- Reset mask: `0x7fffffff`
+
+### Instances
+
+| Name                  | Offset   |
+|:----------------------|:---------|
+| PERF_COUNTER_ENABLE_0 | 0x0      |
+| PERF_COUNTER_ENABLE_1 | 0x8      |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CYCLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_ACCESSED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_CONGESTED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU_SEQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_CORE_TO_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_INSTR", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_LOAD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_I", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_ACC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_B_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUSY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_MISS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_PREFETCH", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_DOUBLE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 33}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                         |
+|:------:|:------:|:-------:|:-------------------------------------------------------------|
+| 63:31  |        |         | Reserved                                                     |
+|   30   |   rw   |   0x0   | [ICACHE_STALL](#perf_counter_enable--icache_stall)           |
+|   29   |   rw   |   0x0   | [ICACHE_DOUBLE_HIT](#perf_counter_enable--icache_double_hit) |
+|   28   |   rw   |   0x0   | [ICACHE_PREFETCH](#perf_counter_enable--icache_prefetch)     |
+|   27   |   rw   |   0x0   | [ICACHE_HIT](#perf_counter_enable--icache_hit)               |
+|   26   |   rw   |   0x0   | [ICACHE_MISS](#perf_counter_enable--icache_miss)             |
+|   25   |   rw   |   0x0   | [DMA_BUSY](#perf_counter_enable--dma_busy)                   |
+|   24   |   rw   |   0x0   | [DMA_B_DONE](#perf_counter_enable--dma_b_done)               |
+|   23   |   rw   |   0x0   | [DMA_W_BW](#perf_counter_enable--dma_w_bw)                   |
+|   22   |   rw   |   0x0   | [DMA_W_DONE](#perf_counter_enable--dma_w_done)               |
+|   21   |   rw   |   0x0   | [DMA_R_BW](#perf_counter_enable--dma_r_bw)                   |
+|   20   |   rw   |   0x0   | [DMA_R_DONE](#perf_counter_enable--dma_r_done)               |
+|   19   |   rw   |   0x0   | [DMA_AR_BW](#perf_counter_enable--dma_ar_bw)                 |
+|   18   |   rw   |   0x0   | [DMA_AR_DONE](#perf_counter_enable--dma_ar_done)             |
+|   17   |   rw   |   0x0   | [DMA_AW_BW](#perf_counter_enable--dma_aw_bw)                 |
+|   16   |   rw   |   0x0   | [DMA_AW_DONE](#perf_counter_enable--dma_aw_done)             |
+|   15   |   rw   |   0x0   | [DMA_BUF_R_STALL](#perf_counter_enable--dma_buf_r_stall)     |
+|   14   |   rw   |   0x0   | [DMA_BUF_W_STALL](#perf_counter_enable--dma_buf_w_stall)     |
+|   13   |   rw   |   0x0   | [DMA_W_STALL](#perf_counter_enable--dma_w_stall)             |
+|   12   |   rw   |   0x0   | [DMA_R_STALL](#perf_counter_enable--dma_r_stall)             |
+|   11   |   rw   |   0x0   | [DMA_AR_STALL](#perf_counter_enable--dma_ar_stall)           |
+|   10   |   rw   |   0x0   | [DMA_AW_STALL](#perf_counter_enable--dma_aw_stall)           |
+|   9    |   rw   |   0x0   | [RETIRED_ACC](#perf_counter_enable--retired_acc)             |
+|   8    |   rw   |   0x0   | [RETIRED_I](#perf_counter_enable--retired_i)                 |
+|   7    |   rw   |   0x0   | [RETIRED_LOAD](#perf_counter_enable--retired_load)           |
+|   6    |   rw   |   0x0   | [RETIRED_INSTR](#perf_counter_enable--retired_instr)         |
+|   5    |   rw   |   0x0   | [ISSUE_CORE_TO_FPU](#perf_counter_enable--issue_core_to_fpu) |
+|   4    |   rw   |   0x0   | [ISSUE_FPU_SEQ](#perf_counter_enable--issue_fpu_seq)         |
+|   3    |   rw   |   0x0   | [ISSUE_FPU](#perf_counter_enable--issue_fpu)                 |
+|   2    |   rw   |   0x0   | [TCDM_CONGESTED](#perf_counter_enable--tcdm_congested)       |
+|   1    |   rw   |   0x0   | [TCDM_ACCESSED](#perf_counter_enable--tcdm_accessed)         |
+|   0    |   rw   |   0x0   | [CYCLE](#perf_counter_enable--cycle)                         |
+
+### PERF_COUNTER_ENABLE . ICACHE_STALL
+  Incremented for instruction cache stalls.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_DOUBLE_HIT
+  Incremented for instruction cache double hit.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_PREFETCH
+  Incremented for instruction cache prefetches.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_HIT
+  Incremented for instruction cache hits.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_MISS
+  Incremented for instruction cache misses.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUSY
+  Incremented whenever DMA is busy.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_B_DONE
+  Incremented whenever B handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_BW
+  Whenever W handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_DONE
+  Incremented whenvever W handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_BW
+  Whenever R handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_DONE
+  Incremented whenever R handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_BW
+  Whenever AR handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_DONE
+  Incremented whenever AR handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_BW
+  Whenever AW handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_DONE
+  Incremented whenever AW handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_R_STALL
+  Incremented whenever r_valid = 1 but r_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_W_STALL
+  Incremented whenever w_ready = 1 but w_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_STALL
+  Incremented whenever w_valid = 1 but w_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_STALL
+  Incremented whenever r_ready = 1 but r_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_STALL
+  Incremented whenever ar_valid = 1 but ar_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_STALL
+  Incremented whenever aw_valid = 1 but aw_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_ACC
+  Offloaded instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_I
+  Base instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_LOAD
+  Load instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_INSTR
+  Instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_CORE_TO_FPU
+Incremented whenever the core issues an FPU instruction.
+  _This is a hart-local signal._
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU_SEQ
+  Incremented whenever the FPU Sequencer issues an FPU instruction.
+  Might be non available if the hardware doesn't support FREP.
+  _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU
+  Core operations performed in the FPU. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_CONGESTED
+  Incremented whenever an access twoards the TCDM is made but the arbitration
+  logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+  _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_ACCESSED
+  Increased whenever the TCDM is accessed. Each individual access is tracked,
+  so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+  so it doesn't matter whether the cores or the for example the SSR hardware accesses
+  the TCDM. _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . CYCLE
+Cycle counter. Counts up as long as the cluster is powered.
+
+## HART_SELECT
+Select from which hart in the cluster, starting from `0`,
+   the event should be counted. For each performance counter
+   the cores can be selected individually. If a hart greater
+   than the clusters total hart size is selected the selection
+   will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+   will be selected.
+- Reset default: `0x0`
+- Reset mask: `0x3ff`
+
+### Instances
+
+| Name          | Offset   |
+|:--------------|:---------|
+| HART_SELECT_0 | 0x10     |
+| HART_SELECT_1 | 0x18     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HART_SELECT", "bits": 10, "attr": ["rw"], "rotate": -90}, {"bits": 54}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                   |
+|:------:|:------:|:-------:|:------------|:----------------------------------------------|
+| 63:10  |        |         |             | Reserved                                      |
+|  9:0   |   rw   |   0x0   | HART_SELECT | Select source of per-hart performance counter |
+
+## PERF_COUNTER
+Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+performance metric you would like to track.
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| PERF_COUNTER_0 | 0x20     |
+| PERF_COUNTER_1 | 0x28     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERF_COUNTER", "bits": 48, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description         |
+|:------:|:------:|:-------:|:-------------|:--------------------|
+| 63:48  |        |         |              | Reserved            |
+|  47:0  |   rw   |    x    | PERF_COUNTER | Performance counter |
+
+## CL_CLINT_SET
+Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_SET", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                           |
+|:------:|:------:|:-------:|:-------------|:--------------------------------------|
+| 63:32  |        |         |              | Reserved                              |
+|  31:0  |   wo   |    x    | CL_CLINT_SET | Set cluster-local interrupt of hart i |
+
+## CL_CLINT_CLEAR
+Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_CLEAR", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                             |
+|:------:|:------:|:-------:|:---------------|:----------------------------------------|
+| 63:32  |        |         |                | Reserved                                |
+|  31:0  |   wo   |    x    | CL_CLINT_CLEAR | Clear cluster-local interrupt of hart i |
+
+## HW_BARRIER
+Hardware barrier register. Loads to this register will block until all cores have
+performed the load. At this stage we know that they reached the same point in the control flow,
+i.e., the cores are synchronized.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HW_BARRIER", "bits": 32, "attr": ["ro"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                |
+|:------:|:------:|:-------:|:-----------|:---------------------------|
+| 63:32  |        |         |            | Reserved                   |
+|  31:0  |   ro   |    x    | HW_BARRIER | Hardware barrier register. |
+
+## ICACHE_PREFETCH_ENABLE
+Controls prefetching of the instruction cache.
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ICACHE_PREFETCH_ENABLE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                |
+|:------:|:------:|:-------:|:-----------------------|:---------------------------|
+|  63:1  |        |         |                        | Reserved                   |
+|   0    |   wo   |   0x1   | ICACHE_PREFETCH_ENABLE | Hardware barrier register. |
+
+## SPATZ_STATUS
+Sets the status of the Spatz cluster.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_PROBE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description                                  |
+|:------:|:------:|:-------:|:--------------------|:---------------------------------------------|
+|  63:1  |        |         |                     | Reserved                                     |
+|   0    |   wo   |   0x0   | SPATZ_CLUSTER_PROBE | Indicates the cluster is computing a kernel. |
+
+## CLUSTER_BOOT_CONTROL
+Controls the cluster boot process.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENTRY_POINT", "bits": 32, "attr": ["rw"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                     |
+|:------:|:------:|:-------:|:------------|:--------------------------------|
+| 63:32  |        |         |             | Reserved                        |
+|  31:0  |   rw   |   0x0   | ENTRY_POINT | Post-bootstrapping entry point. |
+
+
+
+
+
+## gpio
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                 | Offset   |   Length | Description                                   |
+|:-----------------------------------------------------|:---------|---------:|:----------------------------------------------|
+| gpio.[`INTR_STATE`](#intr_state)                     | 0x0      |        4 | Interrupt State Register                      |
+| gpio.[`INTR_ENABLE`](#intr_enable)                   | 0x4      |        4 | Interrupt Enable Register                     |
+| gpio.[`INTR_TEST`](#intr_test)                       | 0x8      |        4 | Interrupt Test Register                       |
+| gpio.[`ALERT_TEST`](#alert_test)                     | 0xc      |        4 | Alert Test Register                           |
+| gpio.[`DATA_IN`](#data_in)                           | 0x10     |        4 | GPIO Input data read value                    |
+| gpio.[`DIRECT_OUT`](#direct_out)                     | 0x14     |        4 | GPIO direct output data write value           |
+| gpio.[`MASKED_OUT_LOWER`](#masked_out_lower)         | 0x18     |        4 | GPIO write data lower with mask.              |
+| gpio.[`MASKED_OUT_UPPER`](#masked_out_upper)         | 0x1c     |        4 | GPIO write data upper with mask.              |
+| gpio.[`DIRECT_OE`](#direct_oe)                       | 0x20     |        4 | GPIO Output Enable.                           |
+| gpio.[`MASKED_OE_LOWER`](#masked_oe_lower)           | 0x24     |        4 | GPIO write Output Enable lower with mask.     |
+| gpio.[`MASKED_OE_UPPER`](#masked_oe_upper)           | 0x28     |        4 | GPIO write Output Enable upper with mask.     |
+| gpio.[`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising)   | 0x2c     |        4 | GPIO interrupt enable for GPIO, rising edge.  |
+| gpio.[`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling) | 0x30     |        4 | GPIO interrupt enable for GPIO, falling edge. |
+| gpio.[`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh) | 0x34     |        4 | GPIO interrupt enable for GPIO, level high.   |
+| gpio.[`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow)   | 0x38     |        4 | GPIO interrupt enable for GPIO, level low.    |
+| gpio.[`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter) | 0x3c     |        4 | filter enable for GPIO input bits.            |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw1c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                 |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------|
+|  31:0  |  rw1c  |   0x0   | gpio   | raised if any of GPIO pin detects configured interrupt mode |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | gpio   | Enable interrupt when corresponding bit in [`INTR_STATE.gpio`](#intr_state) is set. |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | gpio   | Write 1 to force corresponding bit in [`INTR_STATE.gpio`](#intr_state) to 1. |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## DATA_IN
+GPIO Input data read value
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   ro   |    x    | DATA_IN |               |
+
+## DIRECT_OUT
+GPIO direct output data write value
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DIRECT_OUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   rw   |    x    | DIRECT_OUT |               |
+
+## MASKED_OUT_LOWER
+GPIO write data lower with mask.
+
+Masked write for DATA_OUT[15:0].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OUT[15:0] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OUT[15:0].
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                     |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------|
+| 31:16  |   wo   |    x    | mask   | Write data mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15 |
+|  15:0  |   rw   |    x    | data   | Write data value[15:0]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1    |
+
+## MASKED_OUT_UPPER
+GPIO write data upper with mask.
+
+Masked write for DATA_OUT[31:16].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OUT[31:16] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OUT[31:16].
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                       |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------|
+| 31:16  |   wo   |    x    | mask   | Write data mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31 |
+|  15:0  |   rw   |    x    | data   | Write data value[31:16]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1     |
+
+## DIRECT_OE
+GPIO Output Enable.
+
+Setting direct_oe[i] to 1 enables output mode for GPIO[i]
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DIRECT_OE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:0  |   rw   |    x    | DIRECT_OE |               |
+
+## MASKED_OE_LOWER
+GPIO write Output Enable lower with mask.
+
+Masked write for DATA_OE[15:0], the register that controls
+output mode for GPIO pins [15:0].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OE[15:0] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OE[15:0].
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------|
+| 31:16  |   rw   |    x    | mask   | Write OE mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15 |
+|  15:0  |   rw   |    x    | data   | Write OE value[15:0]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1    |
+
+## MASKED_OE_UPPER
+GPIO write Output Enable upper with mask.
+
+Masked write for DATA_OE[31:16], the register that controls
+output mode for GPIO pins [31:16].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OE[31:16] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OE[31:16].
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                    |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------|
+| 31:16  |   rw   |    x    | mask   | Write OE mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31 |
+|  15:0  |   rw   |    x    | data   | Write OE value[31:16]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1     |
+
+## INTR_CTRL_EN_RISING
+GPIO interrupt enable for GPIO, rising edge.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising)[i]
+enables rising-edge interrupt detection on GPIO[i].
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_RISING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_RISING |               |
+
+## INTR_CTRL_EN_FALLING
+GPIO interrupt enable for GPIO, falling edge.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling)[i]
+enables falling-edge interrupt detection on GPIO[i].
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_FALLING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_FALLING |               |
+
+## INTR_CTRL_EN_LVLHIGH
+GPIO interrupt enable for GPIO, level high.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh)[i]
+enables level high interrupt detection on GPIO[i].
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_LVLHIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_LVLHIGH |               |
+
+## INTR_CTRL_EN_LVLLOW
+GPIO interrupt enable for GPIO, level low.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow)[i]
+enables level low interrupt detection on GPIO[i].
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_LVLLOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_LVLLOW |               |
+
+## CTRL_EN_INPUT_FILTER
+filter enable for GPIO input bits.
+
+If [`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter)[i] is true, a value of input bit [i]
+must be stable for 16 cycles before transitioning.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CTRL_EN_INPUT_FILTER", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | CTRL_EN_INPUT_FILTER |               |
+
+
+
+
+
+## gp_timer1_system_timer
+
+
+
+### registers.md
+
+## Summary
+
+| Name                               | Offset   |   Length | Description                           |
+|:-----------------------------------|:---------|---------:|:--------------------------------------|
+| timer_unit.[`CFG_LO`](#cfg_lo)     | 0x0      |        4 | Timer Low Configuration register.     |
+| timer_unit.[`CFG_HI`](#cfg_hi)     | 0x4      |        4 | Timer HIGH Configuration register.    |
+| timer_unit.[`CNT_LO`](#cnt_lo)     | 0x8      |        4 | Timer Low counter value register.     |
+| timer_unit.[`CNT_HI`](#cnt_hi)     | 0xc      |        4 | Timer High counter value register.    |
+| timer_unit.[`CMP_LO`](#cmp_lo)     | 0x10     |        4 | Timer Low comparator value register.  |
+| timer_unit.[`CMP_HI`](#cmp_hi)     | 0x14     |        4 | Timer High comparator value register. |
+| timer_unit.[`START_LO`](#start_lo) | 0x18     |        4 | Start Timer Low counting register.    |
+| timer_unit.[`START_HI`](#start_hi) | 0x1c     |        4 | Start Timer High counting register.   |
+| timer_unit.[`RESET_LO`](#reset_lo) | 0x20     |        4 | Reset Timer Low counter register.     |
+| timer_unit.[`RESET_HI`](#reset_hi) | 0x24     |        4 | Reset Timer High counter register.    |
+
+## CFG_LO
+Timer Low Configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x8000ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PVAL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 15}, {"name": "CASC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | CASC   | Timer low  + Timer high 64bit cascaded mode configuration bitfield.                                                                                                                                                                          |
+| 30:16  |        |         |        | Reserved                                                                                                                                                                                                                                     |
+|  15:8  |   rw   |   0x0   | PVAL   | Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL)                                                                                                                                                                          |
+|   7    |   rw   |   0x0   | CCFG   | Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                 |
+|   6    |   rw   |   0x0   | PEN    | Timer low prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   5    |   rw   |   0x0   | ONE_S  | Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low when compare match with CMP_LO occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer low continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   2    |   rw   |   0x0   | IRQEN  | Timer low compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                            |
+|   1    |   rw   |   0x0   | RESET  | Timer low counter reset command bitfield. Cleared after Timer Low reset execution.                                                                                                                                                           |
+|   0    |   rw   |   0x0   | ENABLE | Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                    |
+
+## CFG_HI
+Timer HIGH Configuration register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLKCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                     |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                                                        |
+|   7    |   rw   |   0x0   | CLKCFG | Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                   |
+|   6    |   rw   |   0x0   | PEN    | Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   5    |   rw   |   0x0   | ONE_S  | Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled counting when compare match with CMP_HI occurs. - 1'b1: disable Timer high when compare match with CMP_HI occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer high continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_HI occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_HI occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   2    |   rw   |   0x0   | IRQEN  | Timer high compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                              |
+|   1    |   wo   |   0x0   | RESET  | Timer high counter reset command bitfield. Cleared after Timer high reset execution.                                                                                                                                                            |
+|   0    |   rw   |   0x0   | ENABLE | Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                      |
+
+## CNT_LO
+Timer Low counter value register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                       |
+|:------:|:------:|:-------:|:-------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_lo | Timer Low counter value bitfield. |
+
+## CNT_HI
+Timer High counter value register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_hi | Timer High counter value bitfield. |
+
+## CMP_LO
+Timer Low comparator value register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                          |
+|:------:|:------:|:-------:|:-------|:-------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_lo | Timer Low comparator value bitfield. |
+
+## CMP_HI
+Timer High comparator value register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_hi | Timer High comparator value bitfield. |
+
+## START_LO
+Start Timer Low counting register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                               |
+|   0    |   wo   |   0x0   | strt_lo | Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set. |
+
+## START_HI
+Start Timer High counting register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                             |
+|:------:|:------:|:-------:|:--------|:------------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                                |
+|   0    |   wo   |   0x0   | strt_hi | Timer High start command bitfield. When executed, CFG_HI.ENABLE is set. |
+
+## RESET_LO
+Reset Timer Low counter register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                   |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                      |
+|   0    |   wo   |   0x0   | rst_lo | Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set. |
+
+## RESET_HI
+Reset Timer High counter register.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                       |
+|   0    |   wo   |   0x0   | rst_hi | Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set. |
+
+
+
+
+
+## gp_timer2_advanced_timer
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                              | Offset   |   Length | Description                                              |
+|:--------------------------------------------------|:---------|---------:|:---------------------------------------------------------|
+| apb_adv_timer.[`T0_CMD`](#t0_cmd)                 | 0x0      |        4 | ADV_TIMER0 command register.                             |
+| apb_adv_timer.[`T0_CONFIG`](#t0_config)           | 0x4      |        4 | ADV_TIMER0 configuration register.                       |
+| apb_adv_timer.[`T0_THRESHOLD`](#t0_threshold)     | 0x8      |        4 | ADV_TIMER0 threshold configuration register.             |
+| apb_adv_timer.[`T0_TH_CHANNEL0`](#t0_th_channel0) | 0xc      |        4 | ADV_TIMER0 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL1`](#t0_th_channel1) | 0x10     |        4 | ADV_TIMER0 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL2`](#t0_th_channel2) | 0x14     |        4 | ADV_TIMER0 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL3`](#t0_th_channel3) | 0x18     |        4 | ADV_TIMER0 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T0_COUNTER`](#t0_counter)         | 0x1c     |        4 | ADV_TIMER0 counter register.                             |
+| apb_adv_timer.[`T1_CMD`](#t1_cmd)                 | 0x20     |        4 | ADV_TIMER1 command register.                             |
+| apb_adv_timer.[`T1_CONFIG`](#t1_config)           | 0x24     |        4 | ADV_TIMER1 configuration register.                       |
+| apb_adv_timer.[`T1_THRESHOLD`](#t1_threshold)     | 0x28     |        4 | ADV_TIMER1 threshold configuration register.             |
+| apb_adv_timer.[`T1_TH_CHANNEL0`](#t1_th_channel0) | 0x2c     |        4 | ADV_TIMER1 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL1`](#t1_th_channel1) | 0x30     |        4 | ADV_TIMER1 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL2`](#t1_th_channel2) | 0x34     |        4 | ADV_TIMER1 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL3`](#t1_th_channel3) | 0x38     |        4 | ADV_TIMER1 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T1_COUNTER`](#t1_counter)         | 0x3c     |        4 | ADV_TIMER1 counter register.                             |
+| apb_adv_timer.[`T2_CMD`](#t2_cmd)                 | 0x40     |        4 | ADV_TIMER2 command register.                             |
+| apb_adv_timer.[`T2_CONFIG`](#t2_config)           | 0x44     |        4 | ADV_TIMER2 configuration register.                       |
+| apb_adv_timer.[`T2_THRESHOLD`](#t2_threshold)     | 0x48     |        4 | ADV_TIMER2 threshold configuration register.             |
+| apb_adv_timer.[`T2_TH_CHANNEL0`](#t2_th_channel0) | 0x4c     |        4 | ADV_TIMER2 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL1`](#t2_th_channel1) | 0x50     |        4 | ADV_TIMER2 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL2`](#t2_th_channel2) | 0x54     |        4 | ADV_TIMER2 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL3`](#t2_th_channel3) | 0x58     |        4 | ADV_TIMER2 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T2_COUNTER`](#t2_counter)         | 0x5c     |        4 | ADV_TIMER2 counter register.                             |
+| apb_adv_timer.[`T3_CMD`](#t3_cmd)                 | 0x60     |        4 | ADV_TIMER3 command register.                             |
+| apb_adv_timer.[`T3_CONFIG`](#t3_config)           | 0x64     |        4 | ADV_TIMER3 configuration register.                       |
+| apb_adv_timer.[`T3_THRESHOLD`](#t3_threshold)     | 0x68     |        4 | ADV_TIMER3 threshold configuration register.             |
+| apb_adv_timer.[`T3_TH_CHANNEL0`](#t3_th_channel0) | 0x6c     |        4 | ADV_TIMER3 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL1`](#t3_th_channel1) | 0x70     |        4 | ADV_TIMER3 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL2`](#t3_th_channel2) | 0x74     |        4 | ADV_TIMER3 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL3`](#t3_th_channel3) | 0x78     |        4 | ADV_TIMER3 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T3_COUNTER`](#t3_counter)         | 0x7c     |        4 | ADV_TIMER3 counter register.                             |
+| apb_adv_timer.[`EVENT_CFG`](#event_cfg)           | 0x80     |        4 | ADV_TIMERS events configuration register.                |
+| apb_adv_timer.[`CG`](#cg)                         | 0x84     |        4 | ADV_TIMERS channels clock gating configuration register. |
+
+## T0_CMD
+ADV_TIMER0 command register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RFU", "bits": 27, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |   wo   |   0x0   | RFU    | ?                                   |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER0 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER0 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER0 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER0 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER0 start command bitfield.  |
+
+## T0_CONFIG
+ADV_TIMER0 configuration register.
+- Offset: `0x4`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t0_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t0_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t0_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t0_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t0_config--insel)         |
+
+### T0_CONFIG . PRESC
+ADV_TIMER0 prescaler value configuration bitfield.
+
+### T0_CONFIG . UPDOWNSEL
+ADV_TIMER0 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.	
+
+### T0_CONFIG . CLKSEL
+ADV_TIMER0 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T0_CONFIG . MODE
+ADV_TIMER0 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T0_CONFIG . INSEL
+ADV_TIMER0 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T0_THRESHOLD
+ADV_TIMER0 threshold configuration register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. |
+
+## T0_TH_CHANNEL0
+ADV_TIMER0 channel 0 threshold configuration register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel0--th)     |
+
+### T0_TH_CHANNEL0 . MODE
+ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL0 . TH
+ADV_TIMER0 channel 0 threshold configuration bitfield.
+
+## T0_TH_CHANNEL1
+ADV_TIMER0 channel 1 threshold configuration register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel1--th)     |
+
+### T0_TH_CHANNEL1 . MODE
+ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL1 . TH
+ADV_TIMER0 channel 1 threshold configuration bitfield.
+
+## T0_TH_CHANNEL2
+ADV_TIMER0 channel 2 threshold configuration register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel2--th)     |
+
+### T0_TH_CHANNEL2 . MODE
+ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL2 . TH
+ADV_TIMER0 channel 2 threshold configuration bitfield.
+
+## T0_TH_CHANNEL3
+ADV_TIMER0 channel 3 threshold configuration register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel3--th)     |
+
+### T0_TH_CHANNEL3 . MODE
+ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL3 . TH
+ADV_TIMER0 channel 3 threshold configuration bitfield.
+
+## T0_COUNTER
+ADV_TIMER0 counter register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER0 counter value. |
+
+## T1_CMD
+ADV_TIMER1 command register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER1 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER1 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER1 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER1 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER1 start command bitfield.  |
+
+## T1_CONFIG
+ADV_TIMER1 configuration register.
+- Offset: `0x24`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t1_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t1_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t1_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t1_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t1_config--insel)         |
+
+### T1_CONFIG . PRESC
+ADV_TIMER1 prescaler value configuration bitfield.
+
+### T1_CONFIG . UPDOWNSEL
+ADV_TIMER1 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T1_CONFIG . CLKSEL
+ADV_TIMER1 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T1_CONFIG . MODE
+ADV_TIMER1 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T1_CONFIG . INSEL
+ADV_TIMER1 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T1_THRESHOLD
+ADV_TIMER1 threshold configuration register.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value. |
+
+## T1_TH_CHANNEL0
+ADV_TIMER1 channel 0 threshold configuration register.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel0--th)     |
+
+### T1_TH_CHANNEL0 . MODE
+ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL0 . TH
+ADV_TIMER1 channel 0 threshold configuration bitfield.
+
+## T1_TH_CHANNEL1
+ADV_TIMER1 channel 1 threshold configuration register.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel1--th)     |
+
+### T1_TH_CHANNEL1 . MODE
+ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL1 . TH
+ADV_TIMER1 channel 1 threshold configuration bitfield.
+
+## T1_TH_CHANNEL2
+ADV_TIMER1 channel 2 threshold configuration register.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel2--th)     |
+
+### T1_TH_CHANNEL2 . MODE
+ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL2 . TH
+ADV_TIMER1 channel 2 threshold configuration bitfield.
+
+## T1_TH_CHANNEL3
+ADV_TIMER1 channel 3 threshold configuration register.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel3--th)     |
+
+### T1_TH_CHANNEL3 . MODE
+ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL3 . TH
+ADV_TIMER1 channel 3 threshold configuration bitfield.
+
+## T1_COUNTER
+ADV_TIMER1 counter register.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER1 counter value. |
+
+## T2_CMD
+ADV_TIMER2 command register.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER2 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER2 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER2 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER2 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER2 start command bitfield.  |
+
+## T2_CONFIG
+ADV_TIMER2 configuration register.
+- Offset: `0x44`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t2_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t2_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t2_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t2_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t2_config--insel)         |
+
+### T2_CONFIG . PRESC
+ADV_TIMER2 prescaler value configuration bitfield.
+
+### T2_CONFIG . UPDOWNSEL
+ADV_TIMER2 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T2_CONFIG . CLKSEL
+ADV_TIMER2 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T2_CONFIG . MODE
+ADV_TIMER2 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T2_CONFIG . INSEL
+ADV_TIMER2 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T2_THRESHOLD
+ADV_TIMER2 threshold configuration register.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value. |
+
+## T2_TH_CHANNEL0
+ADV_TIMER2 channel 0 threshold configuration register.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel0--th)     |
+
+### T2_TH_CHANNEL0 . MODE
+ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL0 . TH
+ADV_TIMER2 channel 0 threshold configuration bitfield.
+
+## T2_TH_CHANNEL1
+ADV_TIMER2 channel 1 threshold configuration register.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel1--th)     |
+
+### T2_TH_CHANNEL1 . MODE
+ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL1 . TH
+ADV_TIMER2 channel 1 threshold configuration bitfield.
+
+## T2_TH_CHANNEL2
+ADV_TIMER2 channel 2 threshold configuration register.
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel2--th)     |
+
+### T2_TH_CHANNEL2 . MODE
+ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL2 . TH
+ADV_TIMER2 channel 2 threshold configuration bitfield.
+
+## T2_TH_CHANNEL3
+ADV_TIMER2 channel 3 threshold configuration register.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel3--th)     |
+
+### T2_TH_CHANNEL3 . MODE
+ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL3 . TH
+ADV_TIMER2 channel 3 threshold configuration bitfield.
+
+## T2_COUNTER
+ADV_TIMER2 counter register.
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER2 counter value. |
+
+## T3_CMD
+ADV_TIMER3 command register.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER3 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER3 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER3 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER3 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER3 start command bitfield.  |
+
+## T3_CONFIG
+ADV_TIMER3 configuration register.
+- Offset: `0x64`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t3_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t3_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t3_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t3_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t3_config--insel)         |
+
+### T3_CONFIG . PRESC
+ADV_TIMER3 prescaler value configuration bitfield.
+
+### T3_CONFIG . UPDOWNSEL
+ADV_TIMER3 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T3_CONFIG . CLKSEL
+ADV_TIMER3 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T3_CONFIG . MODE
+ADV_TIMER3 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T3_CONFIG . INSEL
+ADV_TIMER3 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T3_THRESHOLD
+ADV_TIMER3 threshold configuration register.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value. |
+
+## T3_TH_CHANNEL0
+ADV_TIMER3 channel 0 threshold configuration register.
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel0--th)     |
+
+### T3_TH_CHANNEL0 . MODE
+ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL0 . TH
+ADV_TIMER3 channel 0 threshold configuration bitfield.
+
+## T3_TH_CHANNEL1
+ADV_TIMER3 channel 1 threshold configuration register.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel1--th)     |
+
+### T3_TH_CHANNEL1 . MODE
+ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL1 . TH
+ADV_TIMER3 channel 1 threshold configuration bitfield.
+
+## T3_TH_CHANNEL2
+ADV_TIMER3 channel 2 threshold configuration register.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel2--th)     |
+
+### T3_TH_CHANNEL2 . MODE
+ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL2 . TH
+ADV_TIMER3 channel 2 threshold configuration bitfield.
+
+## T3_TH_CHANNEL3
+ADV_TIMER3 channel 3 threshold configuration register.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel3--th)     |
+
+### T3_TH_CHANNEL3 . MODE
+ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL3 . TH
+ADV_TIMER3 channel 3 threshold configuration bitfield.
+
+## T3_COUNTER
+ADV_TIMER3 counter register.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER3 counter value. |
+
+## EVENT_CFG
+ADV_TIMERS events configuration register.
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SEL0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL2", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL3", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     |
+|:------:|:------:|:-------:|:-------------------------|
+| 31:20  |        |         | Reserved                 |
+| 19:16  |   rw   |   0x0   | [ENA](#event_cfg--ena)   |
+| 15:12  |   rw   |   0x0   | [SEL3](#event_cfg--sel3) |
+|  11:8  |   rw   |   0x0   | [SEL2](#event_cfg--sel2) |
+|  7:4   |   rw   |   0x0   | [SEL1](#event_cfg--sel1) |
+|  3:0   |   rw   |   0x0   | [SEL0](#event_cfg--sel0) |
+
+### EVENT_CFG . ENA
+ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation.
+
+### EVENT_CFG . SEL3
+ADV_TIMER output event 3 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL2
+ADV_TIMER output event 2 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL1
+ADV_TIMER output event 1 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL0
+ADV_TIMER output event 0 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+## CG
+ADV_TIMERS channels clock gating configuration register.
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                      |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------|
+|  31:4  |        |         |        | Reserved                                                                                                         |
+|  3:0   |   rw   |   0x0   | ENA    | ADV_TIMER clock gating configuration bitfield. - ENA[i]=0: clock gate ADV_TIMERi. - ENA[i]=1: enable ADV_TIMERi. |
+
+
+
+
+
+## hyperbus
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                       | Offset   |   Length | Description                                 |
+|:-----------------------------------------------------------|:---------|---------:|:--------------------------------------------|
+| hyperbus.[`T_LATENCY_ACCESS`](#t_latency_access)           | 0x0      |        4 | Initial latency                             |
+| hyperbus.[`EN_LATENCY_ADDITIONAL`](#en_latency_additional) | 0x4      |        4 | Force 2x Latency count                      |
+| hyperbus.[`T_BURST_MAX`](#t_burst_max)                     | 0x8      |        4 | Max burst Length between two memory refresh |
+| hyperbus.[`T_READ_WRITE_RECOVERY`](#t_read_write_recovery) | 0xc      |        4 | Idle time between transactions              |
+| hyperbus.[`T_RX_CLOCK_DELAY`](#t_rx_clock_delay)           | 0x10     |        4 | RX Delay Line                               |
+| hyperbus.[`T_TX_CLOCK_DELAY`](#t_tx_clock_delay)           | 0x14     |        4 | TX Delay Line                               |
+| hyperbus.[`ADDRESS_MASK_MSB`](#address_mask_msb)           | 0x18     |        4 | Address Mask MSB                            |
+| hyperbus.[`ADDRESS_SPACE`](#address_space)                 | 0x1c     |        4 | L2 sleep configuration register             |
+| hyperbus.[`PHYS_IN_USE`](#phys_in_use)                     | 0x20     |        4 | Number of PHYs on use                       |
+| hyperbus.[`WHICH_PHY`](#which_phy)                         | 0x24     |        4 | PHY used in single PHY mode                 |
+| hyperbus.[`CS0_BASE`](#cs0_base)                           | 0x28     |        4 | CS0 Base address range                      |
+| hyperbus.[`CS0_END`](#cs0_end)                             | 0x2c     |        4 | CS0 End address range                       |
+| hyperbus.[`CS1_BASE`](#cs1_base)                           | 0x30     |        4 | CS1 Base address range                      |
+| hyperbus.[`CS1_END`](#cs1_end)                             | 0x34     |        4 | CS1 End address range                       |
+| hyperbus.[`CS2_BASE`](#cs2_base)                           | 0x38     |        4 | CS2 Base address range                      |
+| hyperbus.[`CS2_END`](#cs2_end)                             | 0x3c     |        4 | CS2 End address range                       |
+| hyperbus.[`CS3_BASE`](#cs3_base)                           | 0x40     |        4 | CS3 Base address range                      |
+| hyperbus.[`CS3_END`](#cs3_end)                             | 0x44     |        4 | CS3 End address range                       |
+
+## T_LATENCY_ACCESS
+Initial latency
+- Offset: `0x0`
+- Reset default: `0x6`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_LATENCY_ACCESS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description     |
+|:------:|:------:|:-------:|:-----------------|:----------------|
+|  31:4  |        |         |                  | Reserved        |
+|  3:0   |   rw   |   0x6   | T_LATENCY_ACCESS | Initial latency |
+
+## EN_LATENCY_ADDITIONAL
+Force 2x Latency count
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EN_LATENCY_ADDITIONAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description            |
+|:------:|:------:|:-------:|:----------------------|:-----------------------|
+|  31:1  |        |         |                       | Reserved               |
+|   0    |   rw   |   0x0   | EN_LATENCY_ADDITIONAL | Force 2x Latency count |
+
+## T_BURST_MAX
+Max burst Length between two memory refresh
+- Offset: `0x8`
+- Reset default: `0x15e`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_BURST_MAX", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                 |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------|
+| 31:16  |        |         |             | Reserved                                    |
+|  15:0  |   rw   |  0x15e  | T_BURST_MAX | Max burst Length between two memory refresh |
+
+## T_READ_WRITE_RECOVERY
+Idle time between transactions
+- Offset: `0xc`
+- Reset default: `0x6`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_READ_WRITE_RECOVERY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                    |
+|:------:|:------:|:-------:|:----------------------|:-------------------------------|
+|  31:4  |        |         |                       | Reserved                       |
+|  3:0   |   rw   |   0x6   | T_READ_WRITE_RECOVERY | Idle time between transactions |
+
+## T_RX_CLOCK_DELAY
+RX Delay Line
+- Offset: `0x10`
+- Reset default: `0x8`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_RX_CLOCK_DELAY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:4  |        |         |                  | Reserved      |
+|  3:0   |   rw   |   0x8   | T_RX_CLOCK_DELAY | RX Delay Line |
+
+## T_TX_CLOCK_DELAY
+TX Delay Line
+- Offset: `0x14`
+- Reset default: `0x8`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_TX_CLOCK_DELAY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:4  |        |         |                  | Reserved      |
+|  3:0   |   rw   |   0x8   | T_TX_CLOCK_DELAY | TX Delay Line |
+
+## ADDRESS_MASK_MSB
+Address Mask MSB
+- Offset: `0x18`
+- Reset default: `0x19`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS_MASK_MSB", "bits": 19, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description      |
+|:------:|:------:|:-------:|:-----------------|:-----------------|
+| 31:19  |        |         |                  | Reserved         |
+|  18:0  |   rw   |  0x19   | ADDRESS_MASK_MSB | Address Mask MSB |
+
+## ADDRESS_SPACE
+L2 sleep configuration register
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS_SPACE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                     |
+|:------:|:------:|:-------:|:--------------|:--------------------------------|
+|  31:1  |        |         |               | Reserved                        |
+|   0    |   rw   |   0x0   | ADDRESS_SPACE | L2 sleep configuration register |
+
+## PHYS_IN_USE
+Number of PHYs on use
+- Offset: `0x20`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PHYS_IN_USE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                                   |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                                      |
+|   0    |   rw   |   0x1   | PHYS_IN_USE | Number of PHYs on use: - 1'b0: Uses 1 PHY - 1'b1: Uses 2 PHYs |
+
+## WHICH_PHY
+PHY used in single PHY mode
+- Offset: `0x24`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "WHICH_PHY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                              |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------------------|
+|  31:1  |        |         |           | Reserved                                                                 |
+|   0    |   rw   |   0x1   | WHICH_PHY | PHY used in single PHY mode: - 1'b0: PHY 0 is used - 1'b1: PHY 1 is used |
+
+## CS0_BASE
+CS0 Base address range
+- Offset: `0x28`
+- Reset default: `0x80000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS0_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x80000000 | CS0_BASE | CS0 Base address range |
+
+## CS0_END
+CS0 End address range
+- Offset: `0x2c`
+- Reset default: `0x81000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS0_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x81000000 | CS0_END | CS0 End address range |
+
+## CS1_BASE
+CS1 Base address range
+- Offset: `0x30`
+- Reset default: `0x81000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS1_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x81000000 | CS1_BASE | CS1 Base address range |
+
+## CS1_END
+CS1 End address range
+- Offset: `0x34`
+- Reset default: `0x82000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS1_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x82000000 | CS1_END | CS1 End address range |
+
+## CS2_BASE
+CS2 Base address range
+- Offset: `0x38`
+- Reset default: `0x82000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS2_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x82000000 | CS2_BASE | CS2 Base address range |
+
+## CS2_END
+CS2 End address range
+- Offset: `0x3c`
+- Reset default: `0x83000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS2_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x83000000 | CS2_END | CS2 End address range |
+
+## CS3_BASE
+CS3 Base address range
+- Offset: `0x40`
+- Reset default: `0x83000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS3_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x83000000 | CS3_BASE | CS3 Base address range |
+
+## CS3_END
+CS3 End address range
+- Offset: `0x44`
+- Reset default: `0x84000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS3_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x84000000 | CS3_END | CS3 End address range |
+
+
+
+
+
+## i2c
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                          | Offset   |   Length | Description                                                                                               |
+|:--------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------------|
+| i2c.[`INTR_STATE`](#intr_state)                               | 0x0      |        4 | Interrupt State Register                                                                                  |
+| i2c.[`INTR_ENABLE`](#intr_enable)                             | 0x4      |        4 | Interrupt Enable Register                                                                                 |
+| i2c.[`INTR_TEST`](#intr_test)                                 | 0x8      |        4 | Interrupt Test Register                                                                                   |
+| i2c.[`ALERT_TEST`](#alert_test)                               | 0xc      |        4 | Alert Test Register                                                                                       |
+| i2c.[`CTRL`](#ctrl)                                           | 0x10     |        4 | I2C Control Register                                                                                      |
+| i2c.[`STATUS`](#status)                                       | 0x14     |        4 | I2C Live Status Register for Host and Target modes                                                        |
+| i2c.[`RDATA`](#rdata)                                         | 0x18     |        4 | I2C Read Data                                                                                             |
+| i2c.[`FDATA`](#fdata)                                         | 0x1c     |        4 | I2C Host Format Data                                                                                      |
+| i2c.[`FIFO_CTRL`](#fifo_ctrl)                                 | 0x20     |        4 | I2C FIFO control register                                                                                 |
+| i2c.[`HOST_FIFO_CONFIG`](#host_fifo_config)                   | 0x24     |        4 | Host mode FIFO configuration                                                                              |
+| i2c.[`TARGET_FIFO_CONFIG`](#target_fifo_config)               | 0x28     |        4 | Target mode FIFO configuration                                                                            |
+| i2c.[`HOST_FIFO_STATUS`](#host_fifo_status)                   | 0x2c     |        4 | Host mode FIFO status register                                                                            |
+| i2c.[`TARGET_FIFO_STATUS`](#target_fifo_status)               | 0x30     |        4 | Target mode FIFO status register                                                                          |
+| i2c.[`OVRD`](#ovrd)                                           | 0x34     |        4 | I2C Override Control Register                                                                             |
+| i2c.[`VAL`](#val)                                             | 0x38     |        4 | Oversampled RX values                                                                                     |
+| i2c.[`TIMING0`](#timing0)                                     | 0x3c     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING1`](#timing1)                                     | 0x40     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING2`](#timing2)                                     | 0x44     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING3`](#timing3)                                     | 0x48     |        4 | Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).                      |
+| i2c.[`TIMING4`](#timing4)                                     | 0x4c     |        4 | Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).                      |
+| i2c.[`TIMEOUT_CTRL`](#timeout_ctrl)                           | 0x50     |        4 | I2C clock stretching and bus timeout control.                                                             |
+| i2c.[`TARGET_ID`](#target_id)                                 | 0x54     |        4 | I2C target address and mask pairs                                                                         |
+| i2c.[`ACQDATA`](#acqdata)                                     | 0x58     |        4 | I2C target acquired data                                                                                  |
+| i2c.[`TXDATA`](#txdata)                                       | 0x5c     |        4 | I2C target transmit data                                                                                  |
+| i2c.[`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl)                 | 0x60     |        4 | I2C host clock generation timeout value (in units of input clock frequency).                              |
+| i2c.[`TARGET_TIMEOUT_CTRL`](#target_timeout_ctrl)             | 0x64     |        4 | I2C target internal stretching timeout control.                                                           |
+| i2c.[`TARGET_NACK_COUNT`](#target_nack_count)                 | 0x68     |        4 | Number of times the I2C target has NACK'ed a new transaction since the last read of this register.        |
+| i2c.[`TARGET_ACK_CTRL`](#target_ack_ctrl)                     | 0x6c     |        4 | Controls for mid-transfer (N)ACK phase handling                                                           |
+| i2c.[`ACQ_FIFO_NEXT_DATA`](#acq_fifo_next_data)               | 0x70     |        4 | The data byte pending to be written to the ACQ FIFO.                                                      |
+| i2c.[`HOST_NACK_HANDLER_TIMEOUT`](#host_nack_handler_timeout) | 0x74     |        4 | Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.            |
+| i2c.[`CONTROLLER_EVENTS`](#controller_events)                 | 0x78     |        4 | Latched events that explain why the controller halted.                                                    |
+| i2c.[`TARGET_EVENTS`](#target_events)                         | 0x7c     |        4 | Latched events that can cause the target module to stretch the clock at the beginning of a read transfer. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                                                                                                                                                                                                                                               |
+|   14   |  rw1c  |   0x0   | host_timeout     | target mode interrupt: raised if the host stops sending the clock during an ongoing transaction.                                                                                                                                                                                       |
+|   13   |  rw1c  |   0x0   | unexp_stop       | target mode interrupt: raised if STOP is received without a preceding NACK during an external host read.                                                                                                                                                                               |
+|   12   |   ro   |   0x0   | acq_stretch      | target mode interrupt: raised if the target is stretching clocks due to full ACQ FIFO or zero count in [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) (if enabled). This is a level status interrupt.                                                                                    |
+|   11   |   ro   |   0x0   | tx_threshold     | target mode interrupt: asserted whilst the TX FIFO level is below the low threshold. This is a level status interrupt.                                                                                                                                                                 |
+|   10   |   ro   |   0x0   | tx_stretch       | target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.                                                                                                                                                                 |
+|   9    |  rw1c  |   0x0   | cmd_complete     | host and target mode interrupt. In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.                                                                   |
+|   8    |  rw1c  |   0x0   | sda_unstable     | host mode interrupt: raised if the target does not assert a constant value of SDA during transmission.                                                                                                                                                                                 |
+|   7    |  rw1c  |   0x0   | stretch_timeout  | host mode interrupt: raised if target stretches the clock beyond the allowed timeout period                                                                                                                                                                                            |
+|   6    |  rw1c  |   0x0   | sda_interference | host mode interrupt: raised if the SDA line goes low when host is trying to assert high                                                                                                                                                                                                |
+|   5    |  rw1c  |   0x0   | scl_interference | host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).                                                                                                                                                                                 |
+|   4    |   ro   |   0x0   | controller_halt  | host mode interrupt: raised if the controller FSM is halted, such as on an unexpected NACK or lost arbitration. Check [`CONTROLLER_EVENTS`](#controller_events) for the reason. The interrupt will be released when the bits in [`CONTROLLER_EVENTS`](#controller_events) are cleared. |
+|   3    |  rw1c  |   0x0   | rx_overflow      | host mode interrupt: raised if the RX FIFO has overflowed.                                                                                                                                                                                                                             |
+|   2    |   ro   |   0x0   | acq_threshold    | target mode interrupt: asserted whilst the ACQ FIFO level is above the high threshold. This is a level status interrupt.                                                                                                                                                               |
+|   1    |   ro   |   0x0   | rx_threshold     | host mode interrupt: asserted whilst the RX FIFO level is above the high threshold. This is a level status interrupt.                                                                                                                                                                  |
+|   0    |   ro   |   0x0   | fmt_threshold    | host mode interrupt: asserted whilst the FMT FIFO level is below the low threshold. This is a level status interrupt.                                                                                                                                                                  |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                                   |
+|   14   |   rw   |   0x0   | host_timeout     | Enable interrupt when [`INTR_STATE.host_timeout`](#intr_state) is set.     |
+|   13   |   rw   |   0x0   | unexp_stop       | Enable interrupt when [`INTR_STATE.unexp_stop`](#intr_state) is set.       |
+|   12   |   rw   |   0x0   | acq_stretch      | Enable interrupt when [`INTR_STATE.acq_stretch`](#intr_state) is set.      |
+|   11   |   rw   |   0x0   | tx_threshold     | Enable interrupt when [`INTR_STATE.tx_threshold`](#intr_state) is set.     |
+|   10   |   rw   |   0x0   | tx_stretch       | Enable interrupt when [`INTR_STATE.tx_stretch`](#intr_state) is set.       |
+|   9    |   rw   |   0x0   | cmd_complete     | Enable interrupt when [`INTR_STATE.cmd_complete`](#intr_state) is set.     |
+|   8    |   rw   |   0x0   | sda_unstable     | Enable interrupt when [`INTR_STATE.sda_unstable`](#intr_state) is set.     |
+|   7    |   rw   |   0x0   | stretch_timeout  | Enable interrupt when [`INTR_STATE.stretch_timeout`](#intr_state) is set.  |
+|   6    |   rw   |   0x0   | sda_interference | Enable interrupt when [`INTR_STATE.sda_interference`](#intr_state) is set. |
+|   5    |   rw   |   0x0   | scl_interference | Enable interrupt when [`INTR_STATE.scl_interference`](#intr_state) is set. |
+|   4    |   rw   |   0x0   | controller_halt  | Enable interrupt when [`INTR_STATE.controller_halt`](#intr_state) is set.  |
+|   3    |   rw   |   0x0   | rx_overflow      | Enable interrupt when [`INTR_STATE.rx_overflow`](#intr_state) is set.      |
+|   2    |   rw   |   0x0   | acq_threshold    | Enable interrupt when [`INTR_STATE.acq_threshold`](#intr_state) is set.    |
+|   1    |   rw   |   0x0   | rx_threshold     | Enable interrupt when [`INTR_STATE.rx_threshold`](#intr_state) is set.     |
+|   0    |   rw   |   0x0   | fmt_threshold    | Enable interrupt when [`INTR_STATE.fmt_threshold`](#intr_state) is set.    |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                         |
+|:------:|:------:|:-------:|:-----------------|:--------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                            |
+|   14   |   wo   |   0x0   | host_timeout     | Write 1 to force [`INTR_STATE.host_timeout`](#intr_state) to 1.     |
+|   13   |   wo   |   0x0   | unexp_stop       | Write 1 to force [`INTR_STATE.unexp_stop`](#intr_state) to 1.       |
+|   12   |   wo   |   0x0   | acq_stretch      | Write 1 to force [`INTR_STATE.acq_stretch`](#intr_state) to 1.      |
+|   11   |   wo   |   0x0   | tx_threshold     | Write 1 to force [`INTR_STATE.tx_threshold`](#intr_state) to 1.     |
+|   10   |   wo   |   0x0   | tx_stretch       | Write 1 to force [`INTR_STATE.tx_stretch`](#intr_state) to 1.       |
+|   9    |   wo   |   0x0   | cmd_complete     | Write 1 to force [`INTR_STATE.cmd_complete`](#intr_state) to 1.     |
+|   8    |   wo   |   0x0   | sda_unstable     | Write 1 to force [`INTR_STATE.sda_unstable`](#intr_state) to 1.     |
+|   7    |   wo   |   0x0   | stretch_timeout  | Write 1 to force [`INTR_STATE.stretch_timeout`](#intr_state) to 1.  |
+|   6    |   wo   |   0x0   | sda_interference | Write 1 to force [`INTR_STATE.sda_interference`](#intr_state) to 1. |
+|   5    |   wo   |   0x0   | scl_interference | Write 1 to force [`INTR_STATE.scl_interference`](#intr_state) to 1. |
+|   4    |   wo   |   0x0   | controller_halt  | Write 1 to force [`INTR_STATE.controller_halt`](#intr_state) to 1.  |
+|   3    |   wo   |   0x0   | rx_overflow      | Write 1 to force [`INTR_STATE.rx_overflow`](#intr_state) to 1.      |
+|   2    |   wo   |   0x0   | acq_threshold    | Write 1 to force [`INTR_STATE.acq_threshold`](#intr_state) to 1.    |
+|   1    |   wo   |   0x0   | rx_threshold     | Write 1 to force [`INTR_STATE.rx_threshold`](#intr_state) to 1.     |
+|   0    |   wo   |   0x0   | fmt_threshold    | Write 1 to force [`INTR_STATE.fmt_threshold`](#intr_state) to 1.    |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CTRL
+I2C Control Register
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLEHOST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ENABLETARGET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NACK_ADDR_AFTER_TIMEOUT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACK_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MULTI_CONTROLLER_MONITOR_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TX_STRETCH_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                              |
+|:------:|:------:|:-------:|:------------------------------------------------------------------|
+|  31:7  |        |         | Reserved                                                          |
+|   6    |   rw   |   0x0   | [TX_STRETCH_CTRL_EN](#ctrl--tx_stretch_ctrl_en)                   |
+|   5    |   rw   |   0x0   | [MULTI_CONTROLLER_MONITOR_EN](#ctrl--multi_controller_monitor_en) |
+|   4    |   rw   |   0x0   | [ACK_CTRL_EN](#ctrl--ack_ctrl_en)                                 |
+|   3    |   rw   |   0x0   | [NACK_ADDR_AFTER_TIMEOUT](#ctrl--nack_addr_after_timeout)         |
+|   2    |   rw   |   0x0   | [LLPBK](#ctrl--llpbk)                                             |
+|   1    |   rw   |   0x0   | [ENABLETARGET](#ctrl--enabletarget)                               |
+|   0    |   rw   |   0x0   | [ENABLEHOST](#ctrl--enablehost)                                   |
+
+### CTRL . TX_STRETCH_CTRL_EN
+If set to 1, this bit causes a read transfer addressed to this target to set the corresponding bit in [`TARGET_EVENTS.`](#target_events)
+
+While [`TARGET_EVENTS.TX_PENDING`](#target_events) is 1, subsequent read transactions will stretch the clock, even if there is data in the TX FIFO.
+
+If enabled, this function allows software to confirm the data in the TX FIFO should be released for the current read.
+This may be useful for cases where the TX FIFO has data that does not apply to the current transfer.
+For example, the transaction could've targeted an alternate function via another address.
+
+### CTRL . MULTI_CONTROLLER_MONITOR_EN
+Enable the bus monitor in multi-controller mode.
+
+If a 0->1 transition happens while [`CTRL.ENABLEHOST`](#ctrl) and [`CTRL.ENABLETARGET`](#ctrl) are both 0, the bus monitor will enable and begin in the "bus busy" state.
+To transition to a bus free state, [`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl) must be nonzero, so the bus monitor may count out idle cycles to confirm the freedom to transmit.
+In addition, the bus monitor will track whether the bus is free based on the enabled timeouts and detected Stop symbols.
+For multi-controller mode, ensure [`CTRL.MULTI_CONTROLLER_MONITOR_EN`](#ctrl) becomes 1 no later than [`CTRL.ENABLEHOST`](#ctrl) or [`CTRL.ENABLETARGET.`](#ctrl)
+This bit can be set at the same time as either or both of the other two, though.
+
+Note that if [`CTRL.MULTI_CONTROLLER_MONITOR_EN`](#ctrl) is set after [`CTRL.ENABLEHOST`](#ctrl) or [`CTRL.ENABLETARGET`](#ctrl), the bus monitor will begin in the "bus free" state instead.
+This would violate the proper protocol for a controller to join a multi-controller environment.
+However, if this controller is known to be the first to join, this ordering will enable skipping the idle wait.
+
+When 0, the bus monitor will report that the bus is always free, so the controller FSM is never blocked from transmitting.
+
+### CTRL . ACK_CTRL_EN
+Enable I2C Target ACK Control Mode.
+
+ACK Control Mode works together with [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) to allow software to control upper-layer protocol (N)ACKing (e.g. as in SMBus).
+This bit enables the mode when 1, and [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) limits how many bytes may be automatically ACK'd while the ACQ FIFO has space.
+If it is 0, the decision to ACK or NACK is made only from stretching timeouts and [`CTRL.NACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+
+### CTRL . NACK_ADDR_AFTER_TIMEOUT
+Enable NACKing the address on a stretch timeout.
+
+This is a Target mode feature.
+If enabled (1), a stretch timeout will cause the device to NACK the address byte.
+If disabled (0), a stretch timeout will cause the device to ACK the address byte.
+SMBus requires that devices always ACK their address, even for read commands.
+However, non-SMBus protocols may have a different approach and can choose to NACK instead.
+
+Note that both cases handle data bytes the same way.
+For writes, the Target module will NACK all subsequent data bytes until it receives a Stop.
+For reads, the Target module will release SDA, causing 0xff to be returned for all data bytes until it receives a Stop.
+
+### CTRL . LLPBK
+Enable I2C line loopback test
+If line loopback is enabled, the internal design sees ACQ and RX data as "1"
+
+### CTRL . ENABLETARGET
+Enable Target I2C functionality
+
+### CTRL . ENABLEHOST
+Enable Host I2C functionality
+
+## STATUS
+I2C Live Status Register for Host and Target modes
+- Offset: `0x14`
+- Reset default: `0x33c`
+- Reset mask: `0x7ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FMTFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FMTEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HOSTIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TARGETIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACK_CTRL_STRETCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                              |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------|
+| 31:11  |        |         |                  | Reserved                                                                                                 |
+|   10   |   ro   |    x    | ACK_CTRL_STRETCH | Target mode stretching at (N)ACK phase due to zero count in [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) |
+|   9    |   ro   |   0x1   | ACQEMPTY         | Target mode receive FIFO is empty                                                                        |
+|   8    |   ro   |   0x1   | TXEMPTY          | Target mode TX FIFO is empty                                                                             |
+|   7    |   ro   |    x    | ACQFULL          | Target mode receive FIFO is full                                                                         |
+|   6    |   ro   |    x    | TXFULL           | Target mode TX FIFO is full                                                                              |
+|   5    |   ro   |   0x1   | RXEMPTY          | Host mode RX FIFO is empty                                                                               |
+|   4    |   ro   |   0x1   | TARGETIDLE       | Target functionality is idle. No Target transaction is in progress                                       |
+|   3    |   ro   |   0x1   | HOSTIDLE         | Host functionality is idle. No Host transaction is in progress                                           |
+|   2    |   ro   |   0x1   | FMTEMPTY         | Host mode FMT FIFO is empty                                                                              |
+|   1    |   ro   |    x    | RXFULL           | Host mode RX FIFO is full                                                                                |
+|   0    |   ro   |    x    | FMTFULL          | Host mode FMT FIFO is full                                                                               |
+
+## RDATA
+I2C Read Data
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   ro   |    x    | RDATA  |               |
+
+## FDATA
+I2C Host Format Data
+
+Writes to this register are used to define and drive Controller-Mode transactions.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FBYTE", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "READB", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RCONT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "NAKOK", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   |
+|:------:|:------:|:-------:|:-----------------------|
+| 31:13  |        |         | Reserved               |
+|   12   |   wo   |   0x0   | [NAKOK](#fdata--nakok) |
+|   11   |   wo   |   0x0   | [RCONT](#fdata--rcont) |
+|   10   |   wo   |   0x0   | [READB](#fdata--readb) |
+|   9    |   wo   |   0x0   | [STOP](#fdata--stop)   |
+|   8    |   wo   |   0x0   | [START](#fdata--start) |
+|  7:0   |   wo   |   0x0   | [FBYTE](#fdata--fbyte) |
+
+### FDATA . NAKOK
+For the currrent controller-transmitter byte (WRITE), do not halt via CONTROLLER_EVENTS
+or assert the 'controller_halt' interrupt if the current byte is not ACK'd.
+
+### FDATA . RCONT
+Do not NACK the last byte read, let the read operation continue.
+
+### FDATA . READB
+Transfer Direction Indicator.
+
+If unset, this write to FDATA defines a controller-transmitter operation (WRITE).
+A single byte of data (FBYTE) is written to the bus.
+
+If set, this write to FDATA defines a controller-receiver operation (READ).
+The value of FBYTE defines the number of bytes read from the bus. (256 if FBYTE==0)"
+After this number of bytes are read, the final byte will be NACKed to end the transfer
+unless RCONT is also set.
+
+### FDATA . STOP
+Issue a STOP condition after transmitting FBYTE.
+
+### FDATA . START
+Issue a START condition before transmitting FBYTE.
+
+### FDATA . FBYTE
+Format Byte.
+
+If no flags are set, hardware will transmit this byte directly.
+
+If READB is set, this field becomes the number of bytes hardware will automatically
+read from the bus.
+
+## FIFO_CTRL
+I2C FIFO control register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x183`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "FMTRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 5}, {"name": "ACQRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                             |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------|
+|  31:9  |        |         |        | Reserved                                                                |
+|   8    |   wo   |   0x0   | TXRST  | TX FIFO reset. Write 1 to the register resets it. Read returns 0        |
+|   7    |   wo   |   0x0   | ACQRST | ACQ FIFO reset. Write 1 to the register resets it. Read returns 0       |
+|  6:2   |        |         |        | Reserved                                                                |
+|   1    |   wo   |   0x0   | FMTRST | FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0 |
+|   0    |   wo   |   0x0   | RXRST  | RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0   |
+
+## HOST_FIFO_CONFIG
+Host mode FIFO configuration
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "FMT_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                                |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:28  |        |         |            | Reserved                                                                                                                                                   |
+| 27:16  |   rw   |   0x0   | FMT_THRESH | Threshold level for FMT interrupts. Whilst the number of used entries in the FMT FIFO is below this setting, the fmt_threshold interrupt will be asserted. |
+| 15:12  |        |         |            | Reserved                                                                                                                                                   |
+|  11:0  |   rw   |   0x0   | RX_THRESH  | Threshold level for RX interrupts. Whilst the level of data in the RX FIFO is above this setting, the rx_threshold interrupt will be asserted.             |
+
+## TARGET_FIFO_CONFIG
+Target mode FIFO configuration
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "ACQ_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                             |
+|:------:|:------:|:-------:|:-----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:28  |        |         |            | Reserved                                                                                                                                                |
+| 27:16  |   rw   |   0x0   | ACQ_THRESH | Threshold level for ACQ interrupts. Whilst the level of data in the ACQ FIFO is above this setting, the acq_threshold interrupt will be asserted.       |
+| 15:12  |        |         |            | Reserved                                                                                                                                                |
+|  11:0  |   rw   |   0x0   | TX_THRESH  | Threshold level for TX interrupts. Whilst the number of used entries in the TX FIFO is below this setting, the tx_threshold interrupt will be asserted. |
+
+## HOST_FIFO_STATUS
+Host mode FIFO status register
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FMTLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "RXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:28  |        |         |        | Reserved                       |
+| 27:16  |   ro   |    x    | RXLVL  | Current fill level of RX fifo  |
+| 15:12  |        |         |        | Reserved                       |
+|  11:0  |   ro   |    x    | FMTLVL | Current fill level of FMT fifo |
+
+## TARGET_FIFO_STATUS
+Target mode FIFO status register
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "ACQLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:28  |        |         |        | Reserved                       |
+| 27:16  |   ro   |    x    | ACQLVL | Current fill level of ACQ fifo |
+| 15:12  |        |         |        | Reserved                       |
+|  11:0  |   ro   |    x    | TXLVL  | Current fill level of TX fifo  |
+
+## OVRD
+I2C Override Control Register
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXOVRDEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SCLVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SDAVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                               |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------|
+|  31:3  |        |         |          | Reserved                                                                  |
+|   2    |   rw   |   0x0   | SDAVAL   | Value for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z |
+|   1    |   rw   |   0x0   | SCLVAL   | Value for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z |
+|   0    |   rw   |   0x0   | TXOVRDEN | Override the SDA and SCL TX signals.                                      |
+
+## VAL
+Oversampled RX values
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SCL_RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "SDA_RX", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------|
+| 31:16  |   ro   |    x    | SDA_RX | Last 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31. |
+|  15:0  |   ro   |    x    | SCL_RX | Last 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.  |
+
+## TIMING0
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+These must be greater than 2 in order for the change in SCL to propagate to the input of the FSM so that acknowledgements are detected correctly.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "THIGH", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "TLOW", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                        |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |        | Reserved                                                                                                                                                           |
+| 28:16  |   rw   |   0x0   | TLOW   | The actual time to hold SCL low between any two SCL pulses. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+| 15:13  |        |         |        | Reserved                                                                                                                                                           |
+|  12:0  |   rw   |   0x0   | THIGH  | The actual time to hold SCL high in a given pulse. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.          |
+
+## TIMING1
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x1ff03ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_R", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "T_F", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:25  |        |         |        | Reserved                                                                                                                                                                            |
+| 24:16  |   rw   |   0x0   | T_F    | The nominal fall time to anticipate for the bus (influences SDA hold times). This field is sized to have a range of at least Standard Mode's 300 ns max with a core clock at 1 GHz. |
+| 15:10  |        |         |        | Reserved                                                                                                                                                                            |
+|  9:0   |   rw   |   0x0   | T_R    | The nominal rise time to anticipate for the bus (depends on capacitance). This field is sized to have a range of at least Standard Mode's 1000 ns max with a core clock at 1 GHz.   |
+
+## TIMING2
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "THD_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                          |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |         | Reserved                                                                                                                                             |
+| 28:16  |   rw   |   0x0   | THD_STA | Actual hold time for start signals. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.           |
+| 15:13  |        |         |         | Reserved                                                                                                                                             |
+|  12:0  |   rw   |   0x0   | TSU_STA | Actual setup time for repeated start signals. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+
+## TIMING3
+Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x1fff01ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_DAT", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "THD_DAT", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         |
+|:------:|:------:|:-------:|:-----------------------------|
+| 31:29  |        |         | Reserved                     |
+| 28:16  |   rw   |   0x0   | [THD_DAT](#timing3--thd_dat) |
+|  15:9  |        |         | Reserved                     |
+|  8:0   |   rw   |   0x0   | [TSU_DAT](#timing3--tsu_dat) |
+
+### TIMING3 . THD_DAT
+Actual hold time for data (or ack) bits.
+(Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
+This field is sized to have a range that accommodates Standard Mode's 3.45 us max for TVD_DAT with a core clock at 1 GHz.
+However, this field is generally expected to represent a time substantially shorter than that.
+It should be long enough to cover the maximum round-trip latency from output pins, through pads and voltage transitions on the board, and back to the input pins, but it should not be substantially greater.
+
+### TIMING3 . TSU_DAT
+Actual setup time for data (or ack) bits.
+This field is sized to have a range of at least Standard Mode's 250 ns max with a core clock at 1 GHz.
+
+## TIMING4
+Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_STO", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "T_BUF", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                                 |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |         | Reserved                                                                                                                                                                    |
+| 28:16  |   rw   |   0x0   | T_BUF   | Actual time between each STOP signal and the following START signal. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+| 15:13  |        |         |         | Reserved                                                                                                                                                                    |
+|  12:0  |   rw   |   0x0   | TSU_STO | Actual setup time for stop signals. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.                                  |
+
+## TIMEOUT_CTRL
+I2C clock stretching and bus timeout control.
+
+This timeout must be enabled by setting [`TIMEOUT_CTRL.EN`](#timeout_ctrl) to 1, and the behavior of this feature depends on the value of [`TIMEOUT_CTRL.MODE.`](#timeout_ctrl)
+
+If the mode is "STRETCH_TIMEOUT", this is used in I2C controller mode to detect whether a connected target is stretching a single low time beyond the timeout value.
+Configured as such, this timeout is more informative and doesn't do more than assert the "stretch_timeout" interrupt.
+
+If the mode is "BUS_TIMEOUT", it is used to detect whether the clock has been held low for too long instead, inclusive of the controller's clock low time.
+This is useful for an SMBus context, where the VAL programmed should be tTIMEOUT:MIN.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        |
+|:------:|:------:|:-------:|:----------------------------|
+|   31   |   rw   |   0x0   | [EN](#timeout_ctrl--en)     |
+|   30   |   rw   |   0x0   | [MODE](#timeout_ctrl--mode) |
+|  29:0  |   rw   |   0x0   | [VAL](#timeout_ctrl--val)   |
+
+### TIMEOUT_CTRL . EN
+Enable stretch timeout or bus timeout feature
+
+### TIMEOUT_CTRL . MODE
+Selects the timeout mode, between a stretch timeout and a bus timeout.
+
+Between the two modes, the primary difference is how much of the clock low period is counted.
+For a stretch timeout, only the time that another device holds the clock low will be counted.
+For a bus timeout, the entire clock low time is counted, consistent with the SMBus tTIMEOUT type.
+
+[`TIMEOUT_CTRL.EN`](#timeout_ctrl) must be 1 for either of these features to be enabled.
+
+| Value   | Name            | Description                                                                                                                                                                                                                                |
+|:--------|:----------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 0x0     | STRETCH_TIMEOUT | The timeout is a target stretch timeout. The counter will track how long the clock has been stretched by another device while the controller is active.                                                                                    |
+| 0x1     | BUS_TIMEOUT     | The timeout is a clock low timeout. The counter will track how long the clock low period is, inclusive of the controller's ordinary low count. A timeout will set !!CONTROLLER_EVENTS.BUS_TIMEOUT and cause a "controller_halt" interrupt. |
+
+
+### TIMEOUT_CTRL . VAL
+Clock stretching timeout value (in units of input clock frequency)
+
+## TARGET_ID
+I2C target address and mask pairs
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xfffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "ADDRESS1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                   |
+|:------:|:------:|:-------:|:---------|:----------------------------------------------------------------------------------------------|
+| 31:28  |        |         |          | Reserved                                                                                      |
+| 27:21  |   rw   |   0x0   | MASK1    | I2C target mask number 1. At least one bit in MASK1 must be set to 1 for ADDRESS1 to be used. |
+| 20:14  |   rw   |   0x0   | ADDRESS1 | I2C target address number 1                                                                   |
+|  13:7  |   rw   |   0x0   | MASK0    | I2C target mask number 0. At least one bit in MASK0 must be set to 1 for ADDRESS0 to be used. |
+|  6:0   |   rw   |   0x0   | ADDRESS0 | I2C target address number 0                                                                   |
+
+## ACQDATA
+I2C target acquired data
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ABYTE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "SIGNAL", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       |
+|:------:|:------:|:-------:|:---------------------------|
+| 31:11  |        |         | Reserved                   |
+|  10:8  |   ro   |    x    | [SIGNAL](#acqdata--signal) |
+|  7:0   |   ro   |    x    | [ABYTE](#acqdata--abyte)   |
+
+### ACQDATA . SIGNAL
+Indicates any control symbols associated with the ABYTE.
+
+For the STOP symbol, a stretch timeout or other unexpected events will cause a NACK_STOP to appear in the ACQ FIFO.
+If the ACQ FIFO doesn't have enough space to record a START and a STOP, the transaction will be dropped entirely on a stretch timeout.
+In that case, the START byte will not appear (neither as START nor NACK_START), but a standalone NACK_STOP may, if there was space.
+Software can discard any standalone NACK_STOP that appears.
+
+See the associated values for more information about the contents.
+
+| Value   | Name       | Description                                                                                                                                                                                                                                                                                                                                                                                                                                         |
+|:--------|:-----------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 0x0     | NONE       | ABYTE contains an ordinary data byte that was received and ACK'd.                                                                                                                                                                                                                                                                                                                                                                                   |
+| 0x1     | START      | A START condition preceded the ABYTE to start a new transaction. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.                                                                                                                                                                                                                                                                             |
+| 0x2     | STOP       | A STOP condition was received for a transaction including a transfer that addressed this Target. No transfers addressing this Target in that transaction were NACK'd. ABYTE contains no data.                                                                                                                                                                                                                                                       |
+| 0x3     | RESTART    | A repeated START condition preceded the ABYTE, extending the current transaction with a new transfer. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.                                                                                                                                                                                                                                        |
+| 0x4     | NACK       | ABYTE contains an ordinary data byte that was received and NACK'd.                                                                                                                                                                                                                                                                                                                                                                                  |
+| 0x5     | NACK_START | A START condition preceded the ABYTE (including repeated START) that was part of a NACK'd transfer. The ABYTE contains the matching I2C address and command bit. The ABYTE was ACK'd, but the rest of the transaction was NACK'ed.                                                                                                                                                                                                                  |
+| 0x6     | NACK_STOP  | A transaction including a transfer that addressed this Target was ended, but the transaction ended abnormally and/or the transfer was NACK'd. The end can be due to a STOP condition or unexpected events, such as a bus timeout (if enabled). ABYTE contains no data. NACKing can occur for multiple reasons, including a stretch timeout, a SW-directed NACK, or lost arbitration. This signal is a bucket for all these error-type terminations. |
+
+Other values are reserved.
+
+### ACQDATA . ABYTE
+Address for accepted transaction or acquired byte
+
+## TXDATA
+I2C target transmit data
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   wo   |   0x0   | TXDATA |               |
+
+## HOST_TIMEOUT_CTRL
+I2C host clock generation timeout value (in units of input clock frequency).
+
+In an active transaction in Target-Mode, if the Controller ceases to send SCL pulses
+for this number of cycles then the "host_timeout" interrupt will be asserted.
+
+In multi-controller monitoring mode, [`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl) is required to be nonzero to transition out of the initial busy state.
+Set this CSR to 0 to disable this behaviour.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_TIMEOUT_CTRL", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+| 31:20  |        |         |                   | Reserved      |
+|  19:0  |   rw   |   0x0   | HOST_TIMEOUT_CTRL |               |
+
+## TARGET_TIMEOUT_CTRL
+I2C target internal stretching timeout control.
+When the target has stretched beyond this time it will send a NACK for incoming data bytes or release SDA for outgoing data bytes.
+The behavior for the address byte is configurable via [`CTRL.ACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+Note that the count accumulates stretching time over the course of a transaction.
+In other words, this is equivalent to the SMBus cumulative target clock extension time.
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EN     | Enable timeout feature and send NACK once the timeout has been reached |
+|  30:0  |   rw   |   0x0   | VAL    | Clock stretching timeout value (in units of input clock frequency)     |
+
+## TARGET_NACK_COUNT
+Number of times the I2C target has NACK'ed a new transaction since the last read of this register.
+Reading this register clears it.
+This is useful because when the ACQ FIFO is full the software know that a NACK has occurred, but without this register would not know how many transactions it missed.
+When it reaches its maximum value it will stay at that value.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TARGET_NACK_COUNT", "bits": 8, "attr": ["rc"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:8  |        |         |                   | Reserved      |
+|  7:0   |   rc   |   0x0   | TARGET_NACK_COUNT |               |
+
+## TARGET_ACK_CTRL
+Controls for mid-transfer (N)ACK phase handling
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x800001ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "NBYTES", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 22}, {"name": "NACK", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+|   31   |   wo   |    x    | [NACK](#target_ack_ctrl--nack)     |
+|  30:9  |        |         | Reserved                           |
+|  8:0   |   rw   |    x    | [NBYTES](#target_ack_ctrl--nbytes) |
+
+### TARGET_ACK_CTRL . NACK
+When the Target module stretches on the (N)ACK phase of a Write due to [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) being 0, writing a 1 here will cause it to send a NACK.
+
+If software chooses to NACK, note that the NACKing behavior is the same as if a stretch timeout occurred.
+The rest of the transaction will be NACK'd, including subsequent transfers.
+For the address byte, the (N)ACK phase of subsequent transfers will follow the behavior specified by [`CTRL.NACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+
+Automatically clears to 0.
+
+### TARGET_ACK_CTRL . NBYTES
+Remaining number of bytes the Target module may ACK automatically.
+
+If [`CTRL.ACK_CTRL_EN`](#ctrl) is set to 1, the Target module will stretch the clock at the (N)ACK phase of a byte if this CSR is 0, awaiting software's instructions.
+
+At the beginning of each Write transfer, this byte count is reset to 0.
+Writes to this CSR also are only accepted while the Target module is stretching the clock.
+The Target module will always ACK its address if the ACQ FIFO has space.
+For data bytes afterwards, it will stop at the (N)ACK phase and stretch the clock when this CSR is 0.
+For each data byte that is ACK'd in a transaction, the byte count will decrease by 1.
+
+Note that a full ACQ FIFO can still cause the Target module to halt at the beginning of a new byte.
+The ACK Control Mode provides an additional synchronization point, during the (N)ACK phase instead of after.
+For both cases, [`TARGET_TIMEOUT_CTRL`](#target_timeout_ctrl) applies, and stretching past the timeout will produce an automatic NACK.
+
+This mode can be used to implement the mid-transfer (N)ACK responses required by various SMBus protocols.
+
+## ACQ_FIFO_NEXT_DATA
+The data byte pending to be written to the ACQ FIFO.
+
+This CSR is only valid while the Target module is stretching in the (N)ACK phase, indicated by [`STATUS.ACK_CTRL_STRETCH`](#status) .
+It is intended to be used with ACK Control Mode, so software may check the current byte.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ACQ_FIFO_NEXT_DATA", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:8  |        |         |                    | Reserved      |
+|  7:0   |   ro   |    x    | ACQ_FIFO_NEXT_DATA |               |
+
+## HOST_NACK_HANDLER_TIMEOUT
+Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.
+(in units of input clock frequency)
+
+If an active Controller-Transmitter transfer receives a NACK from the Target, the [`CONTROLLER_EVENTS.NACK`](#controller_events) bit is set.
+In turn, this causes the Controller FSM to halt awaiting software intervention, and the 'controller_halt' interrupt may assert.
+Software must clear the [`CONTROLLER_EVENTS.NACK`](#controller_events) bit to allow the state machine to continue, typically after clearing out the FMTFIFO to start a new transfer.
+While halted, the active transaction is not ended (no STOP (P) condition is created), and the block asserts SCL and leaves SDA released.
+
+This timeout can be used to automatically produce a STOP condition, whether as a backstop for slow software responses (longer timeout) or as a convenience (short timeout).
+If the timeout expires, the Controller FSM will issue a STOP (P) condition on the bus to end the active transaction.
+Additionally, the [`CONTROLLER_EVENTS.UNHANDLED_NACK_TIMEOUT`](#controller_events) bit is set to alert software, and the FSM will return to the idle state and halt until the bit is cleared.
+
+The enable bit must be set for this feature to operate.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                     |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EN     | Timeout enable                                                  |
+|  30:0  |   rw   |   0x0   | VAL    | Unhandled NAK timeout value (in units of input clock frequency) |
+
+## CONTROLLER_EVENTS
+Latched events that explain why the controller halted.
+
+Any bits that are set must be written (with a 1) to clear the CONTROLLER_HALT interrupt.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "NACK", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNHANDLED_NACK_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                                                                                               |
+|:------:|:------:|:-------:|:-----------------------|:--------------------------------------------------------------------------------------------------------------------------|
+|  31:4  |        |         |                        | Reserved                                                                                                                  |
+|   3    |  rw1c  |   0x0   | ARBITRATION_LOST       | A Host-Mode active transaction has terminated due to lost arbitration.                                                    |
+|   2    |  rw1c  |   0x0   | BUS_TIMEOUT            | A Host-Mode active transaction has terminated due to a bus timeout activated by [`TIMEOUT_CTRL.`](#timeout_ctrl)          |
+|   1    |  rw1c  |   0x0   | UNHANDLED_NACK_TIMEOUT | A Host-Mode active transaction has been ended by the [`HOST_NACK_HANDLER_TIMEOUT`](#host_nack_handler_timeout) mechanism. |
+|   0    |  rw1c  |   0x0   | NACK                   | Received an unexpected NACK                                                                                               |
+
+## TARGET_EVENTS
+Latched events that can cause the target module to stretch the clock at the beginning of a read transfer.
+
+These events cause TX FIFO-related stretching even when the TX FIFO has data available.
+Any bits that are set must be written (with a 1) to clear the tx_stretch interrupt.
+
+This CSR serves as a gate to prevent the Target module from responding to a read command with unrelated, leftover data.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX_PENDING", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                 |
+|:------:|:------:|:-------:|:-----------------------------------------------------|
+|  31:3  |        |         | Reserved                                             |
+|   2    |  rw1c  |   0x0   | [ARBITRATION_LOST](#target_events--arbitration_lost) |
+|   1    |  rw1c  |   0x0   | [BUS_TIMEOUT](#target_events--bus_timeout)           |
+|   0    |  rw1c  |   0x0   | [TX_PENDING](#target_events--tx_pending)             |
+
+### TARGET_EVENTS . ARBITRATION_LOST
+A Target-Mode read transfer has terminated due to lost arbitration.
+
+### TARGET_EVENTS . BUS_TIMEOUT
+A Target-Mode read transfer has terminated due to a bus timeout activated by [`TIMEOUT_CTRL.`](#timeout_ctrl)
+
+### TARGET_EVENTS . TX_PENDING
+A new Target-Mode read transfer has arrived that addressed this target.
+
+This bit is used by software to confirm the release of the contents in the TX FIFO.
+If the contents do not apply, software should first reset the TX FIFO, then load it with the correct data, then clear this bit.
+
+Optionally enabled by [`CTRL.TX_STRETCH_CTRL_EN.`](#ctrl)
+
+
+
+
+
+## irq_router
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                             | Offset   |   Length | Description                               |
+|:-------------------------------------------------|:---------|---------:|:------------------------------------------|
+| irq_router.[`IRQ_TARGET_MASK`](#irq_target_mask) | 0x0      |        4 | Target selection bitmask control register |
+
+## IRQ_TARGET_MASK
+Target selection bitmask control register
+- Offset: `0x0`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "mask", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x1   | mask   | Target selection bitmask control register for single interrupt line. Reflects interrupt line logic level. |
+
+
+
+
+
+## l2_ecc_config
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                                  | Offset   |   Length | Description                                     |
+|:----------------------------------------------------------------------|:---------|---------:|:------------------------------------------------|
+| ECC_manager.[`mismatch_count`](#mismatch_count)                       | 0x0      |        4 | Correctable mismatches caught by ecc on access  |
+| ECC_manager.[`scrub_interval`](#scrub_interval)                       | 0x4      |        4 | Interval between scrubs                         |
+| ECC_manager.[`scrub_fix_count`](#scrub_fix_count)                     | 0x8      |        4 | Correctable mismatches caught by ecc on scrub   |
+| ECC_manager.[`scrub_uncorrectable_count`](#scrub_uncorrectable_count) | 0xc      |        4 | Uncorrectable mismatches caught by ecc on scrub |
+| ECC_manager.[`write_mask_data_n`](#write_mask_data_n)                 | 0x10     |        4 | Testing: Inverted write mask for data bits      |
+| ECC_manager.[`write_mask_ecc_n`](#write_mask_ecc_n)                   | 0x14     |        4 | Testing: Inverted write mask for ECC bits       |
+
+## mismatch_count
+Correctable mismatches caught by ecc on access
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                    |
+|:------:|:------:|:-------:|:-----------------------|:-----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on access |
+
+## scrub_interval
+Interval between scrubs
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "scrub_interval", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description             |
+|:------:|:------:|:-------:|:---------------|:------------------------|
+|  31:0  |   rw   |   0x0   | scrub_interval | Interval between scrubs |
+
+## scrub_fix_count
+Correctable mismatches caught by ecc on scrub
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                   |
+|:------:|:------:|:-------:|:-----------------------|:----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on scrub |
+
+## scrub_uncorrectable_count
+Uncorrectable mismatches caught by ecc on scrub
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "uncorrectable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description                                     |
+|:------:|:------:|:-------:|:-------------------------|:------------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | uncorrectable_mismatches | Uncorrectable mismatches caught by ecc on scrub |
+
+## write_mask_data_n
+Testing: Inverted write mask for data bits
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_data_n", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                                |
+|:------:|:------:|:-------:|:------------------|:-------------------------------------------|
+|  31:0  |   rw   |   0x0   | write_mask_data_n | Testing: Inverted write mask for data bits |
+
+## write_mask_ecc_n
+Testing: Inverted write mask for ECC bits
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_ecc_n", "bits": 7, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                               |
+|:------:|:------:|:-------:|:-----------------|:------------------------------------------|
+|  31:7  |        |         |                  | Reserved                                  |
+|  6:0   |   rw   |   0x0   | write_mask_ecc_n | Testing: Inverted write mask for ECC bits |
+
+
+
+
+
+## mailbox
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                    | Offset   |   Length | Description                                 |
+|:----------------------------------------|:---------|---------:|:--------------------------------------------|
+| mailbox.[`IRQ_SND_STAT`](#irq_snd_stat) | 0x0      |        4 | Sender interrupt status register            |
+| mailbox.[`IRQ_SND_SET`](#irq_snd_set)   | 0x4      |        4 | Sender interrupt set register               |
+| mailbox.[`IRQ_SND_CLR`](#irq_snd_clr)   | 0x8      |        4 | Sender interrupt clear register             |
+| mailbox.[`IRQ_SND_EN`](#irq_snd_en)     | 0xc      |        4 | Sender interrupt enable register            |
+| mailbox.[`IRQ_RCV_STAT`](#irq_rcv_stat) | 0x40     |        4 | Receiver interrupt status register          |
+| mailbox.[`IRQ_RCV_SET`](#irq_rcv_set)   | 0x44     |        4 | Receiver interrupt set register             |
+| mailbox.[`IRQ_RCV_CLR`](#irq_rcv_clr)   | 0x48     |        4 | Receiver interrupt clear register           |
+| mailbox.[`IRQ_RCV_EN`](#irq_rcv_en)     | 0x4c     |        4 | Receiver interrupt enable register          |
+| mailbox.[`LETTER0`](#letter0)           | 0x80     |        4 | Memory region 0 to put a message or pointer |
+| mailbox.[`LETTER1`](#letter1)           | 0x84     |        4 | Memory region 1 to put a message or pointer |
+
+## IRQ_SND_STAT
+Sender interrupt status register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stat", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                  |
+|:------:|:------:|:-------:|:---------|:---------------------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                                     |
+|   0    |   ro   |    x    | stat     | Sender side interrupt status. Receiver confirms letter. Reflects interrupt line logic level. |
+
+## IRQ_SND_SET
+Sender interrupt set register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "set", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                          |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                             |
+|   0    |   wo   |    x    | set      | Sender side interrupt set. Receiver confirms letter. |
+
+## IRQ_SND_CLR
+Sender interrupt clear register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clr", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                            |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                               |
+|   0    |   wo   |    x    | clr      | Sender side interrupt clear. Receiver confirms letter. |
+
+## IRQ_SND_EN
+Sender interrupt enable register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                             |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------|
+|  31:1  |   ro   |   0x0   | reserved | reserved                                                |
+|   0    |   rw   |   0x0   | en       | Sender side interrupt enable. Receiver confirms letter. |
+
+## IRQ_RCV_STAT
+Receiver interrupt status register
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stat", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                                             |
+|:------:|:------:|:-------:|:---------|:------------------------------------------------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                                                                |
+|   0    |   ro   |    x    | stat     | Receiver side interrupt status. Sender notifies receiver of a new letter arriving. Reflects interrupt line logic level. |
+
+## IRQ_RCV_SET
+Receiver interrupt set register
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "set", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                     |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                        |
+|   0    |   wo   |    x    | set      | Receiver side interrupt set. Sender notifies receiver of a new letter arriving. |
+
+## IRQ_RCV_CLR
+Receiver interrupt clear register
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clr", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                          |
+|   0    |   wo   |    x    | clr      | Receiver side interrupt clear. Sender notifies receiver of a new letter arriving. |
+
+## IRQ_RCV_EN
+Receiver interrupt enable register
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                        |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------------------------------------------------|
+|  31:1  |   ro   |   0x0   | reserved | reserved                                                                           |
+|   0    |   rw   |   0x0   | en       | Receiver side interrupt enable. Sender notifies receiver of a new letter arriving. |
+
+## LETTER0
+Memory region 0 to put a message or pointer
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LETTER0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   rw   |   0x0   | LETTER0 |               |
+
+## LETTER1
+Memory region 1 to put a message or pointer
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LETTER1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   rw   |   0x0   | LETTER1 |               |
+
+
+
+
+
+## plic
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                | Offset    |   Length | Description                                                        |
+|:------------------------------------|:----------|---------:|:-------------------------------------------------------------------|
+| rv_plic.[`PRIO0`](#prio0)           | 0x0       |        4 | Interrupt Source 0 Priority                                        |
+| rv_plic.[`PRIO1`](#prio1)           | 0x4       |        4 | Interrupt Source 1 Priority                                        |
+| rv_plic.[`PRIO2`](#prio2)           | 0x8       |        4 | Interrupt Source 2 Priority                                        |
+| rv_plic.[`PRIO3`](#prio3)           | 0xc       |        4 | Interrupt Source 3 Priority                                        |
+| rv_plic.[`PRIO4`](#prio4)           | 0x10      |        4 | Interrupt Source 4 Priority                                        |
+| rv_plic.[`PRIO5`](#prio5)           | 0x14      |        4 | Interrupt Source 5 Priority                                        |
+| rv_plic.[`PRIO6`](#prio6)           | 0x18      |        4 | Interrupt Source 6 Priority                                        |
+| rv_plic.[`PRIO7`](#prio7)           | 0x1c      |        4 | Interrupt Source 7 Priority                                        |
+| rv_plic.[`PRIO8`](#prio8)           | 0x20      |        4 | Interrupt Source 8 Priority                                        |
+| rv_plic.[`PRIO9`](#prio9)           | 0x24      |        4 | Interrupt Source 9 Priority                                        |
+| rv_plic.[`PRIO10`](#prio10)         | 0x28      |        4 | Interrupt Source 10 Priority                                       |
+| rv_plic.[`PRIO11`](#prio11)         | 0x2c      |        4 | Interrupt Source 11 Priority                                       |
+| rv_plic.[`PRIO12`](#prio12)         | 0x30      |        4 | Interrupt Source 12 Priority                                       |
+| rv_plic.[`PRIO13`](#prio13)         | 0x34      |        4 | Interrupt Source 13 Priority                                       |
+| rv_plic.[`PRIO14`](#prio14)         | 0x38      |        4 | Interrupt Source 14 Priority                                       |
+| rv_plic.[`PRIO15`](#prio15)         | 0x3c      |        4 | Interrupt Source 15 Priority                                       |
+| rv_plic.[`PRIO16`](#prio16)         | 0x40      |        4 | Interrupt Source 16 Priority                                       |
+| rv_plic.[`PRIO17`](#prio17)         | 0x44      |        4 | Interrupt Source 17 Priority                                       |
+| rv_plic.[`PRIO18`](#prio18)         | 0x48      |        4 | Interrupt Source 18 Priority                                       |
+| rv_plic.[`PRIO19`](#prio19)         | 0x4c      |        4 | Interrupt Source 19 Priority                                       |
+| rv_plic.[`PRIO20`](#prio20)         | 0x50      |        4 | Interrupt Source 20 Priority                                       |
+| rv_plic.[`PRIO21`](#prio21)         | 0x54      |        4 | Interrupt Source 21 Priority                                       |
+| rv_plic.[`PRIO22`](#prio22)         | 0x58      |        4 | Interrupt Source 22 Priority                                       |
+| rv_plic.[`PRIO23`](#prio23)         | 0x5c      |        4 | Interrupt Source 23 Priority                                       |
+| rv_plic.[`PRIO24`](#prio24)         | 0x60      |        4 | Interrupt Source 24 Priority                                       |
+| rv_plic.[`PRIO25`](#prio25)         | 0x64      |        4 | Interrupt Source 25 Priority                                       |
+| rv_plic.[`PRIO26`](#prio26)         | 0x68      |        4 | Interrupt Source 26 Priority                                       |
+| rv_plic.[`PRIO27`](#prio27)         | 0x6c      |        4 | Interrupt Source 27 Priority                                       |
+| rv_plic.[`PRIO28`](#prio28)         | 0x70      |        4 | Interrupt Source 28 Priority                                       |
+| rv_plic.[`PRIO29`](#prio29)         | 0x74      |        4 | Interrupt Source 29 Priority                                       |
+| rv_plic.[`PRIO30`](#prio30)         | 0x78      |        4 | Interrupt Source 30 Priority                                       |
+| rv_plic.[`PRIO31`](#prio31)         | 0x7c      |        4 | Interrupt Source 31 Priority                                       |
+| rv_plic.[`IP`](#IP)                 | 0x1000    |        4 | Interrupt Pending                                                  |
+| rv_plic.[`IE0`](#IE0)               | 0x2000    |        4 | Interrupt Enable for Target 0                                      |
+| rv_plic.[`THRESHOLD0`](#threshold0) | 0x200000  |        4 | Threshold of priority for Target 0                                 |
+| rv_plic.[`CC0`](#cc0)               | 0x200004  |        4 | Claim interrupt by read, complete interrupt by write for Target 0. |
+| rv_plic.[`MSIP0`](#msip0)           | 0x4000000 |        4 | msip for Hart 0.                                                   |
+| rv_plic.[`ALERT_TEST`](#alert_test) | 0x4004000 |        4 | Alert Test Register.                                               |
+
+## PRIO0
+Interrupt Source 0 Priority
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO0  |               |
+
+## PRIO1
+Interrupt Source 1 Priority
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO1  |               |
+
+## PRIO2
+Interrupt Source 2 Priority
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO2  |               |
+
+## PRIO3
+Interrupt Source 3 Priority
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO3  |               |
+
+## PRIO4
+Interrupt Source 4 Priority
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO4", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO4  |               |
+
+## PRIO5
+Interrupt Source 5 Priority
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO5", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO5  |               |
+
+## PRIO6
+Interrupt Source 6 Priority
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO6", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO6  |               |
+
+## PRIO7
+Interrupt Source 7 Priority
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO7", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO7  |               |
+
+## PRIO8
+Interrupt Source 8 Priority
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO8", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO8  |               |
+
+## PRIO9
+Interrupt Source 9 Priority
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO9", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO9  |               |
+
+## PRIO10
+Interrupt Source 10 Priority
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO10", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO10 |               |
+
+## PRIO11
+Interrupt Source 11 Priority
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO11", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO11 |               |
+
+## PRIO12
+Interrupt Source 12 Priority
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO12", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO12 |               |
+
+## PRIO13
+Interrupt Source 13 Priority
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO13", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO13 |               |
+
+## PRIO14
+Interrupt Source 14 Priority
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO14", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO14 |               |
+
+## PRIO15
+Interrupt Source 15 Priority
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO15", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO15 |               |
+
+## PRIO16
+Interrupt Source 16 Priority
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO16", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO16 |               |
+
+## PRIO17
+Interrupt Source 17 Priority
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO17", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO17 |               |
+
+## PRIO18
+Interrupt Source 18 Priority
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO18", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO18 |               |
+
+## PRIO19
+Interrupt Source 19 Priority
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO19", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO19 |               |
+
+## PRIO20
+Interrupt Source 20 Priority
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO20", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO20 |               |
+
+## PRIO21
+Interrupt Source 21 Priority
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO21", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO21 |               |
+
+## PRIO22
+Interrupt Source 22 Priority
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO22", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO22 |               |
+
+## PRIO23
+Interrupt Source 23 Priority
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO23", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO23 |               |
+
+## PRIO24
+Interrupt Source 24 Priority
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO24", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO24 |               |
+
+## PRIO25
+Interrupt Source 25 Priority
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO25", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO25 |               |
+
+## PRIO26
+Interrupt Source 26 Priority
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO26", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO26 |               |
+
+## PRIO27
+Interrupt Source 27 Priority
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO27", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO27 |               |
+
+## PRIO28
+Interrupt Source 28 Priority
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO28", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO28 |               |
+
+## PRIO29
+Interrupt Source 29 Priority
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO29", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO29 |               |
+
+## PRIO30
+Interrupt Source 30 Priority
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO30", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO30 |               |
+
+## PRIO31
+Interrupt Source 31 Priority
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO31", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO31 |               |
+
+## IP
+Interrupt Pending
+- Offset: `0x1000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "P_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_9", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_10", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_11", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_12", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_13", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_14", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_15", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_16", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_17", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_18", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_19", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_20", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_21", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_22", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_23", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_24", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_25", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_26", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_27", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_28", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_29", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_30", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_31", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                 |
+|:------:|:------:|:-------:|:-------|:----------------------------|
+|   31   |   ro   |   0x0   | P_31   | Interrupt Pending of Source |
+|   30   |   ro   |   0x0   | P_30   | Interrupt Pending of Source |
+|   29   |   ro   |   0x0   | P_29   | Interrupt Pending of Source |
+|   28   |   ro   |   0x0   | P_28   | Interrupt Pending of Source |
+|   27   |   ro   |   0x0   | P_27   | Interrupt Pending of Source |
+|   26   |   ro   |   0x0   | P_26   | Interrupt Pending of Source |
+|   25   |   ro   |   0x0   | P_25   | Interrupt Pending of Source |
+|   24   |   ro   |   0x0   | P_24   | Interrupt Pending of Source |
+|   23   |   ro   |   0x0   | P_23   | Interrupt Pending of Source |
+|   22   |   ro   |   0x0   | P_22   | Interrupt Pending of Source |
+|   21   |   ro   |   0x0   | P_21   | Interrupt Pending of Source |
+|   20   |   ro   |   0x0   | P_20   | Interrupt Pending of Source |
+|   19   |   ro   |   0x0   | P_19   | Interrupt Pending of Source |
+|   18   |   ro   |   0x0   | P_18   | Interrupt Pending of Source |
+|   17   |   ro   |   0x0   | P_17   | Interrupt Pending of Source |
+|   16   |   ro   |   0x0   | P_16   | Interrupt Pending of Source |
+|   15   |   ro   |   0x0   | P_15   | Interrupt Pending of Source |
+|   14   |   ro   |   0x0   | P_14   | Interrupt Pending of Source |
+|   13   |   ro   |   0x0   | P_13   | Interrupt Pending of Source |
+|   12   |   ro   |   0x0   | P_12   | Interrupt Pending of Source |
+|   11   |   ro   |   0x0   | P_11   | Interrupt Pending of Source |
+|   10   |   ro   |   0x0   | P_10   | Interrupt Pending of Source |
+|   9    |   ro   |   0x0   | P_9    | Interrupt Pending of Source |
+|   8    |   ro   |   0x0   | P_8    | Interrupt Pending of Source |
+|   7    |   ro   |   0x0   | P_7    | Interrupt Pending of Source |
+|   6    |   ro   |   0x0   | P_6    | Interrupt Pending of Source |
+|   5    |   ro   |   0x0   | P_5    | Interrupt Pending of Source |
+|   4    |   ro   |   0x0   | P_4    | Interrupt Pending of Source |
+|   3    |   ro   |   0x0   | P_3    | Interrupt Pending of Source |
+|   2    |   ro   |   0x0   | P_2    | Interrupt Pending of Source |
+|   1    |   ro   |   0x0   | P_1    | Interrupt Pending of Source |
+|   0    |   ro   |   0x0   | P_0    | Interrupt Pending of Source |
+
+## IE0
+Interrupt Enable for Target 0
+- Offset: `0x2000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "E_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                |
+|:------:|:------:|:-------:|:-------|:---------------------------|
+|   31   |   rw   |   0x0   | E_31   | Interrupt Enable of Source |
+|   30   |   rw   |   0x0   | E_30   | Interrupt Enable of Source |
+|   29   |   rw   |   0x0   | E_29   | Interrupt Enable of Source |
+|   28   |   rw   |   0x0   | E_28   | Interrupt Enable of Source |
+|   27   |   rw   |   0x0   | E_27   | Interrupt Enable of Source |
+|   26   |   rw   |   0x0   | E_26   | Interrupt Enable of Source |
+|   25   |   rw   |   0x0   | E_25   | Interrupt Enable of Source |
+|   24   |   rw   |   0x0   | E_24   | Interrupt Enable of Source |
+|   23   |   rw   |   0x0   | E_23   | Interrupt Enable of Source |
+|   22   |   rw   |   0x0   | E_22   | Interrupt Enable of Source |
+|   21   |   rw   |   0x0   | E_21   | Interrupt Enable of Source |
+|   20   |   rw   |   0x0   | E_20   | Interrupt Enable of Source |
+|   19   |   rw   |   0x0   | E_19   | Interrupt Enable of Source |
+|   18   |   rw   |   0x0   | E_18   | Interrupt Enable of Source |
+|   17   |   rw   |   0x0   | E_17   | Interrupt Enable of Source |
+|   16   |   rw   |   0x0   | E_16   | Interrupt Enable of Source |
+|   15   |   rw   |   0x0   | E_15   | Interrupt Enable of Source |
+|   14   |   rw   |   0x0   | E_14   | Interrupt Enable of Source |
+|   13   |   rw   |   0x0   | E_13   | Interrupt Enable of Source |
+|   12   |   rw   |   0x0   | E_12   | Interrupt Enable of Source |
+|   11   |   rw   |   0x0   | E_11   | Interrupt Enable of Source |
+|   10   |   rw   |   0x0   | E_10   | Interrupt Enable of Source |
+|   9    |   rw   |   0x0   | E_9    | Interrupt Enable of Source |
+|   8    |   rw   |   0x0   | E_8    | Interrupt Enable of Source |
+|   7    |   rw   |   0x0   | E_7    | Interrupt Enable of Source |
+|   6    |   rw   |   0x0   | E_6    | Interrupt Enable of Source |
+|   5    |   rw   |   0x0   | E_5    | Interrupt Enable of Source |
+|   4    |   rw   |   0x0   | E_4    | Interrupt Enable of Source |
+|   3    |   rw   |   0x0   | E_3    | Interrupt Enable of Source |
+|   2    |   rw   |   0x0   | E_2    | Interrupt Enable of Source |
+|   1    |   rw   |   0x0   | E_1    | Interrupt Enable of Source |
+|   0    |   rw   |   0x0   | E_0    | Interrupt Enable of Source |
+
+## THRESHOLD0
+Threshold of priority for Target 0
+- Offset: `0x200000`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "THRESHOLD0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:3  |        |         |            | Reserved      |
+|  2:0   |   rw   |   0x0   | THRESHOLD0 |               |
+
+## CC0
+Claim interrupt by read, complete interrupt by write for Target 0.
+Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.
+- Offset: `0x200004`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CC0", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:5  |        |         |        | Reserved      |
+|  4:0   |   rw   |    x    | CC0    |               |
+
+## MSIP0
+msip for Hart 0.
+Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.
+- Offset: `0x4000000`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSIP0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:1  |        |         |        | Reserved                            |
+|   0    |   rw   |   0x0   | MSIP0  | Software Interrupt Pending register |
+
+## ALERT_TEST
+Alert Test Register.
+- Offset: `0x4004000`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                        |
+|:------:|:------:|:-------:|:------------|:---------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                           |
+|   0    |   wo   |    x    | fatal_fault | 'Write 1 to trigger one alert event of this kind.' |
+
+
+
+
+
+## safety_island
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                        | Offset   |   Length | Description                            |
+|:--------------------------------------------|:---------|---------:|:---------------------------------------|
+| safety_soc_ctrl.[`bootaddr`](#bootaddr)     | 0x0      |        4 | Core Boot Address                      |
+| safety_soc_ctrl.[`fetchen`](#fetchen)       | 0x4      |        4 | Core Fetch Enable                      |
+| safety_soc_ctrl.[`corestatus`](#corestatus) | 0x8      |        4 | Core Return Status (return value, EOC) |
+| safety_soc_ctrl.[`bootmode`](#bootmode)     | 0xc      |        4 | Core Boot Mode                         |
+
+## bootaddr
+Core Boot Address
+- Offset: `0x0`
+- Reset default: `0x1a000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description   |
+|:------:|:------:|:----------:|:---------|:--------------|
+|  31:0  |   rw   | 0x1a000000 | bootaddr | Boot Address  |
+
+## fetchen
+Core Fetch Enable
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:1  |        |         |         | Reserved      |
+|   0    |   rw   |   0x0   | fetchen | Fetch Enable  |
+
+## corestatus
+Core Return Status (return value, EOC)
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                             |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) |
+
+## bootmode
+Core Boot Mode
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:2  |        |         |          | Reserved      |
+|  1:0   |   rw   |   0x0   | bootmode | Boot Mode     |
+
+
+
+
+
+## serial_link
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                                      | Offset   |   Length | Description                                                                   |
+|:--------------------------------------------------------------------------|:---------|---------:|:------------------------------------------------------------------------------|
+| serial_link.[`CTRL`](#ctrl)                                               | 0x0      |        4 | Global clock, isolation and reset control configuration                       |
+| serial_link.[`ISOLATED`](#isolated)                                       | 0x4      |        4 | Isolation status of AXI ports                                                 |
+| serial_link.[`TX_PHY_CLK_DIV_0`](#tx_phy_clk_div)                         | 0x8      |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_1`](#tx_phy_clk_div)                         | 0xc      |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_2`](#tx_phy_clk_div)                         | 0x10     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_3`](#tx_phy_clk_div)                         | 0x14     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_4`](#tx_phy_clk_div)                         | 0x18     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_5`](#tx_phy_clk_div)                         | 0x1c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_6`](#tx_phy_clk_div)                         | 0x20     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_7`](#tx_phy_clk_div)                         | 0x24     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_8`](#tx_phy_clk_div)                         | 0x28     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_9`](#tx_phy_clk_div)                         | 0x2c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_10`](#tx_phy_clk_div)                        | 0x30     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_11`](#tx_phy_clk_div)                        | 0x34     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_12`](#tx_phy_clk_div)                        | 0x38     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_13`](#tx_phy_clk_div)                        | 0x3c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_14`](#tx_phy_clk_div)                        | 0x40     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_15`](#tx_phy_clk_div)                        | 0x44     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_16`](#tx_phy_clk_div)                        | 0x48     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_17`](#tx_phy_clk_div)                        | 0x4c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_18`](#tx_phy_clk_div)                        | 0x50     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_19`](#tx_phy_clk_div)                        | 0x54     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_20`](#tx_phy_clk_div)                        | 0x58     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_21`](#tx_phy_clk_div)                        | 0x5c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_22`](#tx_phy_clk_div)                        | 0x60     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_23`](#tx_phy_clk_div)                        | 0x64     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_24`](#tx_phy_clk_div)                        | 0x68     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_25`](#tx_phy_clk_div)                        | 0x6c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_26`](#tx_phy_clk_div)                        | 0x70     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_27`](#tx_phy_clk_div)                        | 0x74     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_28`](#tx_phy_clk_div)                        | 0x78     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_29`](#tx_phy_clk_div)                        | 0x7c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_30`](#tx_phy_clk_div)                        | 0x80     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_31`](#tx_phy_clk_div)                        | 0x84     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_32`](#tx_phy_clk_div)                        | 0x88     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_33`](#tx_phy_clk_div)                        | 0x8c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_34`](#tx_phy_clk_div)                        | 0x90     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_35`](#tx_phy_clk_div)                        | 0x94     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_36`](#tx_phy_clk_div)                        | 0x98     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_37`](#tx_phy_clk_div)                        | 0x9c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_START_0`](#tx_phy_clk_start)                     | 0xa0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_1`](#tx_phy_clk_start)                     | 0xa4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_2`](#tx_phy_clk_start)                     | 0xa8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_3`](#tx_phy_clk_start)                     | 0xac     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_4`](#tx_phy_clk_start)                     | 0xb0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_5`](#tx_phy_clk_start)                     | 0xb4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_6`](#tx_phy_clk_start)                     | 0xb8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_7`](#tx_phy_clk_start)                     | 0xbc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_8`](#tx_phy_clk_start)                     | 0xc0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_9`](#tx_phy_clk_start)                     | 0xc4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_10`](#tx_phy_clk_start)                    | 0xc8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_11`](#tx_phy_clk_start)                    | 0xcc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_12`](#tx_phy_clk_start)                    | 0xd0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_13`](#tx_phy_clk_start)                    | 0xd4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_14`](#tx_phy_clk_start)                    | 0xd8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_15`](#tx_phy_clk_start)                    | 0xdc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_16`](#tx_phy_clk_start)                    | 0xe0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_17`](#tx_phy_clk_start)                    | 0xe4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_18`](#tx_phy_clk_start)                    | 0xe8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_19`](#tx_phy_clk_start)                    | 0xec     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_20`](#tx_phy_clk_start)                    | 0xf0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_21`](#tx_phy_clk_start)                    | 0xf4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_22`](#tx_phy_clk_start)                    | 0xf8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_23`](#tx_phy_clk_start)                    | 0xfc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_24`](#tx_phy_clk_start)                    | 0x100    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_25`](#tx_phy_clk_start)                    | 0x104    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_26`](#tx_phy_clk_start)                    | 0x108    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_27`](#tx_phy_clk_start)                    | 0x10c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_28`](#tx_phy_clk_start)                    | 0x110    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_29`](#tx_phy_clk_start)                    | 0x114    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_30`](#tx_phy_clk_start)                    | 0x118    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_31`](#tx_phy_clk_start)                    | 0x11c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_32`](#tx_phy_clk_start)                    | 0x120    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_33`](#tx_phy_clk_start)                    | 0x124    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_34`](#tx_phy_clk_start)                    | 0x128    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_35`](#tx_phy_clk_start)                    | 0x12c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_36`](#tx_phy_clk_start)                    | 0x130    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_37`](#tx_phy_clk_start)                    | 0x134    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_END_0`](#tx_phy_clk_end)                         | 0x138    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_1`](#tx_phy_clk_end)                         | 0x13c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_2`](#tx_phy_clk_end)                         | 0x140    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_3`](#tx_phy_clk_end)                         | 0x144    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_4`](#tx_phy_clk_end)                         | 0x148    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_5`](#tx_phy_clk_end)                         | 0x14c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_6`](#tx_phy_clk_end)                         | 0x150    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_7`](#tx_phy_clk_end)                         | 0x154    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_8`](#tx_phy_clk_end)                         | 0x158    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_9`](#tx_phy_clk_end)                         | 0x15c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_10`](#tx_phy_clk_end)                        | 0x160    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_11`](#tx_phy_clk_end)                        | 0x164    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_12`](#tx_phy_clk_end)                        | 0x168    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_13`](#tx_phy_clk_end)                        | 0x16c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_14`](#tx_phy_clk_end)                        | 0x170    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_15`](#tx_phy_clk_end)                        | 0x174    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_16`](#tx_phy_clk_end)                        | 0x178    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_17`](#tx_phy_clk_end)                        | 0x17c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_18`](#tx_phy_clk_end)                        | 0x180    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_19`](#tx_phy_clk_end)                        | 0x184    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_20`](#tx_phy_clk_end)                        | 0x188    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_21`](#tx_phy_clk_end)                        | 0x18c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_22`](#tx_phy_clk_end)                        | 0x190    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_23`](#tx_phy_clk_end)                        | 0x194    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_24`](#tx_phy_clk_end)                        | 0x198    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_25`](#tx_phy_clk_end)                        | 0x19c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_26`](#tx_phy_clk_end)                        | 0x1a0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_27`](#tx_phy_clk_end)                        | 0x1a4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_28`](#tx_phy_clk_end)                        | 0x1a8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_29`](#tx_phy_clk_end)                        | 0x1ac    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_30`](#tx_phy_clk_end)                        | 0x1b0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_31`](#tx_phy_clk_end)                        | 0x1b4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_32`](#tx_phy_clk_end)                        | 0x1b8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_33`](#tx_phy_clk_end)                        | 0x1bc    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_34`](#tx_phy_clk_end)                        | 0x1c0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_35`](#tx_phy_clk_end)                        | 0x1c4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_36`](#tx_phy_clk_end)                        | 0x1c8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_37`](#tx_phy_clk_end)                        | 0x1cc    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`RAW_MODE_EN`](#raw_mode_en)                                 | 0x1d0    |        4 | Enables Raw mode                                                              |
+| serial_link.[`RAW_MODE_IN_CH_SEL`](#raw_mode_in_ch_sel)                   | 0x1d4    |        4 | Receive channel select in RAW mode                                            |
+| serial_link.[`RAW_MODE_IN_DATA_VALID_0`](#RAW_MODE_IN_DATA_VALID_0)       | 0x1d8    |        4 | Mask for valid data in RX FIFOs during RAW mode.                              |
+| serial_link.[`RAW_MODE_IN_DATA_VALID_1`](#RAW_MODE_IN_DATA_VALID_1)       | 0x1dc    |        4 | Mask for valid data in RX FIFOs during RAW mode.                              |
+| serial_link.[`RAW_MODE_IN_DATA`](#raw_mode_in_data)                       | 0x1e0    |        4 | Data received by the selected channel in RAW mode                             |
+| serial_link.[`RAW_MODE_OUT_CH_MASK_0`](#RAW_MODE_OUT_CH_MASK_0)           | 0x1e4    |        4 | Selects channels to send out data in RAW mode, '1 corresponds to broadcasting |
+| serial_link.[`RAW_MODE_OUT_CH_MASK_1`](#RAW_MODE_OUT_CH_MASK_1)           | 0x1e8    |        4 | Selects channels to send out data in RAW mode, '1 corresponds to broadcasting |
+| serial_link.[`RAW_MODE_OUT_DATA_FIFO`](#raw_mode_out_data_fifo)           | 0x1ec    |        4 | Data that will be pushed to the RAW mode output FIFO                          |
+| serial_link.[`RAW_MODE_OUT_DATA_FIFO_CTRL`](#raw_mode_out_data_fifo_ctrl) | 0x1f0    |        4 | Status and control register for the RAW mode data out FIFO                    |
+| serial_link.[`RAW_MODE_OUT_EN`](#raw_mode_out_en)                         | 0x1f4    |        4 | Enable transmission of data currently hold in the output FIFO                 |
+| serial_link.[`FLOW_CONTROL_FIFO_CLEAR`](#flow_control_fifo_clear)         | 0x1f8    |        4 | Clears the flow control Fifo                                                  |
+| serial_link.[`CHANNEL_ALLOC_TX_CFG`](#channel_alloc_tx_cfg)               | 0x1fc    |        4 | Configuration settings for the TX side in the channel allocator               |
+| serial_link.[`CHANNEL_ALLOC_TX_CH_EN_0`](#CHANNEL_ALLOC_TX_CH_EN_0)       | 0x200    |        4 | Channel enable mask for the TX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_TX_CH_EN_1`](#CHANNEL_ALLOC_TX_CH_EN_1)       | 0x204    |        4 | Channel enable mask for the TX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_TX_CTRL`](#channel_alloc_tx_ctrl)             | 0x208    |        4 | Soft clear or force flush the TX side of the channel allocator                |
+| serial_link.[`CHANNEL_ALLOC_RX_CFG`](#channel_alloc_rx_cfg)               | 0x20c    |        4 | Configuration settings for the RX side in the channel allocator               |
+| serial_link.[`CHANNEL_ALLOC_RX_CTRL`](#channel_alloc_rx_ctrl)             | 0x210    |        4 | Soft clear the RX side of the channel allocator                               |
+| serial_link.[`CHANNEL_ALLOC_RX_CH_EN_0`](#CHANNEL_ALLOC_RX_CH_EN_0)       | 0x214    |        4 | Channel enable mask for the RX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_RX_CH_EN_1`](#CHANNEL_ALLOC_RX_CH_EN_1)       | 0x218    |        4 | Channel enable mask for the RX side.                                          |
+
+## CTRL
+Global clock, isolation and reset control configuration
+- Offset: `0x0`
+- Reset default: `0x302`
+- Reset mask: `0x303`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_ena", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reset_n", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "axi_in_isolate", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "axi_out_isolate", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                                                        |
+|:------:|:------:|:-------:|:----------------|:-------------------------------------------------------------------|
+| 31:10  |        |         |                 | Reserved                                                           |
+|   9    |   rw   |   0x1   | axi_out_isolate | Isolate AXI master out port. (active-high)                         |
+|   8    |   rw   |   0x1   | axi_in_isolate  | Isolate AXI slave in port. (active-high)                           |
+|  7:2   |        |         |                 | Reserved                                                           |
+|   1    |   rw   |   0x1   | reset_n         | SW controlled synchronous reset. (active-low)                      |
+|   0    |   rw   |   0x0   | clk_ena         | Clock gate enable for network, link, physical layer. (active-high) |
+
+## ISOLATED
+Isolation status of AXI ports
+- Offset: `0x4`
+- Reset default: `0x3`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "axi_in", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "axi_out", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                 |
+|:------:|:------:|:-------:|:--------|:----------------------------|
+|  31:2  |        |         |         | Reserved                    |
+|   1    |   ro   |   0x1   | axi_out | master out isolation status |
+|   0    |   ro   |   0x1   | axi_in  | slave in isolation status   |
+
+## TX_PHY_CLK_DIV
+Holds clock divider factor for forwarded clock of the TX Phys
+- Reset default: `0x8`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name              | Offset   |
+|:------------------|:---------|
+| TX_PHY_CLK_DIV_0  | 0x8      |
+| TX_PHY_CLK_DIV_1  | 0xc      |
+| TX_PHY_CLK_DIV_2  | 0x10     |
+| TX_PHY_CLK_DIV_3  | 0x14     |
+| TX_PHY_CLK_DIV_4  | 0x18     |
+| TX_PHY_CLK_DIV_5  | 0x1c     |
+| TX_PHY_CLK_DIV_6  | 0x20     |
+| TX_PHY_CLK_DIV_7  | 0x24     |
+| TX_PHY_CLK_DIV_8  | 0x28     |
+| TX_PHY_CLK_DIV_9  | 0x2c     |
+| TX_PHY_CLK_DIV_10 | 0x30     |
+| TX_PHY_CLK_DIV_11 | 0x34     |
+| TX_PHY_CLK_DIV_12 | 0x38     |
+| TX_PHY_CLK_DIV_13 | 0x3c     |
+| TX_PHY_CLK_DIV_14 | 0x40     |
+| TX_PHY_CLK_DIV_15 | 0x44     |
+| TX_PHY_CLK_DIV_16 | 0x48     |
+| TX_PHY_CLK_DIV_17 | 0x4c     |
+| TX_PHY_CLK_DIV_18 | 0x50     |
+| TX_PHY_CLK_DIV_19 | 0x54     |
+| TX_PHY_CLK_DIV_20 | 0x58     |
+| TX_PHY_CLK_DIV_21 | 0x5c     |
+| TX_PHY_CLK_DIV_22 | 0x60     |
+| TX_PHY_CLK_DIV_23 | 0x64     |
+| TX_PHY_CLK_DIV_24 | 0x68     |
+| TX_PHY_CLK_DIV_25 | 0x6c     |
+| TX_PHY_CLK_DIV_26 | 0x70     |
+| TX_PHY_CLK_DIV_27 | 0x74     |
+| TX_PHY_CLK_DIV_28 | 0x78     |
+| TX_PHY_CLK_DIV_29 | 0x7c     |
+| TX_PHY_CLK_DIV_30 | 0x80     |
+| TX_PHY_CLK_DIV_31 | 0x84     |
+| TX_PHY_CLK_DIV_32 | 0x88     |
+| TX_PHY_CLK_DIV_33 | 0x8c     |
+| TX_PHY_CLK_DIV_34 | 0x90     |
+| TX_PHY_CLK_DIV_35 | 0x94     |
+| TX_PHY_CLK_DIV_36 | 0x98     |
+| TX_PHY_CLK_DIV_37 | 0x9c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_divs", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------|
+| 31:11  |        |         |          | Reserved                          |
+|  10:0  |   rw   |   0x8   | clk_divs | Clock division factor of TX clock |
+
+## TX_PHY_CLK_START
+Controls duty cycle and phase of rising edge in TX Phys
+- Reset default: `0x2`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| TX_PHY_CLK_START_0  | 0xa0     |
+| TX_PHY_CLK_START_1  | 0xa4     |
+| TX_PHY_CLK_START_2  | 0xa8     |
+| TX_PHY_CLK_START_3  | 0xac     |
+| TX_PHY_CLK_START_4  | 0xb0     |
+| TX_PHY_CLK_START_5  | 0xb4     |
+| TX_PHY_CLK_START_6  | 0xb8     |
+| TX_PHY_CLK_START_7  | 0xbc     |
+| TX_PHY_CLK_START_8  | 0xc0     |
+| TX_PHY_CLK_START_9  | 0xc4     |
+| TX_PHY_CLK_START_10 | 0xc8     |
+| TX_PHY_CLK_START_11 | 0xcc     |
+| TX_PHY_CLK_START_12 | 0xd0     |
+| TX_PHY_CLK_START_13 | 0xd4     |
+| TX_PHY_CLK_START_14 | 0xd8     |
+| TX_PHY_CLK_START_15 | 0xdc     |
+| TX_PHY_CLK_START_16 | 0xe0     |
+| TX_PHY_CLK_START_17 | 0xe4     |
+| TX_PHY_CLK_START_18 | 0xe8     |
+| TX_PHY_CLK_START_19 | 0xec     |
+| TX_PHY_CLK_START_20 | 0xf0     |
+| TX_PHY_CLK_START_21 | 0xf4     |
+| TX_PHY_CLK_START_22 | 0xf8     |
+| TX_PHY_CLK_START_23 | 0xfc     |
+| TX_PHY_CLK_START_24 | 0x100    |
+| TX_PHY_CLK_START_25 | 0x104    |
+| TX_PHY_CLK_START_26 | 0x108    |
+| TX_PHY_CLK_START_27 | 0x10c    |
+| TX_PHY_CLK_START_28 | 0x110    |
+| TX_PHY_CLK_START_29 | 0x114    |
+| TX_PHY_CLK_START_30 | 0x118    |
+| TX_PHY_CLK_START_31 | 0x11c    |
+| TX_PHY_CLK_START_32 | 0x120    |
+| TX_PHY_CLK_START_33 | 0x124    |
+| TX_PHY_CLK_START_34 | 0x128    |
+| TX_PHY_CLK_START_35 | 0x12c    |
+| TX_PHY_CLK_START_36 | 0x130    |
+| TX_PHY_CLK_START_37 | 0x134    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_shift_start", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                             |
+|:------:|:------:|:-------:|:----------------|:----------------------------------------|
+| 31:11  |        |         |                 | Reserved                                |
+|  10:0  |   rw   |   0x2   | clk_shift_start | Positive Edge of divided, shifted clock |
+
+## TX_PHY_CLK_END
+Controls duty cycle and phase of falling edge in TX Phys
+- Reset default: `0x6`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name              | Offset   |
+|:------------------|:---------|
+| TX_PHY_CLK_END_0  | 0x138    |
+| TX_PHY_CLK_END_1  | 0x13c    |
+| TX_PHY_CLK_END_2  | 0x140    |
+| TX_PHY_CLK_END_3  | 0x144    |
+| TX_PHY_CLK_END_4  | 0x148    |
+| TX_PHY_CLK_END_5  | 0x14c    |
+| TX_PHY_CLK_END_6  | 0x150    |
+| TX_PHY_CLK_END_7  | 0x154    |
+| TX_PHY_CLK_END_8  | 0x158    |
+| TX_PHY_CLK_END_9  | 0x15c    |
+| TX_PHY_CLK_END_10 | 0x160    |
+| TX_PHY_CLK_END_11 | 0x164    |
+| TX_PHY_CLK_END_12 | 0x168    |
+| TX_PHY_CLK_END_13 | 0x16c    |
+| TX_PHY_CLK_END_14 | 0x170    |
+| TX_PHY_CLK_END_15 | 0x174    |
+| TX_PHY_CLK_END_16 | 0x178    |
+| TX_PHY_CLK_END_17 | 0x17c    |
+| TX_PHY_CLK_END_18 | 0x180    |
+| TX_PHY_CLK_END_19 | 0x184    |
+| TX_PHY_CLK_END_20 | 0x188    |
+| TX_PHY_CLK_END_21 | 0x18c    |
+| TX_PHY_CLK_END_22 | 0x190    |
+| TX_PHY_CLK_END_23 | 0x194    |
+| TX_PHY_CLK_END_24 | 0x198    |
+| TX_PHY_CLK_END_25 | 0x19c    |
+| TX_PHY_CLK_END_26 | 0x1a0    |
+| TX_PHY_CLK_END_27 | 0x1a4    |
+| TX_PHY_CLK_END_28 | 0x1a8    |
+| TX_PHY_CLK_END_29 | 0x1ac    |
+| TX_PHY_CLK_END_30 | 0x1b0    |
+| TX_PHY_CLK_END_31 | 0x1b4    |
+| TX_PHY_CLK_END_32 | 0x1b8    |
+| TX_PHY_CLK_END_33 | 0x1bc    |
+| TX_PHY_CLK_END_34 | 0x1c0    |
+| TX_PHY_CLK_END_35 | 0x1c4    |
+| TX_PHY_CLK_END_36 | 0x1c8    |
+| TX_PHY_CLK_END_37 | 0x1cc    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_shift_end", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                             |
+|:------:|:------:|:-------:|:--------------|:----------------------------------------|
+| 31:11  |        |         |               | Reserved                                |
+|  10:0  |   rw   |   0x6   | clk_shift_end | Negative Edge of divided, shifted clock |
+
+## RAW_MODE_EN
+Enables Raw mode
+- Offset: `0x1d0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_EN", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description   |
+|:------:|:------:|:-------:|:------------|:--------------|
+|  31:1  |        |         |             | Reserved      |
+|   0    |   wo   |   0x0   | RAW_MODE_EN |               |
+
+## RAW_MODE_IN_CH_SEL
+Receive channel select in RAW mode
+- Offset: `0x1d4`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_CH_SEL", "bits": 6, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:6  |        |         |                    | Reserved      |
+|  5:0   |   wo   |   0x0   | RAW_MODE_IN_CH_SEL |               |
+
+## RAW_MODE_IN_DATA_VALID_0
+Mask for valid data in RX FIFOs during RAW mode.
+- Offset: `0x1d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA_VALID_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_9", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_10", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_11", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_12", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_13", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_14", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_15", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_16", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_17", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_18", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_19", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_20", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_21", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_22", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_23", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_24", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_25", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_26", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_27", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_28", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_29", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_30", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_31", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_31 |               |
+|   30   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_30 |               |
+|   29   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_29 |               |
+|   28   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_28 |               |
+|   27   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_27 |               |
+|   26   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_26 |               |
+|   25   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_25 |               |
+|   24   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_24 |               |
+|   23   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_23 |               |
+|   22   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_22 |               |
+|   21   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_21 |               |
+|   20   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_20 |               |
+|   19   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_19 |               |
+|   18   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_18 |               |
+|   17   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_17 |               |
+|   16   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_16 |               |
+|   15   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_15 |               |
+|   14   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_14 |               |
+|   13   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_13 |               |
+|   12   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_12 |               |
+|   11   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_11 |               |
+|   10   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_10 |               |
+|   9    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_9  |               |
+|   8    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_8  |               |
+|   7    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_7  |               |
+|   6    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_6  |               |
+|   5    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_5  |               |
+|   4    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_4  |               |
+|   3    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_3  |               |
+|   2    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_2  |               |
+|   1    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_1  |               |
+|   0    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_0  |               |
+
+## RAW_MODE_IN_DATA_VALID_1
+Mask for valid data in RX FIFOs during RAW mode.
+- Offset: `0x1dc`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA_VALID_32", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_33", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_34", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_35", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_36", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_37", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_37 | For RAW_MODE_IN_DATA_VALID1 |
+|   4    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_36 | For RAW_MODE_IN_DATA_VALID1 |
+|   3    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_35 | For RAW_MODE_IN_DATA_VALID1 |
+|   2    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_34 | For RAW_MODE_IN_DATA_VALID1 |
+|   1    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_33 | For RAW_MODE_IN_DATA_VALID1 |
+|   0    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_32 | For RAW_MODE_IN_DATA_VALID1 |
+
+## RAW_MODE_IN_DATA
+Data received by the selected channel in RAW mode
+- Offset: `0x1e0`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:16  |        |         |                  | Reserved      |
+|  15:0  |   ro   |    x    | RAW_MODE_IN_DATA |               |
+
+## RAW_MODE_OUT_CH_MASK_0
+Selects channels to send out data in RAW mode, '1 corresponds to broadcasting
+- Offset: `0x1e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_CH_MASK_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_8", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_9", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_10", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_11", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_12", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_13", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_14", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_15", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_16", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_17", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_18", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_19", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_20", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_21", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_22", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_23", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_24", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_25", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_26", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_27", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_28", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_29", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_30", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_31", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|   31   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_31 |               |
+|   30   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_30 |               |
+|   29   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_29 |               |
+|   28   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_28 |               |
+|   27   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_27 |               |
+|   26   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_26 |               |
+|   25   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_25 |               |
+|   24   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_24 |               |
+|   23   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_23 |               |
+|   22   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_22 |               |
+|   21   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_21 |               |
+|   20   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_20 |               |
+|   19   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_19 |               |
+|   18   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_18 |               |
+|   17   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_17 |               |
+|   16   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_16 |               |
+|   15   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_15 |               |
+|   14   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_14 |               |
+|   13   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_13 |               |
+|   12   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_12 |               |
+|   11   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_11 |               |
+|   10   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_10 |               |
+|   9    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_9  |               |
+|   8    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_8  |               |
+|   7    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_7  |               |
+|   6    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_6  |               |
+|   5    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_5  |               |
+|   4    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_4  |               |
+|   3    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_3  |               |
+|   2    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_2  |               |
+|   1    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_1  |               |
+|   0    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_0  |               |
+
+## RAW_MODE_OUT_CH_MASK_1
+Selects channels to send out data in RAW mode, '1 corresponds to broadcasting
+- Offset: `0x1e8`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_CH_MASK_32", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_33", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_34", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_35", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_36", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_37", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description               |
+|:------:|:------:|:-------:|:------------------------|:--------------------------|
+|  31:6  |        |         |                         | Reserved                  |
+|   5    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_37 | For RAW_MODE_OUT_CH_MASK1 |
+|   4    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_36 | For RAW_MODE_OUT_CH_MASK1 |
+|   3    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_35 | For RAW_MODE_OUT_CH_MASK1 |
+|   2    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_34 | For RAW_MODE_OUT_CH_MASK1 |
+|   1    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_33 | For RAW_MODE_OUT_CH_MASK1 |
+|   0    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_32 | For RAW_MODE_OUT_CH_MASK1 |
+
+## RAW_MODE_OUT_DATA_FIFO
+Data that will be pushed to the RAW mode output FIFO
+- Offset: `0x1ec`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_DATA_FIFO", "bits": 16, "attr": ["wo"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:16  |        |         |                        | Reserved      |
+|  15:0  |   wo   |   0x0   | RAW_MODE_OUT_DATA_FIFO |               |
+
+## RAW_MODE_OUT_DATA_FIFO_CTRL
+Status and control register for the RAW mode data out FIFO
+- Offset: `0x1f0`
+- Reset default: `0x0`
+- Reset mask: `0x80000701`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 7}, {"name": "fill_state", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 20}, {"name": "is_full", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                                       |
+|:------:|:------:|:-------:|:-----------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   ro   |   0x0   | is_full    | If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again. |
+| 30:11  |        |         |            | Reserved                                                                                                                                                          |
+|  10:8  |   ro   |   0x0   | fill_state | The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.                                                                        |
+|  7:1   |        |         |            | Reserved                                                                                                                                                          |
+|   0    |   wo   |    x    | clear      | Clears the raw mode TX FIFO.                                                                                                                                      |
+
+## RAW_MODE_OUT_EN
+Enable transmission of data currently hold in the output FIFO
+- Offset: `0x1f4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description   |
+|:------:|:------:|:-------:|:----------------|:--------------|
+|  31:1  |        |         |                 | Reserved      |
+|   0    |   rw   |   0x0   | RAW_MODE_OUT_EN |               |
+
+## FLOW_CONTROL_FIFO_CLEAR
+Clears the flow control Fifo
+- Offset: `0x1f8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FLOW_CONTROL_FIFO_CLEAR", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   wo   |   0x0   | FLOW_CONTROL_FIFO_CLEAR |               |
+
+## CHANNEL_ALLOC_TX_CFG
+Configuration settings for the TX side in the channel allocator
+- Offset: `0x1fc`
+- Reset default: `0x203`
+- Reset mask: `0xff03`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypass_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auto_flush_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "auto_flush_count", "bits": 8, "attr": ["rw"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                  |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------|
+| 31:16  |        |         |                  | Reserved                                                                                     |
+|  15:8  |   rw   |   0x2   | auto_flush_count | The number of cycles to wait before auto flushing (sending) packets in the channel allocator |
+|  7:2   |        |         |                  | Reserved                                                                                     |
+|   1    |   rw   |   0x1   | auto_flush_en    | Enable the auto-flush feature of the TX side in the channel allocator                        |
+|   0    |   rw   |   0x1   | bypass_en        | Enable bypassing the TX channel allocator                                                    |
+
+## CHANNEL_ALLOC_TX_CH_EN_0
+Channel enable mask for the TX side.
+- Offset: `0x200`
+- Reset default: `0xffffffff`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_TX_CH_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_31 |               |
+|   30   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_30 |               |
+|   29   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_29 |               |
+|   28   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_28 |               |
+|   27   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_27 |               |
+|   26   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_26 |               |
+|   25   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_25 |               |
+|   24   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_24 |               |
+|   23   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_23 |               |
+|   22   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_22 |               |
+|   21   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_21 |               |
+|   20   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_20 |               |
+|   19   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_19 |               |
+|   18   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_18 |               |
+|   17   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_17 |               |
+|   16   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_16 |               |
+|   15   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_15 |               |
+|   14   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_14 |               |
+|   13   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_13 |               |
+|   12   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_12 |               |
+|   11   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_11 |               |
+|   10   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_10 |               |
+|   9    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_9  |               |
+|   8    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_8  |               |
+|   7    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_7  |               |
+|   6    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_6  |               |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_5  |               |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_4  |               |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_3  |               |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_2  |               |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_1  |               |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_0  |               |
+
+## CHANNEL_ALLOC_TX_CH_EN_1
+Channel enable mask for the TX side.
+- Offset: `0x204`
+- Reset default: `0x3f`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_TX_CH_EN_32", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_33", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_34", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_35", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_36", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_37", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_37 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_36 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_35 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_34 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_33 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_32 | For CHANNEL_ALLOC_TX_CH_EN1 |
+
+## CHANNEL_ALLOC_TX_CTRL
+Soft clear or force flush the TX side of the channel allocator
+- Offset: `0x208`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "flush", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------|
+|  31:2  |        |         |        | Reserved                                                                 |
+|   1    |   wo   |    x    | flush  | Flush (transmit remaining data) in the TX side of the channel allocator. |
+|   0    |   wo   |    x    | clear  | Software clear the TX side of the channel allocator                      |
+
+## CHANNEL_ALLOC_RX_CFG
+Configuration settings for the RX side in the channel allocator
+- Offset: `0x20c`
+- Reset default: `0x10203`
+- Reset mask: `0x1ff03`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypass_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auto_flush_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "auto_flush_count", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "sync_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                                    |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------------|
+| 31:17  |        |         |                  | Reserved                                                                                                       |
+|   16   |   rw   |   0x1   | sync_en          | Enable (1) or disable (0) the synchronization barrier between the channels (needs to be disabled in raw mode). |
+|  15:8  |   rw   |   0x2   | auto_flush_count | The number of cycles to wait before synchronizing on partial packets on the RX side                            |
+|  7:2   |        |         |                  | Reserved                                                                                                       |
+|   1    |   rw   |   0x1   | auto_flush_en    | Enable the auto-flush feature of the RX side in the channel allocator                                          |
+|   0    |   rw   |   0x1   | bypass_en        | Enable bypassing the RX channel allocator                                                                      |
+
+## CHANNEL_ALLOC_RX_CTRL
+Soft clear the RX side of the channel allocator
+- Offset: `0x210`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                            |
+|   0    |   wo   |    x    | clear  | Software clear the TX side of the channel allocator |
+
+## CHANNEL_ALLOC_RX_CH_EN_0
+Channel enable mask for the RX side.
+- Offset: `0x214`
+- Reset default: `0xffffffff`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_RX_CH_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_31 |               |
+|   30   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_30 |               |
+|   29   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_29 |               |
+|   28   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_28 |               |
+|   27   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_27 |               |
+|   26   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_26 |               |
+|   25   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_25 |               |
+|   24   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_24 |               |
+|   23   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_23 |               |
+|   22   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_22 |               |
+|   21   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_21 |               |
+|   20   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_20 |               |
+|   19   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_19 |               |
+|   18   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_18 |               |
+|   17   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_17 |               |
+|   16   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_16 |               |
+|   15   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_15 |               |
+|   14   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_14 |               |
+|   13   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_13 |               |
+|   12   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_12 |               |
+|   11   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_11 |               |
+|   10   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_10 |               |
+|   9    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_9  |               |
+|   8    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_8  |               |
+|   7    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_7  |               |
+|   6    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_6  |               |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_5  |               |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_4  |               |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_3  |               |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_2  |               |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_1  |               |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_0  |               |
+
+## CHANNEL_ALLOC_RX_CH_EN_1
+Channel enable mask for the RX side.
+- Offset: `0x218`
+- Reset default: `0x3f`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_RX_CH_EN_32", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_33", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_34", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_35", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_36", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_37", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_37 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_36 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_35 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_34 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_33 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_32 | For CHANNEL_ALLOC_RX_CH_EN1 |
+
+
+
+
+
+## spim
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                     | Offset   |   Length | Description                                              |
+|:-----------------------------------------|:---------|---------:|:---------------------------------------------------------|
+| spi_host.[`INTR_STATE`](#intr_state)     | 0x0      |        4 | Interrupt State Register                                 |
+| spi_host.[`INTR_ENABLE`](#intr_enable)   | 0x4      |        4 | Interrupt Enable Register                                |
+| spi_host.[`INTR_TEST`](#intr_test)       | 0x8      |        4 | Interrupt Test Register                                  |
+| spi_host.[`ALERT_TEST`](#alert_test)     | 0xc      |        4 | Alert Test Register                                      |
+| spi_host.[`CONTROL`](#control)           | 0x10     |        4 | Control register                                         |
+| spi_host.[`STATUS`](#status)             | 0x14     |        4 | Status register                                          |
+| spi_host.[`CONFIGOPTS`](#configopts)     | 0x18     |        4 | Configuration options register.                          |
+| spi_host.[`CSID`](#csid)                 | 0x1c     |        4 | Chip-Select ID                                           |
+| spi_host.[`COMMAND`](#command)           | 0x20     |        4 | Command Register                                         |
+| spi_host.[`RXDATA`](#rxdata)             | 0x24     |        4 | SPI Receive Data.                                        |
+| spi_host.[`TXDATA`](#txdata)             | 0x28     |        4 | SPI Transmit Data.                                       |
+| spi_host.[`ERROR_ENABLE`](#error_enable) | 0x2c     |        4 | Controls which classes of errors raise an interrupt.     |
+| spi_host.[`ERROR_STATUS`](#error_status) | 0x30     |        4 | Indicates that any errors that have occurred.            |
+| spi_host.[`EVENT_ENABLE`](#event_enable) | 0x34     |        4 | Controls which classes of SPI events raise an interrupt. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                  |
+|:------:|:------:|:-------:|:----------|:---------------------------------------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                                                     |
+|   1    |   ro   |   0x0   | spi_event | Event-related interrupts, see [`EVENT_ENABLE`](#event_enable) register for more information. |
+|   0    |  rw1c  |   0x0   | error     | Error-related interrupts, see [`ERROR_ENABLE`](#error_enable) register for more information. |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                         |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                            |
+|   1    |   rw   |   0x0   | spi_event | Enable interrupt when [`INTR_STATE.spi_event`](#intr_state) is set. |
+|   0    |   rw   |   0x0   | error     | Enable interrupt when [`INTR_STATE.error`](#intr_state) is set.     |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                     |
+|   1    |   wo   |   0x0   | spi_event | Write 1 to force [`INTR_STATE.spi_event`](#intr_state) to 1. |
+|   0    |   wo   |   0x0   | error     | Write 1 to force [`INTR_STATE.error`](#intr_state) to 1.     |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CONTROL
+Control register
+- Offset: `0x10`
+- Reset default: `0x7f`
+- Reset mask: `0xe000ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX_WATERMARK", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TX_WATERMARK", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 13}, {"name": "OUTPUT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SW_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SPIEN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                   |
+|:------:|:------:|:-------:|:---------------------------------------|
+|   31   |   rw   |   0x0   | [SPIEN](#control--spien)               |
+|   30   |   rw   |   0x0   | [SW_RST](#control--sw_rst)             |
+|   29   |   rw   |   0x0   | [OUTPUT_EN](#control--output_en)       |
+| 28:16  |        |         | Reserved                               |
+|  15:8  |   rw   |   0x0   | [TX_WATERMARK](#control--tx_watermark) |
+|  7:0   |   rw   |  0x7f   | [RX_WATERMARK](#control--rx_watermark) |
+
+### CONTROL . SPIEN
+Enables the SPI host.  On reset, this field is 0, meaning
+   that no transactions can proceed.
+
+### CONTROL . SW_RST
+Clears the internal state (not registers) to the reset state when set to 1,
+   including the FIFOs, the CDC's, the core state machine and the shift register.
+   In the current implementation, the CDC FIFOs are drained not reset.
+   Therefore software must confirm that both FIFO's empty before releasing
+   the IP from reset.
+
+### CONTROL . OUTPUT_EN
+Enable the SPI host output buffers for the sck, csb, and sd lines.  This allows
+   the SPI_HOST IP to connect to the same bus as other SPI controllers without
+   interference.
+
+### CONTROL . TX_WATERMARK
+If [`EVENT_ENABLE.TXWM`](#event_enable) is set, the IP will send
+   an interrupt when the depth of the TX FIFO drops below
+   TX_WATERMARK words (32b each).
+
+### CONTROL . RX_WATERMARK
+If [`EVENT_ENABLE.RXWM`](#event_enable) is set, the IP will send
+   an interrupt when the depth of the RX FIFO reaches
+   RX_WATERMARK words (32b each).
+
+## STATUS
+Status register
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffdfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXQD", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "RXQD", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CMDQD", "bits": 4, "attr": ["ro"], "rotate": 0}, {"name": "RXWM", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "BYTEORDER", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXSTALL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXWM", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXSTALL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACTIVE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "READY", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                               |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   ro   |   0x0   | READY     | When high, indicates the SPI host is ready to receive commands. Writing to COMMAND when READY is low is an error, and will trigger an interrupt.                          |
+|   30   |   ro   |   0x0   | ACTIVE    | When high, indicates the SPI host is processing a previously issued command.                                                                                              |
+|   29   |   ro   |   0x0   | TXFULL    | When high, indicates that the transmit data fifo is full. Any further writes to [`TXDATA`](#txdata) will create an error interrupt.                                       |
+|   28   |   ro   |   0x0   | TXEMPTY   | When high, indicates that the transmit data fifo is empty.                                                                                                                |
+|   27   |   ro   |   0x0   | TXSTALL   | If high, signifies that an ongoing transaction has stalled due to lack of data in the TX FIFO                                                                             |
+|   26   |   ro   |   0x0   | TXWM      | If high, the amount of data in the TX FIFO has fallen below the level of [`CONTROL.TX_WATERMARK`](#control) words (32b each).                                             |
+|   25   |   ro   |   0x0   | RXFULL    | When high, indicates that the receive fifo is full.  Any ongoing transactions will stall until firmware reads some data from [`RXDATA.`](#rxdata)                         |
+|   24   |   ro   |   0x0   | RXEMPTY   | When high, indicates that the receive fifo is empty. Any reads from RX FIFO will cause an error interrupt.                                                                |
+|   23   |   ro   |   0x0   | RXSTALL   | If high, signifies that an ongoing transaction has stalled due to lack of available space in the RX FIFO                                                                  |
+|   22   |   ro   |   0x0   | BYTEORDER | The value of the ByteOrder parameter, provided so that firmware can confirm proper IP configuration.                                                                      |
+|   21   |        |         |           | Reserved                                                                                                                                                                  |
+|   20   |   ro   |   0x0   | RXWM      | If high, the number of 32-bits in the RX FIFO now exceeds the [`CONTROL.RX_WATERMARK`](#control) entries (32b each).                                                      |
+| 19:16  |   ro   |   0x0   | CMDQD     | Command queue depth. Indicates how many unread 32-bit words are currently in the command segment queue.                                                                   |
+|  15:8  |   ro   |   0x0   | RXQD      | Receive queue depth. Indicates how many unread 32-bit words are currently in the RX FIFO.  When active, this result may an underestimate due to synchronization delays.   |
+|  7:0   |   ro   |   0x0   | TXQD      | Transmit queue depth. Indicates how many unsent 32-bit words are currently in the TX FIFO. When active, this result may be an overestimate due to synchronization delays. |
+
+## CONFIGOPTS
+Configuration options register.
+
+   Contains options for controlling the current peripheral.
+   Firmware needs to configure the options before the transfer.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xefffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CLKDIV", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "CSNIDLE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "CSNTRAIL", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "CSNLEAD", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "FULLCYC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CPHA", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CPOL", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                              |
+|:------:|:------:|:-------:|:----------------------------------|
+|   31   |   rw   |   0x0   | [CPOL](#configopts--cpol)         |
+|   30   |   rw   |   0x0   | [CPHA](#configopts--cpha)         |
+|   29   |   rw   |   0x0   | [FULLCYC](#configopts--fullcyc)   |
+|   28   |        |         | Reserved                          |
+| 27:24  |   rw   |   0x0   | [CSNLEAD](#configopts--csnlead)   |
+| 23:20  |   rw   |   0x0   | [CSNTRAIL](#configopts--csntrail) |
+| 19:16  |   rw   |   0x0   | [CSNIDLE](#configopts--csnidle)   |
+|  15:0  |   rw   |   0x0   | [CLKDIV](#configopts--clkdiv)     |
+
+### CONFIGOPTS . CPOL
+The polarity of the sck clock signal.  When CPOL is 0,
+    sck is low when idle, and emits high pulses.   When CPOL
+    is 1, sck is high when idle, and emits a series of low
+    pulses.
+
+### CONFIGOPTS . CPHA
+The phase of the sck clock signal relative to the data. When
+    CPHA = 0, the data changes on the trailing edge of sck
+    and is typically sampled on the leading edge.  Conversely
+    if CPHA = 1 high, data lines change on the leading edge of
+    sck and are typically sampled on the trailing edge.
+    CPHA should be chosen to match the phase of the selected
+    device.  The sampling behavior is modified by the
+    [`CONFIGOPTS.FULLCYC`](#configopts) bit.
+
+### CONFIGOPTS . FULLCYC
+Full cycle.  Modifies the CPHA sampling behaviour to allow
+    for longer device logic setup times.  Rather than sampling the SD
+    bus a half cycle after shifting out data, the data is sampled
+    a full cycle after shifting data out.  This means that if
+    CPHA = 0, data is shifted out on the trailing edge, and
+    sampled a full cycle later.  If CPHA = 1, data is shifted and
+    sampled with the trailing edge, also separated by a
+    full cycle.
+
+### CONFIGOPTS . CSNLEAD
+CS_N Leading Time.  Indicates the number of half sck cycles,
+    CSNLEAD+1, to leave between the falling edge of cs_n and
+    the first edge of sck.  Setting this register to zero
+    corresponds to the minimum delay of one-half sck cycle
+
+### CONFIGOPTS . CSNTRAIL
+CS_N Trailing Time.  Indicates the number of half sck cycles,
+    CSNTRAIL+1, to leave between last edge of sck and the rising
+    edge of cs_n. Setting this register to zero corresponds
+    to the minimum delay of one-half sck cycle.
+
+### CONFIGOPTS . CSNIDLE
+Minimum idle time between commands. Indicates the minimum
+    number of sck half-cycles to hold cs_n high between commands.
+    Setting this register to zero creates a minimally-wide CS_N-high
+    pulse of one-half sck cycle.
+
+### CONFIGOPTS . CLKDIV
+Core clock divider.  Slows down subsequent SPI transactions by a
+    factor of (CLKDIV+1) relative to the core clock frequency.  The
+    period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`
+
+## CSID
+Chip-Select ID
+
+   Controls which device to target with the next command.  This register
+   is passed to the core whenever [`COMMAND`](#command) is written.  The core then
+   asserts cio_csb_o[[`CSID`](#csid)] during the execution of the command.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CSID", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description    |
+|:------:|:------:|:-------:|:-------|:---------------|
+|  31:0  |   rw   |   0x0   | CSID   | Chip Select ID |
+
+## COMMAND
+Command Register
+
+   Parameters specific to each command segment.  Unlike the [`CONFIGOPTS`](#configopts) multi-register,
+   there is only one command register for controlling all attached SPI devices
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1ffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CSAAT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "SPEED", "bits": 2, "attr": ["wo"], "rotate": -90}, {"name": "DIRECTION", "bits": 2, "attr": ["wo"], "rotate": -90}, {"name": "LEN", "bits": 20, "attr": ["wo"], "rotate": 0}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                             |
+|:------:|:------:|:-------:|:---------------------------------|
+| 31:25  |        |         | Reserved                         |
+|  24:5  |   wo   |   0x0   | [LEN](#command--len)             |
+|  4:3   |   wo   |   0x0   | [DIRECTION](#command--direction) |
+|  2:1   |   wo   |   0x0   | [SPEED](#command--speed)         |
+|   0    |   wo   |   0x0   | [CSAAT](#command--csaat)         |
+
+### COMMAND . LEN
+Segment Length.
+
+   For read or write segments, this field controls the
+   number of 1-byte bursts to transmit and or receive in
+   this command segment.  The number of cyles required
+   to send or received a byte will depend on [`COMMAND.SPEED.`](#command)
+   For dummy segments, ([`COMMAND.DIRECTION`](#command) == 0), this register
+   controls the number of dummy cycles to issue.
+   The number of bytes (or dummy cycles) in the segment will be
+   equal to [`COMMAND.LEN`](#command) + 1.
+
+### COMMAND . DIRECTION
+The direction for the following command: "0" = Dummy cycles
+   (no TX/RX). "1" = Rx only, "2" = Tx only, "3" = Bidirectional
+   Tx/Rx (Standard SPI mode only).
+
+### COMMAND . SPEED
+The speed for this command segment: "0" = Standard SPI. "1" = Dual SPI.
+   "2"=Quad SPI,  "3": RESERVED.
+
+### COMMAND . CSAAT
+**C**hip **S**elect **A**ctive **A**fter **T**ransaction.
+   If [`COMMAND.CSAAT`](#command) = 0, the chip select line is raised immediately
+   at the end of the command segment.
+   If [`COMMAND.CSAAT`](#command) = 1, the chip select line is left low at the
+   end of the current transaction segment.
+   This allows the creation of longer, more complete SPI transactions,
+   consisting of several separate segments for issuing instructions,
+   pausing for dummy cycles, and transmitting or receiving data from
+   the device.
+
+## RXDATA
+SPI Receive Data.
+
+   Reads from this window pull data from the RXFIFO.
+
+   The serial order of bit transmission
+   is chosen to match SPI flash devices. Individual bytes
+   are always transmitted with the most significant bit first.
+   Only four-byte reads are supported. If ByteOrder = 0,
+   the first byte received is packed in the MSB of !!RXDATA.
+   For some processor architectures, this could lead to shuffling
+   of flash data as compared to how it is written in memory.
+   In which case, choosing ByteOrder = 1 can reverse the
+   byte-order of each data read, causing the first byte
+   received to be packed into the LSB of !!RXDATA. (Though within
+   each byte the most significant bit is always pulled
+   from the bus first.)
+
+- Word Aligned Offset Range: `0x24`to`0x24`
+- Size (words): `1`
+- Access: `ro`
+- Byte writes are *not* supported.
+
+## TXDATA
+SPI Transmit Data.
+
+   Data written to this window is placed into the TXFIFO.
+   Byte-enables are supported for writes.
+
+   The serial order of bit transmission
+   is chosen to match SPI flash devices. Individual bytes
+   are always transmitted with the most significant bit first.
+   Multi-byte writes are also supported, and if ByteOrder = 0,
+   the bits of !!TXDATA are transmitted strictly in order of
+   decreasing signficance (i.e. most signicant bit first).
+   For some processor architectures, this could lead to shuffling
+   of flash data as compared to how it is written in memory.
+   In which case, choosing ByteOrder = 1 can reverse the
+   byte-order of multi-byte data writes.  (Though within
+   each byte the most significant bit is always sent first.)
+
+- Word Aligned Offset Range: `0x28`to`0x28`
+- Size (words): `1`
+- Access: `wo`
+- Byte writes are  supported.
+
+## ERROR_ENABLE
+Controls which classes of errors raise an interrupt.
+- Offset: `0x2c`
+- Reset default: `0x1f`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CMDBUSY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "OVERFLOW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UNDERFLOW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CMDINVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CSIDINVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                                                       |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:5  |        |         |           | Reserved                                                                                                                                                                                          |
+|   4    |   rw   |   0x1   | CSIDINVAL | Invalid CSID: If this bit is set, the block sends an error interrupt whenever a command is submitted, but CSID exceeds NumCS.                                                                     |
+|   3    |   rw   |   0x1   | CMDINVAL  | Invalid Command Errors: If this bit is set, the block sends an error interrupt whenever a command is sent with invalid values for [`COMMAND.SPEED`](#command) or [`COMMAND.DIRECTION.`](#command) |
+|   2    |   rw   |   0x1   | UNDERFLOW | Underflow Errors: If this bit is set, the block sends an error interrupt whenever there is a read from [`RXDATA`](#rxdata) but the RX FIFO is empty.                                              |
+|   1    |   rw   |   0x1   | OVERFLOW  | Overflow Errors: If this bit is set, the block sends an error interrupt whenever the TX FIFO overflows.                                                                                           |
+|   0    |   rw   |   0x1   | CMDBUSY   | Command Error: If this bit is set, the block sends an error interrupt whenever a command is issued while busy (i.e. a 1 is when [`STATUS.READY`](#status) is not asserted.)                       |
+
+## ERROR_STATUS
+Indicates that any errors that have occurred.
+   When an error
+   occurs, the corresponding bit must be cleared here before
+   issuing any further commands.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CMDBUSY", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "OVERFLOW", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNDERFLOW", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CMDINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CSIDINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ACCESSINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                                                                                                                                             |
+|:------:|:------:|:-------:|:------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:6  |        |         |             | Reserved                                                                                                                                                                |
+|   5    |  rw1c  |   0x0   | ACCESSINVAL | Indicates that TLUL attempted to write to TXDATA with no bytes enabled. Such 'zero byte' writes are not supported.                                                      |
+|   4    |  rw1c  |   0x0   | CSIDINVAL   | Indicates a command was attempted with an invalid value for [`CSID.`](#csid)                                                                                            |
+|   3    |  rw1c  |   0x0   | CMDINVAL    | Indicates an invalid command segment, meaning either an invalid value of [`COMMAND.SPEED`](#command) or a request for bidirectional data transfer at dual or quad speed |
+|   2    |  rw1c  |   0x0   | UNDERFLOW   | Indicates that firmware has attempted to read from [`RXDATA`](#rxdata) when the RX FIFO is empty.                                                                       |
+|   1    |  rw1c  |   0x0   | OVERFLOW    | Indicates that firmware has overflowed the TX FIFO                                                                                                                      |
+|   0    |  rw1c  |   0x0   | CMDBUSY     | Indicates a write to [`COMMAND`](#command) when [`STATUS.READY`](#status) = 0.                                                                                          |
+
+## EVENT_ENABLE
+Controls which classes of SPI events raise an interrupt.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXFULL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RXWM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXWM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "READY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IDLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                              |
+|:------:|:------:|:-------:|:----------------------------------|
+|  31:6  |        |         | Reserved                          |
+|   5    |   rw   |   0x0   | [IDLE](#event_enable--idle)       |
+|   4    |   rw   |   0x0   | [READY](#event_enable--ready)     |
+|   3    |   rw   |   0x0   | [TXWM](#event_enable--txwm)       |
+|   2    |   rw   |   0x0   | [RXWM](#event_enable--rxwm)       |
+|   1    |   rw   |   0x0   | [TXEMPTY](#event_enable--txempty) |
+|   0    |   rw   |   0x0   | [RXFULL](#event_enable--rxfull)   |
+
+### EVENT_ENABLE . IDLE
+Assert to send a spi_event interrupt whenever [`STATUS.ACTIVE`](#status)
+   goes low
+
+### EVENT_ENABLE . READY
+Assert to send a spi_event interrupt whenever [`STATUS.READY`](#status)
+   goes high
+
+### EVENT_ENABLE . TXWM
+Assert to send a spi_event interrupt whenever the number of 32-bit words in
+   the TX FIFO is less than [`CONTROL.TX_WATERMARK.`](#control)  To prevent the
+   reassertion of this interrupt add more data to the TX FIFO, or
+   reduce [`CONTROL.TX_WATERMARK.`](#control)
+
+### EVENT_ENABLE . RXWM
+Assert to send a spi_event interrupt whenever the number of 32-bit words in
+   the RX FIFO is greater than [`CONTROL.RX_WATERMARK.`](#control) To prevent the
+   reassertion of this interrupt, read more data from the RX FIFO, or
+   increase [`CONTROL.RX_WATERMARK.`](#control)
+
+### EVENT_ENABLE . TXEMPTY
+Assert to send a spi_event interrupt whenever [`STATUS.TXEMPTY`](#status)
+   goes high
+
+### EVENT_ENABLE . RXFULL
+Assert to send a spi_event interrupt whenever [`STATUS.RXFULL`](#status)
+   goes high
+
+
+
+
+
+## tagger
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                   | Offset   |   Length | Description                             |
+|:---------------------------------------|:---------|---------:|:----------------------------------------|
+| tagger_reg.[`PAT_COMMIT`](#PAT_COMMIT) | 0x0      |        4 | Partition configuration commit register |
+| tagger_reg.[`PAT_ADDR_0`](#pat_addr)   | 0x4      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_1`](#pat_addr)   | 0x8      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_2`](#pat_addr)   | 0xc      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_3`](#pat_addr)   | 0x10     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_4`](#pat_addr)   | 0x14     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_5`](#pat_addr)   | 0x18     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_6`](#pat_addr)   | 0x1c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_7`](#pat_addr)   | 0x20     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_8`](#pat_addr)   | 0x24     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_9`](#pat_addr)   | 0x28     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_10`](#pat_addr)  | 0x2c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_11`](#pat_addr)  | 0x30     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_12`](#pat_addr)  | 0x34     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_13`](#pat_addr)  | 0x38     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_14`](#pat_addr)  | 0x3c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_15`](#pat_addr)  | 0x40     |        4 | Partition address                       |
+| tagger_reg.[`PATID_0`](#patid)         | 0x44     |        4 | Partition ID                            |
+| tagger_reg.[`PATID_1`](#patid)         | 0x48     |        4 | Partition ID                            |
+| tagger_reg.[`PATID_2`](#patid)         | 0x4c     |        4 | Partition ID                            |
+| tagger_reg.[`ADDR_CONF`](#addr_conf)   | 0x50     |        4 | Address encoding mode switch register   |
+
+## PAT_COMMIT
+Partition configuration commit register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "commit_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                               |
+|:------:|:------:|:-------:|:---------|:------------------------------------------|
+|  31:1  |        |         |          | Reserved                                  |
+|   0    |   rw   |   0x0   | commit_0 | commit changes of partition configuration |
+
+## PAT_ADDR
+Partition address
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name        | Offset   |
+|:------------|:---------|
+| PAT_ADDR_0  | 0x4      |
+| PAT_ADDR_1  | 0x8      |
+| PAT_ADDR_2  | 0xc      |
+| PAT_ADDR_3  | 0x10     |
+| PAT_ADDR_4  | 0x14     |
+| PAT_ADDR_5  | 0x18     |
+| PAT_ADDR_6  | 0x1c     |
+| PAT_ADDR_7  | 0x20     |
+| PAT_ADDR_8  | 0x24     |
+| PAT_ADDR_9  | 0x28     |
+| PAT_ADDR_10 | 0x2c     |
+| PAT_ADDR_11 | 0x30     |
+| PAT_ADDR_12 | 0x34     |
+| PAT_ADDR_13 | 0x38     |
+| PAT_ADDR_14 | 0x3c     |
+| PAT_ADDR_15 | 0x40     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PAT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                              |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------|
+|  31:0  |   rw   |   0x0   | PAT_ADDR | Single partition configurations: address |
+
+## PATID
+Partition ID
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name    | Offset   |
+|:--------|:---------|
+| PATID_0 | 0x44     |
+| PATID_1 | 0x48     |
+| PATID_2 | 0x4c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PATID", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                          |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | PATID  | Partition ID (PatID) for each partition, length determined by params |
+
+## ADDR_CONF
+Address encoding mode switch register
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name      | Offset   |
+|:----------|:---------|
+| ADDR_CONF | 0x50     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "addr_conf", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                 |
+|:------:|:------:|:-------:|:----------|:----------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | addr_conf | 2 bits configuration for each partition. 2'b00: OFF, 2'b01: TOR, 2'b10: NA4 |
+
+
+
+
+
+## uart
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                 | Offset   |   Length | Description                                                        |
+|:-------------------------------------|:---------|---------:|:-------------------------------------------------------------------|
+| uart.[`INTR_STATE`](#intr_state)     | 0x0      |        4 | Interrupt State Register                                           |
+| uart.[`INTR_ENABLE`](#intr_enable)   | 0x4      |        4 | Interrupt Enable Register                                          |
+| uart.[`INTR_TEST`](#intr_test)       | 0x8      |        4 | Interrupt Test Register                                            |
+| uart.[`ALERT_TEST`](#alert_test)     | 0xc      |        4 | Alert Test Register                                                |
+| uart.[`CTRL`](#ctrl)                 | 0x10     |        4 | UART control register                                              |
+| uart.[`STATUS`](#status)             | 0x14     |        4 | UART live status register                                          |
+| uart.[`RDATA`](#rdata)               | 0x18     |        4 | UART read data                                                     |
+| uart.[`WDATA`](#wdata)               | 0x1c     |        4 | UART write data                                                    |
+| uart.[`FIFO_CTRL`](#fifo_ctrl)       | 0x20     |        4 | UART FIFO control register                                         |
+| uart.[`FIFO_STATUS`](#fifo_status)   | 0x24     |        4 | UART FIFO status register                                          |
+| uart.[`OVRD`](#ovrd)                 | 0x28     |        4 | TX pin override control. Gives direct SW control over TX pin state |
+| uart.[`VAL`](#val)                   | 0x2c     |        4 | UART oversampled values                                            |
+| uart.[`TIMEOUT_CTRL`](#timeout_ctrl) | 0x30     |        4 | UART RX timeout control                                            |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x101`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                                                                    |
+|:------:|:------:|:-------:|:--------------|:---------------------------------------------------------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                                                                       |
+|   8    |   ro   |   0x1   | tx_empty      | raised if the transmit FIFO is empty.                                                                          |
+|   7    |  rw1c  |   0x0   | rx_parity_err | raised if the receiver has detected a parity error.                                                            |
+|   6    |  rw1c  |   0x0   | rx_timeout    | raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period. |
+|   5    |  rw1c  |   0x0   | rx_break_err  | raised if break condition has been detected on receive.                                                        |
+|   4    |  rw1c  |   0x0   | rx_frame_err  | raised if a framing error has been detected on receive.                                                        |
+|   3    |  rw1c  |   0x0   | rx_overflow   | raised if the receive FIFO has overflowed.                                                                     |
+|   2    |  rw1c  |   0x0   | tx_done       | raised if the transmit FIFO has emptied and no transmit is ongoing.                                            |
+|   1    |   ro   |   0x0   | rx_watermark  | raised if the receive FIFO is past the high-water mark.                                                        |
+|   0    |   ro   |   0x1   | tx_watermark  | raised if the transmit FIFO is past the high-water mark.                                                       |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                             |
+|:------:|:------:|:-------:|:--------------|:------------------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                                |
+|   8    |   rw   |   0x0   | tx_empty      | Enable interrupt when [`INTR_STATE.tx_empty`](#intr_state) is set.      |
+|   7    |   rw   |   0x0   | rx_parity_err | Enable interrupt when [`INTR_STATE.rx_parity_err`](#intr_state) is set. |
+|   6    |   rw   |   0x0   | rx_timeout    | Enable interrupt when [`INTR_STATE.rx_timeout`](#intr_state) is set.    |
+|   5    |   rw   |   0x0   | rx_break_err  | Enable interrupt when [`INTR_STATE.rx_break_err`](#intr_state) is set.  |
+|   4    |   rw   |   0x0   | rx_frame_err  | Enable interrupt when [`INTR_STATE.rx_frame_err`](#intr_state) is set.  |
+|   3    |   rw   |   0x0   | rx_overflow   | Enable interrupt when [`INTR_STATE.rx_overflow`](#intr_state) is set.   |
+|   2    |   rw   |   0x0   | tx_done       | Enable interrupt when [`INTR_STATE.tx_done`](#intr_state) is set.       |
+|   1    |   rw   |   0x0   | rx_watermark  | Enable interrupt when [`INTR_STATE.rx_watermark`](#intr_state) is set.  |
+|   0    |   rw   |   0x0   | tx_watermark  | Enable interrupt when [`INTR_STATE.tx_watermark`](#intr_state) is set.  |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                      |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                         |
+|   8    |   wo   |   0x0   | tx_empty      | Write 1 to force [`INTR_STATE.tx_empty`](#intr_state) to 1.      |
+|   7    |   wo   |   0x0   | rx_parity_err | Write 1 to force [`INTR_STATE.rx_parity_err`](#intr_state) to 1. |
+|   6    |   wo   |   0x0   | rx_timeout    | Write 1 to force [`INTR_STATE.rx_timeout`](#intr_state) to 1.    |
+|   5    |   wo   |   0x0   | rx_break_err  | Write 1 to force [`INTR_STATE.rx_break_err`](#intr_state) to 1.  |
+|   4    |   wo   |   0x0   | rx_frame_err  | Write 1 to force [`INTR_STATE.rx_frame_err`](#intr_state) to 1.  |
+|   3    |   wo   |   0x0   | rx_overflow   | Write 1 to force [`INTR_STATE.rx_overflow`](#intr_state) to 1.   |
+|   2    |   wo   |   0x0   | tx_done       | Write 1 to force [`INTR_STATE.tx_done`](#intr_state) to 1.       |
+|   1    |   wo   |   0x0   | rx_watermark  | Write 1 to force [`INTR_STATE.rx_watermark`](#intr_state) to 1.  |
+|   0    |   wo   |   0x0   | tx_watermark  | Write 1 to force [`INTR_STATE.tx_watermark`](#intr_state) to 1.  |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CTRL
+UART control register
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffff03f7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NF", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "SLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_ODD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RXBLVL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "NCO", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                            |
+|:------:|:------:|:-------:|:--------------------------------|
+| 31:16  |   rw   |   0x0   | [NCO](#ctrl--nco)               |
+| 15:10  |        |         | Reserved                        |
+|  9:8   |   rw   |   0x0   | [RXBLVL](#ctrl--rxblvl)         |
+|   7    |   rw   |   0x0   | [PARITY_ODD](#ctrl--parity_odd) |
+|   6    |   rw   |   0x0   | [PARITY_EN](#ctrl--parity_en)   |
+|   5    |   rw   |   0x0   | [LLPBK](#ctrl--llpbk)           |
+|   4    |   rw   |   0x0   | [SLPBK](#ctrl--slpbk)           |
+|   3    |        |         | Reserved                        |
+|   2    |   rw   |   0x0   | [NF](#ctrl--nf)                 |
+|   1    |   rw   |   0x0   | [RX](#ctrl--rx)                 |
+|   0    |   rw   |   0x0   | [TX](#ctrl--tx)                 |
+
+### CTRL . NCO
+BAUD clock rate control.
+
+### CTRL . RXBLVL
+Trigger level for RX break detection. Sets the number of character
+times the line must be low to detect a break.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | break2  | 2 characters  |
+| 0x1     | break4  | 4 characters  |
+| 0x2     | break8  | 8 characters  |
+| 0x3     | break16 | 16 characters |
+
+
+### CTRL . PARITY_ODD
+If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even.
+
+### CTRL . PARITY_EN
+If true, parity is enabled in both RX and TX directions.
+
+### CTRL . LLPBK
+Line loopback enable.
+
+If this bit is turned on, incoming bits are forwarded to TX for testing purpose.
+See Block Diagram. Note that the internal design sees RX value as 1 always if line
+loopback is enabled.
+
+### CTRL . SLPBK
+System loopback enable.
+
+If this bit is turned on, any outgoing bits to TX are received through RX.
+See Block Diagram. Note that the TX line goes 1 if System loopback is enabled.
+
+### CTRL . NF
+RX noise filter enable.
+If the noise filter is enabled, RX line goes through the 3-tap
+repetition code. It ignores single IP clock period noise.
+
+### CTRL . RX
+RX enable
+
+### CTRL . TX
+TX enable
+
+## STATUS
+UART live status register
+- Offset: `0x14`
+- Reset default: `0x3c`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                         |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------|
+|  31:6  |        |         |         | Reserved                                            |
+|   5    |   ro   |   0x1   | RXEMPTY | RX FIFO is empty                                    |
+|   4    |   ro   |   0x1   | RXIDLE  | RX is idle                                          |
+|   3    |   ro   |   0x1   | TXIDLE  | TX FIFO is empty and all bits have been transmitted |
+|   2    |   ro   |   0x1   | TXEMPTY | TX FIFO is empty                                    |
+|   1    |   ro   |    x    | RXFULL  | RX buffer is full                                   |
+|   0    |   ro   |    x    | TXFULL  | TX buffer is full                                   |
+
+## RDATA
+UART read data
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   ro   |    x    | RDATA  |               |
+
+## WDATA
+UART write data
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "WDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   wo   |   0x0   | WDATA  |               |
+
+## FIFO_CTRL
+UART FIFO control register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "TXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         |
+|:------:|:------:|:-------:|:-----------------------------|
+|  31:8  |        |         | Reserved                     |
+|  7:5   |   rw   |   0x0   | [TXILVL](#fifo_ctrl--txilvl) |
+|  4:2   |   rw   |   0x0   | [RXILVL](#fifo_ctrl--rxilvl) |
+|   1    |   wo   |   0x0   | [TXRST](#fifo_ctrl--txrst)   |
+|   0    |   wo   |   0x0   | [RXRST](#fifo_ctrl--rxrst)   |
+
+### FIFO_CTRL . TXILVL
+Trigger level for TX interrupts. If the FIFO depth is less than the setting, it
+raises tx_watermark interrupt.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | txlvl1  | 1 character   |
+| 0x1     | txlvl2  | 2 characters  |
+| 0x2     | txlvl4  | 4 characters  |
+| 0x3     | txlvl8  | 8 characters  |
+| 0x4     | txlvl16 | 16 characters |
+
+Other values are reserved.
+
+### FIFO_CTRL . RXILVL
+Trigger level for RX interrupts. If the FIFO depth is greater than or equal to
+the setting, it raises rx_watermark interrupt.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | rxlvl1  | 1 character   |
+| 0x1     | rxlvl2  | 2 characters  |
+| 0x2     | rxlvl4  | 4 characters  |
+| 0x3     | rxlvl8  | 8 characters  |
+| 0x4     | rxlvl16 | 16 characters |
+| 0x5     | rxlvl32 | 32 characters |
+| 0x6     | rxlvl62 | 62 characters |
+
+Other values are reserved.
+
+### FIFO_CTRL . TXRST
+TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0
+
+### FIFO_CTRL . RXRST
+RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0
+
+## FIFO_STATUS
+UART FIFO status register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xff00ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}, {"name": "RXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                   |
+|:------:|:------:|:-------:|:-------|:------------------------------|
+| 31:24  |        |         |        | Reserved                      |
+| 23:16  |   ro   |    x    | RXLVL  | Current fill level of RX fifo |
+|  15:8  |        |         |        | Reserved                      |
+|  7:0   |   ro   |    x    | TXLVL  | Current fill level of TX fifo |
+
+## OVRD
+TX pin override control. Gives direct SW control over TX pin state
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                          |
+|:------:|:------:|:-------:|:-------|:-------------------------------------|
+|  31:2  |        |         |        | Reserved                             |
+|   1    |   rw   |   0x0   | TXVAL  | Write to set the value of the TX pin |
+|   0    |   rw   |   0x0   | TXEN   | Enable TX pin override control       |
+
+## VAL
+UART oversampled values
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+| 31:16  |        |         |        | Reserved                                                               |
+|  15:0  |   ro   |    x    | RX     | Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15. |
+
+## TIMEOUT_CTRL
+UART RX timeout control
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x80ffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|   31   |   rw   |   0x0   | EN     | Enable RX timeout feature          |
+| 30:24  |        |         |        | Reserved                           |
+|  23:0  |   rw   |   0x0   | VAL    | RX timeout value in UART bit times |
+
+
+
+
+
+## unbent
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                         | Offset   |   Length | Description                         |
+|:---------------------------------------------|:---------|---------:|:------------------------------------|
+| bus_err_unit.[`err_addr`](#err_addr)         | 0x0      |        4 | Address of the bus error            |
+| bus_err_unit.[`err_addr_top`](#err_addr_top) | 0x4      |        4 | Top of the address of the bus error |
+| bus_err_unit.[`err_code`](#err_code)         | 0x8      |        4 | Error code of the bus error         |
+| bus_err_unit.[`meta`](#meta)                 | 0xc      |        4 | Meta information of the bus error   |
+
+## err_addr
+Address of the bus error
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description              |
+|:------:|:------:|:-------:|:---------|:-------------------------|
+|  31:0  |   ro   |    x    | err_addr | Address of the bus error |
+
+## err_addr_top
+Top of the address of the bus error
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description              |
+|:------:|:------:|:-------:|:---------|:-------------------------|
+|  31:0  |   ro   |    x    | err_addr | Address of the bus error |
+
+## err_code
+Error code of the bus error
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_code", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                 |
+|:------:|:------:|:-------:|:---------|:----------------------------|
+|  31:0  |   ro   |    x    | err_code | Error code of the bus error |
+
+## meta
+Meta information of the bus error
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "meta", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                       |
+|:------:|:------:|:-------:|:-------|:----------------------------------|
+|  31:0  |   ro   |    x    | meta   | Meta information of the bus error |
+
+
+
+
+
+## vga
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                                      | Offset   |   Length | Description                               |
+|:----------------------------------------------------------|:---------|---------:|:------------------------------------------|
+| axi_vga.[`CONTROL`](#control)                             | 0x0      |        4 | Control register                          |
+| axi_vga.[`CLK_DIV`](#clk_div)                             | 0x4      |        4 | Clock divider                             |
+| axi_vga.[`HORI_VISIBLE_SIZE`](#hori_visible_size)         | 0x8      |        4 | Size of horizontal visible area           |
+| axi_vga.[`HORI_FRONT_PORCH_SIZE`](#hori_front_porch_size) | 0xc      |        4 | Size of horizontal front porch            |
+| axi_vga.[`HORI_SYNC_SIZE`](#hori_sync_size)               | 0x10     |        4 | Size of horizontal sync area              |
+| axi_vga.[`HORI_BACK_PORCH_SIZE`](#hori_back_porch_size)   | 0x14     |        4 | Size of horizontal back porch             |
+| axi_vga.[`VERT_VISIBLE_SIZE`](#vert_visible_size)         | 0x18     |        4 | Size of vertical visible area             |
+| axi_vga.[`VERT_FRONT_PORCH_SIZE`](#vert_front_porch_size) | 0x1c     |        4 | Size of vertical front porch              |
+| axi_vga.[`VERT_SYNC_SIZE`](#vert_sync_size)               | 0x20     |        4 | Size of vertical sync area                |
+| axi_vga.[`VERT_BACK_PORCH_SIZE`](#vert_back_porch_size)   | 0x24     |        4 | Size of vertical back porch               |
+| axi_vga.[`START_ADDR_LOW`](#start_addr_low)               | 0x28     |        4 | Low end of start address of frame buffer  |
+| axi_vga.[`START_ADDR_HIGH`](#start_addr_high)             | 0x2c     |        4 | High end of start address of frame buffer |
+| axi_vga.[`FRAME_SIZE`](#frame_size)                       | 0x30     |        4 | Size of whole frame                       |
+| axi_vga.[`BURST_LEN`](#burst_len)                         | 0x34     |        4 | Number of beats in a burst                |
+
+## CONTROL
+Control register
+- Offset: `0x0`
+- Reset default: `0x6`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "hsync_pol", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "vsync_pol", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                            |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------|
+|  31:3  |        |         |           | Reserved                                               |
+|   2    |   rw   |   0x1   | vsync_pol | Sets polarity for VSYNC 0 - Active Low 1 - Active High |
+|   1    |   rw   |   0x1   | hsync_pol | Sets polarity for HSYNC 0 - Active Low 1 - Active High |
+|   0    |   rw   |   0x0   | enable    | Enables FSM.                                           |
+
+## CLK_DIV
+Clock divider
+- Offset: `0x4`
+- Reset default: `0x1`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_div", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description    |
+|:------:|:------:|:-------:|:--------|:---------------|
+|  31:8  |        |         |         | Reserved       |
+|  7:0   |   rw   |   0x1   | clk_div | Clock divider. |
+
+## HORI_VISIBLE_SIZE
+Size of horizontal visible area
+- Offset: `0x8`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_visible_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                      |
+|:------:|:------:|:-------:|:------------------|:---------------------------------|
+|  31:0  |   rw   |   0x1   | hori_visible_size | Size of horizontal visible area. |
+
+## HORI_FRONT_PORCH_SIZE
+Size of horizontal front porch
+- Offset: `0xc`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_front_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                     |
+|:------:|:------:|:-------:|:----------------------|:--------------------------------|
+|  31:0  |   rw   |   0x1   | hori_front_porch_size | Size of horizontal front porch. |
+
+## HORI_SYNC_SIZE
+Size of horizontal sync area
+- Offset: `0x10`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_sync_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                   |
+|:------:|:------:|:-------:|:---------------|:------------------------------|
+|  31:0  |   rw   |   0x1   | hori_sync_size | Size of horizontal sync area. |
+
+## HORI_BACK_PORCH_SIZE
+Size of horizontal back porch
+- Offset: `0x14`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_back_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description                    |
+|:------:|:------:|:-------:|:---------------------|:-------------------------------|
+|  31:0  |   rw   |   0x1   | hori_back_porch_size | Size of horizontal back porch. |
+
+## VERT_VISIBLE_SIZE
+Size of vertical visible area
+- Offset: `0x18`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_visible_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                    |
+|:------:|:------:|:-------:|:------------------|:-------------------------------|
+|  31:0  |   rw   |   0x1   | vert_visible_size | Size of vertical visible area. |
+
+## VERT_FRONT_PORCH_SIZE
+Size of vertical front porch
+- Offset: `0x1c`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_front_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                   |
+|:------:|:------:|:-------:|:----------------------|:------------------------------|
+|  31:0  |   rw   |   0x1   | vert_front_porch_size | Size of vertical front porch. |
+
+## VERT_SYNC_SIZE
+Size of vertical sync area
+- Offset: `0x20`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_sync_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                 |
+|:------:|:------:|:-------:|:---------------|:----------------------------|
+|  31:0  |   rw   |   0x1   | vert_sync_size | Size of vertical sync area. |
+
+## VERT_BACK_PORCH_SIZE
+Size of vertical back porch
+- Offset: `0x24`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_back_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description                  |
+|:------:|:------:|:-------:|:---------------------|:-----------------------------|
+|  31:0  |   rw   |   0x1   | vert_back_porch_size | Size of vertical back porch. |
+
+## START_ADDR_LOW
+Low end of start address of frame buffer
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "start_addr_low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                               |
+|:------:|:------:|:-------:|:---------------|:------------------------------------------|
+|  31:0  |   rw   |   0x0   | start_addr_low | Low end of start address of frame buffer. |
+
+## START_ADDR_HIGH
+High end of start address of frame buffer
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "start_addr_high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                                |
+|:------:|:------:|:-------:|:----------------|:-------------------------------------------|
+|  31:0  |   rw   |   0x0   | start_addr_high | High end of start address of frame buffer. |
+
+## FRAME_SIZE
+Size of whole frame
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "frame_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description          |
+|:------:|:------:|:-------:|:-----------|:---------------------|
+|  31:0  |   rw   |   0x0   | frame_size | Size of whole frame. |
+
+## BURST_LEN
+Number of beats in a burst
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "burst_len", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                 |
+|:------:|:------:|:-------:|:----------|:----------------------------|
+|  31:8  |        |         |           | Reserved                    |
+|  7:0   |   rw   |   0x0   | burst_len | Number of beats in a burst. |
+
+
+
+
+
+## watchdog_timer
+
+
+
+### registers.md
+
+## Summary
+
+| Name                                            | Offset   |   Length | Description                            |
+|:------------------------------------------------|:---------|---------:|:---------------------------------------|
+| aon_timer.[`ALERT_TEST`](#alert_test)           | 0x0      |        4 | Alert Test Register                    |
+| aon_timer.[`WKUP_CTRL`](#wkup_ctrl)             | 0x4      |        4 | Wakeup Timer Control register          |
+| aon_timer.[`WKUP_THOLD`](#wkup_thold)           | 0x8      |        4 | Wakeup Timer Threshold Register        |
+| aon_timer.[`WKUP_COUNT`](#wkup_count)           | 0xc      |        4 | Wakeup Timer Count Register            |
+| aon_timer.[`WDOG_REGWEN`](#wdog_regwen)         | 0x10     |        4 | Watchdog Timer Write Enable Register   |
+| aon_timer.[`WDOG_CTRL`](#wdog_ctrl)             | 0x14     |        4 | Watchdog Timer Control register        |
+| aon_timer.[`WDOG_BARK_THOLD`](#wdog_bark_thold) | 0x18     |        4 | Watchdog Timer Bark Threshold Register |
+| aon_timer.[`WDOG_BITE_THOLD`](#wdog_bite_thold) | 0x1c     |        4 | Watchdog Timer Bite Threshold Register |
+| aon_timer.[`WDOG_COUNT`](#wdog_count)           | 0x20     |        4 | Watchdog Timer Count Register          |
+| aon_timer.[`INTR_STATE`](#intr_state)           | 0x24     |        4 | Interrupt State Register               |
+| aon_timer.[`INTR_TEST`](#intr_test)             | 0x28     |        4 | Interrupt Test Register                |
+| aon_timer.[`WKUP_CAUSE`](#wkup_cause)           | 0x2c     |        4 | Wakeup request status                  |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## WKUP_CTRL
+Wakeup Timer Control register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "prescaler", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------|
+| 31:13  |        |         |           | Reserved                                   |
+|  12:1  |   rw   |   0x0   | prescaler | Pre-scaler value for wakeup timer count    |
+|   0    |   rw   |   0x0   | enable    | When set to 1, the wakeup timer will count |
+
+## WKUP_THOLD
+Wakeup Timer Threshold Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                               |
+|:------:|:------:|:-------:|:----------|:----------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a wakeup interrupt should be generated |
+
+## WKUP_COUNT
+Wakeup Timer Count Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "count", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  31:0  |   rw   |   0x0   | count  | The current wakeup counter value |
+
+## WDOG_REGWEN
+Watchdog Timer Write Enable Register
+- Offset: `0x10`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "regwen", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                     |
+|   0    |  rw0c  |   0x1   | regwen | Once cleared, the watchdog configuration will be locked until the next reset |
+
+## WDOG_CTRL
+Watchdog Timer Control register
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pause_in_sleep", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                   |
+|:------:|:------:|:-------:|:---------------|:--------------------------------------------------------------|
+|  31:2  |        |         |                | Reserved                                                      |
+|   1    |   rw   |   0x0   | pause_in_sleep | When set to 1, the watchdog timer will not count during sleep |
+|   0    |   rw   |   0x0   | enable         | When set to 1, the watchdog timer will count                  |
+
+## WDOG_BARK_THOLD
+Watchdog Timer Bark Threshold Register
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                      |
+|:------:|:------:|:-------:|:----------|:-----------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a watchdog bark interrupt should be generated |
+
+## WDOG_BITE_THOLD
+Watchdog Timer Bite Threshold Register
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a watchdog bite reset should be generated |
+
+## WDOG_COUNT
+Watchdog Timer Count Register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "count", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | count  | The current watchdog counter value |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "wkup_timer_expired", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "wdog_timer_bark", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description                                                |
+|:------:|:------:|:-------:|:-------------------|:-----------------------------------------------------------|
+|  31:2  |        |         |                    | Reserved                                                   |
+|   1    |  rw1c  |   0x0   | wdog_timer_bark    | Raised if the watchdog timer has hit the bark threshold    |
+|   0    |  rw1c  |   0x0   | wkup_timer_expired | Raised if the wakeup timer has hit the specified threshold |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "wkup_timer_expired", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "wdog_timer_bark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description                                   |
+|:------:|:------:|:-------:|:-------------------|:----------------------------------------------|
+|  31:2  |        |         |                    | Reserved                                      |
+|   1    |   wo   |    x    | wdog_timer_bark    | Write 1 to force wdog_timer_bark interrupt    |
+|   0    |   wo   |    x    | wkup_timer_expired | Write 1 to force wkup_timer_expired interrupt |
+
+## WKUP_CAUSE
+Wakeup request status
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cause", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------|
+|  31:1  |        |         |        | Reserved                                     |
+|   0    |  rw0c  |   0x0   | cause  | AON timer requested wakeup, write 0 to clear |
+
+
+
diff --git a/docs/um/arch.md b/docs/um/arch.md
index 4e46ed2c..4f26926a 100644
--- a/docs/um/arch.md
+++ b/docs/um/arch.md
@@ -69,20 +69,20 @@ clarity.
 |--------------------------|-------------------------|------------------|----------|-----------------|---------------|-------------|--------------|----------------------------------------------------------------------|
 | **Internal to Cheshire** |                         |                  |          |                 |               |             |              |                                                                      |
 | `0x0000_0000`            | `0x0004_0000`           | `0x04_0000`      | 256 KiB  | (debug)         |               |             | Debug        | Debug CVA6                                                           |
-| `0x0004_0000`            | `0x0100_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
-| `0x0100_0000`            | `0x0100_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | AXI DMA Config                                                       |
+| `0x0004_0000`            | `0x0100_0000`           |                  |          |                 |               |             | *Reserved*   |                                                    |
+| `0x0100_0000`            | `0x0100_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | carfield/docs/um/ip/axi_dma_config/doc/idma_desc64_frontend_doc Config                                                       |
 | `0x0100_1000`            | `0x0200_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
 | `0x0200_0000`            | `0x0204_0000`           | `0x04_0000`      | 256 KiB  | rx              |               |             | Memory       | Boot ROM                                                             |
 | `0x0204_0000`            | `0x0208_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | CLINT                                                                |
-| `0x0208_0000`            | `0x020c_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | IRQ Routing                                                          |
-| `0x020c_0000`            | `0x0210_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | AXI-REALM unit                                                       |
+| `0x0208_0000`            | `0x020c_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | carfield/docs/um/ip/irq_router/doc/registers.md    |
+| `0x020c_0000`            | `0x0210_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | carfield/docs/um/ip/axi_realm/doc/registers.md     |
 | `0x020c_0000`            | `0x0300_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
-| `0x0300_0000`            | `0x0300_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | Cheshire PCRs                                                        |
+| `0x0300_0000`            | `0x0300_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | carfield/docs/um/ip/cheshire/doc/registers.md      |
 | `0x0300_1000`            | `0x0300_2000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | LLC                                                                  |
-| `0x0300_2000`            | `0x0300_3000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [UART](https://opentitan.org/book/hw/ip/uart/doc/registers.html)     |
-| `0x0300_3000`            | `0x0300_4000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [I2C](https://opentitan.org/book/hw/ip/i2c/doc/registers.html)       |
-| `0x0300_4000`            | `0x0300_5000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [SPIM](https://opentitan.org/book/hw/ip/spi_host/doc/registers.html) |
-| `0x0300_5000`            | `0x0300_6000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [GPIO](https://opentitan.org/book/hw/ip/gpio/doc/registers.html)     |
+| `0x0300_2000`            | `0x0300_3000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | carfield/docs/um/ip/uart/doc/registers.md          |
+| `0x0300_3000`            | `0x0300_4000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | carfield/docs/um/ip/i2c/doc/registers.md           |
+| `0x0300_4000`            | `0x0300_5000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | carfield/docs/um/ip/spim/doc/registers.md          |
+| `0x0300_5000`            | `0x0300_6000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | carfield/docs/um/ip/gpio/doc/registers.md          |
 | `0x0300_6000`            | `0x0300_7000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | Serial Link                                                          |
 | `0x0300_7000`            | `0x0300_8000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | VGA                                                                  |
 | `0x0300_8000`            | `0x0300_A000`           | `0x00_1000`      | 8 KiB    | rw              |               |             | Config       | UNBENT (bus error unit)                                              |
diff --git a/docs/um/carfield_full_doc-online.pdf b/docs/um/carfield_full_doc-online.pdf
new file mode 100644
index 00000000..2746140a
Binary files /dev/null and b/docs/um/carfield_full_doc-online.pdf differ
diff --git a/docs/um/carfield_full_doc.md b/docs/um/carfield_full_doc.md
new file mode 100644
index 00000000..97d456f3
--- /dev/null
+++ b/docs/um/carfield_full_doc.md
@@ -0,0 +1,28699 @@
+# Carfield Documentation
+
+# Architecture
+
+![Carfield Block Diagram](../img/arch.svg)
+
+Carfield is organized in *domains*. As a mixed-criticality system (MCS), each domain serves
+different purposes in terms of functional safety and reliability, security, and computation
+capabilities.
+
+Carfield relies on Cheshire as its host domain, and extends its minimal SoC with additional
+interconnect ports and interrupts.
+
+The above block diagram depicts a fully-featured Carfield SoC, which currently provides:
+
+- **Domains**:
+	- *Host domain* (Cheshire), a Linux-capable RV64 system based on dual-core CVA6 processors with
+	  self-invalidation coherency mechanism
+	- *Safe domain*, a Triple-Core-Lockstep (TCLS) RV32 microcontroller system based on CV32E40P,
+	  with fast interrupt handling through the RISC-V CLIC
+	- *Secure domain*, a Dual-Core-Lockstep (DCLS) RV32 Hardware Root of Trust (HW RoT) systems that
+	  ensures the secure boot for the whole platform, serves as secure monitor for the entire
+	  system, and provides crypto acceleration services through various crypto-accelerators
+	- *Accelerator domain*, comprises two programmable multi-core accelerators (PMCAs), an 12-cores
+	  integer cluster with Hybrid Modular Redundancy (HMR) capabilities oriented to compute
+	  intensive integer workloads such as AI, and a vectorial cluster with floating point vector
+	  processing capabilities to accelerate intensive control tasks
+
+- **On-chip and off-chip memory endpoints**:
+	- *Dynamic SPM*: dynamically configurable scratchpad memory (SPM) for *interleaved* or
+	  *contiguous* accesses aiming at reducing systematic bus conflicts to improve the
+	  time-predictability of the on-chip communication
+	- *Partitionable hybrid LLC SPM*: the last-level cache (*host domain*) can be configured as SPM
+	  at runtime, as described in Cheshire's
+	  [Architecture](https://pulp-platform.github.io/cheshire/um/arch/)
+	- *External DRAM*: off-chip HyperRAM (Infineon) interfaced with in-house, open-source AXI4
+	  Hyberbus memory controller and digital PHY connected to Cheshire's LLC
+
+- **Mailbox unit**
+	- Main communication vehicle among domains, based on an interrupt notification mechanism
+
+- **Platform control registers (PCRs)**
+	- Management and control registers for the entire platform, control clock sources assignments,
+	  clock gating, isolation.
+
+- **Interconnect** (as in Cheshire):
+	- A last level cache (LLC) configurable as a scratchpad memory (SPM) per-way
+	- Up to 16 external AXI4 manager ports and 16 AXI and Regbus subordinate ports
+	- Per-manager AXI4 traffic regulators for real-time applications
+	- Per-manager AXI4 bus error units (UNBENT) for interconnect error handling
+
+- **Interrupts** (as in Cheshire):
+	- Core-local (CLINT *and* CLIC) and platform (PLIC) interrupt controllers
+	- Dynamic interrupt routing from and to internal and external targets.
+
+- **Peripherals**:
+	- Generic timers
+	- PWM timers
+	- Watchdog timer
+	- Ethernet
+	- CAN
+
+## Memory Map
+
+This section shows Carfield's memory map. The group `Internal to Cheshire` in the table below only
+recalls the memory map described in the dedicatd [documentation for
+Cheshire](https://pulp-platform.github.io/cheshire/um/arch/) and is explicitely shown here for
+clarity.
+
+| **Start Address**        | **End Address (excl.)** | **Length**       | **Size** | **Permissions** | **Cacheable** | **Atomics** | **Region**   | **Device**                                                           |
+|--------------------------|-------------------------|------------------|----------|-----------------|---------------|-------------|--------------|----------------------------------------------------------------------|
+| **Internal to Cheshire** |                         |                  |          |                 |               |             |              |                                                                      |
+| `0x0000_0000`            | `0x0004_0000`           | `0x04_0000`      | 256 KiB  | (debug)         |               |             | Debug        | Debug CVA6                                                           |
+| `0x0004_0000`            | `0x0100_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x0100_0000`            | `0x0100_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | [AXI_DMA_Config](ip/axi_dma_config/doc/idma_reg64_2d_frontend_doc.md)                               |
+| `0x0100_1000`            | `0x0200_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x0200_0000`            | `0x0204_0000`           | `0x04_0000`      | 256 KiB  | rx              |               |             | Memory       | Boot ROM                                                             |
+| `0x0204_0000`            | `0x0208_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | [CLINT](ip/clint/doc/registers.md)                                                        |
+| `0x0208_0000`            | `0x020c_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | [IRQ_Routing](ip/irq_router/doc/registers.md)                                                    |
+| `0x020c_0000`            | `0x0210_0000`           | `0x04_0000`      | 256 KiB  | rw              |               |             | Irq          | [AXI_REALM_unit](ip/axi_realm/doc/registers.md)                                              |
+| `0x020c_0000`            | `0x0300_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x0300_0000`            | `0x0300_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | [Cheshire_PCRs](ip/cheshire/doc/registers.md)                                                         |
+| `0x0300_1000`            | `0x0300_2000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | [LLC](ip/axi_llc/doc/registers.md)                                                        |
+| `0x0300_2000`            | `0x0300_3000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [UART](ip/uart/doc/registers.md)           |
+| `0x0300_3000`            | `0x0300_4000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [I2C](ip/i2c/doc/registers.md)       |
+| `0x0300_4000`            | `0x0300_5000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [SPIM](ip/spim/doc/registers.md) |
+| `0x0300_5000`            | `0x0300_6000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [GPIO](ip/gpio/doc/registers.md)     |
+| `0x0300_6000`            | `0x0300_7000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | [Serial_Link](ip/serial_link/doc/registers.md)                                                 |
+| `0x0300_7000`            | `0x0300_8000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | [VGA](ip/vga/doc/registers.md)                                                        |
+| `0x0300_8000`            | `0x0300_A000`           | `0x00_1000`      | 8 KiB    | rw              |               |             | Config       | [UNBENT](ip/unbent/doc/registers.md) (bus error unit)                                              |
+| `0x0300_A000`            | `0x0300_B000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Config       | [Tagger](ip/tagger/doc/registers.md) (LLC partitioning)                                            |
+| `0x0300_8000`            | `0x0400_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x0400_0000`            | `0x1000_0000`           | `0x40_0000`      | 64 MiB   | rw              |               |             | Irq          | [PLIC](ip/plic/doc/registers.md)                                                        |
+| `0x0800_0000`            | `0x0C00_0000`           | `0x40_0000`      | 64 MiB   | rw              |               |             | Irq          | [CLIC_INT](ip/clic/doc/clicint_registers.md), [CLIC_TV](ip/clic/doc/clictv_registers.md), [CLIC_VS](ip/clic/doc/clicvs_registers.md), [MCLIC](ip/clic/doc/mclic_registers.md)           |
+| `0x1000_0000`            | `0x1400_0000`           | `0x40_0000`      | 64 MiB   | rwx             | yes           | yes         | Memory       | [LLC_Scratchpad](ip/axi_llc/doc/registers.md)                                                    |
+| `0x1400_0000`            | `0x1800_0000`           | `0x40_0000`      | 64 MiB   | rwx             |               | yes         | Memory       | [LLC_Scratchpad](ip/axi_llc/doc/registers.md)                                                    |
+| `0x1800_0000`            | `0x2000_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| **External to Cheshire** |                         |                  |          | rw              |               |             |              |                                                                      |
+| `0x2000_0000`            | `0x2000_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [Ethernet](ip/ethernet/doc/registers.md)                                                        |
+| `0x2000_1000`            | `0x2000_2000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [CAN_BUS](ip/can_bus/doc/registers.md)                                                    |
+| `0x2000_2000`            | `0x2000_3000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | (empty)                                                              |
+| `0x2000_3000`            | `0x2000_4000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | (empty)                                                              |
+| `0x2000_4000`            | `0x2000_5000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [GP_timer_1](ip/gp_timer1_system_timer/doc/registers.md) (System timer)                                    |
+| `0x2000_5000`            | `0x2000_6000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [GP_timer_2](ip/gp_timer2_advanced_timer/doc/registers.md) (Advanced timer)                                |
+| `0x2000_6000`            | `0x2000_7000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | GP timer 3                                                           |
+| `0x2000_7000`            | `0x2000_8000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [Watchdog_time](ip/watchdog_timer/doc/registers.md)                                               |
+| `0x2000_8000`            | `0x2000_9000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | (empty)                                                              |
+| `0x2000_9000`            | `0x2000_a000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [HyperBUS](ip/hyperbus/doc/registers.md)                                                        |
+| `0x2000_a000`            | `0x2000_b000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | Pad Config                                                           |
+| `0x2000_b000`            | `0x2000_c000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [L2_ECC_Config](ip/l2_ecc_config/doc/registers.md)                                                 |
+| `0x2001_0000`            | `0x2001_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | [Carfield_Control_and_Status](ip/carfield_regs/doc/carfield_regs.md)                               |
+| `0x2002_0000`            | `0x2002_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | I/O          | (if any) PLL/CLOCK                                                   |
+| `0x2800_1000`            | `0x4000_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x4000_0000`            | `0x4000_1000`           | `0x00_1000`      | 4 KiB    | rw              |               |             | Irq          | [Mailboxes](ip/mailbox/doc/registers.md)                                                       |
+| `0x4000_1000`            | `0x5000_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x5000_0000`            | `0x5080_0000`           | `0x80_0000`      | 8 MiB    | rw              |               |             | Accelerators | [Integer_Cluster](ip/integer_cluster/doc/pulp_cluster_peripherals_memory_map)                         |
+| `0x5080_0000`            | `0x5100_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x5100_0000`            | `0x5180_0000`           | `0x80_0000`      | 8 MiB    | rw              |               |             | Accelerators | [FP_Cluster](ip/cluster_peripherals/doc)                                                              |
+| `0x5100_0000`            | `0x6000_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x6000_0000`            | `0x6002_0000`           | `0x02_0000`      | 128 KiB  | rw              |               | yes         | Safe domain  | Safety Island Memory                                                 |
+| `0x6002_0000`            | `0x6020_0000`           | `0x1e_0000`      |          | rw              |               |             | Safe domain  | reserved                                                             |
+| `0x6020_0000`            | `0x6030_0000`           | `0x10_0000`      | 1 MiB    | rw              |               | yes         | Safe domain  | [Safety_Island_Peripherals](ip/safety_island/doc/registers.md)                                          |
+| `0x6030_0000`            | `0x6080_0000`           | `0x50_0000`      |          | rw              |               |             | Safe domain  | reserved                                                             |
+| `0x6080_0000`            | `0x7000_0000`           |                  |          |                 |               |             | *Reserved*   |                                                                      |
+| `0x7000_0000`            | `0x7002_0000`           | `0x02_0000`      | 128 KiB  | rwx             | yes           | yes         | Memory       | LLC Scratchpad                                                       |
+| `0x7800_0000`            | `0x7810_0000`           | `0x10_0000`      | 1 MiB    | rwx             | yes           | yes         | Memory       | L2 Scratchpad (Port 1, interleaved)                                  |
+| `0x7810_0000`            | `0x7820_0000`           | `0x10_0000`      | 1 MiB    | rwx             | yes           | yes         | Memory       | L2 Scratchpad (Port 1, non-interleaved)                              |
+| `0x7820_0000`            | `0x7830_0000`           | `0x10_0000`      | 1 MiB    | rwx             | yes           | yes         | Memory       | L2 Scratchpad (Port 2, interleaved)                                  |
+| `0x7830_0000`            | `0x7840_0000`           | `0x10_0000`      | 1 MiB    | rwx             | yes           | yes         | Memory       | L2 Scratchpad (Port 2, non-interleaved)                              |
+| `0x8000_0000`            | `0x20_8000_0000`        | `0x20_0000_0000` | 128 GiB  | rwx             | yes           | yes         | Memory       | LLC/DRAM                                                             |
+
+## Interrupt map
+
+Carfield's interrupt components are exhaustivly described in
+the dedicated section of the [documentation for
+Cheshire](https://pulp-platform.github.io/cheshire/um/arch/). This section describes Carfield's interrupt map.
+
+| **Interrupt Source**        | **Interrupt sink**  | **Bitwidth** | **Connection**                                                | **Type**        | **Comment**               |
+|-----------------------------|---------------------|--------------|---------------------------------------------------------------|-----------------|---------------------------|
+| **Carfield peripherals**    |                     |              |                                                               |                 |                           |
+| `intr_wkup_timer_expired_o` |                     | 1            | `car_wdt_intrs[0]       `                                     | level-sensitive |                           |
+| `intr_wdog_timer_bark_o   ` |                     | 1            | `car_wdt_intrs[1]       `                                     | level-sensitive |                           |
+| `nmi_wdog_timer_bark_o    ` |                     | 1            | `car_wdt_intrs[2]       `                                     | level-sensitive |                           |
+| `wkup_req_o               ` |                     | 1            | `car_wdt_intrs[3]       `                                     | level-sensitive |                           |
+| `aon_timer_rst_req_o      ` |                     | 1            | `car_wdt_intrs[4]       `                                     | level-sensitive |                           |
+| `irq                      ` |                     | 1            | `car_can_intr           `                                     | level-sensitive |                           |
+| `ch_0_o[0]                ` |                     | 1            | `car_adv_timer_ch0      `                                     | edge-sensitive  |                           |
+| `ch_0_o[1]                ` |                     | 1            | `car_adv_timer_ch1      `                                     | edge-sensitive  |                           |
+| `ch_0_o[2]                ` |                     | 1            | `car_adv_timer_ch2      `                                     | edge-sensitive  |                           |
+| `ch_0_o[3]                ` |                     | 1            | `car_adv_timer_ch3      `                                     | edge-sensitive  |                           |
+| `events_o[0]              ` |                     | 1            | `car_adv_timer_events[0]`                                     | edge-sensitive  |                           |
+| `events_o[1]              ` |                     | 1            | `car_adv_timer_events[1]`                                     | edge-sensitive  |                           |
+| `events_o[2]              ` |                     | 1            | `car_adv_timer_events[2]`                                     | edge-sensitive  |                           |
+| `events_o[3]              ` |                     | 1            | `car_adv_timer_events[3]`                                     | edge-sensitive  |                           |
+| `irq_lo_o                 ` |                     | 1            | `car_sys_timer_lo       `                                     | edge-sensitive  |                           |
+| `irq_hi_o                 ` |                     | 1            | `car_sys_timer_hi       `                                     | edge-sensitive  |                           |
+| **Cheshire peripherals**    |                     |              |                                                               |                 |                           |
+| `zero                `      |                     | 1            | `zero                `                                        | level-sensitive |                           |
+| `uart                `      |                     | 1            | `uart                `                                        | level-sensitive |                           |
+| `i2c_fmt_threshold   `      |                     | 1            | `i2c_fmt_threshold   `                                        | level-sensitive |                           |
+| `i2c_rx_threshold    `      |                     | 1            | `i2c_rx_threshold    `                                        | level-sensitive |                           |
+| `i2c_fmt_overflow    `      |                     | 1            | `i2c_fmt_overflow    `                                        | level-sensitive |                           |
+| `i2c_rx_overflow     `      |                     | 1            | `i2c_rx_overflow     `                                        | level-sensitive |                           |
+| `i2c_nak             `      |                     | 1            | `i2c_nak             `                                        | level-sensitive |                           |
+| `i2c_scl_interference`      |                     | 1            | `i2c_scl_interference`                                        | level-sensitive |                           |
+| `i2c_sda_interference`      |                     | 1            | `i2c_sda_interference`                                        | level-sensitive |                           |
+| `i2c_stretch_timeout `      |                     | 1            | `i2c_stretch_timeout `                                        | level-sensitive |                           |
+| `i2c_sda_unstable    `      |                     | 1            | `i2c_sda_unstable    `                                        | level-sensitive |                           |
+| `i2c_cmd_complete    `      |                     | 1            | `i2c_cmd_complete    `                                        | level-sensitive |                           |
+| `i2c_tx_stretch      `      |                     | 1            | `i2c_tx_stretch      `                                        | level-sensitive |                           |
+| `i2c_tx_overflow     `      |                     | 1            | `i2c_tx_overflow     `                                        | level-sensitive |                           |
+| `i2c_acq_full        `      |                     | 1            | `i2c_acq_full        `                                        | level-sensitive |                           |
+| `i2c_unexp_stop      `      |                     | 1            | `i2c_unexp_stop      `                                        | level-sensitive |                           |
+| `i2c_host_timeout    `      |                     | 1            | `i2c_host_timeout    `                                        | level-sensitive |                           |
+| `spih_error          `      |                     | 1            | `spih_error          `                                        | level-sensitive |                           |
+| `spih_spi_event      `      |                     | 1            | `spih_spi_event      `                                        | level-sensitive |                           |
+| `gpio                `      |                     | 32           | `gpio                `                                        | level-sensitive |                           |
+| **Spatz cluster**           |                     |              |                                                               |                 |                           |
+|                             | `msip_i[0]`         | 1            | `(hostd_spatzcl_mb_intr_ored[0] \| safed_spatzcl_intr_mb[0])` | level-sensitive | Snitch core #0            |
+|                             | `msip_i[1]`         | 1            | `(hostd_spatzcl_mb_intr_ored[1] \| safed_spatzcl_intr_mb[1])` | level-sensitive | Snitch core #1            |
+|                             | `mtip_i[0]`         | 1            | `chs_mti[0]                                                 ` | level-sensitive | Snitch core #0            |
+|                             | `mtip_i[1]`         | 1            | `chs_mti[1]                                                 ` | level-sensitive | Snitch core #1            |
+|                             | `meip_i   `         | 2            | `\-                                                         ` |                 | unconnected               |
+|                             | `seip_i   `         | 2            | `\-                                                         ` |                 | unconnected               |
+| **HRM integer cluster**     |                     |              |                                                               |                 |                           |
+| `eoc_o`                     |                     | 1            | `pulpcl_eoc                                         `         | level-sensitive |                           |
+|                             | `mbox_irq_i`        | 1            | `(hostd_pulpcl_mb_intr_ored \| safed_pulpcl_intr_mb)`         | level-sensitive | to offload binaries       |
+| **Secure domain**           |                     |              |                                                               |                 |                           |
+|                             | `irq_ibex_i`        | 1            | `(hostd_secd_mb_intr_ored \| safed_secd_intr_mb)`             | level-sensitive | to wake-up Ibex core      |
+| **Safe domain**             |                     |              |                                                               |                 |                           |
+|                             | `irqs_i[0]     `    | 1            | `hostd_safed_mbox_intr[0]  `                                  | level-sensitive | from host domain CVA6#0   |
+|                             | `irqs_i[1]     `    | 1            | `hostd_safed_mbox_intr[1]  `                                  | level-sensitive | from host domain CVA6#1   |
+|                             | `irqs_i[2]     `    | 1            | `secd_safed_mbox_intr      `                                  | level-sensitive | from secure domain        |
+|                             | `irqs_i[3]     `    | 1            | `pulpcl_safed_mbox_intr    `                                  | level-sensitive | from HMR custer           |
+|                             | `irqs_i[4]     `    | 1            | `spatzcl_safed_mbox_intr   `                                  | level-sensitive | from vectorial cluster    |
+|                             | `irqs[5]       `    | 1            | `irqs_distributed_249      `                                  | level-sensitive | tied to 0                 |
+|                             | `irqs[6]       `    | 1            | `irqs_distributed_250      `                                  | level-sensitive | host domain UART          |
+|                             | `irqs[7]       `    | 1            | `irqs_distributed_251      `                                  | level-sensitive | i2c_fmt_threshold         |
+|                             | `irqs[8]       `    | 1            | `irqs_distributed_252      `                                  | level-sensitive | i2c_rx_threshold          |
+|                             | `irqs[9]       `    | 1            | `irqs_distributed_253      `                                  | level-sensitive | i2c_fmt_overview          |
+|                             | `irqs[10]      `    | 1            | `irqs_distributed_254      `                                  | level-sensitive | i2c_rx_overflow           |
+|                             | `irqs[11]      `    | 1            | `irqs_distributed_255      `                                  | level-sensitive | i2c_nak                   |
+|                             | `irqs[12]      `    | 1            | `irqs_distributed_256      `                                  | level-sensitive | i2c_scl_interference      |
+|                             | `irqs[13]      `    | 1            | `irqs_distributed_257      `                                  | level-sensitive | i2c_sda_interference      |
+|                             | `irqs[14]      `    | 1            | `irqs_distributed_258      `                                  | level-sensitive | i2c_stret h_timeout       |
+|                             | `irqs[15]      `    | 1            | `irqs_distributed_259      `                                  | level-sensitive | i2c_sda_unstable          |
+|                             | `irqs[16]      `    | 1            | `irqs_distributed_260      `                                  | level-sensitive | i2c_cmd_complete          |
+|                             | `irqs[17]      `    | 1            | `irqs_distributed_261      `                                  | level-sensitive | i2c_tx_stretch            |
+|                             | `irqs[18]      `    | 1            | `irqs_distributed_262      `                                  | level-sensitive | i2c_tx_overflow           |
+|                             | `irqs[19]      `    | 1            | `irqs_distributed_263      `                                  | level-sensitive | i2c_acq_full              |
+|                             | `irqs[20]      `    | 1            | `irqs_distributed_264      `                                  | level-sensitive | i2c_unexp_stop            |
+|                             | `irqs[21]      `    | 1            | `irqs_distributed_265      `                                  | level-sensitive | i2c_host_timeout          |
+|                             | `irqs[22]      `    | 1            | `irqs_distributed_266      `                                  | level-sensitive | spih_error                |
+|                             | `irqs[23]      `    | 1            | `irqs_distributed_267      `                                  | level-sensitive | spih_spi_event            |
+|                             | `irqs[55:24]   `    | 32           | `irqs_distributed_299:268  `                                  | level-sensitive | gpio                      |
+|                             | `irqs_i[56]    `    | 1            | `irqs_distributed_300      `                                  | level-sensitive | pulpcl_eoc                |
+|                             | `irqs_i[57]    `    | 1            | `irqs_distributed_309      `                                  | level-sensitive | car_wdt_intrs[0]          |
+|                             | `irqs_i[58]    `    | 1            | `irqs_distributed_310      `                                  | level-sensitive | car_wdt_intrs[1]          |
+|                             | `irqs_i[59]    `    | 1            | `irqs_distributed_311      `                                  | level-sensitive | car_wdt_intrs[2]          |
+|                             | `irqs_i[60]    `    | 1            | `irqs_distributed_312      `                                  | level-sensitive | car_wdt_intrs[3]          |
+|                             | `irqs_i[61]    `    | 1            | `irqs_distributed_313      `                                  | level-sensitive | car_wdt_intrs[4]          |
+|                             | `irqs_i[62]    `    | 1            | `irqs_distributed_314      `                                  | level-sensitive | car_can_intr              |
+|                             | `irqs_i[63]    `    | 1            | `irqs_distributed_315      `                                  | edge-sensitive  | car_adv_timer_ch0         |
+|                             | `irqs_i[64]    `    | 1            | `irqs_distributed_316      `                                  | edge-sensitive  | car_adv_timer_ch1         |
+|                             | `irqs_i[65]    `    | 1            | `irqs_distributed_317      `                                  | edge-sensitive  | car_adv_timer_ch2         |
+|                             | `irqs_i[66]    `    | 1            | `irqs_distributed_318      `                                  | edge-sensitive  | car_adv_timer_ch3         |
+|                             | `irqs_i[67]    `    | 1            | `irqs_distributed_319      `                                  | edge-sensitive  | car_adv_timer_events[0]   |
+|                             | `irqs_i[68]    `    | 1            | `irqs_distributed_320      `                                  | edge-sensitive  | car_adv_timer_events[1]   |
+|                             | `irqs_i[69]    `    | 1            | `irqs_distributed_321      `                                  | edge-sensitive  | car_adv_timer_events[2]   |
+|                             | `irqs_i[70]    `    | 1            | `irqs_distributed_322      `                                  | edge-sensitive  | car_adv_timer_events[0]   |
+|                             | `irqs_i[71]    `    | 1            | `irqs_distributed_323      `                                  | edge-sensitive  | car_sys_timer_lo          |
+|                             | `irqs_i[72]    `    | 1            | `irqs_distributed_324      `                                  | edge-sensitive  | car_sys_timer_hi          |
+|                             | `irqs_i[127:73]`    | 54           | `irqs_distributed_331:325  `                                  | -               | tied to 0                 |
+| **Cheshire**                |                     |              |                                                               |                 |                           |
+|                             | `intr_ext_i[0]    ` | 1            | `pulpcl_eoc             `                                     | level-sensitive | from HMR cluster          |
+|                             | `intr_ext_i[2:1]  ` | 2            | `pulpcl_hostd_mbox_intr `                                     | level-sensitive | from HMR cluster          |
+|                             | `intr_ext_i[4:3]  ` | 2            | `spatzcl_hostd_mbox_intr`                                     | level-sensitive | from vectorial cluster    |
+|                             | `intr_ext_i[6:5]  ` | 2            | `safed_hostd_mbox_intr  `                                     | level-sensitive | from safe domain          |
+|                             | `intr_ext_i[8:7]  ` | 2            | `secd_hostd_mbox_intr   `                                     | level-sensitive | from secure domain        |
+|                             | `intr_ext_i[9]    ` | 1            | `car_wdt_intrs[0]       `                                     | level-sensitive | from carfield peripherals |
+|                             | `intr_ext_i[10]   ` | 1            | `car_wdt_intrs[1]       `                                     | level-sensitive | from carfield peripherals |
+|                             | `intr_ext_i[11]   ` | 1            | `car_wdt_intrs[2]       `                                     | level-sensitive | from carfield peripherals |
+|                             | `intr_ext_i[12]   ` | 1            | `car_wdt_intrs[3]       `                                     | level-sensitive | from carfield peripherals |
+|                             | `intr_ext_i[13]   ` | 1            | `car_wdt_intrs[4]       `                                     | level-sensitive | from carfield peripherals |
+|                             | `intr_ext_i[14]   ` | 1            | `car_can_intr           `                                     | level-sensitive | from carfield peripherals |
+|                             | `intr_ext_i[15]   ` | 1            | `car_adv_timer_ch0      `                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[16]   ` | 1            | `car_adv_timer_ch1      `                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[17]   ` | 1            | `car_adv_timer_ch2      `                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[18]   ` | 1            | `car_adv_timer_ch3      `                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[19]   ` | 1            | `car_adv_timer_events[0]`                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[20]   ` | 1            | `car_adv_timer_events[1]`                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[21]   ` | 1            | `car_adv_timer_events[2]`                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[22]   ` | 1            | `car_adv_timer_events[3]`                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[23]   ` | 1            | `car_sys_timer_lo       `                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[24]   ` | 1            | `car_sys_timer_hi       `                                     | edge-sensitive  | from carfield peripherals |
+|                             | `intr_ext_i[31:25]` | 7            | `0                      `                                     |                 | tied to 0                 |
+| `meip_ext_o[0]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `meip_ext_o[1]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `meip_ext_o[2]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `seip_ext_o[0]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `seip_ext_o[1]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `seip_ext_o[2]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `msip_ext_o[0]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `msip_ext_o[1]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `msip_ext_o[2]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+| `mtip_ext_o[0]`             |                     | \-           |                                                               | level-sensitive | Snitch core #0            |
+| `mtip_ext_o[1]`             |                     | \-           |                                                               | level-sensitive | Snitch core #1            |
+| `mtip_ext_o[2]`             |                     | \-           |                                                               | level-sensitive | unconnected               |
+
+## Domains
+
+The total number of domains is 7: *host domain*, *safe domain*, *secure domain*, *integer PMCA
+domain*, *vectorial PMCA domain*, *peripheral domain*, *dynamic SPM*.
+
+Carfield's domains live in dedicated repositories. We therefore invite the reader to consult the
+documentation of each domain.
+
+For more information about domains' memory requirements, visit [Synthesis and physical
+implementation](../tg/synth.md).
+
+Below, we focus on domains' parameterization within Carfield.
+
+### [Host domain (Cheshire)](https://github.com/pulp-platform/cheshire)
+
+The *host domain* (Cheshire) embeds all the necessary components required to run OSs such as
+embedded Linux. It has two orthogonal *operation modes*.
+
+1. *Untrusted mode*: in this operation mode, the host domain is tasked to run untrusted services,
+i.e. non time- and non safety-critical applications. For example, this could be the case of infotainment
+on a modern car. In this mode, as in traditional automotive platforms, safety and resiliency
+features are deferred to a dedicated 32-bit microcontroller-like system, called `safe domain` in
+Carfield.
+
+2. *Hybrid trusted/untrusted mode*: in this operation mode, the host domain is in charge of both
+critical and non-critical applications. Key features supported to achieve this are:
+  * A virtualization layer, which allows the system to accommodate the execution of multiple OSs,
+including rich, Unix-like OSs and Real-Time OSs (RTOS), coexisting on the same HW.
+  * Spatial and temporal partitioning of resources: AXI matrix crossbar
+	([AXI-REALM](https://arxiv.org/abs/2311.09662)), LLC, TLB, and a `physical tagger` in front of
+	the cores to mark partitions by acting directly on the physical address space
+  * Runtime configurable data/instruction cache and SPM
+  * Fast interrupt handling, with optional interrupt routing through the RISC-V fast interrupt
+controller CLIC,
+  * Configurable dual core setup between *lockstep* or *SMP* mode.
+
+  Hybrid operation mode is currently experimental, and mostly for research purposes. We advise of
+  relying on a combination of host ad safe domain for a more traditional approach.
+
+Cheshire is configured as follows:
+
+* Two 64-bit, RISC-V CVA6 cores, with lightweight self-invalidation cache coherency, fast interrupt
+and virtualization support.
+* 8 external AXI manager ports (`AxiNumExtSlv`) added to the matrix crossbar:
+  - Dynamic SPM port 0
+  - Dynamic SPM port 1
+  - Safe domain
+  - HMR cluster
+  - Vectorial cluster
+  - Mailbox unit
+  - Ethernet
+  - Peripherals
+* 4 external AXI subordinate ports (`AxiNumExtMst`) added to the matrix crossbar:
+  - Safe domain
+  - Secure domain
+  - HMR cluster
+  - Vectorial cluster
+* 4 external regbus subordinate ports (`NumTotalRegSlv`):
+  - PCRs: control domains enable, clock gate, isolation
+  - PLL control registers: for ASIC top-levels, leave unconnected otherwise
+  - Padmux control registers: for ASIC top-levels, leave unconnected otherwise
+  - Dynamic SPM ECC control registers
+* [AXI-REALM](https://arxiv.org/abs/2311.09662) unit for bandwidth regulation and monitoring
+  integrated in front of each AXI matrix crossbar manager
+* Last-level cache (LLC) with HW spatial partitioning
+* 32 *external* input interrupts (`CarfieldNumExtIntrs`), see [Interrupt map](#interrupt-map) in
+  addition to Cheshire's own internal interrupts. Unused are tied to 0 (currently 9/32)
+* 2 external interruptible harts (`CarfieldNumInterruptibleHarts`). The interruptible harts are
+  Snitch core \#0 and \#1 in the vectorial cluster.
+* An interrupt router with 1 external target (`CarfieldNUmRouterTargets`), tasked to distribute N
+  input interrupts to M targets. In Carfield, the external target is the `safe domain`.
+* All Cheshire peripherals, except for VGA
+
+By default, Cheshire hosts 128KiB of hybrid LLC/SPM, user-configurable.
+
+### [Safe domain](https://github.com/pulp-platform/safety_island)
+
+The *safe domain* is a simple MCU-like domain that comprises three 32-bit real-time CV32E40P
+(CV32RT) RISC-V cores operating in triple-core-lockstep mode (TCLS).
+
+These cores, enhanced with the RISC-V CLIC controller and optimized for fast interrupt handling and
+context switch, run RTOSs and safety-critical applications, embodying a core tenet of the platform
+reliability.
+
+The *safe domain* is essential when the *host domain* is operated in *untrusted* mode.
+
+The *safe domain* is configured as follows:
+
+* 1 RISC-V debug module prividing indipendent JTAG interface off-Carfield
+* 1 AXI manager and 1 AXI subordinate ports, 32-bit data and 32-bit address wide, to and from the
+  *host domain*, respectively. AXI datawidth conversion with the host domain is handled internally
+  to the safe domain.
+* 1 generic timer, essential for periodic ticks common in RTOSs. The generic timer in the *safe
+  domain* is the same integrated in [Carfield's *peripheral domain*](#peripheral-domain).
+* CLIC RISC-V interrupt controller; as opposed to Cheshire, currently the CLIC is configured to run
+  run in M-mode.
+* 128 *external* input interrupts. Unused are tied to 0.
+* Fast interrupt extension that extends CV32 with additional logic to accelerate context switching.
+  From here, the name [CV32RT](https://arxiv.org/abs/2311.08320)
+* 1 32-bit per-core FPU with down to float-16 precision, totaling 3 FPUs
+
+By default, the processing elements share access to 128KiB of SPM for instructions and data,
+user-configurable.
+
+### [Secure domain](https://github.com/pulp-platform/opentitan/tree/carfield-soc)
+
+The secure domain, based on the [OpenTitan
+project](https://opentitan.org/book/doc/introduction.html), serves as the Hardware Root-of-Trust
+(HWRoT) of the platform. It handles *secure boot* and system integrity monitoring fully in HW
+through cryptographic acceleration services.
+
+Compared to vanilla OpenTitan, the secure domain integrated in Carfield is modified/configured as follows:
+
+* 1 AXI4 manager interface to Carfield, with a bridge between AXI4 and TileLink Uncached Lightweight
+  (TL-UL) internally used by OpenTitan. By only exposing a manager port, unwanted access to the
+  secure domain is prevented.
+
+* Embedded flash memory replaced with an SRAM preloaded before secure boot procedure from an
+  external SPI flash through OpenTitan private SPI peripheral. Once preload is over, the OpenTitan
+  secure boot framework is unchanged compared to the vanilla version.
+
+* Finally, a *boot manager* module has been designed and integrated to manage the [two available
+  bootmodes](./sw.md). In **Secure** mode, the systems executes the secure boot framework as soon as
+  the reset is asserted, loading code from the external SPI and performing the signature check on
+  its content. Otherwise, in **Non-secure** mode, the *secure domain* is clock gated and must be
+  clocked and woken-up by an external entity (e.g., *host domain*)
+
+By default, the secure domain hosts 512KiB of main SPM, and 16KiB of OTP memory, user-configurable.
+
+### Accelerator domain
+
+To augment computational capabilities, Carfield incorporates two PMCAs, described below. Both PMCAs
+integrate DMA engines to independently fetch data from the on-chip SPM or external DRAM.
+
+#### [HMR integer PMCA](https://github.com/pulp-platform/pulp_cluster/tree/yt/rapidrecovery)
+
+The [hybrid modular redundancy (HMR) *integer PMCA*](https://arxiv.org/abs/2303.08706) is
+specialized in accelerating the inference of Deep Learning and Machine Learning models. The
+multicore accelerator is built around 12 32-bit RISC-V cores empowered with ISA extensions, enabling
+integer arithmetic from 32-bit down to 2-bit precision.
+
+The integer PMCA does not integrate a fully-fledged FPU co-processor. Nevertheless, it features a
+highly specialized domain specific accelerator (DSA),
+[RedMulE](https://www.sciencedirect.com/science/article/pii/S0167739X23002546), which enables fast
+and energy-efficient floating-point GEMM on 16-bit and 8-bit data formats. This makes the PMCA
+capable of on-chip training of generalized Deep Learning models.
+
+As part of a MCS, the integer PMCA's general-purpose cores can be reconfigured for *redundant
+execution*. A [Hybrid Modular Redundancy (HMR)](https://doi.org/10.1145/3635161) unit allows the
+split/lock of the available cores in different redundant configurations during runtime, trading off
+the computing performance and the fault resilience capability according to the criticality of the
+application.
+
+The PMCA can be configured in multiple redundant modes:
+* **Independent:** All cores act independently with no redundancy mechanism. This configuration allows
+  higher performance but has no reliability.
+* **Dual Modular Redundancy (DMR)**: The cores are grouped in lock-stepped pairs and rely on a
+  specialized hardware extension for fast fault recovery in less than 30 clock cycles in case of
+  fault detection. The PMCA provides the best trade-off between performance and fault recovery in
+  this configuration.
+* **Triple Modular Redundancy (TMR)**: The cores are grouped in lock-stepped triplets and rely on
+  either hardware extension or software mechanisms to recover from incurring faults. The PMCA
+  provides the highest fault resilience in this configuration, at the cost of reduced performance.
+
+By default, the integer PMCA's processing elements and tensor accelerator share access to 256KiB of
+L1 SPM, user-configurable.
+
+#### [Vectorial PMCA](https://github.com/pulp-platform/spatz)
+
+The [*vectorial PMCA*, or Spatz PMCA](https://dl.acm.org/doi/abs/10.1145/3508352.3549367) handles
+vectorizable multi-format floating-point workloads.
+
+A Spatz vector unit acts as a coprocessor of the [Snitch
+core](https://github.com/pulp-platform/snitch_cluster), a tiny RV32IMA core which decodes and
+forwards vector instructions to the vector unit.
+
+A Snitch core and a Spatz vector unit are together referred to as *Core Complex (CC)*. The vectorial
+PMCA is composed by two CCs, each with the following configuration:
+
+* 2 KiB of latch-based VRF
+* 4 transprecision FPUs
+* 1 integer processing unit (IPU)
+
+Each FPU supports *FP8*, *FP16*, *FP32*, and *FP64* computation, while the IPU supports 8, 16, 32,
+and 64-bit integer computation.
+
+By default, the CCs share access to 128KiB of L1 SPM, user-configurable.
+
+## On-chip and off-chip memory endpoints
+
+### [Dynamic scratchpad memory (SPM)](https://github.com/pulp-platform/dyn_spm)
+
+The dynamic SPM features dynamically switching address mapping policy. It manages the following
+features:
+
+* Two AXI subordinate ports
+* Two address mapping modes: *interleaved* and *contiguous*
+* 4 address spaces, 2 for each port. The address space is used to select the AXI port to use, and
+  the mapping mode
+* Every address space points to the same physical SRAM through a low-latency matrix crossbar
+* ECC-equipped memory banks
+
+By default, Carfield hosts 1MiB of dynamic SPM, user-configurable.
+
+### [Partitionable hybrid LLC/SPM](https://github.com/pulp-platform/axi_llc)
+
+Carfield hosts a LLC optionaly reconfigurable as SPM during runtime. In addition, the LLC supports
+HW-based partitioning to exploit intra-process or inter-processes isolation, improving the system's
+predictability. The LLC is described in detail in Cheshire's
+[Architecture](https://pulp-platform.github.io/cheshire/um/arch).
+
+### [HyperBus off-chip link](https://github.com/pulp-platform/hyperbus)
+
+Carfield integrates a in-house, open-source implementation of Infineon' HyperBus off-chip controller
+to connect to external HyperRAM modules.
+
+It manages the following features:
+
+* An AXI interface that attaches to Cheshire's [partitionable hybrid
+  LLC/SPM](#partitionable-hybrid-llc-spm)
+* A configurable number of physical HyperRAM chips it can be attached to; by default, support for 2
+  physical chips is provided
+* Support for HyperRAM chips with different densities (from 8MiB to 64MiB per chip aligned with
+  specs).
+
+## System bus interconnect
+
+The interconnect is composed of a main [AXI4](https://github.com/pulp-platform/axi) matrix (or
+crossbar) with AXI5 atomic operations (ATOPs) support. The crossbar extends Cheshire's with
+additional external AXI manager and subordinate ports.
+
+Cheshire's auxiliary [Regbus](https://github.com/pulp-platform/register_interface) demultiplexer is
+extended with additional peripheral configuration ports for external PLL/FLL and padmux
+configuration, which are specific of ASIC wrappers.
+
+An additional peripheral subsystem based on APB hosts Carfield-specific peripherals.
+
+## [Mailbox unit](https://github.com/pulp-platform/mailbox_unit)
+
+The mailbox unit consists in a number of configurable mailboxes. Each mailbox is the preferred
+communication vehicle between *domains*. It can be used to wake-up certain domains, notify an
+*offloader* (e.g., Cheshire) that a *target device* (e.g., the integer PMCA) has reached execution
+completion, dispatch *entry points* to a *target device* to jump-start its execution, and many
+others.
+
+It manages the following features:
+
+* Interrupt based signaling receiver and sender
+* A shared memory space common to all the mailboxes, implemented as a single register file.
+  Currently, Carfield implements 25 mailboxes.
+* Support for 32-bit word aligned read/write access.
+* A convenience AXI-Lite wrapper for the configuration port.
+
+---
+
+Assuming each mailbox is identified with id `i`, the register file map reads:
+
+| **Offset**         | **Register**     | **Width (bit)** | **Note**           |
+|--------------------|------------------|-----------------|--------------------|
+| `0x00 + i * 0x100` | `INT_SND_STAT`   | `1`             | current irq status |
+| `0x04 + i * 0x100` | `INT_SND_SET `   | `1`             | set irq            |
+| `0x08 + i * 0x100` | `INT_SND_CLR `   | `1`             | clear irq          |
+| `0x0C + i * 0x100` | `INT_SND_EN  `   | `1`             | enable irq         |
+| `0x40 + i * 0x100` | `INT_RCV_STAT`   | `1`             | current irq status |
+| `0x44 + i * 0x100` | `INT_RCV_SET `   | `1`             | set irq            |
+| `0x48 + i * 0x100` | `INT_RCV_CLR `   | `1`             | clear irq          |
+| `0x4C + i * 0x100` | `INT_RCV_EN  `   | `1`             | enable irq         |
+| `0x80 + i * 0x100` | `LETTER0       ` | `32`            | message            |
+| `0x8C + i * 0x100` | `LETTER1       ` | `32`            | message            |
+
+The above register map can be found in the dedicated
+[repository](https://github.com/pulp-platform/mailbox_uni) and is reported here for convenience.
+
+## Platform control registers
+
+PCRs provide basic system information, and control clock, reset and other functionalities of
+Carfield's *domains*.
+
+A more detailed overview of each PCR (register subfields and description) can be found
+[here](../../hw/regs/pcr.md). PCR base address is listed in the [Memory Map](#memory-map) as for the
+other devices.
+
+| **Name**                         | **Offset** | **Length** | **Description**                                                        |
+|:---------------------------------|:-----------|-----------:|:-----------------------------------------------------------------------|
+| `VERSION0`                       | `0x0`      |        `4` | Cheshire sha256 commit                                                 |
+| `VERSION1`                       | `0x4`      |        `4` | Safety Island sha256 commit                                            |
+| `VERSION2`                       | `0x8`      |        `4` | Security Island sha256 commit                                          |
+| `VERSION3`                       | `0xc`      |        `4` | PULP Cluster sha256 commit                                             |
+| `VERSION4`                       | `0x10`     |        `4` | Spatz CLuster sha256 commit                                            |
+| `JEDEC_IDCODE`                   | `0x14`     |        `4` | JEDEC ID CODE                                                          |
+| `GENERIC_SCRATCH0`               | `0x18`     |        `4` | Scratch                                                                |
+| `GENERIC_SCRATCH1`               | `0x1c`     |        `4` | Scratch                                                                |
+| `HOST_RST`                       | `0x20`     |        `4` | Host Domain reset -active high, inverted in HW-                        |
+| `PERIPH_RST`                     | `0x24`     |        `4` | Periph Domain reset -active high, inverted in HW-                      |
+| `SAFETY_ISLAND_RST`              | `0x28`     |        `4` | Safety Island reset -active high, inverted in HW-                      |
+| `SECURITY_ISLAND_RST`            | `0x2c`     |        `4` | Security Island reset -active high, inverted in HW-                    |
+| `PULP_CLUSTER_RST`               | `0x30`     |        `4` | PULP Cluster reset -active high, inverted in HW-                       |
+| `SPATZ_CLUSTER_RST`              | `0x34`     |        `4` | Spatz Cluster reset -active high, inverted in HW-                      |
+| `L2_RST`                         | `0x38`     |        `4` | L2 reset -active high, inverted in HW-                                 |
+| `PERIPH_ISOLATE`                 | `0x3c`     |        `4` | Periph Domain  AXI isolate                                             |
+| `SAFETY_ISLAND_ISOLATE`          | `0x40`     |        `4` | Safety Island AXI isolate                                              |
+| `SECURITY_ISLAND_ISOLATE`        | `0x44`     |        `4` | Security Island AXI isolate                                            |
+| `PULP_CLUSTER_ISOLATE`           | `0x48`     |        `4` | PULP Cluster AXI isolate                                               |
+| `SPATZ_CLUSTER_ISOLATE`          | `0x4c`     |        `4` | Spatz Cluster AXI isolate                                              |
+| `L2_ISOLATE`                     | `0x50`     |        `4` | L2 AXI isolate                                                         |
+| `PERIPH_ISOLATE_STATUS`          | `0x54`     |        `4` | Periph Domain AXI isolate status                                       |
+| `SAFETY_ISLAND_ISOLATE_STATUS`   | `0x58`     |        `4` | Safety Island AXI isolate status                                       |
+| `SECURITY_ISLAND_ISOLATE_STATUS` | `0x5c`     |        `4` | Security Island AXI isolate status                                     |
+| `PULP_CLUSTER_ISOLATE_STATUS`    | `0x60`     |        `4` | PULP Cluster AXI isolate status                                        |
+| `SPATZ_CLUSTER_ISOLATE_STATUS`   | `0x64`     |        `4` | Spatz Cluster AXI isolate status                                       |
+| `L2_ISOLATE_STATUS`              | `0x68`     |        `4` | L2 AXI isolate status                                                  |
+| `PERIPH_CLK_EN`                  | `0x6c`     |        `4` | Periph Domain clk gate enable                                          |
+| `SAFETY_ISLAND_CLK_EN`           | `0x70`     |        `4` | Safety Island clk gate enable                                          |
+| `SECURITY_ISLAND_CLK_EN`         | `0x74`     |        `4` | Security Island clk gate enable                                        |
+| `PULP_CLUSTER_CLK_EN`            | `0x78`     |        `4` | PULP Cluster clk gate enable                                           |
+| `SPATZ_CLUSTER_CLK_EN`           | `0x7c`     |        `4` | Spatz Cluster clk gate enable                                          |
+| `L2_CLK_EN`                      | `0x80`     |        `4` | Shared L2 memory clk gate enable                                       |
+| `PERIPH_CLK_SEL`                 | `0x84`     |        `4` | Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| `SAFETY_ISLAND_CLK_SEL`          | `0x88`     |        `4` | Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| `SECURITY_ISLAND_CLK_SEL`        | `0x8c`     |        `4` | Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) |
+| `PULP_CLUSTER_CLK_SEL`           | `0x90`     |        `4` | PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)    |
+| `SPATZ_CLUSTER_CLK_SEL`          | `0x94`     |        `4` | Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| `L2_CLK_SEL`                     | `0x98`     |        `4` | L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)       |
+| `PERIPH_CLK_DIV_VALUE`           | `0x9c`     |        `4` | Periph Domain clk divider value                                        |
+| `SAFETY_ISLAND_CLK_DIV_VALUE`    | `0xa0`     |        `4` | Safety Island clk divider value                                        |
+| `SECURITY_ISLAND_CLK_DIV_VALUE`  | `0xa4`     |        `4` | Security Island clk divider value                                      |
+| `PULP_CLUSTER_CLK_DIV_VALUE`     | `0xa8`     |        `4` | PULP Cluster clk divider value                                         |
+| `SPATZ_CLUSTER_CLK_DIV_VALUE`    | `0xac`     |        `4` | Spatz Cluster clk divider value                                        |
+| `L2_CLK_DIV_VALUE`               | `0xb0`     |        `4` | L2 Memory clk divider value                                            |
+| `HOST_FETCH_ENABLE`              | `0xb4`     |        `4` | Host Domain fetch enable                                               |
+| `SAFETY_ISLAND_FETCH_ENABLE`     | `0xb8`     |        `4` | Safety Island fetch enable                                             |
+| `SECURITY_ISLAND_FETCH_ENABLE`   | `0xbc`     |        `4` | Security Island fetch enable                                           |
+| `PULP_CLUSTER_FETCH_ENABLE`      | `0xc0`     |        `4` | PULP Cluster fetch enable                                              |
+| `SPATZ_CLUSTER_DEBUG_REQ`        | `0xc4`     |        `4` | Spatz Cluster debug req                                                |
+| `HOST_BOOT_ADDR`                 | `0xc8`     |        `4` | Host boot address                                                      |
+| `SAFETY_ISLAND_BOOT_ADDR`        | `0xcc`     |        `4` | Safety Island boot address                                             |
+| `SECURITY_ISLAND_BOOT_ADDR`      | `0xd0`     |        `4` | Security Island boot address                                           |
+| `PULP_CLUSTER_BOOT_ADDR`         | `0xd4`     |        `4` | PULP Cluster boot address                                              |
+| `SPATZ_CLUSTER_BOOT_ADDR`        | `0xd8`     |        `4` | Spatz Cluster boot address                                             |
+| `PULP_CLUSTER_BOOT_ENABLE`       | `0xdc`     |        `4` | PULP Cluster boot enable                                               |
+| `SPATZ_CLUSTER_BUSY`             | `0xe0`     |        `4` | Spatz Cluster busy                                                     |
+| `PULP_CLUSTER_BUSY`              | `0xe4`     |        `4` | PULP Cluster busy                                                      |
+| `PULP_CLUSTER_EOC`               | `0xe8`     |        `4` | PULP Cluster end of computation                                        |
+| `ETH_RGMII_PHY_CLK_DIV_EN`       | `0xec`     |        `4` | Ethernet RGMII PHY clock divider enable bit                            |
+| `ETH_RGMII_PHY_CLK_DIV_VALUE`    | `0xf0`     |        `4` | Ethernet RGMII PHY clock divider value                                 |
+| `ETH_MDIO_CLK_DIV_EN`            | `0xf4`     |        `4` | Ethernet MDIO clock divider enable bit                                 |
+| `ETH_MDIO_CLK_DIV_VALUE`         | `0xf8`     |        `4` | Ethernet MDIO clock divider value                                      |
+
+## Peripherals
+
+Carfield enhances Cheshire's peripheral subsystem with additional capabilities.
+
+An external AXI manager port is attached to the matrix crossbar. The 64-bit data, 48-bit address AXI
+protocol is converted to the slower, 32-bit data and address APB protocol. An APB demultiplexer
+allows attaching several peripherals, described below.
+
+### Generic and advanced timer
+
+Carfield integrates a generic timer and an advanced timer.
+
+The [*generic timer*](https://github.com/pulp-platform/timer_unit) manages the following features:
+
+- 2 general purpose 32-bit up counter timers
+- Input trigger sources:
+	 - FLL/PLL clock
+	 - FLL/PLL clock + Prescaler
+	 - Real-time clock (RTC) at crystal frequency (32kHz) or higher
+	 - External event
+- 8-bit programmable prescaler to FLL/PLL clock
+- Counting modes:
+	 - One shot mode: timer is stopped after first comparison match
+	 - Continuous mode: timer continues counting after comparison match
+	 - Cycle mode: timer resets to 0 after comparison match and continues counting
+	 - 64 bit cascaded mode
+- Interrupt request generation on comparison match
+
+For more information, read the dedicated
+[documentation](https://github.com/pulp-platform/timer_unit/blob/master/doc/TIMER_UNIT_reference.xlsx).
+
+The [*advanced timer*](https://github.com/pulp-platform/apb_adv_timer) manages the following
+features:
+
+* 4 timers with 4 output signal channels each
+* PWM generation functionality
+* Multiple trigger input sources:
+   - output signal channels of all timers
+   - 32 GPIOs
+   - Real-time clock (RTC) at crystal frequency (32kHz) or higher
+   - FLL/PLL clock
+  In Carfield, we rely on a RTC.
+* Configurable input trigger modes
+* Configurable prescaler for each timer
+* Configurable counting mode for each timer
+* Configurable channel threshold action for each timer
+* 4 configurable output events
+* Configurable clock gating of each timer
+
+For more information, read the dedicated
+[documentation](https://github.com/pulp-platform/apb_adv_timer/blob/master/doc/APB_ADV_TIMER_reference.xlsx).
+
+### Watchdog timer
+
+We employ the watchdog timer developed by the [OpenTitan
+project](https://opentitan.org/book/doc/introduction.html) project. It manages the following
+features:
+
+* Two 32-bit upcounting timers: one timer functions as a wakeup timer, one as a watchdog timer
+* 2 thresholds: *bark* (generates an interrupt) and *bite* (resets core)
+* A 12 bit pre-scaler for the wakeup timer to enable very long timeouts
+
+For more information, read the dedicated
+[documentation](https://opentitan.org/book/hw/ip/aon_timer/).
+
+### CAN
+
+We employ a CAN device developed by the [Czech Technical
+University](https://github.com/AlSaqr-platform/can_bus/tree/pulp) in Prague. It manages the
+following features:
+
+* CAN 2.0, CAN FD 1.0 and ISO CAN FD
+* Avalon memory bus
+* Timestamping and transmission at given time
+* Optional event and error logging
+* Fault confinement state manipulation
+* Transceiver delay measurement
+* Variety of interrupt sources
+* Filtering of received frame
+* Listen-only mode, Self-test mode, Acknowledge forbidden mode
+* Up to 14 Mbit in “Data” bit-rate (with 100 Mhz Core clock)
+
+For more information, read the dedicated
+[documentation](https://github.com/AlSaqr-platform/can_bus/tree/pulp/doc)
+
+### Ethernet
+
+We employ Ethernet IPs developed by [Alex
+Forencich](https://github.com/alexforencich/verilog-ethernet) and assemble them with a
+high-performant DMA, the same used in Cheshire.
+
+We use Reduced gigabit media-independent interface (RGMII) that supports speed up to 1000Mbit/s
+(1GHz).
+
+For more information, read the dedicated
+[documentation](http://alexforencich.com/wiki/en/verilog/ethernet/start) of Ethernet components from
+its original repository.
+
+## Clock and reset
+
+![Reset and Clock Distribution for a domain *X*](../img/clk_rst.svg)
+
+![Isolation for a domain *X*](../img/isolation.svg)
+
+The two figures above show the clock, reset and isolation distribution for a *domain* `X` in
+Carfield, and their relationship. A more detailed description is provided below.
+
+### Clock distribution scheme, clock gating and isolation
+
+Carfield is provided with 3 clocks sources. They can be fully asynchronous and not bound to any
+phase relationship, since dual-clock FIFOs are placed between domains to allow clock domain crossing
+(CDC):
+
+* `host_clk_i`: preferably, clock of the *host domain*
+* `alt_clk_i`: preferably, clock of *alternate* domains, namely *safe domain*, *secure domain*,
+  *accelerator domain*
+* `per_clk_i`: preferably, clock of *peripheral domain*
+
+In addition, a real-time clock (RTC, `rt_clk_i`) is provided externally, at crystal frequency
+(32kHz) or higher.
+
+These clocks are supplied externally, by a dedicated PLL per clock source or by a single PLL that
+supplies all three clock sources. The configuration of the clock source can be handled by the
+external PLL wrapper configuration registers, e.g. in a ASIC top level
+
+Regardless of the specific name used for the clock signals in HW, Carfield has a flexible clock
+distribution that allows each of the 3 clock sources to be assigned to a *domain*, as explained
+below.
+
+---
+
+As the top figure shows, out of the 7 *domains* described in [Domains](#domains), 6 can be clock
+gated and *isolated*: *safe domain*, *secure domain*, *accelerator domain*, *peripheral domain*,
+*dynamic SPM*.
+
+When *isolation* for a domain `X` is enabled, data transfers towards a domain are terminated and
+never reach it. To achieve this, an AXI4 compliant *isolation* module is placed in front of each
+domain. The bottom figure shows in detail the architecture of the isolation scheme between the *host
+domain* and a generic `X` domain, highlighting its relationship with the domain's reset and cloc
+signals.
+
+For each of the 6 clock gateable domains, the following clock distribution scheme applies:
+
+1. The user selects one of the 3 different clock sources
+2. The selected clock source for the domain is fed into a default-bypassed arbitrary integer clock
+   divider with 50% duty cycle. This allows to use different integer clock divisions for every
+   target domain to use different clock frequencies
+3. The internal clock gate of the clock divider is used to provide clock gating for the domain.
+
+HW resources for the clock distribution (steps 1., 2., and 3.) and isolation of a domain `X`, are
+SW-controlled via dedicated PCRs. Refer to [Platform Control Registers](#platform-control-registers)
+in this page for more information.
+
+The only domain that is always-on and de-isolated is the *host domain* (Cheshire). If required,
+clock gating and/or isolation of it can be handled at higher levels of hierarchy, e.g. in a
+dedicated ASIC wrapper.
+
+### Startup behavior after Power-on reset (POR)
+
+The user can decide whether *secure boot* must be performed on the executing code before runtime. If
+so, the *secure domain* must be active after POR, i.e., clocked and de-isolated. This behavior is
+regulated by the input pin `secure_boot_i` according to the following table:
+
+| `secure_boot_i` | **Secure Boot** | **System status after POR**                                                                                                                       |
+|:----------------|----------------:|:--------------------------------------------------------------------------------------------------------------------------------------------------|
+| `0`             |           `OFF` | *secure domain* gated and isolated as the other 5 domains, *host domain* always-on and idle                                                       |
+| `1`             |            `ON` | *host domain* always-on and idle, *secure domain* active, takes over *secure boot* and can't be warm reset-ed; other 5 domains gated and isolated |
+
+Regardless of the value of `secure_boot_i`, since by default some domains are clock gated and
+isolated after POR, SW or external physical interfaces (JTAG/Serial Link) must handle their wake-up
+process. Routines are provided in the [Software Stack](../../sw/include/car_util.h).
+
+### Reset distribution scheme
+
+Carfield is provided with one POR (active-low), `pwr_on_rst_ni`, responsible for the platform's
+*cold reset*.
+
+The POR is synchronized with the clock of each domain, user-selected as explained above, and
+propagated to the domain.
+
+In addition, a *warm reset* can be initiated from SW through the PCRs for each domain. Exceptions to
+this are the *host domain* (always-on), and the *secure domain* when `secure_boot_i` is asserted.
+
+
+## axi_dma_config / doc / idma_desc64_frontend_doc.md
+
+## Summary
+
+| Name                                  | Offset   |   Length | Description                                                         |
+|:--------------------------------------|:---------|---------:|:--------------------------------------------------------------------|
+| idma_desc64.[`desc_addr`](#desc_addr) | 0x0      |        8 | This register specifies the bus address at which the first transfer |
+| idma_desc64.[`status`](#status)       | 0x8      |        8 | This register contains status information for the DMA.              |
+
+## desc_addr
+This register specifies the bus address at which the first transfer
+descriptor can be found. A write to this register starts the transfer.
+- Offset: `0x0`
+- Reset default: `0xffffffffffffffff`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "desc_addr", "bits": 64, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |       Reset        | Name      | Description   |
+|:------:|:------:|:------------------:|:----------|:--------------|
+|  63:0  |   wo   | 0xffffffffffffffff | desc_addr |               |
+
+## status
+This register contains status information for the DMA.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "fifo_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 62}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  63:2  |        |         |           | Reserved                                                                                                                                                     |
+|   1    |   ro   |   0x0   | fifo_full | If this bit is set, the buffers of the DMA are full. Any further submissions via the desc_addr register may overwrite previously submitted jobs or get lost. |
+|   0    |   ro   |   0x0   | busy      | The DMA is busy                                                                                                                                              |
+
+
+
+## axi_dma_config / doc / idma_reg32_2d_frontend_doc.md
+
+## Summary
+
+| Name                                                         | Offset   |   Length | Description                                                            |
+|:-------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg32_2d_frontend.[`src_addr`](#src_addr)               | 0x0      |        4 | Source Address                                                         |
+| idma_reg32_2d_frontend.[`dst_addr`](#dst_addr)               | 0x4      |        4 | Destination Address                                                    |
+| idma_reg32_2d_frontend.[`num_bytes`](#num_bytes)             | 0x8      |        4 | Number of bytes                                                        |
+| idma_reg32_2d_frontend.[`conf`](#conf)                       | 0xc      |        4 | Configuration Register for DMA settings                                |
+| idma_reg32_2d_frontend.[`stride_src`](#stride_src)           | 0x10     |        4 | Source Stride                                                          |
+| idma_reg32_2d_frontend.[`stride_dst`](#stride_dst)           | 0x14     |        4 | Destination Stride                                                     |
+| idma_reg32_2d_frontend.[`num_repetitions`](#num_repetitions) | 0x18     |        4 | Number of 2D repetitions                                               |
+| idma_reg32_2d_frontend.[`status`](#status)                   | 0x1c     |        4 | DMA Status                                                             |
+| idma_reg32_2d_frontend.[`next_id`](#next_id)                 | 0x20     |        4 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg32_2d_frontend.[`done`](#done)                       | 0x24     |        4 | Get ID of finished transactions.                                       |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  31:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  31:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  31:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "twod", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  31:4  |        |         |           | Reserved         |
+|   3    |   rw   |   0x0   | twod      | 2D transfer      |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## stride_src
+Source Stride
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_src", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   rw   |   0x0   | stride_src | Source Stride |
+
+## stride_dst
+Destination Stride
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_dst", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description        |
+|:------:|:------:|:-------:|:-----------|:-------------------|
+|  31:0  |   rw   |   0x0   | stride_dst | Destination Stride |
+
+## num_repetitions
+Number of 2D repetitions
+- Offset: `0x18`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_repetitions", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description              |
+|:------:|:------:|:-------:|:----------------|:-------------------------|
+|  31:0  |   rw   |   0x1   | num_repetitions | Number of 2D repetitions |
+
+## status
+DMA Status
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+| 31:16  |        |         |        | Reserved      |
+|  15:0  |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  31:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
+
+
+## axi_dma_config / doc / idma_reg64_2d_frontend_doc.md
+
+## Summary
+
+| Name                                                         | Offset   |   Length | Description                                                            |
+|:-------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg64_2d_frontend.[`src_addr`](#src_addr)               | 0x0      |        8 | Source Address                                                         |
+| idma_reg64_2d_frontend.[`dst_addr`](#dst_addr)               | 0x8      |        8 | Destination Address                                                    |
+| idma_reg64_2d_frontend.[`num_bytes`](#num_bytes)             | 0x10     |        8 | Number of bytes                                                        |
+| idma_reg64_2d_frontend.[`conf`](#conf)                       | 0x18     |        8 | Configuration Register for DMA settings                                |
+| idma_reg64_2d_frontend.[`status`](#status)                   | 0x20     |        8 | DMA Status                                                             |
+| idma_reg64_2d_frontend.[`next_id`](#next_id)                 | 0x28     |        8 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg64_2d_frontend.[`done`](#done)                       | 0x30     |        8 | Get ID of finished transactions.                                       |
+| idma_reg64_2d_frontend.[`stride_src`](#stride_src)           | 0x38     |        8 | Source Stride                                                          |
+| idma_reg64_2d_frontend.[`stride_dst`](#stride_dst)           | 0x40     |        8 | Destination Stride                                                     |
+| idma_reg64_2d_frontend.[`num_repetitions`](#num_repetitions) | 0x48     |        8 | Number of 2D repetitions                                               |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  63:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  63:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  63:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 61}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  63:3  |        |         |           | Reserved         |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## status
+DMA Status
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  63:1  |        |         |        | Reserved      |
+|   0    |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  63:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  63:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
+## stride_src
+Source Stride
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_src", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  63:0  |   rw   |   0x0   | stride_src | Source Stride |
+
+## stride_dst
+Destination Stride
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_dst", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description        |
+|:------:|:------:|:-------:|:-----------|:-------------------|
+|  63:0  |   rw   |   0x0   | stride_dst | Destination Stride |
+
+## num_repetitions
+Number of 2D repetitions
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_repetitions", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description              |
+|:------:|:------:|:-------:|:----------------|:-------------------------|
+|  63:0  |   rw   |   0x0   | num_repetitions | Number of 2D repetitions |
+
+
+
+## axi_dma_config / doc / idma_reg64_frontend_doc.md
+
+## Summary
+
+| Name                                          | Offset   |   Length | Description                                                            |
+|:----------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg64_frontend.[`src_addr`](#src_addr)   | 0x0      |        8 | Source Address                                                         |
+| idma_reg64_frontend.[`dst_addr`](#dst_addr)   | 0x8      |        8 | Destination Address                                                    |
+| idma_reg64_frontend.[`num_bytes`](#num_bytes) | 0x10     |        8 | Number of bytes                                                        |
+| idma_reg64_frontend.[`conf`](#conf)           | 0x18     |        8 | Configuration Register for DMA settings                                |
+| idma_reg64_frontend.[`status`](#status)       | 0x20     |        8 | DMA Status                                                             |
+| idma_reg64_frontend.[`next_id`](#next_id)     | 0x28     |        8 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg64_frontend.[`done`](#done)           | 0x30     |        8 | Get ID of finished transactions.                                       |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  63:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  63:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  63:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 61}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  63:3  |        |         |           | Reserved         |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## status
+DMA Status
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  63:1  |        |         |        | Reserved      |
+|   0    |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  63:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  63:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
+
+
+## axi_llc / doc / registers.md
+
+## Summary
+
+| Name                                          | Offset   |   Length | Description                                       |
+|:----------------------------------------------|:---------|---------:|:--------------------------------------------------|
+| axi_llc.[`CFG_SPM_LOW`](#cfg_spm_low)         | 0x0      |        4 | SPM Configuration (lower 32 bit)                  |
+| axi_llc.[`CFG_SPM_HIGH`](#cfg_spm_high)       | 0x4      |        4 | SPM Configuration (upper 32 bit)                  |
+| axi_llc.[`CFG_FLUSH_LOW`](#cfg_flush_low)     | 0x8      |        4 | Flush Configuration (lower 32 bit)                |
+| axi_llc.[`CFG_FLUSH_HIGH`](#cfg_flush_high)   | 0xc      |        4 | Flush Configuration (upper 32 bit)                |
+| axi_llc.[`COMMIT_CFG`](#commit_cfg)           | 0x10     |        4 | Commit the configuration                          |
+| axi_llc.[`FLUSHED_LOW`](#flushed_low)         | 0x18     |        4 | Flushed Flag (lower 32 bit)                       |
+| axi_llc.[`FLUSHED_HIGH`](#flushed_high)       | 0x1c     |        4 | Flushed Flag (upper 32 bit)                       |
+| axi_llc.[`BIST_OUT_LOW`](#bist_out_low)       | 0x20     |        4 | Tag Storage BIST Result (lower 32 bit)            |
+| axi_llc.[`BIST_OUT_HIGH`](#bist_out_high)     | 0x24     |        4 | Tag Storage BIST Result (upper 32 bit)            |
+| axi_llc.[`SET_ASSO_LOW`](#set_asso_low)       | 0x28     |        4 | Instantiated Set-Associativity (lower 32 bit)     |
+| axi_llc.[`SET_ASSO_HIGH`](#set_asso_high)     | 0x2c     |        4 | Instantiated Set-Associativity (upper 32 bit)     |
+| axi_llc.[`NUM_LINES_LOW`](#num_lines_low)     | 0x30     |        4 | Instantiated Number of Cache-Lines (lower 32 bit) |
+| axi_llc.[`NUM_LINES_HIGH`](#num_lines_high)   | 0x34     |        4 | Instantiated Number of Cache-Lines (upper 32 bit) |
+| axi_llc.[`NUM_BLOCKS_LOW`](#num_blocks_low)   | 0x38     |        4 | Instantiated Number of Blocks (lower 32 bit)      |
+| axi_llc.[`NUM_BLOCKS_HIGH`](#num_blocks_high) | 0x3c     |        4 | Instantiated Number of Blocks (upper 32 bit)      |
+| axi_llc.[`VERSION_LOW`](#version_low)         | 0x40     |        4 | AXI LLC Version (lower 32 bit)                    |
+| axi_llc.[`VERSION_HIGH`](#version_high)       | 0x44     |        4 | AXI LLC Version (upper 32 bit)                    |
+| axi_llc.[`BIST_STATUS`](#bist_status)         | 0x48     |        4 | Status register of the BIST                       |
+
+## CFG_SPM_LOW
+SPM Configuration (lower 32 bit)
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | low    | lower 32 bit  |
+
+## CFG_SPM_HIGH
+SPM Configuration (upper 32 bit)
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | high   | upper 32 bit  |
+
+## CFG_FLUSH_LOW
+Flush Configuration (lower 32 bit)
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | low    | lower 32 bit  |
+
+## CFG_FLUSH_HIGH
+Flush Configuration (upper 32 bit)
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | high   | upper 32 bit  |
+
+## COMMIT_CFG
+Commit the configuration
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "commit", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description          |
+|:------:|:------:|:-------:|:-------|:---------------------|
+|  31:1  |        |         |        | Reserved             |
+|   0    |  rw1s  |   0x0   | commit | commit configuration |
+
+## FLUSHED_LOW
+Flushed Flag (lower 32 bit)
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## FLUSHED_HIGH
+Flushed Flag (upper 32 bit)
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## BIST_OUT_LOW
+Tag Storage BIST Result (lower 32 bit)
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## BIST_OUT_HIGH
+Tag Storage BIST Result (upper 32 bit)
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## SET_ASSO_LOW
+Instantiated Set-Associativity (lower 32 bit)
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## SET_ASSO_HIGH
+Instantiated Set-Associativity (upper 32 bit)
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## NUM_LINES_LOW
+Instantiated Number of Cache-Lines (lower 32 bit)
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## NUM_LINES_HIGH
+Instantiated Number of Cache-Lines (upper 32 bit)
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## NUM_BLOCKS_LOW
+Instantiated Number of Blocks (lower 32 bit)
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## NUM_BLOCKS_HIGH
+Instantiated Number of Blocks (upper 32 bit)
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## VERSION_LOW
+AXI LLC Version (lower 32 bit)
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## VERSION_HIGH
+AXI LLC Version (upper 32 bit)
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## BIST_STATUS
+Status register of the BIST
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                 |
+|:------:|:------:|:-------:|:-------|:----------------------------|
+|  31:1  |        |         |        | Reserved                    |
+|   0    |   ro   |   0x0   | done   | BIST successfully completed |
+
+
+
+## axi_realm / doc / registers.md
+
+## Summary
+
+| Name                                                    | Offset   |   Length | Description                                |
+|:--------------------------------------------------------|:---------|---------:|:-------------------------------------------|
+| axi_rt.[`major_version`](#major_version)                | 0x0      |        4 | Value of the major_version.                |
+| axi_rt.[`minor_version`](#minor_version)                | 0x4      |        4 | Value of the minor_version.                |
+| axi_rt.[`patch_version`](#patch_version)                | 0x8      |        4 | Value of the patch_version.                |
+| axi_rt.[`rt_enable`](#rt_enable)                        | 0xc      |        4 | Enable RT feature on master                |
+| axi_rt.[`rt_bypassed`](#rt_bypassed)                    | 0x10     |        4 | Is the RT inactive?                        |
+| axi_rt.[`len_limit_0`](#len_limit_0)                    | 0x14     |        4 | Fragmentation of the bursts in beats.      |
+| axi_rt.[`len_limit_1`](#len_limit_1)                    | 0x18     |        4 | Fragmentation of the bursts in beats.      |
+| axi_rt.[`imtu_enable`](#imtu_enable)                    | 0x1c     |        4 | Enables the IMTU.                          |
+| axi_rt.[`imtu_abort`](#imtu_abort)                      | 0x20     |        4 | Resets both the period and the budget.     |
+| axi_rt.[`start_addr_sub_low_0`](#start_addr_sub_low)    | 0x24     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_1`](#start_addr_sub_low)    | 0x28     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_2`](#start_addr_sub_low)    | 0x2c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_3`](#start_addr_sub_low)    | 0x30     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_4`](#start_addr_sub_low)    | 0x34     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_5`](#start_addr_sub_low)    | 0x38     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_6`](#start_addr_sub_low)    | 0x3c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_7`](#start_addr_sub_low)    | 0x40     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_8`](#start_addr_sub_low)    | 0x44     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_9`](#start_addr_sub_low)    | 0x48     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_10`](#start_addr_sub_low)   | 0x4c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_11`](#start_addr_sub_low)   | 0x50     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_12`](#start_addr_sub_low)   | 0x54     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_13`](#start_addr_sub_low)   | 0x58     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_14`](#start_addr_sub_low)   | 0x5c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_15`](#start_addr_sub_low)   | 0x60     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_high_0`](#start_addr_sub_high)  | 0x64     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_1`](#start_addr_sub_high)  | 0x68     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_2`](#start_addr_sub_high)  | 0x6c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_3`](#start_addr_sub_high)  | 0x70     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_4`](#start_addr_sub_high)  | 0x74     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_5`](#start_addr_sub_high)  | 0x78     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_6`](#start_addr_sub_high)  | 0x7c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_7`](#start_addr_sub_high)  | 0x80     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_8`](#start_addr_sub_high)  | 0x84     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_9`](#start_addr_sub_high)  | 0x88     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_10`](#start_addr_sub_high) | 0x8c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_11`](#start_addr_sub_high) | 0x90     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_12`](#start_addr_sub_high) | 0x94     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_13`](#start_addr_sub_high) | 0x98     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_14`](#start_addr_sub_high) | 0x9c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_15`](#start_addr_sub_high) | 0xa0     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`end_addr_sub_low_0`](#end_addr_sub_low)        | 0xa4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_1`](#end_addr_sub_low)        | 0xa8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_2`](#end_addr_sub_low)        | 0xac     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_3`](#end_addr_sub_low)        | 0xb0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_4`](#end_addr_sub_low)        | 0xb4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_5`](#end_addr_sub_low)        | 0xb8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_6`](#end_addr_sub_low)        | 0xbc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_7`](#end_addr_sub_low)        | 0xc0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_8`](#end_addr_sub_low)        | 0xc4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_9`](#end_addr_sub_low)        | 0xc8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_10`](#end_addr_sub_low)       | 0xcc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_11`](#end_addr_sub_low)       | 0xd0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_12`](#end_addr_sub_low)       | 0xd4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_13`](#end_addr_sub_low)       | 0xd8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_14`](#end_addr_sub_low)       | 0xdc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_15`](#end_addr_sub_low)       | 0xe0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_high_0`](#end_addr_sub_high)      | 0xe4     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_1`](#end_addr_sub_high)      | 0xe8     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_2`](#end_addr_sub_high)      | 0xec     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_3`](#end_addr_sub_high)      | 0xf0     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_4`](#end_addr_sub_high)      | 0xf4     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_5`](#end_addr_sub_high)      | 0xf8     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_6`](#end_addr_sub_high)      | 0xfc     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_7`](#end_addr_sub_high)      | 0x100    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_8`](#end_addr_sub_high)      | 0x104    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_9`](#end_addr_sub_high)      | 0x108    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_10`](#end_addr_sub_high)     | 0x10c    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_11`](#end_addr_sub_high)     | 0x110    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_12`](#end_addr_sub_high)     | 0x114    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_13`](#end_addr_sub_high)     | 0x118    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_14`](#end_addr_sub_high)     | 0x11c    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_15`](#end_addr_sub_high)     | 0x120    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`write_budget_0`](#write_budget)                | 0x124    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_1`](#write_budget)                | 0x128    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_2`](#write_budget)                | 0x12c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_3`](#write_budget)                | 0x130    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_4`](#write_budget)                | 0x134    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_5`](#write_budget)                | 0x138    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_6`](#write_budget)                | 0x13c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_7`](#write_budget)                | 0x140    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_8`](#write_budget)                | 0x144    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_9`](#write_budget)                | 0x148    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_10`](#write_budget)               | 0x14c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_11`](#write_budget)               | 0x150    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_12`](#write_budget)               | 0x154    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_13`](#write_budget)               | 0x158    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_14`](#write_budget)               | 0x15c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_15`](#write_budget)               | 0x160    |        4 | The budget for writes.                     |
+| axi_rt.[`read_budget_0`](#read_budget)                  | 0x164    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_1`](#read_budget)                  | 0x168    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_2`](#read_budget)                  | 0x16c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_3`](#read_budget)                  | 0x170    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_4`](#read_budget)                  | 0x174    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_5`](#read_budget)                  | 0x178    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_6`](#read_budget)                  | 0x17c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_7`](#read_budget)                  | 0x180    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_8`](#read_budget)                  | 0x184    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_9`](#read_budget)                  | 0x188    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_10`](#read_budget)                 | 0x18c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_11`](#read_budget)                 | 0x190    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_12`](#read_budget)                 | 0x194    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_13`](#read_budget)                 | 0x198    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_14`](#read_budget)                 | 0x19c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_15`](#read_budget)                 | 0x1a0    |        4 | The budget for reads.                      |
+| axi_rt.[`write_period_0`](#write_period)                | 0x1a4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_1`](#write_period)                | 0x1a8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_2`](#write_period)                | 0x1ac    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_3`](#write_period)                | 0x1b0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_4`](#write_period)                | 0x1b4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_5`](#write_period)                | 0x1b8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_6`](#write_period)                | 0x1bc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_7`](#write_period)                | 0x1c0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_8`](#write_period)                | 0x1c4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_9`](#write_period)                | 0x1c8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_10`](#write_period)               | 0x1cc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_11`](#write_period)               | 0x1d0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_12`](#write_period)               | 0x1d4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_13`](#write_period)               | 0x1d8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_14`](#write_period)               | 0x1dc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_15`](#write_period)               | 0x1e0    |        4 | The period for writes.                     |
+| axi_rt.[`read_period_0`](#read_period)                  | 0x1e4    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_1`](#read_period)                  | 0x1e8    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_2`](#read_period)                  | 0x1ec    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_3`](#read_period)                  | 0x1f0    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_4`](#read_period)                  | 0x1f4    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_5`](#read_period)                  | 0x1f8    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_6`](#read_period)                  | 0x1fc    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_7`](#read_period)                  | 0x200    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_8`](#read_period)                  | 0x204    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_9`](#read_period)                  | 0x208    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_10`](#read_period)                 | 0x20c    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_11`](#read_period)                 | 0x210    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_12`](#read_period)                 | 0x214    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_13`](#read_period)                 | 0x218    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_14`](#read_period)                 | 0x21c    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_15`](#read_period)                 | 0x220    |        4 | The period for reads.                      |
+| axi_rt.[`write_budget_left_0`](#write_budget_left)      | 0x224    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_1`](#write_budget_left)      | 0x228    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_2`](#write_budget_left)      | 0x22c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_3`](#write_budget_left)      | 0x230    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_4`](#write_budget_left)      | 0x234    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_5`](#write_budget_left)      | 0x238    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_6`](#write_budget_left)      | 0x23c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_7`](#write_budget_left)      | 0x240    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_8`](#write_budget_left)      | 0x244    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_9`](#write_budget_left)      | 0x248    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_10`](#write_budget_left)     | 0x24c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_11`](#write_budget_left)     | 0x250    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_12`](#write_budget_left)     | 0x254    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_13`](#write_budget_left)     | 0x258    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_14`](#write_budget_left)     | 0x25c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_15`](#write_budget_left)     | 0x260    |        4 | The budget left for writes.                |
+| axi_rt.[`read_budget_left_0`](#read_budget_left)        | 0x264    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_1`](#read_budget_left)        | 0x268    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_2`](#read_budget_left)        | 0x26c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_3`](#read_budget_left)        | 0x270    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_4`](#read_budget_left)        | 0x274    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_5`](#read_budget_left)        | 0x278    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_6`](#read_budget_left)        | 0x27c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_7`](#read_budget_left)        | 0x280    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_8`](#read_budget_left)        | 0x284    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_9`](#read_budget_left)        | 0x288    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_10`](#read_budget_left)       | 0x28c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_11`](#read_budget_left)       | 0x290    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_12`](#read_budget_left)       | 0x294    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_13`](#read_budget_left)       | 0x298    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_14`](#read_budget_left)       | 0x29c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_15`](#read_budget_left)       | 0x2a0    |        4 | The budget left for reads.                 |
+| axi_rt.[`write_period_left_0`](#write_period_left)      | 0x2a4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_1`](#write_period_left)      | 0x2a8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_2`](#write_period_left)      | 0x2ac    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_3`](#write_period_left)      | 0x2b0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_4`](#write_period_left)      | 0x2b4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_5`](#write_period_left)      | 0x2b8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_6`](#write_period_left)      | 0x2bc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_7`](#write_period_left)      | 0x2c0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_8`](#write_period_left)      | 0x2c4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_9`](#write_period_left)      | 0x2c8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_10`](#write_period_left)     | 0x2cc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_11`](#write_period_left)     | 0x2d0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_12`](#write_period_left)     | 0x2d4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_13`](#write_period_left)     | 0x2d8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_14`](#write_period_left)     | 0x2dc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_15`](#write_period_left)     | 0x2e0    |        4 | The period left for writes.                |
+| axi_rt.[`read_period_left_0`](#read_period_left)        | 0x2e4    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_1`](#read_period_left)        | 0x2e8    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_2`](#read_period_left)        | 0x2ec    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_3`](#read_period_left)        | 0x2f0    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_4`](#read_period_left)        | 0x2f4    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_5`](#read_period_left)        | 0x2f8    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_6`](#read_period_left)        | 0x2fc    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_7`](#read_period_left)        | 0x300    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_8`](#read_period_left)        | 0x304    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_9`](#read_period_left)        | 0x308    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_10`](#read_period_left)       | 0x30c    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_11`](#read_period_left)       | 0x310    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_12`](#read_period_left)       | 0x314    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_13`](#read_period_left)       | 0x318    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_14`](#read_period_left)       | 0x31c    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_15`](#read_period_left)       | 0x320    |        4 | The period left for reads.                 |
+| axi_rt.[`isolate`](#isolate)                            | 0x324    |        4 | Is the interface requested to be isolated? |
+| axi_rt.[`isolated`](#isolated)                          | 0x328    |        4 | Is the interface isolated?                 |
+| axi_rt.[`num_managers`](#num_managers)                  | 0x32c    |        4 | Value of the num_managers parameter.       |
+| axi_rt.[`addr_width`](#addr_width)                      | 0x330    |        4 | Value of the addr_width parameter.         |
+| axi_rt.[`data_width`](#data_width)                      | 0x334    |        4 | Value of the data_width parameter.         |
+| axi_rt.[`id_width`](#id_width)                          | 0x338    |        4 | Value of the id_width parameter.           |
+| axi_rt.[`user_width`](#user_width)                      | 0x33c    |        4 | Value of the user_width parameter.         |
+| axi_rt.[`num_pending`](#num_pending)                    | 0x340    |        4 | Value of the num_pending parameter.        |
+| axi_rt.[`w_buffer_depth`](#w_buffer_depth)              | 0x344    |        4 | Value of the w_buffer_depth parameter.     |
+| axi_rt.[`num_addr_regions`](#num_addr_regions)          | 0x348    |        4 | Value of the num_addr_regions parameter.   |
+| axi_rt.[`period_width`](#period_width)                  | 0x34c    |        4 | Value of the period_width parameter.       |
+| axi_rt.[`budget_width`](#budget_width)                  | 0x350    |        4 | Value of the budget_width parameter.       |
+| axi_rt.[`max_num_managers`](#max_num_managers)          | 0x354    |        4 | Value of the max_num_managers parameter.   |
+
+## major_version
+Value of the major_version.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "major_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | major_version | Value of the major_version. |
+
+## minor_version
+Value of the minor_version.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "minor_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | minor_version | Value of the minor_version. |
+
+## patch_version
+Value of the patch_version.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "patch_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | patch_version | Value of the patch_version. |
+
+## rt_enable
+Enable RT feature on master
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                 |
+|:------:|:------:|:-------:|:---------|:----------------------------|
+|  31:8  |        |         |          | Reserved                    |
+|   7    |   wo   |   0x0   | enable_7 | Enable RT feature on master |
+|   6    |   wo   |   0x0   | enable_6 | Enable RT feature on master |
+|   5    |   wo   |   0x0   | enable_5 | Enable RT feature on master |
+|   4    |   wo   |   0x0   | enable_4 | Enable RT feature on master |
+|   3    |   wo   |   0x0   | enable_3 | Enable RT feature on master |
+|   2    |   wo   |   0x0   | enable_2 | Enable RT feature on master |
+|   1    |   wo   |   0x0   | enable_1 | Enable RT feature on master |
+|   0    |   wo   |   0x0   | enable_0 | Enable RT feature on master |
+
+## rt_bypassed
+Is the RT inactive?
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypassed_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description         |
+|:------:|:------:|:-------:|:-----------|:--------------------|
+|  31:8  |        |         |            | Reserved            |
+|   7    |   ro   |    x    | bypassed_7 | Is the RT inactive? |
+|   6    |   ro   |    x    | bypassed_6 | Is the RT inactive? |
+|   5    |   ro   |    x    | bypassed_5 | Is the RT inactive? |
+|   4    |   ro   |    x    | bypassed_4 | Is the RT inactive? |
+|   3    |   ro   |    x    | bypassed_3 | Is the RT inactive? |
+|   2    |   ro   |    x    | bypassed_2 | Is the RT inactive? |
+|   1    |   ro   |    x    | bypassed_1 | Is the RT inactive? |
+|   0    |   ro   |    x    | bypassed_0 | Is the RT inactive? |
+
+## len_limit_0
+Fragmentation of the bursts in beats.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "len_0", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_1", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_2", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_3", "bits": 8, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------|
+| 31:24  |   wo   |   0x0   | len_3  | Fragmentation of the bursts in beats. |
+| 23:16  |   wo   |   0x0   | len_2  | Fragmentation of the bursts in beats. |
+|  15:8  |   wo   |   0x0   | len_1  | Fragmentation of the bursts in beats. |
+|  7:0   |   wo   |   0x0   | len_0  | Fragmentation of the bursts in beats. |
+
+## len_limit_1
+Fragmentation of the bursts in beats.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "len_4", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_5", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_6", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_7", "bits": 8, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description    |
+|:------:|:------:|:-------:|:-------|:---------------|
+| 31:24  |   wo   |   0x0   | len_7  | For len_limit1 |
+| 23:16  |   wo   |   0x0   | len_6  | For len_limit1 |
+|  15:8  |   wo   |   0x0   | len_5  | For len_limit1 |
+|  7:0   |   wo   |   0x0   | len_4  | For len_limit1 |
+
+## imtu_enable
+Enables the IMTU.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description       |
+|:------:|:------:|:-------:|:---------|:------------------|
+|  31:8  |        |         |          | Reserved          |
+|   7    |   wo   |   0x0   | enable_7 | Enables the IMTU. |
+|   6    |   wo   |   0x0   | enable_6 | Enables the IMTU. |
+|   5    |   wo   |   0x0   | enable_5 | Enables the IMTU. |
+|   4    |   wo   |   0x0   | enable_4 | Enables the IMTU. |
+|   3    |   wo   |   0x0   | enable_3 | Enables the IMTU. |
+|   2    |   wo   |   0x0   | enable_2 | Enables the IMTU. |
+|   1    |   wo   |   0x0   | enable_1 | Enables the IMTU. |
+|   0    |   wo   |   0x0   | enable_0 | Enables the IMTU. |
+
+## imtu_abort
+Resets both the period and the budget.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "abort_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                            |
+|:------:|:------:|:-------:|:--------|:---------------------------------------|
+|  31:8  |        |         |         | Reserved                               |
+|   7    |   wo   |   0x0   | abort_7 | Resets both the period and the budget. |
+|   6    |   wo   |   0x0   | abort_6 | Resets both the period and the budget. |
+|   5    |   wo   |   0x0   | abort_5 | Resets both the period and the budget. |
+|   4    |   wo   |   0x0   | abort_4 | Resets both the period and the budget. |
+|   3    |   wo   |   0x0   | abort_3 | Resets both the period and the budget. |
+|   2    |   wo   |   0x0   | abort_2 | Resets both the period and the budget. |
+|   1    |   wo   |   0x0   | abort_1 | Resets both the period and the budget. |
+|   0    |   wo   |   0x0   | abort_0 | Resets both the period and the budget. |
+
+## start_addr_sub_low
+The lower 32bit of the start address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                  | Offset   |
+|:----------------------|:---------|
+| start_addr_sub_low_0  | 0x24     |
+| start_addr_sub_low_1  | 0x28     |
+| start_addr_sub_low_2  | 0x2c     |
+| start_addr_sub_low_3  | 0x30     |
+| start_addr_sub_low_4  | 0x34     |
+| start_addr_sub_low_5  | 0x38     |
+| start_addr_sub_low_6  | 0x3c     |
+| start_addr_sub_low_7  | 0x40     |
+| start_addr_sub_low_8  | 0x44     |
+| start_addr_sub_low_9  | 0x48     |
+| start_addr_sub_low_10 | 0x4c     |
+| start_addr_sub_low_11 | 0x50     |
+| start_addr_sub_low_12 | 0x54     |
+| start_addr_sub_low_13 | 0x58     |
+| start_addr_sub_low_14 | 0x5c     |
+| start_addr_sub_low_15 | 0x60     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                           |
+|:------:|:------:|:-------:|:-------------|:--------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The lower 32bit of the start address. |
+
+## start_addr_sub_high
+The higher 32bit of the start address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                   | Offset   |
+|:-----------------------|:---------|
+| start_addr_sub_high_0  | 0x64     |
+| start_addr_sub_high_1  | 0x68     |
+| start_addr_sub_high_2  | 0x6c     |
+| start_addr_sub_high_3  | 0x70     |
+| start_addr_sub_high_4  | 0x74     |
+| start_addr_sub_high_5  | 0x78     |
+| start_addr_sub_high_6  | 0x7c     |
+| start_addr_sub_high_7  | 0x80     |
+| start_addr_sub_high_8  | 0x84     |
+| start_addr_sub_high_9  | 0x88     |
+| start_addr_sub_high_10 | 0x8c     |
+| start_addr_sub_high_11 | 0x90     |
+| start_addr_sub_high_12 | 0x94     |
+| start_addr_sub_high_13 | 0x98     |
+| start_addr_sub_high_14 | 0x9c     |
+| start_addr_sub_high_15 | 0xa0     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                            |
+|:------:|:------:|:-------:|:-------------|:---------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The higher 32bit of the start address. |
+
+## end_addr_sub_low
+The lower 32bit of the end address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| end_addr_sub_low_0  | 0xa4     |
+| end_addr_sub_low_1  | 0xa8     |
+| end_addr_sub_low_2  | 0xac     |
+| end_addr_sub_low_3  | 0xb0     |
+| end_addr_sub_low_4  | 0xb4     |
+| end_addr_sub_low_5  | 0xb8     |
+| end_addr_sub_low_6  | 0xbc     |
+| end_addr_sub_low_7  | 0xc0     |
+| end_addr_sub_low_8  | 0xc4     |
+| end_addr_sub_low_9  | 0xc8     |
+| end_addr_sub_low_10 | 0xcc     |
+| end_addr_sub_low_11 | 0xd0     |
+| end_addr_sub_low_12 | 0xd4     |
+| end_addr_sub_low_13 | 0xd8     |
+| end_addr_sub_low_14 | 0xdc     |
+| end_addr_sub_low_15 | 0xe0     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                         |
+|:------:|:------:|:-------:|:-------------|:------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The lower 32bit of the end address. |
+
+## end_addr_sub_high
+The higher 32bit of the end address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| end_addr_sub_high_0  | 0xe4     |
+| end_addr_sub_high_1  | 0xe8     |
+| end_addr_sub_high_2  | 0xec     |
+| end_addr_sub_high_3  | 0xf0     |
+| end_addr_sub_high_4  | 0xf4     |
+| end_addr_sub_high_5  | 0xf8     |
+| end_addr_sub_high_6  | 0xfc     |
+| end_addr_sub_high_7  | 0x100    |
+| end_addr_sub_high_8  | 0x104    |
+| end_addr_sub_high_9  | 0x108    |
+| end_addr_sub_high_10 | 0x10c    |
+| end_addr_sub_high_11 | 0x110    |
+| end_addr_sub_high_12 | 0x114    |
+| end_addr_sub_high_13 | 0x118    |
+| end_addr_sub_high_14 | 0x11c    |
+| end_addr_sub_high_15 | 0x120    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The higher 32bit of the end address. |
+
+## write_budget
+The budget for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name            | Offset   |
+|:----------------|:---------|
+| write_budget_0  | 0x124    |
+| write_budget_1  | 0x128    |
+| write_budget_2  | 0x12c    |
+| write_budget_3  | 0x130    |
+| write_budget_4  | 0x134    |
+| write_budget_5  | 0x138    |
+| write_budget_6  | 0x13c    |
+| write_budget_7  | 0x140    |
+| write_budget_8  | 0x144    |
+| write_budget_9  | 0x148    |
+| write_budget_10 | 0x14c    |
+| write_budget_11 | 0x150    |
+| write_budget_12 | 0x154    |
+| write_budget_13 | 0x158    |
+| write_budget_14 | 0x15c    |
+| write_budget_15 | 0x160    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description            |
+|:------:|:------:|:-------:|:-------------|:-----------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The budget for writes. |
+
+## read_budget
+The budget for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| read_budget_0  | 0x164    |
+| read_budget_1  | 0x168    |
+| read_budget_2  | 0x16c    |
+| read_budget_3  | 0x170    |
+| read_budget_4  | 0x174    |
+| read_budget_5  | 0x178    |
+| read_budget_6  | 0x17c    |
+| read_budget_7  | 0x180    |
+| read_budget_8  | 0x184    |
+| read_budget_9  | 0x188    |
+| read_budget_10 | 0x18c    |
+| read_budget_11 | 0x190    |
+| read_budget_12 | 0x194    |
+| read_budget_13 | 0x198    |
+| read_budget_14 | 0x19c    |
+| read_budget_15 | 0x1a0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description           |
+|:------:|:------:|:-------:|:------------|:----------------------|
+|  31:0  |   wo   |   0x0   | read_budget | The budget for reads. |
+
+## write_period
+The period for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name            | Offset   |
+|:----------------|:---------|
+| write_period_0  | 0x1a4    |
+| write_period_1  | 0x1a8    |
+| write_period_2  | 0x1ac    |
+| write_period_3  | 0x1b0    |
+| write_period_4  | 0x1b4    |
+| write_period_5  | 0x1b8    |
+| write_period_6  | 0x1bc    |
+| write_period_7  | 0x1c0    |
+| write_period_8  | 0x1c4    |
+| write_period_9  | 0x1c8    |
+| write_period_10 | 0x1cc    |
+| write_period_11 | 0x1d0    |
+| write_period_12 | 0x1d4    |
+| write_period_13 | 0x1d8    |
+| write_period_14 | 0x1dc    |
+| write_period_15 | 0x1e0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_period", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description            |
+|:------:|:------:|:-------:|:-------------|:-----------------------|
+|  31:0  |   wo   |   0x0   | write_period | The period for writes. |
+
+## read_period
+The period for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| read_period_0  | 0x1e4    |
+| read_period_1  | 0x1e8    |
+| read_period_2  | 0x1ec    |
+| read_period_3  | 0x1f0    |
+| read_period_4  | 0x1f4    |
+| read_period_5  | 0x1f8    |
+| read_period_6  | 0x1fc    |
+| read_period_7  | 0x200    |
+| read_period_8  | 0x204    |
+| read_period_9  | 0x208    |
+| read_period_10 | 0x20c    |
+| read_period_11 | 0x210    |
+| read_period_12 | 0x214    |
+| read_period_13 | 0x218    |
+| read_period_14 | 0x21c    |
+| read_period_15 | 0x220    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_period", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description           |
+|:------:|:------:|:-------:|:------------|:----------------------|
+|  31:0  |   wo   |   0x0   | read_period | The period for reads. |
+
+## write_budget_left
+The budget left for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| write_budget_left_0  | 0x224    |
+| write_budget_left_1  | 0x228    |
+| write_budget_left_2  | 0x22c    |
+| write_budget_left_3  | 0x230    |
+| write_budget_left_4  | 0x234    |
+| write_budget_left_5  | 0x238    |
+| write_budget_left_6  | 0x23c    |
+| write_budget_left_7  | 0x240    |
+| write_budget_left_8  | 0x244    |
+| write_budget_left_9  | 0x248    |
+| write_budget_left_10 | 0x24c    |
+| write_budget_left_11 | 0x250    |
+| write_budget_left_12 | 0x254    |
+| write_budget_left_13 | 0x258    |
+| write_budget_left_14 | 0x25c    |
+| write_budget_left_15 | 0x260    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                 |
+|:------:|:------:|:-------:|:------------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | write_budget_left | The budget left for writes. |
+
+## read_budget_left
+The budget left for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| read_budget_left_0  | 0x264    |
+| read_budget_left_1  | 0x268    |
+| read_budget_left_2  | 0x26c    |
+| read_budget_left_3  | 0x270    |
+| read_budget_left_4  | 0x274    |
+| read_budget_left_5  | 0x278    |
+| read_budget_left_6  | 0x27c    |
+| read_budget_left_7  | 0x280    |
+| read_budget_left_8  | 0x284    |
+| read_budget_left_9  | 0x288    |
+| read_budget_left_10 | 0x28c    |
+| read_budget_left_11 | 0x290    |
+| read_budget_left_12 | 0x294    |
+| read_budget_left_13 | 0x298    |
+| read_budget_left_14 | 0x29c    |
+| read_budget_left_15 | 0x2a0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_budget_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------|
+|  31:0  |   ro   |   0x0   | read_budget_left | The budget left for reads. |
+
+## write_period_left
+The period left for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| write_period_left_0  | 0x2a4    |
+| write_period_left_1  | 0x2a8    |
+| write_period_left_2  | 0x2ac    |
+| write_period_left_3  | 0x2b0    |
+| write_period_left_4  | 0x2b4    |
+| write_period_left_5  | 0x2b8    |
+| write_period_left_6  | 0x2bc    |
+| write_period_left_7  | 0x2c0    |
+| write_period_left_8  | 0x2c4    |
+| write_period_left_9  | 0x2c8    |
+| write_period_left_10 | 0x2cc    |
+| write_period_left_11 | 0x2d0    |
+| write_period_left_12 | 0x2d4    |
+| write_period_left_13 | 0x2d8    |
+| write_period_left_14 | 0x2dc    |
+| write_period_left_15 | 0x2e0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_period_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                 |
+|:------:|:------:|:-------:|:------------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | write_period_left | The period left for writes. |
+
+## read_period_left
+The period left for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| read_period_left_0  | 0x2e4    |
+| read_period_left_1  | 0x2e8    |
+| read_period_left_2  | 0x2ec    |
+| read_period_left_3  | 0x2f0    |
+| read_period_left_4  | 0x2f4    |
+| read_period_left_5  | 0x2f8    |
+| read_period_left_6  | 0x2fc    |
+| read_period_left_7  | 0x300    |
+| read_period_left_8  | 0x304    |
+| read_period_left_9  | 0x308    |
+| read_period_left_10 | 0x30c    |
+| read_period_left_11 | 0x310    |
+| read_period_left_12 | 0x314    |
+| read_period_left_13 | 0x318    |
+| read_period_left_14 | 0x31c    |
+| read_period_left_15 | 0x320    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_period_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------|
+|  31:0  |   ro   |   0x0   | read_period_left | The period left for reads. |
+
+## isolate
+Is the interface requested to be isolated?
+- Offset: `0x324`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "isolate_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------|
+|  31:8  |        |         |           | Reserved                                   |
+|   7    |   ro   |    x    | isolate_7 | Is the interface requested to be isolated? |
+|   6    |   ro   |    x    | isolate_6 | Is the interface requested to be isolated? |
+|   5    |   ro   |    x    | isolate_5 | Is the interface requested to be isolated? |
+|   4    |   ro   |    x    | isolate_4 | Is the interface requested to be isolated? |
+|   3    |   ro   |    x    | isolate_3 | Is the interface requested to be isolated? |
+|   2    |   ro   |    x    | isolate_2 | Is the interface requested to be isolated? |
+|   1    |   ro   |    x    | isolate_1 | Is the interface requested to be isolated? |
+|   0    |   ro   |    x    | isolate_0 | Is the interface requested to be isolated? |
+
+## isolated
+Is the interface isolated?
+- Offset: `0x328`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "isolated_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                |
+|:------:|:------:|:-------:|:-----------|:---------------------------|
+|  31:8  |        |         |            | Reserved                   |
+|   7    |   ro   |    x    | isolated_7 | Is the interface isolated? |
+|   6    |   ro   |    x    | isolated_6 | Is the interface isolated? |
+|   5    |   ro   |    x    | isolated_5 | Is the interface isolated? |
+|   4    |   ro   |    x    | isolated_4 | Is the interface isolated? |
+|   3    |   ro   |    x    | isolated_3 | Is the interface isolated? |
+|   2    |   ro   |    x    | isolated_2 | Is the interface isolated? |
+|   1    |   ro   |    x    | isolated_1 | Is the interface isolated? |
+|   0    |   ro   |    x    | isolated_0 | Is the interface isolated? |
+
+## num_managers
+Value of the num_managers parameter.
+- Offset: `0x32c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_managers", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | num_managers | Value of the num_managers parameter. |
+
+## addr_width
+Value of the addr_width parameter.
+- Offset: `0x330`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "addr_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | addr_width | Value of the addr_width parameter. |
+
+## data_width
+Value of the data_width parameter.
+- Offset: `0x334`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | data_width | Value of the data_width parameter. |
+
+## id_width
+Value of the id_width parameter.
+- Offset: `0x338`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "id_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                      |
+|:------:|:------:|:-------:|:---------|:---------------------------------|
+|  31:0  |   ro   |    x    | id_width | Value of the id_width parameter. |
+
+## user_width
+Value of the user_width parameter.
+- Offset: `0x33c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "user_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | user_width | Value of the user_width parameter. |
+
+## num_pending
+Value of the num_pending parameter.
+- Offset: `0x340`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_pending", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                         |
+|:------:|:------:|:-------:|:------------|:------------------------------------|
+|  31:0  |   ro   |    x    | num_pending | Value of the num_pending parameter. |
+
+## w_buffer_depth
+Value of the w_buffer_depth parameter.
+- Offset: `0x344`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "w_buffer_depth", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                            |
+|:------:|:------:|:-------:|:---------------|:---------------------------------------|
+|  31:0  |   ro   |    x    | w_buffer_depth | Value of the w_buffer_depth parameter. |
+
+## num_addr_regions
+Value of the num_addr_regions parameter.
+- Offset: `0x348`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_addr_regions", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                              |
+|:------:|:------:|:-------:|:-----------------|:-----------------------------------------|
+|  31:0  |   ro   |    x    | num_addr_regions | Value of the num_addr_regions parameter. |
+
+## period_width
+Value of the period_width parameter.
+- Offset: `0x34c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "period_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | period_width | Value of the period_width parameter. |
+
+## budget_width
+Value of the budget_width parameter.
+- Offset: `0x350`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "budget_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | budget_width | Value of the budget_width parameter. |
+
+## max_num_managers
+Value of the max_num_managers parameter.
+- Offset: `0x354`
+- Reset default: `0x8`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "max_num_managers", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                              |
+|:------:|:------:|:-------:|:-----------------|:-----------------------------------------|
+|  31:0  |   ro   |   0x8   | max_num_managers | Value of the max_num_managers parameter. |
+
+
+
+## can_bus / doc / registers.md
+
+## Summary
+
+| Name                                                                                                          | Offset   |   Length | Description                                                                    |
+|:--------------------------------------------------------------------------------------------------------------|:---------|---------:|:-------------------------------------------------------------------------------|
+| can_bus.[`ahb_ifc_hsel_valid`](#ahb_ifc_hsel_valid)                                                           | 0x0      |        4 | Auto-extracted signal hsel_valid from ahb_ifc.vhd                              |
+| can_bus.[`ahb_ifc_write_acc_d`](#ahb_ifc_write_acc_d)                                                         | 0x4      |        4 | Auto-extracted signal write_acc_d from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_write_acc_q`](#ahb_ifc_write_acc_q)                                                         | 0x8      |        4 | Auto-extracted signal write_acc_q from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_haddr_q`](#ahb_ifc_haddr_q)                                                                 | 0xc      |        4 | Auto-extracted signal haddr_q from ahb_ifc.vhd                                 |
+| can_bus.[`ahb_ifc_h_ready_raw`](#ahb_ifc_h_ready_raw)                                                         | 0x10     |        4 | Auto-extracted signal h_ready_raw from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_sbe_d`](#ahb_ifc_sbe_d)                                                                     | 0x14     |        4 | Auto-extracted signal sbe_d from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_sbe_q`](#ahb_ifc_sbe_q)                                                                     | 0x18     |        4 | Auto-extracted signal sbe_q from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_swr_i`](#ahb_ifc_swr_i)                                                                     | 0x1c     |        4 | Auto-extracted signal swr_i from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_srd_i`](#ahb_ifc_srd_i)                                                                     | 0x20     |        4 | Auto-extracted signal srd_i from ahb_ifc.vhd                                   |
+| can_bus.[`bit_destuffing_discard_stuff_bit`](#bit_destuffing_discard_stuff_bit)                               | 0x24     |        4 | Auto-extracted signal discard_stuff_bit from bit_destuffing.vhd                |
+| can_bus.[`bit_destuffing_non_fix_to_fix_chng`](#bit_destuffing_non_fix_to_fix_chng)                           | 0x28     |        4 | Auto-extracted signal non_fix_to_fix_chng from bit_destuffing.vhd              |
+| can_bus.[`bit_destuffing_stuff_lvl_reached`](#bit_destuffing_stuff_lvl_reached)                               | 0x2c     |        4 | Auto-extracted signal stuff_lvl_reached from bit_destuffing.vhd                |
+| can_bus.[`bit_destuffing_stuff_rule_violate`](#bit_destuffing_stuff_rule_violate)                             | 0x30     |        4 | Auto-extracted signal stuff_rule_violate from bit_destuffing.vhd               |
+| can_bus.[`bit_destuffing_enable_prev`](#bit_destuffing_enable_prev)                                           | 0x34     |        4 | Auto-extracted signal enable_prev from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_fixed_prev_q`](#bit_destuffing_fixed_prev_q)                                         | 0x38     |        4 | Auto-extracted signal fixed_prev_q from bit_destuffing.vhd                     |
+| can_bus.[`bit_destuffing_fixed_prev_d`](#bit_destuffing_fixed_prev_d)                                         | 0x3c     |        4 | Auto-extracted signal fixed_prev_d from bit_destuffing.vhd                     |
+| can_bus.[`bit_destuffing_same_bits_erase`](#bit_destuffing_same_bits_erase)                                   | 0x40     |        4 | Auto-extracted signal same_bits_erase from bit_destuffing.vhd                  |
+| can_bus.[`bit_destuffing_destuffed_q`](#bit_destuffing_destuffed_q)                                           | 0x44     |        4 | Auto-extracted signal destuffed_q from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_destuffed_d`](#bit_destuffing_destuffed_d)                                           | 0x48     |        4 | Auto-extracted signal destuffed_d from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_stuff_err_q`](#bit_destuffing_stuff_err_q)                                           | 0x4c     |        4 | Auto-extracted signal stuff_err_q from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_stuff_err_d`](#bit_destuffing_stuff_err_d)                                           | 0x50     |        4 | Auto-extracted signal stuff_err_d from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_prev_val_q`](#bit_destuffing_prev_val_q)                                             | 0x54     |        4 | Auto-extracted signal prev_val_q from bit_destuffing.vhd                       |
+| can_bus.[`bit_destuffing_prev_val_d`](#bit_destuffing_prev_val_d)                                             | 0x58     |        4 | Auto-extracted signal prev_val_d from bit_destuffing.vhd                       |
+| can_bus.[`bit_err_detector_bit_err_d`](#bit_err_detector_bit_err_d)                                           | 0x5c     |        4 | Auto-extracted signal bit_err_d from bit_err_detector.vhd                      |
+| can_bus.[`bit_err_detector_bit_err_q`](#bit_err_detector_bit_err_q)                                           | 0x60     |        4 | Auto-extracted signal bit_err_q from bit_err_detector.vhd                      |
+| can_bus.[`bit_err_detector_bit_err_ssp_capt_d`](#bit_err_detector_bit_err_ssp_capt_d)                         | 0x64     |        4 | Auto-extracted signal bit_err_ssp_capt_d from bit_err_detector.vhd             |
+| can_bus.[`bit_err_detector_bit_err_ssp_capt_q`](#bit_err_detector_bit_err_ssp_capt_q)                         | 0x68     |        4 | Auto-extracted signal bit_err_ssp_capt_q from bit_err_detector.vhd             |
+| can_bus.[`bit_err_detector_bit_err_ssp_valid`](#bit_err_detector_bit_err_ssp_valid)                           | 0x6c     |        4 | Auto-extracted signal bit_err_ssp_valid from bit_err_detector.vhd              |
+| can_bus.[`bit_err_detector_bit_err_ssp_condition`](#bit_err_detector_bit_err_ssp_condition)                   | 0x70     |        4 | Auto-extracted signal bit_err_ssp_condition from bit_err_detector.vhd          |
+| can_bus.[`bit_err_detector_bit_err_norm_valid`](#bit_err_detector_bit_err_norm_valid)                         | 0x74     |        4 | Auto-extracted signal bit_err_norm_valid from bit_err_detector.vhd             |
+| can_bus.[`bit_filter_masked_input`](#bit_filter_masked_input)                                                 | 0x78     |        4 | Auto-extracted signal masked_input from bit_filter.vhd                         |
+| can_bus.[`bit_filter_masked_value`](#bit_filter_masked_value)                                                 | 0x7c     |        4 | Auto-extracted signal masked_value from bit_filter.vhd                         |
+| can_bus.[`bit_segment_meter_sel_tseg1`](#bit_segment_meter_sel_tseg1)                                         | 0x80     |        4 | Auto-extracted signal sel_tseg1 from bit_segment_meter.vhd                     |
+| can_bus.[`bit_segment_meter_exp_seg_length_ce`](#bit_segment_meter_exp_seg_length_ce)                         | 0x84     |        4 | Auto-extracted signal exp_seg_length_ce from bit_segment_meter.vhd             |
+| can_bus.[`bit_segment_meter_phase_err_mt_sjw`](#bit_segment_meter_phase_err_mt_sjw)                           | 0x88     |        4 | Auto-extracted signal phase_err_mt_sjw from bit_segment_meter.vhd              |
+| can_bus.[`bit_segment_meter_phase_err_eq_sjw`](#bit_segment_meter_phase_err_eq_sjw)                           | 0x8c     |        4 | Auto-extracted signal phase_err_eq_sjw from bit_segment_meter.vhd              |
+| can_bus.[`bit_segment_meter_exit_ph2_immediate`](#bit_segment_meter_exit_ph2_immediate)                       | 0x90     |        4 | Auto-extracted signal exit_ph2_immediate from bit_segment_meter.vhd            |
+| can_bus.[`bit_segment_meter_exit_segm_regular`](#bit_segment_meter_exit_segm_regular)                         | 0x94     |        4 | Auto-extracted signal exit_segm_regular from bit_segment_meter.vhd             |
+| can_bus.[`bit_segment_meter_exit_segm_regular_tseg1`](#bit_segment_meter_exit_segm_regular_tseg1)             | 0x98     |        4 | Auto-extracted signal exit_segm_regular_tseg1 from bit_segment_meter.vhd       |
+| can_bus.[`bit_segment_meter_exit_segm_regular_tseg2`](#bit_segment_meter_exit_segm_regular_tseg2)             | 0x9c     |        4 | Auto-extracted signal exit_segm_regular_tseg2 from bit_segment_meter.vhd       |
+| can_bus.[`bit_segment_meter_sjw_mt_zero`](#bit_segment_meter_sjw_mt_zero)                                     | 0xa0     |        4 | Auto-extracted signal sjw_mt_zero from bit_segment_meter.vhd                   |
+| can_bus.[`bit_segment_meter_use_basic_segm_length`](#bit_segment_meter_use_basic_segm_length)                 | 0xa4     |        4 | Auto-extracted signal use_basic_segm_length from bit_segment_meter.vhd         |
+| can_bus.[`bit_segment_meter_phase_err_sjw_by_one`](#bit_segment_meter_phase_err_sjw_by_one)                   | 0xa8     |        4 | Auto-extracted signal phase_err_sjw_by_one from bit_segment_meter.vhd          |
+| can_bus.[`bit_segment_meter_shorten_tseg1_after_tseg2`](#bit_segment_meter_shorten_tseg1_after_tseg2)         | 0xac     |        4 | Auto-extracted signal shorten_tseg1_after_tseg2 from bit_segment_meter.vhd     |
+| can_bus.[`bit_stuffing_data_out_i`](#bit_stuffing_data_out_i)                                                 | 0xb0     |        4 | Auto-extracted signal data_out_i from bit_stuffing.vhd                         |
+| can_bus.[`bit_stuffing_data_halt_q`](#bit_stuffing_data_halt_q)                                               | 0xb4     |        4 | Auto-extracted signal data_halt_q from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_data_halt_d`](#bit_stuffing_data_halt_d)                                               | 0xb8     |        4 | Auto-extracted signal data_halt_d from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_fixed_reg_q`](#bit_stuffing_fixed_reg_q)                                               | 0xbc     |        4 | Auto-extracted signal fixed_reg_q from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_fixed_reg_d`](#bit_stuffing_fixed_reg_d)                                               | 0xc0     |        4 | Auto-extracted signal fixed_reg_d from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_enable_prev`](#bit_stuffing_enable_prev)                                               | 0xc4     |        4 | Auto-extracted signal enable_prev from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_non_fix_to_fix_chng`](#bit_stuffing_non_fix_to_fix_chng)                               | 0xc8     |        4 | Auto-extracted signal non_fix_to_fix_chng from bit_stuffing.vhd                |
+| can_bus.[`bit_stuffing_stuff_lvl_reached`](#bit_stuffing_stuff_lvl_reached)                                   | 0xcc     |        4 | Auto-extracted signal stuff_lvl_reached from bit_stuffing.vhd                  |
+| can_bus.[`bit_stuffing_same_bits_rst_trig`](#bit_stuffing_same_bits_rst_trig)                                 | 0xd0     |        4 | Auto-extracted signal same_bits_rst_trig from bit_stuffing.vhd                 |
+| can_bus.[`bit_stuffing_same_bits_rst`](#bit_stuffing_same_bits_rst)                                           | 0xd4     |        4 | Auto-extracted signal same_bits_rst from bit_stuffing.vhd                      |
+| can_bus.[`bit_stuffing_insert_stuff_bit`](#bit_stuffing_insert_stuff_bit)                                     | 0xd8     |        4 | Auto-extracted signal insert_stuff_bit from bit_stuffing.vhd                   |
+| can_bus.[`bit_stuffing_data_out_d_ena`](#bit_stuffing_data_out_d_ena)                                         | 0xdc     |        4 | Auto-extracted signal data_out_d_ena from bit_stuffing.vhd                     |
+| can_bus.[`bit_stuffing_data_out_d`](#bit_stuffing_data_out_d)                                                 | 0xe0     |        4 | Auto-extracted signal data_out_d from bit_stuffing.vhd                         |
+| can_bus.[`bit_stuffing_data_out_ce`](#bit_stuffing_data_out_ce)                                               | 0xe4     |        4 | Auto-extracted signal data_out_ce from bit_stuffing.vhd                        |
+| can_bus.[`bit_time_cfg_capture_drv_tq_nbt`](#bit_time_cfg_capture_drv_tq_nbt)                                 | 0xe8     |        4 | Auto-extracted signal drv_tq_nbt from bit_time_cfg_capture.vhd                 |
+| can_bus.[`bit_time_cfg_capture_drv_prs_nbt`](#bit_time_cfg_capture_drv_prs_nbt)                               | 0xec     |        4 | Auto-extracted signal drv_prs_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph1_nbt`](#bit_time_cfg_capture_drv_ph1_nbt)                               | 0xf0     |        4 | Auto-extracted signal drv_ph1_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph2_nbt`](#bit_time_cfg_capture_drv_ph2_nbt)                               | 0xf4     |        4 | Auto-extracted signal drv_ph2_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_sjw_nbt`](#bit_time_cfg_capture_drv_sjw_nbt)                               | 0xf8     |        4 | Auto-extracted signal drv_sjw_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_tq_dbt`](#bit_time_cfg_capture_drv_tq_dbt)                                 | 0xfc     |        4 | Auto-extracted signal drv_tq_dbt from bit_time_cfg_capture.vhd                 |
+| can_bus.[`bit_time_cfg_capture_drv_prs_dbt`](#bit_time_cfg_capture_drv_prs_dbt)                               | 0x100    |        4 | Auto-extracted signal drv_prs_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph1_dbt`](#bit_time_cfg_capture_drv_ph1_dbt)                               | 0x104    |        4 | Auto-extracted signal drv_ph1_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph2_dbt`](#bit_time_cfg_capture_drv_ph2_dbt)                               | 0x108    |        4 | Auto-extracted signal drv_ph2_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_sjw_dbt`](#bit_time_cfg_capture_drv_sjw_dbt)                               | 0x10c    |        4 | Auto-extracted signal drv_sjw_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_tseg1_nbt_d`](#bit_time_cfg_capture_tseg1_nbt_d)                               | 0x110    |        4 | Auto-extracted signal tseg1_nbt_d from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_tseg1_dbt_d`](#bit_time_cfg_capture_tseg1_dbt_d)                               | 0x114    |        4 | Auto-extracted signal tseg1_dbt_d from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ena`](#bit_time_cfg_capture_drv_ena)                                       | 0x118    |        4 | Auto-extracted signal drv_ena from bit_time_cfg_capture.vhd                    |
+| can_bus.[`bit_time_cfg_capture_drv_ena_reg`](#bit_time_cfg_capture_drv_ena_reg)                               | 0x11c    |        4 | Auto-extracted signal drv_ena_reg from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ena_reg_2`](#bit_time_cfg_capture_drv_ena_reg_2)                           | 0x120    |        4 | Auto-extracted signal drv_ena_reg_2 from bit_time_cfg_capture.vhd              |
+| can_bus.[`bit_time_cfg_capture_capture`](#bit_time_cfg_capture_capture)                                       | 0x124    |        4 | Auto-extracted signal capture from bit_time_cfg_capture.vhd                    |
+| can_bus.[`bit_time_counters_tq_counter_d`](#bit_time_counters_tq_counter_d)                                   | 0x128    |        4 | Auto-extracted signal tq_counter_d from bit_time_counters.vhd                  |
+| can_bus.[`bit_time_counters_tq_counter_q`](#bit_time_counters_tq_counter_q)                                   | 0x12c    |        4 | Auto-extracted signal tq_counter_q from bit_time_counters.vhd                  |
+| can_bus.[`bit_time_counters_tq_counter_ce`](#bit_time_counters_tq_counter_ce)                                 | 0x130    |        4 | Auto-extracted signal tq_counter_ce from bit_time_counters.vhd                 |
+| can_bus.[`bit_time_counters_tq_counter_allow`](#bit_time_counters_tq_counter_allow)                           | 0x134    |        4 | Auto-extracted signal tq_counter_allow from bit_time_counters.vhd              |
+| can_bus.[`bit_time_counters_tq_edge_i`](#bit_time_counters_tq_edge_i)                                         | 0x138    |        4 | Auto-extracted signal tq_edge_i from bit_time_counters.vhd                     |
+| can_bus.[`bit_time_counters_segm_counter_d`](#bit_time_counters_segm_counter_d)                               | 0x13c    |        4 | Auto-extracted signal segm_counter_d from bit_time_counters.vhd                |
+| can_bus.[`bit_time_counters_segm_counter_q`](#bit_time_counters_segm_counter_q)                               | 0x140    |        4 | Auto-extracted signal segm_counter_q from bit_time_counters.vhd                |
+| can_bus.[`bit_time_counters_segm_counter_ce`](#bit_time_counters_segm_counter_ce)                             | 0x144    |        4 | Auto-extracted signal segm_counter_ce from bit_time_counters.vhd               |
+| can_bus.[`bit_time_fsm_bt_fsm_ce`](#bit_time_fsm_bt_fsm_ce)                                                   | 0x148    |        4 | Auto-extracted signal bt_fsm_ce from bit_time_fsm.vhd                          |
+| can_bus.[`bus_sampling_drv_ena`](#bus_sampling_drv_ena)                                                       | 0x14c    |        4 | Auto-extracted signal drv_ena from bus_sampling.vhd                            |
+| can_bus.[`bus_sampling_drv_ssp_offset`](#bus_sampling_drv_ssp_offset)                                         | 0x150    |        4 | Auto-extracted signal drv_ssp_offset from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_drv_ssp_delay_select`](#bus_sampling_drv_ssp_delay_select)                             | 0x154    |        4 | Auto-extracted signal drv_ssp_delay_select from bus_sampling.vhd               |
+| can_bus.[`bus_sampling_data_rx_synced`](#bus_sampling_data_rx_synced)                                         | 0x158    |        4 | Auto-extracted signal data_rx_synced from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_prev_Sample`](#bus_sampling_prev_sample)                                               | 0x15c    |        4 | Auto-extracted signal prev_Sample from bus_sampling.vhd                        |
+| can_bus.[`bus_sampling_sample_sec_i`](#bus_sampling_sample_sec_i)                                             | 0x160    |        4 | Auto-extracted signal sample_sec_i from bus_sampling.vhd                       |
+| can_bus.[`bus_sampling_data_tx_delayed`](#bus_sampling_data_tx_delayed)                                       | 0x164    |        4 | Auto-extracted signal data_tx_delayed from bus_sampling.vhd                    |
+| can_bus.[`bus_sampling_edge_rx_valid`](#bus_sampling_edge_rx_valid)                                           | 0x168    |        4 | Auto-extracted signal edge_rx_valid from bus_sampling.vhd                      |
+| can_bus.[`bus_sampling_edge_tx_valid`](#bus_sampling_edge_tx_valid)                                           | 0x16c    |        4 | Auto-extracted signal edge_tx_valid from bus_sampling.vhd                      |
+| can_bus.[`bus_sampling_ssp_delay`](#bus_sampling_ssp_delay)                                                   | 0x170    |        4 | Auto-extracted signal ssp_delay from bus_sampling.vhd                          |
+| can_bus.[`bus_sampling_tx_trigger_q`](#bus_sampling_tx_trigger_q)                                             | 0x174    |        4 | Auto-extracted signal tx_trigger_q from bus_sampling.vhd                       |
+| can_bus.[`bus_sampling_tx_trigger_ssp`](#bus_sampling_tx_trigger_ssp)                                         | 0x178    |        4 | Auto-extracted signal tx_trigger_ssp from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_shift_regs_res_d`](#bus_sampling_shift_regs_res_d)                                     | 0x17c    |        4 | Auto-extracted signal shift_regs_res_d from bus_sampling.vhd                   |
+| can_bus.[`bus_sampling_shift_regs_res_q`](#bus_sampling_shift_regs_res_q)                                     | 0x180    |        4 | Auto-extracted signal shift_regs_res_q from bus_sampling.vhd                   |
+| can_bus.[`bus_sampling_shift_regs_res_q_scan`](#bus_sampling_shift_regs_res_q_scan)                           | 0x184    |        4 | Auto-extracted signal shift_regs_res_q_scan from bus_sampling.vhd              |
+| can_bus.[`bus_sampling_ssp_enable`](#bus_sampling_ssp_enable)                                                 | 0x188    |        4 | Auto-extracted signal ssp_enable from bus_sampling.vhd                         |
+| can_bus.[`bus_traffic_counters_tx_ctr_i`](#bus_traffic_counters_tx_ctr_i)                                     | 0x18c    |        4 | Auto-extracted signal tx_ctr_i from bus_traffic_counters.vhd                   |
+| can_bus.[`bus_traffic_counters_rx_ctr_i`](#bus_traffic_counters_rx_ctr_i)                                     | 0x190    |        4 | Auto-extracted signal rx_ctr_i from bus_traffic_counters.vhd                   |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_d`](#bus_traffic_counters_tx_ctr_rst_n_d)                         | 0x194    |        4 | Auto-extracted signal tx_ctr_rst_n_d from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_q`](#bus_traffic_counters_tx_ctr_rst_n_q)                         | 0x198    |        4 | Auto-extracted signal tx_ctr_rst_n_q from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_q_scan`](#bus_traffic_counters_tx_ctr_rst_n_q_scan)               | 0x19c    |        4 | Auto-extracted signal tx_ctr_rst_n_q_scan from bus_traffic_counters.vhd        |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_d`](#bus_traffic_counters_rx_ctr_rst_n_d)                         | 0x1a0    |        4 | Auto-extracted signal rx_ctr_rst_n_d from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_q`](#bus_traffic_counters_rx_ctr_rst_n_q)                         | 0x1a4    |        4 | Auto-extracted signal rx_ctr_rst_n_q from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_q_scan`](#bus_traffic_counters_rx_ctr_rst_n_q_scan)               | 0x1a8    |        4 | Auto-extracted signal rx_ctr_rst_n_q_scan from bus_traffic_counters.vhd        |
+| can_bus.[`can_apb_tb_s_apb_paddr`](#can_apb_tb_s_apb_paddr)                                                   | 0x1ac    |        4 | Auto-extracted signal s_apb_paddr from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_penable`](#can_apb_tb_s_apb_penable)                                               | 0x1b0    |        4 | Auto-extracted signal s_apb_penable from can_apb_tb.vhd                        |
+| can_bus.[`can_apb_tb_s_apb_pprot`](#can_apb_tb_s_apb_pprot)                                                   | 0x1b4    |        4 | Auto-extracted signal s_apb_pprot from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_prdata`](#can_apb_tb_s_apb_prdata)                                                 | 0x1b8    |        4 | Auto-extracted signal s_apb_prdata from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_pready`](#can_apb_tb_s_apb_pready)                                                 | 0x1bc    |        4 | Auto-extracted signal s_apb_pready from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_psel`](#can_apb_tb_s_apb_psel)                                                     | 0x1c0    |        4 | Auto-extracted signal s_apb_psel from can_apb_tb.vhd                           |
+| can_bus.[`can_apb_tb_s_apb_pslverr`](#can_apb_tb_s_apb_pslverr)                                               | 0x1c4    |        4 | Auto-extracted signal s_apb_pslverr from can_apb_tb.vhd                        |
+| can_bus.[`can_apb_tb_s_apb_pstrb`](#can_apb_tb_s_apb_pstrb)                                                   | 0x1c8    |        4 | Auto-extracted signal s_apb_pstrb from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_pwdata`](#can_apb_tb_s_apb_pwdata)                                                 | 0x1cc    |        4 | Auto-extracted signal s_apb_pwdata from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_pwrite`](#can_apb_tb_s_apb_pwrite)                                                 | 0x1d0    |        4 | Auto-extracted signal s_apb_pwrite from can_apb_tb.vhd                         |
+| can_bus.[`can_core_drv_clr_rx_ctr`](#can_core_drv_clr_rx_ctr)                                                 | 0x1d4    |        4 | Auto-extracted signal drv_clr_rx_ctr from can_core.vhd                         |
+| can_bus.[`can_core_drv_clr_tx_ctr`](#can_core_drv_clr_tx_ctr)                                                 | 0x1d8    |        4 | Auto-extracted signal drv_clr_tx_ctr from can_core.vhd                         |
+| can_bus.[`can_core_drv_bus_mon_ena`](#can_core_drv_bus_mon_ena)                                               | 0x1dc    |        4 | Auto-extracted signal drv_bus_mon_ena from can_core.vhd                        |
+| can_bus.[`can_core_drv_ena`](#can_core_drv_ena)                                                               | 0x1e0    |        4 | Auto-extracted signal drv_ena from can_core.vhd                                |
+| can_bus.[`can_core_rec_ident_i`](#can_core_rec_ident_i)                                                       | 0x1e4    |        4 | Auto-extracted signal rec_ident_i from can_core.vhd                            |
+| can_bus.[`can_core_rec_dlc_i`](#can_core_rec_dlc_i)                                                           | 0x1e8    |        4 | Auto-extracted signal rec_dlc_i from can_core.vhd                              |
+| can_bus.[`can_core_rec_ident_type_i`](#can_core_rec_ident_type_i)                                             | 0x1ec    |        4 | Auto-extracted signal rec_ident_type_i from can_core.vhd                       |
+| can_bus.[`can_core_rec_frame_type_i`](#can_core_rec_frame_type_i)                                             | 0x1f0    |        4 | Auto-extracted signal rec_frame_type_i from can_core.vhd                       |
+| can_bus.[`can_core_rec_is_rtr_i`](#can_core_rec_is_rtr_i)                                                     | 0x1f4    |        4 | Auto-extracted signal rec_is_rtr_i from can_core.vhd                           |
+| can_bus.[`can_core_rec_brs_i`](#can_core_rec_brs_i)                                                           | 0x1f8    |        4 | Auto-extracted signal rec_brs_i from can_core.vhd                              |
+| can_bus.[`can_core_rec_esi_i`](#can_core_rec_esi_i)                                                           | 0x1fc    |        4 | Auto-extracted signal rec_esi_i from can_core.vhd                              |
+| can_bus.[`can_core_alc`](#can_core_alc)                                                                       | 0x200    |        4 | Auto-extracted signal alc from can_core.vhd                                    |
+| can_bus.[`can_core_erc_capture`](#can_core_erc_capture)                                                       | 0x204    |        4 | Auto-extracted signal erc_capture from can_core.vhd                            |
+| can_bus.[`can_core_is_transmitter`](#can_core_is_transmitter)                                                 | 0x208    |        4 | Auto-extracted signal is_transmitter from can_core.vhd                         |
+| can_bus.[`can_core_is_receiver`](#can_core_is_receiver)                                                       | 0x20c    |        4 | Auto-extracted signal is_receiver from can_core.vhd                            |
+| can_bus.[`can_core_is_idle`](#can_core_is_idle)                                                               | 0x210    |        4 | Auto-extracted signal is_idle from can_core.vhd                                |
+| can_bus.[`can_core_arbitration_lost_i`](#can_core_arbitration_lost_i)                                         | 0x214    |        4 | Auto-extracted signal arbitration_lost_i from can_core.vhd                     |
+| can_bus.[`can_core_set_transmitter`](#can_core_set_transmitter)                                               | 0x218    |        4 | Auto-extracted signal set_transmitter from can_core.vhd                        |
+| can_bus.[`can_core_set_receiver`](#can_core_set_receiver)                                                     | 0x21c    |        4 | Auto-extracted signal set_receiver from can_core.vhd                           |
+| can_bus.[`can_core_set_idle`](#can_core_set_idle)                                                             | 0x220    |        4 | Auto-extracted signal set_idle from can_core.vhd                               |
+| can_bus.[`can_core_is_err_active`](#can_core_is_err_active)                                                   | 0x224    |        4 | Auto-extracted signal is_err_active from can_core.vhd                          |
+| can_bus.[`can_core_is_err_passive`](#can_core_is_err_passive)                                                 | 0x228    |        4 | Auto-extracted signal is_err_passive from can_core.vhd                         |
+| can_bus.[`can_core_is_bus_off_i`](#can_core_is_bus_off_i)                                                     | 0x22c    |        4 | Auto-extracted signal is_bus_off_i from can_core.vhd                           |
+| can_bus.[`can_core_err_detected_i`](#can_core_err_detected_i)                                                 | 0x230    |        4 | Auto-extracted signal err_detected_i from can_core.vhd                         |
+| can_bus.[`can_core_primary_err`](#can_core_primary_err)                                                       | 0x234    |        4 | Auto-extracted signal primary_err from can_core.vhd                            |
+| can_bus.[`can_core_act_err_ovr_flag`](#can_core_act_err_ovr_flag)                                             | 0x238    |        4 | Auto-extracted signal act_err_ovr_flag from can_core.vhd                       |
+| can_bus.[`can_core_err_delim_late`](#can_core_err_delim_late)                                                 | 0x23c    |        4 | Auto-extracted signal err_delim_late from can_core.vhd                         |
+| can_bus.[`can_core_set_err_active`](#can_core_set_err_active)                                                 | 0x240    |        4 | Auto-extracted signal set_err_active from can_core.vhd                         |
+| can_bus.[`can_core_err_ctrs_unchanged`](#can_core_err_ctrs_unchanged)                                         | 0x244    |        4 | Auto-extracted signal err_ctrs_unchanged from can_core.vhd                     |
+| can_bus.[`can_core_stuff_enable`](#can_core_stuff_enable)                                                     | 0x248    |        4 | Auto-extracted signal stuff_enable from can_core.vhd                           |
+| can_bus.[`can_core_destuff_enable`](#can_core_destuff_enable)                                                 | 0x24c    |        4 | Auto-extracted signal destuff_enable from can_core.vhd                         |
+| can_bus.[`can_core_fixed_stuff`](#can_core_fixed_stuff)                                                       | 0x250    |        4 | Auto-extracted signal fixed_stuff from can_core.vhd                            |
+| can_bus.[`can_core_tx_frame_no_sof`](#can_core_tx_frame_no_sof)                                               | 0x254    |        4 | Auto-extracted signal tx_frame_no_sof from can_core.vhd                        |
+| can_bus.[`can_core_stuff_length`](#can_core_stuff_length)                                                     | 0x258    |        4 | Auto-extracted signal stuff_length from can_core.vhd                           |
+| can_bus.[`can_core_dst_ctr`](#can_core_dst_ctr)                                                               | 0x25c    |        4 | Auto-extracted signal dst_ctr from can_core.vhd                                |
+| can_bus.[`can_core_bst_ctr`](#can_core_bst_ctr)                                                               | 0x260    |        4 | Auto-extracted signal bst_ctr from can_core.vhd                                |
+| can_bus.[`can_core_stuff_err`](#can_core_stuff_err)                                                           | 0x264    |        4 | Auto-extracted signal stuff_err from can_core.vhd                              |
+| can_bus.[`can_core_crc_enable`](#can_core_crc_enable)                                                         | 0x268    |        4 | Auto-extracted signal crc_enable from can_core.vhd                             |
+| can_bus.[`can_core_crc_spec_enable`](#can_core_crc_spec_enable)                                               | 0x26c    |        4 | Auto-extracted signal crc_spec_enable from can_core.vhd                        |
+| can_bus.[`can_core_crc_calc_from_rx`](#can_core_crc_calc_from_rx)                                             | 0x270    |        4 | Auto-extracted signal crc_calc_from_rx from can_core.vhd                       |
+| can_bus.[`can_core_crc_15`](#can_core_crc_15)                                                                 | 0x274    |        4 | Auto-extracted signal crc_15 from can_core.vhd                                 |
+| can_bus.[`can_core_crc_17`](#can_core_crc_17)                                                                 | 0x278    |        4 | Auto-extracted signal crc_17 from can_core.vhd                                 |
+| can_bus.[`can_core_crc_21`](#can_core_crc_21)                                                                 | 0x27c    |        4 | Auto-extracted signal crc_21 from can_core.vhd                                 |
+| can_bus.[`can_core_sp_control_i`](#can_core_sp_control_i)                                                     | 0x280    |        4 | Auto-extracted signal sp_control_i from can_core.vhd                           |
+| can_bus.[`can_core_sp_control_q`](#can_core_sp_control_q)                                                     | 0x284    |        4 | Auto-extracted signal sp_control_q from can_core.vhd                           |
+| can_bus.[`can_core_sync_control_i`](#can_core_sync_control_i)                                                 | 0x288    |        4 | Auto-extracted signal sync_control_i from can_core.vhd                         |
+| can_bus.[`can_core_ssp_reset_i`](#can_core_ssp_reset_i)                                                       | 0x28c    |        4 | Auto-extracted signal ssp_reset_i from can_core.vhd                            |
+| can_bus.[`can_core_tran_delay_meas_i`](#can_core_tran_delay_meas_i)                                           | 0x290    |        4 | Auto-extracted signal tran_delay_meas_i from can_core.vhd                      |
+| can_bus.[`can_core_tran_valid_i`](#can_core_tran_valid_i)                                                     | 0x294    |        4 | Auto-extracted signal tran_valid_i from can_core.vhd                           |
+| can_bus.[`can_core_rec_valid_i`](#can_core_rec_valid_i)                                                       | 0x298    |        4 | Auto-extracted signal rec_valid_i from can_core.vhd                            |
+| can_bus.[`can_core_br_shifted_i`](#can_core_br_shifted_i)                                                     | 0x29c    |        4 | Auto-extracted signal br_shifted_i from can_core.vhd                           |
+| can_bus.[`can_core_fcs_changed_i`](#can_core_fcs_changed_i)                                                   | 0x2a0    |        4 | Auto-extracted signal fcs_changed_i from can_core.vhd                          |
+| can_bus.[`can_core_err_warning_limit_i`](#can_core_err_warning_limit_i)                                       | 0x2a4    |        4 | Auto-extracted signal err_warning_limit_i from can_core.vhd                    |
+| can_bus.[`can_core_tx_err_ctr`](#can_core_tx_err_ctr)                                                         | 0x2a8    |        4 | Auto-extracted signal tx_err_ctr from can_core.vhd                             |
+| can_bus.[`can_core_rx_err_ctr`](#can_core_rx_err_ctr)                                                         | 0x2ac    |        4 | Auto-extracted signal rx_err_ctr from can_core.vhd                             |
+| can_bus.[`can_core_norm_err_ctr`](#can_core_norm_err_ctr)                                                     | 0x2b0    |        4 | Auto-extracted signal norm_err_ctr from can_core.vhd                           |
+| can_bus.[`can_core_data_err_ctr`](#can_core_data_err_ctr)                                                     | 0x2b4    |        4 | Auto-extracted signal data_err_ctr from can_core.vhd                           |
+| can_bus.[`can_core_pc_tx_trigger`](#can_core_pc_tx_trigger)                                                   | 0x2b8    |        4 | Auto-extracted signal pc_tx_trigger from can_core.vhd                          |
+| can_bus.[`can_core_pc_rx_trigger`](#can_core_pc_rx_trigger)                                                   | 0x2bc    |        4 | Auto-extracted signal pc_rx_trigger from can_core.vhd                          |
+| can_bus.[`can_core_pc_tx_data_nbs`](#can_core_pc_tx_data_nbs)                                                 | 0x2c0    |        4 | Auto-extracted signal pc_tx_data_nbs from can_core.vhd                         |
+| can_bus.[`can_core_pc_rx_data_nbs`](#can_core_pc_rx_data_nbs)                                                 | 0x2c4    |        4 | Auto-extracted signal pc_rx_data_nbs from can_core.vhd                         |
+| can_bus.[`can_core_crc_data_tx_wbs`](#can_core_crc_data_tx_wbs)                                               | 0x2c8    |        4 | Auto-extracted signal crc_data_tx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_tx_nbs`](#can_core_crc_data_tx_nbs)                                               | 0x2cc    |        4 | Auto-extracted signal crc_data_tx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_rx_wbs`](#can_core_crc_data_rx_wbs)                                               | 0x2d0    |        4 | Auto-extracted signal crc_data_rx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_rx_nbs`](#can_core_crc_data_rx_nbs)                                               | 0x2d4    |        4 | Auto-extracted signal crc_data_rx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_tx_wbs`](#can_core_crc_trig_tx_wbs)                                               | 0x2d8    |        4 | Auto-extracted signal crc_trig_tx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_tx_nbs`](#can_core_crc_trig_tx_nbs)                                               | 0x2dc    |        4 | Auto-extracted signal crc_trig_tx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_rx_wbs`](#can_core_crc_trig_rx_wbs)                                               | 0x2e0    |        4 | Auto-extracted signal crc_trig_rx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_rx_nbs`](#can_core_crc_trig_rx_nbs)                                               | 0x2e4    |        4 | Auto-extracted signal crc_trig_rx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_bst_data_in`](#can_core_bst_data_in)                                                       | 0x2e8    |        4 | Auto-extracted signal bst_data_in from can_core.vhd                            |
+| can_bus.[`can_core_bst_data_out`](#can_core_bst_data_out)                                                     | 0x2ec    |        4 | Auto-extracted signal bst_data_out from can_core.vhd                           |
+| can_bus.[`can_core_bst_trigger`](#can_core_bst_trigger)                                                       | 0x2f0    |        4 | Auto-extracted signal bst_trigger from can_core.vhd                            |
+| can_bus.[`can_core_data_halt`](#can_core_data_halt)                                                           | 0x2f4    |        4 | Auto-extracted signal data_halt from can_core.vhd                              |
+| can_bus.[`can_core_bds_data_in`](#can_core_bds_data_in)                                                       | 0x2f8    |        4 | Auto-extracted signal bds_data_in from can_core.vhd                            |
+| can_bus.[`can_core_bds_data_out`](#can_core_bds_data_out)                                                     | 0x2fc    |        4 | Auto-extracted signal bds_data_out from can_core.vhd                           |
+| can_bus.[`can_core_bds_trigger`](#can_core_bds_trigger)                                                       | 0x300    |        4 | Auto-extracted signal bds_trigger from can_core.vhd                            |
+| can_bus.[`can_core_destuffed`](#can_core_destuffed)                                                           | 0x304    |        4 | Auto-extracted signal destuffed from can_core.vhd                              |
+| can_bus.[`can_core_tx_ctr`](#can_core_tx_ctr)                                                                 | 0x308    |        4 | Auto-extracted signal tx_ctr from can_core.vhd                                 |
+| can_bus.[`can_core_rx_ctr`](#can_core_rx_ctr)                                                                 | 0x30c    |        4 | Auto-extracted signal rx_ctr from can_core.vhd                                 |
+| can_bus.[`can_core_tx_data_wbs_i`](#can_core_tx_data_wbs_i)                                                   | 0x310    |        4 | Auto-extracted signal tx_data_wbs_i from can_core.vhd                          |
+| can_bus.[`can_core_lpb_dominant`](#can_core_lpb_dominant)                                                     | 0x314    |        4 | Auto-extracted signal lpb_dominant from can_core.vhd                           |
+| can_bus.[`can_core_form_err`](#can_core_form_err)                                                             | 0x318    |        4 | Auto-extracted signal form_err from can_core.vhd                               |
+| can_bus.[`can_core_ack_err`](#can_core_ack_err)                                                               | 0x31c    |        4 | Auto-extracted signal ack_err from can_core.vhd                                |
+| can_bus.[`can_core_crc_err`](#can_core_crc_err)                                                               | 0x320    |        4 | Auto-extracted signal crc_err from can_core.vhd                                |
+| can_bus.[`can_core_is_arbitration`](#can_core_is_arbitration)                                                 | 0x324    |        4 | Auto-extracted signal is_arbitration from can_core.vhd                         |
+| can_bus.[`can_core_is_control`](#can_core_is_control)                                                         | 0x328    |        4 | Auto-extracted signal is_control from can_core.vhd                             |
+| can_bus.[`can_core_is_data`](#can_core_is_data)                                                               | 0x32c    |        4 | Auto-extracted signal is_data from can_core.vhd                                |
+| can_bus.[`can_core_is_stuff_count`](#can_core_is_stuff_count)                                                 | 0x330    |        4 | Auto-extracted signal is_stuff_count from can_core.vhd                         |
+| can_bus.[`can_core_is_crc`](#can_core_is_crc)                                                                 | 0x334    |        4 | Auto-extracted signal is_crc from can_core.vhd                                 |
+| can_bus.[`can_core_is_crc_delim`](#can_core_is_crc_delim)                                                     | 0x338    |        4 | Auto-extracted signal is_crc_delim from can_core.vhd                           |
+| can_bus.[`can_core_is_ack_field`](#can_core_is_ack_field)                                                     | 0x33c    |        4 | Auto-extracted signal is_ack_field from can_core.vhd                           |
+| can_bus.[`can_core_is_ack_delim`](#can_core_is_ack_delim)                                                     | 0x340    |        4 | Auto-extracted signal is_ack_delim from can_core.vhd                           |
+| can_bus.[`can_core_is_eof`](#can_core_is_eof)                                                                 | 0x344    |        4 | Auto-extracted signal is_eof from can_core.vhd                                 |
+| can_bus.[`can_core_is_err_frm`](#can_core_is_err_frm)                                                         | 0x348    |        4 | Auto-extracted signal is_err_frm from can_core.vhd                             |
+| can_bus.[`can_core_is_intermission`](#can_core_is_intermission)                                               | 0x34c    |        4 | Auto-extracted signal is_intermission from can_core.vhd                        |
+| can_bus.[`can_core_is_suspend`](#can_core_is_suspend)                                                         | 0x350    |        4 | Auto-extracted signal is_suspend from can_core.vhd                             |
+| can_bus.[`can_core_is_overload_i`](#can_core_is_overload_i)                                                   | 0x354    |        4 | Auto-extracted signal is_overload_i from can_core.vhd                          |
+| can_bus.[`can_core_is_sof`](#can_core_is_sof)                                                                 | 0x358    |        4 | Auto-extracted signal is_sof from can_core.vhd                                 |
+| can_bus.[`can_core_sof_pulse_i`](#can_core_sof_pulse_i)                                                       | 0x35c    |        4 | Auto-extracted signal sof_pulse_i from can_core.vhd                            |
+| can_bus.[`can_core_load_init_vect`](#can_core_load_init_vect)                                                 | 0x360    |        4 | Auto-extracted signal load_init_vect from can_core.vhd                         |
+| can_bus.[`can_core_retr_ctr_i`](#can_core_retr_ctr_i)                                                         | 0x364    |        4 | Auto-extracted signal retr_ctr_i from can_core.vhd                             |
+| can_bus.[`can_core_decrement_rec`](#can_core_decrement_rec)                                                   | 0x368    |        4 | Auto-extracted signal decrement_rec from can_core.vhd                          |
+| can_bus.[`can_core_bit_err_after_ack_err`](#can_core_bit_err_after_ack_err)                                   | 0x36c    |        4 | Auto-extracted signal bit_err_after_ack_err from can_core.vhd                  |
+| can_bus.[`can_core_is_pexs`](#can_core_is_pexs)                                                               | 0x370    |        4 | Auto-extracted signal is_pexs from can_core.vhd                                |
+| can_bus.[`can_crc_drv_fd_type`](#can_crc_drv_fd_type)                                                         | 0x374    |        4 | Auto-extracted signal drv_fd_type from can_crc.vhd                             |
+| can_bus.[`can_crc_init_vect_15`](#can_crc_init_vect_15)                                                       | 0x378    |        4 | Auto-extracted signal init_vect_15 from can_crc.vhd                            |
+| can_bus.[`can_crc_init_vect_17`](#can_crc_init_vect_17)                                                       | 0x37c    |        4 | Auto-extracted signal init_vect_17 from can_crc.vhd                            |
+| can_bus.[`can_crc_init_vect_21`](#can_crc_init_vect_21)                                                       | 0x380    |        4 | Auto-extracted signal init_vect_21 from can_crc.vhd                            |
+| can_bus.[`can_crc_crc_17_21_data_in`](#can_crc_crc_17_21_data_in)                                             | 0x384    |        4 | Auto-extracted signal crc_17_21_data_in from can_crc.vhd                       |
+| can_bus.[`can_crc_crc_17_21_trigger`](#can_crc_crc_17_21_trigger)                                             | 0x388    |        4 | Auto-extracted signal crc_17_21_trigger from can_crc.vhd                       |
+| can_bus.[`can_crc_crc_15_data_in`](#can_crc_crc_15_data_in)                                                   | 0x38c    |        4 | Auto-extracted signal crc_15_data_in from can_crc.vhd                          |
+| can_bus.[`can_crc_crc_15_trigger`](#can_crc_crc_15_trigger)                                                   | 0x390    |        4 | Auto-extracted signal crc_15_trigger from can_crc.vhd                          |
+| can_bus.[`can_crc_crc_ena_15`](#can_crc_crc_ena_15)                                                           | 0x394    |        4 | Auto-extracted signal crc_ena_15 from can_crc.vhd                              |
+| can_bus.[`can_crc_crc_ena_17_21`](#can_crc_crc_ena_17_21)                                                     | 0x398    |        4 | Auto-extracted signal crc_ena_17_21 from can_crc.vhd                           |
+| can_bus.[`can_top_ahb_ctu_can_data_in`](#can_top_ahb_ctu_can_data_in)                                         | 0x39c    |        4 | Auto-extracted signal ctu_can_data_in from can_top_ahb.vhd                     |
+| can_bus.[`can_top_ahb_ctu_can_data_out`](#can_top_ahb_ctu_can_data_out)                                       | 0x3a0    |        4 | Auto-extracted signal ctu_can_data_out from can_top_ahb.vhd                    |
+| can_bus.[`can_top_ahb_ctu_can_adress`](#can_top_ahb_ctu_can_adress)                                           | 0x3a4    |        4 | Auto-extracted signal ctu_can_adress from can_top_ahb.vhd                      |
+| can_bus.[`can_top_ahb_ctu_can_scs`](#can_top_ahb_ctu_can_scs)                                                 | 0x3a8    |        4 | Auto-extracted signal ctu_can_scs from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_srd`](#can_top_ahb_ctu_can_srd)                                                 | 0x3ac    |        4 | Auto-extracted signal ctu_can_srd from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_swr`](#can_top_ahb_ctu_can_swr)                                                 | 0x3b0    |        4 | Auto-extracted signal ctu_can_swr from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_sbe`](#can_top_ahb_ctu_can_sbe)                                                 | 0x3b4    |        4 | Auto-extracted signal ctu_can_sbe from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_res_n_out_i`](#can_top_ahb_res_n_out_i)                                                 | 0x3b8    |        4 | Auto-extracted signal res_n_out_i from can_top_ahb.vhd                         |
+| can_bus.[`can_top_apb_reg_data_in`](#can_top_apb_reg_data_in)                                                 | 0x3bc    |        4 | Auto-extracted signal reg_data_in from can_top_apb.vhd                         |
+| can_bus.[`can_top_apb_reg_data_out`](#can_top_apb_reg_data_out)                                               | 0x3c0    |        4 | Auto-extracted signal reg_data_out from can_top_apb.vhd                        |
+| can_bus.[`can_top_apb_reg_addr`](#can_top_apb_reg_addr)                                                       | 0x3c4    |        4 | Auto-extracted signal reg_addr from can_top_apb.vhd                            |
+| can_bus.[`can_top_apb_reg_be`](#can_top_apb_reg_be)                                                           | 0x3c8    |        4 | Auto-extracted signal reg_be from can_top_apb.vhd                              |
+| can_bus.[`can_top_apb_reg_rden`](#can_top_apb_reg_rden)                                                       | 0x3cc    |        4 | Auto-extracted signal reg_rden from can_top_apb.vhd                            |
+| can_bus.[`can_top_apb_reg_wren`](#can_top_apb_reg_wren)                                                       | 0x3d0    |        4 | Auto-extracted signal reg_wren from can_top_apb.vhd                            |
+| can_bus.[`can_top_level_drv_bus`](#can_top_level_drv_bus)                                                     | 0x3d4    |        4 | Auto-extracted signal drv_bus from can_top_level.vhd                           |
+| can_bus.[`can_top_level_stat_bus`](#can_top_level_stat_bus)                                                   | 0x3d8    |        4 | Auto-extracted signal stat_bus from can_top_level.vhd                          |
+| can_bus.[`can_top_level_res_n_sync`](#can_top_level_res_n_sync)                                               | 0x3dc    |        4 | Auto-extracted signal res_n_sync from can_top_level.vhd                        |
+| can_bus.[`can_top_level_res_core_n`](#can_top_level_res_core_n)                                               | 0x3e0    |        4 | Auto-extracted signal res_core_n from can_top_level.vhd                        |
+| can_bus.[`can_top_level_res_soft_n`](#can_top_level_res_soft_n)                                               | 0x3e4    |        4 | Auto-extracted signal res_soft_n from can_top_level.vhd                        |
+| can_bus.[`can_top_level_sp_control`](#can_top_level_sp_control)                                               | 0x3e8    |        4 | Auto-extracted signal sp_control from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rx_buf_size`](#can_top_level_rx_buf_size)                                             | 0x3ec    |        4 | Auto-extracted signal rx_buf_size from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_full`](#can_top_level_rx_full)                                                     | 0x3f0    |        4 | Auto-extracted signal rx_full from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rx_empty`](#can_top_level_rx_empty)                                                   | 0x3f4    |        4 | Auto-extracted signal rx_empty from can_top_level.vhd                          |
+| can_bus.[`can_top_level_rx_frame_count`](#can_top_level_rx_frame_count)                                       | 0x3f8    |        4 | Auto-extracted signal rx_frame_count from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rx_mem_free`](#can_top_level_rx_mem_free)                                             | 0x3fc    |        4 | Auto-extracted signal rx_mem_free from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_read_pointer`](#can_top_level_rx_read_pointer)                                     | 0x400    |        4 | Auto-extracted signal rx_read_pointer from can_top_level.vhd                   |
+| can_bus.[`can_top_level_rx_write_pointer`](#can_top_level_rx_write_pointer)                                   | 0x404    |        4 | Auto-extracted signal rx_write_pointer from can_top_level.vhd                  |
+| can_bus.[`can_top_level_rx_data_overrun`](#can_top_level_rx_data_overrun)                                     | 0x408    |        4 | Auto-extracted signal rx_data_overrun from can_top_level.vhd                   |
+| can_bus.[`can_top_level_rx_read_buff`](#can_top_level_rx_read_buff)                                           | 0x40c    |        4 | Auto-extracted signal rx_read_buff from can_top_level.vhd                      |
+| can_bus.[`can_top_level_rx_mof`](#can_top_level_rx_mof)                                                       | 0x410    |        4 | Auto-extracted signal rx_mof from can_top_level.vhd                            |
+| can_bus.[`can_top_level_txtb_port_a_data`](#can_top_level_txtb_port_a_data)                                   | 0x414    |        4 | Auto-extracted signal txtb_port_a_data from can_top_level.vhd                  |
+| can_bus.[`can_top_level_txtb_port_a_address`](#can_top_level_txtb_port_a_address)                             | 0x418    |        4 | Auto-extracted signal txtb_port_a_address from can_top_level.vhd               |
+| can_bus.[`can_top_level_txtb_port_a_cs`](#can_top_level_txtb_port_a_cs)                                       | 0x41c    |        4 | Auto-extracted signal txtb_port_a_cs from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_port_a_be`](#can_top_level_txtb_port_a_be)                                       | 0x420    |        4 | Auto-extracted signal txtb_port_a_be from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_sw_cmd_index`](#can_top_level_txtb_sw_cmd_index)                                 | 0x424    |        4 | Auto-extracted signal txtb_sw_cmd_index from can_top_level.vhd                 |
+| can_bus.[`can_top_level_txt_buf_failed_bof`](#can_top_level_txt_buf_failed_bof)                               | 0x428    |        4 | Auto-extracted signal txt_buf_failed_bof from can_top_level.vhd                |
+| can_bus.[`can_top_level_int_vector`](#can_top_level_int_vector)                                               | 0x42c    |        4 | Auto-extracted signal int_vector from can_top_level.vhd                        |
+| can_bus.[`can_top_level_int_ena`](#can_top_level_int_ena)                                                     | 0x430    |        4 | Auto-extracted signal int_ena from can_top_level.vhd                           |
+| can_bus.[`can_top_level_int_mask`](#can_top_level_int_mask)                                                   | 0x434    |        4 | Auto-extracted signal int_mask from can_top_level.vhd                          |
+| can_bus.[`can_top_level_rec_ident`](#can_top_level_rec_ident)                                                 | 0x438    |        4 | Auto-extracted signal rec_ident from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rec_dlc`](#can_top_level_rec_dlc)                                                     | 0x43c    |        4 | Auto-extracted signal rec_dlc from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rec_ident_type`](#can_top_level_rec_ident_type)                                       | 0x440    |        4 | Auto-extracted signal rec_ident_type from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rec_frame_type`](#can_top_level_rec_frame_type)                                       | 0x444    |        4 | Auto-extracted signal rec_frame_type from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rec_is_rtr`](#can_top_level_rec_is_rtr)                                               | 0x448    |        4 | Auto-extracted signal rec_is_rtr from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rec_brs`](#can_top_level_rec_brs)                                                     | 0x44c    |        4 | Auto-extracted signal rec_brs from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rec_esi`](#can_top_level_rec_esi)                                                     | 0x450    |        4 | Auto-extracted signal rec_esi from can_top_level.vhd                           |
+| can_bus.[`can_top_level_store_data_word`](#can_top_level_store_data_word)                                     | 0x454    |        4 | Auto-extracted signal store_data_word from can_top_level.vhd                   |
+| can_bus.[`can_top_level_sof_pulse`](#can_top_level_sof_pulse)                                                 | 0x458    |        4 | Auto-extracted signal sof_pulse from can_top_level.vhd                         |
+| can_bus.[`can_top_level_store_metadata`](#can_top_level_store_metadata)                                       | 0x45c    |        4 | Auto-extracted signal store_metadata from can_top_level.vhd                    |
+| can_bus.[`can_top_level_store_data`](#can_top_level_store_data)                                               | 0x460    |        4 | Auto-extracted signal store_data from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rec_valid`](#can_top_level_rec_valid)                                                 | 0x464    |        4 | Auto-extracted signal rec_valid from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rec_abort`](#can_top_level_rec_abort)                                                 | 0x468    |        4 | Auto-extracted signal rec_abort from can_top_level.vhd                         |
+| can_bus.[`can_top_level_store_metadata_f`](#can_top_level_store_metadata_f)                                   | 0x46c    |        4 | Auto-extracted signal store_metadata_f from can_top_level.vhd                  |
+| can_bus.[`can_top_level_store_data_f`](#can_top_level_store_data_f)                                           | 0x470    |        4 | Auto-extracted signal store_data_f from can_top_level.vhd                      |
+| can_bus.[`can_top_level_rec_valid_f`](#can_top_level_rec_valid_f)                                             | 0x474    |        4 | Auto-extracted signal rec_valid_f from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rec_abort_f`](#can_top_level_rec_abort_f)                                             | 0x478    |        4 | Auto-extracted signal rec_abort_f from can_top_level.vhd                       |
+| can_bus.[`can_top_level_txtb_hw_cmd_int`](#can_top_level_txtb_hw_cmd_int)                                     | 0x47c    |        4 | Auto-extracted signal txtb_hw_cmd_int from can_top_level.vhd                   |
+| can_bus.[`can_top_level_is_bus_off`](#can_top_level_is_bus_off)                                               | 0x480    |        4 | Auto-extracted signal is_bus_off from can_top_level.vhd                        |
+| can_bus.[`can_top_level_txtb_available`](#can_top_level_txtb_available)                                       | 0x484    |        4 | Auto-extracted signal txtb_available from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_port_b_clk_en`](#can_top_level_txtb_port_b_clk_en)                               | 0x488    |        4 | Auto-extracted signal txtb_port_b_clk_en from can_top_level.vhd                |
+| can_bus.[`can_top_level_tran_dlc`](#can_top_level_tran_dlc)                                                   | 0x48c    |        4 | Auto-extracted signal tran_dlc from can_top_level.vhd                          |
+| can_bus.[`can_top_level_tran_is_rtr`](#can_top_level_tran_is_rtr)                                             | 0x490    |        4 | Auto-extracted signal tran_is_rtr from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tran_ident_type`](#can_top_level_tran_ident_type)                                     | 0x494    |        4 | Auto-extracted signal tran_ident_type from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_frame_type`](#can_top_level_tran_frame_type)                                     | 0x498    |        4 | Auto-extracted signal tran_frame_type from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_brs`](#can_top_level_tran_brs)                                                   | 0x49c    |        4 | Auto-extracted signal tran_brs from can_top_level.vhd                          |
+| can_bus.[`can_top_level_tran_identifier`](#can_top_level_tran_identifier)                                     | 0x4a0    |        4 | Auto-extracted signal tran_identifier from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_word`](#can_top_level_tran_word)                                                 | 0x4a4    |        4 | Auto-extracted signal tran_word from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tran_frame_valid`](#can_top_level_tran_frame_valid)                                   | 0x4a8    |        4 | Auto-extracted signal tran_frame_valid from can_top_level.vhd                  |
+| can_bus.[`can_top_level_txtb_changed`](#can_top_level_txtb_changed)                                           | 0x4ac    |        4 | Auto-extracted signal txtb_changed from can_top_level.vhd                      |
+| can_bus.[`can_top_level_txtb_clk_en`](#can_top_level_txtb_clk_en)                                             | 0x4b0    |        4 | Auto-extracted signal txtb_clk_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_err_detected`](#can_top_level_err_detected)                                           | 0x4b4    |        4 | Auto-extracted signal err_detected from can_top_level.vhd                      |
+| can_bus.[`can_top_level_fcs_changed`](#can_top_level_fcs_changed)                                             | 0x4b8    |        4 | Auto-extracted signal fcs_changed from can_top_level.vhd                       |
+| can_bus.[`can_top_level_err_warning_limit`](#can_top_level_err_warning_limit)                                 | 0x4bc    |        4 | Auto-extracted signal err_warning_limit from can_top_level.vhd                 |
+| can_bus.[`can_top_level_arbitration_lost`](#can_top_level_arbitration_lost)                                   | 0x4c0    |        4 | Auto-extracted signal arbitration_lost from can_top_level.vhd                  |
+| can_bus.[`can_top_level_tran_valid`](#can_top_level_tran_valid)                                               | 0x4c4    |        4 | Auto-extracted signal tran_valid from can_top_level.vhd                        |
+| can_bus.[`can_top_level_br_shifted`](#can_top_level_br_shifted)                                               | 0x4c8    |        4 | Auto-extracted signal br_shifted from can_top_level.vhd                        |
+| can_bus.[`can_top_level_is_overload`](#can_top_level_is_overload)                                             | 0x4cc    |        4 | Auto-extracted signal is_overload from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_triggers`](#can_top_level_rx_triggers)                                             | 0x4d0    |        4 | Auto-extracted signal rx_triggers from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tx_trigger`](#can_top_level_tx_trigger)                                               | 0x4d4    |        4 | Auto-extracted signal tx_trigger from can_top_level.vhd                        |
+| can_bus.[`can_top_level_sync_control`](#can_top_level_sync_control)                                           | 0x4d8    |        4 | Auto-extracted signal sync_control from can_top_level.vhd                      |
+| can_bus.[`can_top_level_no_pos_resync`](#can_top_level_no_pos_resync)                                         | 0x4dc    |        4 | Auto-extracted signal no_pos_resync from can_top_level.vhd                     |
+| can_bus.[`can_top_level_nbt_ctrs_en`](#can_top_level_nbt_ctrs_en)                                             | 0x4e0    |        4 | Auto-extracted signal nbt_ctrs_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_dbt_ctrs_en`](#can_top_level_dbt_ctrs_en)                                             | 0x4e4    |        4 | Auto-extracted signal dbt_ctrs_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_trv_delay`](#can_top_level_trv_delay)                                                 | 0x4e8    |        4 | Auto-extracted signal trv_delay from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rx_data_wbs`](#can_top_level_rx_data_wbs)                                             | 0x4ec    |        4 | Auto-extracted signal rx_data_wbs from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tx_data_wbs`](#can_top_level_tx_data_wbs)                                             | 0x4f0    |        4 | Auto-extracted signal tx_data_wbs from can_top_level.vhd                       |
+| can_bus.[`can_top_level_ssp_reset`](#can_top_level_ssp_reset)                                                 | 0x4f4    |        4 | Auto-extracted signal ssp_reset from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tran_delay_meas`](#can_top_level_tran_delay_meas)                                     | 0x4f8    |        4 | Auto-extracted signal tran_delay_meas from can_top_level.vhd                   |
+| can_bus.[`can_top_level_bit_err`](#can_top_level_bit_err)                                                     | 0x4fc    |        4 | Auto-extracted signal bit_err from can_top_level.vhd                           |
+| can_bus.[`can_top_level_sample_sec`](#can_top_level_sample_sec)                                               | 0x500    |        4 | Auto-extracted signal sample_sec from can_top_level.vhd                        |
+| can_bus.[`can_top_level_btmc_reset`](#can_top_level_btmc_reset)                                               | 0x504    |        4 | Auto-extracted signal btmc_reset from can_top_level.vhd                        |
+| can_bus.[`can_top_level_dbt_measure_start`](#can_top_level_dbt_measure_start)                                 | 0x508    |        4 | Auto-extracted signal dbt_measure_start from can_top_level.vhd                 |
+| can_bus.[`can_top_level_gen_first_ssp`](#can_top_level_gen_first_ssp)                                         | 0x50c    |        4 | Auto-extracted signal gen_first_ssp from can_top_level.vhd                     |
+| can_bus.[`can_top_level_sync_edge`](#can_top_level_sync_edge)                                                 | 0x510    |        4 | Auto-extracted signal sync_edge from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tq_edge`](#can_top_level_tq_edge)                                                     | 0x514    |        4 | Auto-extracted signal tq_edge from can_top_level.vhd                           |
+| can_bus.[`can_top_level_tst_rdata_rx_buf`](#can_top_level_tst_rdata_rx_buf)                                   | 0x518    |        4 | Auto-extracted signal tst_rdata_rx_buf from can_top_level.vhd                  |
+| can_bus.[`clk_gate_clk_en_q`](#clk_gate_clk_en_q)                                                             | 0x51c    |        4 | Auto-extracted signal clk_en_q from clk_gate.vhd                               |
+| can_bus.[`control_counter_ctrl_ctr_ce`](#control_counter_ctrl_ctr_ce)                                         | 0x520    |        4 | Auto-extracted signal ctrl_ctr_ce from control_counter.vhd                     |
+| can_bus.[`control_counter_compl_ctr_ce`](#control_counter_compl_ctr_ce)                                       | 0x524    |        4 | Auto-extracted signal compl_ctr_ce from control_counter.vhd                    |
+| can_bus.[`control_registers_reg_map_reg_sel`](#control_registers_reg_map_reg_sel)                             | 0x528    |        4 | Auto-extracted signal reg_sel from control_registers_reg_map.vhd               |
+| can_bus.[`control_registers_reg_map_read_data_mux_in`](#control_registers_reg_map_read_data_mux_in)           | 0x52c    |        4 | Auto-extracted signal read_data_mux_in from control_registers_reg_map.vhd      |
+| can_bus.[`control_registers_reg_map_read_data_mask_n`](#control_registers_reg_map_read_data_mask_n)           | 0x530    |        4 | Auto-extracted signal read_data_mask_n from control_registers_reg_map.vhd      |
+| can_bus.[`control_registers_reg_map_read_mux_ena`](#control_registers_reg_map_read_mux_ena)                   | 0x534    |        4 | Auto-extracted signal read_mux_ena from control_registers_reg_map.vhd          |
+| can_bus.[`crc_calc_crc_q`](#crc_calc_crc_q)                                                                   | 0x538    |        4 | Auto-extracted signal crc_q from crc_calc.vhd                                  |
+| can_bus.[`crc_calc_crc_nxt`](#crc_calc_crc_nxt)                                                               | 0x53c    |        4 | Auto-extracted signal crc_nxt from crc_calc.vhd                                |
+| can_bus.[`crc_calc_crc_shift`](#crc_calc_crc_shift)                                                           | 0x540    |        4 | Auto-extracted signal crc_shift from crc_calc.vhd                              |
+| can_bus.[`crc_calc_crc_shift_n_xor`](#crc_calc_crc_shift_n_xor)                                               | 0x544    |        4 | Auto-extracted signal crc_shift_n_xor from crc_calc.vhd                        |
+| can_bus.[`crc_calc_crc_d`](#crc_calc_crc_d)                                                                   | 0x548    |        4 | Auto-extracted signal crc_d from crc_calc.vhd                                  |
+| can_bus.[`crc_calc_crc_ce`](#crc_calc_crc_ce)                                                                 | 0x54c    |        4 | Auto-extracted signal crc_ce from crc_calc.vhd                                 |
+| can_bus.[`data_edge_detector_rx_data_prev`](#data_edge_detector_rx_data_prev)                                 | 0x550    |        4 | Auto-extracted signal rx_data_prev from data_edge_detector.vhd                 |
+| can_bus.[`data_edge_detector_tx_data_prev`](#data_edge_detector_tx_data_prev)                                 | 0x554    |        4 | Auto-extracted signal tx_data_prev from data_edge_detector.vhd                 |
+| can_bus.[`data_edge_detector_rx_data_sync_prev`](#data_edge_detector_rx_data_sync_prev)                       | 0x558    |        4 | Auto-extracted signal rx_data_sync_prev from data_edge_detector.vhd            |
+| can_bus.[`data_edge_detector_rx_edge_i`](#data_edge_detector_rx_edge_i)                                       | 0x55c    |        4 | Auto-extracted signal rx_edge_i from data_edge_detector.vhd                    |
+| can_bus.[`data_edge_detector_tx_edge_i`](#data_edge_detector_tx_edge_i)                                       | 0x560    |        4 | Auto-extracted signal tx_edge_i from data_edge_detector.vhd                    |
+| can_bus.[`data_mux_sel_data`](#data_mux_sel_data)                                                             | 0x564    |        4 | Auto-extracted signal sel_data from data_mux.vhd                               |
+| can_bus.[`data_mux_saturated_data`](#data_mux_saturated_data)                                                 | 0x568    |        4 | Auto-extracted signal saturated_data from data_mux.vhd                         |
+| can_bus.[`data_mux_masked_data`](#data_mux_masked_data)                                                       | 0x56c    |        4 | Auto-extracted signal masked_data from data_mux.vhd                            |
+| can_bus.[`dlc_decoder_data_len_8_to_64`](#dlc_decoder_data_len_8_to_64)                                       | 0x570    |        4 | Auto-extracted signal data_len_8_to_64 from dlc_decoder.vhd                    |
+| can_bus.[`dlc_decoder_data_len_can_2_0`](#dlc_decoder_data_len_can_2_0)                                       | 0x574    |        4 | Auto-extracted signal data_len_can_2_0 from dlc_decoder.vhd                    |
+| can_bus.[`dlc_decoder_data_len_can_fd`](#dlc_decoder_data_len_can_fd)                                         | 0x578    |        4 | Auto-extracted signal data_len_can_fd from dlc_decoder.vhd                     |
+| can_bus.[`endian_swapper_swapped`](#endian_swapper_swapped)                                                   | 0x57c    |        4 | Auto-extracted signal swapped from endian_swapper.vhd                          |
+| can_bus.[`err_counters_tx_err_ctr_ce`](#err_counters_tx_err_ctr_ce)                                           | 0x580    |        4 | Auto-extracted signal tx_err_ctr_ce from err_counters.vhd                      |
+| can_bus.[`err_counters_rx_err_ctr_ce`](#err_counters_rx_err_ctr_ce)                                           | 0x584    |        4 | Auto-extracted signal rx_err_ctr_ce from err_counters.vhd                      |
+| can_bus.[`err_counters_modif_tx_ctr`](#err_counters_modif_tx_ctr)                                             | 0x588    |        4 | Auto-extracted signal modif_tx_ctr from err_counters.vhd                       |
+| can_bus.[`err_counters_modif_rx_ctr`](#err_counters_modif_rx_ctr)                                             | 0x58c    |        4 | Auto-extracted signal modif_rx_ctr from err_counters.vhd                       |
+| can_bus.[`err_counters_nom_err_ctr_ce`](#err_counters_nom_err_ctr_ce)                                         | 0x590    |        4 | Auto-extracted signal nom_err_ctr_ce from err_counters.vhd                     |
+| can_bus.[`err_counters_data_err_ctr_ce`](#err_counters_data_err_ctr_ce)                                       | 0x594    |        4 | Auto-extracted signal data_err_ctr_ce from err_counters.vhd                    |
+| can_bus.[`err_counters_res_err_ctrs_d`](#err_counters_res_err_ctrs_d)                                         | 0x598    |        4 | Auto-extracted signal res_err_ctrs_d from err_counters.vhd                     |
+| can_bus.[`err_counters_res_err_ctrs_q`](#err_counters_res_err_ctrs_q)                                         | 0x59c    |        4 | Auto-extracted signal res_err_ctrs_q from err_counters.vhd                     |
+| can_bus.[`err_counters_res_err_ctrs_q_scan`](#err_counters_res_err_ctrs_q_scan)                               | 0x5a0    |        4 | Auto-extracted signal res_err_ctrs_q_scan from err_counters.vhd                |
+| can_bus.[`err_detector_err_frm_req_i`](#err_detector_err_frm_req_i)                                           | 0x5a4    |        4 | Auto-extracted signal err_frm_req_i from err_detector.vhd                      |
+| can_bus.[`err_detector_err_type_d`](#err_detector_err_type_d)                                                 | 0x5a8    |        4 | Auto-extracted signal err_type_d from err_detector.vhd                         |
+| can_bus.[`err_detector_err_type_q`](#err_detector_err_type_q)                                                 | 0x5ac    |        4 | Auto-extracted signal err_type_q from err_detector.vhd                         |
+| can_bus.[`err_detector_err_pos_q`](#err_detector_err_pos_q)                                                   | 0x5b0    |        4 | Auto-extracted signal err_pos_q from err_detector.vhd                          |
+| can_bus.[`err_detector_form_err_i`](#err_detector_form_err_i)                                                 | 0x5b4    |        4 | Auto-extracted signal form_err_i from err_detector.vhd                         |
+| can_bus.[`err_detector_crc_match_c`](#err_detector_crc_match_c)                                               | 0x5b8    |        4 | Auto-extracted signal crc_match_c from err_detector.vhd                        |
+| can_bus.[`err_detector_crc_match_d`](#err_detector_crc_match_d)                                               | 0x5bc    |        4 | Auto-extracted signal crc_match_d from err_detector.vhd                        |
+| can_bus.[`err_detector_crc_match_q`](#err_detector_crc_match_q)                                               | 0x5c0    |        4 | Auto-extracted signal crc_match_q from err_detector.vhd                        |
+| can_bus.[`err_detector_dst_ctr_grey`](#err_detector_dst_ctr_grey)                                             | 0x5c4    |        4 | Auto-extracted signal dst_ctr_grey from err_detector.vhd                       |
+| can_bus.[`err_detector_dst_parity`](#err_detector_dst_parity)                                                 | 0x5c8    |        4 | Auto-extracted signal dst_parity from err_detector.vhd                         |
+| can_bus.[`err_detector_stuff_count_check`](#err_detector_stuff_count_check)                                   | 0x5cc    |        4 | Auto-extracted signal stuff_count_check from err_detector.vhd                  |
+| can_bus.[`err_detector_crc_15_ok`](#err_detector_crc_15_ok)                                                   | 0x5d0    |        4 | Auto-extracted signal crc_15_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_crc_17_ok`](#err_detector_crc_17_ok)                                                   | 0x5d4    |        4 | Auto-extracted signal crc_17_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_crc_21_ok`](#err_detector_crc_21_ok)                                                   | 0x5d8    |        4 | Auto-extracted signal crc_21_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_stuff_count_ok`](#err_detector_stuff_count_ok)                                         | 0x5dc    |        4 | Auto-extracted signal stuff_count_ok from err_detector.vhd                     |
+| can_bus.[`err_detector_rx_crc_15`](#err_detector_rx_crc_15)                                                   | 0x5e0    |        4 | Auto-extracted signal rx_crc_15 from err_detector.vhd                          |
+| can_bus.[`err_detector_rx_crc_17`](#err_detector_rx_crc_17)                                                   | 0x5e4    |        4 | Auto-extracted signal rx_crc_17 from err_detector.vhd                          |
+| can_bus.[`err_detector_rx_crc_21`](#err_detector_rx_crc_21)                                                   | 0x5e8    |        4 | Auto-extracted signal rx_crc_21 from err_detector.vhd                          |
+| can_bus.[`fault_confinement_drv_ewl`](#fault_confinement_drv_ewl)                                             | 0x5ec    |        4 | Auto-extracted signal drv_ewl from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_erp`](#fault_confinement_drv_erp)                                             | 0x5f0    |        4 | Auto-extracted signal drv_erp from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_ctr_val`](#fault_confinement_drv_ctr_val)                                     | 0x5f4    |        4 | Auto-extracted signal drv_ctr_val from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_drv_ctr_sel`](#fault_confinement_drv_ctr_sel)                                     | 0x5f8    |        4 | Auto-extracted signal drv_ctr_sel from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_drv_ena`](#fault_confinement_drv_ena)                                             | 0x5fc    |        4 | Auto-extracted signal drv_ena from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_tx_err_ctr_i`](#fault_confinement_tx_err_ctr_i)                                   | 0x600    |        4 | Auto-extracted signal tx_err_ctr_i from fault_confinement.vhd                  |
+| can_bus.[`fault_confinement_rx_err_ctr_i`](#fault_confinement_rx_err_ctr_i)                                   | 0x604    |        4 | Auto-extracted signal rx_err_ctr_i from fault_confinement.vhd                  |
+| can_bus.[`fault_confinement_inc_one`](#fault_confinement_inc_one)                                             | 0x608    |        4 | Auto-extracted signal inc_one from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_inc_eight`](#fault_confinement_inc_eight)                                         | 0x60c    |        4 | Auto-extracted signal inc_eight from fault_confinement.vhd                     |
+| can_bus.[`fault_confinement_dec_one`](#fault_confinement_dec_one)                                             | 0x610    |        4 | Auto-extracted signal dec_one from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_rom_ena`](#fault_confinement_drv_rom_ena)                                     | 0x614    |        4 | Auto-extracted signal drv_rom_ena from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_erp`](#fault_confinement_fsm_tx_err_ctr_mt_erp)                 | 0x618    |        4 | Auto-extracted signal tx_err_ctr_mt_erp from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_rx_err_ctr_mt_erp`](#fault_confinement_fsm_rx_err_ctr_mt_erp)                 | 0x61c    |        4 | Auto-extracted signal rx_err_ctr_mt_erp from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_ewl`](#fault_confinement_fsm_tx_err_ctr_mt_ewl)                 | 0x620    |        4 | Auto-extracted signal tx_err_ctr_mt_ewl from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_rx_err_ctr_mt_ewl`](#fault_confinement_fsm_rx_err_ctr_mt_ewl)                 | 0x624    |        4 | Auto-extracted signal rx_err_ctr_mt_ewl from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_255`](#fault_confinement_fsm_tx_err_ctr_mt_255)                 | 0x628    |        4 | Auto-extracted signal tx_err_ctr_mt_255 from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_err_warning_limit_d`](#fault_confinement_fsm_err_warning_limit_d)             | 0x62c    |        4 | Auto-extracted signal err_warning_limit_d from fault_confinement_fsm.vhd       |
+| can_bus.[`fault_confinement_fsm_err_warning_limit_q`](#fault_confinement_fsm_err_warning_limit_q)             | 0x630    |        4 | Auto-extracted signal err_warning_limit_q from fault_confinement_fsm.vhd       |
+| can_bus.[`fault_confinement_fsm_fc_fsm_res_d`](#fault_confinement_fsm_fc_fsm_res_d)                           | 0x634    |        4 | Auto-extracted signal fc_fsm_res_d from fault_confinement_fsm.vhd              |
+| can_bus.[`fault_confinement_fsm_fc_fsm_res_q`](#fault_confinement_fsm_fc_fsm_res_q)                           | 0x638    |        4 | Auto-extracted signal fc_fsm_res_q from fault_confinement_fsm.vhd              |
+| can_bus.[`fault_confinement_rules_inc_one_i`](#fault_confinement_rules_inc_one_i)                             | 0x63c    |        4 | Auto-extracted signal inc_one_i from fault_confinement_rules.vhd               |
+| can_bus.[`fault_confinement_rules_inc_eight_i`](#fault_confinement_rules_inc_eight_i)                         | 0x640    |        4 | Auto-extracted signal inc_eight_i from fault_confinement_rules.vhd             |
+| can_bus.[`frame_filters_drv_filter_A_mask`](#frame_filters_drv_filter_a_mask)                                 | 0x644    |        4 | Auto-extracted signal drv_filter_A_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_A_ctrl`](#frame_filters_drv_filter_a_ctrl)                                 | 0x648    |        4 | Auto-extracted signal drv_filter_A_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_A_bits`](#frame_filters_drv_filter_a_bits)                                 | 0x64c    |        4 | Auto-extracted signal drv_filter_A_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_A_valid`](#frame_filters_int_filter_a_valid)                               | 0x650    |        4 | Auto-extracted signal int_filter_A_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_B_mask`](#frame_filters_drv_filter_b_mask)                                 | 0x654    |        4 | Auto-extracted signal drv_filter_B_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_B_ctrl`](#frame_filters_drv_filter_b_ctrl)                                 | 0x658    |        4 | Auto-extracted signal drv_filter_B_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_B_bits`](#frame_filters_drv_filter_b_bits)                                 | 0x65c    |        4 | Auto-extracted signal drv_filter_B_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_B_valid`](#frame_filters_int_filter_b_valid)                               | 0x660    |        4 | Auto-extracted signal int_filter_B_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_C_mask`](#frame_filters_drv_filter_c_mask)                                 | 0x664    |        4 | Auto-extracted signal drv_filter_C_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_C_ctrl`](#frame_filters_drv_filter_c_ctrl)                                 | 0x668    |        4 | Auto-extracted signal drv_filter_C_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_C_bits`](#frame_filters_drv_filter_c_bits)                                 | 0x66c    |        4 | Auto-extracted signal drv_filter_C_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_C_valid`](#frame_filters_int_filter_c_valid)                               | 0x670    |        4 | Auto-extracted signal int_filter_C_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_ran_ctrl`](#frame_filters_drv_filter_ran_ctrl)                             | 0x674    |        4 | Auto-extracted signal drv_filter_ran_ctrl from frame_filters.vhd               |
+| can_bus.[`frame_filters_drv_filter_ran_lo_th`](#frame_filters_drv_filter_ran_lo_th)                           | 0x678    |        4 | Auto-extracted signal drv_filter_ran_lo_th from frame_filters.vhd              |
+| can_bus.[`frame_filters_drv_filter_ran_hi_th`](#frame_filters_drv_filter_ran_hi_th)                           | 0x67c    |        4 | Auto-extracted signal drv_filter_ran_hi_th from frame_filters.vhd              |
+| can_bus.[`frame_filters_int_filter_ran_valid`](#frame_filters_int_filter_ran_valid)                           | 0x680    |        4 | Auto-extracted signal int_filter_ran_valid from frame_filters.vhd              |
+| can_bus.[`frame_filters_drv_filters_ena`](#frame_filters_drv_filters_ena)                                     | 0x684    |        4 | Auto-extracted signal drv_filters_ena from frame_filters.vhd                   |
+| can_bus.[`frame_filters_int_data_type`](#frame_filters_int_data_type)                                         | 0x688    |        4 | Auto-extracted signal int_data_type from frame_filters.vhd                     |
+| can_bus.[`frame_filters_int_data_ctrl`](#frame_filters_int_data_ctrl)                                         | 0x68c    |        4 | Auto-extracted signal int_data_ctrl from frame_filters.vhd                     |
+| can_bus.[`frame_filters_filter_A_enable`](#frame_filters_filter_a_enable)                                     | 0x690    |        4 | Auto-extracted signal filter_A_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_B_enable`](#frame_filters_filter_b_enable)                                     | 0x694    |        4 | Auto-extracted signal filter_B_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_C_enable`](#frame_filters_filter_c_enable)                                     | 0x698    |        4 | Auto-extracted signal filter_C_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_range_enable`](#frame_filters_filter_range_enable)                             | 0x69c    |        4 | Auto-extracted signal filter_range_enable from frame_filters.vhd               |
+| can_bus.[`frame_filters_filter_result`](#frame_filters_filter_result)                                         | 0x6a0    |        4 | Auto-extracted signal filter_result from frame_filters.vhd                     |
+| can_bus.[`frame_filters_ident_valid_d`](#frame_filters_ident_valid_d)                                         | 0x6a4    |        4 | Auto-extracted signal ident_valid_d from frame_filters.vhd                     |
+| can_bus.[`frame_filters_ident_valid_q`](#frame_filters_ident_valid_q)                                         | 0x6a8    |        4 | Auto-extracted signal ident_valid_q from frame_filters.vhd                     |
+| can_bus.[`frame_filters_drv_drop_remote_frames`](#frame_filters_drv_drop_remote_frames)                       | 0x6ac    |        4 | Auto-extracted signal drv_drop_remote_frames from frame_filters.vhd            |
+| can_bus.[`frame_filters_drop_rtr_frame`](#frame_filters_drop_rtr_frame)                                       | 0x6b0    |        4 | Auto-extracted signal drop_rtr_frame from frame_filters.vhd                    |
+| can_bus.[`inf_ram_wrapper_int_read_data`](#inf_ram_wrapper_int_read_data)                                     | 0x6b4    |        4 | Auto-extracted signal int_read_data from inf_ram_wrapper.vhd                   |
+| can_bus.[`inf_ram_wrapper_byte_we`](#inf_ram_wrapper_byte_we)                                                 | 0x6b8    |        4 | Auto-extracted signal byte_we from inf_ram_wrapper.vhd                         |
+| can_bus.[`int_manager_drv_int_vect_clr`](#int_manager_drv_int_vect_clr)                                       | 0x6bc    |        4 | Auto-extracted signal drv_int_vect_clr from int_manager.vhd                    |
+| can_bus.[`int_manager_drv_int_ena_set`](#int_manager_drv_int_ena_set)                                         | 0x6c0    |        4 | Auto-extracted signal drv_int_ena_set from int_manager.vhd                     |
+| can_bus.[`int_manager_drv_int_ena_clr`](#int_manager_drv_int_ena_clr)                                         | 0x6c4    |        4 | Auto-extracted signal drv_int_ena_clr from int_manager.vhd                     |
+| can_bus.[`int_manager_drv_int_mask_set`](#int_manager_drv_int_mask_set)                                       | 0x6c8    |        4 | Auto-extracted signal drv_int_mask_set from int_manager.vhd                    |
+| can_bus.[`int_manager_drv_int_mask_clr`](#int_manager_drv_int_mask_clr)                                       | 0x6cc    |        4 | Auto-extracted signal drv_int_mask_clr from int_manager.vhd                    |
+| can_bus.[`int_manager_int_ena_i`](#int_manager_int_ena_i)                                                     | 0x6d0    |        4 | Auto-extracted signal int_ena_i from int_manager.vhd                           |
+| can_bus.[`int_manager_int_mask_i`](#int_manager_int_mask_i)                                                   | 0x6d4    |        4 | Auto-extracted signal int_mask_i from int_manager.vhd                          |
+| can_bus.[`int_manager_int_vect_i`](#int_manager_int_vect_i)                                                   | 0x6d8    |        4 | Auto-extracted signal int_vect_i from int_manager.vhd                          |
+| can_bus.[`int_manager_int_input_active`](#int_manager_int_input_active)                                       | 0x6dc    |        4 | Auto-extracted signal int_input_active from int_manager.vhd                    |
+| can_bus.[`int_manager_int_i`](#int_manager_int_i)                                                             | 0x6e0    |        4 | Auto-extracted signal int_i from int_manager.vhd                               |
+| can_bus.[`int_module_int_mask_i`](#int_module_int_mask_i)                                                     | 0x6e4    |        4 | Auto-extracted signal int_mask_i from int_module.vhd                           |
+| can_bus.[`int_module_int_ena_i`](#int_module_int_ena_i)                                                       | 0x6e8    |        4 | Auto-extracted signal int_ena_i from int_module.vhd                            |
+| can_bus.[`int_module_int_mask_load`](#int_module_int_mask_load)                                               | 0x6ec    |        4 | Auto-extracted signal int_mask_load from int_module.vhd                        |
+| can_bus.[`int_module_int_mask_next`](#int_module_int_mask_next)                                               | 0x6f0    |        4 | Auto-extracted signal int_mask_next from int_module.vhd                        |
+| can_bus.[`memory_reg_reg_value_r`](#memory_reg_reg_value_r)                                                   | 0x6f4    |        4 | Auto-extracted signal reg_value_r from memory_reg.vhd                          |
+| can_bus.[`memory_reg_wr_select`](#memory_reg_wr_select)                                                       | 0x6f8    |        4 | Auto-extracted signal wr_select from memory_reg.vhd                            |
+| can_bus.[`memory_reg_wr_select_expanded`](#memory_reg_wr_select_expanded)                                     | 0x6fc    |        4 | Auto-extracted signal wr_select_expanded from memory_reg.vhd                   |
+| can_bus.[`memory_registers_status_comb`](#memory_registers_status_comb)                                       | 0x700    |        4 | Auto-extracted signal status_comb from memory_registers.vhd                    |
+| can_bus.[`memory_registers_can_core_cs`](#memory_registers_can_core_cs)                                       | 0x704    |        4 | Auto-extracted signal can_core_cs from memory_registers.vhd                    |
+| can_bus.[`memory_registers_control_registers_cs`](#memory_registers_control_registers_cs)                     | 0x708    |        4 | Auto-extracted signal control_registers_cs from memory_registers.vhd           |
+| can_bus.[`memory_registers_control_registers_cs_reg`](#memory_registers_control_registers_cs_reg)             | 0x70c    |        4 | Auto-extracted signal control_registers_cs_reg from memory_registers.vhd       |
+| can_bus.[`memory_registers_test_registers_cs`](#memory_registers_test_registers_cs)                           | 0x710    |        4 | Auto-extracted signal test_registers_cs from memory_registers.vhd              |
+| can_bus.[`memory_registers_test_registers_cs_reg`](#memory_registers_test_registers_cs_reg)                   | 0x714    |        4 | Auto-extracted signal test_registers_cs_reg from memory_registers.vhd          |
+| can_bus.[`memory_registers_control_registers_rdata`](#memory_registers_control_registers_rdata)               | 0x718    |        4 | Auto-extracted signal control_registers_rdata from memory_registers.vhd        |
+| can_bus.[`memory_registers_test_registers_rdata`](#memory_registers_test_registers_rdata)                     | 0x71c    |        4 | Auto-extracted signal test_registers_rdata from memory_registers.vhd           |
+| can_bus.[`memory_registers_is_err_active`](#memory_registers_is_err_active)                                   | 0x720    |        4 | Auto-extracted signal is_err_active from memory_registers.vhd                  |
+| can_bus.[`memory_registers_is_err_passive`](#memory_registers_is_err_passive)                                 | 0x724    |        4 | Auto-extracted signal is_err_passive from memory_registers.vhd                 |
+| can_bus.[`memory_registers_is_bus_off`](#memory_registers_is_bus_off)                                         | 0x728    |        4 | Auto-extracted signal is_bus_off from memory_registers.vhd                     |
+| can_bus.[`memory_registers_is_transmitter`](#memory_registers_is_transmitter)                                 | 0x72c    |        4 | Auto-extracted signal is_transmitter from memory_registers.vhd                 |
+| can_bus.[`memory_registers_is_receiver`](#memory_registers_is_receiver)                                       | 0x730    |        4 | Auto-extracted signal is_receiver from memory_registers.vhd                    |
+| can_bus.[`memory_registers_is_idle`](#memory_registers_is_idle)                                               | 0x734    |        4 | Auto-extracted signal is_idle from memory_registers.vhd                        |
+| can_bus.[`memory_registers_reg_lock_1_active`](#memory_registers_reg_lock_1_active)                           | 0x738    |        4 | Auto-extracted signal reg_lock_1_active from memory_registers.vhd              |
+| can_bus.[`memory_registers_reg_lock_2_active`](#memory_registers_reg_lock_2_active)                           | 0x73c    |        4 | Auto-extracted signal reg_lock_2_active from memory_registers.vhd              |
+| can_bus.[`memory_registers_soft_res_q_n`](#memory_registers_soft_res_q_n)                                     | 0x740    |        4 | Auto-extracted signal soft_res_q_n from memory_registers.vhd                   |
+| can_bus.[`memory_registers_ewl_padded`](#memory_registers_ewl_padded)                                         | 0x744    |        4 | Auto-extracted signal ewl_padded from memory_registers.vhd                     |
+| can_bus.[`memory_registers_control_regs_clk_en`](#memory_registers_control_regs_clk_en)                       | 0x748    |        4 | Auto-extracted signal control_regs_clk_en from memory_registers.vhd            |
+| can_bus.[`memory_registers_test_regs_clk_en`](#memory_registers_test_regs_clk_en)                             | 0x74c    |        4 | Auto-extracted signal test_regs_clk_en from memory_registers.vhd               |
+| can_bus.[`memory_registers_clk_control_regs`](#memory_registers_clk_control_regs)                             | 0x750    |        4 | Auto-extracted signal clk_control_regs from memory_registers.vhd               |
+| can_bus.[`memory_registers_clk_test_regs`](#memory_registers_clk_test_regs)                                   | 0x754    |        4 | Auto-extracted signal clk_test_regs from memory_registers.vhd                  |
+| can_bus.[`memory_registers_rx_buf_mode`](#memory_registers_rx_buf_mode)                                       | 0x758    |        4 | Auto-extracted signal rx_buf_mode from memory_registers.vhd                    |
+| can_bus.[`memory_registers_rx_move_cmd`](#memory_registers_rx_move_cmd)                                       | 0x75c    |        4 | Auto-extracted signal rx_move_cmd from memory_registers.vhd                    |
+| can_bus.[`memory_registers_ctr_pres_sel_q`](#memory_registers_ctr_pres_sel_q)                                 | 0x760    |        4 | Auto-extracted signal ctr_pres_sel_q from memory_registers.vhd                 |
+| can_bus.[`operation_control_drv_ena`](#operation_control_drv_ena)                                             | 0x764    |        4 | Auto-extracted signal drv_ena from operation_control.vhd                       |
+| can_bus.[`operation_control_go_to_off`](#operation_control_go_to_off)                                         | 0x768    |        4 | Auto-extracted signal go_to_off from operation_control.vhd                     |
+| can_bus.[`prescaler_drv_ena`](#prescaler_drv_ena)                                                             | 0x76c    |        4 | Auto-extracted signal drv_ena from prescaler.vhd                               |
+| can_bus.[`prescaler_tseg1_nbt`](#prescaler_tseg1_nbt)                                                         | 0x770    |        4 | Auto-extracted signal tseg1_nbt from prescaler.vhd                             |
+| can_bus.[`prescaler_tseg2_nbt`](#prescaler_tseg2_nbt)                                                         | 0x774    |        4 | Auto-extracted signal tseg2_nbt from prescaler.vhd                             |
+| can_bus.[`prescaler_brp_nbt`](#prescaler_brp_nbt)                                                             | 0x778    |        4 | Auto-extracted signal brp_nbt from prescaler.vhd                               |
+| can_bus.[`prescaler_sjw_nbt`](#prescaler_sjw_nbt)                                                             | 0x77c    |        4 | Auto-extracted signal sjw_nbt from prescaler.vhd                               |
+| can_bus.[`prescaler_tseg1_dbt`](#prescaler_tseg1_dbt)                                                         | 0x780    |        4 | Auto-extracted signal tseg1_dbt from prescaler.vhd                             |
+| can_bus.[`prescaler_tseg2_dbt`](#prescaler_tseg2_dbt)                                                         | 0x784    |        4 | Auto-extracted signal tseg2_dbt from prescaler.vhd                             |
+| can_bus.[`prescaler_brp_dbt`](#prescaler_brp_dbt)                                                             | 0x788    |        4 | Auto-extracted signal brp_dbt from prescaler.vhd                               |
+| can_bus.[`prescaler_sjw_dbt`](#prescaler_sjw_dbt)                                                             | 0x78c    |        4 | Auto-extracted signal sjw_dbt from prescaler.vhd                               |
+| can_bus.[`prescaler_segment_end`](#prescaler_segment_end)                                                     | 0x790    |        4 | Auto-extracted signal segment_end from prescaler.vhd                           |
+| can_bus.[`prescaler_h_sync_valid`](#prescaler_h_sync_valid)                                                   | 0x794    |        4 | Auto-extracted signal h_sync_valid from prescaler.vhd                          |
+| can_bus.[`prescaler_is_tseg1`](#prescaler_is_tseg1)                                                           | 0x798    |        4 | Auto-extracted signal is_tseg1 from prescaler.vhd                              |
+| can_bus.[`prescaler_is_tseg2`](#prescaler_is_tseg2)                                                           | 0x79c    |        4 | Auto-extracted signal is_tseg2 from prescaler.vhd                              |
+| can_bus.[`prescaler_resync_edge_valid`](#prescaler_resync_edge_valid)                                         | 0x7a0    |        4 | Auto-extracted signal resync_edge_valid from prescaler.vhd                     |
+| can_bus.[`prescaler_h_sync_edge_valid`](#prescaler_h_sync_edge_valid)                                         | 0x7a4    |        4 | Auto-extracted signal h_sync_edge_valid from prescaler.vhd                     |
+| can_bus.[`prescaler_segm_counter_nbt`](#prescaler_segm_counter_nbt)                                           | 0x7a8    |        4 | Auto-extracted signal segm_counter_nbt from prescaler.vhd                      |
+| can_bus.[`prescaler_segm_counter_dbt`](#prescaler_segm_counter_dbt)                                           | 0x7ac    |        4 | Auto-extracted signal segm_counter_dbt from prescaler.vhd                      |
+| can_bus.[`prescaler_exit_segm_req_nbt`](#prescaler_exit_segm_req_nbt)                                         | 0x7b0    |        4 | Auto-extracted signal exit_segm_req_nbt from prescaler.vhd                     |
+| can_bus.[`prescaler_exit_segm_req_dbt`](#prescaler_exit_segm_req_dbt)                                         | 0x7b4    |        4 | Auto-extracted signal exit_segm_req_dbt from prescaler.vhd                     |
+| can_bus.[`prescaler_tq_edge_nbt`](#prescaler_tq_edge_nbt)                                                     | 0x7b8    |        4 | Auto-extracted signal tq_edge_nbt from prescaler.vhd                           |
+| can_bus.[`prescaler_tq_edge_dbt`](#prescaler_tq_edge_dbt)                                                     | 0x7bc    |        4 | Auto-extracted signal tq_edge_dbt from prescaler.vhd                           |
+| can_bus.[`prescaler_rx_trig_req`](#prescaler_rx_trig_req)                                                     | 0x7c0    |        4 | Auto-extracted signal rx_trig_req from prescaler.vhd                           |
+| can_bus.[`prescaler_tx_trig_req`](#prescaler_tx_trig_req)                                                     | 0x7c4    |        4 | Auto-extracted signal tx_trig_req from prescaler.vhd                           |
+| can_bus.[`prescaler_start_edge`](#prescaler_start_edge)                                                       | 0x7c8    |        4 | Auto-extracted signal start_edge from prescaler.vhd                            |
+| can_bus.[`prescaler_bt_ctr_clear`](#prescaler_bt_ctr_clear)                                                   | 0x7cc    |        4 | Auto-extracted signal bt_ctr_clear from prescaler.vhd                          |
+| can_bus.[`priority_decoder_l0_valid`](#priority_decoder_l0_valid)                                             | 0x7d0    |        4 | Auto-extracted signal l0_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l1_valid`](#priority_decoder_l1_valid)                                             | 0x7d4    |        4 | Auto-extracted signal l1_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l1_winner`](#priority_decoder_l1_winner)                                           | 0x7d8    |        4 | Auto-extracted signal l1_winner from priority_decoder.vhd                      |
+| can_bus.[`priority_decoder_l2_valid`](#priority_decoder_l2_valid)                                             | 0x7dc    |        4 | Auto-extracted signal l2_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l2_winner`](#priority_decoder_l2_winner)                                           | 0x7e0    |        4 | Auto-extracted signal l2_winner from priority_decoder.vhd                      |
+| can_bus.[`priority_decoder_l3_valid`](#priority_decoder_l3_valid)                                             | 0x7e4    |        4 | Auto-extracted signal l3_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l3_winner`](#priority_decoder_l3_winner)                                           | 0x7e8    |        4 | Auto-extracted signal l3_winner from priority_decoder.vhd                      |
+| can_bus.[`protocol_control_drv_can_fd_ena`](#protocol_control_drv_can_fd_ena)                                 | 0x7ec    |        4 | Auto-extracted signal drv_can_fd_ena from protocol_control.vhd                 |
+| can_bus.[`protocol_control_drv_bus_mon_ena`](#protocol_control_drv_bus_mon_ena)                               | 0x7f0    |        4 | Auto-extracted signal drv_bus_mon_ena from protocol_control.vhd                |
+| can_bus.[`protocol_control_drv_retr_lim_ena`](#protocol_control_drv_retr_lim_ena)                             | 0x7f4    |        4 | Auto-extracted signal drv_retr_lim_ena from protocol_control.vhd               |
+| can_bus.[`protocol_control_drv_retr_th`](#protocol_control_drv_retr_th)                                       | 0x7f8    |        4 | Auto-extracted signal drv_retr_th from protocol_control.vhd                    |
+| can_bus.[`protocol_control_drv_self_test_ena`](#protocol_control_drv_self_test_ena)                           | 0x7fc    |        4 | Auto-extracted signal drv_self_test_ena from protocol_control.vhd              |
+| can_bus.[`protocol_control_drv_ack_forb`](#protocol_control_drv_ack_forb)                                     | 0x800    |        4 | Auto-extracted signal drv_ack_forb from protocol_control.vhd                   |
+| can_bus.[`protocol_control_drv_ena`](#protocol_control_drv_ena)                                               | 0x804    |        4 | Auto-extracted signal drv_ena from protocol_control.vhd                        |
+| can_bus.[`protocol_control_drv_fd_type`](#protocol_control_drv_fd_type)                                       | 0x808    |        4 | Auto-extracted signal drv_fd_type from protocol_control.vhd                    |
+| can_bus.[`protocol_control_drv_int_loopback_ena`](#protocol_control_drv_int_loopback_ena)                     | 0x80c    |        4 | Auto-extracted signal drv_int_loopback_ena from protocol_control.vhd           |
+| can_bus.[`protocol_control_drv_bus_off_reset`](#protocol_control_drv_bus_off_reset)                           | 0x810    |        4 | Auto-extracted signal drv_bus_off_reset from protocol_control.vhd              |
+| can_bus.[`protocol_control_drv_ssp_delay_select`](#protocol_control_drv_ssp_delay_select)                     | 0x814    |        4 | Auto-extracted signal drv_ssp_delay_select from protocol_control.vhd           |
+| can_bus.[`protocol_control_drv_pex`](#protocol_control_drv_pex)                                               | 0x818    |        4 | Auto-extracted signal drv_pex from protocol_control.vhd                        |
+| can_bus.[`protocol_control_drv_cpexs`](#protocol_control_drv_cpexs)                                           | 0x81c    |        4 | Auto-extracted signal drv_cpexs from protocol_control.vhd                      |
+| can_bus.[`protocol_control_tran_word_swapped`](#protocol_control_tran_word_swapped)                           | 0x820    |        4 | Auto-extracted signal tran_word_swapped from protocol_control.vhd              |
+| can_bus.[`protocol_control_err_frm_req`](#protocol_control_err_frm_req)                                       | 0x824    |        4 | Auto-extracted signal err_frm_req from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_load_base_id`](#protocol_control_tx_load_base_id)                               | 0x828    |        4 | Auto-extracted signal tx_load_base_id from protocol_control.vhd                |
+| can_bus.[`protocol_control_tx_load_ext_id`](#protocol_control_tx_load_ext_id)                                 | 0x82c    |        4 | Auto-extracted signal tx_load_ext_id from protocol_control.vhd                 |
+| can_bus.[`protocol_control_tx_load_dlc`](#protocol_control_tx_load_dlc)                                       | 0x830    |        4 | Auto-extracted signal tx_load_dlc from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_load_data_word`](#protocol_control_tx_load_data_word)                           | 0x834    |        4 | Auto-extracted signal tx_load_data_word from protocol_control.vhd              |
+| can_bus.[`protocol_control_tx_load_stuff_count`](#protocol_control_tx_load_stuff_count)                       | 0x838    |        4 | Auto-extracted signal tx_load_stuff_count from protocol_control.vhd            |
+| can_bus.[`protocol_control_tx_load_crc`](#protocol_control_tx_load_crc)                                       | 0x83c    |        4 | Auto-extracted signal tx_load_crc from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_shift_ena`](#protocol_control_tx_shift_ena)                                     | 0x840    |        4 | Auto-extracted signal tx_shift_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_tx_dominant`](#protocol_control_tx_dominant)                                       | 0x844    |        4 | Auto-extracted signal tx_dominant from protocol_control.vhd                    |
+| can_bus.[`protocol_control_rx_clear`](#protocol_control_rx_clear)                                             | 0x848    |        4 | Auto-extracted signal rx_clear from protocol_control.vhd                       |
+| can_bus.[`protocol_control_rx_store_base_id`](#protocol_control_rx_store_base_id)                             | 0x84c    |        4 | Auto-extracted signal rx_store_base_id from protocol_control.vhd               |
+| can_bus.[`protocol_control_rx_store_ext_id`](#protocol_control_rx_store_ext_id)                               | 0x850    |        4 | Auto-extracted signal rx_store_ext_id from protocol_control.vhd                |
+| can_bus.[`protocol_control_rx_store_ide`](#protocol_control_rx_store_ide)                                     | 0x854    |        4 | Auto-extracted signal rx_store_ide from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_rtr`](#protocol_control_rx_store_rtr)                                     | 0x858    |        4 | Auto-extracted signal rx_store_rtr from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_edl`](#protocol_control_rx_store_edl)                                     | 0x85c    |        4 | Auto-extracted signal rx_store_edl from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_dlc`](#protocol_control_rx_store_dlc)                                     | 0x860    |        4 | Auto-extracted signal rx_store_dlc from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_esi`](#protocol_control_rx_store_esi)                                     | 0x864    |        4 | Auto-extracted signal rx_store_esi from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_brs`](#protocol_control_rx_store_brs)                                     | 0x868    |        4 | Auto-extracted signal rx_store_brs from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_stuff_count`](#protocol_control_rx_store_stuff_count)                     | 0x86c    |        4 | Auto-extracted signal rx_store_stuff_count from protocol_control.vhd           |
+| can_bus.[`protocol_control_rx_shift_ena`](#protocol_control_rx_shift_ena)                                     | 0x870    |        4 | Auto-extracted signal rx_shift_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_shift_in_sel`](#protocol_control_rx_shift_in_sel)                               | 0x874    |        4 | Auto-extracted signal rx_shift_in_sel from protocol_control.vhd                |
+| can_bus.[`protocol_control_rec_is_rtr_i`](#protocol_control_rec_is_rtr_i)                                     | 0x878    |        4 | Auto-extracted signal rec_is_rtr_i from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rec_dlc_d`](#protocol_control_rec_dlc_d)                                           | 0x87c    |        4 | Auto-extracted signal rec_dlc_d from protocol_control.vhd                      |
+| can_bus.[`protocol_control_rec_dlc_q`](#protocol_control_rec_dlc_q)                                           | 0x880    |        4 | Auto-extracted signal rec_dlc_q from protocol_control.vhd                      |
+| can_bus.[`protocol_control_rec_frame_type_i`](#protocol_control_rec_frame_type_i)                             | 0x884    |        4 | Auto-extracted signal rec_frame_type_i from protocol_control.vhd               |
+| can_bus.[`protocol_control_ctrl_ctr_pload`](#protocol_control_ctrl_ctr_pload)                                 | 0x888    |        4 | Auto-extracted signal ctrl_ctr_pload from protocol_control.vhd                 |
+| can_bus.[`protocol_control_ctrl_ctr_pload_val`](#protocol_control_ctrl_ctr_pload_val)                         | 0x88c    |        4 | Auto-extracted signal ctrl_ctr_pload_val from protocol_control.vhd             |
+| can_bus.[`protocol_control_ctrl_ctr_ena`](#protocol_control_ctrl_ctr_ena)                                     | 0x890    |        4 | Auto-extracted signal ctrl_ctr_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_ctrl_ctr_zero`](#protocol_control_ctrl_ctr_zero)                                   | 0x894    |        4 | Auto-extracted signal ctrl_ctr_zero from protocol_control.vhd                  |
+| can_bus.[`protocol_control_ctrl_ctr_one`](#protocol_control_ctrl_ctr_one)                                     | 0x898    |        4 | Auto-extracted signal ctrl_ctr_one from protocol_control.vhd                   |
+| can_bus.[`protocol_control_ctrl_counted_byte`](#protocol_control_ctrl_counted_byte)                           | 0x89c    |        4 | Auto-extracted signal ctrl_counted_byte from protocol_control.vhd              |
+| can_bus.[`protocol_control_ctrl_counted_byte_index`](#protocol_control_ctrl_counted_byte_index)               | 0x8a0    |        4 | Auto-extracted signal ctrl_counted_byte_index from protocol_control.vhd        |
+| can_bus.[`protocol_control_ctrl_ctr_mem_index`](#protocol_control_ctrl_ctr_mem_index)                         | 0x8a4    |        4 | Auto-extracted signal ctrl_ctr_mem_index from protocol_control.vhd             |
+| can_bus.[`protocol_control_compl_ctr_ena`](#protocol_control_compl_ctr_ena)                                   | 0x8a8    |        4 | Auto-extracted signal compl_ctr_ena from protocol_control.vhd                  |
+| can_bus.[`protocol_control_reinteg_ctr_clr`](#protocol_control_reinteg_ctr_clr)                               | 0x8ac    |        4 | Auto-extracted signal reinteg_ctr_clr from protocol_control.vhd                |
+| can_bus.[`protocol_control_reinteg_ctr_enable`](#protocol_control_reinteg_ctr_enable)                         | 0x8b0    |        4 | Auto-extracted signal reinteg_ctr_enable from protocol_control.vhd             |
+| can_bus.[`protocol_control_reinteg_ctr_expired`](#protocol_control_reinteg_ctr_expired)                       | 0x8b4    |        4 | Auto-extracted signal reinteg_ctr_expired from protocol_control.vhd            |
+| can_bus.[`protocol_control_retr_ctr_clear`](#protocol_control_retr_ctr_clear)                                 | 0x8b8    |        4 | Auto-extracted signal retr_ctr_clear from protocol_control.vhd                 |
+| can_bus.[`protocol_control_retr_ctr_add`](#protocol_control_retr_ctr_add)                                     | 0x8bc    |        4 | Auto-extracted signal retr_ctr_add from protocol_control.vhd                   |
+| can_bus.[`protocol_control_retr_limit_reached`](#protocol_control_retr_limit_reached)                         | 0x8c0    |        4 | Auto-extracted signal retr_limit_reached from protocol_control.vhd             |
+| can_bus.[`protocol_control_form_err_i`](#protocol_control_form_err_i)                                         | 0x8c4    |        4 | Auto-extracted signal form_err_i from protocol_control.vhd                     |
+| can_bus.[`protocol_control_ack_err_i`](#protocol_control_ack_err_i)                                           | 0x8c8    |        4 | Auto-extracted signal ack_err_i from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_check`](#protocol_control_crc_check)                                           | 0x8cc    |        4 | Auto-extracted signal crc_check from protocol_control.vhd                      |
+| can_bus.[`protocol_control_bit_err_arb`](#protocol_control_bit_err_arb)                                       | 0x8d0    |        4 | Auto-extracted signal bit_err_arb from protocol_control.vhd                    |
+| can_bus.[`protocol_control_crc_match`](#protocol_control_crc_match)                                           | 0x8d4    |        4 | Auto-extracted signal crc_match from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_err_i`](#protocol_control_crc_err_i)                                           | 0x8d8    |        4 | Auto-extracted signal crc_err_i from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_clear_match_flag`](#protocol_control_crc_clear_match_flag)                     | 0x8dc    |        4 | Auto-extracted signal crc_clear_match_flag from protocol_control.vhd           |
+| can_bus.[`protocol_control_crc_src`](#protocol_control_crc_src)                                               | 0x8e0    |        4 | Auto-extracted signal crc_src from protocol_control.vhd                        |
+| can_bus.[`protocol_control_err_pos`](#protocol_control_err_pos)                                               | 0x8e4    |        4 | Auto-extracted signal err_pos from protocol_control.vhd                        |
+| can_bus.[`protocol_control_is_arbitration_i`](#protocol_control_is_arbitration_i)                             | 0x8e8    |        4 | Auto-extracted signal is_arbitration_i from protocol_control.vhd               |
+| can_bus.[`protocol_control_bit_err_enable`](#protocol_control_bit_err_enable)                                 | 0x8ec    |        4 | Auto-extracted signal bit_err_enable from protocol_control.vhd                 |
+| can_bus.[`protocol_control_tx_data_nbs_i`](#protocol_control_tx_data_nbs_i)                                   | 0x8f0    |        4 | Auto-extracted signal tx_data_nbs_i from protocol_control.vhd                  |
+| can_bus.[`protocol_control_rx_crc`](#protocol_control_rx_crc)                                                 | 0x8f4    |        4 | Auto-extracted signal rx_crc from protocol_control.vhd                         |
+| can_bus.[`protocol_control_rx_stuff_count`](#protocol_control_rx_stuff_count)                                 | 0x8f8    |        4 | Auto-extracted signal rx_stuff_count from protocol_control.vhd                 |
+| can_bus.[`protocol_control_fixed_stuff_i`](#protocol_control_fixed_stuff_i)                                   | 0x8fc    |        4 | Auto-extracted signal fixed_stuff_i from protocol_control.vhd                  |
+| can_bus.[`protocol_control_arbitration_lost_i`](#protocol_control_arbitration_lost_i)                         | 0x900    |        4 | Auto-extracted signal arbitration_lost_i from protocol_control.vhd             |
+| can_bus.[`protocol_control_alc_id_field`](#protocol_control_alc_id_field)                                     | 0x904    |        4 | Auto-extracted signal alc_id_field from protocol_control.vhd                   |
+| can_bus.[`protocol_control_drv_rom_ena`](#protocol_control_drv_rom_ena)                                       | 0x908    |        4 | Auto-extracted signal drv_rom_ena from protocol_control.vhd                    |
+| can_bus.[`protocol_control_fsm_state_reg_ce`](#protocol_control_fsm_state_reg_ce)                             | 0x90c    |        4 | Auto-extracted signal state_reg_ce from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_no_data_transmitter`](#protocol_control_fsm_no_data_transmitter)               | 0x910    |        4 | Auto-extracted signal no_data_transmitter from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_no_data_receiver`](#protocol_control_fsm_no_data_receiver)                     | 0x914    |        4 | Auto-extracted signal no_data_receiver from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_no_data_field`](#protocol_control_fsm_no_data_field)                           | 0x918    |        4 | Auto-extracted signal no_data_field from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_ctrl_ctr_pload_i`](#protocol_control_fsm_ctrl_ctr_pload_i)                     | 0x91c    |        4 | Auto-extracted signal ctrl_ctr_pload_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_ctrl_ctr_pload_unaliged`](#protocol_control_fsm_ctrl_ctr_pload_unaliged)       | 0x920    |        4 | Auto-extracted signal ctrl_ctr_pload_unaliged from protocol_control_fsm.vhd    |
+| can_bus.[`protocol_control_fsm_crc_use_21`](#protocol_control_fsm_crc_use_21)                                 | 0x924    |        4 | Auto-extracted signal crc_use_21 from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_crc_use_17`](#protocol_control_fsm_crc_use_17)                                 | 0x928    |        4 | Auto-extracted signal crc_use_17 from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_crc_src_i`](#protocol_control_fsm_crc_src_i)                                   | 0x92c    |        4 | Auto-extracted signal crc_src_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_crc_length_i`](#protocol_control_fsm_crc_length_i)                             | 0x930    |        4 | Auto-extracted signal crc_length_i from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_tran_data_length`](#protocol_control_fsm_tran_data_length)                     | 0x934    |        4 | Auto-extracted signal tran_data_length from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_rec_data_length`](#protocol_control_fsm_rec_data_length)                       | 0x938    |        4 | Auto-extracted signal rec_data_length from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_rec_data_length_c`](#protocol_control_fsm_rec_data_length_c)                   | 0x93c    |        4 | Auto-extracted signal rec_data_length_c from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_data_length_c`](#protocol_control_fsm_data_length_c)                           | 0x940    |        4 | Auto-extracted signal data_length_c from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_data_length_shifted_c`](#protocol_control_fsm_data_length_shifted_c)           | 0x944    |        4 | Auto-extracted signal data_length_shifted_c from protocol_control_fsm.vhd      |
+| can_bus.[`protocol_control_fsm_data_length_bits_c`](#protocol_control_fsm_data_length_bits_c)                 | 0x948    |        4 | Auto-extracted signal data_length_bits_c from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_is_fd_frame`](#protocol_control_fsm_is_fd_frame)                               | 0x94c    |        4 | Auto-extracted signal is_fd_frame from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_frame_start`](#protocol_control_fsm_frame_start)                               | 0x950    |        4 | Auto-extracted signal frame_start from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_tx_frame_ready`](#protocol_control_fsm_tx_frame_ready)                         | 0x954    |        4 | Auto-extracted signal tx_frame_ready from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_ide_is_arbitration`](#protocol_control_fsm_ide_is_arbitration)                 | 0x958    |        4 | Auto-extracted signal ide_is_arbitration from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_arbitration_lost_condition`](#protocol_control_fsm_arbitration_lost_condition) | 0x95c    |        4 | Auto-extracted signal arbitration_lost_condition from protocol_control_fsm.vhd |
+| can_bus.[`protocol_control_fsm_arbitration_lost_i`](#protocol_control_fsm_arbitration_lost_i)                 | 0x960    |        4 | Auto-extracted signal arbitration_lost_i from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_tx_failed`](#protocol_control_fsm_tx_failed)                                   | 0x964    |        4 | Auto-extracted signal tx_failed from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_store_metadata_d`](#protocol_control_fsm_store_metadata_d)                     | 0x968    |        4 | Auto-extracted signal store_metadata_d from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_store_data_d`](#protocol_control_fsm_store_data_d)                             | 0x96c    |        4 | Auto-extracted signal store_data_d from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_rec_valid_d`](#protocol_control_fsm_rec_valid_d)                               | 0x970    |        4 | Auto-extracted signal rec_valid_d from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_rec_abort_d`](#protocol_control_fsm_rec_abort_d)                               | 0x974    |        4 | Auto-extracted signal rec_abort_d from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_go_to_suspend`](#protocol_control_fsm_go_to_suspend)                           | 0x978    |        4 | Auto-extracted signal go_to_suspend from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_go_to_stuff_count`](#protocol_control_fsm_go_to_stuff_count)                   | 0x97c    |        4 | Auto-extracted signal go_to_stuff_count from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_store_base_id_i`](#protocol_control_fsm_rx_store_base_id_i)                 | 0x980    |        4 | Auto-extracted signal rx_store_base_id_i from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_rx_store_ext_id_i`](#protocol_control_fsm_rx_store_ext_id_i)                   | 0x984    |        4 | Auto-extracted signal rx_store_ext_id_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_store_ide_i`](#protocol_control_fsm_rx_store_ide_i)                         | 0x988    |        4 | Auto-extracted signal rx_store_ide_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_rtr_i`](#protocol_control_fsm_rx_store_rtr_i)                         | 0x98c    |        4 | Auto-extracted signal rx_store_rtr_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_edl_i`](#protocol_control_fsm_rx_store_edl_i)                         | 0x990    |        4 | Auto-extracted signal rx_store_edl_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_dlc_i`](#protocol_control_fsm_rx_store_dlc_i)                         | 0x994    |        4 | Auto-extracted signal rx_store_dlc_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_esi_i`](#protocol_control_fsm_rx_store_esi_i)                         | 0x998    |        4 | Auto-extracted signal rx_store_esi_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_brs_i`](#protocol_control_fsm_rx_store_brs_i)                         | 0x99c    |        4 | Auto-extracted signal rx_store_brs_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_stuff_count_i`](#protocol_control_fsm_rx_store_stuff_count_i)         | 0x9a0    |        4 | Auto-extracted signal rx_store_stuff_count_i from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_rx_clear_i`](#protocol_control_fsm_rx_clear_i)                                 | 0x9a4    |        4 | Auto-extracted signal rx_clear_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_tx_load_base_id_i`](#protocol_control_fsm_tx_load_base_id_i)                   | 0x9a8    |        4 | Auto-extracted signal tx_load_base_id_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_load_ext_id_i`](#protocol_control_fsm_tx_load_ext_id_i)                     | 0x9ac    |        4 | Auto-extracted signal tx_load_ext_id_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_tx_load_dlc_i`](#protocol_control_fsm_tx_load_dlc_i)                           | 0x9b0    |        4 | Auto-extracted signal tx_load_dlc_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_tx_load_data_word_i`](#protocol_control_fsm_tx_load_data_word_i)               | 0x9b4    |        4 | Auto-extracted signal tx_load_data_word_i from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_tx_load_stuff_count_i`](#protocol_control_fsm_tx_load_stuff_count_i)           | 0x9b8    |        4 | Auto-extracted signal tx_load_stuff_count_i from protocol_control_fsm.vhd      |
+| can_bus.[`protocol_control_fsm_tx_load_crc_i`](#protocol_control_fsm_tx_load_crc_i)                           | 0x9bc    |        4 | Auto-extracted signal tx_load_crc_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_tx_shift_ena_i`](#protocol_control_fsm_tx_shift_ena_i)                         | 0x9c0    |        4 | Auto-extracted signal tx_shift_ena_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_form_err_i`](#protocol_control_fsm_form_err_i)                                 | 0x9c4    |        4 | Auto-extracted signal form_err_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_ack_err_i`](#protocol_control_fsm_ack_err_i)                                   | 0x9c8    |        4 | Auto-extracted signal ack_err_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_ack_err_flag`](#protocol_control_fsm_ack_err_flag)                             | 0x9cc    |        4 | Auto-extracted signal ack_err_flag from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_ack_err_flag_clr`](#protocol_control_fsm_ack_err_flag_clr)                     | 0x9d0    |        4 | Auto-extracted signal ack_err_flag_clr from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_crc_err_i`](#protocol_control_fsm_crc_err_i)                                   | 0x9d4    |        4 | Auto-extracted signal crc_err_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_bit_err_arb_i`](#protocol_control_fsm_bit_err_arb_i)                           | 0x9d8    |        4 | Auto-extracted signal bit_err_arb_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_switch_data`](#protocol_control_fsm_sp_control_switch_data)         | 0x9dc    |        4 | Auto-extracted signal sp_control_switch_data from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_sp_control_switch_nominal`](#protocol_control_fsm_sp_control_switch_nominal)   | 0x9e0    |        4 | Auto-extracted signal sp_control_switch_nominal from protocol_control_fsm.vhd  |
+| can_bus.[`protocol_control_fsm_switch_to_ssp`](#protocol_control_fsm_switch_to_ssp)                           | 0x9e4    |        4 | Auto-extracted signal switch_to_ssp from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_ce`](#protocol_control_fsm_sp_control_ce)                           | 0x9e8    |        4 | Auto-extracted signal sp_control_ce from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_d`](#protocol_control_fsm_sp_control_d)                             | 0x9ec    |        4 | Auto-extracted signal sp_control_d from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_sp_control_q_i`](#protocol_control_fsm_sp_control_q_i)                         | 0x9f0    |        4 | Auto-extracted signal sp_control_q_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_ssp_reset_i`](#protocol_control_fsm_ssp_reset_i)                               | 0x9f4    |        4 | Auto-extracted signal ssp_reset_i from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_sync_control_d`](#protocol_control_fsm_sync_control_d)                         | 0x9f8    |        4 | Auto-extracted signal sync_control_d from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_sync_control_q`](#protocol_control_fsm_sync_control_q)                         | 0x9fc    |        4 | Auto-extracted signal sync_control_q from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_perform_hsync`](#protocol_control_fsm_perform_hsync)                           | 0xa00    |        4 | Auto-extracted signal perform_hsync from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_primary_err_i`](#protocol_control_fsm_primary_err_i)                           | 0xa04    |        4 | Auto-extracted signal primary_err_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_err_delim_late_i`](#protocol_control_fsm_err_delim_late_i)                     | 0xa08    |        4 | Auto-extracted signal err_delim_late_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_set_err_active_i`](#protocol_control_fsm_set_err_active_i)                     | 0xa0c    |        4 | Auto-extracted signal set_err_active_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_set_transmitter_i`](#protocol_control_fsm_set_transmitter_i)                   | 0xa10    |        4 | Auto-extracted signal set_transmitter_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_set_receiver_i`](#protocol_control_fsm_set_receiver_i)                         | 0xa14    |        4 | Auto-extracted signal set_receiver_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_set_idle_i`](#protocol_control_fsm_set_idle_i)                                 | 0xa18    |        4 | Auto-extracted signal set_idle_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_first_err_delim_d`](#protocol_control_fsm_first_err_delim_d)                   | 0xa1c    |        4 | Auto-extracted signal first_err_delim_d from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_first_err_delim_q`](#protocol_control_fsm_first_err_delim_q)                   | 0xa20    |        4 | Auto-extracted signal first_err_delim_q from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_stuff_enable_set`](#protocol_control_fsm_stuff_enable_set)                     | 0xa24    |        4 | Auto-extracted signal stuff_enable_set from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_stuff_enable_clear`](#protocol_control_fsm_stuff_enable_clear)                 | 0xa28    |        4 | Auto-extracted signal stuff_enable_clear from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_destuff_enable_set`](#protocol_control_fsm_destuff_enable_set)                 | 0xa2c    |        4 | Auto-extracted signal destuff_enable_set from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_destuff_enable_clear`](#protocol_control_fsm_destuff_enable_clear)             | 0xa30    |        4 | Auto-extracted signal destuff_enable_clear from protocol_control_fsm.vhd       |
+| can_bus.[`protocol_control_fsm_bit_err_disable`](#protocol_control_fsm_bit_err_disable)                       | 0xa34    |        4 | Auto-extracted signal bit_err_disable from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_bit_err_disable_receiver`](#protocol_control_fsm_bit_err_disable_receiver)     | 0xa38    |        4 | Auto-extracted signal bit_err_disable_receiver from protocol_control_fsm.vhd   |
+| can_bus.[`protocol_control_fsm_sof_pulse_i`](#protocol_control_fsm_sof_pulse_i)                               | 0xa3c    |        4 | Auto-extracted signal sof_pulse_i from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_compl_ctr_ena_i`](#protocol_control_fsm_compl_ctr_ena_i)                       | 0xa40    |        4 | Auto-extracted signal compl_ctr_ena_i from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_tick_state_reg`](#protocol_control_fsm_tick_state_reg)                         | 0xa44    |        4 | Auto-extracted signal tick_state_reg from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_br_shifted_i`](#protocol_control_fsm_br_shifted_i)                             | 0xa48    |        4 | Auto-extracted signal br_shifted_i from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_is_arbitration_i`](#protocol_control_fsm_is_arbitration_i)                     | 0xa4c    |        4 | Auto-extracted signal is_arbitration_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_crc_spec_enable_i`](#protocol_control_fsm_crc_spec_enable_i)                   | 0xa50    |        4 | Auto-extracted signal crc_spec_enable_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_load_init_vect_i`](#protocol_control_fsm_load_init_vect_i)                     | 0xa54    |        4 | Auto-extracted signal load_init_vect_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_drv_bus_off_reset_q`](#protocol_control_fsm_drv_bus_off_reset_q)               | 0xa58    |        4 | Auto-extracted signal drv_bus_off_reset_q from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_retr_ctr_clear_i`](#protocol_control_fsm_retr_ctr_clear_i)                     | 0xa5c    |        4 | Auto-extracted signal retr_ctr_clear_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_i`](#protocol_control_fsm_retr_ctr_add_i)                         | 0xa60    |        4 | Auto-extracted signal retr_ctr_add_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_decrement_rec_i`](#protocol_control_fsm_decrement_rec_i)                       | 0xa64    |        4 | Auto-extracted signal decrement_rec_i from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_block`](#protocol_control_fsm_retr_ctr_add_block)                 | 0xa68    |        4 | Auto-extracted signal retr_ctr_add_block from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_block_clr`](#protocol_control_fsm_retr_ctr_add_block_clr)         | 0xa6c    |        4 | Auto-extracted signal retr_ctr_add_block_clr from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_block_txtb_unlock`](#protocol_control_fsm_block_txtb_unlock)                   | 0xa70    |        4 | Auto-extracted signal block_txtb_unlock from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_frame_no_sof_d`](#protocol_control_fsm_tx_frame_no_sof_d)                   | 0xa74    |        4 | Auto-extracted signal tx_frame_no_sof_d from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_frame_no_sof_q`](#protocol_control_fsm_tx_frame_no_sof_q)                   | 0xa78    |        4 | Auto-extracted signal tx_frame_no_sof_q from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_ctrl_signal_upd`](#protocol_control_fsm_ctrl_signal_upd)                       | 0xa7c    |        4 | Auto-extracted signal ctrl_signal_upd from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_clr_bus_off_rst_flg`](#protocol_control_fsm_clr_bus_off_rst_flg)               | 0xa80    |        4 | Auto-extracted signal clr_bus_off_rst_flg from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_pex_on_fdf_enable`](#protocol_control_fsm_pex_on_fdf_enable)                   | 0xa84    |        4 | Auto-extracted signal pex_on_fdf_enable from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_pex_on_res_enable`](#protocol_control_fsm_pex_on_res_enable)                   | 0xa88    |        4 | Auto-extracted signal pex_on_res_enable from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_data_nbs_prev`](#protocol_control_fsm_rx_data_nbs_prev)                     | 0xa8c    |        4 | Auto-extracted signal rx_data_nbs_prev from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_pexs_set`](#protocol_control_fsm_pexs_set)                                     | 0xa90    |        4 | Auto-extracted signal pexs_set from protocol_control_fsm.vhd                   |
+| can_bus.[`protocol_control_fsm_tran_frame_type_i`](#protocol_control_fsm_tran_frame_type_i)                   | 0xa94    |        4 | Auto-extracted signal tran_frame_type_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_txtb_clk_en_d`](#protocol_control_fsm_txtb_clk_en_d)                           | 0xa98    |        4 | Auto-extracted signal txtb_clk_en_d from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_txtb_clk_en_q`](#protocol_control_fsm_txtb_clk_en_q)                           | 0xa9c    |        4 | Auto-extracted signal txtb_clk_en_q from protocol_control_fsm.vhd              |
+| can_bus.[`reintegration_counter_reinteg_ctr_ce`](#reintegration_counter_reinteg_ctr_ce)                       | 0xaa0    |        4 | Auto-extracted signal reinteg_ctr_ce from reintegration_counter.vhd            |
+| can_bus.[`retransmitt_counter_retr_ctr_ce`](#retransmitt_counter_retr_ctr_ce)                                 | 0xaa4    |        4 | Auto-extracted signal retr_ctr_ce from retransmitt_counter.vhd                 |
+| can_bus.[`rst_sync_rff`](#rst_sync_rff)                                                                       | 0xaa8    |        4 | Auto-extracted signal rff from rst_sync.vhd                                    |
+| can_bus.[`rx_buffer_drv_erase_rx`](#rx_buffer_drv_erase_rx)                                                   | 0xaac    |        4 | Auto-extracted signal drv_erase_rx from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_drv_read_start`](#rx_buffer_drv_read_start)                                               | 0xab0    |        4 | Auto-extracted signal drv_read_start from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_drv_clr_ovr`](#rx_buffer_drv_clr_ovr)                                                     | 0xab4    |        4 | Auto-extracted signal drv_clr_ovr from rx_buffer.vhd                           |
+| can_bus.[`rx_buffer_drv_rtsopt`](#rx_buffer_drv_rtsopt)                                                       | 0xab8    |        4 | Auto-extracted signal drv_rtsopt from rx_buffer.vhd                            |
+| can_bus.[`rx_buffer_read_pointer`](#rx_buffer_read_pointer)                                                   | 0xabc    |        4 | Auto-extracted signal read_pointer from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_read_pointer_inc_1`](#rx_buffer_read_pointer_inc_1)                                       | 0xac0    |        4 | Auto-extracted signal read_pointer_inc_1 from rx_buffer.vhd                    |
+| can_bus.[`rx_buffer_write_pointer`](#rx_buffer_write_pointer)                                                 | 0xac4    |        4 | Auto-extracted signal write_pointer from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_write_pointer_raw`](#rx_buffer_write_pointer_raw)                                         | 0xac8    |        4 | Auto-extracted signal write_pointer_raw from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_write_pointer_ts`](#rx_buffer_write_pointer_ts)                                           | 0xacc    |        4 | Auto-extracted signal write_pointer_ts from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_rx_mem_free_i`](#rx_buffer_rx_mem_free_i)                                                 | 0xad0    |        4 | Auto-extracted signal rx_mem_free_i from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_memory_write_data`](#rx_buffer_memory_write_data)                                         | 0xad4    |        4 | Auto-extracted signal memory_write_data from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_data_overrun_flg`](#rx_buffer_data_overrun_flg)                                           | 0xad8    |        4 | Auto-extracted signal data_overrun_flg from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_data_overrun_i`](#rx_buffer_data_overrun_i)                                               | 0xadc    |        4 | Auto-extracted signal data_overrun_i from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_overrun_condition`](#rx_buffer_overrun_condition)                                         | 0xae0    |        4 | Auto-extracted signal overrun_condition from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_rx_empty_i`](#rx_buffer_rx_empty_i)                                                       | 0xae4    |        4 | Auto-extracted signal rx_empty_i from rx_buffer.vhd                            |
+| can_bus.[`rx_buffer_is_free_word`](#rx_buffer_is_free_word)                                                   | 0xae8    |        4 | Auto-extracted signal is_free_word from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_commit_rx_frame`](#rx_buffer_commit_rx_frame)                                             | 0xaec    |        4 | Auto-extracted signal commit_rx_frame from rx_buffer.vhd                       |
+| can_bus.[`rx_buffer_commit_overrun_abort`](#rx_buffer_commit_overrun_abort)                                   | 0xaf0    |        4 | Auto-extracted signal commit_overrun_abort from rx_buffer.vhd                  |
+| can_bus.[`rx_buffer_read_increment`](#rx_buffer_read_increment)                                               | 0xaf4    |        4 | Auto-extracted signal read_increment from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_write_raw_OK`](#rx_buffer_write_raw_ok)                                                   | 0xaf8    |        4 | Auto-extracted signal write_raw_OK from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_write_raw_intent`](#rx_buffer_write_raw_intent)                                           | 0xafc    |        4 | Auto-extracted signal write_raw_intent from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_write_ts`](#rx_buffer_write_ts)                                                           | 0xb00    |        4 | Auto-extracted signal write_ts from rx_buffer.vhd                              |
+| can_bus.[`rx_buffer_stored_ts`](#rx_buffer_stored_ts)                                                         | 0xb04    |        4 | Auto-extracted signal stored_ts from rx_buffer.vhd                             |
+| can_bus.[`rx_buffer_data_selector`](#rx_buffer_data_selector)                                                 | 0xb08    |        4 | Auto-extracted signal data_selector from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_store_ts_wr_ptr`](#rx_buffer_store_ts_wr_ptr)                                             | 0xb0c    |        4 | Auto-extracted signal store_ts_wr_ptr from rx_buffer.vhd                       |
+| can_bus.[`rx_buffer_inc_ts_wr_ptr`](#rx_buffer_inc_ts_wr_ptr)                                                 | 0xb10    |        4 | Auto-extracted signal inc_ts_wr_ptr from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_reset_overrun_flag`](#rx_buffer_reset_overrun_flag)                                       | 0xb14    |        4 | Auto-extracted signal reset_overrun_flag from rx_buffer.vhd                    |
+| can_bus.[`rx_buffer_frame_form_w`](#rx_buffer_frame_form_w)                                                   | 0xb18    |        4 | Auto-extracted signal frame_form_w from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_timestamp_capture`](#rx_buffer_timestamp_capture)                                         | 0xb1c    |        4 | Auto-extracted signal timestamp_capture from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_timestamp_capture_ce`](#rx_buffer_timestamp_capture_ce)                                   | 0xb20    |        4 | Auto-extracted signal timestamp_capture_ce from rx_buffer.vhd                  |
+| can_bus.[`rx_buffer_RAM_write`](#rx_buffer_ram_write)                                                         | 0xb24    |        4 | Auto-extracted signal RAM_write from rx_buffer.vhd                             |
+| can_bus.[`rx_buffer_RAM_data_out`](#rx_buffer_ram_data_out)                                                   | 0xb28    |        4 | Auto-extracted signal RAM_data_out from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_RAM_write_address`](#rx_buffer_ram_write_address)                                         | 0xb2c    |        4 | Auto-extracted signal RAM_write_address from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_RAM_read_address`](#rx_buffer_ram_read_address)                                           | 0xb30    |        4 | Auto-extracted signal RAM_read_address from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_rx_buf_res_n_d`](#rx_buffer_rx_buf_res_n_d)                                               | 0xb34    |        4 | Auto-extracted signal rx_buf_res_n_d from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_rx_buf_res_n_q`](#rx_buffer_rx_buf_res_n_q)                                               | 0xb38    |        4 | Auto-extracted signal rx_buf_res_n_q from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_rx_buf_res_n_q_scan`](#rx_buffer_rx_buf_res_n_q_scan)                                     | 0xb3c    |        4 | Auto-extracted signal rx_buf_res_n_q_scan from rx_buffer.vhd                   |
+| can_bus.[`rx_buffer_rx_buf_ram_clk_en`](#rx_buffer_rx_buf_ram_clk_en)                                         | 0xb40    |        4 | Auto-extracted signal rx_buf_ram_clk_en from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_clk_ram`](#rx_buffer_clk_ram)                                                             | 0xb44    |        4 | Auto-extracted signal clk_ram from rx_buffer.vhd                               |
+| can_bus.[`rx_buffer_fsm_rx_fsm_ce`](#rx_buffer_fsm_rx_fsm_ce)                                                 | 0xb48    |        4 | Auto-extracted signal rx_fsm_ce from rx_buffer_fsm.vhd                         |
+| can_bus.[`rx_buffer_fsm_cmd_join`](#rx_buffer_fsm_cmd_join)                                                   | 0xb4c    |        4 | Auto-extracted signal cmd_join from rx_buffer_fsm.vhd                          |
+| can_bus.[`rx_buffer_pointers_write_pointer_raw_ce`](#rx_buffer_pointers_write_pointer_raw_ce)                 | 0xb50    |        4 | Auto-extracted signal write_pointer_raw_ce from rx_buffer_pointers.vhd         |
+| can_bus.[`rx_buffer_pointers_write_pointer_ts_ce`](#rx_buffer_pointers_write_pointer_ts_ce)                   | 0xb54    |        4 | Auto-extracted signal write_pointer_ts_ce from rx_buffer_pointers.vhd          |
+| can_bus.[`rx_buffer_ram_port_a_address_i`](#rx_buffer_ram_port_a_address_i)                                   | 0xb58    |        4 | Auto-extracted signal port_a_address_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_a_write_i`](#rx_buffer_ram_port_a_write_i)                                       | 0xb5c    |        4 | Auto-extracted signal port_a_write_i from rx_buffer_ram.vhd                    |
+| can_bus.[`rx_buffer_ram_port_a_data_in_i`](#rx_buffer_ram_port_a_data_in_i)                                   | 0xb60    |        4 | Auto-extracted signal port_a_data_in_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_b_address_i`](#rx_buffer_ram_port_b_address_i)                                   | 0xb64    |        4 | Auto-extracted signal port_b_address_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_b_data_out_i`](#rx_buffer_ram_port_b_data_out_i)                                 | 0xb68    |        4 | Auto-extracted signal port_b_data_out_i from rx_buffer_ram.vhd                 |
+| can_bus.[`rx_buffer_ram_tst_ena`](#rx_buffer_ram_tst_ena)                                                     | 0xb6c    |        4 | Auto-extracted signal tst_ena from rx_buffer_ram.vhd                           |
+| can_bus.[`rx_buffer_ram_tst_addr`](#rx_buffer_ram_tst_addr)                                                   | 0xb70    |        4 | Auto-extracted signal tst_addr from rx_buffer_ram.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_d`](#rx_shift_reg_res_n_i_d)                                                   | 0xb74    |        4 | Auto-extracted signal res_n_i_d from rx_shift_reg.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_q`](#rx_shift_reg_res_n_i_q)                                                   | 0xb78    |        4 | Auto-extracted signal res_n_i_q from rx_shift_reg.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_q_scan`](#rx_shift_reg_res_n_i_q_scan)                                         | 0xb7c    |        4 | Auto-extracted signal res_n_i_q_scan from rx_shift_reg.vhd                     |
+| can_bus.[`rx_shift_reg_rx_shift_reg_q`](#rx_shift_reg_rx_shift_reg_q)                                         | 0xb80    |        4 | Auto-extracted signal rx_shift_reg_q from rx_shift_reg.vhd                     |
+| can_bus.[`rx_shift_reg_rx_shift_cmd`](#rx_shift_reg_rx_shift_cmd)                                             | 0xb84    |        4 | Auto-extracted signal rx_shift_cmd from rx_shift_reg.vhd                       |
+| can_bus.[`rx_shift_reg_rx_shift_in_sel_demuxed`](#rx_shift_reg_rx_shift_in_sel_demuxed)                       | 0xb88    |        4 | Auto-extracted signal rx_shift_in_sel_demuxed from rx_shift_reg.vhd            |
+| can_bus.[`rx_shift_reg_rec_is_rtr_i`](#rx_shift_reg_rec_is_rtr_i)                                             | 0xb8c    |        4 | Auto-extracted signal rec_is_rtr_i from rx_shift_reg.vhd                       |
+| can_bus.[`rx_shift_reg_rec_frame_type_i`](#rx_shift_reg_rec_frame_type_i)                                     | 0xb90    |        4 | Auto-extracted signal rec_frame_type_i from rx_shift_reg.vhd                   |
+| can_bus.[`sample_mux_sample`](#sample_mux_sample)                                                             | 0xb94    |        4 | Auto-extracted signal sample from sample_mux.vhd                               |
+| can_bus.[`sample_mux_prev_sample_d`](#sample_mux_prev_sample_d)                                               | 0xb98    |        4 | Auto-extracted signal prev_sample_d from sample_mux.vhd                        |
+| can_bus.[`sample_mux_prev_sample_q`](#sample_mux_prev_sample_q)                                               | 0xb9c    |        4 | Auto-extracted signal prev_sample_q from sample_mux.vhd                        |
+| can_bus.[`segment_end_detector_req_input`](#segment_end_detector_req_input)                                   | 0xba0    |        4 | Auto-extracted signal req_input from segment_end_detector.vhd                  |
+| can_bus.[`segment_end_detector_segm_end_req_capt_d`](#segment_end_detector_segm_end_req_capt_d)               | 0xba4    |        4 | Auto-extracted signal segm_end_req_capt_d from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_segm_end_req_capt_q`](#segment_end_detector_segm_end_req_capt_q)               | 0xba8    |        4 | Auto-extracted signal segm_end_req_capt_q from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_segm_end_req_capt_ce`](#segment_end_detector_segm_end_req_capt_ce)             | 0xbac    |        4 | Auto-extracted signal segm_end_req_capt_ce from segment_end_detector.vhd       |
+| can_bus.[`segment_end_detector_segm_end_req_capt_clr`](#segment_end_detector_segm_end_req_capt_clr)           | 0xbb0    |        4 | Auto-extracted signal segm_end_req_capt_clr from segment_end_detector.vhd      |
+| can_bus.[`segment_end_detector_segm_end_req_capt_dq`](#segment_end_detector_segm_end_req_capt_dq)             | 0xbb4    |        4 | Auto-extracted signal segm_end_req_capt_dq from segment_end_detector.vhd       |
+| can_bus.[`segment_end_detector_segm_end_nbt_valid`](#segment_end_detector_segm_end_nbt_valid)                 | 0xbb8    |        4 | Auto-extracted signal segm_end_nbt_valid from segment_end_detector.vhd         |
+| can_bus.[`segment_end_detector_segm_end_dbt_valid`](#segment_end_detector_segm_end_dbt_valid)                 | 0xbbc    |        4 | Auto-extracted signal segm_end_dbt_valid from segment_end_detector.vhd         |
+| can_bus.[`segment_end_detector_segm_end_nbt_dbt_valid`](#segment_end_detector_segm_end_nbt_dbt_valid)         | 0xbc0    |        4 | Auto-extracted signal segm_end_nbt_dbt_valid from segment_end_detector.vhd     |
+| can_bus.[`segment_end_detector_tseg1_end_req_valid`](#segment_end_detector_tseg1_end_req_valid)               | 0xbc4    |        4 | Auto-extracted signal tseg1_end_req_valid from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_tseg2_end_req_valid`](#segment_end_detector_tseg2_end_req_valid)               | 0xbc8    |        4 | Auto-extracted signal tseg2_end_req_valid from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_h_sync_valid_i`](#segment_end_detector_h_sync_valid_i)                         | 0xbcc    |        4 | Auto-extracted signal h_sync_valid_i from segment_end_detector.vhd             |
+| can_bus.[`segment_end_detector_segment_end_i`](#segment_end_detector_segment_end_i)                           | 0xbd0    |        4 | Auto-extracted signal segment_end_i from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_nbt_tq_active`](#segment_end_detector_nbt_tq_active)                           | 0xbd4    |        4 | Auto-extracted signal nbt_tq_active from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_dbt_tq_active`](#segment_end_detector_dbt_tq_active)                           | 0xbd8    |        4 | Auto-extracted signal dbt_tq_active from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_bt_ctr_clear_i`](#segment_end_detector_bt_ctr_clear_i)                         | 0xbdc    |        4 | Auto-extracted signal bt_ctr_clear_i from segment_end_detector.vhd             |
+| can_bus.[`shift_reg_shift_regs`](#shift_reg_shift_regs)                                                       | 0xbe0    |        4 | Auto-extracted signal shift_regs from shift_reg.vhd                            |
+| can_bus.[`shift_reg_next_shift_reg_val`](#shift_reg_next_shift_reg_val)                                       | 0xbe4    |        4 | Auto-extracted signal next_shift_reg_val from shift_reg.vhd                    |
+| can_bus.[`shift_reg_byte_shift_reg_in`](#shift_reg_byte_shift_reg_in)                                         | 0xbe8    |        4 | Auto-extracted signal shift_reg_in from shift_reg_byte.vhd                     |
+| can_bus.[`shift_reg_preload_shift_regs`](#shift_reg_preload_shift_regs)                                       | 0xbec    |        4 | Auto-extracted signal shift_regs from shift_reg_preload.vhd                    |
+| can_bus.[`shift_reg_preload_next_shift_reg_val`](#shift_reg_preload_next_shift_reg_val)                       | 0xbf0    |        4 | Auto-extracted signal next_shift_reg_val from shift_reg_preload.vhd            |
+| can_bus.[`sig_sync_rff`](#sig_sync_rff)                                                                       | 0xbf4    |        4 | Auto-extracted signal rff from sig_sync.vhd                                    |
+| can_bus.[`ssp_generator_btmc_d`](#ssp_generator_btmc_d)                                                       | 0xbf8    |        4 | Auto-extracted signal btmc_d from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_btmc_q`](#ssp_generator_btmc_q)                                                       | 0xbfc    |        4 | Auto-extracted signal btmc_q from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_btmc_add`](#ssp_generator_btmc_add)                                                   | 0xc00    |        4 | Auto-extracted signal btmc_add from ssp_generator.vhd                          |
+| can_bus.[`ssp_generator_btmc_ce`](#ssp_generator_btmc_ce)                                                     | 0xc04    |        4 | Auto-extracted signal btmc_ce from ssp_generator.vhd                           |
+| can_bus.[`ssp_generator_btmc_meas_running_d`](#ssp_generator_btmc_meas_running_d)                             | 0xc08    |        4 | Auto-extracted signal btmc_meas_running_d from ssp_generator.vhd               |
+| can_bus.[`ssp_generator_btmc_meas_running_q`](#ssp_generator_btmc_meas_running_q)                             | 0xc0c    |        4 | Auto-extracted signal btmc_meas_running_q from ssp_generator.vhd               |
+| can_bus.[`ssp_generator_sspc_d`](#ssp_generator_sspc_d)                                                       | 0xc10    |        4 | Auto-extracted signal sspc_d from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_sspc_q`](#ssp_generator_sspc_q)                                                       | 0xc14    |        4 | Auto-extracted signal sspc_q from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_sspc_ce`](#ssp_generator_sspc_ce)                                                     | 0xc18    |        4 | Auto-extracted signal sspc_ce from ssp_generator.vhd                           |
+| can_bus.[`ssp_generator_sspc_expired`](#ssp_generator_sspc_expired)                                           | 0xc1c    |        4 | Auto-extracted signal sspc_expired from ssp_generator.vhd                      |
+| can_bus.[`ssp_generator_sspc_threshold`](#ssp_generator_sspc_threshold)                                       | 0xc20    |        4 | Auto-extracted signal sspc_threshold from ssp_generator.vhd                    |
+| can_bus.[`ssp_generator_sspc_add`](#ssp_generator_sspc_add)                                                   | 0xc24    |        4 | Auto-extracted signal sspc_add from ssp_generator.vhd                          |
+| can_bus.[`ssp_generator_first_ssp_d`](#ssp_generator_first_ssp_d)                                             | 0xc28    |        4 | Auto-extracted signal first_ssp_d from ssp_generator.vhd                       |
+| can_bus.[`ssp_generator_first_ssp_q`](#ssp_generator_first_ssp_q)                                             | 0xc2c    |        4 | Auto-extracted signal first_ssp_q from ssp_generator.vhd                       |
+| can_bus.[`ssp_generator_sspc_ena_d`](#ssp_generator_sspc_ena_d)                                               | 0xc30    |        4 | Auto-extracted signal sspc_ena_d from ssp_generator.vhd                        |
+| can_bus.[`ssp_generator_sspc_ena_q`](#ssp_generator_sspc_ena_q)                                               | 0xc34    |        4 | Auto-extracted signal sspc_ena_q from ssp_generator.vhd                        |
+| can_bus.[`ssp_generator_ssp_delay_padded`](#ssp_generator_ssp_delay_padded)                                   | 0xc38    |        4 | Auto-extracted signal ssp_delay_padded from ssp_generator.vhd                  |
+| can_bus.[`synchronisation_checker_resync_edge`](#synchronisation_checker_resync_edge)                         | 0xc3c    |        4 | Auto-extracted signal resync_edge from synchronisation_checker.vhd             |
+| can_bus.[`synchronisation_checker_h_sync_edge`](#synchronisation_checker_h_sync_edge)                         | 0xc40    |        4 | Auto-extracted signal h_sync_edge from synchronisation_checker.vhd             |
+| can_bus.[`synchronisation_checker_h_or_re_sync_edge`](#synchronisation_checker_h_or_re_sync_edge)             | 0xc44    |        4 | Auto-extracted signal h_or_re_sync_edge from synchronisation_checker.vhd       |
+| can_bus.[`synchronisation_checker_sync_flag`](#synchronisation_checker_sync_flag)                             | 0xc48    |        4 | Auto-extracted signal sync_flag from synchronisation_checker.vhd               |
+| can_bus.[`synchronisation_checker_sync_flag_ce`](#synchronisation_checker_sync_flag_ce)                       | 0xc4c    |        4 | Auto-extracted signal sync_flag_ce from synchronisation_checker.vhd            |
+| can_bus.[`synchronisation_checker_sync_flag_nxt`](#synchronisation_checker_sync_flag_nxt)                     | 0xc50    |        4 | Auto-extracted signal sync_flag_nxt from synchronisation_checker.vhd           |
+| can_bus.[`test_registers_reg_map_reg_sel`](#test_registers_reg_map_reg_sel)                                   | 0xc54    |        4 | Auto-extracted signal reg_sel from test_registers_reg_map.vhd                  |
+| can_bus.[`test_registers_reg_map_read_data_mux_in`](#test_registers_reg_map_read_data_mux_in)                 | 0xc58    |        4 | Auto-extracted signal read_data_mux_in from test_registers_reg_map.vhd         |
+| can_bus.[`test_registers_reg_map_read_data_mask_n`](#test_registers_reg_map_read_data_mask_n)                 | 0xc5c    |        4 | Auto-extracted signal read_data_mask_n from test_registers_reg_map.vhd         |
+| can_bus.[`test_registers_reg_map_read_mux_ena`](#test_registers_reg_map_read_mux_ena)                         | 0xc60    |        4 | Auto-extracted signal read_mux_ena from test_registers_reg_map.vhd             |
+| can_bus.[`trigger_generator_rx_trig_req_q`](#trigger_generator_rx_trig_req_q)                                 | 0xc64    |        4 | Auto-extracted signal rx_trig_req_q from trigger_generator.vhd                 |
+| can_bus.[`trigger_generator_tx_trig_req_flag_d`](#trigger_generator_tx_trig_req_flag_d)                       | 0xc68    |        4 | Auto-extracted signal tx_trig_req_flag_d from trigger_generator.vhd            |
+| can_bus.[`trigger_generator_tx_trig_req_flag_q`](#trigger_generator_tx_trig_req_flag_q)                       | 0xc6c    |        4 | Auto-extracted signal tx_trig_req_flag_q from trigger_generator.vhd            |
+| can_bus.[`trigger_generator_tx_trig_req_flag_dq`](#trigger_generator_tx_trig_req_flag_dq)                     | 0xc70    |        4 | Auto-extracted signal tx_trig_req_flag_dq from trigger_generator.vhd           |
+| can_bus.[`trigger_mux_tx_trigger_q`](#trigger_mux_tx_trigger_q)                                               | 0xc74    |        4 | Auto-extracted signal tx_trigger_q from trigger_mux.vhd                        |
+| can_bus.[`trv_delay_meas_trv_meas_progress_d`](#trv_delay_meas_trv_meas_progress_d)                           | 0xc78    |        4 | Auto-extracted signal trv_meas_progress_d from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_meas_progress_q`](#trv_delay_meas_trv_meas_progress_q)                           | 0xc7c    |        4 | Auto-extracted signal trv_meas_progress_q from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_meas_progress_del`](#trv_delay_meas_trv_meas_progress_del)                       | 0xc80    |        4 | Auto-extracted signal trv_meas_progress_del from trv_delay_meas.vhd            |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_q`](#trv_delay_meas_trv_delay_ctr_q)                                   | 0xc84    |        4 | Auto-extracted signal trv_delay_ctr_q from trv_delay_meas.vhd                  |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_d`](#trv_delay_meas_trv_delay_ctr_d)                                   | 0xc88    |        4 | Auto-extracted signal trv_delay_ctr_d from trv_delay_meas.vhd                  |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_add`](#trv_delay_meas_trv_delay_ctr_add)                               | 0xc8c    |        4 | Auto-extracted signal trv_delay_ctr_add from trv_delay_meas.vhd                |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_q_padded`](#trv_delay_meas_trv_delay_ctr_q_padded)                     | 0xc90    |        4 | Auto-extracted signal trv_delay_ctr_q_padded from trv_delay_meas.vhd           |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_d`](#trv_delay_meas_trv_delay_ctr_rst_d)                           | 0xc94    |        4 | Auto-extracted signal trv_delay_ctr_rst_d from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_q`](#trv_delay_meas_trv_delay_ctr_rst_q)                           | 0xc98    |        4 | Auto-extracted signal trv_delay_ctr_rst_q from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_q_scan`](#trv_delay_meas_trv_delay_ctr_rst_q_scan)                 | 0xc9c    |        4 | Auto-extracted signal trv_delay_ctr_rst_q_scan from trv_delay_meas.vhd         |
+| can_bus.[`trv_delay_meas_ssp_shadow_ce`](#trv_delay_meas_ssp_shadow_ce)                                       | 0xca0    |        4 | Auto-extracted signal ssp_shadow_ce from trv_delay_meas.vhd                    |
+| can_bus.[`trv_delay_meas_ssp_delay_raw`](#trv_delay_meas_ssp_delay_raw)                                       | 0xca4    |        4 | Auto-extracted signal ssp_delay_raw from trv_delay_meas.vhd                    |
+| can_bus.[`trv_delay_meas_ssp_delay_saturated`](#trv_delay_meas_ssp_delay_saturated)                           | 0xca8    |        4 | Auto-extracted signal ssp_delay_saturated from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_sum`](#trv_delay_meas_trv_delay_sum)                                       | 0xcac    |        4 | Auto-extracted signal trv_delay_sum from trv_delay_meas.vhd                    |
+| can_bus.[`tx_arbitrator_select_buf_avail`](#tx_arbitrator_select_buf_avail)                                   | 0xcb0    |        4 | Auto-extracted signal select_buf_avail from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_txtb_selected_input`](#tx_arbitrator_txtb_selected_input)                             | 0xcb4    |        4 | Auto-extracted signal txtb_selected_input from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_txtb_timestamp`](#tx_arbitrator_txtb_timestamp)                                       | 0xcb8    |        4 | Auto-extracted signal txtb_timestamp from tx_arbitrator.vhd                    |
+| can_bus.[`tx_arbitrator_timestamp_valid`](#tx_arbitrator_timestamp_valid)                                     | 0xcbc    |        4 | Auto-extracted signal timestamp_valid from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_select_index_changed`](#tx_arbitrator_select_index_changed)                           | 0xcc0    |        4 | Auto-extracted signal select_index_changed from tx_arbitrator.vhd              |
+| can_bus.[`tx_arbitrator_validated_buffer`](#tx_arbitrator_validated_buffer)                                   | 0xcc4    |        4 | Auto-extracted signal validated_buffer from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_ts_low_internal`](#tx_arbitrator_ts_low_internal)                                     | 0xcc8    |        4 | Auto-extracted signal ts_low_internal from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_tran_dlc_dbl_buf`](#tx_arbitrator_tran_dlc_dbl_buf)                                   | 0xccc    |        4 | Auto-extracted signal tran_dlc_dbl_buf from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_tran_is_rtr_dbl_buf`](#tx_arbitrator_tran_is_rtr_dbl_buf)                             | 0xcd0    |        4 | Auto-extracted signal tran_is_rtr_dbl_buf from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_ident_type_dbl_buf`](#tx_arbitrator_tran_ident_type_dbl_buf)                     | 0xcd4    |        4 | Auto-extracted signal tran_ident_type_dbl_buf from tx_arbitrator.vhd           |
+| can_bus.[`tx_arbitrator_tran_frame_type_dbl_buf`](#tx_arbitrator_tran_frame_type_dbl_buf)                     | 0xcd8    |        4 | Auto-extracted signal tran_frame_type_dbl_buf from tx_arbitrator.vhd           |
+| can_bus.[`tx_arbitrator_tran_brs_dbl_buf`](#tx_arbitrator_tran_brs_dbl_buf)                                   | 0xcdc    |        4 | Auto-extracted signal tran_brs_dbl_buf from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_tran_dlc_com`](#tx_arbitrator_tran_dlc_com)                                           | 0xce0    |        4 | Auto-extracted signal tran_dlc_com from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_tran_is_rtr_com`](#tx_arbitrator_tran_is_rtr_com)                                     | 0xce4    |        4 | Auto-extracted signal tran_is_rtr_com from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_tran_ident_type_com`](#tx_arbitrator_tran_ident_type_com)                             | 0xce8    |        4 | Auto-extracted signal tran_ident_type_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_frame_type_com`](#tx_arbitrator_tran_frame_type_com)                             | 0xcec    |        4 | Auto-extracted signal tran_frame_type_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_brs_com`](#tx_arbitrator_tran_brs_com)                                           | 0xcf0    |        4 | Auto-extracted signal tran_brs_com from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_tran_frame_valid_com`](#tx_arbitrator_tran_frame_valid_com)                           | 0xcf4    |        4 | Auto-extracted signal tran_frame_valid_com from tx_arbitrator.vhd              |
+| can_bus.[`tx_arbitrator_tran_identifier_com`](#tx_arbitrator_tran_identifier_com)                             | 0xcf8    |        4 | Auto-extracted signal tran_identifier_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_load_ts_lw_addr`](#tx_arbitrator_load_ts_lw_addr)                                     | 0xcfc    |        4 | Auto-extracted signal load_ts_lw_addr from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_load_ts_uw_addr`](#tx_arbitrator_load_ts_uw_addr)                                     | 0xd00    |        4 | Auto-extracted signal load_ts_uw_addr from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_load_ffmt_w_addr`](#tx_arbitrator_load_ffmt_w_addr)                                   | 0xd04    |        4 | Auto-extracted signal load_ffmt_w_addr from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_load_ident_w_addr`](#tx_arbitrator_load_ident_w_addr)                                 | 0xd08    |        4 | Auto-extracted signal load_ident_w_addr from tx_arbitrator.vhd                 |
+| can_bus.[`tx_arbitrator_store_ts_l_w`](#tx_arbitrator_store_ts_l_w)                                           | 0xd0c    |        4 | Auto-extracted signal store_ts_l_w from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_store_md_w`](#tx_arbitrator_store_md_w)                                               | 0xd10    |        4 | Auto-extracted signal store_md_w from tx_arbitrator.vhd                        |
+| can_bus.[`tx_arbitrator_store_ident_w`](#tx_arbitrator_store_ident_w)                                         | 0xd14    |        4 | Auto-extracted signal store_ident_w from tx_arbitrator.vhd                     |
+| can_bus.[`tx_arbitrator_buffer_md_w`](#tx_arbitrator_buffer_md_w)                                             | 0xd18    |        4 | Auto-extracted signal buffer_md_w from tx_arbitrator.vhd                       |
+| can_bus.[`tx_arbitrator_store_last_txtb_index`](#tx_arbitrator_store_last_txtb_index)                         | 0xd1c    |        4 | Auto-extracted signal store_last_txtb_index from tx_arbitrator.vhd             |
+| can_bus.[`tx_arbitrator_frame_valid_com_set`](#tx_arbitrator_frame_valid_com_set)                             | 0xd20    |        4 | Auto-extracted signal frame_valid_com_set from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_frame_valid_com_clear`](#tx_arbitrator_frame_valid_com_clear)                         | 0xd24    |        4 | Auto-extracted signal frame_valid_com_clear from tx_arbitrator.vhd             |
+| can_bus.[`tx_arbitrator_tx_arb_locked`](#tx_arbitrator_tx_arb_locked)                                         | 0xd28    |        4 | Auto-extracted signal tx_arb_locked from tx_arbitrator.vhd                     |
+| can_bus.[`tx_arbitrator_txtb_meta_clk_en`](#tx_arbitrator_txtb_meta_clk_en)                                   | 0xd2c    |        4 | Auto-extracted signal txtb_meta_clk_en from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_drv_tttm_ena`](#tx_arbitrator_drv_tttm_ena)                                           | 0xd30    |        4 | Auto-extracted signal drv_tttm_ena from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_fsm_tx_arb_fsm_ce`](#tx_arbitrator_fsm_tx_arb_fsm_ce)                                 | 0xd34    |        4 | Auto-extracted signal tx_arb_fsm_ce from tx_arbitrator_fsm.vhd                 |
+| can_bus.[`tx_arbitrator_fsm_fsm_wait_state_d`](#tx_arbitrator_fsm_fsm_wait_state_d)                           | 0xd38    |        4 | Auto-extracted signal fsm_wait_state_d from tx_arbitrator_fsm.vhd              |
+| can_bus.[`tx_arbitrator_fsm_fsm_wait_state_q`](#tx_arbitrator_fsm_fsm_wait_state_q)                           | 0xd3c    |        4 | Auto-extracted signal fsm_wait_state_q from tx_arbitrator_fsm.vhd              |
+| can_bus.[`tx_data_cache_tx_cache_mem`](#tx_data_cache_tx_cache_mem)                                           | 0xd40    |        4 | Auto-extracted signal tx_cache_mem from tx_data_cache.vhd                      |
+| can_bus.[`tx_shift_reg_tx_sr_output`](#tx_shift_reg_tx_sr_output)                                             | 0xd44    |        4 | Auto-extracted signal tx_sr_output from tx_shift_reg.vhd                       |
+| can_bus.[`tx_shift_reg_tx_sr_ce`](#tx_shift_reg_tx_sr_ce)                                                     | 0xd48    |        4 | Auto-extracted signal tx_sr_ce from tx_shift_reg.vhd                           |
+| can_bus.[`tx_shift_reg_tx_sr_pload`](#tx_shift_reg_tx_sr_pload)                                               | 0xd4c    |        4 | Auto-extracted signal tx_sr_pload from tx_shift_reg.vhd                        |
+| can_bus.[`tx_shift_reg_tx_sr_pload_val`](#tx_shift_reg_tx_sr_pload_val)                                       | 0xd50    |        4 | Auto-extracted signal tx_sr_pload_val from tx_shift_reg.vhd                    |
+| can_bus.[`tx_shift_reg_tx_base_id`](#tx_shift_reg_tx_base_id)                                                 | 0xd54    |        4 | Auto-extracted signal tx_base_id from tx_shift_reg.vhd                         |
+| can_bus.[`tx_shift_reg_tx_ext_id`](#tx_shift_reg_tx_ext_id)                                                   | 0xd58    |        4 | Auto-extracted signal tx_ext_id from tx_shift_reg.vhd                          |
+| can_bus.[`tx_shift_reg_tx_crc`](#tx_shift_reg_tx_crc)                                                         | 0xd5c    |        4 | Auto-extracted signal tx_crc from tx_shift_reg.vhd                             |
+| can_bus.[`tx_shift_reg_bst_ctr_grey`](#tx_shift_reg_bst_ctr_grey)                                             | 0xd60    |        4 | Auto-extracted signal bst_ctr_grey from tx_shift_reg.vhd                       |
+| can_bus.[`tx_shift_reg_bst_parity`](#tx_shift_reg_bst_parity)                                                 | 0xd64    |        4 | Auto-extracted signal bst_parity from tx_shift_reg.vhd                         |
+| can_bus.[`tx_shift_reg_stuff_count`](#tx_shift_reg_stuff_count)                                               | 0xd68    |        4 | Auto-extracted signal stuff_count from tx_shift_reg.vhd                        |
+| can_bus.[`txt_buffer_txtb_user_accessible`](#txt_buffer_txtb_user_accessible)                                 | 0xd6c    |        4 | Auto-extracted signal txtb_user_accessible from txt_buffer.vhd                 |
+| can_bus.[`txt_buffer_hw_cbs`](#txt_buffer_hw_cbs)                                                             | 0xd70    |        4 | Auto-extracted signal hw_cbs from txt_buffer.vhd                               |
+| can_bus.[`txt_buffer_sw_cbs`](#txt_buffer_sw_cbs)                                                             | 0xd74    |        4 | Auto-extracted signal sw_cbs from txt_buffer.vhd                               |
+| can_bus.[`txt_buffer_txtb_unmask_data_ram`](#txt_buffer_txtb_unmask_data_ram)                                 | 0xd78    |        4 | Auto-extracted signal txtb_unmask_data_ram from txt_buffer.vhd                 |
+| can_bus.[`txt_buffer_txtb_port_b_data_i`](#txt_buffer_txtb_port_b_data_i)                                     | 0xd7c    |        4 | Auto-extracted signal txtb_port_b_data_i from txt_buffer.vhd                   |
+| can_bus.[`txt_buffer_ram_write`](#txt_buffer_ram_write)                                                       | 0xd80    |        4 | Auto-extracted signal ram_write from txt_buffer.vhd                            |
+| can_bus.[`txt_buffer_ram_read_address`](#txt_buffer_ram_read_address)                                         | 0xd84    |        4 | Auto-extracted signal ram_read_address from txt_buffer.vhd                     |
+| can_bus.[`txt_buffer_txtb_ram_clk_en`](#txt_buffer_txtb_ram_clk_en)                                           | 0xd88    |        4 | Auto-extracted signal txtb_ram_clk_en from txt_buffer.vhd                      |
+| can_bus.[`txt_buffer_clk_ram`](#txt_buffer_clk_ram)                                                           | 0xd8c    |        4 | Auto-extracted signal clk_ram from txt_buffer.vhd                              |
+| can_bus.[`txt_buffer_fsm_abort_applied`](#txt_buffer_fsm_abort_applied)                                       | 0xd90    |        4 | Auto-extracted signal abort_applied from txt_buffer_fsm.vhd                    |
+| can_bus.[`txt_buffer_fsm_txt_fsm_ce`](#txt_buffer_fsm_txt_fsm_ce)                                             | 0xd94    |        4 | Auto-extracted signal txt_fsm_ce from txt_buffer_fsm.vhd                       |
+| can_bus.[`txt_buffer_fsm_go_to_failed`](#txt_buffer_fsm_go_to_failed)                                         | 0xd98    |        4 | Auto-extracted signal go_to_failed from txt_buffer_fsm.vhd                     |
+| can_bus.[`txt_buffer_fsm_transient_state`](#txt_buffer_fsm_transient_state)                                   | 0xd9c    |        4 | Auto-extracted signal transient_state from txt_buffer_fsm.vhd                  |
+| can_bus.[`txt_buffer_ram_port_a_address_i`](#txt_buffer_ram_port_a_address_i)                                 | 0xda0    |        4 | Auto-extracted signal port_a_address_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_a_write_i`](#txt_buffer_ram_port_a_write_i)                                     | 0xda4    |        4 | Auto-extracted signal port_a_write_i from txt_buffer_ram.vhd                   |
+| can_bus.[`txt_buffer_ram_port_a_data_in_i`](#txt_buffer_ram_port_a_data_in_i)                                 | 0xda8    |        4 | Auto-extracted signal port_a_data_in_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_b_address_i`](#txt_buffer_ram_port_b_address_i)                                 | 0xdac    |        4 | Auto-extracted signal port_b_address_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_b_data_out_i`](#txt_buffer_ram_port_b_data_out_i)                               | 0xdb0    |        4 | Auto-extracted signal port_b_data_out_i from txt_buffer_ram.vhd                |
+| can_bus.[`txt_buffer_ram_tst_ena`](#txt_buffer_ram_tst_ena)                                                   | 0xdb4    |        4 | Auto-extracted signal tst_ena from txt_buffer_ram.vhd                          |
+| can_bus.[`txt_buffer_ram_tst_addr`](#txt_buffer_ram_tst_addr)                                                 | 0xdb8    |        4 | Auto-extracted signal tst_addr from txt_buffer_ram.vhd                         |
+| can_bus.[`access_signaler_be_active`](#access_signaler_be_active)                                             | 0xdbc    |        4 | Auto-extracted signal be_active from access_signaler.vhd                       |
+| can_bus.[`access_signaler_access_in`](#access_signaler_access_in)                                             | 0xdc0    |        4 | Auto-extracted signal access_in from access_signaler.vhd                       |
+| can_bus.[`access_signaler_access_active`](#access_signaler_access_active)                                     | 0xdc4    |        4 | Auto-extracted signal access_active from access_signaler.vhd                   |
+| can_bus.[`access_signaler_access_active_reg`](#access_signaler_access_active_reg)                             | 0xdc8    |        4 | Auto-extracted signal access_active_reg from access_signaler.vhd               |
+| can_bus.[`address_decoder_addr_dec_i`](#address_decoder_addr_dec_i)                                           | 0xdcc    |        4 | Auto-extracted signal addr_dec_i from address_decoder.vhd                      |
+| can_bus.[`address_decoder_addr_dec_enabled_i`](#address_decoder_addr_dec_enabled_i)                           | 0xdd0    |        4 | Auto-extracted signal addr_dec_enabled_i from address_decoder.vhd              |
+
+## ahb_ifc_hsel_valid
+Auto-extracted signal hsel_valid from ahb_ifc.vhd
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_write_acc_d
+Auto-extracted signal write_acc_d from ahb_ifc.vhd
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_write_acc_q
+Auto-extracted signal write_acc_q from ahb_ifc.vhd
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_haddr_q
+Auto-extracted signal haddr_q from ahb_ifc.vhd
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_h_ready_raw
+Auto-extracted signal h_ready_raw from ahb_ifc.vhd
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_sbe_d
+Auto-extracted signal sbe_d from ahb_ifc.vhd
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_sbe_q
+Auto-extracted signal sbe_q from ahb_ifc.vhd
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_swr_i
+Auto-extracted signal swr_i from ahb_ifc.vhd
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_srd_i
+Auto-extracted signal srd_i from ahb_ifc.vhd
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_discard_stuff_bit
+Auto-extracted signal discard_stuff_bit from bit_destuffing.vhd
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_non_fix_to_fix_chng
+Auto-extracted signal non_fix_to_fix_chng from bit_destuffing.vhd
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_lvl_reached
+Auto-extracted signal stuff_lvl_reached from bit_destuffing.vhd
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_rule_violate
+Auto-extracted signal stuff_rule_violate from bit_destuffing.vhd
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_enable_prev
+Auto-extracted signal enable_prev from bit_destuffing.vhd
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_fixed_prev_q
+Auto-extracted signal fixed_prev_q from bit_destuffing.vhd
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_fixed_prev_d
+Auto-extracted signal fixed_prev_d from bit_destuffing.vhd
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_same_bits_erase
+Auto-extracted signal same_bits_erase from bit_destuffing.vhd
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_destuffed_q
+Auto-extracted signal destuffed_q from bit_destuffing.vhd
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_destuffed_d
+Auto-extracted signal destuffed_d from bit_destuffing.vhd
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_err_q
+Auto-extracted signal stuff_err_q from bit_destuffing.vhd
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_err_d
+Auto-extracted signal stuff_err_d from bit_destuffing.vhd
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_prev_val_q
+Auto-extracted signal prev_val_q from bit_destuffing.vhd
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_prev_val_d
+Auto-extracted signal prev_val_d from bit_destuffing.vhd
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_d
+Auto-extracted signal bit_err_d from bit_err_detector.vhd
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_q
+Auto-extracted signal bit_err_q from bit_err_detector.vhd
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_capt_d
+Auto-extracted signal bit_err_ssp_capt_d from bit_err_detector.vhd
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_capt_q
+Auto-extracted signal bit_err_ssp_capt_q from bit_err_detector.vhd
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_valid
+Auto-extracted signal bit_err_ssp_valid from bit_err_detector.vhd
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_condition
+Auto-extracted signal bit_err_ssp_condition from bit_err_detector.vhd
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_norm_valid
+Auto-extracted signal bit_err_norm_valid from bit_err_detector.vhd
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_filter_masked_input
+Auto-extracted signal masked_input from bit_filter.vhd
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_filter_masked_value
+Auto-extracted signal masked_value from bit_filter.vhd
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_sel_tseg1
+Auto-extracted signal sel_tseg1 from bit_segment_meter.vhd
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exp_seg_length_ce
+Auto-extracted signal exp_seg_length_ce from bit_segment_meter.vhd
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_mt_sjw
+Auto-extracted signal phase_err_mt_sjw from bit_segment_meter.vhd
+- Offset: `0x88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_eq_sjw
+Auto-extracted signal phase_err_eq_sjw from bit_segment_meter.vhd
+- Offset: `0x8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_ph2_immediate
+Auto-extracted signal exit_ph2_immediate from bit_segment_meter.vhd
+- Offset: `0x90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular
+Auto-extracted signal exit_segm_regular from bit_segment_meter.vhd
+- Offset: `0x94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular_tseg1
+Auto-extracted signal exit_segm_regular_tseg1 from bit_segment_meter.vhd
+- Offset: `0x98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular_tseg2
+Auto-extracted signal exit_segm_regular_tseg2 from bit_segment_meter.vhd
+- Offset: `0x9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_sjw_mt_zero
+Auto-extracted signal sjw_mt_zero from bit_segment_meter.vhd
+- Offset: `0xa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_use_basic_segm_length
+Auto-extracted signal use_basic_segm_length from bit_segment_meter.vhd
+- Offset: `0xa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_sjw_by_one
+Auto-extracted signal phase_err_sjw_by_one from bit_segment_meter.vhd
+- Offset: `0xa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_shorten_tseg1_after_tseg2
+Auto-extracted signal shorten_tseg1_after_tseg2 from bit_segment_meter.vhd
+- Offset: `0xac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_i
+Auto-extracted signal data_out_i from bit_stuffing.vhd
+- Offset: `0xb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_halt_q
+Auto-extracted signal data_halt_q from bit_stuffing.vhd
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_halt_d
+Auto-extracted signal data_halt_d from bit_stuffing.vhd
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_fixed_reg_q
+Auto-extracted signal fixed_reg_q from bit_stuffing.vhd
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_fixed_reg_d
+Auto-extracted signal fixed_reg_d from bit_stuffing.vhd
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_enable_prev
+Auto-extracted signal enable_prev from bit_stuffing.vhd
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_non_fix_to_fix_chng
+Auto-extracted signal non_fix_to_fix_chng from bit_stuffing.vhd
+- Offset: `0xc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_stuff_lvl_reached
+Auto-extracted signal stuff_lvl_reached from bit_stuffing.vhd
+- Offset: `0xcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_same_bits_rst_trig
+Auto-extracted signal same_bits_rst_trig from bit_stuffing.vhd
+- Offset: `0xd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_same_bits_rst
+Auto-extracted signal same_bits_rst from bit_stuffing.vhd
+- Offset: `0xd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_insert_stuff_bit
+Auto-extracted signal insert_stuff_bit from bit_stuffing.vhd
+- Offset: `0xd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_d_ena
+Auto-extracted signal data_out_d_ena from bit_stuffing.vhd
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_d
+Auto-extracted signal data_out_d from bit_stuffing.vhd
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_ce
+Auto-extracted signal data_out_ce from bit_stuffing.vhd
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_tq_nbt
+Auto-extracted signal drv_tq_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_prs_nbt
+Auto-extracted signal drv_prs_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph1_nbt
+Auto-extracted signal drv_ph1_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph2_nbt
+Auto-extracted signal drv_ph2_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_sjw_nbt
+Auto-extracted signal drv_sjw_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_tq_dbt
+Auto-extracted signal drv_tq_dbt from bit_time_cfg_capture.vhd
+- Offset: `0xfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_prs_dbt
+Auto-extracted signal drv_prs_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x100`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph1_dbt
+Auto-extracted signal drv_ph1_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x104`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph2_dbt
+Auto-extracted signal drv_ph2_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x108`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_sjw_dbt
+Auto-extracted signal drv_sjw_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x10c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_tseg1_nbt_d
+Auto-extracted signal tseg1_nbt_d from bit_time_cfg_capture.vhd
+- Offset: `0x110`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_tseg1_dbt_d
+Auto-extracted signal tseg1_dbt_d from bit_time_cfg_capture.vhd
+- Offset: `0x114`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena
+Auto-extracted signal drv_ena from bit_time_cfg_capture.vhd
+- Offset: `0x118`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena_reg
+Auto-extracted signal drv_ena_reg from bit_time_cfg_capture.vhd
+- Offset: `0x11c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena_reg_2
+Auto-extracted signal drv_ena_reg_2 from bit_time_cfg_capture.vhd
+- Offset: `0x120`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_capture
+Auto-extracted signal capture from bit_time_cfg_capture.vhd
+- Offset: `0x124`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_d
+Auto-extracted signal tq_counter_d from bit_time_counters.vhd
+- Offset: `0x128`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_q
+Auto-extracted signal tq_counter_q from bit_time_counters.vhd
+- Offset: `0x12c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_ce
+Auto-extracted signal tq_counter_ce from bit_time_counters.vhd
+- Offset: `0x130`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_allow
+Auto-extracted signal tq_counter_allow from bit_time_counters.vhd
+- Offset: `0x134`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_edge_i
+Auto-extracted signal tq_edge_i from bit_time_counters.vhd
+- Offset: `0x138`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_d
+Auto-extracted signal segm_counter_d from bit_time_counters.vhd
+- Offset: `0x13c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_q
+Auto-extracted signal segm_counter_q from bit_time_counters.vhd
+- Offset: `0x140`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_ce
+Auto-extracted signal segm_counter_ce from bit_time_counters.vhd
+- Offset: `0x144`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_fsm_bt_fsm_ce
+Auto-extracted signal bt_fsm_ce from bit_time_fsm.vhd
+- Offset: `0x148`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ena
+Auto-extracted signal drv_ena from bus_sampling.vhd
+- Offset: `0x14c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ssp_offset
+Auto-extracted signal drv_ssp_offset from bus_sampling.vhd
+- Offset: `0x150`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ssp_delay_select
+Auto-extracted signal drv_ssp_delay_select from bus_sampling.vhd
+- Offset: `0x154`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_data_rx_synced
+Auto-extracted signal data_rx_synced from bus_sampling.vhd
+- Offset: `0x158`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_prev_Sample
+Auto-extracted signal prev_Sample from bus_sampling.vhd
+- Offset: `0x15c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_sample_sec_i
+Auto-extracted signal sample_sec_i from bus_sampling.vhd
+- Offset: `0x160`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_data_tx_delayed
+Auto-extracted signal data_tx_delayed from bus_sampling.vhd
+- Offset: `0x164`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_edge_rx_valid
+Auto-extracted signal edge_rx_valid from bus_sampling.vhd
+- Offset: `0x168`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_edge_tx_valid
+Auto-extracted signal edge_tx_valid from bus_sampling.vhd
+- Offset: `0x16c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_ssp_delay
+Auto-extracted signal ssp_delay from bus_sampling.vhd
+- Offset: `0x170`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_tx_trigger_q
+Auto-extracted signal tx_trigger_q from bus_sampling.vhd
+- Offset: `0x174`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_tx_trigger_ssp
+Auto-extracted signal tx_trigger_ssp from bus_sampling.vhd
+- Offset: `0x178`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_d
+Auto-extracted signal shift_regs_res_d from bus_sampling.vhd
+- Offset: `0x17c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_q
+Auto-extracted signal shift_regs_res_q from bus_sampling.vhd
+- Offset: `0x180`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_q_scan
+Auto-extracted signal shift_regs_res_q_scan from bus_sampling.vhd
+- Offset: `0x184`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_ssp_enable
+Auto-extracted signal ssp_enable from bus_sampling.vhd
+- Offset: `0x188`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_i
+Auto-extracted signal tx_ctr_i from bus_traffic_counters.vhd
+- Offset: `0x18c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_i
+Auto-extracted signal rx_ctr_i from bus_traffic_counters.vhd
+- Offset: `0x190`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_d
+Auto-extracted signal tx_ctr_rst_n_d from bus_traffic_counters.vhd
+- Offset: `0x194`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_q
+Auto-extracted signal tx_ctr_rst_n_q from bus_traffic_counters.vhd
+- Offset: `0x198`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_q_scan
+Auto-extracted signal tx_ctr_rst_n_q_scan from bus_traffic_counters.vhd
+- Offset: `0x19c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_d
+Auto-extracted signal rx_ctr_rst_n_d from bus_traffic_counters.vhd
+- Offset: `0x1a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_q
+Auto-extracted signal rx_ctr_rst_n_q from bus_traffic_counters.vhd
+- Offset: `0x1a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_q_scan
+Auto-extracted signal rx_ctr_rst_n_q_scan from bus_traffic_counters.vhd
+- Offset: `0x1a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_paddr
+Auto-extracted signal s_apb_paddr from can_apb_tb.vhd
+- Offset: `0x1ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_penable
+Auto-extracted signal s_apb_penable from can_apb_tb.vhd
+- Offset: `0x1b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pprot
+Auto-extracted signal s_apb_pprot from can_apb_tb.vhd
+- Offset: `0x1b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_prdata
+Auto-extracted signal s_apb_prdata from can_apb_tb.vhd
+- Offset: `0x1b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pready
+Auto-extracted signal s_apb_pready from can_apb_tb.vhd
+- Offset: `0x1bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_psel
+Auto-extracted signal s_apb_psel from can_apb_tb.vhd
+- Offset: `0x1c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pslverr
+Auto-extracted signal s_apb_pslverr from can_apb_tb.vhd
+- Offset: `0x1c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pstrb
+Auto-extracted signal s_apb_pstrb from can_apb_tb.vhd
+- Offset: `0x1c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pwdata
+Auto-extracted signal s_apb_pwdata from can_apb_tb.vhd
+- Offset: `0x1cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pwrite
+Auto-extracted signal s_apb_pwrite from can_apb_tb.vhd
+- Offset: `0x1d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_clr_rx_ctr
+Auto-extracted signal drv_clr_rx_ctr from can_core.vhd
+- Offset: `0x1d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_clr_tx_ctr
+Auto-extracted signal drv_clr_tx_ctr from can_core.vhd
+- Offset: `0x1d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_bus_mon_ena
+Auto-extracted signal drv_bus_mon_ena from can_core.vhd
+- Offset: `0x1dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_ena
+Auto-extracted signal drv_ena from can_core.vhd
+- Offset: `0x1e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_ident_i
+Auto-extracted signal rec_ident_i from can_core.vhd
+- Offset: `0x1e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_dlc_i
+Auto-extracted signal rec_dlc_i from can_core.vhd
+- Offset: `0x1e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_ident_type_i
+Auto-extracted signal rec_ident_type_i from can_core.vhd
+- Offset: `0x1ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from can_core.vhd
+- Offset: `0x1f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from can_core.vhd
+- Offset: `0x1f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_brs_i
+Auto-extracted signal rec_brs_i from can_core.vhd
+- Offset: `0x1f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_esi_i
+Auto-extracted signal rec_esi_i from can_core.vhd
+- Offset: `0x1fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_alc
+Auto-extracted signal alc from can_core.vhd
+- Offset: `0x200`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_erc_capture
+Auto-extracted signal erc_capture from can_core.vhd
+- Offset: `0x204`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_transmitter
+Auto-extracted signal is_transmitter from can_core.vhd
+- Offset: `0x208`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_receiver
+Auto-extracted signal is_receiver from can_core.vhd
+- Offset: `0x20c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_idle
+Auto-extracted signal is_idle from can_core.vhd
+- Offset: `0x210`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from can_core.vhd
+- Offset: `0x214`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_transmitter
+Auto-extracted signal set_transmitter from can_core.vhd
+- Offset: `0x218`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_receiver
+Auto-extracted signal set_receiver from can_core.vhd
+- Offset: `0x21c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_idle
+Auto-extracted signal set_idle from can_core.vhd
+- Offset: `0x220`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_active
+Auto-extracted signal is_err_active from can_core.vhd
+- Offset: `0x224`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_passive
+Auto-extracted signal is_err_passive from can_core.vhd
+- Offset: `0x228`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_bus_off_i
+Auto-extracted signal is_bus_off_i from can_core.vhd
+- Offset: `0x22c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_detected_i
+Auto-extracted signal err_detected_i from can_core.vhd
+- Offset: `0x230`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_primary_err
+Auto-extracted signal primary_err from can_core.vhd
+- Offset: `0x234`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_act_err_ovr_flag
+Auto-extracted signal act_err_ovr_flag from can_core.vhd
+- Offset: `0x238`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_delim_late
+Auto-extracted signal err_delim_late from can_core.vhd
+- Offset: `0x23c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_err_active
+Auto-extracted signal set_err_active from can_core.vhd
+- Offset: `0x240`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_ctrs_unchanged
+Auto-extracted signal err_ctrs_unchanged from can_core.vhd
+- Offset: `0x244`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_enable
+Auto-extracted signal stuff_enable from can_core.vhd
+- Offset: `0x248`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_destuff_enable
+Auto-extracted signal destuff_enable from can_core.vhd
+- Offset: `0x24c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_fixed_stuff
+Auto-extracted signal fixed_stuff from can_core.vhd
+- Offset: `0x250`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_frame_no_sof
+Auto-extracted signal tx_frame_no_sof from can_core.vhd
+- Offset: `0x254`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_length
+Auto-extracted signal stuff_length from can_core.vhd
+- Offset: `0x258`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_dst_ctr
+Auto-extracted signal dst_ctr from can_core.vhd
+- Offset: `0x25c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_ctr
+Auto-extracted signal bst_ctr from can_core.vhd
+- Offset: `0x260`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_err
+Auto-extracted signal stuff_err from can_core.vhd
+- Offset: `0x264`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_enable
+Auto-extracted signal crc_enable from can_core.vhd
+- Offset: `0x268`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_spec_enable
+Auto-extracted signal crc_spec_enable from can_core.vhd
+- Offset: `0x26c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_calc_from_rx
+Auto-extracted signal crc_calc_from_rx from can_core.vhd
+- Offset: `0x270`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_15
+Auto-extracted signal crc_15 from can_core.vhd
+- Offset: `0x274`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_17
+Auto-extracted signal crc_17 from can_core.vhd
+- Offset: `0x278`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_21
+Auto-extracted signal crc_21 from can_core.vhd
+- Offset: `0x27c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sp_control_i
+Auto-extracted signal sp_control_i from can_core.vhd
+- Offset: `0x280`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sp_control_q
+Auto-extracted signal sp_control_q from can_core.vhd
+- Offset: `0x284`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sync_control_i
+Auto-extracted signal sync_control_i from can_core.vhd
+- Offset: `0x288`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_ssp_reset_i
+Auto-extracted signal ssp_reset_i from can_core.vhd
+- Offset: `0x28c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tran_delay_meas_i
+Auto-extracted signal tran_delay_meas_i from can_core.vhd
+- Offset: `0x290`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tran_valid_i
+Auto-extracted signal tran_valid_i from can_core.vhd
+- Offset: `0x294`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_valid_i
+Auto-extracted signal rec_valid_i from can_core.vhd
+- Offset: `0x298`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_br_shifted_i
+Auto-extracted signal br_shifted_i from can_core.vhd
+- Offset: `0x29c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_fcs_changed_i
+Auto-extracted signal fcs_changed_i from can_core.vhd
+- Offset: `0x2a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_warning_limit_i
+Auto-extracted signal err_warning_limit_i from can_core.vhd
+- Offset: `0x2a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_err_ctr
+Auto-extracted signal tx_err_ctr from can_core.vhd
+- Offset: `0x2a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rx_err_ctr
+Auto-extracted signal rx_err_ctr from can_core.vhd
+- Offset: `0x2ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_norm_err_ctr
+Auto-extracted signal norm_err_ctr from can_core.vhd
+- Offset: `0x2b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_data_err_ctr
+Auto-extracted signal data_err_ctr from can_core.vhd
+- Offset: `0x2b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_tx_trigger
+Auto-extracted signal pc_tx_trigger from can_core.vhd
+- Offset: `0x2b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_rx_trigger
+Auto-extracted signal pc_rx_trigger from can_core.vhd
+- Offset: `0x2bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_tx_data_nbs
+Auto-extracted signal pc_tx_data_nbs from can_core.vhd
+- Offset: `0x2c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_rx_data_nbs
+Auto-extracted signal pc_rx_data_nbs from can_core.vhd
+- Offset: `0x2c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_tx_wbs
+Auto-extracted signal crc_data_tx_wbs from can_core.vhd
+- Offset: `0x2c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_tx_nbs
+Auto-extracted signal crc_data_tx_nbs from can_core.vhd
+- Offset: `0x2cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_rx_wbs
+Auto-extracted signal crc_data_rx_wbs from can_core.vhd
+- Offset: `0x2d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_rx_nbs
+Auto-extracted signal crc_data_rx_nbs from can_core.vhd
+- Offset: `0x2d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_tx_wbs
+Auto-extracted signal crc_trig_tx_wbs from can_core.vhd
+- Offset: `0x2d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_tx_nbs
+Auto-extracted signal crc_trig_tx_nbs from can_core.vhd
+- Offset: `0x2dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_rx_wbs
+Auto-extracted signal crc_trig_rx_wbs from can_core.vhd
+- Offset: `0x2e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_rx_nbs
+Auto-extracted signal crc_trig_rx_nbs from can_core.vhd
+- Offset: `0x2e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_data_in
+Auto-extracted signal bst_data_in from can_core.vhd
+- Offset: `0x2e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_data_out
+Auto-extracted signal bst_data_out from can_core.vhd
+- Offset: `0x2ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_trigger
+Auto-extracted signal bst_trigger from can_core.vhd
+- Offset: `0x2f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_data_halt
+Auto-extracted signal data_halt from can_core.vhd
+- Offset: `0x2f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_data_in
+Auto-extracted signal bds_data_in from can_core.vhd
+- Offset: `0x2f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_data_out
+Auto-extracted signal bds_data_out from can_core.vhd
+- Offset: `0x2fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_trigger
+Auto-extracted signal bds_trigger from can_core.vhd
+- Offset: `0x300`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_destuffed
+Auto-extracted signal destuffed from can_core.vhd
+- Offset: `0x304`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_ctr
+Auto-extracted signal tx_ctr from can_core.vhd
+- Offset: `0x308`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rx_ctr
+Auto-extracted signal rx_ctr from can_core.vhd
+- Offset: `0x30c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_data_wbs_i
+Auto-extracted signal tx_data_wbs_i from can_core.vhd
+- Offset: `0x310`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_lpb_dominant
+Auto-extracted signal lpb_dominant from can_core.vhd
+- Offset: `0x314`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_form_err
+Auto-extracted signal form_err from can_core.vhd
+- Offset: `0x318`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_ack_err
+Auto-extracted signal ack_err from can_core.vhd
+- Offset: `0x31c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_err
+Auto-extracted signal crc_err from can_core.vhd
+- Offset: `0x320`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_arbitration
+Auto-extracted signal is_arbitration from can_core.vhd
+- Offset: `0x324`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_control
+Auto-extracted signal is_control from can_core.vhd
+- Offset: `0x328`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_data
+Auto-extracted signal is_data from can_core.vhd
+- Offset: `0x32c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_stuff_count
+Auto-extracted signal is_stuff_count from can_core.vhd
+- Offset: `0x330`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_crc
+Auto-extracted signal is_crc from can_core.vhd
+- Offset: `0x334`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_crc_delim
+Auto-extracted signal is_crc_delim from can_core.vhd
+- Offset: `0x338`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_ack_field
+Auto-extracted signal is_ack_field from can_core.vhd
+- Offset: `0x33c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_ack_delim
+Auto-extracted signal is_ack_delim from can_core.vhd
+- Offset: `0x340`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_eof
+Auto-extracted signal is_eof from can_core.vhd
+- Offset: `0x344`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_frm
+Auto-extracted signal is_err_frm from can_core.vhd
+- Offset: `0x348`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_intermission
+Auto-extracted signal is_intermission from can_core.vhd
+- Offset: `0x34c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_suspend
+Auto-extracted signal is_suspend from can_core.vhd
+- Offset: `0x350`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_overload_i
+Auto-extracted signal is_overload_i from can_core.vhd
+- Offset: `0x354`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_sof
+Auto-extracted signal is_sof from can_core.vhd
+- Offset: `0x358`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sof_pulse_i
+Auto-extracted signal sof_pulse_i from can_core.vhd
+- Offset: `0x35c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_load_init_vect
+Auto-extracted signal load_init_vect from can_core.vhd
+- Offset: `0x360`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_retr_ctr_i
+Auto-extracted signal retr_ctr_i from can_core.vhd
+- Offset: `0x364`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_decrement_rec
+Auto-extracted signal decrement_rec from can_core.vhd
+- Offset: `0x368`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bit_err_after_ack_err
+Auto-extracted signal bit_err_after_ack_err from can_core.vhd
+- Offset: `0x36c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_pexs
+Auto-extracted signal is_pexs from can_core.vhd
+- Offset: `0x370`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_drv_fd_type
+Auto-extracted signal drv_fd_type from can_crc.vhd
+- Offset: `0x374`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_15
+Auto-extracted signal init_vect_15 from can_crc.vhd
+- Offset: `0x378`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_17
+Auto-extracted signal init_vect_17 from can_crc.vhd
+- Offset: `0x37c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_21
+Auto-extracted signal init_vect_21 from can_crc.vhd
+- Offset: `0x380`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_17_21_data_in
+Auto-extracted signal crc_17_21_data_in from can_crc.vhd
+- Offset: `0x384`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_17_21_trigger
+Auto-extracted signal crc_17_21_trigger from can_crc.vhd
+- Offset: `0x388`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_15_data_in
+Auto-extracted signal crc_15_data_in from can_crc.vhd
+- Offset: `0x38c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_15_trigger
+Auto-extracted signal crc_15_trigger from can_crc.vhd
+- Offset: `0x390`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_ena_15
+Auto-extracted signal crc_ena_15 from can_crc.vhd
+- Offset: `0x394`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_ena_17_21
+Auto-extracted signal crc_ena_17_21 from can_crc.vhd
+- Offset: `0x398`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_data_in
+Auto-extracted signal ctu_can_data_in from can_top_ahb.vhd
+- Offset: `0x39c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_data_out
+Auto-extracted signal ctu_can_data_out from can_top_ahb.vhd
+- Offset: `0x3a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_adress
+Auto-extracted signal ctu_can_adress from can_top_ahb.vhd
+- Offset: `0x3a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_scs
+Auto-extracted signal ctu_can_scs from can_top_ahb.vhd
+- Offset: `0x3a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_srd
+Auto-extracted signal ctu_can_srd from can_top_ahb.vhd
+- Offset: `0x3ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_swr
+Auto-extracted signal ctu_can_swr from can_top_ahb.vhd
+- Offset: `0x3b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_sbe
+Auto-extracted signal ctu_can_sbe from can_top_ahb.vhd
+- Offset: `0x3b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_res_n_out_i
+Auto-extracted signal res_n_out_i from can_top_ahb.vhd
+- Offset: `0x3b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_data_in
+Auto-extracted signal reg_data_in from can_top_apb.vhd
+- Offset: `0x3bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_data_out
+Auto-extracted signal reg_data_out from can_top_apb.vhd
+- Offset: `0x3c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_addr
+Auto-extracted signal reg_addr from can_top_apb.vhd
+- Offset: `0x3c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_be
+Auto-extracted signal reg_be from can_top_apb.vhd
+- Offset: `0x3c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_rden
+Auto-extracted signal reg_rden from can_top_apb.vhd
+- Offset: `0x3cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_wren
+Auto-extracted signal reg_wren from can_top_apb.vhd
+- Offset: `0x3d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_drv_bus
+Auto-extracted signal drv_bus from can_top_level.vhd
+- Offset: `0x3d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_stat_bus
+Auto-extracted signal stat_bus from can_top_level.vhd
+- Offset: `0x3d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_n_sync
+Auto-extracted signal res_n_sync from can_top_level.vhd
+- Offset: `0x3dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_core_n
+Auto-extracted signal res_core_n from can_top_level.vhd
+- Offset: `0x3e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_soft_n
+Auto-extracted signal res_soft_n from can_top_level.vhd
+- Offset: `0x3e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sp_control
+Auto-extracted signal sp_control from can_top_level.vhd
+- Offset: `0x3e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_buf_size
+Auto-extracted signal rx_buf_size from can_top_level.vhd
+- Offset: `0x3ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_full
+Auto-extracted signal rx_full from can_top_level.vhd
+- Offset: `0x3f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_empty
+Auto-extracted signal rx_empty from can_top_level.vhd
+- Offset: `0x3f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_frame_count
+Auto-extracted signal rx_frame_count from can_top_level.vhd
+- Offset: `0x3f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_mem_free
+Auto-extracted signal rx_mem_free from can_top_level.vhd
+- Offset: `0x3fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_read_pointer
+Auto-extracted signal rx_read_pointer from can_top_level.vhd
+- Offset: `0x400`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_write_pointer
+Auto-extracted signal rx_write_pointer from can_top_level.vhd
+- Offset: `0x404`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_data_overrun
+Auto-extracted signal rx_data_overrun from can_top_level.vhd
+- Offset: `0x408`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_read_buff
+Auto-extracted signal rx_read_buff from can_top_level.vhd
+- Offset: `0x40c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_mof
+Auto-extracted signal rx_mof from can_top_level.vhd
+- Offset: `0x410`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_data
+Auto-extracted signal txtb_port_a_data from can_top_level.vhd
+- Offset: `0x414`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_address
+Auto-extracted signal txtb_port_a_address from can_top_level.vhd
+- Offset: `0x418`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_cs
+Auto-extracted signal txtb_port_a_cs from can_top_level.vhd
+- Offset: `0x41c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_be
+Auto-extracted signal txtb_port_a_be from can_top_level.vhd
+- Offset: `0x420`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_sw_cmd_index
+Auto-extracted signal txtb_sw_cmd_index from can_top_level.vhd
+- Offset: `0x424`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txt_buf_failed_bof
+Auto-extracted signal txt_buf_failed_bof from can_top_level.vhd
+- Offset: `0x428`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_vector
+Auto-extracted signal int_vector from can_top_level.vhd
+- Offset: `0x42c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_ena
+Auto-extracted signal int_ena from can_top_level.vhd
+- Offset: `0x430`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_mask
+Auto-extracted signal int_mask from can_top_level.vhd
+- Offset: `0x434`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_ident
+Auto-extracted signal rec_ident from can_top_level.vhd
+- Offset: `0x438`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_dlc
+Auto-extracted signal rec_dlc from can_top_level.vhd
+- Offset: `0x43c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_ident_type
+Auto-extracted signal rec_ident_type from can_top_level.vhd
+- Offset: `0x440`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_frame_type
+Auto-extracted signal rec_frame_type from can_top_level.vhd
+- Offset: `0x444`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_is_rtr
+Auto-extracted signal rec_is_rtr from can_top_level.vhd
+- Offset: `0x448`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_brs
+Auto-extracted signal rec_brs from can_top_level.vhd
+- Offset: `0x44c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_esi
+Auto-extracted signal rec_esi from can_top_level.vhd
+- Offset: `0x450`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data_word
+Auto-extracted signal store_data_word from can_top_level.vhd
+- Offset: `0x454`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sof_pulse
+Auto-extracted signal sof_pulse from can_top_level.vhd
+- Offset: `0x458`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_metadata
+Auto-extracted signal store_metadata from can_top_level.vhd
+- Offset: `0x45c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data
+Auto-extracted signal store_data from can_top_level.vhd
+- Offset: `0x460`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_valid
+Auto-extracted signal rec_valid from can_top_level.vhd
+- Offset: `0x464`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_abort
+Auto-extracted signal rec_abort from can_top_level.vhd
+- Offset: `0x468`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_metadata_f
+Auto-extracted signal store_metadata_f from can_top_level.vhd
+- Offset: `0x46c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data_f
+Auto-extracted signal store_data_f from can_top_level.vhd
+- Offset: `0x470`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_valid_f
+Auto-extracted signal rec_valid_f from can_top_level.vhd
+- Offset: `0x474`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_abort_f
+Auto-extracted signal rec_abort_f from can_top_level.vhd
+- Offset: `0x478`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_hw_cmd_int
+Auto-extracted signal txtb_hw_cmd_int from can_top_level.vhd
+- Offset: `0x47c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_is_bus_off
+Auto-extracted signal is_bus_off from can_top_level.vhd
+- Offset: `0x480`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_available
+Auto-extracted signal txtb_available from can_top_level.vhd
+- Offset: `0x484`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_b_clk_en
+Auto-extracted signal txtb_port_b_clk_en from can_top_level.vhd
+- Offset: `0x488`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_dlc
+Auto-extracted signal tran_dlc from can_top_level.vhd
+- Offset: `0x48c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_is_rtr
+Auto-extracted signal tran_is_rtr from can_top_level.vhd
+- Offset: `0x490`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_ident_type
+Auto-extracted signal tran_ident_type from can_top_level.vhd
+- Offset: `0x494`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_frame_type
+Auto-extracted signal tran_frame_type from can_top_level.vhd
+- Offset: `0x498`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_brs
+Auto-extracted signal tran_brs from can_top_level.vhd
+- Offset: `0x49c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_identifier
+Auto-extracted signal tran_identifier from can_top_level.vhd
+- Offset: `0x4a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_word
+Auto-extracted signal tran_word from can_top_level.vhd
+- Offset: `0x4a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_frame_valid
+Auto-extracted signal tran_frame_valid from can_top_level.vhd
+- Offset: `0x4a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_changed
+Auto-extracted signal txtb_changed from can_top_level.vhd
+- Offset: `0x4ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_clk_en
+Auto-extracted signal txtb_clk_en from can_top_level.vhd
+- Offset: `0x4b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_err_detected
+Auto-extracted signal err_detected from can_top_level.vhd
+- Offset: `0x4b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_fcs_changed
+Auto-extracted signal fcs_changed from can_top_level.vhd
+- Offset: `0x4b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_err_warning_limit
+Auto-extracted signal err_warning_limit from can_top_level.vhd
+- Offset: `0x4bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_arbitration_lost
+Auto-extracted signal arbitration_lost from can_top_level.vhd
+- Offset: `0x4c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_valid
+Auto-extracted signal tran_valid from can_top_level.vhd
+- Offset: `0x4c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_br_shifted
+Auto-extracted signal br_shifted from can_top_level.vhd
+- Offset: `0x4c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_is_overload
+Auto-extracted signal is_overload from can_top_level.vhd
+- Offset: `0x4cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_triggers
+Auto-extracted signal rx_triggers from can_top_level.vhd
+- Offset: `0x4d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tx_trigger
+Auto-extracted signal tx_trigger from can_top_level.vhd
+- Offset: `0x4d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sync_control
+Auto-extracted signal sync_control from can_top_level.vhd
+- Offset: `0x4d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_no_pos_resync
+Auto-extracted signal no_pos_resync from can_top_level.vhd
+- Offset: `0x4dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_nbt_ctrs_en
+Auto-extracted signal nbt_ctrs_en from can_top_level.vhd
+- Offset: `0x4e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_dbt_ctrs_en
+Auto-extracted signal dbt_ctrs_en from can_top_level.vhd
+- Offset: `0x4e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_trv_delay
+Auto-extracted signal trv_delay from can_top_level.vhd
+- Offset: `0x4e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_data_wbs
+Auto-extracted signal rx_data_wbs from can_top_level.vhd
+- Offset: `0x4ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tx_data_wbs
+Auto-extracted signal tx_data_wbs from can_top_level.vhd
+- Offset: `0x4f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_ssp_reset
+Auto-extracted signal ssp_reset from can_top_level.vhd
+- Offset: `0x4f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_delay_meas
+Auto-extracted signal tran_delay_meas from can_top_level.vhd
+- Offset: `0x4f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_bit_err
+Auto-extracted signal bit_err from can_top_level.vhd
+- Offset: `0x4fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sample_sec
+Auto-extracted signal sample_sec from can_top_level.vhd
+- Offset: `0x500`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_btmc_reset
+Auto-extracted signal btmc_reset from can_top_level.vhd
+- Offset: `0x504`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_dbt_measure_start
+Auto-extracted signal dbt_measure_start from can_top_level.vhd
+- Offset: `0x508`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_gen_first_ssp
+Auto-extracted signal gen_first_ssp from can_top_level.vhd
+- Offset: `0x50c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sync_edge
+Auto-extracted signal sync_edge from can_top_level.vhd
+- Offset: `0x510`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tq_edge
+Auto-extracted signal tq_edge from can_top_level.vhd
+- Offset: `0x514`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tst_rdata_rx_buf
+Auto-extracted signal tst_rdata_rx_buf from can_top_level.vhd
+- Offset: `0x518`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## clk_gate_clk_en_q
+Auto-extracted signal clk_en_q from clk_gate.vhd
+- Offset: `0x51c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_counter_ctrl_ctr_ce
+Auto-extracted signal ctrl_ctr_ce from control_counter.vhd
+- Offset: `0x520`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_counter_compl_ctr_ce
+Auto-extracted signal compl_ctr_ce from control_counter.vhd
+- Offset: `0x524`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_reg_sel
+Auto-extracted signal reg_sel from control_registers_reg_map.vhd
+- Offset: `0x528`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_data_mux_in
+Auto-extracted signal read_data_mux_in from control_registers_reg_map.vhd
+- Offset: `0x52c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_data_mask_n
+Auto-extracted signal read_data_mask_n from control_registers_reg_map.vhd
+- Offset: `0x530`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_mux_ena
+Auto-extracted signal read_mux_ena from control_registers_reg_map.vhd
+- Offset: `0x534`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_q
+Auto-extracted signal crc_q from crc_calc.vhd
+- Offset: `0x538`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_nxt
+Auto-extracted signal crc_nxt from crc_calc.vhd
+- Offset: `0x53c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_shift
+Auto-extracted signal crc_shift from crc_calc.vhd
+- Offset: `0x540`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_shift_n_xor
+Auto-extracted signal crc_shift_n_xor from crc_calc.vhd
+- Offset: `0x544`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_d
+Auto-extracted signal crc_d from crc_calc.vhd
+- Offset: `0x548`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_ce
+Auto-extracted signal crc_ce from crc_calc.vhd
+- Offset: `0x54c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_data_prev
+Auto-extracted signal rx_data_prev from data_edge_detector.vhd
+- Offset: `0x550`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_tx_data_prev
+Auto-extracted signal tx_data_prev from data_edge_detector.vhd
+- Offset: `0x554`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_data_sync_prev
+Auto-extracted signal rx_data_sync_prev from data_edge_detector.vhd
+- Offset: `0x558`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_edge_i
+Auto-extracted signal rx_edge_i from data_edge_detector.vhd
+- Offset: `0x55c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_tx_edge_i
+Auto-extracted signal tx_edge_i from data_edge_detector.vhd
+- Offset: `0x560`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_sel_data
+Auto-extracted signal sel_data from data_mux.vhd
+- Offset: `0x564`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_saturated_data
+Auto-extracted signal saturated_data from data_mux.vhd
+- Offset: `0x568`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_masked_data
+Auto-extracted signal masked_data from data_mux.vhd
+- Offset: `0x56c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_8_to_64
+Auto-extracted signal data_len_8_to_64 from dlc_decoder.vhd
+- Offset: `0x570`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_can_2_0
+Auto-extracted signal data_len_can_2_0 from dlc_decoder.vhd
+- Offset: `0x574`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_can_fd
+Auto-extracted signal data_len_can_fd from dlc_decoder.vhd
+- Offset: `0x578`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## endian_swapper_swapped
+Auto-extracted signal swapped from endian_swapper.vhd
+- Offset: `0x57c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_tx_err_ctr_ce
+Auto-extracted signal tx_err_ctr_ce from err_counters.vhd
+- Offset: `0x580`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_rx_err_ctr_ce
+Auto-extracted signal rx_err_ctr_ce from err_counters.vhd
+- Offset: `0x584`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_modif_tx_ctr
+Auto-extracted signal modif_tx_ctr from err_counters.vhd
+- Offset: `0x588`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_modif_rx_ctr
+Auto-extracted signal modif_rx_ctr from err_counters.vhd
+- Offset: `0x58c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_nom_err_ctr_ce
+Auto-extracted signal nom_err_ctr_ce from err_counters.vhd
+- Offset: `0x590`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_data_err_ctr_ce
+Auto-extracted signal data_err_ctr_ce from err_counters.vhd
+- Offset: `0x594`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_d
+Auto-extracted signal res_err_ctrs_d from err_counters.vhd
+- Offset: `0x598`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_q
+Auto-extracted signal res_err_ctrs_q from err_counters.vhd
+- Offset: `0x59c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_q_scan
+Auto-extracted signal res_err_ctrs_q_scan from err_counters.vhd
+- Offset: `0x5a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_frm_req_i
+Auto-extracted signal err_frm_req_i from err_detector.vhd
+- Offset: `0x5a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_type_d
+Auto-extracted signal err_type_d from err_detector.vhd
+- Offset: `0x5a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_type_q
+Auto-extracted signal err_type_q from err_detector.vhd
+- Offset: `0x5ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_pos_q
+Auto-extracted signal err_pos_q from err_detector.vhd
+- Offset: `0x5b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_form_err_i
+Auto-extracted signal form_err_i from err_detector.vhd
+- Offset: `0x5b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_c
+Auto-extracted signal crc_match_c from err_detector.vhd
+- Offset: `0x5b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_d
+Auto-extracted signal crc_match_d from err_detector.vhd
+- Offset: `0x5bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_q
+Auto-extracted signal crc_match_q from err_detector.vhd
+- Offset: `0x5c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_dst_ctr_grey
+Auto-extracted signal dst_ctr_grey from err_detector.vhd
+- Offset: `0x5c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_dst_parity
+Auto-extracted signal dst_parity from err_detector.vhd
+- Offset: `0x5c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_stuff_count_check
+Auto-extracted signal stuff_count_check from err_detector.vhd
+- Offset: `0x5cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_15_ok
+Auto-extracted signal crc_15_ok from err_detector.vhd
+- Offset: `0x5d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_17_ok
+Auto-extracted signal crc_17_ok from err_detector.vhd
+- Offset: `0x5d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_21_ok
+Auto-extracted signal crc_21_ok from err_detector.vhd
+- Offset: `0x5d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_stuff_count_ok
+Auto-extracted signal stuff_count_ok from err_detector.vhd
+- Offset: `0x5dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_15
+Auto-extracted signal rx_crc_15 from err_detector.vhd
+- Offset: `0x5e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_17
+Auto-extracted signal rx_crc_17 from err_detector.vhd
+- Offset: `0x5e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_21
+Auto-extracted signal rx_crc_21 from err_detector.vhd
+- Offset: `0x5e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ewl
+Auto-extracted signal drv_ewl from fault_confinement.vhd
+- Offset: `0x5ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_erp
+Auto-extracted signal drv_erp from fault_confinement.vhd
+- Offset: `0x5f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ctr_val
+Auto-extracted signal drv_ctr_val from fault_confinement.vhd
+- Offset: `0x5f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ctr_sel
+Auto-extracted signal drv_ctr_sel from fault_confinement.vhd
+- Offset: `0x5f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ena
+Auto-extracted signal drv_ena from fault_confinement.vhd
+- Offset: `0x5fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_tx_err_ctr_i
+Auto-extracted signal tx_err_ctr_i from fault_confinement.vhd
+- Offset: `0x600`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rx_err_ctr_i
+Auto-extracted signal rx_err_ctr_i from fault_confinement.vhd
+- Offset: `0x604`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_inc_one
+Auto-extracted signal inc_one from fault_confinement.vhd
+- Offset: `0x608`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_inc_eight
+Auto-extracted signal inc_eight from fault_confinement.vhd
+- Offset: `0x60c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_dec_one
+Auto-extracted signal dec_one from fault_confinement.vhd
+- Offset: `0x610`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_rom_ena
+Auto-extracted signal drv_rom_ena from fault_confinement.vhd
+- Offset: `0x614`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_erp
+Auto-extracted signal tx_err_ctr_mt_erp from fault_confinement_fsm.vhd
+- Offset: `0x618`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_rx_err_ctr_mt_erp
+Auto-extracted signal rx_err_ctr_mt_erp from fault_confinement_fsm.vhd
+- Offset: `0x61c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_ewl
+Auto-extracted signal tx_err_ctr_mt_ewl from fault_confinement_fsm.vhd
+- Offset: `0x620`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_rx_err_ctr_mt_ewl
+Auto-extracted signal rx_err_ctr_mt_ewl from fault_confinement_fsm.vhd
+- Offset: `0x624`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_255
+Auto-extracted signal tx_err_ctr_mt_255 from fault_confinement_fsm.vhd
+- Offset: `0x628`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_err_warning_limit_d
+Auto-extracted signal err_warning_limit_d from fault_confinement_fsm.vhd
+- Offset: `0x62c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_err_warning_limit_q
+Auto-extracted signal err_warning_limit_q from fault_confinement_fsm.vhd
+- Offset: `0x630`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_fc_fsm_res_d
+Auto-extracted signal fc_fsm_res_d from fault_confinement_fsm.vhd
+- Offset: `0x634`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_fc_fsm_res_q
+Auto-extracted signal fc_fsm_res_q from fault_confinement_fsm.vhd
+- Offset: `0x638`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rules_inc_one_i
+Auto-extracted signal inc_one_i from fault_confinement_rules.vhd
+- Offset: `0x63c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rules_inc_eight_i
+Auto-extracted signal inc_eight_i from fault_confinement_rules.vhd
+- Offset: `0x640`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_mask
+Auto-extracted signal drv_filter_A_mask from frame_filters.vhd
+- Offset: `0x644`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_ctrl
+Auto-extracted signal drv_filter_A_ctrl from frame_filters.vhd
+- Offset: `0x648`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_bits
+Auto-extracted signal drv_filter_A_bits from frame_filters.vhd
+- Offset: `0x64c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_A_valid
+Auto-extracted signal int_filter_A_valid from frame_filters.vhd
+- Offset: `0x650`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_mask
+Auto-extracted signal drv_filter_B_mask from frame_filters.vhd
+- Offset: `0x654`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_ctrl
+Auto-extracted signal drv_filter_B_ctrl from frame_filters.vhd
+- Offset: `0x658`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_bits
+Auto-extracted signal drv_filter_B_bits from frame_filters.vhd
+- Offset: `0x65c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_B_valid
+Auto-extracted signal int_filter_B_valid from frame_filters.vhd
+- Offset: `0x660`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_mask
+Auto-extracted signal drv_filter_C_mask from frame_filters.vhd
+- Offset: `0x664`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_ctrl
+Auto-extracted signal drv_filter_C_ctrl from frame_filters.vhd
+- Offset: `0x668`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_bits
+Auto-extracted signal drv_filter_C_bits from frame_filters.vhd
+- Offset: `0x66c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_C_valid
+Auto-extracted signal int_filter_C_valid from frame_filters.vhd
+- Offset: `0x670`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_ctrl
+Auto-extracted signal drv_filter_ran_ctrl from frame_filters.vhd
+- Offset: `0x674`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_lo_th
+Auto-extracted signal drv_filter_ran_lo_th from frame_filters.vhd
+- Offset: `0x678`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_hi_th
+Auto-extracted signal drv_filter_ran_hi_th from frame_filters.vhd
+- Offset: `0x67c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_ran_valid
+Auto-extracted signal int_filter_ran_valid from frame_filters.vhd
+- Offset: `0x680`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filters_ena
+Auto-extracted signal drv_filters_ena from frame_filters.vhd
+- Offset: `0x684`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_data_type
+Auto-extracted signal int_data_type from frame_filters.vhd
+- Offset: `0x688`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_data_ctrl
+Auto-extracted signal int_data_ctrl from frame_filters.vhd
+- Offset: `0x68c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_A_enable
+Auto-extracted signal filter_A_enable from frame_filters.vhd
+- Offset: `0x690`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_B_enable
+Auto-extracted signal filter_B_enable from frame_filters.vhd
+- Offset: `0x694`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_C_enable
+Auto-extracted signal filter_C_enable from frame_filters.vhd
+- Offset: `0x698`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_range_enable
+Auto-extracted signal filter_range_enable from frame_filters.vhd
+- Offset: `0x69c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_result
+Auto-extracted signal filter_result from frame_filters.vhd
+- Offset: `0x6a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_ident_valid_d
+Auto-extracted signal ident_valid_d from frame_filters.vhd
+- Offset: `0x6a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_ident_valid_q
+Auto-extracted signal ident_valid_q from frame_filters.vhd
+- Offset: `0x6a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_drop_remote_frames
+Auto-extracted signal drv_drop_remote_frames from frame_filters.vhd
+- Offset: `0x6ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drop_rtr_frame
+Auto-extracted signal drop_rtr_frame from frame_filters.vhd
+- Offset: `0x6b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## inf_ram_wrapper_int_read_data
+Auto-extracted signal int_read_data from inf_ram_wrapper.vhd
+- Offset: `0x6b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## inf_ram_wrapper_byte_we
+Auto-extracted signal byte_we from inf_ram_wrapper.vhd
+- Offset: `0x6b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_vect_clr
+Auto-extracted signal drv_int_vect_clr from int_manager.vhd
+- Offset: `0x6bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_ena_set
+Auto-extracted signal drv_int_ena_set from int_manager.vhd
+- Offset: `0x6c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_ena_clr
+Auto-extracted signal drv_int_ena_clr from int_manager.vhd
+- Offset: `0x6c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_mask_set
+Auto-extracted signal drv_int_mask_set from int_manager.vhd
+- Offset: `0x6c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_mask_clr
+Auto-extracted signal drv_int_mask_clr from int_manager.vhd
+- Offset: `0x6cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_ena_i
+Auto-extracted signal int_ena_i from int_manager.vhd
+- Offset: `0x6d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_mask_i
+Auto-extracted signal int_mask_i from int_manager.vhd
+- Offset: `0x6d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_vect_i
+Auto-extracted signal int_vect_i from int_manager.vhd
+- Offset: `0x6d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_input_active
+Auto-extracted signal int_input_active from int_manager.vhd
+- Offset: `0x6dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_i
+Auto-extracted signal int_i from int_manager.vhd
+- Offset: `0x6e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_i
+Auto-extracted signal int_mask_i from int_module.vhd
+- Offset: `0x6e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_ena_i
+Auto-extracted signal int_ena_i from int_module.vhd
+- Offset: `0x6e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_load
+Auto-extracted signal int_mask_load from int_module.vhd
+- Offset: `0x6ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_next
+Auto-extracted signal int_mask_next from int_module.vhd
+- Offset: `0x6f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_reg_value_r
+Auto-extracted signal reg_value_r from memory_reg.vhd
+- Offset: `0x6f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_wr_select
+Auto-extracted signal wr_select from memory_reg.vhd
+- Offset: `0x6f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_wr_select_expanded
+Auto-extracted signal wr_select_expanded from memory_reg.vhd
+- Offset: `0x6fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_status_comb
+Auto-extracted signal status_comb from memory_registers.vhd
+- Offset: `0x700`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_can_core_cs
+Auto-extracted signal can_core_cs from memory_registers.vhd
+- Offset: `0x704`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_cs
+Auto-extracted signal control_registers_cs from memory_registers.vhd
+- Offset: `0x708`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_cs_reg
+Auto-extracted signal control_registers_cs_reg from memory_registers.vhd
+- Offset: `0x70c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_cs
+Auto-extracted signal test_registers_cs from memory_registers.vhd
+- Offset: `0x710`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_cs_reg
+Auto-extracted signal test_registers_cs_reg from memory_registers.vhd
+- Offset: `0x714`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_rdata
+Auto-extracted signal control_registers_rdata from memory_registers.vhd
+- Offset: `0x718`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_rdata
+Auto-extracted signal test_registers_rdata from memory_registers.vhd
+- Offset: `0x71c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_err_active
+Auto-extracted signal is_err_active from memory_registers.vhd
+- Offset: `0x720`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_err_passive
+Auto-extracted signal is_err_passive from memory_registers.vhd
+- Offset: `0x724`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_bus_off
+Auto-extracted signal is_bus_off from memory_registers.vhd
+- Offset: `0x728`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_transmitter
+Auto-extracted signal is_transmitter from memory_registers.vhd
+- Offset: `0x72c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_receiver
+Auto-extracted signal is_receiver from memory_registers.vhd
+- Offset: `0x730`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_idle
+Auto-extracted signal is_idle from memory_registers.vhd
+- Offset: `0x734`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_reg_lock_1_active
+Auto-extracted signal reg_lock_1_active from memory_registers.vhd
+- Offset: `0x738`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_reg_lock_2_active
+Auto-extracted signal reg_lock_2_active from memory_registers.vhd
+- Offset: `0x73c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_soft_res_q_n
+Auto-extracted signal soft_res_q_n from memory_registers.vhd
+- Offset: `0x740`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_ewl_padded
+Auto-extracted signal ewl_padded from memory_registers.vhd
+- Offset: `0x744`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_regs_clk_en
+Auto-extracted signal control_regs_clk_en from memory_registers.vhd
+- Offset: `0x748`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_regs_clk_en
+Auto-extracted signal test_regs_clk_en from memory_registers.vhd
+- Offset: `0x74c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_clk_control_regs
+Auto-extracted signal clk_control_regs from memory_registers.vhd
+- Offset: `0x750`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_clk_test_regs
+Auto-extracted signal clk_test_regs from memory_registers.vhd
+- Offset: `0x754`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_rx_buf_mode
+Auto-extracted signal rx_buf_mode from memory_registers.vhd
+- Offset: `0x758`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_rx_move_cmd
+Auto-extracted signal rx_move_cmd from memory_registers.vhd
+- Offset: `0x75c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_ctr_pres_sel_q
+Auto-extracted signal ctr_pres_sel_q from memory_registers.vhd
+- Offset: `0x760`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## operation_control_drv_ena
+Auto-extracted signal drv_ena from operation_control.vhd
+- Offset: `0x764`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## operation_control_go_to_off
+Auto-extracted signal go_to_off from operation_control.vhd
+- Offset: `0x768`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_drv_ena
+Auto-extracted signal drv_ena from prescaler.vhd
+- Offset: `0x76c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg1_nbt
+Auto-extracted signal tseg1_nbt from prescaler.vhd
+- Offset: `0x770`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg2_nbt
+Auto-extracted signal tseg2_nbt from prescaler.vhd
+- Offset: `0x774`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_brp_nbt
+Auto-extracted signal brp_nbt from prescaler.vhd
+- Offset: `0x778`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_sjw_nbt
+Auto-extracted signal sjw_nbt from prescaler.vhd
+- Offset: `0x77c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg1_dbt
+Auto-extracted signal tseg1_dbt from prescaler.vhd
+- Offset: `0x780`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg2_dbt
+Auto-extracted signal tseg2_dbt from prescaler.vhd
+- Offset: `0x784`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_brp_dbt
+Auto-extracted signal brp_dbt from prescaler.vhd
+- Offset: `0x788`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_sjw_dbt
+Auto-extracted signal sjw_dbt from prescaler.vhd
+- Offset: `0x78c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segment_end
+Auto-extracted signal segment_end from prescaler.vhd
+- Offset: `0x790`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_h_sync_valid
+Auto-extracted signal h_sync_valid from prescaler.vhd
+- Offset: `0x794`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_is_tseg1
+Auto-extracted signal is_tseg1 from prescaler.vhd
+- Offset: `0x798`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_is_tseg2
+Auto-extracted signal is_tseg2 from prescaler.vhd
+- Offset: `0x79c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_resync_edge_valid
+Auto-extracted signal resync_edge_valid from prescaler.vhd
+- Offset: `0x7a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_h_sync_edge_valid
+Auto-extracted signal h_sync_edge_valid from prescaler.vhd
+- Offset: `0x7a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segm_counter_nbt
+Auto-extracted signal segm_counter_nbt from prescaler.vhd
+- Offset: `0x7a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segm_counter_dbt
+Auto-extracted signal segm_counter_dbt from prescaler.vhd
+- Offset: `0x7ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_exit_segm_req_nbt
+Auto-extracted signal exit_segm_req_nbt from prescaler.vhd
+- Offset: `0x7b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_exit_segm_req_dbt
+Auto-extracted signal exit_segm_req_dbt from prescaler.vhd
+- Offset: `0x7b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tq_edge_nbt
+Auto-extracted signal tq_edge_nbt from prescaler.vhd
+- Offset: `0x7b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tq_edge_dbt
+Auto-extracted signal tq_edge_dbt from prescaler.vhd
+- Offset: `0x7bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_rx_trig_req
+Auto-extracted signal rx_trig_req from prescaler.vhd
+- Offset: `0x7c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tx_trig_req
+Auto-extracted signal tx_trig_req from prescaler.vhd
+- Offset: `0x7c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_start_edge
+Auto-extracted signal start_edge from prescaler.vhd
+- Offset: `0x7c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_bt_ctr_clear
+Auto-extracted signal bt_ctr_clear from prescaler.vhd
+- Offset: `0x7cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l0_valid
+Auto-extracted signal l0_valid from priority_decoder.vhd
+- Offset: `0x7d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l1_valid
+Auto-extracted signal l1_valid from priority_decoder.vhd
+- Offset: `0x7d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l1_winner
+Auto-extracted signal l1_winner from priority_decoder.vhd
+- Offset: `0x7d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l2_valid
+Auto-extracted signal l2_valid from priority_decoder.vhd
+- Offset: `0x7dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l2_winner
+Auto-extracted signal l2_winner from priority_decoder.vhd
+- Offset: `0x7e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l3_valid
+Auto-extracted signal l3_valid from priority_decoder.vhd
+- Offset: `0x7e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l3_winner
+Auto-extracted signal l3_winner from priority_decoder.vhd
+- Offset: `0x7e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_can_fd_ena
+Auto-extracted signal drv_can_fd_ena from protocol_control.vhd
+- Offset: `0x7ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_bus_mon_ena
+Auto-extracted signal drv_bus_mon_ena from protocol_control.vhd
+- Offset: `0x7f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_retr_lim_ena
+Auto-extracted signal drv_retr_lim_ena from protocol_control.vhd
+- Offset: `0x7f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_retr_th
+Auto-extracted signal drv_retr_th from protocol_control.vhd
+- Offset: `0x7f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_self_test_ena
+Auto-extracted signal drv_self_test_ena from protocol_control.vhd
+- Offset: `0x7fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ack_forb
+Auto-extracted signal drv_ack_forb from protocol_control.vhd
+- Offset: `0x800`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ena
+Auto-extracted signal drv_ena from protocol_control.vhd
+- Offset: `0x804`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_fd_type
+Auto-extracted signal drv_fd_type from protocol_control.vhd
+- Offset: `0x808`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_int_loopback_ena
+Auto-extracted signal drv_int_loopback_ena from protocol_control.vhd
+- Offset: `0x80c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_bus_off_reset
+Auto-extracted signal drv_bus_off_reset from protocol_control.vhd
+- Offset: `0x810`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ssp_delay_select
+Auto-extracted signal drv_ssp_delay_select from protocol_control.vhd
+- Offset: `0x814`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_pex
+Auto-extracted signal drv_pex from protocol_control.vhd
+- Offset: `0x818`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_cpexs
+Auto-extracted signal drv_cpexs from protocol_control.vhd
+- Offset: `0x81c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tran_word_swapped
+Auto-extracted signal tran_word_swapped from protocol_control.vhd
+- Offset: `0x820`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_err_frm_req
+Auto-extracted signal err_frm_req from protocol_control.vhd
+- Offset: `0x824`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_base_id
+Auto-extracted signal tx_load_base_id from protocol_control.vhd
+- Offset: `0x828`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_ext_id
+Auto-extracted signal tx_load_ext_id from protocol_control.vhd
+- Offset: `0x82c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_dlc
+Auto-extracted signal tx_load_dlc from protocol_control.vhd
+- Offset: `0x830`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_data_word
+Auto-extracted signal tx_load_data_word from protocol_control.vhd
+- Offset: `0x834`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_stuff_count
+Auto-extracted signal tx_load_stuff_count from protocol_control.vhd
+- Offset: `0x838`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_crc
+Auto-extracted signal tx_load_crc from protocol_control.vhd
+- Offset: `0x83c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_shift_ena
+Auto-extracted signal tx_shift_ena from protocol_control.vhd
+- Offset: `0x840`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_dominant
+Auto-extracted signal tx_dominant from protocol_control.vhd
+- Offset: `0x844`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_clear
+Auto-extracted signal rx_clear from protocol_control.vhd
+- Offset: `0x848`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_base_id
+Auto-extracted signal rx_store_base_id from protocol_control.vhd
+- Offset: `0x84c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_ext_id
+Auto-extracted signal rx_store_ext_id from protocol_control.vhd
+- Offset: `0x850`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_ide
+Auto-extracted signal rx_store_ide from protocol_control.vhd
+- Offset: `0x854`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_rtr
+Auto-extracted signal rx_store_rtr from protocol_control.vhd
+- Offset: `0x858`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_edl
+Auto-extracted signal rx_store_edl from protocol_control.vhd
+- Offset: `0x85c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_dlc
+Auto-extracted signal rx_store_dlc from protocol_control.vhd
+- Offset: `0x860`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_esi
+Auto-extracted signal rx_store_esi from protocol_control.vhd
+- Offset: `0x864`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_brs
+Auto-extracted signal rx_store_brs from protocol_control.vhd
+- Offset: `0x868`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_stuff_count
+Auto-extracted signal rx_store_stuff_count from protocol_control.vhd
+- Offset: `0x86c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_shift_ena
+Auto-extracted signal rx_shift_ena from protocol_control.vhd
+- Offset: `0x870`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_shift_in_sel
+Auto-extracted signal rx_shift_in_sel from protocol_control.vhd
+- Offset: `0x874`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from protocol_control.vhd
+- Offset: `0x878`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_dlc_d
+Auto-extracted signal rec_dlc_d from protocol_control.vhd
+- Offset: `0x87c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_dlc_q
+Auto-extracted signal rec_dlc_q from protocol_control.vhd
+- Offset: `0x880`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from protocol_control.vhd
+- Offset: `0x884`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_pload
+Auto-extracted signal ctrl_ctr_pload from protocol_control.vhd
+- Offset: `0x888`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_pload_val
+Auto-extracted signal ctrl_ctr_pload_val from protocol_control.vhd
+- Offset: `0x88c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_ena
+Auto-extracted signal ctrl_ctr_ena from protocol_control.vhd
+- Offset: `0x890`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_zero
+Auto-extracted signal ctrl_ctr_zero from protocol_control.vhd
+- Offset: `0x894`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_one
+Auto-extracted signal ctrl_ctr_one from protocol_control.vhd
+- Offset: `0x898`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_counted_byte
+Auto-extracted signal ctrl_counted_byte from protocol_control.vhd
+- Offset: `0x89c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_counted_byte_index
+Auto-extracted signal ctrl_counted_byte_index from protocol_control.vhd
+- Offset: `0x8a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_mem_index
+Auto-extracted signal ctrl_ctr_mem_index from protocol_control.vhd
+- Offset: `0x8a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_compl_ctr_ena
+Auto-extracted signal compl_ctr_ena from protocol_control.vhd
+- Offset: `0x8a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_clr
+Auto-extracted signal reinteg_ctr_clr from protocol_control.vhd
+- Offset: `0x8ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_enable
+Auto-extracted signal reinteg_ctr_enable from protocol_control.vhd
+- Offset: `0x8b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_expired
+Auto-extracted signal reinteg_ctr_expired from protocol_control.vhd
+- Offset: `0x8b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_ctr_clear
+Auto-extracted signal retr_ctr_clear from protocol_control.vhd
+- Offset: `0x8b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_ctr_add
+Auto-extracted signal retr_ctr_add from protocol_control.vhd
+- Offset: `0x8bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_limit_reached
+Auto-extracted signal retr_limit_reached from protocol_control.vhd
+- Offset: `0x8c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_form_err_i
+Auto-extracted signal form_err_i from protocol_control.vhd
+- Offset: `0x8c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ack_err_i
+Auto-extracted signal ack_err_i from protocol_control.vhd
+- Offset: `0x8c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_check
+Auto-extracted signal crc_check from protocol_control.vhd
+- Offset: `0x8cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_bit_err_arb
+Auto-extracted signal bit_err_arb from protocol_control.vhd
+- Offset: `0x8d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_match
+Auto-extracted signal crc_match from protocol_control.vhd
+- Offset: `0x8d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_err_i
+Auto-extracted signal crc_err_i from protocol_control.vhd
+- Offset: `0x8d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_clear_match_flag
+Auto-extracted signal crc_clear_match_flag from protocol_control.vhd
+- Offset: `0x8dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_src
+Auto-extracted signal crc_src from protocol_control.vhd
+- Offset: `0x8e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_err_pos
+Auto-extracted signal err_pos from protocol_control.vhd
+- Offset: `0x8e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_is_arbitration_i
+Auto-extracted signal is_arbitration_i from protocol_control.vhd
+- Offset: `0x8e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_bit_err_enable
+Auto-extracted signal bit_err_enable from protocol_control.vhd
+- Offset: `0x8ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_data_nbs_i
+Auto-extracted signal tx_data_nbs_i from protocol_control.vhd
+- Offset: `0x8f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_crc
+Auto-extracted signal rx_crc from protocol_control.vhd
+- Offset: `0x8f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_stuff_count
+Auto-extracted signal rx_stuff_count from protocol_control.vhd
+- Offset: `0x8f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fixed_stuff_i
+Auto-extracted signal fixed_stuff_i from protocol_control.vhd
+- Offset: `0x8fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from protocol_control.vhd
+- Offset: `0x900`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_alc_id_field
+Auto-extracted signal alc_id_field from protocol_control.vhd
+- Offset: `0x904`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_rom_ena
+Auto-extracted signal drv_rom_ena from protocol_control.vhd
+- Offset: `0x908`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_state_reg_ce
+Auto-extracted signal state_reg_ce from protocol_control_fsm.vhd
+- Offset: `0x90c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_transmitter
+Auto-extracted signal no_data_transmitter from protocol_control_fsm.vhd
+- Offset: `0x910`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_receiver
+Auto-extracted signal no_data_receiver from protocol_control_fsm.vhd
+- Offset: `0x914`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_field
+Auto-extracted signal no_data_field from protocol_control_fsm.vhd
+- Offset: `0x918`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_ctr_pload_i
+Auto-extracted signal ctrl_ctr_pload_i from protocol_control_fsm.vhd
+- Offset: `0x91c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_ctr_pload_unaliged
+Auto-extracted signal ctrl_ctr_pload_unaliged from protocol_control_fsm.vhd
+- Offset: `0x920`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_use_21
+Auto-extracted signal crc_use_21 from protocol_control_fsm.vhd
+- Offset: `0x924`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_use_17
+Auto-extracted signal crc_use_17 from protocol_control_fsm.vhd
+- Offset: `0x928`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_src_i
+Auto-extracted signal crc_src_i from protocol_control_fsm.vhd
+- Offset: `0x92c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_length_i
+Auto-extracted signal crc_length_i from protocol_control_fsm.vhd
+- Offset: `0x930`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tran_data_length
+Auto-extracted signal tran_data_length from protocol_control_fsm.vhd
+- Offset: `0x934`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_data_length
+Auto-extracted signal rec_data_length from protocol_control_fsm.vhd
+- Offset: `0x938`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_data_length_c
+Auto-extracted signal rec_data_length_c from protocol_control_fsm.vhd
+- Offset: `0x93c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_c
+Auto-extracted signal data_length_c from protocol_control_fsm.vhd
+- Offset: `0x940`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_shifted_c
+Auto-extracted signal data_length_shifted_c from protocol_control_fsm.vhd
+- Offset: `0x944`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_bits_c
+Auto-extracted signal data_length_bits_c from protocol_control_fsm.vhd
+- Offset: `0x948`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_is_fd_frame
+Auto-extracted signal is_fd_frame from protocol_control_fsm.vhd
+- Offset: `0x94c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_frame_start
+Auto-extracted signal frame_start from protocol_control_fsm.vhd
+- Offset: `0x950`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_ready
+Auto-extracted signal tx_frame_ready from protocol_control_fsm.vhd
+- Offset: `0x954`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ide_is_arbitration
+Auto-extracted signal ide_is_arbitration from protocol_control_fsm.vhd
+- Offset: `0x958`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_arbitration_lost_condition
+Auto-extracted signal arbitration_lost_condition from protocol_control_fsm.vhd
+- Offset: `0x95c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from protocol_control_fsm.vhd
+- Offset: `0x960`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_failed
+Auto-extracted signal tx_failed from protocol_control_fsm.vhd
+- Offset: `0x964`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_store_metadata_d
+Auto-extracted signal store_metadata_d from protocol_control_fsm.vhd
+- Offset: `0x968`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_store_data_d
+Auto-extracted signal store_data_d from protocol_control_fsm.vhd
+- Offset: `0x96c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_valid_d
+Auto-extracted signal rec_valid_d from protocol_control_fsm.vhd
+- Offset: `0x970`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_abort_d
+Auto-extracted signal rec_abort_d from protocol_control_fsm.vhd
+- Offset: `0x974`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_go_to_suspend
+Auto-extracted signal go_to_suspend from protocol_control_fsm.vhd
+- Offset: `0x978`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_go_to_stuff_count
+Auto-extracted signal go_to_stuff_count from protocol_control_fsm.vhd
+- Offset: `0x97c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_base_id_i
+Auto-extracted signal rx_store_base_id_i from protocol_control_fsm.vhd
+- Offset: `0x980`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_ext_id_i
+Auto-extracted signal rx_store_ext_id_i from protocol_control_fsm.vhd
+- Offset: `0x984`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_ide_i
+Auto-extracted signal rx_store_ide_i from protocol_control_fsm.vhd
+- Offset: `0x988`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_rtr_i
+Auto-extracted signal rx_store_rtr_i from protocol_control_fsm.vhd
+- Offset: `0x98c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_edl_i
+Auto-extracted signal rx_store_edl_i from protocol_control_fsm.vhd
+- Offset: `0x990`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_dlc_i
+Auto-extracted signal rx_store_dlc_i from protocol_control_fsm.vhd
+- Offset: `0x994`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_esi_i
+Auto-extracted signal rx_store_esi_i from protocol_control_fsm.vhd
+- Offset: `0x998`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_brs_i
+Auto-extracted signal rx_store_brs_i from protocol_control_fsm.vhd
+- Offset: `0x99c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_stuff_count_i
+Auto-extracted signal rx_store_stuff_count_i from protocol_control_fsm.vhd
+- Offset: `0x9a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_clear_i
+Auto-extracted signal rx_clear_i from protocol_control_fsm.vhd
+- Offset: `0x9a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_base_id_i
+Auto-extracted signal tx_load_base_id_i from protocol_control_fsm.vhd
+- Offset: `0x9a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_ext_id_i
+Auto-extracted signal tx_load_ext_id_i from protocol_control_fsm.vhd
+- Offset: `0x9ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_dlc_i
+Auto-extracted signal tx_load_dlc_i from protocol_control_fsm.vhd
+- Offset: `0x9b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_data_word_i
+Auto-extracted signal tx_load_data_word_i from protocol_control_fsm.vhd
+- Offset: `0x9b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_stuff_count_i
+Auto-extracted signal tx_load_stuff_count_i from protocol_control_fsm.vhd
+- Offset: `0x9b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_crc_i
+Auto-extracted signal tx_load_crc_i from protocol_control_fsm.vhd
+- Offset: `0x9bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_shift_ena_i
+Auto-extracted signal tx_shift_ena_i from protocol_control_fsm.vhd
+- Offset: `0x9c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_form_err_i
+Auto-extracted signal form_err_i from protocol_control_fsm.vhd
+- Offset: `0x9c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_i
+Auto-extracted signal ack_err_i from protocol_control_fsm.vhd
+- Offset: `0x9c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_flag
+Auto-extracted signal ack_err_flag from protocol_control_fsm.vhd
+- Offset: `0x9cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_flag_clr
+Auto-extracted signal ack_err_flag_clr from protocol_control_fsm.vhd
+- Offset: `0x9d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_err_i
+Auto-extracted signal crc_err_i from protocol_control_fsm.vhd
+- Offset: `0x9d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_arb_i
+Auto-extracted signal bit_err_arb_i from protocol_control_fsm.vhd
+- Offset: `0x9d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_switch_data
+Auto-extracted signal sp_control_switch_data from protocol_control_fsm.vhd
+- Offset: `0x9dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_switch_nominal
+Auto-extracted signal sp_control_switch_nominal from protocol_control_fsm.vhd
+- Offset: `0x9e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_switch_to_ssp
+Auto-extracted signal switch_to_ssp from protocol_control_fsm.vhd
+- Offset: `0x9e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_ce
+Auto-extracted signal sp_control_ce from protocol_control_fsm.vhd
+- Offset: `0x9e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_d
+Auto-extracted signal sp_control_d from protocol_control_fsm.vhd
+- Offset: `0x9ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_q_i
+Auto-extracted signal sp_control_q_i from protocol_control_fsm.vhd
+- Offset: `0x9f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ssp_reset_i
+Auto-extracted signal ssp_reset_i from protocol_control_fsm.vhd
+- Offset: `0x9f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sync_control_d
+Auto-extracted signal sync_control_d from protocol_control_fsm.vhd
+- Offset: `0x9f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sync_control_q
+Auto-extracted signal sync_control_q from protocol_control_fsm.vhd
+- Offset: `0x9fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_perform_hsync
+Auto-extracted signal perform_hsync from protocol_control_fsm.vhd
+- Offset: `0xa00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_primary_err_i
+Auto-extracted signal primary_err_i from protocol_control_fsm.vhd
+- Offset: `0xa04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_err_delim_late_i
+Auto-extracted signal err_delim_late_i from protocol_control_fsm.vhd
+- Offset: `0xa08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_err_active_i
+Auto-extracted signal set_err_active_i from protocol_control_fsm.vhd
+- Offset: `0xa0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_transmitter_i
+Auto-extracted signal set_transmitter_i from protocol_control_fsm.vhd
+- Offset: `0xa10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_receiver_i
+Auto-extracted signal set_receiver_i from protocol_control_fsm.vhd
+- Offset: `0xa14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_idle_i
+Auto-extracted signal set_idle_i from protocol_control_fsm.vhd
+- Offset: `0xa18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_first_err_delim_d
+Auto-extracted signal first_err_delim_d from protocol_control_fsm.vhd
+- Offset: `0xa1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_first_err_delim_q
+Auto-extracted signal first_err_delim_q from protocol_control_fsm.vhd
+- Offset: `0xa20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_stuff_enable_set
+Auto-extracted signal stuff_enable_set from protocol_control_fsm.vhd
+- Offset: `0xa24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_stuff_enable_clear
+Auto-extracted signal stuff_enable_clear from protocol_control_fsm.vhd
+- Offset: `0xa28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_destuff_enable_set
+Auto-extracted signal destuff_enable_set from protocol_control_fsm.vhd
+- Offset: `0xa2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_destuff_enable_clear
+Auto-extracted signal destuff_enable_clear from protocol_control_fsm.vhd
+- Offset: `0xa30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_disable
+Auto-extracted signal bit_err_disable from protocol_control_fsm.vhd
+- Offset: `0xa34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_disable_receiver
+Auto-extracted signal bit_err_disable_receiver from protocol_control_fsm.vhd
+- Offset: `0xa38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sof_pulse_i
+Auto-extracted signal sof_pulse_i from protocol_control_fsm.vhd
+- Offset: `0xa3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_compl_ctr_ena_i
+Auto-extracted signal compl_ctr_ena_i from protocol_control_fsm.vhd
+- Offset: `0xa40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tick_state_reg
+Auto-extracted signal tick_state_reg from protocol_control_fsm.vhd
+- Offset: `0xa44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_br_shifted_i
+Auto-extracted signal br_shifted_i from protocol_control_fsm.vhd
+- Offset: `0xa48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_is_arbitration_i
+Auto-extracted signal is_arbitration_i from protocol_control_fsm.vhd
+- Offset: `0xa4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_spec_enable_i
+Auto-extracted signal crc_spec_enable_i from protocol_control_fsm.vhd
+- Offset: `0xa50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_load_init_vect_i
+Auto-extracted signal load_init_vect_i from protocol_control_fsm.vhd
+- Offset: `0xa54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_drv_bus_off_reset_q
+Auto-extracted signal drv_bus_off_reset_q from protocol_control_fsm.vhd
+- Offset: `0xa58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_clear_i
+Auto-extracted signal retr_ctr_clear_i from protocol_control_fsm.vhd
+- Offset: `0xa5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_i
+Auto-extracted signal retr_ctr_add_i from protocol_control_fsm.vhd
+- Offset: `0xa60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_decrement_rec_i
+Auto-extracted signal decrement_rec_i from protocol_control_fsm.vhd
+- Offset: `0xa64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_block
+Auto-extracted signal retr_ctr_add_block from protocol_control_fsm.vhd
+- Offset: `0xa68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_block_clr
+Auto-extracted signal retr_ctr_add_block_clr from protocol_control_fsm.vhd
+- Offset: `0xa6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_block_txtb_unlock
+Auto-extracted signal block_txtb_unlock from protocol_control_fsm.vhd
+- Offset: `0xa70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_no_sof_d
+Auto-extracted signal tx_frame_no_sof_d from protocol_control_fsm.vhd
+- Offset: `0xa74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_no_sof_q
+Auto-extracted signal tx_frame_no_sof_q from protocol_control_fsm.vhd
+- Offset: `0xa78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_signal_upd
+Auto-extracted signal ctrl_signal_upd from protocol_control_fsm.vhd
+- Offset: `0xa7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_clr_bus_off_rst_flg
+Auto-extracted signal clr_bus_off_rst_flg from protocol_control_fsm.vhd
+- Offset: `0xa80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pex_on_fdf_enable
+Auto-extracted signal pex_on_fdf_enable from protocol_control_fsm.vhd
+- Offset: `0xa84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pex_on_res_enable
+Auto-extracted signal pex_on_res_enable from protocol_control_fsm.vhd
+- Offset: `0xa88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_data_nbs_prev
+Auto-extracted signal rx_data_nbs_prev from protocol_control_fsm.vhd
+- Offset: `0xa8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pexs_set
+Auto-extracted signal pexs_set from protocol_control_fsm.vhd
+- Offset: `0xa90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tran_frame_type_i
+Auto-extracted signal tran_frame_type_i from protocol_control_fsm.vhd
+- Offset: `0xa94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_txtb_clk_en_d
+Auto-extracted signal txtb_clk_en_d from protocol_control_fsm.vhd
+- Offset: `0xa98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_txtb_clk_en_q
+Auto-extracted signal txtb_clk_en_q from protocol_control_fsm.vhd
+- Offset: `0xa9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## reintegration_counter_reinteg_ctr_ce
+Auto-extracted signal reinteg_ctr_ce from reintegration_counter.vhd
+- Offset: `0xaa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## retransmitt_counter_retr_ctr_ce
+Auto-extracted signal retr_ctr_ce from retransmitt_counter.vhd
+- Offset: `0xaa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rst_sync_rff
+Auto-extracted signal rff from rst_sync.vhd
+- Offset: `0xaa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_erase_rx
+Auto-extracted signal drv_erase_rx from rx_buffer.vhd
+- Offset: `0xaac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_read_start
+Auto-extracted signal drv_read_start from rx_buffer.vhd
+- Offset: `0xab0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_clr_ovr
+Auto-extracted signal drv_clr_ovr from rx_buffer.vhd
+- Offset: `0xab4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_rtsopt
+Auto-extracted signal drv_rtsopt from rx_buffer.vhd
+- Offset: `0xab8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_pointer
+Auto-extracted signal read_pointer from rx_buffer.vhd
+- Offset: `0xabc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_pointer_inc_1
+Auto-extracted signal read_pointer_inc_1 from rx_buffer.vhd
+- Offset: `0xac0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer
+Auto-extracted signal write_pointer from rx_buffer.vhd
+- Offset: `0xac4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer_raw
+Auto-extracted signal write_pointer_raw from rx_buffer.vhd
+- Offset: `0xac8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer_ts
+Auto-extracted signal write_pointer_ts from rx_buffer.vhd
+- Offset: `0xacc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_mem_free_i
+Auto-extracted signal rx_mem_free_i from rx_buffer.vhd
+- Offset: `0xad0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_memory_write_data
+Auto-extracted signal memory_write_data from rx_buffer.vhd
+- Offset: `0xad4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_overrun_flg
+Auto-extracted signal data_overrun_flg from rx_buffer.vhd
+- Offset: `0xad8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_overrun_i
+Auto-extracted signal data_overrun_i from rx_buffer.vhd
+- Offset: `0xadc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_overrun_condition
+Auto-extracted signal overrun_condition from rx_buffer.vhd
+- Offset: `0xae0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_empty_i
+Auto-extracted signal rx_empty_i from rx_buffer.vhd
+- Offset: `0xae4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_is_free_word
+Auto-extracted signal is_free_word from rx_buffer.vhd
+- Offset: `0xae8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_commit_rx_frame
+Auto-extracted signal commit_rx_frame from rx_buffer.vhd
+- Offset: `0xaec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_commit_overrun_abort
+Auto-extracted signal commit_overrun_abort from rx_buffer.vhd
+- Offset: `0xaf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_increment
+Auto-extracted signal read_increment from rx_buffer.vhd
+- Offset: `0xaf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_raw_OK
+Auto-extracted signal write_raw_OK from rx_buffer.vhd
+- Offset: `0xaf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_raw_intent
+Auto-extracted signal write_raw_intent from rx_buffer.vhd
+- Offset: `0xafc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_ts
+Auto-extracted signal write_ts from rx_buffer.vhd
+- Offset: `0xb00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_stored_ts
+Auto-extracted signal stored_ts from rx_buffer.vhd
+- Offset: `0xb04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_selector
+Auto-extracted signal data_selector from rx_buffer.vhd
+- Offset: `0xb08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_store_ts_wr_ptr
+Auto-extracted signal store_ts_wr_ptr from rx_buffer.vhd
+- Offset: `0xb0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_inc_ts_wr_ptr
+Auto-extracted signal inc_ts_wr_ptr from rx_buffer.vhd
+- Offset: `0xb10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_reset_overrun_flag
+Auto-extracted signal reset_overrun_flag from rx_buffer.vhd
+- Offset: `0xb14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_frame_form_w
+Auto-extracted signal frame_form_w from rx_buffer.vhd
+- Offset: `0xb18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_timestamp_capture
+Auto-extracted signal timestamp_capture from rx_buffer.vhd
+- Offset: `0xb1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_timestamp_capture_ce
+Auto-extracted signal timestamp_capture_ce from rx_buffer.vhd
+- Offset: `0xb20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_write
+Auto-extracted signal RAM_write from rx_buffer.vhd
+- Offset: `0xb24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_data_out
+Auto-extracted signal RAM_data_out from rx_buffer.vhd
+- Offset: `0xb28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_write_address
+Auto-extracted signal RAM_write_address from rx_buffer.vhd
+- Offset: `0xb2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_read_address
+Auto-extracted signal RAM_read_address from rx_buffer.vhd
+- Offset: `0xb30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_d
+Auto-extracted signal rx_buf_res_n_d from rx_buffer.vhd
+- Offset: `0xb34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_q
+Auto-extracted signal rx_buf_res_n_q from rx_buffer.vhd
+- Offset: `0xb38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_q_scan
+Auto-extracted signal rx_buf_res_n_q_scan from rx_buffer.vhd
+- Offset: `0xb3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_ram_clk_en
+Auto-extracted signal rx_buf_ram_clk_en from rx_buffer.vhd
+- Offset: `0xb40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_clk_ram
+Auto-extracted signal clk_ram from rx_buffer.vhd
+- Offset: `0xb44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_fsm_rx_fsm_ce
+Auto-extracted signal rx_fsm_ce from rx_buffer_fsm.vhd
+- Offset: `0xb48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_fsm_cmd_join
+Auto-extracted signal cmd_join from rx_buffer_fsm.vhd
+- Offset: `0xb4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_pointers_write_pointer_raw_ce
+Auto-extracted signal write_pointer_raw_ce from rx_buffer_pointers.vhd
+- Offset: `0xb50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_pointers_write_pointer_ts_ce
+Auto-extracted signal write_pointer_ts_ce from rx_buffer_pointers.vhd
+- Offset: `0xb54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_address_i
+Auto-extracted signal port_a_address_i from rx_buffer_ram.vhd
+- Offset: `0xb58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_write_i
+Auto-extracted signal port_a_write_i from rx_buffer_ram.vhd
+- Offset: `0xb5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_data_in_i
+Auto-extracted signal port_a_data_in_i from rx_buffer_ram.vhd
+- Offset: `0xb60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_b_address_i
+Auto-extracted signal port_b_address_i from rx_buffer_ram.vhd
+- Offset: `0xb64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_b_data_out_i
+Auto-extracted signal port_b_data_out_i from rx_buffer_ram.vhd
+- Offset: `0xb68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_tst_ena
+Auto-extracted signal tst_ena from rx_buffer_ram.vhd
+- Offset: `0xb6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_tst_addr
+Auto-extracted signal tst_addr from rx_buffer_ram.vhd
+- Offset: `0xb70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_d
+Auto-extracted signal res_n_i_d from rx_shift_reg.vhd
+- Offset: `0xb74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_q
+Auto-extracted signal res_n_i_q from rx_shift_reg.vhd
+- Offset: `0xb78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_q_scan
+Auto-extracted signal res_n_i_q_scan from rx_shift_reg.vhd
+- Offset: `0xb7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_reg_q
+Auto-extracted signal rx_shift_reg_q from rx_shift_reg.vhd
+- Offset: `0xb80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_cmd
+Auto-extracted signal rx_shift_cmd from rx_shift_reg.vhd
+- Offset: `0xb84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_in_sel_demuxed
+Auto-extracted signal rx_shift_in_sel_demuxed from rx_shift_reg.vhd
+- Offset: `0xb88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from rx_shift_reg.vhd
+- Offset: `0xb8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from rx_shift_reg.vhd
+- Offset: `0xb90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_sample
+Auto-extracted signal sample from sample_mux.vhd
+- Offset: `0xb94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_prev_sample_d
+Auto-extracted signal prev_sample_d from sample_mux.vhd
+- Offset: `0xb98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_prev_sample_q
+Auto-extracted signal prev_sample_q from sample_mux.vhd
+- Offset: `0xb9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_req_input
+Auto-extracted signal req_input from segment_end_detector.vhd
+- Offset: `0xba0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_d
+Auto-extracted signal segm_end_req_capt_d from segment_end_detector.vhd
+- Offset: `0xba4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_q
+Auto-extracted signal segm_end_req_capt_q from segment_end_detector.vhd
+- Offset: `0xba8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_ce
+Auto-extracted signal segm_end_req_capt_ce from segment_end_detector.vhd
+- Offset: `0xbac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_clr
+Auto-extracted signal segm_end_req_capt_clr from segment_end_detector.vhd
+- Offset: `0xbb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_dq
+Auto-extracted signal segm_end_req_capt_dq from segment_end_detector.vhd
+- Offset: `0xbb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_nbt_valid
+Auto-extracted signal segm_end_nbt_valid from segment_end_detector.vhd
+- Offset: `0xbb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_dbt_valid
+Auto-extracted signal segm_end_dbt_valid from segment_end_detector.vhd
+- Offset: `0xbbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_nbt_dbt_valid
+Auto-extracted signal segm_end_nbt_dbt_valid from segment_end_detector.vhd
+- Offset: `0xbc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_tseg1_end_req_valid
+Auto-extracted signal tseg1_end_req_valid from segment_end_detector.vhd
+- Offset: `0xbc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_tseg2_end_req_valid
+Auto-extracted signal tseg2_end_req_valid from segment_end_detector.vhd
+- Offset: `0xbc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_h_sync_valid_i
+Auto-extracted signal h_sync_valid_i from segment_end_detector.vhd
+- Offset: `0xbcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segment_end_i
+Auto-extracted signal segment_end_i from segment_end_detector.vhd
+- Offset: `0xbd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_nbt_tq_active
+Auto-extracted signal nbt_tq_active from segment_end_detector.vhd
+- Offset: `0xbd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_dbt_tq_active
+Auto-extracted signal dbt_tq_active from segment_end_detector.vhd
+- Offset: `0xbd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_bt_ctr_clear_i
+Auto-extracted signal bt_ctr_clear_i from segment_end_detector.vhd
+- Offset: `0xbdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_shift_regs
+Auto-extracted signal shift_regs from shift_reg.vhd
+- Offset: `0xbe0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_next_shift_reg_val
+Auto-extracted signal next_shift_reg_val from shift_reg.vhd
+- Offset: `0xbe4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_byte_shift_reg_in
+Auto-extracted signal shift_reg_in from shift_reg_byte.vhd
+- Offset: `0xbe8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_preload_shift_regs
+Auto-extracted signal shift_regs from shift_reg_preload.vhd
+- Offset: `0xbec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_preload_next_shift_reg_val
+Auto-extracted signal next_shift_reg_val from shift_reg_preload.vhd
+- Offset: `0xbf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sig_sync_rff
+Auto-extracted signal rff from sig_sync.vhd
+- Offset: `0xbf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_d
+Auto-extracted signal btmc_d from ssp_generator.vhd
+- Offset: `0xbf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_q
+Auto-extracted signal btmc_q from ssp_generator.vhd
+- Offset: `0xbfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_add
+Auto-extracted signal btmc_add from ssp_generator.vhd
+- Offset: `0xc00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_ce
+Auto-extracted signal btmc_ce from ssp_generator.vhd
+- Offset: `0xc04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_meas_running_d
+Auto-extracted signal btmc_meas_running_d from ssp_generator.vhd
+- Offset: `0xc08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_meas_running_q
+Auto-extracted signal btmc_meas_running_q from ssp_generator.vhd
+- Offset: `0xc0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_d
+Auto-extracted signal sspc_d from ssp_generator.vhd
+- Offset: `0xc10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_q
+Auto-extracted signal sspc_q from ssp_generator.vhd
+- Offset: `0xc14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ce
+Auto-extracted signal sspc_ce from ssp_generator.vhd
+- Offset: `0xc18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_expired
+Auto-extracted signal sspc_expired from ssp_generator.vhd
+- Offset: `0xc1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_threshold
+Auto-extracted signal sspc_threshold from ssp_generator.vhd
+- Offset: `0xc20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_add
+Auto-extracted signal sspc_add from ssp_generator.vhd
+- Offset: `0xc24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_first_ssp_d
+Auto-extracted signal first_ssp_d from ssp_generator.vhd
+- Offset: `0xc28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_first_ssp_q
+Auto-extracted signal first_ssp_q from ssp_generator.vhd
+- Offset: `0xc2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ena_d
+Auto-extracted signal sspc_ena_d from ssp_generator.vhd
+- Offset: `0xc30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ena_q
+Auto-extracted signal sspc_ena_q from ssp_generator.vhd
+- Offset: `0xc34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_ssp_delay_padded
+Auto-extracted signal ssp_delay_padded from ssp_generator.vhd
+- Offset: `0xc38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_resync_edge
+Auto-extracted signal resync_edge from synchronisation_checker.vhd
+- Offset: `0xc3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_h_sync_edge
+Auto-extracted signal h_sync_edge from synchronisation_checker.vhd
+- Offset: `0xc40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_h_or_re_sync_edge
+Auto-extracted signal h_or_re_sync_edge from synchronisation_checker.vhd
+- Offset: `0xc44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag
+Auto-extracted signal sync_flag from synchronisation_checker.vhd
+- Offset: `0xc48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag_ce
+Auto-extracted signal sync_flag_ce from synchronisation_checker.vhd
+- Offset: `0xc4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag_nxt
+Auto-extracted signal sync_flag_nxt from synchronisation_checker.vhd
+- Offset: `0xc50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_reg_sel
+Auto-extracted signal reg_sel from test_registers_reg_map.vhd
+- Offset: `0xc54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_data_mux_in
+Auto-extracted signal read_data_mux_in from test_registers_reg_map.vhd
+- Offset: `0xc58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_data_mask_n
+Auto-extracted signal read_data_mask_n from test_registers_reg_map.vhd
+- Offset: `0xc5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_mux_ena
+Auto-extracted signal read_mux_ena from test_registers_reg_map.vhd
+- Offset: `0xc60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_rx_trig_req_q
+Auto-extracted signal rx_trig_req_q from trigger_generator.vhd
+- Offset: `0xc64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_d
+Auto-extracted signal tx_trig_req_flag_d from trigger_generator.vhd
+- Offset: `0xc68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_q
+Auto-extracted signal tx_trig_req_flag_q from trigger_generator.vhd
+- Offset: `0xc6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_dq
+Auto-extracted signal tx_trig_req_flag_dq from trigger_generator.vhd
+- Offset: `0xc70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_mux_tx_trigger_q
+Auto-extracted signal tx_trigger_q from trigger_mux.vhd
+- Offset: `0xc74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_d
+Auto-extracted signal trv_meas_progress_d from trv_delay_meas.vhd
+- Offset: `0xc78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_q
+Auto-extracted signal trv_meas_progress_q from trv_delay_meas.vhd
+- Offset: `0xc7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_del
+Auto-extracted signal trv_meas_progress_del from trv_delay_meas.vhd
+- Offset: `0xc80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_q
+Auto-extracted signal trv_delay_ctr_q from trv_delay_meas.vhd
+- Offset: `0xc84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_d
+Auto-extracted signal trv_delay_ctr_d from trv_delay_meas.vhd
+- Offset: `0xc88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_add
+Auto-extracted signal trv_delay_ctr_add from trv_delay_meas.vhd
+- Offset: `0xc8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_q_padded
+Auto-extracted signal trv_delay_ctr_q_padded from trv_delay_meas.vhd
+- Offset: `0xc90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_d
+Auto-extracted signal trv_delay_ctr_rst_d from trv_delay_meas.vhd
+- Offset: `0xc94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_q
+Auto-extracted signal trv_delay_ctr_rst_q from trv_delay_meas.vhd
+- Offset: `0xc98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_q_scan
+Auto-extracted signal trv_delay_ctr_rst_q_scan from trv_delay_meas.vhd
+- Offset: `0xc9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_shadow_ce
+Auto-extracted signal ssp_shadow_ce from trv_delay_meas.vhd
+- Offset: `0xca0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_delay_raw
+Auto-extracted signal ssp_delay_raw from trv_delay_meas.vhd
+- Offset: `0xca4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_delay_saturated
+Auto-extracted signal ssp_delay_saturated from trv_delay_meas.vhd
+- Offset: `0xca8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_sum
+Auto-extracted signal trv_delay_sum from trv_delay_meas.vhd
+- Offset: `0xcac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_select_buf_avail
+Auto-extracted signal select_buf_avail from tx_arbitrator.vhd
+- Offset: `0xcb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_selected_input
+Auto-extracted signal txtb_selected_input from tx_arbitrator.vhd
+- Offset: `0xcb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_timestamp
+Auto-extracted signal txtb_timestamp from tx_arbitrator.vhd
+- Offset: `0xcb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_timestamp_valid
+Auto-extracted signal timestamp_valid from tx_arbitrator.vhd
+- Offset: `0xcbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_select_index_changed
+Auto-extracted signal select_index_changed from tx_arbitrator.vhd
+- Offset: `0xcc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_validated_buffer
+Auto-extracted signal validated_buffer from tx_arbitrator.vhd
+- Offset: `0xcc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_ts_low_internal
+Auto-extracted signal ts_low_internal from tx_arbitrator.vhd
+- Offset: `0xcc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_dlc_dbl_buf
+Auto-extracted signal tran_dlc_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xccc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_is_rtr_dbl_buf
+Auto-extracted signal tran_is_rtr_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_ident_type_dbl_buf
+Auto-extracted signal tran_ident_type_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_type_dbl_buf
+Auto-extracted signal tran_frame_type_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_brs_dbl_buf
+Auto-extracted signal tran_brs_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_dlc_com
+Auto-extracted signal tran_dlc_com from tx_arbitrator.vhd
+- Offset: `0xce0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_is_rtr_com
+Auto-extracted signal tran_is_rtr_com from tx_arbitrator.vhd
+- Offset: `0xce4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_ident_type_com
+Auto-extracted signal tran_ident_type_com from tx_arbitrator.vhd
+- Offset: `0xce8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_type_com
+Auto-extracted signal tran_frame_type_com from tx_arbitrator.vhd
+- Offset: `0xcec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_brs_com
+Auto-extracted signal tran_brs_com from tx_arbitrator.vhd
+- Offset: `0xcf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_valid_com
+Auto-extracted signal tran_frame_valid_com from tx_arbitrator.vhd
+- Offset: `0xcf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_identifier_com
+Auto-extracted signal tran_identifier_com from tx_arbitrator.vhd
+- Offset: `0xcf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ts_lw_addr
+Auto-extracted signal load_ts_lw_addr from tx_arbitrator.vhd
+- Offset: `0xcfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ts_uw_addr
+Auto-extracted signal load_ts_uw_addr from tx_arbitrator.vhd
+- Offset: `0xd00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ffmt_w_addr
+Auto-extracted signal load_ffmt_w_addr from tx_arbitrator.vhd
+- Offset: `0xd04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ident_w_addr
+Auto-extracted signal load_ident_w_addr from tx_arbitrator.vhd
+- Offset: `0xd08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_ts_l_w
+Auto-extracted signal store_ts_l_w from tx_arbitrator.vhd
+- Offset: `0xd0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_md_w
+Auto-extracted signal store_md_w from tx_arbitrator.vhd
+- Offset: `0xd10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_ident_w
+Auto-extracted signal store_ident_w from tx_arbitrator.vhd
+- Offset: `0xd14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_buffer_md_w
+Auto-extracted signal buffer_md_w from tx_arbitrator.vhd
+- Offset: `0xd18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_last_txtb_index
+Auto-extracted signal store_last_txtb_index from tx_arbitrator.vhd
+- Offset: `0xd1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_frame_valid_com_set
+Auto-extracted signal frame_valid_com_set from tx_arbitrator.vhd
+- Offset: `0xd20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_frame_valid_com_clear
+Auto-extracted signal frame_valid_com_clear from tx_arbitrator.vhd
+- Offset: `0xd24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tx_arb_locked
+Auto-extracted signal tx_arb_locked from tx_arbitrator.vhd
+- Offset: `0xd28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_meta_clk_en
+Auto-extracted signal txtb_meta_clk_en from tx_arbitrator.vhd
+- Offset: `0xd2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_drv_tttm_ena
+Auto-extracted signal drv_tttm_ena from tx_arbitrator.vhd
+- Offset: `0xd30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_tx_arb_fsm_ce
+Auto-extracted signal tx_arb_fsm_ce from tx_arbitrator_fsm.vhd
+- Offset: `0xd34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_fsm_wait_state_d
+Auto-extracted signal fsm_wait_state_d from tx_arbitrator_fsm.vhd
+- Offset: `0xd38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_fsm_wait_state_q
+Auto-extracted signal fsm_wait_state_q from tx_arbitrator_fsm.vhd
+- Offset: `0xd3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_data_cache_tx_cache_mem
+Auto-extracted signal tx_cache_mem from tx_data_cache.vhd
+- Offset: `0xd40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_output
+Auto-extracted signal tx_sr_output from tx_shift_reg.vhd
+- Offset: `0xd44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_ce
+Auto-extracted signal tx_sr_ce from tx_shift_reg.vhd
+- Offset: `0xd48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_pload
+Auto-extracted signal tx_sr_pload from tx_shift_reg.vhd
+- Offset: `0xd4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_pload_val
+Auto-extracted signal tx_sr_pload_val from tx_shift_reg.vhd
+- Offset: `0xd50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_base_id
+Auto-extracted signal tx_base_id from tx_shift_reg.vhd
+- Offset: `0xd54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_ext_id
+Auto-extracted signal tx_ext_id from tx_shift_reg.vhd
+- Offset: `0xd58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_crc
+Auto-extracted signal tx_crc from tx_shift_reg.vhd
+- Offset: `0xd5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_bst_ctr_grey
+Auto-extracted signal bst_ctr_grey from tx_shift_reg.vhd
+- Offset: `0xd60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_bst_parity
+Auto-extracted signal bst_parity from tx_shift_reg.vhd
+- Offset: `0xd64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_stuff_count
+Auto-extracted signal stuff_count from tx_shift_reg.vhd
+- Offset: `0xd68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_user_accessible
+Auto-extracted signal txtb_user_accessible from txt_buffer.vhd
+- Offset: `0xd6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_hw_cbs
+Auto-extracted signal hw_cbs from txt_buffer.vhd
+- Offset: `0xd70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_sw_cbs
+Auto-extracted signal sw_cbs from txt_buffer.vhd
+- Offset: `0xd74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_unmask_data_ram
+Auto-extracted signal txtb_unmask_data_ram from txt_buffer.vhd
+- Offset: `0xd78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_port_b_data_i
+Auto-extracted signal txtb_port_b_data_i from txt_buffer.vhd
+- Offset: `0xd7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_write
+Auto-extracted signal ram_write from txt_buffer.vhd
+- Offset: `0xd80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_read_address
+Auto-extracted signal ram_read_address from txt_buffer.vhd
+- Offset: `0xd84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_ram_clk_en
+Auto-extracted signal txtb_ram_clk_en from txt_buffer.vhd
+- Offset: `0xd88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_clk_ram
+Auto-extracted signal clk_ram from txt_buffer.vhd
+- Offset: `0xd8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_abort_applied
+Auto-extracted signal abort_applied from txt_buffer_fsm.vhd
+- Offset: `0xd90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_txt_fsm_ce
+Auto-extracted signal txt_fsm_ce from txt_buffer_fsm.vhd
+- Offset: `0xd94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_go_to_failed
+Auto-extracted signal go_to_failed from txt_buffer_fsm.vhd
+- Offset: `0xd98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_transient_state
+Auto-extracted signal transient_state from txt_buffer_fsm.vhd
+- Offset: `0xd9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_address_i
+Auto-extracted signal port_a_address_i from txt_buffer_ram.vhd
+- Offset: `0xda0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_write_i
+Auto-extracted signal port_a_write_i from txt_buffer_ram.vhd
+- Offset: `0xda4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_data_in_i
+Auto-extracted signal port_a_data_in_i from txt_buffer_ram.vhd
+- Offset: `0xda8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_b_address_i
+Auto-extracted signal port_b_address_i from txt_buffer_ram.vhd
+- Offset: `0xdac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_b_data_out_i
+Auto-extracted signal port_b_data_out_i from txt_buffer_ram.vhd
+- Offset: `0xdb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_tst_ena
+Auto-extracted signal tst_ena from txt_buffer_ram.vhd
+- Offset: `0xdb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_tst_addr
+Auto-extracted signal tst_addr from txt_buffer_ram.vhd
+- Offset: `0xdb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_be_active
+Auto-extracted signal be_active from access_signaler.vhd
+- Offset: `0xdbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_in
+Auto-extracted signal access_in from access_signaler.vhd
+- Offset: `0xdc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_active
+Auto-extracted signal access_active from access_signaler.vhd
+- Offset: `0xdc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_active_reg
+Auto-extracted signal access_active_reg from access_signaler.vhd
+- Offset: `0xdc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## address_decoder_addr_dec_i
+Auto-extracted signal addr_dec_i from address_decoder.vhd
+- Offset: `0xdcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## address_decoder_addr_dec_enabled_i
+Auto-extracted signal addr_dec_enabled_i from address_decoder.vhd
+- Offset: `0xdd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+
+
+## carfield_regs / doc / carfield_regs.md
+
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                            |
+|:-----------------------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| carfield.[`VERSION0`](#version0)                                             | 0x0      |        4 | Cheshire sha256 commit                                                 |
+| carfield.[`VERSION1`](#version1)                                             | 0x4      |        4 | Safety Island sha256 commit                                            |
+| carfield.[`VERSION2`](#version2)                                             | 0x8      |        4 | Security Island sha256 commit                                          |
+| carfield.[`VERSION3`](#version3)                                             | 0xc      |        4 | PULP Cluster sha256 commit                                             |
+| carfield.[`VERSION4`](#version4)                                             | 0x10     |        4 | Spatz CLuster sha256 commit                                            |
+| carfield.[`JEDEC_IDCODE`](#jedec_idcode)                                     | 0x14     |        4 | JEDEC ID CODE -TODO assign-                                            |
+| carfield.[`GENERIC_SCRATCH0`](#generic_scratch0)                             | 0x18     |        4 | Scratch                                                                |
+| carfield.[`GENERIC_SCRATCH1`](#generic_scratch1)                             | 0x1c     |        4 | Scratch                                                                |
+| carfield.[`HOST_RST`](#host_rst)                                             | 0x20     |        4 | Host Domain reset -active high, inverted in HW-                        |
+| carfield.[`PERIPH_RST`](#periph_rst)                                         | 0x24     |        4 | Periph Domain reset -active high, inverted in HW-                      |
+| carfield.[`SAFETY_ISLAND_RST`](#safety_island_rst)                           | 0x28     |        4 | Safety Island reset -active high, inverted in HW-                      |
+| carfield.[`SECURITY_ISLAND_RST`](#security_island_rst)                       | 0x2c     |        4 | Security Island reset -active high, inverted in HW-                    |
+| carfield.[`PULP_CLUSTER_RST`](#pulp_cluster_rst)                             | 0x30     |        4 | PULP Cluster reset -active high, inverted in HW-                       |
+| carfield.[`SPATZ_CLUSTER_RST`](#spatz_cluster_rst)                           | 0x34     |        4 | Spatz Cluster reset -active high, inverted in HW-                      |
+| carfield.[`L2_RST`](#l2_rst)                                                 | 0x38     |        4 | L2 reset -active high, inverted in HW-                                 |
+| carfield.[`PERIPH_ISOLATE`](#periph_isolate)                                 | 0x3c     |        4 | Periph Domain  AXI isolate                                             |
+| carfield.[`SAFETY_ISLAND_ISOLATE`](#safety_island_isolate)                   | 0x40     |        4 | Safety Island AXI isolate                                              |
+| carfield.[`SECURITY_ISLAND_ISOLATE`](#security_island_isolate)               | 0x44     |        4 | Security Island AXI isolate                                            |
+| carfield.[`PULP_CLUSTER_ISOLATE`](#pulp_cluster_isolate)                     | 0x48     |        4 | PULP Cluster AXI isolate                                               |
+| carfield.[`SPATZ_CLUSTER_ISOLATE`](#spatz_cluster_isolate)                   | 0x4c     |        4 | Spatz Cluster AXI isolate                                              |
+| carfield.[`L2_ISOLATE`](#l2_isolate)                                         | 0x50     |        4 | L2 AXI isolate                                                         |
+| carfield.[`PERIPH_ISOLATE_STATUS`](#periph_isolate_status)                   | 0x54     |        4 | Periph Domain AXI isolate status                                       |
+| carfield.[`SAFETY_ISLAND_ISOLATE_STATUS`](#safety_island_isolate_status)     | 0x58     |        4 | Safety Island AXI isolate status                                       |
+| carfield.[`SECURITY_ISLAND_ISOLATE_STATUS`](#security_island_isolate_status) | 0x5c     |        4 | Security Island AXI isolate status                                     |
+| carfield.[`PULP_CLUSTER_ISOLATE_STATUS`](#pulp_cluster_isolate_status)       | 0x60     |        4 | PULP Cluster AXI isolate status                                        |
+| carfield.[`SPATZ_CLUSTER_ISOLATE_STATUS`](#spatz_cluster_isolate_status)     | 0x64     |        4 | Spatz Cluster AXI isolate status                                       |
+| carfield.[`L2_ISOLATE_STATUS`](#l2_isolate_status)                           | 0x68     |        4 | L2 AXI isolate status                                                  |
+| carfield.[`PERIPH_CLK_EN`](#periph_clk_en)                                   | 0x6c     |        4 | Periph Domain clk gate enable                                          |
+| carfield.[`SAFETY_ISLAND_CLK_EN`](#safety_island_clk_en)                     | 0x70     |        4 | Safety Island clk gate enable                                          |
+| carfield.[`SECURITY_ISLAND_CLK_EN`](#security_island_clk_en)                 | 0x74     |        4 | Security Island clk gate enable                                        |
+| carfield.[`PULP_CLUSTER_CLK_EN`](#pulp_cluster_clk_en)                       | 0x78     |        4 | PULP Cluster clk gate enable                                           |
+| carfield.[`SPATZ_CLUSTER_CLK_EN`](#spatz_cluster_clk_en)                     | 0x7c     |        4 | Spatz Cluster clk gate enable                                          |
+| carfield.[`L2_CLK_EN`](#l2_clk_en)                                           | 0x80     |        4 | Shared L2 memory clk gate enable                                       |
+| carfield.[`PERIPH_CLK_SEL`](#periph_clk_sel)                                 | 0x84     |        4 | Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SAFETY_ISLAND_CLK_SEL`](#safety_island_clk_sel)                   | 0x88     |        4 | Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SECURITY_ISLAND_CLK_SEL`](#security_island_clk_sel)               | 0x8c     |        4 | Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) |
+| carfield.[`PULP_CLUSTER_CLK_SEL`](#pulp_cluster_clk_sel)                     | 0x90     |        4 | PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)    |
+| carfield.[`SPATZ_CLUSTER_CLK_SEL`](#spatz_cluster_clk_sel)                   | 0x94     |        4 | Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`L2_CLK_SEL`](#l2_clk_sel)                                         | 0x98     |        4 | L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)       |
+| carfield.[`PERIPH_CLK_DIV_VALUE`](#periph_clk_div_value)                     | 0x9c     |        4 | Periph Domain clk divider value                                        |
+| carfield.[`SAFETY_ISLAND_CLK_DIV_VALUE`](#safety_island_clk_div_value)       | 0xa0     |        4 | Safety Island clk divider value                                        |
+| carfield.[`SECURITY_ISLAND_CLK_DIV_VALUE`](#security_island_clk_div_value)   | 0xa4     |        4 | Security Island clk divider value                                      |
+| carfield.[`PULP_CLUSTER_CLK_DIV_VALUE`](#pulp_cluster_clk_div_value)         | 0xa8     |        4 | PULP Cluster clk divider value                                         |
+| carfield.[`SPATZ_CLUSTER_CLK_DIV_VALUE`](#spatz_cluster_clk_div_value)       | 0xac     |        4 | Spatz Cluster clk divider value                                        |
+| carfield.[`L2_CLK_DIV_VALUE`](#l2_clk_div_value)                             | 0xb0     |        4 | L2 Memory clk divider value                                            |
+| carfield.[`HOST_FETCH_ENABLE`](#host_fetch_enable)                           | 0xb4     |        4 | Host Domain fetch enable                                               |
+| carfield.[`SAFETY_ISLAND_FETCH_ENABLE`](#safety_island_fetch_enable)         | 0xb8     |        4 | Safety Island fetch enable                                             |
+| carfield.[`SECURITY_ISLAND_FETCH_ENABLE`](#security_island_fetch_enable)     | 0xbc     |        4 | Security Island fetch enable                                           |
+| carfield.[`PULP_CLUSTER_FETCH_ENABLE`](#pulp_cluster_fetch_enable)           | 0xc0     |        4 | PULP Cluster fetch enable                                              |
+| carfield.[`SPATZ_CLUSTER_DEBUG_REQ`](#spatz_cluster_debug_req)               | 0xc4     |        4 | Spatz Cluster debug req                                                |
+| carfield.[`HOST_BOOT_ADDR`](#host_boot_addr)                                 | 0xc8     |        4 | Host boot address                                                      |
+| carfield.[`SAFETY_ISLAND_BOOT_ADDR`](#safety_island_boot_addr)               | 0xcc     |        4 | Safety Island boot address                                             |
+| carfield.[`SECURITY_ISLAND_BOOT_ADDR`](#security_island_boot_addr)           | 0xd0     |        4 | Security Island boot address                                           |
+| carfield.[`PULP_CLUSTER_BOOT_ADDR`](#pulp_cluster_boot_addr)                 | 0xd4     |        4 | PULP Cluster boot address                                              |
+| carfield.[`SPATZ_CLUSTER_BOOT_ADDR`](#spatz_cluster_boot_addr)               | 0xd8     |        4 | Spatz Cluster boot address                                             |
+| carfield.[`PULP_CLUSTER_BOOT_ENABLE`](#pulp_cluster_boot_enable)             | 0xdc     |        4 | PULP Cluster boot enable                                               |
+| carfield.[`SPATZ_CLUSTER_BUSY`](#spatz_cluster_busy)                         | 0xe0     |        4 | Spatz Cluster busy                                                     |
+| carfield.[`PULP_CLUSTER_BUSY`](#pulp_cluster_busy)                           | 0xe4     |        4 | PULP Cluster busy                                                      |
+| carfield.[`PULP_CLUSTER_EOC`](#pulp_cluster_eoc)                             | 0xe8     |        4 | PULP Cluster end of computation                                        |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_EN`](#eth_rgmii_phy_clk_div_en)             | 0xec     |        4 | Ethernet RGMII PHY clock divider enable bit                            |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_VALUE`](#eth_rgmii_phy_clk_div_value)       | 0xf0     |        4 | Ethernet RGMII PHY clock divider value                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_EN`](#eth_mdio_clk_div_en)                       | 0xf4     |        4 | Ethernet MDIO clock divider enable bit                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_VALUE`](#eth_mdio_clk_div_value)                 | 0xf8     |        4 | Ethernet MDIO clock divider value                                      |
+
+## VERSION0
+Cheshire sha256 commit
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION0", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION0 |               |
+
+## VERSION1
+Safety Island sha256 commit
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION1", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION1 |               |
+
+## VERSION2
+Security Island sha256 commit
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION2", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION2 |               |
+
+## VERSION3
+PULP Cluster sha256 commit
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION3", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION3 |               |
+
+## VERSION4
+Spatz CLuster sha256 commit
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION4", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION4 |               |
+
+## JEDEC_IDCODE
+JEDEC ID CODE -TODO assign-
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "JEDEC_IDCODE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description   |
+|:------:|:------:|:-------:|:-------------|:--------------|
+|  31:0  |   rw   |   0x0   | JEDEC_IDCODE |               |
+
+## GENERIC_SCRATCH0
+Scratch
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH0 |               |
+
+## GENERIC_SCRATCH1
+Scratch
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH1 |               |
+
+## HOST_RST
+Host Domain reset -active high, inverted in HW-
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_RST", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:1  |        |         |          | Reserved      |
+|   0    |   ro   |   0x0   | HOST_RST |               |
+
+## PERIPH_RST
+Periph Domain reset -active high, inverted in HW-
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_RST |               |
+
+## SAFETY_ISLAND_RST
+Safety Island reset -active high, inverted in HW-
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_RST |               |
+
+## SECURITY_ISLAND_RST
+Security Island reset -active high, inverted in HW-
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_RST |               |
+
+## PULP_CLUSTER_RST
+PULP Cluster reset -active high, inverted in HW-
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_RST |               |
+
+## SPATZ_CLUSTER_RST
+Spatz Cluster reset -active high, inverted in HW-
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_RST |               |
+
+## L2_RST
+L2 reset -active high, inverted in HW-
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:1  |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | L2_RST |               |
+
+## PERIPH_ISOLATE
+Periph Domain  AXI isolate
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:1  |        |         |                | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE |               |
+
+## SAFETY_ISLAND_ISOLATE
+Safety Island AXI isolate
+- Offset: `0x40`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SAFETY_ISLAND_ISOLATE |               |
+
+## SECURITY_ISLAND_ISOLATE
+Security Island AXI isolate
+- Offset: `0x44`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   rw   |   0x1   | SECURITY_ISLAND_ISOLATE |               |
+
+## PULP_CLUSTER_ISOLATE
+PULP Cluster AXI isolate
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x1   | PULP_CLUSTER_ISOLATE |               |
+
+## SPATZ_CLUSTER_ISOLATE
+Spatz Cluster AXI isolate
+- Offset: `0x4c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SPATZ_CLUSTER_ISOLATE |               |
+
+## L2_ISOLATE
+L2 AXI isolate
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE |               |
+
+## PERIPH_ISOLATE_STATUS
+Periph Domain AXI isolate status
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE_STATUS |               |
+
+## SAFETY_ISLAND_ISOLATE_STATUS
+Safety Island AXI isolate status
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_ISOLATE_STATUS |               |
+
+## SECURITY_ISLAND_ISOLATE_STATUS
+Security Island AXI isolate status
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                           | Description   |
+|:------:|:------:|:-------:|:-------------------------------|:--------------|
+|  31:1  |        |         |                                | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_ISOLATE_STATUS |               |
+
+## PULP_CLUSTER_ISOLATE_STATUS
+PULP Cluster AXI isolate status
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+|  31:1  |        |         |                             | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_ISOLATE_STATUS |               |
+
+## SPATZ_CLUSTER_ISOLATE_STATUS
+Spatz Cluster AXI isolate status
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_ISOLATE_STATUS |               |
+
+## L2_ISOLATE_STATUS
+L2 AXI isolate status
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE_STATUS |               |
+
+## PERIPH_CLK_EN
+Periph Domain clk gate enable
+- Offset: `0x6c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x1   | PERIPH_CLK_EN |               |
+
+## SAFETY_ISLAND_CLK_EN
+Safety Island clk gate enable
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_CLK_EN |               |
+
+## SECURITY_ISLAND_CLK_EN
+Security Island clk gate enable
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+|  31:1  |        |         |                        | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_CLK_EN |               |
+
+## PULP_CLUSTER_CLK_EN
+PULP Cluster clk gate enable
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_CLK_EN |               |
+
+## SPATZ_CLUSTER_CLK_EN
+Spatz Cluster clk gate enable
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_CLK_EN |               |
+
+## L2_CLK_EN
+Shared L2 memory clk gate enable
+- Offset: `0x80`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:1  |        |         |           | Reserved      |
+|   0    |   rw   |   0x1   | L2_CLK_EN |               |
+
+## PERIPH_CLK_SEL
+Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x84`
+- Reset default: `0x2`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:2  |        |         |                | Reserved      |
+|  1:0   |   rw   |   0x2   | PERIPH_CLK_SEL |               |
+
+## SAFETY_ISLAND_CLK_SEL
+Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x88`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SAFETY_ISLAND_CLK_SEL |               |
+
+## SECURITY_ISLAND_CLK_SEL
+Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x8c`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x1   | SECURITY_ISLAND_CLK_SEL |               |
+
+## PULP_CLUSTER_CLK_SEL
+PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x90`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:2  |        |         |                      | Reserved      |
+|  1:0   |   rw   |   0x1   | PULP_CLUSTER_CLK_SEL |               |
+
+## SPATZ_CLUSTER_CLK_SEL
+Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x94`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SPATZ_CLUSTER_CLK_SEL |               |
+
+## L2_CLK_SEL
+L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x98`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:2  |        |         |            | Reserved      |
+|  1:0   |   rw   |   0x1   | L2_CLK_SEL |               |
+
+## PERIPH_CLK_DIV_VALUE
+Periph Domain clk divider value
+- Offset: `0x9c`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+| 31:24  |        |         |                      | Reserved      |
+|  23:0  |   rw   |   0x1   | PERIPH_CLK_DIV_VALUE |               |
+
+## SAFETY_ISLAND_CLK_DIV_VALUE
+Safety Island clk divider value
+- Offset: `0xa0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SAFETY_ISLAND_CLK_DIV_VALUE |               |
+
+## SECURITY_ISLAND_CLK_DIV_VALUE
+Security Island clk divider value
+- Offset: `0xa4`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          | Description   |
+|:------:|:------:|:-------:|:------------------------------|:--------------|
+| 31:24  |        |         |                               | Reserved      |
+|  23:0  |   rw   |   0x1   | SECURITY_ISLAND_CLK_DIV_VALUE |               |
+
+## PULP_CLUSTER_CLK_DIV_VALUE
+PULP Cluster clk divider value
+- Offset: `0xa8`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+| 31:24  |        |         |                            | Reserved      |
+|  23:0  |   rw   |   0x1   | PULP_CLUSTER_CLK_DIV_VALUE |               |
+
+## SPATZ_CLUSTER_CLK_DIV_VALUE
+Spatz Cluster clk divider value
+- Offset: `0xac`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SPATZ_CLUSTER_CLK_DIV_VALUE |               |
+
+## L2_CLK_DIV_VALUE
+L2 Memory clk divider value
+- Offset: `0xb0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:24  |        |         |                  | Reserved      |
+|  23:0  |   rw   |   0x1   | L2_CLK_DIV_VALUE |               |
+
+## HOST_FETCH_ENABLE
+Host Domain fetch enable
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_FETCH_ENABLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | HOST_FETCH_ENABLE |               |
+
+## SAFETY_ISLAND_FETCH_ENABLE
+Safety Island fetch enable
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+|  31:1  |        |         |                            | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_FETCH_ENABLE |               |
+
+## SECURITY_ISLAND_FETCH_ENABLE
+Security Island fetch enable
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_FETCH_ENABLE |               |
+
+## PULP_CLUSTER_FETCH_ENABLE
+PULP Cluster fetch enable
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|  31:1  |        |         |                           | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_FETCH_ENABLE |               |
+
+## SPATZ_CLUSTER_DEBUG_REQ
+Spatz Cluster debug req
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_DEBUG_REQ", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x0   | SPATZ_CLUSTER_DEBUG_REQ |               |
+
+## HOST_BOOT_ADDR
+Host boot address
+- Offset: `0xc8`
+- Reset default: `0x1000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:0  |   rw   | 0x1000  | HOST_BOOT_ADDR |               |
+
+## SAFETY_ISLAND_BOOT_ADDR
+Safety Island boot address
+- Offset: `0xcc`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SAFETY_ISLAND_BOOT_ADDR |               |
+
+## SECURITY_ISLAND_BOOT_ADDR
+Security Island boot address
+- Offset: `0xd0`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                      | Description   |
+|:------:|:------:|:----------:|:--------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SECURITY_ISLAND_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ADDR
+PULP Cluster boot address
+- Offset: `0xd4`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                   | Description   |
+|:------:|:------:|:----------:|:-----------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | PULP_CLUSTER_BOOT_ADDR |               |
+
+## SPATZ_CLUSTER_BOOT_ADDR
+Spatz Cluster boot address
+- Offset: `0xd8`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SPATZ_CLUSTER_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ENABLE
+PULP Cluster boot enable
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_BOOT_ENABLE |               |
+
+## SPATZ_CLUSTER_BUSY
+Spatz Cluster busy
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:1  |        |         |                    | Reserved      |
+|   0    |   ro   |   0x0   | SPATZ_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_BUSY
+PULP Cluster busy
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_EOC
+PULP Cluster end of computation
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_EOC", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_EOC |               |
+
+## ETH_RGMII_PHY_CLK_DIV_EN
+Ethernet RGMII PHY clock divider enable bit
+- Offset: `0xec`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x1   | ETH_RGMII_PHY_CLK_DIV_EN |               |
+
+## ETH_RGMII_PHY_CLK_DIV_VALUE
+Ethernet RGMII PHY clock divider value
+- Offset: `0xf0`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:20  |        |         |                             | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_RGMII_PHY_CLK_DIV_VALUE |               |
+
+## ETH_MDIO_CLK_DIV_EN
+Ethernet MDIO clock divider enable bit
+- Offset: `0xf4`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x1   | ETH_MDIO_CLK_DIV_EN |               |
+
+## ETH_MDIO_CLK_DIV_VALUE
+Ethernet MDIO clock divider value
+- Offset: `0xf8`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:20  |        |         |                        | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_MDIO_CLK_DIV_VALUE |               |
+
+
+
+## cheshire / doc / registers.md
+
+## Summary
+
+| Name                                       | Offset   |   Length | Description                                        |
+|:-------------------------------------------|:---------|---------:|:---------------------------------------------------|
+| cheshire.[`scratch_0`](#scratch)           | 0x0      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_1`](#scratch)           | 0x4      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_2`](#scratch)           | 0x8      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_3`](#scratch)           | 0xc      |        4 | Registers for use by software                      |
+| cheshire.[`scratch_4`](#scratch)           | 0x10     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_5`](#scratch)           | 0x14     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_6`](#scratch)           | 0x18     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_7`](#scratch)           | 0x1c     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_8`](#scratch)           | 0x20     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_9`](#scratch)           | 0x24     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_10`](#scratch)          | 0x28     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_11`](#scratch)          | 0x2c     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_12`](#scratch)          | 0x30     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_13`](#scratch)          | 0x34     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_14`](#scratch)          | 0x38     |        4 | Registers for use by software                      |
+| cheshire.[`scratch_15`](#scratch)          | 0x3c     |        4 | Registers for use by software                      |
+| cheshire.[`boot_mode`](#boot_mode)         | 0x40     |        4 | Method to load boot code (connected to input pins) |
+| cheshire.[`rtc_freq`](#rtc_freq)           | 0x44     |        4 | Frequency (Hz) configured for RTC                  |
+| cheshire.[`platform_rom`](#platform_rom)   | 0x48     |        4 | Address of platform ROM                            |
+| cheshire.[`num_int_harts`](#num_int_harts) | 0x4c     |        4 | Number of internal harts                           |
+| cheshire.[`hw_features`](#hw_features)     | 0x50     |        4 | Specifies which hardware features are available    |
+| cheshire.[`llc_size`](#llc_size)           | 0x54     |        4 | Total size of LLC in bytes                         |
+| cheshire.[`vga_params`](#vga_params)       | 0x58     |        4 | VGA hardware parameters                            |
+
+## scratch
+Registers for use by software
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name       | Offset   |
+|:-----------|:---------|
+| scratch_0  | 0x0      |
+| scratch_1  | 0x4      |
+| scratch_2  | 0x8      |
+| scratch_3  | 0xc      |
+| scratch_4  | 0x10     |
+| scratch_5  | 0x14     |
+| scratch_6  | 0x18     |
+| scratch_7  | 0x1c     |
+| scratch_8  | 0x20     |
+| scratch_9  | 0x24     |
+| scratch_10 | 0x28     |
+| scratch_11 | 0x2c     |
+| scratch_12 | 0x30     |
+| scratch_13 | 0x34     |
+| scratch_14 | 0x38     |
+| scratch_15 | 0x3c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "scratch", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                   |
+|:------:|:------:|:-------:|:--------|:------------------------------|
+|  31:0  |   rw   |   0x0   | scratch | Registers for use by software |
+
+## boot_mode
+Method to load boot code (connected to input pins)
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "boot_mode", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+|  31:2  |        |         | Reserved                           |
+|  1:0   |   ro   |    x    | [boot_mode](#boot_mode--boot_mode) |
+
+### boot_mode . boot_mode
+Method to load boot code (connected to input pins)
+
+| Value   | Name          | Description                          |
+|:--------|:--------------|:-------------------------------------|
+| 0x0     | passive       | Wait for external preload and launch |
+| 0x1     | spi_sdcard    | Boot from SD Card in SPI mode        |
+| 0x2     | spi_s25fs512s | Boot from S25FS512S SPI NOR flash    |
+| 0x3     | i2c_24xx1025  | Boot from 24xx1025 I2C EEPROM        |
+
+
+## rtc_freq
+Frequency (Hz) configured for RTC
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ref_freq", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------|
+|  31:0  |   ro   |    x    | ref_freq | Frequency (Hz) configured for RTC |
+
+## platform_rom
+Address of platform ROM
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "platform_rom", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description             |
+|:------:|:------:|:-------:|:-------------|:------------------------|
+|  31:0  |   ro   |    x    | platform_rom | Address of platform ROM |
+
+## num_int_harts
+Number of internal harts
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_harts", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description              |
+|:------:|:------:|:-------:|:----------|:-------------------------|
+|  31:0  |   ro   |    x    | num_harts | Number of internal harts |
+
+## hw_features
+Specifies which hardware features are available
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootrom", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "llc", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "uart", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "spi_host", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "i2c", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "gpio", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "dma", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "serial_link", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "vga", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "axirt", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "clic", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "irq_router", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bus_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                      |
+|:------:|:------:|:-------:|:------------|:---------------------------------|
+| 31:13  |        |         |             | Reserved                         |
+|   12   |   ro   |    x    | bus_err     | Whether UNBENT is available      |
+|   11   |   ro   |    x    | irq_router  | Whether IRQ router is available  |
+|   10   |   ro   |    x    | clic        | Whether CLIC is available        |
+|   9    |   ro   |    x    | axirt       | Whether AXI RT is available      |
+|   8    |   ro   |    x    | vga         | Whether VGA is available         |
+|   7    |   ro   |    x    | serial_link | Whether serial link is available |
+|   6    |   ro   |    x    | dma         | Whether DMA is available         |
+|   5    |   ro   |    x    | gpio        | Whether GPIO is available        |
+|   4    |   ro   |    x    | i2c         | Whether I2C is available         |
+|   3    |   ro   |    x    | spi_host    | Whether SPI host is available    |
+|   2    |   ro   |    x    | uart        | Whether UART is available        |
+|   1    |   ro   |    x    | llc         | Whether LLC is available         |
+|   0    |   ro   |    x    | bootrom     | Whether boot ROM is available    |
+
+## llc_size
+Total size of LLC in bytes
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "llc_size", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                |
+|:------:|:------:|:-------:|:---------|:---------------------------|
+|  31:0  |   ro   |    x    | llc_size | Total size of LLC in bytes |
+
+## vga_params
+VGA hardware parameters
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "red_width", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "green_width", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "blue_width", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description         |
+|:------:|:------:|:-------:|:------------|:--------------------|
+| 31:24  |        |         |             | Reserved            |
+| 23:16  |   ro   |    x    | blue_width  | Blue channel width  |
+|  15:8  |   ro   |    x    | green_width | Green channel width |
+|  7:0   |   ro   |    x    | red_width   | Red channel width   |
+
+
+
+## clic / doc / clicint_registers.md
+
+## Summary
+
+| Name                          | Offset   |   Length | Description                                           |
+|:------------------------------|:---------|---------:|:------------------------------------------------------|
+| CLICINT.[`CLICINT`](#clicint) | 0x0      |        4 | CLIC interrupt pending, enable, attribute and control |
+
+## CLICINT
+CLIC interrupt pending, enable, attribute and control
+- Offset: `0x0`
+- Reset default: `0xc00000`
+- Reset mask: `0xffc70101`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "IE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "ATTR_SHV", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ATTR_TRIG", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "ATTR_MODE", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "CTL", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                  |
+|:------:|:------:|:-------:|:----------|:---------------------------------------------|
+| 31:24  |   rw   |   0x0   | CTL       | interrupt control for interrupt              |
+| 23:22  |   rw   |   0x3   | ATTR_MODE | privilege mode of this interrupt             |
+| 21:19  |        |         |           | Reserved                                     |
+| 18:17  |   rw   |   0x0   | ATTR_TRIG | specify trigger type for this interrupt      |
+|   16   |   rw   |   0x0   | ATTR_SHV  | enable hardware vectoring for this interrupt |
+|  15:9  |        |         |           | Reserved                                     |
+|   8    |   rw   |   0x0   | IE        | interrupt enable for interrupt               |
+|  7:1   |        |         |           | Reserved                                     |
+|   0    |   rw   |   0x0   | IP        | interrupt pending for interrupt              |
+
+
+
+## clic / doc / clictv_registers.md
+
+## Summary
+
+| Name                             | Offset   |   Length | Description                   |
+|:---------------------------------|:---------|---------:|:------------------------------|
+| CLICINTV.[`CLICINTV`](#clicintv) | 0x0      |        4 | CLIC interrupt virtualization |
+
+## CLICINTV
+CLIC interrupt virtualization
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xfdfdfdfd`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "V0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID0", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID1", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID2", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID3", "bits": 6, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:26  |   rw   |   0x0   | VSID3  | interrupt VS id                |
+|   25   |        |         |        | Reserved                       |
+|   24   |   rw   |   0x0   | V3     | interrupt delegated to VS-mode |
+| 23:18  |   rw   |   0x0   | VSID2  | interrupt VS id                |
+|   17   |        |         |        | Reserved                       |
+|   16   |   rw   |   0x0   | V2     | interrupt delegated to VS-mode |
+| 15:10  |   rw   |   0x0   | VSID1  | interrupt VS id                |
+|   9    |        |         |        | Reserved                       |
+|   8    |   rw   |   0x0   | V1     | interrupt delegated to VS-mode |
+|  7:2   |   rw   |   0x0   | VSID0  | interrupt VS id                |
+|   1    |        |         |        | Reserved                       |
+|   0    |   rw   |   0x0   | V0     | interrupt delegated to VS-mode |
+
+
+
+## clic / doc / clicvs_registers.md
+
+## Summary
+
+| Name                       | Offset   |   Length | Description                      |
+|:---------------------------|:---------|---------:|:---------------------------------|
+| CLICVS.[`vsprio`](#vsprio) | 0x0      |        4 | CLIC virtual supervisor priority |
+
+## vsprio
+CLIC virtual supervisor priority
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1010101`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "prio0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+| 31:25  |        |         |        | Reserved      |
+|   24   |   rw   |   0x0   | prio3  | VS3 priority  |
+| 23:17  |        |         |        | Reserved      |
+|   16   |   rw   |   0x0   | prio2  | VS2 priority  |
+|  15:9  |        |         |        | Reserved      |
+|   8    |   rw   |   0x0   | prio1  | VS1 priority  |
+|  7:1   |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | prio0  | VS0 priority  |
+
+
+
+## clic / doc / mclic_registers.md
+
+## Summary
+
+| Name                                    | Offset   |   Length | Description                            |
+|:----------------------------------------|:---------|---------:|:---------------------------------------|
+| MCLIC.[`MCLICCFG`](#mcliccfg)           | 0x0      |        4 | CLIC configuration                     |
+| MCLIC.[`CLICMNXTICONF`](#clicmnxticonf) | 0x4      |        4 | CLIC enable mnxti irq forwarding logic |
+
+## MCLICCFG
+CLIC configuration
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xff0f003f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "mnlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "nmbits", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 10}, {"name": "snlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 4}, {"name": "unlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 4, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                      |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------|
+| 31:28  |   ro   |   0x0   | reserved | reserved                                         |
+| 27:24  |   rw   |   0x0   | unlbits  | number of privilege mode bits in user mode       |
+| 23:20  |        |         |          | Reserved                                         |
+| 19:16  |   rw   |   0x0   | snlbits  | number of privilege mode bits in supervisor mode |
+|  15:6  |        |         |          | Reserved                                         |
+|  5:4   |   rw   |   0x0   | nmbits   | number of privilege mode bits                    |
+|  3:0   |   rw   |   0x0   | mnlbits  | number of interrupt level bits in machine mode   |
+
+## CLICMNXTICONF
+CLIC enable mnxti irq forwarding logic
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CLICMNXTICONF", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x0   | CLICMNXTICONF |               |
+
+
+
+## clint / doc / registers.md
+
+## Summary
+
+| Name                                      | Offset   |   Length | Description                        |
+|:------------------------------------------|:---------|---------:|:-----------------------------------|
+| CLINT.[`MSIP_0`](#msip)                   | 0x0      |        4 | Machine Software Interrupt Pending |
+| CLINT.[`MSIP_1`](#msip)                   | 0x4      |        4 | Machine Software Interrupt Pending |
+| CLINT.[`MTIMECMP_LOW0`](#mtimecmp_low0)   | 0x4000   |        4 | Machine Timer Compare for Core 0   |
+| CLINT.[`MTIMECMP_HIGH0`](#mtimecmp_high0) | 0x4004   |        4 | Machine Timer Compare for Core 0   |
+| CLINT.[`MTIMECMP_LOW1`](#mtimecmp_low1)   | 0x4008   |        4 | Machine Timer Compare for Core 1   |
+| CLINT.[`MTIMECMP_HIGH1`](#mtimecmp_high1) | 0x400c   |        4 | Machine Timer Compare for Core 1   |
+| CLINT.[`MTIME_LOW`](#mtime_low)           | 0xbff8   |        4 | Timer Register Low                 |
+| CLINT.[`MTIME_HIGH`](#mtime_high)         | 0xbffc   |        4 | Timer Register High                |
+
+## MSIP
+Machine Software Interrupt Pending
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name   | Offset   |
+|:-------|:---------|
+| MSIP_0 | 0x0      |
+| MSIP_1 | 0x4      |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "P", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RSVD", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:1  |   ro   |   0x0   | RSVD   | Reserved                           |
+|   0    |   rw   |   0x0   | P      | Machine Software Interrupt Pending |
+
+## MTIMECMP_LOW0
+Machine Timer Compare for Core 0
+- Offset: `0x4000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                       |
+|:------:|:------:|:-------:|:-------------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_LOW | Machine Time Compare (Low) Core 0 |
+
+## MTIMECMP_HIGH0
+Machine Timer Compare for Core 0
+- Offset: `0x4004`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                        |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_HIGH | Machine Time Compare (High) Core 0 |
+
+## MTIMECMP_LOW1
+Machine Timer Compare for Core 1
+- Offset: `0x4008`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                       |
+|:------:|:------:|:-------:|:-------------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_LOW | Machine Time Compare (Low) Core 1 |
+
+## MTIMECMP_HIGH1
+Machine Timer Compare for Core 1
+- Offset: `0x400c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                        |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_HIGH | Machine Time Compare (High) Core 1 |
+
+## MTIME_LOW
+Timer Register Low
+- Offset: `0xbff8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIME_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description        |
+|:------:|:------:|:-------:|:----------|:-------------------|
+|  31:0  |   rw   |   0x0   | MTIME_LOW | Machine Time (Low) |
+
+## MTIME_HIGH
+Timer Register High
+- Offset: `0xbffc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIME_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description         |
+|:------:|:------:|:-------:|:-----------|:--------------------|
+|  31:0  |   rw   |   0x0   | MTIME_HIGH | Machine Time (High) |
+
+
+
+## cl_event_unit / doc / registers.md
+
+## Summary
+
+| Name                                                                               | Offset   |   Length | Description                                                                                        |
+|:-----------------------------------------------------------------------------------|:---------|---------:|:---------------------------------------------------------------------------------------------------|
+| cluster_event_unit.[`EVT_MASK`](#evt_mask)                                         | 0x0      |        4 | Input event mask configuration register.                                                           |
+| cluster_event_unit.[`EVT_MASK_AND`](#evt_mask_and)                                 | 0x4      |        4 | Input event mask update command register with bitwise AND operation.                               |
+| cluster_event_unit.[`EVT_MASK_OR`](#evt_mask_or)                                   | 0x8      |        4 | Input event mask update command register with bitwise OR operation.                                |
+| cluster_event_unit.[`IRQ_MASK`](#irq_mask)                                         | 0xc      |        4 | Interrupt request mask configuration register.                                                     |
+| cluster_event_unit.[`IRQ_MASK_AND`](#irq_mask_and)                                 | 0x10     |        4 | Interrupt request mask update command register with bitwise AND operation.                         |
+| cluster_event_unit.[`IRQ_MASK_OR`](#irq_mask_or)                                   | 0x14     |        4 | Interrupt request mask update command register with bitwise OR operation.                          |
+| cluster_event_unit.[`CLOCK_STATUS`](#clock_status)                                 | 0x18     |        4 | Cluster cores clock status register.                                                               |
+| cluster_event_unit.[`EVENT_BUFFER`](#event_buffer)                                 | 0x1c     |        4 | Pending input events status register.                                                              |
+| cluster_event_unit.[`EVENT_BUFFER_MASKED`](#event_buffer_masked)                   | 0x20     |        4 | Pending input events status register with EVT_MASK applied.                                        |
+| cluster_event_unit.[`EVENT_BUFFER_IRQ_MASKED`](#event_buffer_irq_masked)           | 0x24     |        4 | Pending input events status register with IRQ_MASK applied.                                        |
+| cluster_event_unit.[`EVENT_BUFFER_CLEAR`](#event_buffer_clear)                     | 0x28     |        4 | Pending input events status clear command register.                                                |
+| cluster_event_unit.[`SW_EVENT_MASK`](#sw_event_mask)                               | 0x2c     |        4 | Software events cluster cores destination mask configuration register.                             |
+| cluster_event_unit.[`SW_EVENT_MASK_AND`](#sw_event_mask_and)                       | 0x30     |        4 | Software events cluster cores destination mask update command register with bitwise AND operation. |
+| cluster_event_unit.[`SW_EVENT_MASK_OR`](#sw_event_mask_or)                         | 0x34     |        4 | Software events cluster cores destination mask update command register with bitwise OR operation.  |
+| cluster_event_unit.[`EVENT_WAIT`](#event_wait)                                     | 0x38     |        4 | Input event wait command register.                                                                 |
+| cluster_event_unit.[`EVENT_WAIT_CLEAR`](#event_wait_clear)                         | 0x3c     |        4 | Input event wait and clear command register.                                                       |
+| cluster_event_unit.[`HW_DISPATCH_PUSH_TASK`](#hw_dispatch_push_task)               | 0x40     |        4 | Hardware task dispatcher push command register.                                                    |
+| cluster_event_unit.[`HW_DISPATCH_POP_TASK`](#hw_dispatch_pop_task)                 | 0x44     |        4 | Hardware task dispatcher pop command register.                                                     |
+| cluster_event_unit.[`HW_DISPATCH_PUSH_TEAM_CONFIG`](#hw_dispatch_push_team_config) | 0x48     |        4 | Hardware task dispatcher cluster core team configuration register.                                 |
+| cluster_event_unit.[`HW_MUTEX_0_MSG_PUT`](#hw_mutex_0_msg_put)                     | 0x4c     |        4 | Hardware mutex 0 non-blocking put command register.                                                |
+| cluster_event_unit.[`HW_MUTEX_0_MSG_GET`](#hw_mutex_0_msg_get)                     | 0x50     |        4 | Hardware mutex 0 blocking get command register.                                                    |
+| cluster_event_unit.[`HW_MUTEX_1_MSG_PUT`](#hw_mutex_1_msg_put)                     | 0x54     |        4 | Hardware mutex 1 non-blocking put command register.                                                |
+| cluster_event_unit.[`HW_MUTEX_1_MSG_GET`](#hw_mutex_1_msg_get)                     | 0x58     |        4 | Hardware mutex 1 blocking get command register.                                                    |
+| cluster_event_unit.[`SW_EVENT_0_TRIG`](#sw_event_0_trig)                           | 0x5c     |        4 | Cluster Software event 0 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_1_TRIG`](#sw_event_1_trig)                           | 0x60     |        4 | Cluster Software event 1 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_2_TRIG`](#sw_event_2_trig)                           | 0x64     |        4 | Cluster Software event 2 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_3_TRIG`](#sw_event_3_trig)                           | 0x68     |        4 | Cluster Software event 3 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_4_TRIG`](#sw_event_4_trig)                           | 0x6c     |        4 | Cluster Software event 4 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_5_TRIG`](#sw_event_5_trig)                           | 0x70     |        4 | Cluster Software event 5 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_6_TRIG`](#sw_event_6_trig)                           | 0x74     |        4 | Cluster Software event 6 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_7_TRIG`](#sw_event_7_trig)                           | 0x78     |        4 | Cluster Software event 7 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_0_TRIG_WAIT`](#sw_event_0_trig_wait)                 | 0x7c     |        4 | Cluster Software event 0 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_1_TRIG_WAIT`](#sw_event_1_trig_wait)                 | 0x80     |        4 | Cluster Software event 1 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_2_TRIG_WAIT`](#sw_event_2_trig_wait)                 | 0x84     |        4 | Cluster Software event 2 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_3_TRIG_WAIT`](#sw_event_3_trig_wait)                 | 0x88     |        4 | Cluster Software event 3 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_4_TRIG_WAIT`](#sw_event_4_trig_wait)                 | 0x8c     |        4 | Cluster Software event 4 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_5_TRIG_WAIT`](#sw_event_5_trig_wait)                 | 0x90     |        4 | Cluster Software event 5 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_6_TRIG_WAIT`](#sw_event_6_trig_wait)                 | 0x94     |        4 | Cluster Software event 6 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_7_TRIG_WAIT`](#sw_event_7_trig_wait)                 | 0x98     |        4 | Cluster Software event 7 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_0_TRIG_WAIT_CLEAR`](#sw_event_0_trig_wait_clear)     | 0x9c     |        4 | Cluster Software event 0 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_1_TRIG_WAIT_CLEAR`](#sw_event_1_trig_wait_clear)     | 0xa0     |        4 | Cluster Software event 1 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_2_TRIG_WAIT_CLEAR`](#sw_event_2_trig_wait_clear)     | 0xa4     |        4 | Cluster Software event 2 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_3_TRIG_WAIT_CLEAR`](#sw_event_3_trig_wait_clear)     | 0xa8     |        4 | Cluster Software event 3 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_4_TRIG_WAIT_CLEAR`](#sw_event_4_trig_wait_clear)     | 0xac     |        4 | Cluster Software event 4 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_5_TRIG_WAIT_CLEAR`](#sw_event_5_trig_wait_clear)     | 0xb0     |        4 | Cluster Software event 5 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_6_TRIG_WAIT_CLEAR`](#sw_event_6_trig_wait_clear)     | 0xb4     |        4 | Cluster Software event 6 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_7_TRIG_WAIT_CLEAR`](#sw_event_7_trig_wait_clear)     | 0xb8     |        4 | Cluster Software event 7 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SOC_PERIPH_EVENT_ID`](#soc_periph_event_id)                   | 0xbc     |        4 | Cluster SoC peripheral event ID status register.                                                   |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG_MASK`](#hw_barrier_0_trig_mask)             | 0xc0     |        4 | Cluster hardware barrier 0 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG_MASK`](#hw_barrier_1_trig_mask)             | 0xc4     |        4 | Cluster hardware barrier 1 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG_MASK`](#hw_barrier_2_trig_mask)             | 0xc8     |        4 | Cluster hardware barrier 2 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG_MASK`](#hw_barrier_3_trig_mask)             | 0xcc     |        4 | Cluster hardware barrier 3 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG_MASK`](#hw_barrier_4_trig_mask)             | 0xd0     |        4 | Cluster hardware barrier 4 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG_MASK`](#hw_barrier_5_trig_mask)             | 0xd4     |        4 | Cluster hardware barrier 5 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG_MASK`](#hw_barrier_6_trig_mask)             | 0xd8     |        4 | Cluster hardware barrier 6 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG_MASK`](#hw_barrier_7_trig_mask)             | 0xdc     |        4 | Cluster hardware barrier 7 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_0_STATUS`](#hw_barrier_0_status)                   | 0xe0     |        4 | Cluster hardware barrier 0 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_1_STATUS`](#hw_barrier_1_status)                   | 0xe4     |        4 | Cluster hardware barrier 1 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_2_STATUS`](#hw_barrier_2_status)                   | 0xe8     |        4 | Cluster hardware barrier 2 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_3_STATUS`](#hw_barrier_3_status)                   | 0xec     |        4 | Cluster hardware barrier 3 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_4_STATUS`](#hw_barrier_4_status)                   | 0xf0     |        4 | Cluster hardware barrier 4 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_5_STATUS`](#hw_barrier_5_status)                   | 0xf4     |        4 | Cluster hardware barrier 5 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_6_STATUS`](#hw_barrier_6_status)                   | 0xf8     |        4 | Cluster hardware barrier 6 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_7_STATUS`](#hw_barrier_7_status)                   | 0xfc     |        4 | Cluster hardware barrier 7 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_0_STATUS_SUM`](#hw_barrier_0_status_sum)           | 0x100    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_1_STATUS_SUM`](#hw_barrier_1_status_sum)           | 0x104    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_2_STATUS_SUM`](#hw_barrier_2_status_sum)           | 0x108    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_3_STATUS_SUM`](#hw_barrier_3_status_sum)           | 0x10c    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_4_STATUS_SUM`](#hw_barrier_4_status_sum)           | 0x110    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_5_STATUS_SUM`](#hw_barrier_5_status_sum)           | 0x114    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_6_STATUS_SUM`](#hw_barrier_6_status_sum)           | 0x118    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_7_STATUS_SUM`](#hw_barrier_7_status_sum)           | 0x11c    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_0_TARGET_MASK`](#hw_barrier_0_target_mask)         | 0x120    |        4 | Cluster hardware barrier 0 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_1_TARGET_MASK`](#hw_barrier_1_target_mask)         | 0x124    |        4 | Cluster hardware barrier 1 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_2_TARGET_MASK`](#hw_barrier_2_target_mask)         | 0x128    |        4 | Cluster hardware barrier 2 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_3_TARGET_MASK`](#hw_barrier_3_target_mask)         | 0x12c    |        4 | Cluster hardware barrier 3 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_4_TARGET_MASK`](#hw_barrier_4_target_mask)         | 0x130    |        4 | Cluster hardware barrier 4 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_5_TARGET_MASK`](#hw_barrier_5_target_mask)         | 0x134    |        4 | Cluster hardware barrier 5 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_6_TARGET_MASK`](#hw_barrier_6_target_mask)         | 0x138    |        4 | Cluster hardware barrier 6 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_7_TARGET_MASK`](#hw_barrier_7_target_mask)         | 0x13c    |        4 | Cluster hardware barrier 7 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG`](#hw_barrier_0_trig)                       | 0x140    |        4 | Cluster hardware barrier 0 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG`](#hw_barrier_1_trig)                       | 0x144    |        4 | Cluster hardware barrier 1 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG`](#hw_barrier_2_trig)                       | 0x148    |        4 | Cluster hardware barrier 2 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG`](#hw_barrier_3_trig)                       | 0x14c    |        4 | Cluster hardware barrier 3 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG`](#hw_barrier_4_trig)                       | 0x150    |        4 | Cluster hardware barrier 4 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG`](#hw_barrier_5_trig)                       | 0x154    |        4 | Cluster hardware barrier 5 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG`](#hw_barrier_6_trig)                       | 0x158    |        4 | Cluster hardware barrier 6 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG`](#hw_barrier_7_trig)                       | 0x15c    |        4 | Cluster hardware barrier 7 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_0_SELF_TRIG`](#hw_barrier_0_self_trig)             | 0x160    |        4 | Cluster hardware barrier 0 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_1_SELF_TRIG`](#hw_barrier_1_self_trig)             | 0x164    |        4 | Cluster hardware barrier 1 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_2_SELF_TRIG`](#hw_barrier_2_self_trig)             | 0x168    |        4 | Cluster hardware barrier 2 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_3_SELF_TRIG`](#hw_barrier_3_self_trig)             | 0x16c    |        4 | Cluster hardware barrier 3 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_4_SELF_TRIG`](#hw_barrier_4_self_trig)             | 0x170    |        4 | Cluster hardware barrier 4 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_5_SELF_TRIG`](#hw_barrier_5_self_trig)             | 0x174    |        4 | Cluster hardware barrier 5 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_6_SELF_TRIG`](#hw_barrier_6_self_trig)             | 0x178    |        4 | Cluster hardware barrier 6 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_7_SELF_TRIG`](#hw_barrier_7_self_trig)             | 0x17c    |        4 | Cluster hardware barrier 7 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG_WAIT`](#hw_barrier_0_trig_wait)             | 0x180    |        4 | Cluster hardware barrier 0 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG_WAIT`](#hw_barrier_1_trig_wait)             | 0x184    |        4 | Cluster hardware barrier 1 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG_WAIT`](#hw_barrier_2_trig_wait)             | 0x188    |        4 | Cluster hardware barrier 2 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG_WAIT`](#hw_barrier_3_trig_wait)             | 0x18c    |        4 | Cluster hardware barrier 3 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG_WAIT`](#hw_barrier_4_trig_wait)             | 0x190    |        4 | Cluster hardware barrier 4 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG_WAIT`](#hw_barrier_5_trig_wait)             | 0x194    |        4 | Cluster hardware barrier 5 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG_WAIT`](#hw_barrier_6_trig_wait)             | 0x198    |        4 | Cluster hardware barrier 6 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG_WAIT`](#hw_barrier_7_trig_wait)             | 0x19c    |        4 | Cluster hardware barrier 7 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG_WAIT_CLEAR`](#hw_barrier_0_trig_wait_clear) | 0x1a0    |        4 | Cluster hardware barrier 0 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG_WAIT_CLEAR`](#hw_barrier_1_trig_wait_clear) | 0x1a4    |        4 | Cluster hardware barrier 1 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG_WAIT_CLEAR`](#hw_barrier_2_trig_wait_clear) | 0x1a8    |        4 | Cluster hardware barrier 2 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG_WAIT_CLEAR`](#hw_barrier_3_trig_wait_clear) | 0x1ac    |        4 | Cluster hardware barrier 3 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG_WAIT_CLEAR`](#hw_barrier_4_trig_wait_clear) | 0x1b0    |        4 | Cluster hardware barrier 4 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG_WAIT_CLEAR`](#hw_barrier_5_trig_wait_clear) | 0x1b4    |        4 | Cluster hardware barrier 5 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG_WAIT_CLEAR`](#hw_barrier_6_trig_wait_clear) | 0x1b8    |        4 | Cluster hardware barrier 6 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG_WAIT_CLEAR`](#hw_barrier_7_trig_wait_clear) | 0x1bc    |        4 | Cluster hardware barrier 7 trigger, wait and clear command register.                               |
+
+## EVT_MASK
+Input event mask configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EMCL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "EMINTCL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EMSOC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                      |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EMSOC   | Soc peripheral input event mask configuration bitfield: - EMSOC[i]=1'b0: Input event request i is masked - EMSOC[i]=1'b1: Input event request i is not masked    |
+|   30   |   rw   |   0x0   | EMINTCL | Inter-cluster input event mask configuration bitfield: - EMINTCL[i]=1'b0: Input event request i is masked - EMINTCL[i]=1'b1: Input event request i is not masked |
+|  29:0  |   rw   |   0x0   | EMCL    | Cluster internal input event mask configuration bitfield: - EMCL[i]=1'b0: Input event request i is masked - EMCL[i]=1'b1: Input event request i is not masked    |
+
+## EVT_MASK_AND
+Input event mask update command register with bitwise AND operation.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EMA", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | EMA    | Input event mask configuration bitfield update with bitwise AND operation. It allows clearing EMCL[i], EMINTCL[i] or EMSOC[i] if EMA[i]=1'b1. |
+
+## EVT_MASK_OR
+Input event mask update command register with bitwise OR operation.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EMO", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                 |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | EMO    | Input event mask configuration bitfield update with bitwise OR operation. It allows setting EMCL[i], EMINTCL[i] or EMSOC[i] if EMO[i]=1'b1. |
+
+## IRQ_MASK
+Interrupt request mask configuration register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IMCL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "IMINTCL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IMSOC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                   |
+|:------:|:------:|:-------:|:--------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | IMSOC   | Soc peripheral interrupt request mask configuration bitfield: - bit[i]=1'b0: Interrupt request i is masked - bit[i]=1'b1: Interrupt request i is not masked   |
+|   30   |   rw   |   0x0   | IMINTCL | Inter-cluster interrupt request mask configuration bitfield: - bit[i]=1'b0: Interrupt request i is masked - bit[i]=1'b1: Interrupt request i is not masked    |
+|  29:0  |   rw   |   0x0   | IMCL    | Cluster internal interrupt request mask configuration bitfield: - bit[i]=1'b0: Interrupt request i is masked - bit[i]=1'b1: Interrupt request i is not masked |
+
+## IRQ_MASK_AND
+Interrupt request mask update command register with bitwise AND operation.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IMA", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | IMA    | Interrupt request mask configuration bitfield update with bitwise AND operation. It allows clearing IMCL[i], IMINTCL[i] or IMSOC[i] if IMA[i]=1'b1. |
+
+## IRQ_MASK_OR
+Interrupt request mask update command register with bitwise OR operation.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IMO", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                       |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | IMO    | Interrupt request mask configuration bitfield update with bitwise OR operation. It allows setting IMCL[i], IMINTCL[i] or IMSOC[i] if IMO[i]=1'b1. |
+
+## CLOCK_STATUS
+Cluster cores clock status register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                       |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                          |
+|   0    |   ro   |   0x0   | CS     | Cluster core clock status bitfield: - 1'b0: Cluster core clocked is gated - 1'b1: Cluster core clocked is running |
+
+## EVENT_BUFFER
+Pending input events status register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EB", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                      |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EB     | Pending input events status bitfield. EB[i]=1'b1: one or more input event i request are pending. |
+
+## EVENT_BUFFER_MASKED
+Pending input events status register with EVT_MASK applied.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                             |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Pending input events status bitfield with EVT_MASK applied. EBM[i]=1'b1: one or more input event i request are pending. |
+
+## EVENT_BUFFER_IRQ_MASKED
+Pending input events status register with IRQ_MASK applied.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                       |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | IBM    | Pending input events status bitfield with IRQ_MASK applied. IBM[i]=1'b1:  one or more input events i are pending. |
+
+## EVENT_BUFFER_CLEAR
+Pending input events status clear command register.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBC", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | EBC    | Pending input events status clear command bitfield. It allows clearing EB[i] if EBC[i]=1'b1. |
+
+## SW_EVENT_MASK
+Software events cluster cores destination mask configuration register.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SWEM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                        |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                           |
+|  7:0   |   rw   |   0x0   | SWEM   | Software events mask configuration bitfield: - bit[i]=1'b0: software events are masked for CL_CORE[i] - bit[i]=1'b1: software events are not masked for CL_CORE[i] |
+
+## SW_EVENT_MASK_AND
+Software events cluster cores destination mask update command register with bitwise AND operation.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SWEMA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                   |
+|  7:0   |   wo   |   0x0   | SWEMA  | Software event mask configuration bitfield update with bitwise AND operation. It allows clearing SWEM[i] if SWEMA[i]=1'b1. |
+
+## SW_EVENT_MASK_OR
+Software events cluster cores destination mask update command register with bitwise OR operation.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SWEMO", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                 |
+|  7:0   |   wo   |   0x0   | SWEMO  | Software event mask configuration bitfield update with bitwise OR operation. It allows setting SWEM[i] if SWEMO[i]=1'b1. |
+
+## EVENT_WAIT
+Input event wait command register.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                 |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Reading this register will gate the Cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## EVENT_WAIT_CLEAR
+Input event wait and clear command register.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Reading this register has the same effect as reading EVENT_WAIT.EBM. In addition, EVENT_BUFFER.EB[i] bits are cleared if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_DISPATCH_PUSH_TASK
+Hardware task dispatcher push command register.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                  |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | MSG    | Message to dispatch to all cluster cores selected in HW_DISPATCH_PUSH_TEAM_CONFIG.CT configuration bitfield. |
+
+## HW_DISPATCH_POP_TASK
+Hardware task dispatcher pop command register.
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | MSG    | Message dispatched using HW_DISPATCH_PUSH_TASK command and popped by cluster core who issued HW_DISPATCH_POP_TASK command. |
+
+## HW_DISPATCH_PUSH_TEAM_CONFIG
+Hardware task dispatcher cluster core team configuration register.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CT", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                              |
+|  7:0   |   rw   |   0x0   | CT     | Cluster cores team selection configuration bitfield. It allows to transmit HW_DISPATCH_PUSH_TASK.MSG to cluster core i if CT[i]=1'b1. |
+
+## HW_MUTEX_0_MSG_PUT
+Hardware mutex 0 non-blocking put command register.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | MSG    | Message pushed when releasing hardware mutex 0 configuration bitfiled. It is a non-blocking access. |
+
+## HW_MUTEX_0_MSG_GET
+Hardware mutex 0 blocking get command register.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | MSG    | Message popped when taking hardware mutex 0 data bitfiled. It is a blocking access. |
+
+## HW_MUTEX_1_MSG_PUT
+Hardware mutex 1 non-blocking put command register.
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | MSG    | Message pushed when releasing hardware mutex 1 configuration bitfiled. It is a non-blocking access. |
+
+## HW_MUTEX_1_MSG_GET
+Hardware mutex 1 blocking get command register.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | MSG    | Message popped when taking hardware mutex 1 data bitfiled. It is a blocking access. |
+
+## SW_EVENT_0_TRIG
+Cluster Software event 0 trigger command register.
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW0T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW0T   | Triggers software event 0 for cluster core i if SW0T[i]=1'b1. |
+
+## SW_EVENT_1_TRIG
+Cluster Software event 1 trigger command register.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW1T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW1T   | Triggers software event 1 for cluster core i if SW1T[i]=1'b1. |
+
+## SW_EVENT_2_TRIG
+Cluster Software event 2 trigger command register.
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW2T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW2T   | Triggers software event 2 for cluster core i if SW2T[i]=1'b1. |
+
+## SW_EVENT_3_TRIG
+Cluster Software event 3 trigger command register.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW3T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW3T   | Triggers software event 3 for cluster core i if SW3T[i]=1'b1. |
+
+## SW_EVENT_4_TRIG
+Cluster Software event 4 trigger command register.
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW4T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW4T   | Triggers software event 4 for cluster core i if SW4T[i]=1'b1. |
+
+## SW_EVENT_5_TRIG
+Cluster Software event 5 trigger command register.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW5T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW5T   | Triggers software event 5 for cluster core i if SW5T[i]=1'b1. |
+
+## SW_EVENT_6_TRIG
+Cluster Software event 6 trigger command register.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW6T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW6T   | Triggers software event 6 for cluster core i if SW6T[i]=1'b1. |
+
+## SW_EVENT_7_TRIG
+Cluster Software event 7 trigger command register.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW7T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW7T   | Triggers software event 7 for cluster core i if SW7T[i]=1'b1. |
+
+## SW_EVENT_0_TRIG_WAIT
+Cluster Software event 0 trigger and wait command register.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_1_TRIG_WAIT
+Cluster Software event 1 trigger and wait command register.
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_2_TRIG_WAIT
+Cluster Software event 2 trigger and wait command register.
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_3_TRIG_WAIT
+Cluster Software event 3 trigger and wait command register.
+- Offset: `0x88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_4_TRIG_WAIT
+Cluster Software event 4 trigger and wait command register.
+- Offset: `0x8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_5_TRIG_WAIT
+Cluster Software event 5 trigger and wait command register.
+- Offset: `0x90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_6_TRIG_WAIT
+Cluster Software event 6 trigger and wait command register.
+- Offset: `0x94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_7_TRIG_WAIT
+Cluster Software event 7 trigger and wait command register.
+- Offset: `0x98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_0_TRIG_WAIT_CLEAR
+Cluster Software event 0 trigger, wait and clear command register.
+- Offset: `0x9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_0_trig_wait_clear--ebm) |
+
+### SW_EVENT_0_TRIG_WAIT_CLEAR . EBM
+Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_1_TRIG_WAIT_CLEAR
+Cluster Software event 1 trigger, wait and clear command register.
+- Offset: `0xa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_1_trig_wait_clear--ebm) |
+
+### SW_EVENT_1_TRIG_WAIT_CLEAR . EBM
+Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_2_TRIG_WAIT_CLEAR
+Cluster Software event 2 trigger, wait and clear command register.
+- Offset: `0xa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_2_trig_wait_clear--ebm) |
+
+### SW_EVENT_2_TRIG_WAIT_CLEAR . EBM
+Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_3_TRIG_WAIT_CLEAR
+Cluster Software event 3 trigger, wait and clear command register.
+- Offset: `0xa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_3_trig_wait_clear--ebm) |
+
+### SW_EVENT_3_TRIG_WAIT_CLEAR . EBM
+Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_4_TRIG_WAIT_CLEAR
+Cluster Software event 4 trigger, wait and clear command register.
+- Offset: `0xac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_4_trig_wait_clear--ebm) |
+
+### SW_EVENT_4_TRIG_WAIT_CLEAR . EBM
+Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_5_TRIG_WAIT_CLEAR
+Cluster Software event 5 trigger, wait and clear command register.
+- Offset: `0xb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_5_trig_wait_clear--ebm) |
+
+### SW_EVENT_5_TRIG_WAIT_CLEAR . EBM
+Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_6_TRIG_WAIT_CLEAR
+Cluster Software event 6 trigger, wait and clear command register.
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_6_trig_wait_clear--ebm) |
+
+### SW_EVENT_6_TRIG_WAIT_CLEAR . EBM
+Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_7_TRIG_WAIT_CLEAR
+Cluster Software event 7 trigger, wait and clear command register.
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_7_trig_wait_clear--ebm) |
+
+### SW_EVENT_7_TRIG_WAIT_CLEAR . EBM
+Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SOC_PERIPH_EVENT_ID
+Cluster SoC peripheral event ID status register.
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0x800000ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 23}, {"name": "VALID", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                      |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------|
+|   31   |   ro   |   0x0   | VALID  | Validity bit of SOC_PERIPH_EVENT_ID.ID bitfield. |
+|  30:8  |        |         |        | Reserved                                         |
+|  7:0   |   ro   |   0x0   | ID     | Oldest SoC peripheral event ID status bitfield.  |
+
+## HW_BARRIER_0_TRIG_MASK
+Cluster hardware barrier 0 trigger mask configuration register.
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB0TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB0TM  | Trigger mask for hardware barrier 0 bitfield. Hardware barrier 0 will be triggered only if for all HB0TM[i] = 1'b1,  HW_BARRIER_0_STATUS.HB0S[i]=1'b1. HB0TM=0 means that hardware barrier 0 is disabled. |
+
+## HW_BARRIER_1_TRIG_MASK
+Cluster hardware barrier 1 trigger mask configuration register.
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB1TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB1TM  | Trigger mask for hardware barrier 1 bitfield. Hardware barrier 1 will be triggered only if for all HB1TM[i] = 1'b1,  HW_BARRIER_1_STATUS.HB1S[i]=1'b1. HB1TM=0 means that hardware barrier 1 is disabled. |
+
+## HW_BARRIER_2_TRIG_MASK
+Cluster hardware barrier 2 trigger mask configuration register.
+- Offset: `0xc8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB2TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB2TM  | Trigger mask for hardware barrier 2 bitfield. Hardware barrier 2 will be triggered only if for all HB2TM[i] = 1'b1,  HW_BARRIER_2_STATUS.HB2S[i]=1'b1. HB2TM=0 means that hardware barrier 2 is disabled. |
+
+## HW_BARRIER_3_TRIG_MASK
+Cluster hardware barrier 3 trigger mask configuration register.
+- Offset: `0xcc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB3TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB3TM  | Trigger mask for hardware barrier 3 bitfield. Hardware barrier 3 will be triggered only if for all HB3TM[i] = 1'b1,  HW_BARRIER_3_STATUS.HB3S[i]=1'b1. HB3TM=0 means that hardware barrier 3 is disabled. |
+
+## HW_BARRIER_4_TRIG_MASK
+Cluster hardware barrier 4 trigger mask configuration register.
+- Offset: `0xd0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB4TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB4TM  | Trigger mask for hardware barrier 4 bitfield. Hardware barrier 4 will be triggered only if for all HB4TM[i] = 1'b1,  HW_BARRIER_4_STATUS.HB4S[i]=1'b1. HB4TM=0 means that hardware barrier 4 is disabled. |
+
+## HW_BARRIER_5_TRIG_MASK
+Cluster hardware barrier 5 trigger mask configuration register.
+- Offset: `0xd4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB5TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB5TM  | Trigger mask for hardware barrier 5 bitfield. Hardware barrier 5 will be triggered only if for all HB5TM[i] = 1'b1,  HW_BARRIER_5_STATUS.HB5S[i]=1'b1. HB5TM=0 means that hardware barrier 5 is disabled. |
+
+## HW_BARRIER_6_TRIG_MASK
+Cluster hardware barrier 6 trigger mask configuration register.
+- Offset: `0xd8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB6TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB6TM  | Trigger mask for hardware barrier 6 bitfield. Hardware barrier 6 will be triggered only if for all HB6TM[i] = 1'b1,  HW_BARRIER_6_STATUS.HB6S[i]=1'b1. HB6TM=0 means that hardware barrier 6 is disabled. |
+
+## HW_BARRIER_7_TRIG_MASK
+Cluster hardware barrier 7 trigger mask configuration register.
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB7TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB7TM  | Trigger mask for hardware barrier 7 bitfield. Hardware barrier 7 will be triggered only if for all HB7TM[i] = 1'b1,  HW_BARRIER_7_STATUS.HB7S[i]=1'b1. HB7TM=0 means that hardware barrier 7 is disabled. |
+
+## HW_BARRIER_0_STATUS
+Cluster hardware barrier 0 status register.
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 0 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 0. It is cleared when HBS matches HW_BARRIER_0_TRIG_MASK.HB0TM. |
+
+## HW_BARRIER_1_STATUS
+Cluster hardware barrier 1 status register.
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 1 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 1. It is cleared when HBS matches HW_BARRIER_1_TRIG_MASK.HB1TM. |
+
+## HW_BARRIER_2_STATUS
+Cluster hardware barrier 2 status register.
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 2 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 2. It is cleared when HBS matches HW_BARRIER_2_TRIG_MASK.HB2TM. |
+
+## HW_BARRIER_3_STATUS
+Cluster hardware barrier 3 status register.
+- Offset: `0xec`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 3 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 3. It is cleared when HBS matches HW_BARRIER_3_TRIG_MASK.HB3TM. |
+
+## HW_BARRIER_4_STATUS
+Cluster hardware barrier 4 status register.
+- Offset: `0xf0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 4 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 4. It is cleared when HBS matches HW_BARRIER_4_TRIG_MASK.HB4TM. |
+
+## HW_BARRIER_5_STATUS
+Cluster hardware barrier 5 status register.
+- Offset: `0xf4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 5 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 5. It is cleared when HBS matches HW_BARRIER_5_TRIG_MASK.HB5TM. |
+
+## HW_BARRIER_6_STATUS
+Cluster hardware barrier 6 status register.
+- Offset: `0xf8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 6 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 6. It is cleared when HBS matches HW_BARRIER_6_TRIG_MASK.HB6TM. |
+
+## HW_BARRIER_7_STATUS
+Cluster hardware barrier 7 status register.
+- Offset: `0xfc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 7 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 7. It is cleared when HBS matches HW_BARRIER_7_TRIG_MASK.HB7TM. |
+
+## HW_BARRIER_0_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x100`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 0. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_1_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x104`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 1. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_2_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x108`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 2. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_3_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x10c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 3. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_4_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x110`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 4. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_5_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x114`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 5. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_6_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x118`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 6. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_7_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x11c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 7. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_0_TARGET_MASK
+Cluster hardware barrier 0 target mask configuration register.
+- Offset: `0x120`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 0 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 0 event when HW_BARRIER_0_STATUS will match HW_BARRIER_0_TRIG_MASK. |
+
+## HW_BARRIER_1_TARGET_MASK
+Cluster hardware barrier 1 target mask configuration register.
+- Offset: `0x124`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 1 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 1 event when HW_BARRIER_1_STATUS will match HW_BARRIER_1_TRIG_MASK. |
+
+## HW_BARRIER_2_TARGET_MASK
+Cluster hardware barrier 2 target mask configuration register.
+- Offset: `0x128`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 2 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 2 event when HW_BARRIER_2_STATUS will match HW_BARRIER_2_TRIG_MASK. |
+
+## HW_BARRIER_3_TARGET_MASK
+Cluster hardware barrier 3 target mask configuration register.
+- Offset: `0x12c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 3 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 3 event when HW_BARRIER_3_STATUS will match HW_BARRIER_3_TRIG_MASK. |
+
+## HW_BARRIER_4_TARGET_MASK
+Cluster hardware barrier 4 target mask configuration register.
+- Offset: `0x130`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 4 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 4 event when HW_BARRIER_4_STATUS will match HW_BARRIER_4_TRIG_MASK. |
+
+## HW_BARRIER_5_TARGET_MASK
+Cluster hardware barrier 5 target mask configuration register.
+- Offset: `0x134`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 5 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 5 event when HW_BARRIER_5_STATUS will match HW_BARRIER_5_TRIG_MASK. |
+
+## HW_BARRIER_6_TARGET_MASK
+Cluster hardware barrier 6 target mask configuration register.
+- Offset: `0x138`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 6 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 6 event when HW_BARRIER_6_STATUS will match HW_BARRIER_6_TRIG_MASK. |
+
+## HW_BARRIER_7_TARGET_MASK
+Cluster hardware barrier 7 target mask configuration register.
+- Offset: `0x13c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 7 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 7 event when HW_BARRIER_7_STATUS will match HW_BARRIER_7_TRIG_MASK. |
+
+## HW_BARRIER_0_TRIG
+Cluster hardware barrier 0 trigger command register.
+- Offset: `0x140`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_0_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_1_TRIG
+Cluster hardware barrier 1 trigger command register.
+- Offset: `0x144`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_1_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_2_TRIG
+Cluster hardware barrier 2 trigger command register.
+- Offset: `0x148`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_2_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_3_TRIG
+Cluster hardware barrier 3 trigger command register.
+- Offset: `0x14c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_3_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_4_TRIG
+Cluster hardware barrier 4 trigger command register.
+- Offset: `0x150`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_4_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_5_TRIG
+Cluster hardware barrier 5 trigger command register.
+- Offset: `0x154`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_5_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_6_TRIG
+Cluster hardware barrier 6 trigger command register.
+- Offset: `0x158`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_6_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_7_TRIG
+Cluster hardware barrier 7 trigger command register.
+- Offset: `0x15c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_7_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_0_SELF_TRIG
+Cluster hardware barrier 0 self trigger command register.
+- Offset: `0x160`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_0_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_1_SELF_TRIG
+Cluster hardware barrier 1 self trigger command register.
+- Offset: `0x164`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_1_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_2_SELF_TRIG
+Cluster hardware barrier 2 self trigger command register.
+- Offset: `0x168`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_2_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_3_SELF_TRIG
+Cluster hardware barrier 3 self trigger command register.
+- Offset: `0x16c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_3_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_4_SELF_TRIG
+Cluster hardware barrier 4 self trigger command register.
+- Offset: `0x170`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_4_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_5_SELF_TRIG
+Cluster hardware barrier 5 self trigger command register.
+- Offset: `0x174`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_5_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_6_SELF_TRIG
+Cluster hardware barrier 6 self trigger command register.
+- Offset: `0x178`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_6_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_7_SELF_TRIG
+Cluster hardware barrier 7 self trigger command register.
+- Offset: `0x17c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_7_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_0_TRIG_WAIT
+Cluster hardware barrier 0 trigger and wait command register.
+- Offset: `0x180`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_0[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_0 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_1_TRIG_WAIT
+Cluster hardware barrier 1 trigger and wait command register.
+- Offset: `0x184`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_1[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_1 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_2_TRIG_WAIT
+Cluster hardware barrier 2 trigger and wait command register.
+- Offset: `0x188`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_2[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_2 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_3_TRIG_WAIT
+Cluster hardware barrier 3 trigger and wait command register.
+- Offset: `0x18c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_3[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_3 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_4_TRIG_WAIT
+Cluster hardware barrier 4 trigger and wait command register.
+- Offset: `0x190`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_4[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_4 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_5_TRIG_WAIT
+Cluster hardware barrier 5 trigger and wait command register.
+- Offset: `0x194`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_5[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_5 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_6_TRIG_WAIT
+Cluster hardware barrier 6 trigger and wait command register.
+- Offset: `0x198`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_6[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_6 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_7_TRIG_WAIT
+Cluster hardware barrier 7 trigger and wait command register.
+- Offset: `0x19c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_7[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_7 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_0_TRIG_WAIT_CLEAR
+Cluster hardware barrier 0 trigger, wait and clear command register.
+- Offset: `0x1a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_0_trig_wait_clear--ebm) |
+
+### HW_BARRIER_0_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_0[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_0 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_1_TRIG_WAIT_CLEAR
+Cluster hardware barrier 1 trigger, wait and clear command register.
+- Offset: `0x1a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_1_trig_wait_clear--ebm) |
+
+### HW_BARRIER_1_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_1[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_1 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_2_TRIG_WAIT_CLEAR
+Cluster hardware barrier 2 trigger, wait and clear command register.
+- Offset: `0x1a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_2_trig_wait_clear--ebm) |
+
+### HW_BARRIER_2_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_2[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_2 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_3_TRIG_WAIT_CLEAR
+Cluster hardware barrier 3 trigger, wait and clear command register.
+- Offset: `0x1ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_3_trig_wait_clear--ebm) |
+
+### HW_BARRIER_3_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_3[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_3 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_4_TRIG_WAIT_CLEAR
+Cluster hardware barrier 4 trigger, wait and clear command register.
+- Offset: `0x1b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_4_trig_wait_clear--ebm) |
+
+### HW_BARRIER_4_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_4[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_4 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_5_TRIG_WAIT_CLEAR
+Cluster hardware barrier 5 trigger, wait and clear command register.
+- Offset: `0x1b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_5_trig_wait_clear--ebm) |
+
+### HW_BARRIER_5_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_5[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_5 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_6_TRIG_WAIT_CLEAR
+Cluster hardware barrier 6 trigger, wait and clear command register.
+- Offset: `0x1b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_6_trig_wait_clear--ebm) |
+
+### HW_BARRIER_6_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_6[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_6 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_7_TRIG_WAIT_CLEAR
+Cluster hardware barrier 7 trigger, wait and clear command register.
+- Offset: `0x1bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_7_trig_wait_clear--ebm) |
+
+### HW_BARRIER_7_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_7[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_7 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+
+
+## cluster_ctrl_unit / doc / registers.md
+
+## Summary
+
+| Name                                                                       | Offset   |   Length | Description                                                           |
+|:---------------------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------|
+| cluster_control_unit.[`EOC`](#eoc)                                         | 0x0      |        4 | End Of Computation status register.                                   |
+| cluster_control_unit.[`FETCH_EN`](#fetch_en)                               | 0x4      |        4 | Cluster cores fetch enable configuration register.                    |
+| cluster_control_unit.[`CLOCK_GATE`](#clock_gate)                           | 0x8      |        4 | Cluster clock gate configuration register.                            |
+| cluster_control_unit.[`DBG_RESUME`](#dbg_resume)                           | 0xc      |        4 | Cluster cores debug resume register.                                  |
+| cluster_control_unit.[`DBG_HALT_STATUS`](#dbg_halt_status)                 | 0x10     |        4 | Cluster cores debug halt status register.                             |
+| cluster_control_unit.[`DBG_HALT_MASK`](#dbg_halt_mask)                     | 0x14     |        4 | Cluster cores debug halt mask configuration register.                 |
+| cluster_control_unit.[`BOOT_ADDR0`](#boot_addr0)                           | 0x18     |        4 | Cluster core 0 boot address configuration register.                   |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH0`](#tcdm_arb_policy_ch0)         | 0x1c     |        4 | TCDM arbitration policy ch0 for cluster cores configuration register. |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH1`](#tcdm_arb_policy_ch1)         | 0x20     |        4 | TCDM arbitration policy ch1 for DMA/HWCE configuration register.      |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH0_REP`](#tcdm_arb_policy_ch0_rep) | 0x24     |        4 | Read only duplicate of TCDM_ARB_POLICY_CH0 register                   |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH1_REP`](#tcdm_arb_policy_ch1_rep) | 0x28     |        4 | Read only duplicate of TCDM_ARB_POLICY_CH1 register                   |
+
+## EOC
+End Of Computation status register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "eoc", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                       |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                          |
+|   0    |   rw   |   0x0   | eoc    | End of computation status flag bitfield: - 1'b0: program execution under going - 1'b1: end of computation reached |
+
+## FETCH_EN
+Cluster cores fetch enable configuration register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                     |
+|   7    |   rw   |   0x0   | CORE7  | Core 7 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   6    |   rw   |   0x0   | CORE6  | Core 6 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   5    |   rw   |   0x0   | CORE5  | Core 5 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   4    |   rw   |   0x0   | CORE4  | Core 4 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   3    |   rw   |   0x0   | CORE3  | Core 3 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   2    |   rw   |   0x0   | CORE2  | Core 2 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   1    |   rw   |   0x0   | CORE1  | Core 1 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   0    |   rw   |   0x0   | CORE0  | Core 0 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
+## CLOCK_GATE
+Cluster clock gate configuration register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                 |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                    |
+|   0    |   rw   |   0x0   | EN     | Cluster clock gate configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
+## DBG_RESUME
+Cluster cores debug resume register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                              |
+|   7    |   wo   |   0x0   | CORE7  | Core 7 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 7 |
+|   6    |   wo   |   0x0   | CORE6  | Core 6 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 6 |
+|   5    |   wo   |   0x0   | CORE5  | Core 5 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 5 |
+|   4    |   wo   |   0x0   | CORE4  | Core 4 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 4 |
+|   3    |   wo   |   0x0   | CORE3  | Core 3 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 3 |
+|   2    |   wo   |   0x0   | CORE2  | Core 2 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 2 |
+|   1    |   wo   |   0x0   | CORE1  | Core 1 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 1 |
+|   0    |   wo   |   0x0   | CORE0  | Core 0 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 0 |
+
+## DBG_HALT_STATUS
+Cluster cores debug halt status register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                               |
+|   7    |   ro   |   0x0   | CORE7  | Core 7 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   6    |   ro   |   0x0   | CORE6  | Core 6 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   5    |   ro   |   0x0   | CORE5  | Core 5 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   4    |   ro   |   0x0   | CORE4  | Core 4 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   3    |   ro   |   0x0   | CORE3  | Core 3 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   2    |   ro   |   0x0   | CORE2  | Core 2 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   1    |   ro   |   0x0   | CORE1  | Core 1 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   0    |   ro   |   0x0   | CORE0  | Core 0 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+
+## DBG_HALT_MASK
+Cluster cores debug halt mask configuration register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                  |
+|   7    |   rw   |   0x0   | CORE7  | Core 7 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   6    |   rw   |   0x0   | CORE6  | Core 6 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   5    |   rw   |   0x0   | CORE5  | Core 5 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   4    |   rw   |   0x0   | CORE4  | Core 4 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   3    |   rw   |   0x0   | CORE3  | Core 3 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   2    |   rw   |   0x0   | CORE2  | Core 2 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   1    |   rw   |   0x0   | CORE1  | Core 1 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   0    |   rw   |   0x0   | CORE0  | Core 0 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+
+## BOOT_ADDR0
+Cluster core 0 boot address configuration register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "BA", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------|
+|  31:0  |   rw   |   0x0   | BA     | Cluster core 0 boot address configuration bitfield. |
+
+## TCDM_ARB_POLICY_CH0
+TCDM arbitration policy ch0 for cluster cores configuration register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                    |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                       |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for cluster cores configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
+## TCDM_ARB_POLICY_CH1
+TCDM arbitration policy ch1 for DMA/HWCE configuration register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                  |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for DMA/HWCE configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
+## TCDM_ARB_POLICY_CH0_REP
+Read only duplicate of TCDM_ARB_POLICY_CH0 register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                    |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                       |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for cluster cores configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
+## TCDM_ARB_POLICY_CH1_REP
+Read only duplicate of TCDM_ARB_POLICY_CH1 register
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                  |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for DMA/HWCE configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
+
+
+## cluster_icache_ctrl / doc / registers.md
+
+## Summary
+
+| Name                                                      | Offset   |   Length | Description                                                      |
+|:----------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------|
+| cluster_icache_ctrl.[`ENABLE`](#enable)                   | 0x0      |        4 | Cluster instruction cache unit enable configuration register.    |
+| cluster_icache_ctrl.[`FLUSH`](#flush)                     | 0x4      |        4 | Cluster instruction cache unit flush command register.           |
+| cluster_icache_ctrl.[`L0_FLUSH`](#l0_flush)               | 0x8      |        4 | Cluster level 0 instruction cache unit flush command register.   |
+| cluster_icache_ctrl.[`SEL_FLUSH`](#sel_flush)             | 0xc      |        4 | Cluster instruction cache unit selective flush command register. |
+| cluster_icache_ctrl.[`L1_L15_PREFETCH`](#l1_l15_prefetch) | 0x10     |        4 | Enable L1 and L1.5 prefetch register.                            |
+
+## ENABLE
+Cluster instruction cache unit enable configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                               |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                  |
+|   0    |   rw   |   0x0   | EN     | Cluster instruction cache enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
+## FLUSH
+Cluster instruction cache unit flush command register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:1  |        |         |        | Reserved                                      |
+|   0    |   rw   |   0x0   | FL     | Cluster instruction cache full flush command. |
+
+## L0_FLUSH
+Cluster level 0 instruction cache unit flush command register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L0_FL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                           |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                              |
+|   0    |   rw   |   0x0   | L0_FL  | Cluster level 0 instruction cache full flush command. |
+
+## SEL_FLUSH
+Cluster instruction cache unit selective flush command register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                               |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | ADDR   | Cluster instruction cache selective flush address configuration bitfield. |
+
+## L1_L15_PREFETCH
+Enable L1 and L1.5 prefetch register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                            |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                               |
+|   7    |   rw   |   0x0   | CORE7  | Core 7 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   6    |   rw   |   0x0   | CORE6  | Core 6 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   5    |   rw   |   0x0   | CORE5  | Core 5 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   4    |   rw   |   0x0   | CORE4  | Core 4 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   3    |   rw   |   0x0   | CORE3  | Core 3 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   2    |   rw   |   0x0   | CORE2  | Core 2 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   1    |   rw   |   0x0   | CORE1  | Core 1 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   0    |   rw   |   0x0   | CORE0  | Core 0 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
+
+
+## ethernet / doc / registers.md
+
+## Summary
+
+| Name                              | Offset   |   Length | Description                                                                                |
+|:----------------------------------|:---------|---------:|:-------------------------------------------------------------------------------------------|
+| eth_framing.[`CONFIG0`](#config0) | 0x0      |        4 | Configures the lower 4 bytes of the devices MAC address                                    |
+| eth_framing.[`CONFIG1`](#config1) | 0x4      |        4 | Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface |
+| eth_framing.[`CONFIG2`](#config2) | 0x8      |        4 | The FCS TX status                                                                          |
+| eth_framing.[`CONFIG3`](#config3) | 0xc      |        4 | The FCS RX status                                                                          |
+
+## CONFIG0
+Configures the lower 4 bytes of the devices MAC address
+- Offset: `0x0`
+- Reset default: `0x890702`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "lower_mac_address", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset   | Name              | Description                             |
+|:------:|:------:|:--------:|:------------------|:----------------------------------------|
+|  31:0  |   rw   | 0x890702 | lower_mac_address | Lower 32 bit of the devices MAC address |
+
+## CONFIG1
+Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface
+- Offset: `0x4`
+- Reset default: `0x2301`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "upper_mac_address", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "promiscuous", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdclk", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdio_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdio_oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                             |
+|:------:|:------:|:-------:|:------------------|:----------------------------------------|
+| 31:20  |        |         |                   | Reserved                                |
+|   19   |   rw   |   0x0   | phy_mdio_oe       | MDIO output enable                      |
+|   18   |   rw   |   0x0   | phy_mdio_o        | MDIO output                             |
+|   17   |   rw   |   0x0   | phy_mdclk         | MDIO clock                              |
+|   16   |   rw   |   0x0   | promiscuous       | promiscuous flag                        |
+|  15:0  |   rw   | 0x2301  | upper_mac_address | Upper 16 bit of the devices MAC address |
+
+## CONFIG2
+The FCS TX status
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_fcs_reg", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   ro   |   0x0   | tx_fcs_reg | FCS TX status |
+
+## CONFIG3
+The FCS RX status
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rx_fcs_reg", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   ro   |   0x0   | rx_fcs_reg | FCS RX status |
+
+
+
+## fp_cluster / doc / registers.md
+
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                                                         |
+|:-----------------------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------|
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_0`](#perf_counter_enable)     | 0x0      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_1`](#perf_counter_enable)     | 0x8      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_0`](#hart_select)                     | 0x10     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_1`](#hart_select)                     | 0x18     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_0`](#perf_counter)                   | 0x20     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`PERF_COUNTER_1`](#perf_counter)                   | 0x28     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`CL_CLINT_SET`](#cl_clint_set)                     | 0x30     |        8 | Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt     |
+| spatz_cluster_peripheral.[`CL_CLINT_CLEAR`](#cl_clint_clear)                 | 0x38     |        8 | Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt |
+| spatz_cluster_peripheral.[`HW_BARRIER`](#hw_barrier)                         | 0x40     |        8 | Hardware barrier register. Loads to this register will block until all cores have                   |
+| spatz_cluster_peripheral.[`ICACHE_PREFETCH_ENABLE`](#icache_prefetch_enable) | 0x48     |        8 | Controls prefetching of the instruction cache.                                                      |
+| spatz_cluster_peripheral.[`SPATZ_STATUS`](#spatz_status)                     | 0x50     |        8 | Sets the status of the Spatz cluster.                                                               |
+| spatz_cluster_peripheral.[`CLUSTER_BOOT_CONTROL`](#cluster_boot_control)     | 0x58     |        8 | Controls the cluster boot process.                                                                  |
+
+## PERF_COUNTER_ENABLE
+Enable particular performance counter and start tracking.
+- Reset default: `0x0`
+- Reset mask: `0x7fffffff`
+
+### Instances
+
+| Name                  | Offset   |
+|:----------------------|:---------|
+| PERF_COUNTER_ENABLE_0 | 0x0      |
+| PERF_COUNTER_ENABLE_1 | 0x8      |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CYCLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_ACCESSED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_CONGESTED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU_SEQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_CORE_TO_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_INSTR", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_LOAD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_I", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_ACC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_B_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUSY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_MISS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_PREFETCH", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_DOUBLE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 33}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                         |
+|:------:|:------:|:-------:|:-------------------------------------------------------------|
+| 63:31  |        |         | Reserved                                                     |
+|   30   |   rw   |   0x0   | [ICACHE_STALL](#perf_counter_enable--icache_stall)           |
+|   29   |   rw   |   0x0   | [ICACHE_DOUBLE_HIT](#perf_counter_enable--icache_double_hit) |
+|   28   |   rw   |   0x0   | [ICACHE_PREFETCH](#perf_counter_enable--icache_prefetch)     |
+|   27   |   rw   |   0x0   | [ICACHE_HIT](#perf_counter_enable--icache_hit)               |
+|   26   |   rw   |   0x0   | [ICACHE_MISS](#perf_counter_enable--icache_miss)             |
+|   25   |   rw   |   0x0   | [DMA_BUSY](#perf_counter_enable--dma_busy)                   |
+|   24   |   rw   |   0x0   | [DMA_B_DONE](#perf_counter_enable--dma_b_done)               |
+|   23   |   rw   |   0x0   | [DMA_W_BW](#perf_counter_enable--dma_w_bw)                   |
+|   22   |   rw   |   0x0   | [DMA_W_DONE](#perf_counter_enable--dma_w_done)               |
+|   21   |   rw   |   0x0   | [DMA_R_BW](#perf_counter_enable--dma_r_bw)                   |
+|   20   |   rw   |   0x0   | [DMA_R_DONE](#perf_counter_enable--dma_r_done)               |
+|   19   |   rw   |   0x0   | [DMA_AR_BW](#perf_counter_enable--dma_ar_bw)                 |
+|   18   |   rw   |   0x0   | [DMA_AR_DONE](#perf_counter_enable--dma_ar_done)             |
+|   17   |   rw   |   0x0   | [DMA_AW_BW](#perf_counter_enable--dma_aw_bw)                 |
+|   16   |   rw   |   0x0   | [DMA_AW_DONE](#perf_counter_enable--dma_aw_done)             |
+|   15   |   rw   |   0x0   | [DMA_BUF_R_STALL](#perf_counter_enable--dma_buf_r_stall)     |
+|   14   |   rw   |   0x0   | [DMA_BUF_W_STALL](#perf_counter_enable--dma_buf_w_stall)     |
+|   13   |   rw   |   0x0   | [DMA_W_STALL](#perf_counter_enable--dma_w_stall)             |
+|   12   |   rw   |   0x0   | [DMA_R_STALL](#perf_counter_enable--dma_r_stall)             |
+|   11   |   rw   |   0x0   | [DMA_AR_STALL](#perf_counter_enable--dma_ar_stall)           |
+|   10   |   rw   |   0x0   | [DMA_AW_STALL](#perf_counter_enable--dma_aw_stall)           |
+|   9    |   rw   |   0x0   | [RETIRED_ACC](#perf_counter_enable--retired_acc)             |
+|   8    |   rw   |   0x0   | [RETIRED_I](#perf_counter_enable--retired_i)                 |
+|   7    |   rw   |   0x0   | [RETIRED_LOAD](#perf_counter_enable--retired_load)           |
+|   6    |   rw   |   0x0   | [RETIRED_INSTR](#perf_counter_enable--retired_instr)         |
+|   5    |   rw   |   0x0   | [ISSUE_CORE_TO_FPU](#perf_counter_enable--issue_core_to_fpu) |
+|   4    |   rw   |   0x0   | [ISSUE_FPU_SEQ](#perf_counter_enable--issue_fpu_seq)         |
+|   3    |   rw   |   0x0   | [ISSUE_FPU](#perf_counter_enable--issue_fpu)                 |
+|   2    |   rw   |   0x0   | [TCDM_CONGESTED](#perf_counter_enable--tcdm_congested)       |
+|   1    |   rw   |   0x0   | [TCDM_ACCESSED](#perf_counter_enable--tcdm_accessed)         |
+|   0    |   rw   |   0x0   | [CYCLE](#perf_counter_enable--cycle)                         |
+
+### PERF_COUNTER_ENABLE . ICACHE_STALL
+  Incremented for instruction cache stalls.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_DOUBLE_HIT
+  Incremented for instruction cache double hit.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_PREFETCH
+  Incremented for instruction cache prefetches.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_HIT
+  Incremented for instruction cache hits.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_MISS
+  Incremented for instruction cache misses.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUSY
+  Incremented whenever DMA is busy.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_B_DONE
+  Incremented whenever B handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_BW
+  Whenever W handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_DONE
+  Incremented whenvever W handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_BW
+  Whenever R handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_DONE
+  Incremented whenever R handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_BW
+  Whenever AR handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_DONE
+  Incremented whenever AR handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_BW
+  Whenever AW handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_DONE
+  Incremented whenever AW handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_R_STALL
+  Incremented whenever r_valid = 1 but r_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_W_STALL
+  Incremented whenever w_ready = 1 but w_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_STALL
+  Incremented whenever w_valid = 1 but w_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_STALL
+  Incremented whenever r_ready = 1 but r_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_STALL
+  Incremented whenever ar_valid = 1 but ar_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_STALL
+  Incremented whenever aw_valid = 1 but aw_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_ACC
+  Offloaded instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_I
+  Base instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_LOAD
+  Load instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_INSTR
+  Instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_CORE_TO_FPU
+Incremented whenever the core issues an FPU instruction.
+  _This is a hart-local signal._
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU_SEQ
+  Incremented whenever the FPU Sequencer issues an FPU instruction.
+  Might be non available if the hardware doesn't support FREP.
+  _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU
+  Core operations performed in the FPU. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_CONGESTED
+  Incremented whenever an access twoards the TCDM is made but the arbitration
+  logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+  _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_ACCESSED
+  Increased whenever the TCDM is accessed. Each individual access is tracked,
+  so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+  so it doesn't matter whether the cores or the for example the SSR hardware accesses
+  the TCDM. _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . CYCLE
+Cycle counter. Counts up as long as the cluster is powered.
+
+## HART_SELECT
+Select from which hart in the cluster, starting from `0`,
+   the event should be counted. For each performance counter
+   the cores can be selected individually. If a hart greater
+   than the clusters total hart size is selected the selection
+   will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+   will be selected.
+- Reset default: `0x0`
+- Reset mask: `0x3ff`
+
+### Instances
+
+| Name          | Offset   |
+|:--------------|:---------|
+| HART_SELECT_0 | 0x10     |
+| HART_SELECT_1 | 0x18     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HART_SELECT", "bits": 10, "attr": ["rw"], "rotate": -90}, {"bits": 54}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                   |
+|:------:|:------:|:-------:|:------------|:----------------------------------------------|
+| 63:10  |        |         |             | Reserved                                      |
+|  9:0   |   rw   |   0x0   | HART_SELECT | Select source of per-hart performance counter |
+
+## PERF_COUNTER
+Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+performance metric you would like to track.
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| PERF_COUNTER_0 | 0x20     |
+| PERF_COUNTER_1 | 0x28     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERF_COUNTER", "bits": 48, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description         |
+|:------:|:------:|:-------:|:-------------|:--------------------|
+| 63:48  |        |         |              | Reserved            |
+|  47:0  |   rw   |    x    | PERF_COUNTER | Performance counter |
+
+## CL_CLINT_SET
+Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_SET", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                           |
+|:------:|:------:|:-------:|:-------------|:--------------------------------------|
+| 63:32  |        |         |              | Reserved                              |
+|  31:0  |   wo   |    x    | CL_CLINT_SET | Set cluster-local interrupt of hart i |
+
+## CL_CLINT_CLEAR
+Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_CLEAR", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                             |
+|:------:|:------:|:-------:|:---------------|:----------------------------------------|
+| 63:32  |        |         |                | Reserved                                |
+|  31:0  |   wo   |    x    | CL_CLINT_CLEAR | Clear cluster-local interrupt of hart i |
+
+## HW_BARRIER
+Hardware barrier register. Loads to this register will block until all cores have
+performed the load. At this stage we know that they reached the same point in the control flow,
+i.e., the cores are synchronized.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HW_BARRIER", "bits": 32, "attr": ["ro"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                |
+|:------:|:------:|:-------:|:-----------|:---------------------------|
+| 63:32  |        |         |            | Reserved                   |
+|  31:0  |   ro   |    x    | HW_BARRIER | Hardware barrier register. |
+
+## ICACHE_PREFETCH_ENABLE
+Controls prefetching of the instruction cache.
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ICACHE_PREFETCH_ENABLE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                |
+|:------:|:------:|:-------:|:-----------------------|:---------------------------|
+|  63:1  |        |         |                        | Reserved                   |
+|   0    |   wo   |   0x1   | ICACHE_PREFETCH_ENABLE | Hardware barrier register. |
+
+## SPATZ_STATUS
+Sets the status of the Spatz cluster.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_PROBE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description                                  |
+|:------:|:------:|:-------:|:--------------------|:---------------------------------------------|
+|  63:1  |        |         |                     | Reserved                                     |
+|   0    |   wo   |   0x0   | SPATZ_CLUSTER_PROBE | Indicates the cluster is computing a kernel. |
+
+## CLUSTER_BOOT_CONTROL
+Controls the cluster boot process.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENTRY_POINT", "bits": 32, "attr": ["rw"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                     |
+|:------:|:------:|:-------:|:------------|:--------------------------------|
+| 63:32  |        |         |             | Reserved                        |
+|  31:0  |   rw   |   0x0   | ENTRY_POINT | Post-bootstrapping entry point. |
+
+
+
+## gp_timer1_system_timer / doc / registers.md
+
+## Summary
+
+| Name                               | Offset   |   Length | Description                           |
+|:-----------------------------------|:---------|---------:|:--------------------------------------|
+| timer_unit.[`CFG_LO`](#cfg_lo)     | 0x0      |        4 | Timer Low Configuration register.     |
+| timer_unit.[`CFG_HI`](#cfg_hi)     | 0x4      |        4 | Timer HIGH Configuration register.    |
+| timer_unit.[`CNT_LO`](#cnt_lo)     | 0x8      |        4 | Timer Low counter value register.     |
+| timer_unit.[`CNT_HI`](#cnt_hi)     | 0xc      |        4 | Timer High counter value register.    |
+| timer_unit.[`CMP_LO`](#cmp_lo)     | 0x10     |        4 | Timer Low comparator value register.  |
+| timer_unit.[`CMP_HI`](#cmp_hi)     | 0x14     |        4 | Timer High comparator value register. |
+| timer_unit.[`START_LO`](#start_lo) | 0x18     |        4 | Start Timer Low counting register.    |
+| timer_unit.[`START_HI`](#start_hi) | 0x1c     |        4 | Start Timer High counting register.   |
+| timer_unit.[`RESET_LO`](#reset_lo) | 0x20     |        4 | Reset Timer Low counter register.     |
+| timer_unit.[`RESET_HI`](#reset_hi) | 0x24     |        4 | Reset Timer High counter register.    |
+
+## CFG_LO
+Timer Low Configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x8000ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PVAL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 15}, {"name": "CASC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | CASC   | Timer low  + Timer high 64bit cascaded mode configuration bitfield.                                                                                                                                                                          |
+| 30:16  |        |         |        | Reserved                                                                                                                                                                                                                                     |
+|  15:8  |   rw   |   0x0   | PVAL   | Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL)                                                                                                                                                                          |
+|   7    |   rw   |   0x0   | CCFG   | Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                 |
+|   6    |   rw   |   0x0   | PEN    | Timer low prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   5    |   rw   |   0x0   | ONE_S  | Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low when compare match with CMP_LO occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer low continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   2    |   rw   |   0x0   | IRQEN  | Timer low compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                            |
+|   1    |   rw   |   0x0   | RESET  | Timer low counter reset command bitfield. Cleared after Timer Low reset execution.                                                                                                                                                           |
+|   0    |   rw   |   0x0   | ENABLE | Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                    |
+
+## CFG_HI
+Timer HIGH Configuration register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLKCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                     |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                                                        |
+|   7    |   rw   |   0x0   | CLKCFG | Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                   |
+|   6    |   rw   |   0x0   | PEN    | Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   5    |   rw   |   0x0   | ONE_S  | Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled counting when compare match with CMP_HI occurs. - 1'b1: disable Timer high when compare match with CMP_HI occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer high continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_HI occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_HI occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   2    |   rw   |   0x0   | IRQEN  | Timer high compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                              |
+|   1    |   wo   |   0x0   | RESET  | Timer high counter reset command bitfield. Cleared after Timer high reset execution.                                                                                                                                                            |
+|   0    |   rw   |   0x0   | ENABLE | Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                      |
+
+## CNT_LO
+Timer Low counter value register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                       |
+|:------:|:------:|:-------:|:-------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_lo | Timer Low counter value bitfield. |
+
+## CNT_HI
+Timer High counter value register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_hi | Timer High counter value bitfield. |
+
+## CMP_LO
+Timer Low comparator value register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                          |
+|:------:|:------:|:-------:|:-------|:-------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_lo | Timer Low comparator value bitfield. |
+
+## CMP_HI
+Timer High comparator value register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_hi | Timer High comparator value bitfield. |
+
+## START_LO
+Start Timer Low counting register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                               |
+|   0    |   wo   |   0x0   | strt_lo | Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set. |
+
+## START_HI
+Start Timer High counting register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                             |
+|:------:|:------:|:-------:|:--------|:------------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                                |
+|   0    |   wo   |   0x0   | strt_hi | Timer High start command bitfield. When executed, CFG_HI.ENABLE is set. |
+
+## RESET_LO
+Reset Timer Low counter register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                   |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                      |
+|   0    |   wo   |   0x0   | rst_lo | Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set. |
+
+## RESET_HI
+Reset Timer High counter register.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                       |
+|   0    |   wo   |   0x0   | rst_hi | Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set. |
+
+
+
+## gp_timer2_advanced_timer / doc / registers.md
+
+## Summary
+
+| Name                                              | Offset   |   Length | Description                                              |
+|:--------------------------------------------------|:---------|---------:|:---------------------------------------------------------|
+| apb_adv_timer.[`T0_CMD`](#t0_cmd)                 | 0x0      |        4 | ADV_TIMER0 command register.                             |
+| apb_adv_timer.[`T0_CONFIG`](#t0_config)           | 0x4      |        4 | ADV_TIMER0 configuration register.                       |
+| apb_adv_timer.[`T0_THRESHOLD`](#t0_threshold)     | 0x8      |        4 | ADV_TIMER0 threshold configuration register.             |
+| apb_adv_timer.[`T0_TH_CHANNEL0`](#t0_th_channel0) | 0xc      |        4 | ADV_TIMER0 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL1`](#t0_th_channel1) | 0x10     |        4 | ADV_TIMER0 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL2`](#t0_th_channel2) | 0x14     |        4 | ADV_TIMER0 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL3`](#t0_th_channel3) | 0x18     |        4 | ADV_TIMER0 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T0_COUNTER`](#t0_counter)         | 0x1c     |        4 | ADV_TIMER0 counter register.                             |
+| apb_adv_timer.[`T1_CMD`](#t1_cmd)                 | 0x20     |        4 | ADV_TIMER1 command register.                             |
+| apb_adv_timer.[`T1_CONFIG`](#t1_config)           | 0x24     |        4 | ADV_TIMER1 configuration register.                       |
+| apb_adv_timer.[`T1_THRESHOLD`](#t1_threshold)     | 0x28     |        4 | ADV_TIMER1 threshold configuration register.             |
+| apb_adv_timer.[`T1_TH_CHANNEL0`](#t1_th_channel0) | 0x2c     |        4 | ADV_TIMER1 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL1`](#t1_th_channel1) | 0x30     |        4 | ADV_TIMER1 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL2`](#t1_th_channel2) | 0x34     |        4 | ADV_TIMER1 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL3`](#t1_th_channel3) | 0x38     |        4 | ADV_TIMER1 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T1_COUNTER`](#t1_counter)         | 0x3c     |        4 | ADV_TIMER1 counter register.                             |
+| apb_adv_timer.[`T2_CMD`](#t2_cmd)                 | 0x40     |        4 | ADV_TIMER2 command register.                             |
+| apb_adv_timer.[`T2_CONFIG`](#t2_config)           | 0x44     |        4 | ADV_TIMER2 configuration register.                       |
+| apb_adv_timer.[`T2_THRESHOLD`](#t2_threshold)     | 0x48     |        4 | ADV_TIMER2 threshold configuration register.             |
+| apb_adv_timer.[`T2_TH_CHANNEL0`](#t2_th_channel0) | 0x4c     |        4 | ADV_TIMER2 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL1`](#t2_th_channel1) | 0x50     |        4 | ADV_TIMER2 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL2`](#t2_th_channel2) | 0x54     |        4 | ADV_TIMER2 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL3`](#t2_th_channel3) | 0x58     |        4 | ADV_TIMER2 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T2_COUNTER`](#t2_counter)         | 0x5c     |        4 | ADV_TIMER2 counter register.                             |
+| apb_adv_timer.[`T3_CMD`](#t3_cmd)                 | 0x60     |        4 | ADV_TIMER3 command register.                             |
+| apb_adv_timer.[`T3_CONFIG`](#t3_config)           | 0x64     |        4 | ADV_TIMER3 configuration register.                       |
+| apb_adv_timer.[`T3_THRESHOLD`](#t3_threshold)     | 0x68     |        4 | ADV_TIMER3 threshold configuration register.             |
+| apb_adv_timer.[`T3_TH_CHANNEL0`](#t3_th_channel0) | 0x6c     |        4 | ADV_TIMER3 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL1`](#t3_th_channel1) | 0x70     |        4 | ADV_TIMER3 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL2`](#t3_th_channel2) | 0x74     |        4 | ADV_TIMER3 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL3`](#t3_th_channel3) | 0x78     |        4 | ADV_TIMER3 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T3_COUNTER`](#t3_counter)         | 0x7c     |        4 | ADV_TIMER3 counter register.                             |
+| apb_adv_timer.[`EVENT_CFG`](#event_cfg)           | 0x80     |        4 | ADV_TIMERS events configuration register.                |
+| apb_adv_timer.[`CG`](#cg)                         | 0x84     |        4 | ADV_TIMERS channels clock gating configuration register. |
+
+## T0_CMD
+ADV_TIMER0 command register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RFU", "bits": 27, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |   wo   |   0x0   | RFU    | ?                                   |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER0 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER0 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER0 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER0 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER0 start command bitfield.  |
+
+## T0_CONFIG
+ADV_TIMER0 configuration register.
+- Offset: `0x4`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t0_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t0_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t0_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t0_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t0_config--insel)         |
+
+### T0_CONFIG . PRESC
+ADV_TIMER0 prescaler value configuration bitfield.
+
+### T0_CONFIG . UPDOWNSEL
+ADV_TIMER0 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.	
+
+### T0_CONFIG . CLKSEL
+ADV_TIMER0 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T0_CONFIG . MODE
+ADV_TIMER0 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T0_CONFIG . INSEL
+ADV_TIMER0 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T0_THRESHOLD
+ADV_TIMER0 threshold configuration register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. |
+
+## T0_TH_CHANNEL0
+ADV_TIMER0 channel 0 threshold configuration register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel0--th)     |
+
+### T0_TH_CHANNEL0 . MODE
+ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL0 . TH
+ADV_TIMER0 channel 0 threshold configuration bitfield.
+
+## T0_TH_CHANNEL1
+ADV_TIMER0 channel 1 threshold configuration register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel1--th)     |
+
+### T0_TH_CHANNEL1 . MODE
+ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL1 . TH
+ADV_TIMER0 channel 1 threshold configuration bitfield.
+
+## T0_TH_CHANNEL2
+ADV_TIMER0 channel 2 threshold configuration register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel2--th)     |
+
+### T0_TH_CHANNEL2 . MODE
+ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL2 . TH
+ADV_TIMER0 channel 2 threshold configuration bitfield.
+
+## T0_TH_CHANNEL3
+ADV_TIMER0 channel 3 threshold configuration register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel3--th)     |
+
+### T0_TH_CHANNEL3 . MODE
+ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL3 . TH
+ADV_TIMER0 channel 3 threshold configuration bitfield.
+
+## T0_COUNTER
+ADV_TIMER0 counter register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER0 counter value. |
+
+## T1_CMD
+ADV_TIMER1 command register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER1 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER1 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER1 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER1 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER1 start command bitfield.  |
+
+## T1_CONFIG
+ADV_TIMER1 configuration register.
+- Offset: `0x24`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t1_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t1_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t1_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t1_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t1_config--insel)         |
+
+### T1_CONFIG . PRESC
+ADV_TIMER1 prescaler value configuration bitfield.
+
+### T1_CONFIG . UPDOWNSEL
+ADV_TIMER1 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T1_CONFIG . CLKSEL
+ADV_TIMER1 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T1_CONFIG . MODE
+ADV_TIMER1 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T1_CONFIG . INSEL
+ADV_TIMER1 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T1_THRESHOLD
+ADV_TIMER1 threshold configuration register.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value. |
+
+## T1_TH_CHANNEL0
+ADV_TIMER1 channel 0 threshold configuration register.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel0--th)     |
+
+### T1_TH_CHANNEL0 . MODE
+ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL0 . TH
+ADV_TIMER1 channel 0 threshold configuration bitfield.
+
+## T1_TH_CHANNEL1
+ADV_TIMER1 channel 1 threshold configuration register.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel1--th)     |
+
+### T1_TH_CHANNEL1 . MODE
+ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL1 . TH
+ADV_TIMER1 channel 1 threshold configuration bitfield.
+
+## T1_TH_CHANNEL2
+ADV_TIMER1 channel 2 threshold configuration register.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel2--th)     |
+
+### T1_TH_CHANNEL2 . MODE
+ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL2 . TH
+ADV_TIMER1 channel 2 threshold configuration bitfield.
+
+## T1_TH_CHANNEL3
+ADV_TIMER1 channel 3 threshold configuration register.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel3--th)     |
+
+### T1_TH_CHANNEL3 . MODE
+ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL3 . TH
+ADV_TIMER1 channel 3 threshold configuration bitfield.
+
+## T1_COUNTER
+ADV_TIMER1 counter register.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER1 counter value. |
+
+## T2_CMD
+ADV_TIMER2 command register.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER2 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER2 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER2 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER2 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER2 start command bitfield.  |
+
+## T2_CONFIG
+ADV_TIMER2 configuration register.
+- Offset: `0x44`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t2_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t2_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t2_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t2_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t2_config--insel)         |
+
+### T2_CONFIG . PRESC
+ADV_TIMER2 prescaler value configuration bitfield.
+
+### T2_CONFIG . UPDOWNSEL
+ADV_TIMER2 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T2_CONFIG . CLKSEL
+ADV_TIMER2 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T2_CONFIG . MODE
+ADV_TIMER2 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T2_CONFIG . INSEL
+ADV_TIMER2 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T2_THRESHOLD
+ADV_TIMER2 threshold configuration register.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value. |
+
+## T2_TH_CHANNEL0
+ADV_TIMER2 channel 0 threshold configuration register.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel0--th)     |
+
+### T2_TH_CHANNEL0 . MODE
+ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL0 . TH
+ADV_TIMER2 channel 0 threshold configuration bitfield.
+
+## T2_TH_CHANNEL1
+ADV_TIMER2 channel 1 threshold configuration register.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel1--th)     |
+
+### T2_TH_CHANNEL1 . MODE
+ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL1 . TH
+ADV_TIMER2 channel 1 threshold configuration bitfield.
+
+## T2_TH_CHANNEL2
+ADV_TIMER2 channel 2 threshold configuration register.
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel2--th)     |
+
+### T2_TH_CHANNEL2 . MODE
+ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL2 . TH
+ADV_TIMER2 channel 2 threshold configuration bitfield.
+
+## T2_TH_CHANNEL3
+ADV_TIMER2 channel 3 threshold configuration register.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel3--th)     |
+
+### T2_TH_CHANNEL3 . MODE
+ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL3 . TH
+ADV_TIMER2 channel 3 threshold configuration bitfield.
+
+## T2_COUNTER
+ADV_TIMER2 counter register.
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER2 counter value. |
+
+## T3_CMD
+ADV_TIMER3 command register.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER3 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER3 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER3 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER3 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER3 start command bitfield.  |
+
+## T3_CONFIG
+ADV_TIMER3 configuration register.
+- Offset: `0x64`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t3_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t3_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t3_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t3_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t3_config--insel)         |
+
+### T3_CONFIG . PRESC
+ADV_TIMER3 prescaler value configuration bitfield.
+
+### T3_CONFIG . UPDOWNSEL
+ADV_TIMER3 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T3_CONFIG . CLKSEL
+ADV_TIMER3 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T3_CONFIG . MODE
+ADV_TIMER3 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T3_CONFIG . INSEL
+ADV_TIMER3 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T3_THRESHOLD
+ADV_TIMER3 threshold configuration register.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value. |
+
+## T3_TH_CHANNEL0
+ADV_TIMER3 channel 0 threshold configuration register.
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel0--th)     |
+
+### T3_TH_CHANNEL0 . MODE
+ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL0 . TH
+ADV_TIMER3 channel 0 threshold configuration bitfield.
+
+## T3_TH_CHANNEL1
+ADV_TIMER3 channel 1 threshold configuration register.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel1--th)     |
+
+### T3_TH_CHANNEL1 . MODE
+ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL1 . TH
+ADV_TIMER3 channel 1 threshold configuration bitfield.
+
+## T3_TH_CHANNEL2
+ADV_TIMER3 channel 2 threshold configuration register.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel2--th)     |
+
+### T3_TH_CHANNEL2 . MODE
+ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL2 . TH
+ADV_TIMER3 channel 2 threshold configuration bitfield.
+
+## T3_TH_CHANNEL3
+ADV_TIMER3 channel 3 threshold configuration register.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel3--th)     |
+
+### T3_TH_CHANNEL3 . MODE
+ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL3 . TH
+ADV_TIMER3 channel 3 threshold configuration bitfield.
+
+## T3_COUNTER
+ADV_TIMER3 counter register.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER3 counter value. |
+
+## EVENT_CFG
+ADV_TIMERS events configuration register.
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SEL0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL2", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL3", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     |
+|:------:|:------:|:-------:|:-------------------------|
+| 31:20  |        |         | Reserved                 |
+| 19:16  |   rw   |   0x0   | [ENA](#event_cfg--ena)   |
+| 15:12  |   rw   |   0x0   | [SEL3](#event_cfg--sel3) |
+|  11:8  |   rw   |   0x0   | [SEL2](#event_cfg--sel2) |
+|  7:4   |   rw   |   0x0   | [SEL1](#event_cfg--sel1) |
+|  3:0   |   rw   |   0x0   | [SEL0](#event_cfg--sel0) |
+
+### EVENT_CFG . ENA
+ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation.
+
+### EVENT_CFG . SEL3
+ADV_TIMER output event 3 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL2
+ADV_TIMER output event 2 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL1
+ADV_TIMER output event 1 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL0
+ADV_TIMER output event 0 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+## CG
+ADV_TIMERS channels clock gating configuration register.
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                      |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------|
+|  31:4  |        |         |        | Reserved                                                                                                         |
+|  3:0   |   rw   |   0x0   | ENA    | ADV_TIMER clock gating configuration bitfield. - ENA[i]=0: clock gate ADV_TIMERi. - ENA[i]=1: enable ADV_TIMERi. |
+
+
+
+## gpio / doc / registers.md
+
+## Summary
+
+| Name                                                 | Offset   |   Length | Description                                   |
+|:-----------------------------------------------------|:---------|---------:|:----------------------------------------------|
+| gpio.[`INTR_STATE`](#intr_state)                     | 0x0      |        4 | Interrupt State Register                      |
+| gpio.[`INTR_ENABLE`](#intr_enable)                   | 0x4      |        4 | Interrupt Enable Register                     |
+| gpio.[`INTR_TEST`](#intr_test)                       | 0x8      |        4 | Interrupt Test Register                       |
+| gpio.[`ALERT_TEST`](#alert_test)                     | 0xc      |        4 | Alert Test Register                           |
+| gpio.[`DATA_IN`](#data_in)                           | 0x10     |        4 | GPIO Input data read value                    |
+| gpio.[`DIRECT_OUT`](#direct_out)                     | 0x14     |        4 | GPIO direct output data write value           |
+| gpio.[`MASKED_OUT_LOWER`](#masked_out_lower)         | 0x18     |        4 | GPIO write data lower with mask.              |
+| gpio.[`MASKED_OUT_UPPER`](#masked_out_upper)         | 0x1c     |        4 | GPIO write data upper with mask.              |
+| gpio.[`DIRECT_OE`](#direct_oe)                       | 0x20     |        4 | GPIO Output Enable.                           |
+| gpio.[`MASKED_OE_LOWER`](#masked_oe_lower)           | 0x24     |        4 | GPIO write Output Enable lower with mask.     |
+| gpio.[`MASKED_OE_UPPER`](#masked_oe_upper)           | 0x28     |        4 | GPIO write Output Enable upper with mask.     |
+| gpio.[`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising)   | 0x2c     |        4 | GPIO interrupt enable for GPIO, rising edge.  |
+| gpio.[`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling) | 0x30     |        4 | GPIO interrupt enable for GPIO, falling edge. |
+| gpio.[`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh) | 0x34     |        4 | GPIO interrupt enable for GPIO, level high.   |
+| gpio.[`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow)   | 0x38     |        4 | GPIO interrupt enable for GPIO, level low.    |
+| gpio.[`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter) | 0x3c     |        4 | filter enable for GPIO input bits.            |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw1c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                 |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------|
+|  31:0  |  rw1c  |   0x0   | gpio   | raised if any of GPIO pin detects configured interrupt mode |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | gpio   | Enable interrupt when corresponding bit in [`INTR_STATE.gpio`](#intr_state) is set. |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | gpio   | Write 1 to force corresponding bit in [`INTR_STATE.gpio`](#intr_state) to 1. |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## DATA_IN
+GPIO Input data read value
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   ro   |    x    | DATA_IN |               |
+
+## DIRECT_OUT
+GPIO direct output data write value
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DIRECT_OUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   rw   |    x    | DIRECT_OUT |               |
+
+## MASKED_OUT_LOWER
+GPIO write data lower with mask.
+
+Masked write for DATA_OUT[15:0].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OUT[15:0] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OUT[15:0].
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                     |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------|
+| 31:16  |   wo   |    x    | mask   | Write data mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15 |
+|  15:0  |   rw   |    x    | data   | Write data value[15:0]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1    |
+
+## MASKED_OUT_UPPER
+GPIO write data upper with mask.
+
+Masked write for DATA_OUT[31:16].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OUT[31:16] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OUT[31:16].
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                       |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------|
+| 31:16  |   wo   |    x    | mask   | Write data mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31 |
+|  15:0  |   rw   |    x    | data   | Write data value[31:16]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1     |
+
+## DIRECT_OE
+GPIO Output Enable.
+
+Setting direct_oe[i] to 1 enables output mode for GPIO[i]
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DIRECT_OE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:0  |   rw   |    x    | DIRECT_OE |               |
+
+## MASKED_OE_LOWER
+GPIO write Output Enable lower with mask.
+
+Masked write for DATA_OE[15:0], the register that controls
+output mode for GPIO pins [15:0].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OE[15:0] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OE[15:0].
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------|
+| 31:16  |   rw   |    x    | mask   | Write OE mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15 |
+|  15:0  |   rw   |    x    | data   | Write OE value[15:0]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1    |
+
+## MASKED_OE_UPPER
+GPIO write Output Enable upper with mask.
+
+Masked write for DATA_OE[31:16], the register that controls
+output mode for GPIO pins [31:16].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OE[31:16] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OE[31:16].
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                    |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------|
+| 31:16  |   rw   |    x    | mask   | Write OE mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31 |
+|  15:0  |   rw   |    x    | data   | Write OE value[31:16]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1     |
+
+## INTR_CTRL_EN_RISING
+GPIO interrupt enable for GPIO, rising edge.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising)[i]
+enables rising-edge interrupt detection on GPIO[i].
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_RISING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_RISING |               |
+
+## INTR_CTRL_EN_FALLING
+GPIO interrupt enable for GPIO, falling edge.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling)[i]
+enables falling-edge interrupt detection on GPIO[i].
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_FALLING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_FALLING |               |
+
+## INTR_CTRL_EN_LVLHIGH
+GPIO interrupt enable for GPIO, level high.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh)[i]
+enables level high interrupt detection on GPIO[i].
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_LVLHIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_LVLHIGH |               |
+
+## INTR_CTRL_EN_LVLLOW
+GPIO interrupt enable for GPIO, level low.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow)[i]
+enables level low interrupt detection on GPIO[i].
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_LVLLOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_LVLLOW |               |
+
+## CTRL_EN_INPUT_FILTER
+filter enable for GPIO input bits.
+
+If [`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter)[i] is true, a value of input bit [i]
+must be stable for 16 cycles before transitioning.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CTRL_EN_INPUT_FILTER", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | CTRL_EN_INPUT_FILTER |               |
+
+
+
+## hyperbus / doc / registers.md
+
+## Summary
+
+| Name                                                       | Offset   |   Length | Description                                 |
+|:-----------------------------------------------------------|:---------|---------:|:--------------------------------------------|
+| hyperbus.[`T_LATENCY_ACCESS`](#t_latency_access)           | 0x0      |        4 | Initial latency                             |
+| hyperbus.[`EN_LATENCY_ADDITIONAL`](#en_latency_additional) | 0x4      |        4 | Force 2x Latency count                      |
+| hyperbus.[`T_BURST_MAX`](#t_burst_max)                     | 0x8      |        4 | Max burst Length between two memory refresh |
+| hyperbus.[`T_READ_WRITE_RECOVERY`](#t_read_write_recovery) | 0xc      |        4 | Idle time between transactions              |
+| hyperbus.[`T_RX_CLOCK_DELAY`](#t_rx_clock_delay)           | 0x10     |        4 | RX Delay Line                               |
+| hyperbus.[`T_TX_CLOCK_DELAY`](#t_tx_clock_delay)           | 0x14     |        4 | TX Delay Line                               |
+| hyperbus.[`ADDRESS_MASK_MSB`](#address_mask_msb)           | 0x18     |        4 | Address Mask MSB                            |
+| hyperbus.[`ADDRESS_SPACE`](#address_space)                 | 0x1c     |        4 | L2 sleep configuration register             |
+| hyperbus.[`PHYS_IN_USE`](#phys_in_use)                     | 0x20     |        4 | Number of PHYs on use                       |
+| hyperbus.[`WHICH_PHY`](#which_phy)                         | 0x24     |        4 | PHY used in single PHY mode                 |
+| hyperbus.[`CS0_BASE`](#cs0_base)                           | 0x28     |        4 | CS0 Base address range                      |
+| hyperbus.[`CS0_END`](#cs0_end)                             | 0x2c     |        4 | CS0 End address range                       |
+| hyperbus.[`CS1_BASE`](#cs1_base)                           | 0x30     |        4 | CS1 Base address range                      |
+| hyperbus.[`CS1_END`](#cs1_end)                             | 0x34     |        4 | CS1 End address range                       |
+| hyperbus.[`CS2_BASE`](#cs2_base)                           | 0x38     |        4 | CS2 Base address range                      |
+| hyperbus.[`CS2_END`](#cs2_end)                             | 0x3c     |        4 | CS2 End address range                       |
+| hyperbus.[`CS3_BASE`](#cs3_base)                           | 0x40     |        4 | CS3 Base address range                      |
+| hyperbus.[`CS3_END`](#cs3_end)                             | 0x44     |        4 | CS3 End address range                       |
+
+## T_LATENCY_ACCESS
+Initial latency
+- Offset: `0x0`
+- Reset default: `0x6`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_LATENCY_ACCESS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description     |
+|:------:|:------:|:-------:|:-----------------|:----------------|
+|  31:4  |        |         |                  | Reserved        |
+|  3:0   |   rw   |   0x6   | T_LATENCY_ACCESS | Initial latency |
+
+## EN_LATENCY_ADDITIONAL
+Force 2x Latency count
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EN_LATENCY_ADDITIONAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description            |
+|:------:|:------:|:-------:|:----------------------|:-----------------------|
+|  31:1  |        |         |                       | Reserved               |
+|   0    |   rw   |   0x0   | EN_LATENCY_ADDITIONAL | Force 2x Latency count |
+
+## T_BURST_MAX
+Max burst Length between two memory refresh
+- Offset: `0x8`
+- Reset default: `0x15e`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_BURST_MAX", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                 |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------|
+| 31:16  |        |         |             | Reserved                                    |
+|  15:0  |   rw   |  0x15e  | T_BURST_MAX | Max burst Length between two memory refresh |
+
+## T_READ_WRITE_RECOVERY
+Idle time between transactions
+- Offset: `0xc`
+- Reset default: `0x6`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_READ_WRITE_RECOVERY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                    |
+|:------:|:------:|:-------:|:----------------------|:-------------------------------|
+|  31:4  |        |         |                       | Reserved                       |
+|  3:0   |   rw   |   0x6   | T_READ_WRITE_RECOVERY | Idle time between transactions |
+
+## T_RX_CLOCK_DELAY
+RX Delay Line
+- Offset: `0x10`
+- Reset default: `0x8`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_RX_CLOCK_DELAY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:4  |        |         |                  | Reserved      |
+|  3:0   |   rw   |   0x8   | T_RX_CLOCK_DELAY | RX Delay Line |
+
+## T_TX_CLOCK_DELAY
+TX Delay Line
+- Offset: `0x14`
+- Reset default: `0x8`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_TX_CLOCK_DELAY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:4  |        |         |                  | Reserved      |
+|  3:0   |   rw   |   0x8   | T_TX_CLOCK_DELAY | TX Delay Line |
+
+## ADDRESS_MASK_MSB
+Address Mask MSB
+- Offset: `0x18`
+- Reset default: `0x19`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS_MASK_MSB", "bits": 19, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description      |
+|:------:|:------:|:-------:|:-----------------|:-----------------|
+| 31:19  |        |         |                  | Reserved         |
+|  18:0  |   rw   |  0x19   | ADDRESS_MASK_MSB | Address Mask MSB |
+
+## ADDRESS_SPACE
+L2 sleep configuration register
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS_SPACE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                     |
+|:------:|:------:|:-------:|:--------------|:--------------------------------|
+|  31:1  |        |         |               | Reserved                        |
+|   0    |   rw   |   0x0   | ADDRESS_SPACE | L2 sleep configuration register |
+
+## PHYS_IN_USE
+Number of PHYs on use
+- Offset: `0x20`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PHYS_IN_USE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                                   |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                                      |
+|   0    |   rw   |   0x1   | PHYS_IN_USE | Number of PHYs on use: - 1'b0: Uses 1 PHY - 1'b1: Uses 2 PHYs |
+
+## WHICH_PHY
+PHY used in single PHY mode
+- Offset: `0x24`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "WHICH_PHY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                              |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------------------|
+|  31:1  |        |         |           | Reserved                                                                 |
+|   0    |   rw   |   0x1   | WHICH_PHY | PHY used in single PHY mode: - 1'b0: PHY 0 is used - 1'b1: PHY 1 is used |
+
+## CS0_BASE
+CS0 Base address range
+- Offset: `0x28`
+- Reset default: `0x80000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS0_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x80000000 | CS0_BASE | CS0 Base address range |
+
+## CS0_END
+CS0 End address range
+- Offset: `0x2c`
+- Reset default: `0x81000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS0_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x81000000 | CS0_END | CS0 End address range |
+
+## CS1_BASE
+CS1 Base address range
+- Offset: `0x30`
+- Reset default: `0x81000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS1_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x81000000 | CS1_BASE | CS1 Base address range |
+
+## CS1_END
+CS1 End address range
+- Offset: `0x34`
+- Reset default: `0x82000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS1_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x82000000 | CS1_END | CS1 End address range |
+
+## CS2_BASE
+CS2 Base address range
+- Offset: `0x38`
+- Reset default: `0x82000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS2_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x82000000 | CS2_BASE | CS2 Base address range |
+
+## CS2_END
+CS2 End address range
+- Offset: `0x3c`
+- Reset default: `0x83000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS2_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x83000000 | CS2_END | CS2 End address range |
+
+## CS3_BASE
+CS3 Base address range
+- Offset: `0x40`
+- Reset default: `0x83000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS3_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x83000000 | CS3_BASE | CS3 Base address range |
+
+## CS3_END
+CS3 End address range
+- Offset: `0x44`
+- Reset default: `0x84000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS3_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x84000000 | CS3_END | CS3 End address range |
+
+
+
+## i2c / doc / registers.md
+
+## Summary
+
+| Name                                                          | Offset   |   Length | Description                                                                                               |
+|:--------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------------|
+| i2c.[`INTR_STATE`](#intr_state)                               | 0x0      |        4 | Interrupt State Register                                                                                  |
+| i2c.[`INTR_ENABLE`](#intr_enable)                             | 0x4      |        4 | Interrupt Enable Register                                                                                 |
+| i2c.[`INTR_TEST`](#intr_test)                                 | 0x8      |        4 | Interrupt Test Register                                                                                   |
+| i2c.[`ALERT_TEST`](#alert_test)                               | 0xc      |        4 | Alert Test Register                                                                                       |
+| i2c.[`CTRL`](#ctrl)                                           | 0x10     |        4 | I2C Control Register                                                                                      |
+| i2c.[`STATUS`](#status)                                       | 0x14     |        4 | I2C Live Status Register for Host and Target modes                                                        |
+| i2c.[`RDATA`](#rdata)                                         | 0x18     |        4 | I2C Read Data                                                                                             |
+| i2c.[`FDATA`](#fdata)                                         | 0x1c     |        4 | I2C Host Format Data                                                                                      |
+| i2c.[`FIFO_CTRL`](#fifo_ctrl)                                 | 0x20     |        4 | I2C FIFO control register                                                                                 |
+| i2c.[`HOST_FIFO_CONFIG`](#host_fifo_config)                   | 0x24     |        4 | Host mode FIFO configuration                                                                              |
+| i2c.[`TARGET_FIFO_CONFIG`](#target_fifo_config)               | 0x28     |        4 | Target mode FIFO configuration                                                                            |
+| i2c.[`HOST_FIFO_STATUS`](#host_fifo_status)                   | 0x2c     |        4 | Host mode FIFO status register                                                                            |
+| i2c.[`TARGET_FIFO_STATUS`](#target_fifo_status)               | 0x30     |        4 | Target mode FIFO status register                                                                          |
+| i2c.[`OVRD`](#ovrd)                                           | 0x34     |        4 | I2C Override Control Register                                                                             |
+| i2c.[`VAL`](#val)                                             | 0x38     |        4 | Oversampled RX values                                                                                     |
+| i2c.[`TIMING0`](#timing0)                                     | 0x3c     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING1`](#timing1)                                     | 0x40     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING2`](#timing2)                                     | 0x44     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING3`](#timing3)                                     | 0x48     |        4 | Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).                      |
+| i2c.[`TIMING4`](#timing4)                                     | 0x4c     |        4 | Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).                      |
+| i2c.[`TIMEOUT_CTRL`](#timeout_ctrl)                           | 0x50     |        4 | I2C clock stretching and bus timeout control.                                                             |
+| i2c.[`TARGET_ID`](#target_id)                                 | 0x54     |        4 | I2C target address and mask pairs                                                                         |
+| i2c.[`ACQDATA`](#acqdata)                                     | 0x58     |        4 | I2C target acquired data                                                                                  |
+| i2c.[`TXDATA`](#txdata)                                       | 0x5c     |        4 | I2C target transmit data                                                                                  |
+| i2c.[`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl)                 | 0x60     |        4 | I2C host clock generation timeout value (in units of input clock frequency).                              |
+| i2c.[`TARGET_TIMEOUT_CTRL`](#target_timeout_ctrl)             | 0x64     |        4 | I2C target internal stretching timeout control.                                                           |
+| i2c.[`TARGET_NACK_COUNT`](#target_nack_count)                 | 0x68     |        4 | Number of times the I2C target has NACK'ed a new transaction since the last read of this register.        |
+| i2c.[`TARGET_ACK_CTRL`](#target_ack_ctrl)                     | 0x6c     |        4 | Controls for mid-transfer (N)ACK phase handling                                                           |
+| i2c.[`ACQ_FIFO_NEXT_DATA`](#acq_fifo_next_data)               | 0x70     |        4 | The data byte pending to be written to the ACQ FIFO.                                                      |
+| i2c.[`HOST_NACK_HANDLER_TIMEOUT`](#host_nack_handler_timeout) | 0x74     |        4 | Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.            |
+| i2c.[`CONTROLLER_EVENTS`](#controller_events)                 | 0x78     |        4 | Latched events that explain why the controller halted.                                                    |
+| i2c.[`TARGET_EVENTS`](#target_events)                         | 0x7c     |        4 | Latched events that can cause the target module to stretch the clock at the beginning of a read transfer. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                                                                                                                                                                                                                                               |
+|   14   |  rw1c  |   0x0   | host_timeout     | target mode interrupt: raised if the host stops sending the clock during an ongoing transaction.                                                                                                                                                                                       |
+|   13   |  rw1c  |   0x0   | unexp_stop       | target mode interrupt: raised if STOP is received without a preceding NACK during an external host read.                                                                                                                                                                               |
+|   12   |   ro   |   0x0   | acq_stretch      | target mode interrupt: raised if the target is stretching clocks due to full ACQ FIFO or zero count in [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) (if enabled). This is a level status interrupt.                                                                                    |
+|   11   |   ro   |   0x0   | tx_threshold     | target mode interrupt: asserted whilst the TX FIFO level is below the low threshold. This is a level status interrupt.                                                                                                                                                                 |
+|   10   |   ro   |   0x0   | tx_stretch       | target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.                                                                                                                                                                 |
+|   9    |  rw1c  |   0x0   | cmd_complete     | host and target mode interrupt. In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.                                                                   |
+|   8    |  rw1c  |   0x0   | sda_unstable     | host mode interrupt: raised if the target does not assert a constant value of SDA during transmission.                                                                                                                                                                                 |
+|   7    |  rw1c  |   0x0   | stretch_timeout  | host mode interrupt: raised if target stretches the clock beyond the allowed timeout period                                                                                                                                                                                            |
+|   6    |  rw1c  |   0x0   | sda_interference | host mode interrupt: raised if the SDA line goes low when host is trying to assert high                                                                                                                                                                                                |
+|   5    |  rw1c  |   0x0   | scl_interference | host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).                                                                                                                                                                                 |
+|   4    |   ro   |   0x0   | controller_halt  | host mode interrupt: raised if the controller FSM is halted, such as on an unexpected NACK or lost arbitration. Check [`CONTROLLER_EVENTS`](#controller_events) for the reason. The interrupt will be released when the bits in [`CONTROLLER_EVENTS`](#controller_events) are cleared. |
+|   3    |  rw1c  |   0x0   | rx_overflow      | host mode interrupt: raised if the RX FIFO has overflowed.                                                                                                                                                                                                                             |
+|   2    |   ro   |   0x0   | acq_threshold    | target mode interrupt: asserted whilst the ACQ FIFO level is above the high threshold. This is a level status interrupt.                                                                                                                                                               |
+|   1    |   ro   |   0x0   | rx_threshold     | host mode interrupt: asserted whilst the RX FIFO level is above the high threshold. This is a level status interrupt.                                                                                                                                                                  |
+|   0    |   ro   |   0x0   | fmt_threshold    | host mode interrupt: asserted whilst the FMT FIFO level is below the low threshold. This is a level status interrupt.                                                                                                                                                                  |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                                   |
+|   14   |   rw   |   0x0   | host_timeout     | Enable interrupt when [`INTR_STATE.host_timeout`](#intr_state) is set.     |
+|   13   |   rw   |   0x0   | unexp_stop       | Enable interrupt when [`INTR_STATE.unexp_stop`](#intr_state) is set.       |
+|   12   |   rw   |   0x0   | acq_stretch      | Enable interrupt when [`INTR_STATE.acq_stretch`](#intr_state) is set.      |
+|   11   |   rw   |   0x0   | tx_threshold     | Enable interrupt when [`INTR_STATE.tx_threshold`](#intr_state) is set.     |
+|   10   |   rw   |   0x0   | tx_stretch       | Enable interrupt when [`INTR_STATE.tx_stretch`](#intr_state) is set.       |
+|   9    |   rw   |   0x0   | cmd_complete     | Enable interrupt when [`INTR_STATE.cmd_complete`](#intr_state) is set.     |
+|   8    |   rw   |   0x0   | sda_unstable     | Enable interrupt when [`INTR_STATE.sda_unstable`](#intr_state) is set.     |
+|   7    |   rw   |   0x0   | stretch_timeout  | Enable interrupt when [`INTR_STATE.stretch_timeout`](#intr_state) is set.  |
+|   6    |   rw   |   0x0   | sda_interference | Enable interrupt when [`INTR_STATE.sda_interference`](#intr_state) is set. |
+|   5    |   rw   |   0x0   | scl_interference | Enable interrupt when [`INTR_STATE.scl_interference`](#intr_state) is set. |
+|   4    |   rw   |   0x0   | controller_halt  | Enable interrupt when [`INTR_STATE.controller_halt`](#intr_state) is set.  |
+|   3    |   rw   |   0x0   | rx_overflow      | Enable interrupt when [`INTR_STATE.rx_overflow`](#intr_state) is set.      |
+|   2    |   rw   |   0x0   | acq_threshold    | Enable interrupt when [`INTR_STATE.acq_threshold`](#intr_state) is set.    |
+|   1    |   rw   |   0x0   | rx_threshold     | Enable interrupt when [`INTR_STATE.rx_threshold`](#intr_state) is set.     |
+|   0    |   rw   |   0x0   | fmt_threshold    | Enable interrupt when [`INTR_STATE.fmt_threshold`](#intr_state) is set.    |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                         |
+|:------:|:------:|:-------:|:-----------------|:--------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                            |
+|   14   |   wo   |   0x0   | host_timeout     | Write 1 to force [`INTR_STATE.host_timeout`](#intr_state) to 1.     |
+|   13   |   wo   |   0x0   | unexp_stop       | Write 1 to force [`INTR_STATE.unexp_stop`](#intr_state) to 1.       |
+|   12   |   wo   |   0x0   | acq_stretch      | Write 1 to force [`INTR_STATE.acq_stretch`](#intr_state) to 1.      |
+|   11   |   wo   |   0x0   | tx_threshold     | Write 1 to force [`INTR_STATE.tx_threshold`](#intr_state) to 1.     |
+|   10   |   wo   |   0x0   | tx_stretch       | Write 1 to force [`INTR_STATE.tx_stretch`](#intr_state) to 1.       |
+|   9    |   wo   |   0x0   | cmd_complete     | Write 1 to force [`INTR_STATE.cmd_complete`](#intr_state) to 1.     |
+|   8    |   wo   |   0x0   | sda_unstable     | Write 1 to force [`INTR_STATE.sda_unstable`](#intr_state) to 1.     |
+|   7    |   wo   |   0x0   | stretch_timeout  | Write 1 to force [`INTR_STATE.stretch_timeout`](#intr_state) to 1.  |
+|   6    |   wo   |   0x0   | sda_interference | Write 1 to force [`INTR_STATE.sda_interference`](#intr_state) to 1. |
+|   5    |   wo   |   0x0   | scl_interference | Write 1 to force [`INTR_STATE.scl_interference`](#intr_state) to 1. |
+|   4    |   wo   |   0x0   | controller_halt  | Write 1 to force [`INTR_STATE.controller_halt`](#intr_state) to 1.  |
+|   3    |   wo   |   0x0   | rx_overflow      | Write 1 to force [`INTR_STATE.rx_overflow`](#intr_state) to 1.      |
+|   2    |   wo   |   0x0   | acq_threshold    | Write 1 to force [`INTR_STATE.acq_threshold`](#intr_state) to 1.    |
+|   1    |   wo   |   0x0   | rx_threshold     | Write 1 to force [`INTR_STATE.rx_threshold`](#intr_state) to 1.     |
+|   0    |   wo   |   0x0   | fmt_threshold    | Write 1 to force [`INTR_STATE.fmt_threshold`](#intr_state) to 1.    |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CTRL
+I2C Control Register
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLEHOST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ENABLETARGET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NACK_ADDR_AFTER_TIMEOUT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACK_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MULTI_CONTROLLER_MONITOR_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TX_STRETCH_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                              |
+|:------:|:------:|:-------:|:------------------------------------------------------------------|
+|  31:7  |        |         | Reserved                                                          |
+|   6    |   rw   |   0x0   | [TX_STRETCH_CTRL_EN](#ctrl--tx_stretch_ctrl_en)                   |
+|   5    |   rw   |   0x0   | [MULTI_CONTROLLER_MONITOR_EN](#ctrl--multi_controller_monitor_en) |
+|   4    |   rw   |   0x0   | [ACK_CTRL_EN](#ctrl--ack_ctrl_en)                                 |
+|   3    |   rw   |   0x0   | [NACK_ADDR_AFTER_TIMEOUT](#ctrl--nack_addr_after_timeout)         |
+|   2    |   rw   |   0x0   | [LLPBK](#ctrl--llpbk)                                             |
+|   1    |   rw   |   0x0   | [ENABLETARGET](#ctrl--enabletarget)                               |
+|   0    |   rw   |   0x0   | [ENABLEHOST](#ctrl--enablehost)                                   |
+
+### CTRL . TX_STRETCH_CTRL_EN
+If set to 1, this bit causes a read transfer addressed to this target to set the corresponding bit in [`TARGET_EVENTS.`](#target_events)
+
+While [`TARGET_EVENTS.TX_PENDING`](#target_events) is 1, subsequent read transactions will stretch the clock, even if there is data in the TX FIFO.
+
+If enabled, this function allows software to confirm the data in the TX FIFO should be released for the current read.
+This may be useful for cases where the TX FIFO has data that does not apply to the current transfer.
+For example, the transaction could've targeted an alternate function via another address.
+
+### CTRL . MULTI_CONTROLLER_MONITOR_EN
+Enable the bus monitor in multi-controller mode.
+
+If a 0->1 transition happens while [`CTRL.ENABLEHOST`](#ctrl) and [`CTRL.ENABLETARGET`](#ctrl) are both 0, the bus monitor will enable and begin in the "bus busy" state.
+To transition to a bus free state, [`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl) must be nonzero, so the bus monitor may count out idle cycles to confirm the freedom to transmit.
+In addition, the bus monitor will track whether the bus is free based on the enabled timeouts and detected Stop symbols.
+For multi-controller mode, ensure [`CTRL.MULTI_CONTROLLER_MONITOR_EN`](#ctrl) becomes 1 no later than [`CTRL.ENABLEHOST`](#ctrl) or [`CTRL.ENABLETARGET.`](#ctrl)
+This bit can be set at the same time as either or both of the other two, though.
+
+Note that if [`CTRL.MULTI_CONTROLLER_MONITOR_EN`](#ctrl) is set after [`CTRL.ENABLEHOST`](#ctrl) or [`CTRL.ENABLETARGET`](#ctrl), the bus monitor will begin in the "bus free" state instead.
+This would violate the proper protocol for a controller to join a multi-controller environment.
+However, if this controller is known to be the first to join, this ordering will enable skipping the idle wait.
+
+When 0, the bus monitor will report that the bus is always free, so the controller FSM is never blocked from transmitting.
+
+### CTRL . ACK_CTRL_EN
+Enable I2C Target ACK Control Mode.
+
+ACK Control Mode works together with [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) to allow software to control upper-layer protocol (N)ACKing (e.g. as in SMBus).
+This bit enables the mode when 1, and [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) limits how many bytes may be automatically ACK'd while the ACQ FIFO has space.
+If it is 0, the decision to ACK or NACK is made only from stretching timeouts and [`CTRL.NACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+
+### CTRL . NACK_ADDR_AFTER_TIMEOUT
+Enable NACKing the address on a stretch timeout.
+
+This is a Target mode feature.
+If enabled (1), a stretch timeout will cause the device to NACK the address byte.
+If disabled (0), a stretch timeout will cause the device to ACK the address byte.
+SMBus requires that devices always ACK their address, even for read commands.
+However, non-SMBus protocols may have a different approach and can choose to NACK instead.
+
+Note that both cases handle data bytes the same way.
+For writes, the Target module will NACK all subsequent data bytes until it receives a Stop.
+For reads, the Target module will release SDA, causing 0xff to be returned for all data bytes until it receives a Stop.
+
+### CTRL . LLPBK
+Enable I2C line loopback test
+If line loopback is enabled, the internal design sees ACQ and RX data as "1"
+
+### CTRL . ENABLETARGET
+Enable Target I2C functionality
+
+### CTRL . ENABLEHOST
+Enable Host I2C functionality
+
+## STATUS
+I2C Live Status Register for Host and Target modes
+- Offset: `0x14`
+- Reset default: `0x33c`
+- Reset mask: `0x7ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FMTFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FMTEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HOSTIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TARGETIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACK_CTRL_STRETCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                              |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------|
+| 31:11  |        |         |                  | Reserved                                                                                                 |
+|   10   |   ro   |    x    | ACK_CTRL_STRETCH | Target mode stretching at (N)ACK phase due to zero count in [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) |
+|   9    |   ro   |   0x1   | ACQEMPTY         | Target mode receive FIFO is empty                                                                        |
+|   8    |   ro   |   0x1   | TXEMPTY          | Target mode TX FIFO is empty                                                                             |
+|   7    |   ro   |    x    | ACQFULL          | Target mode receive FIFO is full                                                                         |
+|   6    |   ro   |    x    | TXFULL           | Target mode TX FIFO is full                                                                              |
+|   5    |   ro   |   0x1   | RXEMPTY          | Host mode RX FIFO is empty                                                                               |
+|   4    |   ro   |   0x1   | TARGETIDLE       | Target functionality is idle. No Target transaction is in progress                                       |
+|   3    |   ro   |   0x1   | HOSTIDLE         | Host functionality is idle. No Host transaction is in progress                                           |
+|   2    |   ro   |   0x1   | FMTEMPTY         | Host mode FMT FIFO is empty                                                                              |
+|   1    |   ro   |    x    | RXFULL           | Host mode RX FIFO is full                                                                                |
+|   0    |   ro   |    x    | FMTFULL          | Host mode FMT FIFO is full                                                                               |
+
+## RDATA
+I2C Read Data
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   ro   |    x    | RDATA  |               |
+
+## FDATA
+I2C Host Format Data
+
+Writes to this register are used to define and drive Controller-Mode transactions.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FBYTE", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "READB", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RCONT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "NAKOK", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   |
+|:------:|:------:|:-------:|:-----------------------|
+| 31:13  |        |         | Reserved               |
+|   12   |   wo   |   0x0   | [NAKOK](#fdata--nakok) |
+|   11   |   wo   |   0x0   | [RCONT](#fdata--rcont) |
+|   10   |   wo   |   0x0   | [READB](#fdata--readb) |
+|   9    |   wo   |   0x0   | [STOP](#fdata--stop)   |
+|   8    |   wo   |   0x0   | [START](#fdata--start) |
+|  7:0   |   wo   |   0x0   | [FBYTE](#fdata--fbyte) |
+
+### FDATA . NAKOK
+For the currrent controller-transmitter byte (WRITE), do not halt via CONTROLLER_EVENTS
+or assert the 'controller_halt' interrupt if the current byte is not ACK'd.
+
+### FDATA . RCONT
+Do not NACK the last byte read, let the read operation continue.
+
+### FDATA . READB
+Transfer Direction Indicator.
+
+If unset, this write to FDATA defines a controller-transmitter operation (WRITE).
+A single byte of data (FBYTE) is written to the bus.
+
+If set, this write to FDATA defines a controller-receiver operation (READ).
+The value of FBYTE defines the number of bytes read from the bus. (256 if FBYTE==0)"
+After this number of bytes are read, the final byte will be NACKed to end the transfer
+unless RCONT is also set.
+
+### FDATA . STOP
+Issue a STOP condition after transmitting FBYTE.
+
+### FDATA . START
+Issue a START condition before transmitting FBYTE.
+
+### FDATA . FBYTE
+Format Byte.
+
+If no flags are set, hardware will transmit this byte directly.
+
+If READB is set, this field becomes the number of bytes hardware will automatically
+read from the bus.
+
+## FIFO_CTRL
+I2C FIFO control register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x183`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "FMTRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 5}, {"name": "ACQRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                             |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------|
+|  31:9  |        |         |        | Reserved                                                                |
+|   8    |   wo   |   0x0   | TXRST  | TX FIFO reset. Write 1 to the register resets it. Read returns 0        |
+|   7    |   wo   |   0x0   | ACQRST | ACQ FIFO reset. Write 1 to the register resets it. Read returns 0       |
+|  6:2   |        |         |        | Reserved                                                                |
+|   1    |   wo   |   0x0   | FMTRST | FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0 |
+|   0    |   wo   |   0x0   | RXRST  | RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0   |
+
+## HOST_FIFO_CONFIG
+Host mode FIFO configuration
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "FMT_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                                |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:28  |        |         |            | Reserved                                                                                                                                                   |
+| 27:16  |   rw   |   0x0   | FMT_THRESH | Threshold level for FMT interrupts. Whilst the number of used entries in the FMT FIFO is below this setting, the fmt_threshold interrupt will be asserted. |
+| 15:12  |        |         |            | Reserved                                                                                                                                                   |
+|  11:0  |   rw   |   0x0   | RX_THRESH  | Threshold level for RX interrupts. Whilst the level of data in the RX FIFO is above this setting, the rx_threshold interrupt will be asserted.             |
+
+## TARGET_FIFO_CONFIG
+Target mode FIFO configuration
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "ACQ_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                             |
+|:------:|:------:|:-------:|:-----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:28  |        |         |            | Reserved                                                                                                                                                |
+| 27:16  |   rw   |   0x0   | ACQ_THRESH | Threshold level for ACQ interrupts. Whilst the level of data in the ACQ FIFO is above this setting, the acq_threshold interrupt will be asserted.       |
+| 15:12  |        |         |            | Reserved                                                                                                                                                |
+|  11:0  |   rw   |   0x0   | TX_THRESH  | Threshold level for TX interrupts. Whilst the number of used entries in the TX FIFO is below this setting, the tx_threshold interrupt will be asserted. |
+
+## HOST_FIFO_STATUS
+Host mode FIFO status register
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FMTLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "RXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:28  |        |         |        | Reserved                       |
+| 27:16  |   ro   |    x    | RXLVL  | Current fill level of RX fifo  |
+| 15:12  |        |         |        | Reserved                       |
+|  11:0  |   ro   |    x    | FMTLVL | Current fill level of FMT fifo |
+
+## TARGET_FIFO_STATUS
+Target mode FIFO status register
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "ACQLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:28  |        |         |        | Reserved                       |
+| 27:16  |   ro   |    x    | ACQLVL | Current fill level of ACQ fifo |
+| 15:12  |        |         |        | Reserved                       |
+|  11:0  |   ro   |    x    | TXLVL  | Current fill level of TX fifo  |
+
+## OVRD
+I2C Override Control Register
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXOVRDEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SCLVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SDAVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                               |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------|
+|  31:3  |        |         |          | Reserved                                                                  |
+|   2    |   rw   |   0x0   | SDAVAL   | Value for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z |
+|   1    |   rw   |   0x0   | SCLVAL   | Value for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z |
+|   0    |   rw   |   0x0   | TXOVRDEN | Override the SDA and SCL TX signals.                                      |
+
+## VAL
+Oversampled RX values
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SCL_RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "SDA_RX", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------|
+| 31:16  |   ro   |    x    | SDA_RX | Last 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31. |
+|  15:0  |   ro   |    x    | SCL_RX | Last 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.  |
+
+## TIMING0
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+These must be greater than 2 in order for the change in SCL to propagate to the input of the FSM so that acknowledgements are detected correctly.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "THIGH", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "TLOW", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                        |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |        | Reserved                                                                                                                                                           |
+| 28:16  |   rw   |   0x0   | TLOW   | The actual time to hold SCL low between any two SCL pulses. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+| 15:13  |        |         |        | Reserved                                                                                                                                                           |
+|  12:0  |   rw   |   0x0   | THIGH  | The actual time to hold SCL high in a given pulse. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.          |
+
+## TIMING1
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x1ff03ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_R", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "T_F", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:25  |        |         |        | Reserved                                                                                                                                                                            |
+| 24:16  |   rw   |   0x0   | T_F    | The nominal fall time to anticipate for the bus (influences SDA hold times). This field is sized to have a range of at least Standard Mode's 300 ns max with a core clock at 1 GHz. |
+| 15:10  |        |         |        | Reserved                                                                                                                                                                            |
+|  9:0   |   rw   |   0x0   | T_R    | The nominal rise time to anticipate for the bus (depends on capacitance). This field is sized to have a range of at least Standard Mode's 1000 ns max with a core clock at 1 GHz.   |
+
+## TIMING2
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "THD_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                          |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |         | Reserved                                                                                                                                             |
+| 28:16  |   rw   |   0x0   | THD_STA | Actual hold time for start signals. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.           |
+| 15:13  |        |         |         | Reserved                                                                                                                                             |
+|  12:0  |   rw   |   0x0   | TSU_STA | Actual setup time for repeated start signals. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+
+## TIMING3
+Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x1fff01ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_DAT", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "THD_DAT", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         |
+|:------:|:------:|:-------:|:-----------------------------|
+| 31:29  |        |         | Reserved                     |
+| 28:16  |   rw   |   0x0   | [THD_DAT](#timing3--thd_dat) |
+|  15:9  |        |         | Reserved                     |
+|  8:0   |   rw   |   0x0   | [TSU_DAT](#timing3--tsu_dat) |
+
+### TIMING3 . THD_DAT
+Actual hold time for data (or ack) bits.
+(Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
+This field is sized to have a range that accommodates Standard Mode's 3.45 us max for TVD_DAT with a core clock at 1 GHz.
+However, this field is generally expected to represent a time substantially shorter than that.
+It should be long enough to cover the maximum round-trip latency from output pins, through pads and voltage transitions on the board, and back to the input pins, but it should not be substantially greater.
+
+### TIMING3 . TSU_DAT
+Actual setup time for data (or ack) bits.
+This field is sized to have a range of at least Standard Mode's 250 ns max with a core clock at 1 GHz.
+
+## TIMING4
+Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_STO", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "T_BUF", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                                 |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |         | Reserved                                                                                                                                                                    |
+| 28:16  |   rw   |   0x0   | T_BUF   | Actual time between each STOP signal and the following START signal. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+| 15:13  |        |         |         | Reserved                                                                                                                                                                    |
+|  12:0  |   rw   |   0x0   | TSU_STO | Actual setup time for stop signals. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.                                  |
+
+## TIMEOUT_CTRL
+I2C clock stretching and bus timeout control.
+
+This timeout must be enabled by setting [`TIMEOUT_CTRL.EN`](#timeout_ctrl) to 1, and the behavior of this feature depends on the value of [`TIMEOUT_CTRL.MODE.`](#timeout_ctrl)
+
+If the mode is "STRETCH_TIMEOUT", this is used in I2C controller mode to detect whether a connected target is stretching a single low time beyond the timeout value.
+Configured as such, this timeout is more informative and doesn't do more than assert the "stretch_timeout" interrupt.
+
+If the mode is "BUS_TIMEOUT", it is used to detect whether the clock has been held low for too long instead, inclusive of the controller's clock low time.
+This is useful for an SMBus context, where the VAL programmed should be tTIMEOUT:MIN.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        |
+|:------:|:------:|:-------:|:----------------------------|
+|   31   |   rw   |   0x0   | [EN](#timeout_ctrl--en)     |
+|   30   |   rw   |   0x0   | [MODE](#timeout_ctrl--mode) |
+|  29:0  |   rw   |   0x0   | [VAL](#timeout_ctrl--val)   |
+
+### TIMEOUT_CTRL . EN
+Enable stretch timeout or bus timeout feature
+
+### TIMEOUT_CTRL . MODE
+Selects the timeout mode, between a stretch timeout and a bus timeout.
+
+Between the two modes, the primary difference is how much of the clock low period is counted.
+For a stretch timeout, only the time that another device holds the clock low will be counted.
+For a bus timeout, the entire clock low time is counted, consistent with the SMBus tTIMEOUT type.
+
+[`TIMEOUT_CTRL.EN`](#timeout_ctrl) must be 1 for either of these features to be enabled.
+
+| Value   | Name            | Description                                                                                                                                                                                                                                |
+|:--------|:----------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 0x0     | STRETCH_TIMEOUT | The timeout is a target stretch timeout. The counter will track how long the clock has been stretched by another device while the controller is active.                                                                                    |
+| 0x1     | BUS_TIMEOUT     | The timeout is a clock low timeout. The counter will track how long the clock low period is, inclusive of the controller's ordinary low count. A timeout will set !!CONTROLLER_EVENTS.BUS_TIMEOUT and cause a "controller_halt" interrupt. |
+
+
+### TIMEOUT_CTRL . VAL
+Clock stretching timeout value (in units of input clock frequency)
+
+## TARGET_ID
+I2C target address and mask pairs
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xfffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "ADDRESS1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                   |
+|:------:|:------:|:-------:|:---------|:----------------------------------------------------------------------------------------------|
+| 31:28  |        |         |          | Reserved                                                                                      |
+| 27:21  |   rw   |   0x0   | MASK1    | I2C target mask number 1. At least one bit in MASK1 must be set to 1 for ADDRESS1 to be used. |
+| 20:14  |   rw   |   0x0   | ADDRESS1 | I2C target address number 1                                                                   |
+|  13:7  |   rw   |   0x0   | MASK0    | I2C target mask number 0. At least one bit in MASK0 must be set to 1 for ADDRESS0 to be used. |
+|  6:0   |   rw   |   0x0   | ADDRESS0 | I2C target address number 0                                                                   |
+
+## ACQDATA
+I2C target acquired data
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ABYTE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "SIGNAL", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       |
+|:------:|:------:|:-------:|:---------------------------|
+| 31:11  |        |         | Reserved                   |
+|  10:8  |   ro   |    x    | [SIGNAL](#acqdata--signal) |
+|  7:0   |   ro   |    x    | [ABYTE](#acqdata--abyte)   |
+
+### ACQDATA . SIGNAL
+Indicates any control symbols associated with the ABYTE.
+
+For the STOP symbol, a stretch timeout or other unexpected events will cause a NACK_STOP to appear in the ACQ FIFO.
+If the ACQ FIFO doesn't have enough space to record a START and a STOP, the transaction will be dropped entirely on a stretch timeout.
+In that case, the START byte will not appear (neither as START nor NACK_START), but a standalone NACK_STOP may, if there was space.
+Software can discard any standalone NACK_STOP that appears.
+
+See the associated values for more information about the contents.
+
+| Value   | Name       | Description                                                                                                                                                                                                                                                                                                                                                                                                                                         |
+|:--------|:-----------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 0x0     | NONE       | ABYTE contains an ordinary data byte that was received and ACK'd.                                                                                                                                                                                                                                                                                                                                                                                   |
+| 0x1     | START      | A START condition preceded the ABYTE to start a new transaction. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.                                                                                                                                                                                                                                                                             |
+| 0x2     | STOP       | A STOP condition was received for a transaction including a transfer that addressed this Target. No transfers addressing this Target in that transaction were NACK'd. ABYTE contains no data.                                                                                                                                                                                                                                                       |
+| 0x3     | RESTART    | A repeated START condition preceded the ABYTE, extending the current transaction with a new transfer. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.                                                                                                                                                                                                                                        |
+| 0x4     | NACK       | ABYTE contains an ordinary data byte that was received and NACK'd.                                                                                                                                                                                                                                                                                                                                                                                  |
+| 0x5     | NACK_START | A START condition preceded the ABYTE (including repeated START) that was part of a NACK'd transfer. The ABYTE contains the matching I2C address and command bit. The ABYTE was ACK'd, but the rest of the transaction was NACK'ed.                                                                                                                                                                                                                  |
+| 0x6     | NACK_STOP  | A transaction including a transfer that addressed this Target was ended, but the transaction ended abnormally and/or the transfer was NACK'd. The end can be due to a STOP condition or unexpected events, such as a bus timeout (if enabled). ABYTE contains no data. NACKing can occur for multiple reasons, including a stretch timeout, a SW-directed NACK, or lost arbitration. This signal is a bucket for all these error-type terminations. |
+
+Other values are reserved.
+
+### ACQDATA . ABYTE
+Address for accepted transaction or acquired byte
+
+## TXDATA
+I2C target transmit data
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   wo   |   0x0   | TXDATA |               |
+
+## HOST_TIMEOUT_CTRL
+I2C host clock generation timeout value (in units of input clock frequency).
+
+In an active transaction in Target-Mode, if the Controller ceases to send SCL pulses
+for this number of cycles then the "host_timeout" interrupt will be asserted.
+
+In multi-controller monitoring mode, [`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl) is required to be nonzero to transition out of the initial busy state.
+Set this CSR to 0 to disable this behaviour.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_TIMEOUT_CTRL", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+| 31:20  |        |         |                   | Reserved      |
+|  19:0  |   rw   |   0x0   | HOST_TIMEOUT_CTRL |               |
+
+## TARGET_TIMEOUT_CTRL
+I2C target internal stretching timeout control.
+When the target has stretched beyond this time it will send a NACK for incoming data bytes or release SDA for outgoing data bytes.
+The behavior for the address byte is configurable via [`CTRL.ACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+Note that the count accumulates stretching time over the course of a transaction.
+In other words, this is equivalent to the SMBus cumulative target clock extension time.
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EN     | Enable timeout feature and send NACK once the timeout has been reached |
+|  30:0  |   rw   |   0x0   | VAL    | Clock stretching timeout value (in units of input clock frequency)     |
+
+## TARGET_NACK_COUNT
+Number of times the I2C target has NACK'ed a new transaction since the last read of this register.
+Reading this register clears it.
+This is useful because when the ACQ FIFO is full the software know that a NACK has occurred, but without this register would not know how many transactions it missed.
+When it reaches its maximum value it will stay at that value.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TARGET_NACK_COUNT", "bits": 8, "attr": ["rc"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:8  |        |         |                   | Reserved      |
+|  7:0   |   rc   |   0x0   | TARGET_NACK_COUNT |               |
+
+## TARGET_ACK_CTRL
+Controls for mid-transfer (N)ACK phase handling
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x800001ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "NBYTES", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 22}, {"name": "NACK", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+|   31   |   wo   |    x    | [NACK](#target_ack_ctrl--nack)     |
+|  30:9  |        |         | Reserved                           |
+|  8:0   |   rw   |    x    | [NBYTES](#target_ack_ctrl--nbytes) |
+
+### TARGET_ACK_CTRL . NACK
+When the Target module stretches on the (N)ACK phase of a Write due to [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) being 0, writing a 1 here will cause it to send a NACK.
+
+If software chooses to NACK, note that the NACKing behavior is the same as if a stretch timeout occurred.
+The rest of the transaction will be NACK'd, including subsequent transfers.
+For the address byte, the (N)ACK phase of subsequent transfers will follow the behavior specified by [`CTRL.NACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+
+Automatically clears to 0.
+
+### TARGET_ACK_CTRL . NBYTES
+Remaining number of bytes the Target module may ACK automatically.
+
+If [`CTRL.ACK_CTRL_EN`](#ctrl) is set to 1, the Target module will stretch the clock at the (N)ACK phase of a byte if this CSR is 0, awaiting software's instructions.
+
+At the beginning of each Write transfer, this byte count is reset to 0.
+Writes to this CSR also are only accepted while the Target module is stretching the clock.
+The Target module will always ACK its address if the ACQ FIFO has space.
+For data bytes afterwards, it will stop at the (N)ACK phase and stretch the clock when this CSR is 0.
+For each data byte that is ACK'd in a transaction, the byte count will decrease by 1.
+
+Note that a full ACQ FIFO can still cause the Target module to halt at the beginning of a new byte.
+The ACK Control Mode provides an additional synchronization point, during the (N)ACK phase instead of after.
+For both cases, [`TARGET_TIMEOUT_CTRL`](#target_timeout_ctrl) applies, and stretching past the timeout will produce an automatic NACK.
+
+This mode can be used to implement the mid-transfer (N)ACK responses required by various SMBus protocols.
+
+## ACQ_FIFO_NEXT_DATA
+The data byte pending to be written to the ACQ FIFO.
+
+This CSR is only valid while the Target module is stretching in the (N)ACK phase, indicated by [`STATUS.ACK_CTRL_STRETCH`](#status) .
+It is intended to be used with ACK Control Mode, so software may check the current byte.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ACQ_FIFO_NEXT_DATA", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:8  |        |         |                    | Reserved      |
+|  7:0   |   ro   |    x    | ACQ_FIFO_NEXT_DATA |               |
+
+## HOST_NACK_HANDLER_TIMEOUT
+Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.
+(in units of input clock frequency)
+
+If an active Controller-Transmitter transfer receives a NACK from the Target, the [`CONTROLLER_EVENTS.NACK`](#controller_events) bit is set.
+In turn, this causes the Controller FSM to halt awaiting software intervention, and the 'controller_halt' interrupt may assert.
+Software must clear the [`CONTROLLER_EVENTS.NACK`](#controller_events) bit to allow the state machine to continue, typically after clearing out the FMTFIFO to start a new transfer.
+While halted, the active transaction is not ended (no STOP (P) condition is created), and the block asserts SCL and leaves SDA released.
+
+This timeout can be used to automatically produce a STOP condition, whether as a backstop for slow software responses (longer timeout) or as a convenience (short timeout).
+If the timeout expires, the Controller FSM will issue a STOP (P) condition on the bus to end the active transaction.
+Additionally, the [`CONTROLLER_EVENTS.UNHANDLED_NACK_TIMEOUT`](#controller_events) bit is set to alert software, and the FSM will return to the idle state and halt until the bit is cleared.
+
+The enable bit must be set for this feature to operate.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                     |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EN     | Timeout enable                                                  |
+|  30:0  |   rw   |   0x0   | VAL    | Unhandled NAK timeout value (in units of input clock frequency) |
+
+## CONTROLLER_EVENTS
+Latched events that explain why the controller halted.
+
+Any bits that are set must be written (with a 1) to clear the CONTROLLER_HALT interrupt.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "NACK", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNHANDLED_NACK_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                                                                                               |
+|:------:|:------:|:-------:|:-----------------------|:--------------------------------------------------------------------------------------------------------------------------|
+|  31:4  |        |         |                        | Reserved                                                                                                                  |
+|   3    |  rw1c  |   0x0   | ARBITRATION_LOST       | A Host-Mode active transaction has terminated due to lost arbitration.                                                    |
+|   2    |  rw1c  |   0x0   | BUS_TIMEOUT            | A Host-Mode active transaction has terminated due to a bus timeout activated by [`TIMEOUT_CTRL.`](#timeout_ctrl)          |
+|   1    |  rw1c  |   0x0   | UNHANDLED_NACK_TIMEOUT | A Host-Mode active transaction has been ended by the [`HOST_NACK_HANDLER_TIMEOUT`](#host_nack_handler_timeout) mechanism. |
+|   0    |  rw1c  |   0x0   | NACK                   | Received an unexpected NACK                                                                                               |
+
+## TARGET_EVENTS
+Latched events that can cause the target module to stretch the clock at the beginning of a read transfer.
+
+These events cause TX FIFO-related stretching even when the TX FIFO has data available.
+Any bits that are set must be written (with a 1) to clear the tx_stretch interrupt.
+
+This CSR serves as a gate to prevent the Target module from responding to a read command with unrelated, leftover data.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX_PENDING", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                 |
+|:------:|:------:|:-------:|:-----------------------------------------------------|
+|  31:3  |        |         | Reserved                                             |
+|   2    |  rw1c  |   0x0   | [ARBITRATION_LOST](#target_events--arbitration_lost) |
+|   1    |  rw1c  |   0x0   | [BUS_TIMEOUT](#target_events--bus_timeout)           |
+|   0    |  rw1c  |   0x0   | [TX_PENDING](#target_events--tx_pending)             |
+
+### TARGET_EVENTS . ARBITRATION_LOST
+A Target-Mode read transfer has terminated due to lost arbitration.
+
+### TARGET_EVENTS . BUS_TIMEOUT
+A Target-Mode read transfer has terminated due to a bus timeout activated by [`TIMEOUT_CTRL.`](#timeout_ctrl)
+
+### TARGET_EVENTS . TX_PENDING
+A new Target-Mode read transfer has arrived that addressed this target.
+
+This bit is used by software to confirm the release of the contents in the TX FIFO.
+If the contents do not apply, software should first reset the TX FIFO, then load it with the correct data, then clear this bit.
+
+Optionally enabled by [`CTRL.TX_STRETCH_CTRL_EN.`](#ctrl)
+
+
+
+## integer_cluster / doc / pulp_cluster_peripherals_memory_map.md
+
+## PULP Cluster Peripheral Memory Map
+
+This document describes the memory-mapped peripheral devices accessible from the PULP cluster through the peripheral interconnect slave port.
+
+## Base Address
+
+- **Cluster Base Address**: `0x5000_0000`
+- **Peripheral Offset**: `0x0020_0000`
+- **External Offset**: `0x0040_0000`
+
+**Cluster Peripheral Base Address**:  
+`0x5020_0000` – `0x5040_0000` (2 MiB region)
+
+---
+
+## Peripheral Layout
+
+| Peripheral           | ID   | Offset (from Peripheral Base) | Address Range                  |
+|----------------------|------|-------------------------------|--------------------------------|
+| EOC                  | 0    | `0x0000`                      | `0x5020_0000` – `0x5020_03FF`  |
+| Timer                | 1    | `0x0400`                      | `0x5020_0400` – `0x5020_07FF`  |
+| Event Unit (also 3)  | 2/3  | `0x0800`                      | `0x5020_0800` – `0x5020_0FFF`  |
+| HWPE                 | 4    | `0x1000`                      | `0x5020_1000` – `0x5020_13FF`  |
+| ICache Controller    | 5    | `0x1400`                      | `0x5020_1400` – `0x5020_17FF`  |
+| DMA (Cluster)        | 6    | `0x1800`                      | `0x5020_1800` – `0x5020_1BFF`  |
+| DMA (Fabric Ctrl)    | 7    | `0x1C00`                      | `0x5020_1C00` – `0x5020_1FFF`  |
+| HMR Unit             | 8    | `0x2000`                      | `0x5020_2000` – `0x5020_23FF`  |
+| External             | 9    | `0x2400`                      | `0x5020_2400` – `0x5020_27FF`  |
+| Error Unit           | 10   | `0x2800`                      | `0x5020_2800` – `0x5020_2BFF`  |
+
+---
+
+## Address Mapping Summary
+
+| Region           | Index | Start Address | End Address   | Notes                          |
+|------------------|--------|----------------|---------------|--------------------------------|
+| TCDM             | 0      | `0x5000_0000`   | `0x5000_0000 + TCDM_SIZE` | Tightly Coupled Data Memory    |
+| Peripherals      | 1      | `0x5020_0000`   | `0x5040_0000` | Cluster Peripheral Region      |
+| External         | 2      | `0x5040_0000`   | `0xFFFF_FFFF` | Access beyond cluster          |
+| Below Cluster    | 3      | `0x0000_0000`   | `0x5000_0000` | Not cluster-related            |
+
+
+## irq_router / doc / registers.md
+
+## Summary
+
+| Name                                             | Offset   |   Length | Description                               |
+|:-------------------------------------------------|:---------|---------:|:------------------------------------------|
+| irq_router.[`IRQ_TARGET_MASK`](#irq_target_mask) | 0x0      |        4 | Target selection bitmask control register |
+
+## IRQ_TARGET_MASK
+Target selection bitmask control register
+- Offset: `0x0`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "mask", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x1   | mask   | Target selection bitmask control register for single interrupt line. Reflects interrupt line logic level. |
+
+
+
+## l2_ecc_config / doc / registers.md
+
+## Summary
+
+| Name                                                                  | Offset   |   Length | Description                                     |
+|:----------------------------------------------------------------------|:---------|---------:|:------------------------------------------------|
+| ECC_manager.[`mismatch_count`](#mismatch_count)                       | 0x0      |        4 | Correctable mismatches caught by ecc on access  |
+| ECC_manager.[`scrub_interval`](#scrub_interval)                       | 0x4      |        4 | Interval between scrubs                         |
+| ECC_manager.[`scrub_fix_count`](#scrub_fix_count)                     | 0x8      |        4 | Correctable mismatches caught by ecc on scrub   |
+| ECC_manager.[`scrub_uncorrectable_count`](#scrub_uncorrectable_count) | 0xc      |        4 | Uncorrectable mismatches caught by ecc on scrub |
+| ECC_manager.[`write_mask_data_n`](#write_mask_data_n)                 | 0x10     |        4 | Testing: Inverted write mask for data bits      |
+| ECC_manager.[`write_mask_ecc_n`](#write_mask_ecc_n)                   | 0x14     |        4 | Testing: Inverted write mask for ECC bits       |
+
+## mismatch_count
+Correctable mismatches caught by ecc on access
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                    |
+|:------:|:------:|:-------:|:-----------------------|:-----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on access |
+
+## scrub_interval
+Interval between scrubs
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "scrub_interval", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description             |
+|:------:|:------:|:-------:|:---------------|:------------------------|
+|  31:0  |   rw   |   0x0   | scrub_interval | Interval between scrubs |
+
+## scrub_fix_count
+Correctable mismatches caught by ecc on scrub
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                   |
+|:------:|:------:|:-------:|:-----------------------|:----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on scrub |
+
+## scrub_uncorrectable_count
+Uncorrectable mismatches caught by ecc on scrub
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "uncorrectable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description                                     |
+|:------:|:------:|:-------:|:-------------------------|:------------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | uncorrectable_mismatches | Uncorrectable mismatches caught by ecc on scrub |
+
+## write_mask_data_n
+Testing: Inverted write mask for data bits
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_data_n", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                                |
+|:------:|:------:|:-------:|:------------------|:-------------------------------------------|
+|  31:0  |   rw   |   0x0   | write_mask_data_n | Testing: Inverted write mask for data bits |
+
+## write_mask_ecc_n
+Testing: Inverted write mask for ECC bits
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_ecc_n", "bits": 7, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                               |
+|:------:|:------:|:-------:|:-----------------|:------------------------------------------|
+|  31:7  |        |         |                  | Reserved                                  |
+|  6:0   |   rw   |   0x0   | write_mask_ecc_n | Testing: Inverted write mask for ECC bits |
+
+
+
+## mailbox / doc / registers.md
+
+## Summary
+
+| Name                                    | Offset   |   Length | Description                                 |
+|:----------------------------------------|:---------|---------:|:--------------------------------------------|
+| mailbox.[`IRQ_SND_STAT`](#irq_snd_stat) | 0x0      |        4 | Sender interrupt status register            |
+| mailbox.[`IRQ_SND_SET`](#irq_snd_set)   | 0x4      |        4 | Sender interrupt set register               |
+| mailbox.[`IRQ_SND_CLR`](#irq_snd_clr)   | 0x8      |        4 | Sender interrupt clear register             |
+| mailbox.[`IRQ_SND_EN`](#irq_snd_en)     | 0xc      |        4 | Sender interrupt enable register            |
+| mailbox.[`IRQ_RCV_STAT`](#irq_rcv_stat) | 0x40     |        4 | Receiver interrupt status register          |
+| mailbox.[`IRQ_RCV_SET`](#irq_rcv_set)   | 0x44     |        4 | Receiver interrupt set register             |
+| mailbox.[`IRQ_RCV_CLR`](#irq_rcv_clr)   | 0x48     |        4 | Receiver interrupt clear register           |
+| mailbox.[`IRQ_RCV_EN`](#irq_rcv_en)     | 0x4c     |        4 | Receiver interrupt enable register          |
+| mailbox.[`LETTER0`](#letter0)           | 0x80     |        4 | Memory region 0 to put a message or pointer |
+| mailbox.[`LETTER1`](#letter1)           | 0x84     |        4 | Memory region 1 to put a message or pointer |
+
+## IRQ_SND_STAT
+Sender interrupt status register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stat", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                  |
+|:------:|:------:|:-------:|:---------|:---------------------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                                     |
+|   0    |   ro   |    x    | stat     | Sender side interrupt status. Receiver confirms letter. Reflects interrupt line logic level. |
+
+## IRQ_SND_SET
+Sender interrupt set register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "set", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                          |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                             |
+|   0    |   wo   |    x    | set      | Sender side interrupt set. Receiver confirms letter. |
+
+## IRQ_SND_CLR
+Sender interrupt clear register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clr", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                            |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                               |
+|   0    |   wo   |    x    | clr      | Sender side interrupt clear. Receiver confirms letter. |
+
+## IRQ_SND_EN
+Sender interrupt enable register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                             |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------|
+|  31:1  |   ro   |   0x0   | reserved | reserved                                                |
+|   0    |   rw   |   0x0   | en       | Sender side interrupt enable. Receiver confirms letter. |
+
+## IRQ_RCV_STAT
+Receiver interrupt status register
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stat", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                                             |
+|:------:|:------:|:-------:|:---------|:------------------------------------------------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                                                                |
+|   0    |   ro   |    x    | stat     | Receiver side interrupt status. Sender notifies receiver of a new letter arriving. Reflects interrupt line logic level. |
+
+## IRQ_RCV_SET
+Receiver interrupt set register
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "set", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                     |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                        |
+|   0    |   wo   |    x    | set      | Receiver side interrupt set. Sender notifies receiver of a new letter arriving. |
+
+## IRQ_RCV_CLR
+Receiver interrupt clear register
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clr", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                          |
+|   0    |   wo   |    x    | clr      | Receiver side interrupt clear. Sender notifies receiver of a new letter arriving. |
+
+## IRQ_RCV_EN
+Receiver interrupt enable register
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                        |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------------------------------------------------|
+|  31:1  |   ro   |   0x0   | reserved | reserved                                                                           |
+|   0    |   rw   |   0x0   | en       | Receiver side interrupt enable. Sender notifies receiver of a new letter arriving. |
+
+## LETTER0
+Memory region 0 to put a message or pointer
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LETTER0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   rw   |   0x0   | LETTER0 |               |
+
+## LETTER1
+Memory region 1 to put a message or pointer
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LETTER1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   rw   |   0x0   | LETTER1 |               |
+
+
+
+## plic / doc / registers.md
+
+## Summary
+
+| Name                                | Offset    |   Length | Description                                                        |
+|:------------------------------------|:----------|---------:|:-------------------------------------------------------------------|
+| rv_plic.[`PRIO0`](#prio0)           | 0x0       |        4 | Interrupt Source 0 Priority                                        |
+| rv_plic.[`PRIO1`](#prio1)           | 0x4       |        4 | Interrupt Source 1 Priority                                        |
+| rv_plic.[`PRIO2`](#prio2)           | 0x8       |        4 | Interrupt Source 2 Priority                                        |
+| rv_plic.[`PRIO3`](#prio3)           | 0xc       |        4 | Interrupt Source 3 Priority                                        |
+| rv_plic.[`PRIO4`](#prio4)           | 0x10      |        4 | Interrupt Source 4 Priority                                        |
+| rv_plic.[`PRIO5`](#prio5)           | 0x14      |        4 | Interrupt Source 5 Priority                                        |
+| rv_plic.[`PRIO6`](#prio6)           | 0x18      |        4 | Interrupt Source 6 Priority                                        |
+| rv_plic.[`PRIO7`](#prio7)           | 0x1c      |        4 | Interrupt Source 7 Priority                                        |
+| rv_plic.[`PRIO8`](#prio8)           | 0x20      |        4 | Interrupt Source 8 Priority                                        |
+| rv_plic.[`PRIO9`](#prio9)           | 0x24      |        4 | Interrupt Source 9 Priority                                        |
+| rv_plic.[`PRIO10`](#prio10)         | 0x28      |        4 | Interrupt Source 10 Priority                                       |
+| rv_plic.[`PRIO11`](#prio11)         | 0x2c      |        4 | Interrupt Source 11 Priority                                       |
+| rv_plic.[`PRIO12`](#prio12)         | 0x30      |        4 | Interrupt Source 12 Priority                                       |
+| rv_plic.[`PRIO13`](#prio13)         | 0x34      |        4 | Interrupt Source 13 Priority                                       |
+| rv_plic.[`PRIO14`](#prio14)         | 0x38      |        4 | Interrupt Source 14 Priority                                       |
+| rv_plic.[`PRIO15`](#prio15)         | 0x3c      |        4 | Interrupt Source 15 Priority                                       |
+| rv_plic.[`PRIO16`](#prio16)         | 0x40      |        4 | Interrupt Source 16 Priority                                       |
+| rv_plic.[`PRIO17`](#prio17)         | 0x44      |        4 | Interrupt Source 17 Priority                                       |
+| rv_plic.[`PRIO18`](#prio18)         | 0x48      |        4 | Interrupt Source 18 Priority                                       |
+| rv_plic.[`PRIO19`](#prio19)         | 0x4c      |        4 | Interrupt Source 19 Priority                                       |
+| rv_plic.[`PRIO20`](#prio20)         | 0x50      |        4 | Interrupt Source 20 Priority                                       |
+| rv_plic.[`PRIO21`](#prio21)         | 0x54      |        4 | Interrupt Source 21 Priority                                       |
+| rv_plic.[`PRIO22`](#prio22)         | 0x58      |        4 | Interrupt Source 22 Priority                                       |
+| rv_plic.[`PRIO23`](#prio23)         | 0x5c      |        4 | Interrupt Source 23 Priority                                       |
+| rv_plic.[`PRIO24`](#prio24)         | 0x60      |        4 | Interrupt Source 24 Priority                                       |
+| rv_plic.[`PRIO25`](#prio25)         | 0x64      |        4 | Interrupt Source 25 Priority                                       |
+| rv_plic.[`PRIO26`](#prio26)         | 0x68      |        4 | Interrupt Source 26 Priority                                       |
+| rv_plic.[`PRIO27`](#prio27)         | 0x6c      |        4 | Interrupt Source 27 Priority                                       |
+| rv_plic.[`PRIO28`](#prio28)         | 0x70      |        4 | Interrupt Source 28 Priority                                       |
+| rv_plic.[`PRIO29`](#prio29)         | 0x74      |        4 | Interrupt Source 29 Priority                                       |
+| rv_plic.[`PRIO30`](#prio30)         | 0x78      |        4 | Interrupt Source 30 Priority                                       |
+| rv_plic.[`PRIO31`](#prio31)         | 0x7c      |        4 | Interrupt Source 31 Priority                                       |
+| rv_plic.[`IP`](#IP)                 | 0x1000    |        4 | Interrupt Pending                                                  |
+| rv_plic.[`IE0`](#IE0)               | 0x2000    |        4 | Interrupt Enable for Target 0                                      |
+| rv_plic.[`THRESHOLD0`](#threshold0) | 0x200000  |        4 | Threshold of priority for Target 0                                 |
+| rv_plic.[`CC0`](#cc0)               | 0x200004  |        4 | Claim interrupt by read, complete interrupt by write for Target 0. |
+| rv_plic.[`MSIP0`](#msip0)           | 0x4000000 |        4 | msip for Hart 0.                                                   |
+| rv_plic.[`ALERT_TEST`](#alert_test) | 0x4004000 |        4 | Alert Test Register.                                               |
+
+## PRIO0
+Interrupt Source 0 Priority
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO0  |               |
+
+## PRIO1
+Interrupt Source 1 Priority
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO1  |               |
+
+## PRIO2
+Interrupt Source 2 Priority
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO2  |               |
+
+## PRIO3
+Interrupt Source 3 Priority
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO3  |               |
+
+## PRIO4
+Interrupt Source 4 Priority
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO4", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO4  |               |
+
+## PRIO5
+Interrupt Source 5 Priority
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO5", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO5  |               |
+
+## PRIO6
+Interrupt Source 6 Priority
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO6", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO6  |               |
+
+## PRIO7
+Interrupt Source 7 Priority
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO7", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO7  |               |
+
+## PRIO8
+Interrupt Source 8 Priority
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO8", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO8  |               |
+
+## PRIO9
+Interrupt Source 9 Priority
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO9", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO9  |               |
+
+## PRIO10
+Interrupt Source 10 Priority
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO10", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO10 |               |
+
+## PRIO11
+Interrupt Source 11 Priority
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO11", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO11 |               |
+
+## PRIO12
+Interrupt Source 12 Priority
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO12", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO12 |               |
+
+## PRIO13
+Interrupt Source 13 Priority
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO13", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO13 |               |
+
+## PRIO14
+Interrupt Source 14 Priority
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO14", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO14 |               |
+
+## PRIO15
+Interrupt Source 15 Priority
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO15", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO15 |               |
+
+## PRIO16
+Interrupt Source 16 Priority
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO16", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO16 |               |
+
+## PRIO17
+Interrupt Source 17 Priority
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO17", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO17 |               |
+
+## PRIO18
+Interrupt Source 18 Priority
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO18", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO18 |               |
+
+## PRIO19
+Interrupt Source 19 Priority
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO19", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO19 |               |
+
+## PRIO20
+Interrupt Source 20 Priority
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO20", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO20 |               |
+
+## PRIO21
+Interrupt Source 21 Priority
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO21", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO21 |               |
+
+## PRIO22
+Interrupt Source 22 Priority
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO22", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO22 |               |
+
+## PRIO23
+Interrupt Source 23 Priority
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO23", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO23 |               |
+
+## PRIO24
+Interrupt Source 24 Priority
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO24", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO24 |               |
+
+## PRIO25
+Interrupt Source 25 Priority
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO25", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO25 |               |
+
+## PRIO26
+Interrupt Source 26 Priority
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO26", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO26 |               |
+
+## PRIO27
+Interrupt Source 27 Priority
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO27", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO27 |               |
+
+## PRIO28
+Interrupt Source 28 Priority
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO28", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO28 |               |
+
+## PRIO29
+Interrupt Source 29 Priority
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO29", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO29 |               |
+
+## PRIO30
+Interrupt Source 30 Priority
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO30", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO30 |               |
+
+## PRIO31
+Interrupt Source 31 Priority
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO31", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO31 |               |
+
+## IP
+Interrupt Pending
+- Offset: `0x1000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "P_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_9", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_10", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_11", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_12", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_13", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_14", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_15", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_16", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_17", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_18", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_19", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_20", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_21", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_22", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_23", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_24", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_25", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_26", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_27", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_28", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_29", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_30", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_31", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                 |
+|:------:|:------:|:-------:|:-------|:----------------------------|
+|   31   |   ro   |   0x0   | P_31   | Interrupt Pending of Source |
+|   30   |   ro   |   0x0   | P_30   | Interrupt Pending of Source |
+|   29   |   ro   |   0x0   | P_29   | Interrupt Pending of Source |
+|   28   |   ro   |   0x0   | P_28   | Interrupt Pending of Source |
+|   27   |   ro   |   0x0   | P_27   | Interrupt Pending of Source |
+|   26   |   ro   |   0x0   | P_26   | Interrupt Pending of Source |
+|   25   |   ro   |   0x0   | P_25   | Interrupt Pending of Source |
+|   24   |   ro   |   0x0   | P_24   | Interrupt Pending of Source |
+|   23   |   ro   |   0x0   | P_23   | Interrupt Pending of Source |
+|   22   |   ro   |   0x0   | P_22   | Interrupt Pending of Source |
+|   21   |   ro   |   0x0   | P_21   | Interrupt Pending of Source |
+|   20   |   ro   |   0x0   | P_20   | Interrupt Pending of Source |
+|   19   |   ro   |   0x0   | P_19   | Interrupt Pending of Source |
+|   18   |   ro   |   0x0   | P_18   | Interrupt Pending of Source |
+|   17   |   ro   |   0x0   | P_17   | Interrupt Pending of Source |
+|   16   |   ro   |   0x0   | P_16   | Interrupt Pending of Source |
+|   15   |   ro   |   0x0   | P_15   | Interrupt Pending of Source |
+|   14   |   ro   |   0x0   | P_14   | Interrupt Pending of Source |
+|   13   |   ro   |   0x0   | P_13   | Interrupt Pending of Source |
+|   12   |   ro   |   0x0   | P_12   | Interrupt Pending of Source |
+|   11   |   ro   |   0x0   | P_11   | Interrupt Pending of Source |
+|   10   |   ro   |   0x0   | P_10   | Interrupt Pending of Source |
+|   9    |   ro   |   0x0   | P_9    | Interrupt Pending of Source |
+|   8    |   ro   |   0x0   | P_8    | Interrupt Pending of Source |
+|   7    |   ro   |   0x0   | P_7    | Interrupt Pending of Source |
+|   6    |   ro   |   0x0   | P_6    | Interrupt Pending of Source |
+|   5    |   ro   |   0x0   | P_5    | Interrupt Pending of Source |
+|   4    |   ro   |   0x0   | P_4    | Interrupt Pending of Source |
+|   3    |   ro   |   0x0   | P_3    | Interrupt Pending of Source |
+|   2    |   ro   |   0x0   | P_2    | Interrupt Pending of Source |
+|   1    |   ro   |   0x0   | P_1    | Interrupt Pending of Source |
+|   0    |   ro   |   0x0   | P_0    | Interrupt Pending of Source |
+
+## IE0
+Interrupt Enable for Target 0
+- Offset: `0x2000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "E_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                |
+|:------:|:------:|:-------:|:-------|:---------------------------|
+|   31   |   rw   |   0x0   | E_31   | Interrupt Enable of Source |
+|   30   |   rw   |   0x0   | E_30   | Interrupt Enable of Source |
+|   29   |   rw   |   0x0   | E_29   | Interrupt Enable of Source |
+|   28   |   rw   |   0x0   | E_28   | Interrupt Enable of Source |
+|   27   |   rw   |   0x0   | E_27   | Interrupt Enable of Source |
+|   26   |   rw   |   0x0   | E_26   | Interrupt Enable of Source |
+|   25   |   rw   |   0x0   | E_25   | Interrupt Enable of Source |
+|   24   |   rw   |   0x0   | E_24   | Interrupt Enable of Source |
+|   23   |   rw   |   0x0   | E_23   | Interrupt Enable of Source |
+|   22   |   rw   |   0x0   | E_22   | Interrupt Enable of Source |
+|   21   |   rw   |   0x0   | E_21   | Interrupt Enable of Source |
+|   20   |   rw   |   0x0   | E_20   | Interrupt Enable of Source |
+|   19   |   rw   |   0x0   | E_19   | Interrupt Enable of Source |
+|   18   |   rw   |   0x0   | E_18   | Interrupt Enable of Source |
+|   17   |   rw   |   0x0   | E_17   | Interrupt Enable of Source |
+|   16   |   rw   |   0x0   | E_16   | Interrupt Enable of Source |
+|   15   |   rw   |   0x0   | E_15   | Interrupt Enable of Source |
+|   14   |   rw   |   0x0   | E_14   | Interrupt Enable of Source |
+|   13   |   rw   |   0x0   | E_13   | Interrupt Enable of Source |
+|   12   |   rw   |   0x0   | E_12   | Interrupt Enable of Source |
+|   11   |   rw   |   0x0   | E_11   | Interrupt Enable of Source |
+|   10   |   rw   |   0x0   | E_10   | Interrupt Enable of Source |
+|   9    |   rw   |   0x0   | E_9    | Interrupt Enable of Source |
+|   8    |   rw   |   0x0   | E_8    | Interrupt Enable of Source |
+|   7    |   rw   |   0x0   | E_7    | Interrupt Enable of Source |
+|   6    |   rw   |   0x0   | E_6    | Interrupt Enable of Source |
+|   5    |   rw   |   0x0   | E_5    | Interrupt Enable of Source |
+|   4    |   rw   |   0x0   | E_4    | Interrupt Enable of Source |
+|   3    |   rw   |   0x0   | E_3    | Interrupt Enable of Source |
+|   2    |   rw   |   0x0   | E_2    | Interrupt Enable of Source |
+|   1    |   rw   |   0x0   | E_1    | Interrupt Enable of Source |
+|   0    |   rw   |   0x0   | E_0    | Interrupt Enable of Source |
+
+## THRESHOLD0
+Threshold of priority for Target 0
+- Offset: `0x200000`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "THRESHOLD0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:3  |        |         |            | Reserved      |
+|  2:0   |   rw   |   0x0   | THRESHOLD0 |               |
+
+## CC0
+Claim interrupt by read, complete interrupt by write for Target 0.
+Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.
+- Offset: `0x200004`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CC0", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:5  |        |         |        | Reserved      |
+|  4:0   |   rw   |    x    | CC0    |               |
+
+## MSIP0
+msip for Hart 0.
+Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.
+- Offset: `0x4000000`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSIP0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:1  |        |         |        | Reserved                            |
+|   0    |   rw   |   0x0   | MSIP0  | Software Interrupt Pending register |
+
+## ALERT_TEST
+Alert Test Register.
+- Offset: `0x4004000`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                        |
+|:------:|:------:|:-------:|:------------|:---------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                           |
+|   0    |   wo   |    x    | fatal_fault | 'Write 1 to trigger one alert event of this kind.' |
+
+
+
+## safety_island / doc / registers.md
+
+## Summary
+
+| Name                                        | Offset   |   Length | Description                            |
+|:--------------------------------------------|:---------|---------:|:---------------------------------------|
+| safety_soc_ctrl.[`bootaddr`](#bootaddr)     | 0x0      |        4 | Core Boot Address                      |
+| safety_soc_ctrl.[`fetchen`](#fetchen)       | 0x4      |        4 | Core Fetch Enable                      |
+| safety_soc_ctrl.[`corestatus`](#corestatus) | 0x8      |        4 | Core Return Status (return value, EOC) |
+| safety_soc_ctrl.[`bootmode`](#bootmode)     | 0xc      |        4 | Core Boot Mode                         |
+
+## bootaddr
+Core Boot Address
+- Offset: `0x0`
+- Reset default: `0x1a000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description   |
+|:------:|:------:|:----------:|:---------|:--------------|
+|  31:0  |   rw   | 0x1a000000 | bootaddr | Boot Address  |
+
+## fetchen
+Core Fetch Enable
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:1  |        |         |         | Reserved      |
+|   0    |   rw   |   0x0   | fetchen | Fetch Enable  |
+
+## corestatus
+Core Return Status (return value, EOC)
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                             |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) |
+
+## bootmode
+Core Boot Mode
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:2  |        |         |          | Reserved      |
+|  1:0   |   rw   |   0x0   | bootmode | Boot Mode     |
+
+
+
+## serial_link / doc / registers.md
+
+## Summary
+
+| Name                                                                      | Offset   |   Length | Description                                                                   |
+|:--------------------------------------------------------------------------|:---------|---------:|:------------------------------------------------------------------------------|
+| serial_link.[`CTRL`](#ctrl)                                               | 0x0      |        4 | Global clock, isolation and reset control configuration                       |
+| serial_link.[`ISOLATED`](#isolated)                                       | 0x4      |        4 | Isolation status of AXI ports                                                 |
+| serial_link.[`TX_PHY_CLK_DIV_0`](#tx_phy_clk_div)                         | 0x8      |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_1`](#tx_phy_clk_div)                         | 0xc      |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_2`](#tx_phy_clk_div)                         | 0x10     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_3`](#tx_phy_clk_div)                         | 0x14     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_4`](#tx_phy_clk_div)                         | 0x18     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_5`](#tx_phy_clk_div)                         | 0x1c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_6`](#tx_phy_clk_div)                         | 0x20     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_7`](#tx_phy_clk_div)                         | 0x24     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_8`](#tx_phy_clk_div)                         | 0x28     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_9`](#tx_phy_clk_div)                         | 0x2c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_10`](#tx_phy_clk_div)                        | 0x30     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_11`](#tx_phy_clk_div)                        | 0x34     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_12`](#tx_phy_clk_div)                        | 0x38     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_13`](#tx_phy_clk_div)                        | 0x3c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_14`](#tx_phy_clk_div)                        | 0x40     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_15`](#tx_phy_clk_div)                        | 0x44     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_16`](#tx_phy_clk_div)                        | 0x48     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_17`](#tx_phy_clk_div)                        | 0x4c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_18`](#tx_phy_clk_div)                        | 0x50     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_19`](#tx_phy_clk_div)                        | 0x54     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_20`](#tx_phy_clk_div)                        | 0x58     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_21`](#tx_phy_clk_div)                        | 0x5c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_22`](#tx_phy_clk_div)                        | 0x60     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_23`](#tx_phy_clk_div)                        | 0x64     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_24`](#tx_phy_clk_div)                        | 0x68     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_25`](#tx_phy_clk_div)                        | 0x6c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_26`](#tx_phy_clk_div)                        | 0x70     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_27`](#tx_phy_clk_div)                        | 0x74     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_28`](#tx_phy_clk_div)                        | 0x78     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_29`](#tx_phy_clk_div)                        | 0x7c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_30`](#tx_phy_clk_div)                        | 0x80     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_31`](#tx_phy_clk_div)                        | 0x84     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_32`](#tx_phy_clk_div)                        | 0x88     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_33`](#tx_phy_clk_div)                        | 0x8c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_34`](#tx_phy_clk_div)                        | 0x90     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_35`](#tx_phy_clk_div)                        | 0x94     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_36`](#tx_phy_clk_div)                        | 0x98     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_37`](#tx_phy_clk_div)                        | 0x9c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_START_0`](#tx_phy_clk_start)                     | 0xa0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_1`](#tx_phy_clk_start)                     | 0xa4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_2`](#tx_phy_clk_start)                     | 0xa8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_3`](#tx_phy_clk_start)                     | 0xac     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_4`](#tx_phy_clk_start)                     | 0xb0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_5`](#tx_phy_clk_start)                     | 0xb4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_6`](#tx_phy_clk_start)                     | 0xb8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_7`](#tx_phy_clk_start)                     | 0xbc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_8`](#tx_phy_clk_start)                     | 0xc0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_9`](#tx_phy_clk_start)                     | 0xc4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_10`](#tx_phy_clk_start)                    | 0xc8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_11`](#tx_phy_clk_start)                    | 0xcc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_12`](#tx_phy_clk_start)                    | 0xd0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_13`](#tx_phy_clk_start)                    | 0xd4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_14`](#tx_phy_clk_start)                    | 0xd8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_15`](#tx_phy_clk_start)                    | 0xdc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_16`](#tx_phy_clk_start)                    | 0xe0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_17`](#tx_phy_clk_start)                    | 0xe4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_18`](#tx_phy_clk_start)                    | 0xe8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_19`](#tx_phy_clk_start)                    | 0xec     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_20`](#tx_phy_clk_start)                    | 0xf0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_21`](#tx_phy_clk_start)                    | 0xf4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_22`](#tx_phy_clk_start)                    | 0xf8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_23`](#tx_phy_clk_start)                    | 0xfc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_24`](#tx_phy_clk_start)                    | 0x100    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_25`](#tx_phy_clk_start)                    | 0x104    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_26`](#tx_phy_clk_start)                    | 0x108    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_27`](#tx_phy_clk_start)                    | 0x10c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_28`](#tx_phy_clk_start)                    | 0x110    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_29`](#tx_phy_clk_start)                    | 0x114    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_30`](#tx_phy_clk_start)                    | 0x118    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_31`](#tx_phy_clk_start)                    | 0x11c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_32`](#tx_phy_clk_start)                    | 0x120    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_33`](#tx_phy_clk_start)                    | 0x124    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_34`](#tx_phy_clk_start)                    | 0x128    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_35`](#tx_phy_clk_start)                    | 0x12c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_36`](#tx_phy_clk_start)                    | 0x130    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_37`](#tx_phy_clk_start)                    | 0x134    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_END_0`](#tx_phy_clk_end)                         | 0x138    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_1`](#tx_phy_clk_end)                         | 0x13c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_2`](#tx_phy_clk_end)                         | 0x140    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_3`](#tx_phy_clk_end)                         | 0x144    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_4`](#tx_phy_clk_end)                         | 0x148    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_5`](#tx_phy_clk_end)                         | 0x14c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_6`](#tx_phy_clk_end)                         | 0x150    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_7`](#tx_phy_clk_end)                         | 0x154    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_8`](#tx_phy_clk_end)                         | 0x158    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_9`](#tx_phy_clk_end)                         | 0x15c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_10`](#tx_phy_clk_end)                        | 0x160    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_11`](#tx_phy_clk_end)                        | 0x164    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_12`](#tx_phy_clk_end)                        | 0x168    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_13`](#tx_phy_clk_end)                        | 0x16c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_14`](#tx_phy_clk_end)                        | 0x170    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_15`](#tx_phy_clk_end)                        | 0x174    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_16`](#tx_phy_clk_end)                        | 0x178    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_17`](#tx_phy_clk_end)                        | 0x17c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_18`](#tx_phy_clk_end)                        | 0x180    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_19`](#tx_phy_clk_end)                        | 0x184    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_20`](#tx_phy_clk_end)                        | 0x188    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_21`](#tx_phy_clk_end)                        | 0x18c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_22`](#tx_phy_clk_end)                        | 0x190    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_23`](#tx_phy_clk_end)                        | 0x194    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_24`](#tx_phy_clk_end)                        | 0x198    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_25`](#tx_phy_clk_end)                        | 0x19c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_26`](#tx_phy_clk_end)                        | 0x1a0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_27`](#tx_phy_clk_end)                        | 0x1a4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_28`](#tx_phy_clk_end)                        | 0x1a8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_29`](#tx_phy_clk_end)                        | 0x1ac    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_30`](#tx_phy_clk_end)                        | 0x1b0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_31`](#tx_phy_clk_end)                        | 0x1b4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_32`](#tx_phy_clk_end)                        | 0x1b8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_33`](#tx_phy_clk_end)                        | 0x1bc    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_34`](#tx_phy_clk_end)                        | 0x1c0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_35`](#tx_phy_clk_end)                        | 0x1c4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_36`](#tx_phy_clk_end)                        | 0x1c8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_37`](#tx_phy_clk_end)                        | 0x1cc    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`RAW_MODE_EN`](#raw_mode_en)                                 | 0x1d0    |        4 | Enables Raw mode                                                              |
+| serial_link.[`RAW_MODE_IN_CH_SEL`](#raw_mode_in_ch_sel)                   | 0x1d4    |        4 | Receive channel select in RAW mode                                            |
+| serial_link.[`RAW_MODE_IN_DATA_VALID_0`](#RAW_MODE_IN_DATA_VALID_0)       | 0x1d8    |        4 | Mask for valid data in RX FIFOs during RAW mode.                              |
+| serial_link.[`RAW_MODE_IN_DATA_VALID_1`](#RAW_MODE_IN_DATA_VALID_1)       | 0x1dc    |        4 | Mask for valid data in RX FIFOs during RAW mode.                              |
+| serial_link.[`RAW_MODE_IN_DATA`](#raw_mode_in_data)                       | 0x1e0    |        4 | Data received by the selected channel in RAW mode                             |
+| serial_link.[`RAW_MODE_OUT_CH_MASK_0`](#RAW_MODE_OUT_CH_MASK_0)           | 0x1e4    |        4 | Selects channels to send out data in RAW mode, '1 corresponds to broadcasting |
+| serial_link.[`RAW_MODE_OUT_CH_MASK_1`](#RAW_MODE_OUT_CH_MASK_1)           | 0x1e8    |        4 | Selects channels to send out data in RAW mode, '1 corresponds to broadcasting |
+| serial_link.[`RAW_MODE_OUT_DATA_FIFO`](#raw_mode_out_data_fifo)           | 0x1ec    |        4 | Data that will be pushed to the RAW mode output FIFO                          |
+| serial_link.[`RAW_MODE_OUT_DATA_FIFO_CTRL`](#raw_mode_out_data_fifo_ctrl) | 0x1f0    |        4 | Status and control register for the RAW mode data out FIFO                    |
+| serial_link.[`RAW_MODE_OUT_EN`](#raw_mode_out_en)                         | 0x1f4    |        4 | Enable transmission of data currently hold in the output FIFO                 |
+| serial_link.[`FLOW_CONTROL_FIFO_CLEAR`](#flow_control_fifo_clear)         | 0x1f8    |        4 | Clears the flow control Fifo                                                  |
+| serial_link.[`CHANNEL_ALLOC_TX_CFG`](#channel_alloc_tx_cfg)               | 0x1fc    |        4 | Configuration settings for the TX side in the channel allocator               |
+| serial_link.[`CHANNEL_ALLOC_TX_CH_EN_0`](#CHANNEL_ALLOC_TX_CH_EN_0)       | 0x200    |        4 | Channel enable mask for the TX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_TX_CH_EN_1`](#CHANNEL_ALLOC_TX_CH_EN_1)       | 0x204    |        4 | Channel enable mask for the TX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_TX_CTRL`](#channel_alloc_tx_ctrl)             | 0x208    |        4 | Soft clear or force flush the TX side of the channel allocator                |
+| serial_link.[`CHANNEL_ALLOC_RX_CFG`](#channel_alloc_rx_cfg)               | 0x20c    |        4 | Configuration settings for the RX side in the channel allocator               |
+| serial_link.[`CHANNEL_ALLOC_RX_CTRL`](#channel_alloc_rx_ctrl)             | 0x210    |        4 | Soft clear the RX side of the channel allocator                               |
+| serial_link.[`CHANNEL_ALLOC_RX_CH_EN_0`](#CHANNEL_ALLOC_RX_CH_EN_0)       | 0x214    |        4 | Channel enable mask for the RX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_RX_CH_EN_1`](#CHANNEL_ALLOC_RX_CH_EN_1)       | 0x218    |        4 | Channel enable mask for the RX side.                                          |
+
+## CTRL
+Global clock, isolation and reset control configuration
+- Offset: `0x0`
+- Reset default: `0x302`
+- Reset mask: `0x303`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_ena", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reset_n", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "axi_in_isolate", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "axi_out_isolate", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                                                        |
+|:------:|:------:|:-------:|:----------------|:-------------------------------------------------------------------|
+| 31:10  |        |         |                 | Reserved                                                           |
+|   9    |   rw   |   0x1   | axi_out_isolate | Isolate AXI master out port. (active-high)                         |
+|   8    |   rw   |   0x1   | axi_in_isolate  | Isolate AXI slave in port. (active-high)                           |
+|  7:2   |        |         |                 | Reserved                                                           |
+|   1    |   rw   |   0x1   | reset_n         | SW controlled synchronous reset. (active-low)                      |
+|   0    |   rw   |   0x0   | clk_ena         | Clock gate enable for network, link, physical layer. (active-high) |
+
+## ISOLATED
+Isolation status of AXI ports
+- Offset: `0x4`
+- Reset default: `0x3`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "axi_in", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "axi_out", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                 |
+|:------:|:------:|:-------:|:--------|:----------------------------|
+|  31:2  |        |         |         | Reserved                    |
+|   1    |   ro   |   0x1   | axi_out | master out isolation status |
+|   0    |   ro   |   0x1   | axi_in  | slave in isolation status   |
+
+## TX_PHY_CLK_DIV
+Holds clock divider factor for forwarded clock of the TX Phys
+- Reset default: `0x8`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name              | Offset   |
+|:------------------|:---------|
+| TX_PHY_CLK_DIV_0  | 0x8      |
+| TX_PHY_CLK_DIV_1  | 0xc      |
+| TX_PHY_CLK_DIV_2  | 0x10     |
+| TX_PHY_CLK_DIV_3  | 0x14     |
+| TX_PHY_CLK_DIV_4  | 0x18     |
+| TX_PHY_CLK_DIV_5  | 0x1c     |
+| TX_PHY_CLK_DIV_6  | 0x20     |
+| TX_PHY_CLK_DIV_7  | 0x24     |
+| TX_PHY_CLK_DIV_8  | 0x28     |
+| TX_PHY_CLK_DIV_9  | 0x2c     |
+| TX_PHY_CLK_DIV_10 | 0x30     |
+| TX_PHY_CLK_DIV_11 | 0x34     |
+| TX_PHY_CLK_DIV_12 | 0x38     |
+| TX_PHY_CLK_DIV_13 | 0x3c     |
+| TX_PHY_CLK_DIV_14 | 0x40     |
+| TX_PHY_CLK_DIV_15 | 0x44     |
+| TX_PHY_CLK_DIV_16 | 0x48     |
+| TX_PHY_CLK_DIV_17 | 0x4c     |
+| TX_PHY_CLK_DIV_18 | 0x50     |
+| TX_PHY_CLK_DIV_19 | 0x54     |
+| TX_PHY_CLK_DIV_20 | 0x58     |
+| TX_PHY_CLK_DIV_21 | 0x5c     |
+| TX_PHY_CLK_DIV_22 | 0x60     |
+| TX_PHY_CLK_DIV_23 | 0x64     |
+| TX_PHY_CLK_DIV_24 | 0x68     |
+| TX_PHY_CLK_DIV_25 | 0x6c     |
+| TX_PHY_CLK_DIV_26 | 0x70     |
+| TX_PHY_CLK_DIV_27 | 0x74     |
+| TX_PHY_CLK_DIV_28 | 0x78     |
+| TX_PHY_CLK_DIV_29 | 0x7c     |
+| TX_PHY_CLK_DIV_30 | 0x80     |
+| TX_PHY_CLK_DIV_31 | 0x84     |
+| TX_PHY_CLK_DIV_32 | 0x88     |
+| TX_PHY_CLK_DIV_33 | 0x8c     |
+| TX_PHY_CLK_DIV_34 | 0x90     |
+| TX_PHY_CLK_DIV_35 | 0x94     |
+| TX_PHY_CLK_DIV_36 | 0x98     |
+| TX_PHY_CLK_DIV_37 | 0x9c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_divs", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------|
+| 31:11  |        |         |          | Reserved                          |
+|  10:0  |   rw   |   0x8   | clk_divs | Clock division factor of TX clock |
+
+## TX_PHY_CLK_START
+Controls duty cycle and phase of rising edge in TX Phys
+- Reset default: `0x2`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| TX_PHY_CLK_START_0  | 0xa0     |
+| TX_PHY_CLK_START_1  | 0xa4     |
+| TX_PHY_CLK_START_2  | 0xa8     |
+| TX_PHY_CLK_START_3  | 0xac     |
+| TX_PHY_CLK_START_4  | 0xb0     |
+| TX_PHY_CLK_START_5  | 0xb4     |
+| TX_PHY_CLK_START_6  | 0xb8     |
+| TX_PHY_CLK_START_7  | 0xbc     |
+| TX_PHY_CLK_START_8  | 0xc0     |
+| TX_PHY_CLK_START_9  | 0xc4     |
+| TX_PHY_CLK_START_10 | 0xc8     |
+| TX_PHY_CLK_START_11 | 0xcc     |
+| TX_PHY_CLK_START_12 | 0xd0     |
+| TX_PHY_CLK_START_13 | 0xd4     |
+| TX_PHY_CLK_START_14 | 0xd8     |
+| TX_PHY_CLK_START_15 | 0xdc     |
+| TX_PHY_CLK_START_16 | 0xe0     |
+| TX_PHY_CLK_START_17 | 0xe4     |
+| TX_PHY_CLK_START_18 | 0xe8     |
+| TX_PHY_CLK_START_19 | 0xec     |
+| TX_PHY_CLK_START_20 | 0xf0     |
+| TX_PHY_CLK_START_21 | 0xf4     |
+| TX_PHY_CLK_START_22 | 0xf8     |
+| TX_PHY_CLK_START_23 | 0xfc     |
+| TX_PHY_CLK_START_24 | 0x100    |
+| TX_PHY_CLK_START_25 | 0x104    |
+| TX_PHY_CLK_START_26 | 0x108    |
+| TX_PHY_CLK_START_27 | 0x10c    |
+| TX_PHY_CLK_START_28 | 0x110    |
+| TX_PHY_CLK_START_29 | 0x114    |
+| TX_PHY_CLK_START_30 | 0x118    |
+| TX_PHY_CLK_START_31 | 0x11c    |
+| TX_PHY_CLK_START_32 | 0x120    |
+| TX_PHY_CLK_START_33 | 0x124    |
+| TX_PHY_CLK_START_34 | 0x128    |
+| TX_PHY_CLK_START_35 | 0x12c    |
+| TX_PHY_CLK_START_36 | 0x130    |
+| TX_PHY_CLK_START_37 | 0x134    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_shift_start", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                             |
+|:------:|:------:|:-------:|:----------------|:----------------------------------------|
+| 31:11  |        |         |                 | Reserved                                |
+|  10:0  |   rw   |   0x2   | clk_shift_start | Positive Edge of divided, shifted clock |
+
+## TX_PHY_CLK_END
+Controls duty cycle and phase of falling edge in TX Phys
+- Reset default: `0x6`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name              | Offset   |
+|:------------------|:---------|
+| TX_PHY_CLK_END_0  | 0x138    |
+| TX_PHY_CLK_END_1  | 0x13c    |
+| TX_PHY_CLK_END_2  | 0x140    |
+| TX_PHY_CLK_END_3  | 0x144    |
+| TX_PHY_CLK_END_4  | 0x148    |
+| TX_PHY_CLK_END_5  | 0x14c    |
+| TX_PHY_CLK_END_6  | 0x150    |
+| TX_PHY_CLK_END_7  | 0x154    |
+| TX_PHY_CLK_END_8  | 0x158    |
+| TX_PHY_CLK_END_9  | 0x15c    |
+| TX_PHY_CLK_END_10 | 0x160    |
+| TX_PHY_CLK_END_11 | 0x164    |
+| TX_PHY_CLK_END_12 | 0x168    |
+| TX_PHY_CLK_END_13 | 0x16c    |
+| TX_PHY_CLK_END_14 | 0x170    |
+| TX_PHY_CLK_END_15 | 0x174    |
+| TX_PHY_CLK_END_16 | 0x178    |
+| TX_PHY_CLK_END_17 | 0x17c    |
+| TX_PHY_CLK_END_18 | 0x180    |
+| TX_PHY_CLK_END_19 | 0x184    |
+| TX_PHY_CLK_END_20 | 0x188    |
+| TX_PHY_CLK_END_21 | 0x18c    |
+| TX_PHY_CLK_END_22 | 0x190    |
+| TX_PHY_CLK_END_23 | 0x194    |
+| TX_PHY_CLK_END_24 | 0x198    |
+| TX_PHY_CLK_END_25 | 0x19c    |
+| TX_PHY_CLK_END_26 | 0x1a0    |
+| TX_PHY_CLK_END_27 | 0x1a4    |
+| TX_PHY_CLK_END_28 | 0x1a8    |
+| TX_PHY_CLK_END_29 | 0x1ac    |
+| TX_PHY_CLK_END_30 | 0x1b0    |
+| TX_PHY_CLK_END_31 | 0x1b4    |
+| TX_PHY_CLK_END_32 | 0x1b8    |
+| TX_PHY_CLK_END_33 | 0x1bc    |
+| TX_PHY_CLK_END_34 | 0x1c0    |
+| TX_PHY_CLK_END_35 | 0x1c4    |
+| TX_PHY_CLK_END_36 | 0x1c8    |
+| TX_PHY_CLK_END_37 | 0x1cc    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_shift_end", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                             |
+|:------:|:------:|:-------:|:--------------|:----------------------------------------|
+| 31:11  |        |         |               | Reserved                                |
+|  10:0  |   rw   |   0x6   | clk_shift_end | Negative Edge of divided, shifted clock |
+
+## RAW_MODE_EN
+Enables Raw mode
+- Offset: `0x1d0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_EN", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description   |
+|:------:|:------:|:-------:|:------------|:--------------|
+|  31:1  |        |         |             | Reserved      |
+|   0    |   wo   |   0x0   | RAW_MODE_EN |               |
+
+## RAW_MODE_IN_CH_SEL
+Receive channel select in RAW mode
+- Offset: `0x1d4`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_CH_SEL", "bits": 6, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:6  |        |         |                    | Reserved      |
+|  5:0   |   wo   |   0x0   | RAW_MODE_IN_CH_SEL |               |
+
+## RAW_MODE_IN_DATA_VALID_0
+Mask for valid data in RX FIFOs during RAW mode.
+- Offset: `0x1d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA_VALID_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_9", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_10", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_11", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_12", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_13", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_14", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_15", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_16", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_17", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_18", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_19", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_20", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_21", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_22", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_23", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_24", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_25", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_26", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_27", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_28", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_29", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_30", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_31", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_31 |               |
+|   30   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_30 |               |
+|   29   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_29 |               |
+|   28   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_28 |               |
+|   27   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_27 |               |
+|   26   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_26 |               |
+|   25   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_25 |               |
+|   24   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_24 |               |
+|   23   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_23 |               |
+|   22   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_22 |               |
+|   21   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_21 |               |
+|   20   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_20 |               |
+|   19   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_19 |               |
+|   18   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_18 |               |
+|   17   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_17 |               |
+|   16   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_16 |               |
+|   15   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_15 |               |
+|   14   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_14 |               |
+|   13   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_13 |               |
+|   12   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_12 |               |
+|   11   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_11 |               |
+|   10   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_10 |               |
+|   9    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_9  |               |
+|   8    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_8  |               |
+|   7    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_7  |               |
+|   6    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_6  |               |
+|   5    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_5  |               |
+|   4    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_4  |               |
+|   3    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_3  |               |
+|   2    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_2  |               |
+|   1    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_1  |               |
+|   0    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_0  |               |
+
+## RAW_MODE_IN_DATA_VALID_1
+Mask for valid data in RX FIFOs during RAW mode.
+- Offset: `0x1dc`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA_VALID_32", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_33", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_34", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_35", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_36", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_37", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_37 | For RAW_MODE_IN_DATA_VALID1 |
+|   4    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_36 | For RAW_MODE_IN_DATA_VALID1 |
+|   3    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_35 | For RAW_MODE_IN_DATA_VALID1 |
+|   2    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_34 | For RAW_MODE_IN_DATA_VALID1 |
+|   1    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_33 | For RAW_MODE_IN_DATA_VALID1 |
+|   0    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_32 | For RAW_MODE_IN_DATA_VALID1 |
+
+## RAW_MODE_IN_DATA
+Data received by the selected channel in RAW mode
+- Offset: `0x1e0`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:16  |        |         |                  | Reserved      |
+|  15:0  |   ro   |    x    | RAW_MODE_IN_DATA |               |
+
+## RAW_MODE_OUT_CH_MASK_0
+Selects channels to send out data in RAW mode, '1 corresponds to broadcasting
+- Offset: `0x1e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_CH_MASK_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_8", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_9", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_10", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_11", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_12", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_13", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_14", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_15", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_16", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_17", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_18", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_19", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_20", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_21", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_22", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_23", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_24", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_25", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_26", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_27", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_28", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_29", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_30", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_31", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|   31   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_31 |               |
+|   30   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_30 |               |
+|   29   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_29 |               |
+|   28   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_28 |               |
+|   27   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_27 |               |
+|   26   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_26 |               |
+|   25   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_25 |               |
+|   24   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_24 |               |
+|   23   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_23 |               |
+|   22   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_22 |               |
+|   21   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_21 |               |
+|   20   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_20 |               |
+|   19   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_19 |               |
+|   18   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_18 |               |
+|   17   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_17 |               |
+|   16   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_16 |               |
+|   15   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_15 |               |
+|   14   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_14 |               |
+|   13   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_13 |               |
+|   12   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_12 |               |
+|   11   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_11 |               |
+|   10   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_10 |               |
+|   9    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_9  |               |
+|   8    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_8  |               |
+|   7    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_7  |               |
+|   6    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_6  |               |
+|   5    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_5  |               |
+|   4    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_4  |               |
+|   3    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_3  |               |
+|   2    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_2  |               |
+|   1    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_1  |               |
+|   0    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_0  |               |
+
+## RAW_MODE_OUT_CH_MASK_1
+Selects channels to send out data in RAW mode, '1 corresponds to broadcasting
+- Offset: `0x1e8`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_CH_MASK_32", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_33", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_34", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_35", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_36", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_37", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description               |
+|:------:|:------:|:-------:|:------------------------|:--------------------------|
+|  31:6  |        |         |                         | Reserved                  |
+|   5    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_37 | For RAW_MODE_OUT_CH_MASK1 |
+|   4    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_36 | For RAW_MODE_OUT_CH_MASK1 |
+|   3    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_35 | For RAW_MODE_OUT_CH_MASK1 |
+|   2    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_34 | For RAW_MODE_OUT_CH_MASK1 |
+|   1    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_33 | For RAW_MODE_OUT_CH_MASK1 |
+|   0    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_32 | For RAW_MODE_OUT_CH_MASK1 |
+
+## RAW_MODE_OUT_DATA_FIFO
+Data that will be pushed to the RAW mode output FIFO
+- Offset: `0x1ec`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_DATA_FIFO", "bits": 16, "attr": ["wo"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:16  |        |         |                        | Reserved      |
+|  15:0  |   wo   |   0x0   | RAW_MODE_OUT_DATA_FIFO |               |
+
+## RAW_MODE_OUT_DATA_FIFO_CTRL
+Status and control register for the RAW mode data out FIFO
+- Offset: `0x1f0`
+- Reset default: `0x0`
+- Reset mask: `0x80000701`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 7}, {"name": "fill_state", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 20}, {"name": "is_full", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                                       |
+|:------:|:------:|:-------:|:-----------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   ro   |   0x0   | is_full    | If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again. |
+| 30:11  |        |         |            | Reserved                                                                                                                                                          |
+|  10:8  |   ro   |   0x0   | fill_state | The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.                                                                        |
+|  7:1   |        |         |            | Reserved                                                                                                                                                          |
+|   0    |   wo   |    x    | clear      | Clears the raw mode TX FIFO.                                                                                                                                      |
+
+## RAW_MODE_OUT_EN
+Enable transmission of data currently hold in the output FIFO
+- Offset: `0x1f4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description   |
+|:------:|:------:|:-------:|:----------------|:--------------|
+|  31:1  |        |         |                 | Reserved      |
+|   0    |   rw   |   0x0   | RAW_MODE_OUT_EN |               |
+
+## FLOW_CONTROL_FIFO_CLEAR
+Clears the flow control Fifo
+- Offset: `0x1f8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FLOW_CONTROL_FIFO_CLEAR", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   wo   |   0x0   | FLOW_CONTROL_FIFO_CLEAR |               |
+
+## CHANNEL_ALLOC_TX_CFG
+Configuration settings for the TX side in the channel allocator
+- Offset: `0x1fc`
+- Reset default: `0x203`
+- Reset mask: `0xff03`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypass_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auto_flush_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "auto_flush_count", "bits": 8, "attr": ["rw"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                  |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------|
+| 31:16  |        |         |                  | Reserved                                                                                     |
+|  15:8  |   rw   |   0x2   | auto_flush_count | The number of cycles to wait before auto flushing (sending) packets in the channel allocator |
+|  7:2   |        |         |                  | Reserved                                                                                     |
+|   1    |   rw   |   0x1   | auto_flush_en    | Enable the auto-flush feature of the TX side in the channel allocator                        |
+|   0    |   rw   |   0x1   | bypass_en        | Enable bypassing the TX channel allocator                                                    |
+
+## CHANNEL_ALLOC_TX_CH_EN_0
+Channel enable mask for the TX side.
+- Offset: `0x200`
+- Reset default: `0xffffffff`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_TX_CH_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_31 |               |
+|   30   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_30 |               |
+|   29   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_29 |               |
+|   28   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_28 |               |
+|   27   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_27 |               |
+|   26   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_26 |               |
+|   25   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_25 |               |
+|   24   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_24 |               |
+|   23   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_23 |               |
+|   22   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_22 |               |
+|   21   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_21 |               |
+|   20   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_20 |               |
+|   19   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_19 |               |
+|   18   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_18 |               |
+|   17   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_17 |               |
+|   16   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_16 |               |
+|   15   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_15 |               |
+|   14   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_14 |               |
+|   13   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_13 |               |
+|   12   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_12 |               |
+|   11   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_11 |               |
+|   10   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_10 |               |
+|   9    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_9  |               |
+|   8    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_8  |               |
+|   7    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_7  |               |
+|   6    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_6  |               |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_5  |               |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_4  |               |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_3  |               |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_2  |               |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_1  |               |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_0  |               |
+
+## CHANNEL_ALLOC_TX_CH_EN_1
+Channel enable mask for the TX side.
+- Offset: `0x204`
+- Reset default: `0x3f`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_TX_CH_EN_32", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_33", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_34", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_35", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_36", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_37", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_37 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_36 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_35 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_34 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_33 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_32 | For CHANNEL_ALLOC_TX_CH_EN1 |
+
+## CHANNEL_ALLOC_TX_CTRL
+Soft clear or force flush the TX side of the channel allocator
+- Offset: `0x208`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "flush", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------|
+|  31:2  |        |         |        | Reserved                                                                 |
+|   1    |   wo   |    x    | flush  | Flush (transmit remaining data) in the TX side of the channel allocator. |
+|   0    |   wo   |    x    | clear  | Software clear the TX side of the channel allocator                      |
+
+## CHANNEL_ALLOC_RX_CFG
+Configuration settings for the RX side in the channel allocator
+- Offset: `0x20c`
+- Reset default: `0x10203`
+- Reset mask: `0x1ff03`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypass_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auto_flush_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "auto_flush_count", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "sync_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                                    |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------------|
+| 31:17  |        |         |                  | Reserved                                                                                                       |
+|   16   |   rw   |   0x1   | sync_en          | Enable (1) or disable (0) the synchronization barrier between the channels (needs to be disabled in raw mode). |
+|  15:8  |   rw   |   0x2   | auto_flush_count | The number of cycles to wait before synchronizing on partial packets on the RX side                            |
+|  7:2   |        |         |                  | Reserved                                                                                                       |
+|   1    |   rw   |   0x1   | auto_flush_en    | Enable the auto-flush feature of the RX side in the channel allocator                                          |
+|   0    |   rw   |   0x1   | bypass_en        | Enable bypassing the RX channel allocator                                                                      |
+
+## CHANNEL_ALLOC_RX_CTRL
+Soft clear the RX side of the channel allocator
+- Offset: `0x210`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                            |
+|   0    |   wo   |    x    | clear  | Software clear the TX side of the channel allocator |
+
+## CHANNEL_ALLOC_RX_CH_EN_0
+Channel enable mask for the RX side.
+- Offset: `0x214`
+- Reset default: `0xffffffff`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_RX_CH_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_31 |               |
+|   30   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_30 |               |
+|   29   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_29 |               |
+|   28   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_28 |               |
+|   27   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_27 |               |
+|   26   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_26 |               |
+|   25   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_25 |               |
+|   24   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_24 |               |
+|   23   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_23 |               |
+|   22   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_22 |               |
+|   21   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_21 |               |
+|   20   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_20 |               |
+|   19   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_19 |               |
+|   18   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_18 |               |
+|   17   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_17 |               |
+|   16   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_16 |               |
+|   15   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_15 |               |
+|   14   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_14 |               |
+|   13   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_13 |               |
+|   12   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_12 |               |
+|   11   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_11 |               |
+|   10   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_10 |               |
+|   9    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_9  |               |
+|   8    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_8  |               |
+|   7    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_7  |               |
+|   6    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_6  |               |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_5  |               |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_4  |               |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_3  |               |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_2  |               |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_1  |               |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_0  |               |
+
+## CHANNEL_ALLOC_RX_CH_EN_1
+Channel enable mask for the RX side.
+- Offset: `0x218`
+- Reset default: `0x3f`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_RX_CH_EN_32", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_33", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_34", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_35", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_36", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_37", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_37 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_36 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_35 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_34 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_33 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_32 | For CHANNEL_ALLOC_RX_CH_EN1 |
+
+
+
+## spim / doc / registers.md
+
+## Summary
+
+| Name                                     | Offset   |   Length | Description                                              |
+|:-----------------------------------------|:---------|---------:|:---------------------------------------------------------|
+| spi_host.[`INTR_STATE`](#intr_state)     | 0x0      |        4 | Interrupt State Register                                 |
+| spi_host.[`INTR_ENABLE`](#intr_enable)   | 0x4      |        4 | Interrupt Enable Register                                |
+| spi_host.[`INTR_TEST`](#intr_test)       | 0x8      |        4 | Interrupt Test Register                                  |
+| spi_host.[`ALERT_TEST`](#alert_test)     | 0xc      |        4 | Alert Test Register                                      |
+| spi_host.[`CONTROL`](#control)           | 0x10     |        4 | Control register                                         |
+| spi_host.[`STATUS`](#status)             | 0x14     |        4 | Status register                                          |
+| spi_host.[`CONFIGOPTS`](#configopts)     | 0x18     |        4 | Configuration options register.                          |
+| spi_host.[`CSID`](#csid)                 | 0x1c     |        4 | Chip-Select ID                                           |
+| spi_host.[`COMMAND`](#command)           | 0x20     |        4 | Command Register                                         |
+| spi_host.[`RXDATA`](#rxdata)             | 0x24     |        4 | SPI Receive Data.                                        |
+| spi_host.[`TXDATA`](#txdata)             | 0x28     |        4 | SPI Transmit Data.                                       |
+| spi_host.[`ERROR_ENABLE`](#error_enable) | 0x2c     |        4 | Controls which classes of errors raise an interrupt.     |
+| spi_host.[`ERROR_STATUS`](#error_status) | 0x30     |        4 | Indicates that any errors that have occurred.            |
+| spi_host.[`EVENT_ENABLE`](#event_enable) | 0x34     |        4 | Controls which classes of SPI events raise an interrupt. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                  |
+|:------:|:------:|:-------:|:----------|:---------------------------------------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                                                     |
+|   1    |   ro   |   0x0   | spi_event | Event-related interrupts, see [`EVENT_ENABLE`](#event_enable) register for more information. |
+|   0    |  rw1c  |   0x0   | error     | Error-related interrupts, see [`ERROR_ENABLE`](#error_enable) register for more information. |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                         |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                            |
+|   1    |   rw   |   0x0   | spi_event | Enable interrupt when [`INTR_STATE.spi_event`](#intr_state) is set. |
+|   0    |   rw   |   0x0   | error     | Enable interrupt when [`INTR_STATE.error`](#intr_state) is set.     |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                     |
+|   1    |   wo   |   0x0   | spi_event | Write 1 to force [`INTR_STATE.spi_event`](#intr_state) to 1. |
+|   0    |   wo   |   0x0   | error     | Write 1 to force [`INTR_STATE.error`](#intr_state) to 1.     |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CONTROL
+Control register
+- Offset: `0x10`
+- Reset default: `0x7f`
+- Reset mask: `0xe000ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX_WATERMARK", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TX_WATERMARK", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 13}, {"name": "OUTPUT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SW_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SPIEN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                   |
+|:------:|:------:|:-------:|:---------------------------------------|
+|   31   |   rw   |   0x0   | [SPIEN](#control--spien)               |
+|   30   |   rw   |   0x0   | [SW_RST](#control--sw_rst)             |
+|   29   |   rw   |   0x0   | [OUTPUT_EN](#control--output_en)       |
+| 28:16  |        |         | Reserved                               |
+|  15:8  |   rw   |   0x0   | [TX_WATERMARK](#control--tx_watermark) |
+|  7:0   |   rw   |  0x7f   | [RX_WATERMARK](#control--rx_watermark) |
+
+### CONTROL . SPIEN
+Enables the SPI host.  On reset, this field is 0, meaning
+   that no transactions can proceed.
+
+### CONTROL . SW_RST
+Clears the internal state (not registers) to the reset state when set to 1,
+   including the FIFOs, the CDC's, the core state machine and the shift register.
+   In the current implementation, the CDC FIFOs are drained not reset.
+   Therefore software must confirm that both FIFO's empty before releasing
+   the IP from reset.
+
+### CONTROL . OUTPUT_EN
+Enable the SPI host output buffers for the sck, csb, and sd lines.  This allows
+   the SPI_HOST IP to connect to the same bus as other SPI controllers without
+   interference.
+
+### CONTROL . TX_WATERMARK
+If [`EVENT_ENABLE.TXWM`](#event_enable) is set, the IP will send
+   an interrupt when the depth of the TX FIFO drops below
+   TX_WATERMARK words (32b each).
+
+### CONTROL . RX_WATERMARK
+If [`EVENT_ENABLE.RXWM`](#event_enable) is set, the IP will send
+   an interrupt when the depth of the RX FIFO reaches
+   RX_WATERMARK words (32b each).
+
+## STATUS
+Status register
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffdfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXQD", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "RXQD", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CMDQD", "bits": 4, "attr": ["ro"], "rotate": 0}, {"name": "RXWM", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "BYTEORDER", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXSTALL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXWM", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXSTALL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACTIVE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "READY", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                               |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   ro   |   0x0   | READY     | When high, indicates the SPI host is ready to receive commands. Writing to COMMAND when READY is low is an error, and will trigger an interrupt.                          |
+|   30   |   ro   |   0x0   | ACTIVE    | When high, indicates the SPI host is processing a previously issued command.                                                                                              |
+|   29   |   ro   |   0x0   | TXFULL    | When high, indicates that the transmit data fifo is full. Any further writes to [`TXDATA`](#txdata) will create an error interrupt.                                       |
+|   28   |   ro   |   0x0   | TXEMPTY   | When high, indicates that the transmit data fifo is empty.                                                                                                                |
+|   27   |   ro   |   0x0   | TXSTALL   | If high, signifies that an ongoing transaction has stalled due to lack of data in the TX FIFO                                                                             |
+|   26   |   ro   |   0x0   | TXWM      | If high, the amount of data in the TX FIFO has fallen below the level of [`CONTROL.TX_WATERMARK`](#control) words (32b each).                                             |
+|   25   |   ro   |   0x0   | RXFULL    | When high, indicates that the receive fifo is full.  Any ongoing transactions will stall until firmware reads some data from [`RXDATA.`](#rxdata)                         |
+|   24   |   ro   |   0x0   | RXEMPTY   | When high, indicates that the receive fifo is empty. Any reads from RX FIFO will cause an error interrupt.                                                                |
+|   23   |   ro   |   0x0   | RXSTALL   | If high, signifies that an ongoing transaction has stalled due to lack of available space in the RX FIFO                                                                  |
+|   22   |   ro   |   0x0   | BYTEORDER | The value of the ByteOrder parameter, provided so that firmware can confirm proper IP configuration.                                                                      |
+|   21   |        |         |           | Reserved                                                                                                                                                                  |
+|   20   |   ro   |   0x0   | RXWM      | If high, the number of 32-bits in the RX FIFO now exceeds the [`CONTROL.RX_WATERMARK`](#control) entries (32b each).                                                      |
+| 19:16  |   ro   |   0x0   | CMDQD     | Command queue depth. Indicates how many unread 32-bit words are currently in the command segment queue.                                                                   |
+|  15:8  |   ro   |   0x0   | RXQD      | Receive queue depth. Indicates how many unread 32-bit words are currently in the RX FIFO.  When active, this result may an underestimate due to synchronization delays.   |
+|  7:0   |   ro   |   0x0   | TXQD      | Transmit queue depth. Indicates how many unsent 32-bit words are currently in the TX FIFO. When active, this result may be an overestimate due to synchronization delays. |
+
+## CONFIGOPTS
+Configuration options register.
+
+   Contains options for controlling the current peripheral.
+   Firmware needs to configure the options before the transfer.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xefffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CLKDIV", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "CSNIDLE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "CSNTRAIL", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "CSNLEAD", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "FULLCYC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CPHA", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CPOL", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                              |
+|:------:|:------:|:-------:|:----------------------------------|
+|   31   |   rw   |   0x0   | [CPOL](#configopts--cpol)         |
+|   30   |   rw   |   0x0   | [CPHA](#configopts--cpha)         |
+|   29   |   rw   |   0x0   | [FULLCYC](#configopts--fullcyc)   |
+|   28   |        |         | Reserved                          |
+| 27:24  |   rw   |   0x0   | [CSNLEAD](#configopts--csnlead)   |
+| 23:20  |   rw   |   0x0   | [CSNTRAIL](#configopts--csntrail) |
+| 19:16  |   rw   |   0x0   | [CSNIDLE](#configopts--csnidle)   |
+|  15:0  |   rw   |   0x0   | [CLKDIV](#configopts--clkdiv)     |
+
+### CONFIGOPTS . CPOL
+The polarity of the sck clock signal.  When CPOL is 0,
+    sck is low when idle, and emits high pulses.   When CPOL
+    is 1, sck is high when idle, and emits a series of low
+    pulses.
+
+### CONFIGOPTS . CPHA
+The phase of the sck clock signal relative to the data. When
+    CPHA = 0, the data changes on the trailing edge of sck
+    and is typically sampled on the leading edge.  Conversely
+    if CPHA = 1 high, data lines change on the leading edge of
+    sck and are typically sampled on the trailing edge.
+    CPHA should be chosen to match the phase of the selected
+    device.  The sampling behavior is modified by the
+    [`CONFIGOPTS.FULLCYC`](#configopts) bit.
+
+### CONFIGOPTS . FULLCYC
+Full cycle.  Modifies the CPHA sampling behaviour to allow
+    for longer device logic setup times.  Rather than sampling the SD
+    bus a half cycle after shifting out data, the data is sampled
+    a full cycle after shifting data out.  This means that if
+    CPHA = 0, data is shifted out on the trailing edge, and
+    sampled a full cycle later.  If CPHA = 1, data is shifted and
+    sampled with the trailing edge, also separated by a
+    full cycle.
+
+### CONFIGOPTS . CSNLEAD
+CS_N Leading Time.  Indicates the number of half sck cycles,
+    CSNLEAD+1, to leave between the falling edge of cs_n and
+    the first edge of sck.  Setting this register to zero
+    corresponds to the minimum delay of one-half sck cycle
+
+### CONFIGOPTS . CSNTRAIL
+CS_N Trailing Time.  Indicates the number of half sck cycles,
+    CSNTRAIL+1, to leave between last edge of sck and the rising
+    edge of cs_n. Setting this register to zero corresponds
+    to the minimum delay of one-half sck cycle.
+
+### CONFIGOPTS . CSNIDLE
+Minimum idle time between commands. Indicates the minimum
+    number of sck half-cycles to hold cs_n high between commands.
+    Setting this register to zero creates a minimally-wide CS_N-high
+    pulse of one-half sck cycle.
+
+### CONFIGOPTS . CLKDIV
+Core clock divider.  Slows down subsequent SPI transactions by a
+    factor of (CLKDIV+1) relative to the core clock frequency.  The
+    period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`
+
+## CSID
+Chip-Select ID
+
+   Controls which device to target with the next command.  This register
+   is passed to the core whenever [`COMMAND`](#command) is written.  The core then
+   asserts cio_csb_o[[`CSID`](#csid)] during the execution of the command.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CSID", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description    |
+|:------:|:------:|:-------:|:-------|:---------------|
+|  31:0  |   rw   |   0x0   | CSID   | Chip Select ID |
+
+## COMMAND
+Command Register
+
+   Parameters specific to each command segment.  Unlike the [`CONFIGOPTS`](#configopts) multi-register,
+   there is only one command register for controlling all attached SPI devices
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1ffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CSAAT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "SPEED", "bits": 2, "attr": ["wo"], "rotate": -90}, {"name": "DIRECTION", "bits": 2, "attr": ["wo"], "rotate": -90}, {"name": "LEN", "bits": 20, "attr": ["wo"], "rotate": 0}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                             |
+|:------:|:------:|:-------:|:---------------------------------|
+| 31:25  |        |         | Reserved                         |
+|  24:5  |   wo   |   0x0   | [LEN](#command--len)             |
+|  4:3   |   wo   |   0x0   | [DIRECTION](#command--direction) |
+|  2:1   |   wo   |   0x0   | [SPEED](#command--speed)         |
+|   0    |   wo   |   0x0   | [CSAAT](#command--csaat)         |
+
+### COMMAND . LEN
+Segment Length.
+
+   For read or write segments, this field controls the
+   number of 1-byte bursts to transmit and or receive in
+   this command segment.  The number of cyles required
+   to send or received a byte will depend on [`COMMAND.SPEED.`](#command)
+   For dummy segments, ([`COMMAND.DIRECTION`](#command) == 0), this register
+   controls the number of dummy cycles to issue.
+   The number of bytes (or dummy cycles) in the segment will be
+   equal to [`COMMAND.LEN`](#command) + 1.
+
+### COMMAND . DIRECTION
+The direction for the following command: "0" = Dummy cycles
+   (no TX/RX). "1" = Rx only, "2" = Tx only, "3" = Bidirectional
+   Tx/Rx (Standard SPI mode only).
+
+### COMMAND . SPEED
+The speed for this command segment: "0" = Standard SPI. "1" = Dual SPI.
+   "2"=Quad SPI,  "3": RESERVED.
+
+### COMMAND . CSAAT
+**C**hip **S**elect **A**ctive **A**fter **T**ransaction.
+   If [`COMMAND.CSAAT`](#command) = 0, the chip select line is raised immediately
+   at the end of the command segment.
+   If [`COMMAND.CSAAT`](#command) = 1, the chip select line is left low at the
+   end of the current transaction segment.
+   This allows the creation of longer, more complete SPI transactions,
+   consisting of several separate segments for issuing instructions,
+   pausing for dummy cycles, and transmitting or receiving data from
+   the device.
+
+## RXDATA
+SPI Receive Data.
+
+   Reads from this window pull data from the RXFIFO.
+
+   The serial order of bit transmission
+   is chosen to match SPI flash devices. Individual bytes
+   are always transmitted with the most significant bit first.
+   Only four-byte reads are supported. If ByteOrder = 0,
+   the first byte received is packed in the MSB of !!RXDATA.
+   For some processor architectures, this could lead to shuffling
+   of flash data as compared to how it is written in memory.
+   In which case, choosing ByteOrder = 1 can reverse the
+   byte-order of each data read, causing the first byte
+   received to be packed into the LSB of !!RXDATA. (Though within
+   each byte the most significant bit is always pulled
+   from the bus first.)
+
+- Word Aligned Offset Range: `0x24`to`0x24`
+- Size (words): `1`
+- Access: `ro`
+- Byte writes are *not* supported.
+
+## TXDATA
+SPI Transmit Data.
+
+   Data written to this window is placed into the TXFIFO.
+   Byte-enables are supported for writes.
+
+   The serial order of bit transmission
+   is chosen to match SPI flash devices. Individual bytes
+   are always transmitted with the most significant bit first.
+   Multi-byte writes are also supported, and if ByteOrder = 0,
+   the bits of !!TXDATA are transmitted strictly in order of
+   decreasing signficance (i.e. most signicant bit first).
+   For some processor architectures, this could lead to shuffling
+   of flash data as compared to how it is written in memory.
+   In which case, choosing ByteOrder = 1 can reverse the
+   byte-order of multi-byte data writes.  (Though within
+   each byte the most significant bit is always sent first.)
+
+- Word Aligned Offset Range: `0x28`to`0x28`
+- Size (words): `1`
+- Access: `wo`
+- Byte writes are  supported.
+
+## ERROR_ENABLE
+Controls which classes of errors raise an interrupt.
+- Offset: `0x2c`
+- Reset default: `0x1f`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CMDBUSY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "OVERFLOW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UNDERFLOW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CMDINVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CSIDINVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                                                       |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:5  |        |         |           | Reserved                                                                                                                                                                                          |
+|   4    |   rw   |   0x1   | CSIDINVAL | Invalid CSID: If this bit is set, the block sends an error interrupt whenever a command is submitted, but CSID exceeds NumCS.                                                                     |
+|   3    |   rw   |   0x1   | CMDINVAL  | Invalid Command Errors: If this bit is set, the block sends an error interrupt whenever a command is sent with invalid values for [`COMMAND.SPEED`](#command) or [`COMMAND.DIRECTION.`](#command) |
+|   2    |   rw   |   0x1   | UNDERFLOW | Underflow Errors: If this bit is set, the block sends an error interrupt whenever there is a read from [`RXDATA`](#rxdata) but the RX FIFO is empty.                                              |
+|   1    |   rw   |   0x1   | OVERFLOW  | Overflow Errors: If this bit is set, the block sends an error interrupt whenever the TX FIFO overflows.                                                                                           |
+|   0    |   rw   |   0x1   | CMDBUSY   | Command Error: If this bit is set, the block sends an error interrupt whenever a command is issued while busy (i.e. a 1 is when [`STATUS.READY`](#status) is not asserted.)                       |
+
+## ERROR_STATUS
+Indicates that any errors that have occurred.
+   When an error
+   occurs, the corresponding bit must be cleared here before
+   issuing any further commands.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CMDBUSY", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "OVERFLOW", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNDERFLOW", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CMDINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CSIDINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ACCESSINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                                                                                                                                             |
+|:------:|:------:|:-------:|:------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:6  |        |         |             | Reserved                                                                                                                                                                |
+|   5    |  rw1c  |   0x0   | ACCESSINVAL | Indicates that TLUL attempted to write to TXDATA with no bytes enabled. Such 'zero byte' writes are not supported.                                                      |
+|   4    |  rw1c  |   0x0   | CSIDINVAL   | Indicates a command was attempted with an invalid value for [`CSID.`](#csid)                                                                                            |
+|   3    |  rw1c  |   0x0   | CMDINVAL    | Indicates an invalid command segment, meaning either an invalid value of [`COMMAND.SPEED`](#command) or a request for bidirectional data transfer at dual or quad speed |
+|   2    |  rw1c  |   0x0   | UNDERFLOW   | Indicates that firmware has attempted to read from [`RXDATA`](#rxdata) when the RX FIFO is empty.                                                                       |
+|   1    |  rw1c  |   0x0   | OVERFLOW    | Indicates that firmware has overflowed the TX FIFO                                                                                                                      |
+|   0    |  rw1c  |   0x0   | CMDBUSY     | Indicates a write to [`COMMAND`](#command) when [`STATUS.READY`](#status) = 0.                                                                                          |
+
+## EVENT_ENABLE
+Controls which classes of SPI events raise an interrupt.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXFULL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RXWM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXWM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "READY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IDLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                              |
+|:------:|:------:|:-------:|:----------------------------------|
+|  31:6  |        |         | Reserved                          |
+|   5    |   rw   |   0x0   | [IDLE](#event_enable--idle)       |
+|   4    |   rw   |   0x0   | [READY](#event_enable--ready)     |
+|   3    |   rw   |   0x0   | [TXWM](#event_enable--txwm)       |
+|   2    |   rw   |   0x0   | [RXWM](#event_enable--rxwm)       |
+|   1    |   rw   |   0x0   | [TXEMPTY](#event_enable--txempty) |
+|   0    |   rw   |   0x0   | [RXFULL](#event_enable--rxfull)   |
+
+### EVENT_ENABLE . IDLE
+Assert to send a spi_event interrupt whenever [`STATUS.ACTIVE`](#status)
+   goes low
+
+### EVENT_ENABLE . READY
+Assert to send a spi_event interrupt whenever [`STATUS.READY`](#status)
+   goes high
+
+### EVENT_ENABLE . TXWM
+Assert to send a spi_event interrupt whenever the number of 32-bit words in
+   the TX FIFO is less than [`CONTROL.TX_WATERMARK.`](#control)  To prevent the
+   reassertion of this interrupt add more data to the TX FIFO, or
+   reduce [`CONTROL.TX_WATERMARK.`](#control)
+
+### EVENT_ENABLE . RXWM
+Assert to send a spi_event interrupt whenever the number of 32-bit words in
+   the RX FIFO is greater than [`CONTROL.RX_WATERMARK.`](#control) To prevent the
+   reassertion of this interrupt, read more data from the RX FIFO, or
+   increase [`CONTROL.RX_WATERMARK.`](#control)
+
+### EVENT_ENABLE . TXEMPTY
+Assert to send a spi_event interrupt whenever [`STATUS.TXEMPTY`](#status)
+   goes high
+
+### EVENT_ENABLE . RXFULL
+Assert to send a spi_event interrupt whenever [`STATUS.RXFULL`](#status)
+   goes high
+
+
+
+## tagger / doc / registers.md
+
+## Summary
+
+| Name                                   | Offset   |   Length | Description                             |
+|:---------------------------------------|:---------|---------:|:----------------------------------------|
+| tagger_reg.[`PAT_COMMIT`](#PAT_COMMIT) | 0x0      |        4 | Partition configuration commit register |
+| tagger_reg.[`PAT_ADDR_0`](#pat_addr)   | 0x4      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_1`](#pat_addr)   | 0x8      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_2`](#pat_addr)   | 0xc      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_3`](#pat_addr)   | 0x10     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_4`](#pat_addr)   | 0x14     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_5`](#pat_addr)   | 0x18     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_6`](#pat_addr)   | 0x1c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_7`](#pat_addr)   | 0x20     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_8`](#pat_addr)   | 0x24     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_9`](#pat_addr)   | 0x28     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_10`](#pat_addr)  | 0x2c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_11`](#pat_addr)  | 0x30     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_12`](#pat_addr)  | 0x34     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_13`](#pat_addr)  | 0x38     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_14`](#pat_addr)  | 0x3c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_15`](#pat_addr)  | 0x40     |        4 | Partition address                       |
+| tagger_reg.[`PATID_0`](#patid)         | 0x44     |        4 | Partition ID                            |
+| tagger_reg.[`PATID_1`](#patid)         | 0x48     |        4 | Partition ID                            |
+| tagger_reg.[`PATID_2`](#patid)         | 0x4c     |        4 | Partition ID                            |
+| tagger_reg.[`ADDR_CONF`](#addr_conf)   | 0x50     |        4 | Address encoding mode switch register   |
+
+## PAT_COMMIT
+Partition configuration commit register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "commit_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                               |
+|:------:|:------:|:-------:|:---------|:------------------------------------------|
+|  31:1  |        |         |          | Reserved                                  |
+|   0    |   rw   |   0x0   | commit_0 | commit changes of partition configuration |
+
+## PAT_ADDR
+Partition address
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name        | Offset   |
+|:------------|:---------|
+| PAT_ADDR_0  | 0x4      |
+| PAT_ADDR_1  | 0x8      |
+| PAT_ADDR_2  | 0xc      |
+| PAT_ADDR_3  | 0x10     |
+| PAT_ADDR_4  | 0x14     |
+| PAT_ADDR_5  | 0x18     |
+| PAT_ADDR_6  | 0x1c     |
+| PAT_ADDR_7  | 0x20     |
+| PAT_ADDR_8  | 0x24     |
+| PAT_ADDR_9  | 0x28     |
+| PAT_ADDR_10 | 0x2c     |
+| PAT_ADDR_11 | 0x30     |
+| PAT_ADDR_12 | 0x34     |
+| PAT_ADDR_13 | 0x38     |
+| PAT_ADDR_14 | 0x3c     |
+| PAT_ADDR_15 | 0x40     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PAT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                              |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------|
+|  31:0  |   rw   |   0x0   | PAT_ADDR | Single partition configurations: address |
+
+## PATID
+Partition ID
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name    | Offset   |
+|:--------|:---------|
+| PATID_0 | 0x44     |
+| PATID_1 | 0x48     |
+| PATID_2 | 0x4c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PATID", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                          |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | PATID  | Partition ID (PatID) for each partition, length determined by params |
+
+## ADDR_CONF
+Address encoding mode switch register
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name      | Offset   |
+|:----------|:---------|
+| ADDR_CONF | 0x50     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "addr_conf", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                 |
+|:------:|:------:|:-------:|:----------|:----------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | addr_conf | 2 bits configuration for each partition. 2'b00: OFF, 2'b01: TOR, 2'b10: NA4 |
+
+
+
+## uart / doc / registers.md
+
+## Summary
+
+| Name                                 | Offset   |   Length | Description                                                        |
+|:-------------------------------------|:---------|---------:|:-------------------------------------------------------------------|
+| uart.[`INTR_STATE`](#intr_state)     | 0x0      |        4 | Interrupt State Register                                           |
+| uart.[`INTR_ENABLE`](#intr_enable)   | 0x4      |        4 | Interrupt Enable Register                                          |
+| uart.[`INTR_TEST`](#intr_test)       | 0x8      |        4 | Interrupt Test Register                                            |
+| uart.[`ALERT_TEST`](#alert_test)     | 0xc      |        4 | Alert Test Register                                                |
+| uart.[`CTRL`](#ctrl)                 | 0x10     |        4 | UART control register                                              |
+| uart.[`STATUS`](#status)             | 0x14     |        4 | UART live status register                                          |
+| uart.[`RDATA`](#rdata)               | 0x18     |        4 | UART read data                                                     |
+| uart.[`WDATA`](#wdata)               | 0x1c     |        4 | UART write data                                                    |
+| uart.[`FIFO_CTRL`](#fifo_ctrl)       | 0x20     |        4 | UART FIFO control register                                         |
+| uart.[`FIFO_STATUS`](#fifo_status)   | 0x24     |        4 | UART FIFO status register                                          |
+| uart.[`OVRD`](#ovrd)                 | 0x28     |        4 | TX pin override control. Gives direct SW control over TX pin state |
+| uart.[`VAL`](#val)                   | 0x2c     |        4 | UART oversampled values                                            |
+| uart.[`TIMEOUT_CTRL`](#timeout_ctrl) | 0x30     |        4 | UART RX timeout control                                            |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x101`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                                                                    |
+|:------:|:------:|:-------:|:--------------|:---------------------------------------------------------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                                                                       |
+|   8    |   ro   |   0x1   | tx_empty      | raised if the transmit FIFO is empty.                                                                          |
+|   7    |  rw1c  |   0x0   | rx_parity_err | raised if the receiver has detected a parity error.                                                            |
+|   6    |  rw1c  |   0x0   | rx_timeout    | raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period. |
+|   5    |  rw1c  |   0x0   | rx_break_err  | raised if break condition has been detected on receive.                                                        |
+|   4    |  rw1c  |   0x0   | rx_frame_err  | raised if a framing error has been detected on receive.                                                        |
+|   3    |  rw1c  |   0x0   | rx_overflow   | raised if the receive FIFO has overflowed.                                                                     |
+|   2    |  rw1c  |   0x0   | tx_done       | raised if the transmit FIFO has emptied and no transmit is ongoing.                                            |
+|   1    |   ro   |   0x0   | rx_watermark  | raised if the receive FIFO is past the high-water mark.                                                        |
+|   0    |   ro   |   0x1   | tx_watermark  | raised if the transmit FIFO is past the high-water mark.                                                       |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                             |
+|:------:|:------:|:-------:|:--------------|:------------------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                                |
+|   8    |   rw   |   0x0   | tx_empty      | Enable interrupt when [`INTR_STATE.tx_empty`](#intr_state) is set.      |
+|   7    |   rw   |   0x0   | rx_parity_err | Enable interrupt when [`INTR_STATE.rx_parity_err`](#intr_state) is set. |
+|   6    |   rw   |   0x0   | rx_timeout    | Enable interrupt when [`INTR_STATE.rx_timeout`](#intr_state) is set.    |
+|   5    |   rw   |   0x0   | rx_break_err  | Enable interrupt when [`INTR_STATE.rx_break_err`](#intr_state) is set.  |
+|   4    |   rw   |   0x0   | rx_frame_err  | Enable interrupt when [`INTR_STATE.rx_frame_err`](#intr_state) is set.  |
+|   3    |   rw   |   0x0   | rx_overflow   | Enable interrupt when [`INTR_STATE.rx_overflow`](#intr_state) is set.   |
+|   2    |   rw   |   0x0   | tx_done       | Enable interrupt when [`INTR_STATE.tx_done`](#intr_state) is set.       |
+|   1    |   rw   |   0x0   | rx_watermark  | Enable interrupt when [`INTR_STATE.rx_watermark`](#intr_state) is set.  |
+|   0    |   rw   |   0x0   | tx_watermark  | Enable interrupt when [`INTR_STATE.tx_watermark`](#intr_state) is set.  |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                      |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                         |
+|   8    |   wo   |   0x0   | tx_empty      | Write 1 to force [`INTR_STATE.tx_empty`](#intr_state) to 1.      |
+|   7    |   wo   |   0x0   | rx_parity_err | Write 1 to force [`INTR_STATE.rx_parity_err`](#intr_state) to 1. |
+|   6    |   wo   |   0x0   | rx_timeout    | Write 1 to force [`INTR_STATE.rx_timeout`](#intr_state) to 1.    |
+|   5    |   wo   |   0x0   | rx_break_err  | Write 1 to force [`INTR_STATE.rx_break_err`](#intr_state) to 1.  |
+|   4    |   wo   |   0x0   | rx_frame_err  | Write 1 to force [`INTR_STATE.rx_frame_err`](#intr_state) to 1.  |
+|   3    |   wo   |   0x0   | rx_overflow   | Write 1 to force [`INTR_STATE.rx_overflow`](#intr_state) to 1.   |
+|   2    |   wo   |   0x0   | tx_done       | Write 1 to force [`INTR_STATE.tx_done`](#intr_state) to 1.       |
+|   1    |   wo   |   0x0   | rx_watermark  | Write 1 to force [`INTR_STATE.rx_watermark`](#intr_state) to 1.  |
+|   0    |   wo   |   0x0   | tx_watermark  | Write 1 to force [`INTR_STATE.tx_watermark`](#intr_state) to 1.  |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CTRL
+UART control register
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffff03f7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NF", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "SLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_ODD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RXBLVL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "NCO", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                            |
+|:------:|:------:|:-------:|:--------------------------------|
+| 31:16  |   rw   |   0x0   | [NCO](#ctrl--nco)               |
+| 15:10  |        |         | Reserved                        |
+|  9:8   |   rw   |   0x0   | [RXBLVL](#ctrl--rxblvl)         |
+|   7    |   rw   |   0x0   | [PARITY_ODD](#ctrl--parity_odd) |
+|   6    |   rw   |   0x0   | [PARITY_EN](#ctrl--parity_en)   |
+|   5    |   rw   |   0x0   | [LLPBK](#ctrl--llpbk)           |
+|   4    |   rw   |   0x0   | [SLPBK](#ctrl--slpbk)           |
+|   3    |        |         | Reserved                        |
+|   2    |   rw   |   0x0   | [NF](#ctrl--nf)                 |
+|   1    |   rw   |   0x0   | [RX](#ctrl--rx)                 |
+|   0    |   rw   |   0x0   | [TX](#ctrl--tx)                 |
+
+### CTRL . NCO
+BAUD clock rate control.
+
+### CTRL . RXBLVL
+Trigger level for RX break detection. Sets the number of character
+times the line must be low to detect a break.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | break2  | 2 characters  |
+| 0x1     | break4  | 4 characters  |
+| 0x2     | break8  | 8 characters  |
+| 0x3     | break16 | 16 characters |
+
+
+### CTRL . PARITY_ODD
+If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even.
+
+### CTRL . PARITY_EN
+If true, parity is enabled in both RX and TX directions.
+
+### CTRL . LLPBK
+Line loopback enable.
+
+If this bit is turned on, incoming bits are forwarded to TX for testing purpose.
+See Block Diagram. Note that the internal design sees RX value as 1 always if line
+loopback is enabled.
+
+### CTRL . SLPBK
+System loopback enable.
+
+If this bit is turned on, any outgoing bits to TX are received through RX.
+See Block Diagram. Note that the TX line goes 1 if System loopback is enabled.
+
+### CTRL . NF
+RX noise filter enable.
+If the noise filter is enabled, RX line goes through the 3-tap
+repetition code. It ignores single IP clock period noise.
+
+### CTRL . RX
+RX enable
+
+### CTRL . TX
+TX enable
+
+## STATUS
+UART live status register
+- Offset: `0x14`
+- Reset default: `0x3c`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                         |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------|
+|  31:6  |        |         |         | Reserved                                            |
+|   5    |   ro   |   0x1   | RXEMPTY | RX FIFO is empty                                    |
+|   4    |   ro   |   0x1   | RXIDLE  | RX is idle                                          |
+|   3    |   ro   |   0x1   | TXIDLE  | TX FIFO is empty and all bits have been transmitted |
+|   2    |   ro   |   0x1   | TXEMPTY | TX FIFO is empty                                    |
+|   1    |   ro   |    x    | RXFULL  | RX buffer is full                                   |
+|   0    |   ro   |    x    | TXFULL  | TX buffer is full                                   |
+
+## RDATA
+UART read data
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   ro   |    x    | RDATA  |               |
+
+## WDATA
+UART write data
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "WDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   wo   |   0x0   | WDATA  |               |
+
+## FIFO_CTRL
+UART FIFO control register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "TXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         |
+|:------:|:------:|:-------:|:-----------------------------|
+|  31:8  |        |         | Reserved                     |
+|  7:5   |   rw   |   0x0   | [TXILVL](#fifo_ctrl--txilvl) |
+|  4:2   |   rw   |   0x0   | [RXILVL](#fifo_ctrl--rxilvl) |
+|   1    |   wo   |   0x0   | [TXRST](#fifo_ctrl--txrst)   |
+|   0    |   wo   |   0x0   | [RXRST](#fifo_ctrl--rxrst)   |
+
+### FIFO_CTRL . TXILVL
+Trigger level for TX interrupts. If the FIFO depth is less than the setting, it
+raises tx_watermark interrupt.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | txlvl1  | 1 character   |
+| 0x1     | txlvl2  | 2 characters  |
+| 0x2     | txlvl4  | 4 characters  |
+| 0x3     | txlvl8  | 8 characters  |
+| 0x4     | txlvl16 | 16 characters |
+
+Other values are reserved.
+
+### FIFO_CTRL . RXILVL
+Trigger level for RX interrupts. If the FIFO depth is greater than or equal to
+the setting, it raises rx_watermark interrupt.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | rxlvl1  | 1 character   |
+| 0x1     | rxlvl2  | 2 characters  |
+| 0x2     | rxlvl4  | 4 characters  |
+| 0x3     | rxlvl8  | 8 characters  |
+| 0x4     | rxlvl16 | 16 characters |
+| 0x5     | rxlvl32 | 32 characters |
+| 0x6     | rxlvl62 | 62 characters |
+
+Other values are reserved.
+
+### FIFO_CTRL . TXRST
+TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0
+
+### FIFO_CTRL . RXRST
+RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0
+
+## FIFO_STATUS
+UART FIFO status register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xff00ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}, {"name": "RXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                   |
+|:------:|:------:|:-------:|:-------|:------------------------------|
+| 31:24  |        |         |        | Reserved                      |
+| 23:16  |   ro   |    x    | RXLVL  | Current fill level of RX fifo |
+|  15:8  |        |         |        | Reserved                      |
+|  7:0   |   ro   |    x    | TXLVL  | Current fill level of TX fifo |
+
+## OVRD
+TX pin override control. Gives direct SW control over TX pin state
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                          |
+|:------:|:------:|:-------:|:-------|:-------------------------------------|
+|  31:2  |        |         |        | Reserved                             |
+|   1    |   rw   |   0x0   | TXVAL  | Write to set the value of the TX pin |
+|   0    |   rw   |   0x0   | TXEN   | Enable TX pin override control       |
+
+## VAL
+UART oversampled values
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+| 31:16  |        |         |        | Reserved                                                               |
+|  15:0  |   ro   |    x    | RX     | Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15. |
+
+## TIMEOUT_CTRL
+UART RX timeout control
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x80ffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|   31   |   rw   |   0x0   | EN     | Enable RX timeout feature          |
+| 30:24  |        |         |        | Reserved                           |
+|  23:0  |   rw   |   0x0   | VAL    | RX timeout value in UART bit times |
+
+
+
+## unbent / doc / registers.md
+
+## Summary
+
+| Name                                         | Offset   |   Length | Description                         |
+|:---------------------------------------------|:---------|---------:|:------------------------------------|
+| bus_err_unit.[`err_addr`](#err_addr)         | 0x0      |        4 | Address of the bus error            |
+| bus_err_unit.[`err_addr_top`](#err_addr_top) | 0x4      |        4 | Top of the address of the bus error |
+| bus_err_unit.[`err_code`](#err_code)         | 0x8      |        4 | Error code of the bus error         |
+| bus_err_unit.[`meta`](#meta)                 | 0xc      |        4 | Meta information of the bus error   |
+
+## err_addr
+Address of the bus error
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description              |
+|:------:|:------:|:-------:|:---------|:-------------------------|
+|  31:0  |   ro   |    x    | err_addr | Address of the bus error |
+
+## err_addr_top
+Top of the address of the bus error
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description              |
+|:------:|:------:|:-------:|:---------|:-------------------------|
+|  31:0  |   ro   |    x    | err_addr | Address of the bus error |
+
+## err_code
+Error code of the bus error
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_code", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                 |
+|:------:|:------:|:-------:|:---------|:----------------------------|
+|  31:0  |   ro   |    x    | err_code | Error code of the bus error |
+
+## meta
+Meta information of the bus error
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "meta", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                       |
+|:------:|:------:|:-------:|:-------|:----------------------------------|
+|  31:0  |   ro   |    x    | meta   | Meta information of the bus error |
+
+
+
+## vga / doc / registers.md
+
+## Summary
+
+| Name                                                      | Offset   |   Length | Description                               |
+|:----------------------------------------------------------|:---------|---------:|:------------------------------------------|
+| axi_vga.[`CONTROL`](#control)                             | 0x0      |        4 | Control register                          |
+| axi_vga.[`CLK_DIV`](#clk_div)                             | 0x4      |        4 | Clock divider                             |
+| axi_vga.[`HORI_VISIBLE_SIZE`](#hori_visible_size)         | 0x8      |        4 | Size of horizontal visible area           |
+| axi_vga.[`HORI_FRONT_PORCH_SIZE`](#hori_front_porch_size) | 0xc      |        4 | Size of horizontal front porch            |
+| axi_vga.[`HORI_SYNC_SIZE`](#hori_sync_size)               | 0x10     |        4 | Size of horizontal sync area              |
+| axi_vga.[`HORI_BACK_PORCH_SIZE`](#hori_back_porch_size)   | 0x14     |        4 | Size of horizontal back porch             |
+| axi_vga.[`VERT_VISIBLE_SIZE`](#vert_visible_size)         | 0x18     |        4 | Size of vertical visible area             |
+| axi_vga.[`VERT_FRONT_PORCH_SIZE`](#vert_front_porch_size) | 0x1c     |        4 | Size of vertical front porch              |
+| axi_vga.[`VERT_SYNC_SIZE`](#vert_sync_size)               | 0x20     |        4 | Size of vertical sync area                |
+| axi_vga.[`VERT_BACK_PORCH_SIZE`](#vert_back_porch_size)   | 0x24     |        4 | Size of vertical back porch               |
+| axi_vga.[`START_ADDR_LOW`](#start_addr_low)               | 0x28     |        4 | Low end of start address of frame buffer  |
+| axi_vga.[`START_ADDR_HIGH`](#start_addr_high)             | 0x2c     |        4 | High end of start address of frame buffer |
+| axi_vga.[`FRAME_SIZE`](#frame_size)                       | 0x30     |        4 | Size of whole frame                       |
+| axi_vga.[`BURST_LEN`](#burst_len)                         | 0x34     |        4 | Number of beats in a burst                |
+
+## CONTROL
+Control register
+- Offset: `0x0`
+- Reset default: `0x6`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "hsync_pol", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "vsync_pol", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                            |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------|
+|  31:3  |        |         |           | Reserved                                               |
+|   2    |   rw   |   0x1   | vsync_pol | Sets polarity for VSYNC 0 - Active Low 1 - Active High |
+|   1    |   rw   |   0x1   | hsync_pol | Sets polarity for HSYNC 0 - Active Low 1 - Active High |
+|   0    |   rw   |   0x0   | enable    | Enables FSM.                                           |
+
+## CLK_DIV
+Clock divider
+- Offset: `0x4`
+- Reset default: `0x1`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_div", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description    |
+|:------:|:------:|:-------:|:--------|:---------------|
+|  31:8  |        |         |         | Reserved       |
+|  7:0   |   rw   |   0x1   | clk_div | Clock divider. |
+
+## HORI_VISIBLE_SIZE
+Size of horizontal visible area
+- Offset: `0x8`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_visible_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                      |
+|:------:|:------:|:-------:|:------------------|:---------------------------------|
+|  31:0  |   rw   |   0x1   | hori_visible_size | Size of horizontal visible area. |
+
+## HORI_FRONT_PORCH_SIZE
+Size of horizontal front porch
+- Offset: `0xc`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_front_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                     |
+|:------:|:------:|:-------:|:----------------------|:--------------------------------|
+|  31:0  |   rw   |   0x1   | hori_front_porch_size | Size of horizontal front porch. |
+
+## HORI_SYNC_SIZE
+Size of horizontal sync area
+- Offset: `0x10`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_sync_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                   |
+|:------:|:------:|:-------:|:---------------|:------------------------------|
+|  31:0  |   rw   |   0x1   | hori_sync_size | Size of horizontal sync area. |
+
+## HORI_BACK_PORCH_SIZE
+Size of horizontal back porch
+- Offset: `0x14`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_back_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description                    |
+|:------:|:------:|:-------:|:---------------------|:-------------------------------|
+|  31:0  |   rw   |   0x1   | hori_back_porch_size | Size of horizontal back porch. |
+
+## VERT_VISIBLE_SIZE
+Size of vertical visible area
+- Offset: `0x18`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_visible_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                    |
+|:------:|:------:|:-------:|:------------------|:-------------------------------|
+|  31:0  |   rw   |   0x1   | vert_visible_size | Size of vertical visible area. |
+
+## VERT_FRONT_PORCH_SIZE
+Size of vertical front porch
+- Offset: `0x1c`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_front_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                   |
+|:------:|:------:|:-------:|:----------------------|:------------------------------|
+|  31:0  |   rw   |   0x1   | vert_front_porch_size | Size of vertical front porch. |
+
+## VERT_SYNC_SIZE
+Size of vertical sync area
+- Offset: `0x20`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_sync_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                 |
+|:------:|:------:|:-------:|:---------------|:----------------------------|
+|  31:0  |   rw   |   0x1   | vert_sync_size | Size of vertical sync area. |
+
+## VERT_BACK_PORCH_SIZE
+Size of vertical back porch
+- Offset: `0x24`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_back_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description                  |
+|:------:|:------:|:-------:|:---------------------|:-----------------------------|
+|  31:0  |   rw   |   0x1   | vert_back_porch_size | Size of vertical back porch. |
+
+## START_ADDR_LOW
+Low end of start address of frame buffer
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "start_addr_low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                               |
+|:------:|:------:|:-------:|:---------------|:------------------------------------------|
+|  31:0  |   rw   |   0x0   | start_addr_low | Low end of start address of frame buffer. |
+
+## START_ADDR_HIGH
+High end of start address of frame buffer
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "start_addr_high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                                |
+|:------:|:------:|:-------:|:----------------|:-------------------------------------------|
+|  31:0  |   rw   |   0x0   | start_addr_high | High end of start address of frame buffer. |
+
+## FRAME_SIZE
+Size of whole frame
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "frame_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description          |
+|:------:|:------:|:-------:|:-----------|:---------------------|
+|  31:0  |   rw   |   0x0   | frame_size | Size of whole frame. |
+
+## BURST_LEN
+Number of beats in a burst
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "burst_len", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                 |
+|:------:|:------:|:-------:|:----------|:----------------------------|
+|  31:8  |        |         |           | Reserved                    |
+|  7:0   |   rw   |   0x0   | burst_len | Number of beats in a burst. |
+
+
+
+## watchdog_timer / doc / registers.md
+
+## Summary
+
+| Name                                            | Offset   |   Length | Description                            |
+|:------------------------------------------------|:---------|---------:|:---------------------------------------|
+| aon_timer.[`ALERT_TEST`](#alert_test)           | 0x0      |        4 | Alert Test Register                    |
+| aon_timer.[`WKUP_CTRL`](#wkup_ctrl)             | 0x4      |        4 | Wakeup Timer Control register          |
+| aon_timer.[`WKUP_THOLD`](#wkup_thold)           | 0x8      |        4 | Wakeup Timer Threshold Register        |
+| aon_timer.[`WKUP_COUNT`](#wkup_count)           | 0xc      |        4 | Wakeup Timer Count Register            |
+| aon_timer.[`WDOG_REGWEN`](#wdog_regwen)         | 0x10     |        4 | Watchdog Timer Write Enable Register   |
+| aon_timer.[`WDOG_CTRL`](#wdog_ctrl)             | 0x14     |        4 | Watchdog Timer Control register        |
+| aon_timer.[`WDOG_BARK_THOLD`](#wdog_bark_thold) | 0x18     |        4 | Watchdog Timer Bark Threshold Register |
+| aon_timer.[`WDOG_BITE_THOLD`](#wdog_bite_thold) | 0x1c     |        4 | Watchdog Timer Bite Threshold Register |
+| aon_timer.[`WDOG_COUNT`](#wdog_count)           | 0x20     |        4 | Watchdog Timer Count Register          |
+| aon_timer.[`INTR_STATE`](#intr_state)           | 0x24     |        4 | Interrupt State Register               |
+| aon_timer.[`INTR_TEST`](#intr_test)             | 0x28     |        4 | Interrupt Test Register                |
+| aon_timer.[`WKUP_CAUSE`](#wkup_cause)           | 0x2c     |        4 | Wakeup request status                  |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## WKUP_CTRL
+Wakeup Timer Control register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "prescaler", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------|
+| 31:13  |        |         |           | Reserved                                   |
+|  12:1  |   rw   |   0x0   | prescaler | Pre-scaler value for wakeup timer count    |
+|   0    |   rw   |   0x0   | enable    | When set to 1, the wakeup timer will count |
+
+## WKUP_THOLD
+Wakeup Timer Threshold Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                               |
+|:------:|:------:|:-------:|:----------|:----------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a wakeup interrupt should be generated |
+
+## WKUP_COUNT
+Wakeup Timer Count Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "count", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  31:0  |   rw   |   0x0   | count  | The current wakeup counter value |
+
+## WDOG_REGWEN
+Watchdog Timer Write Enable Register
+- Offset: `0x10`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "regwen", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                     |
+|   0    |  rw0c  |   0x1   | regwen | Once cleared, the watchdog configuration will be locked until the next reset |
+
+## WDOG_CTRL
+Watchdog Timer Control register
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pause_in_sleep", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                   |
+|:------:|:------:|:-------:|:---------------|:--------------------------------------------------------------|
+|  31:2  |        |         |                | Reserved                                                      |
+|   1    |   rw   |   0x0   | pause_in_sleep | When set to 1, the watchdog timer will not count during sleep |
+|   0    |   rw   |   0x0   | enable         | When set to 1, the watchdog timer will count                  |
+
+## WDOG_BARK_THOLD
+Watchdog Timer Bark Threshold Register
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                      |
+|:------:|:------:|:-------:|:----------|:-----------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a watchdog bark interrupt should be generated |
+
+## WDOG_BITE_THOLD
+Watchdog Timer Bite Threshold Register
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a watchdog bite reset should be generated |
+
+## WDOG_COUNT
+Watchdog Timer Count Register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "count", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | count  | The current watchdog counter value |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "wkup_timer_expired", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "wdog_timer_bark", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description                                                |
+|:------:|:------:|:-------:|:-------------------|:-----------------------------------------------------------|
+|  31:2  |        |         |                    | Reserved                                                   |
+|   1    |  rw1c  |   0x0   | wdog_timer_bark    | Raised if the watchdog timer has hit the bark threshold    |
+|   0    |  rw1c  |   0x0   | wkup_timer_expired | Raised if the wakeup timer has hit the specified threshold |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "wkup_timer_expired", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "wdog_timer_bark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description                                   |
+|:------:|:------:|:-------:|:-------------------|:----------------------------------------------|
+|  31:2  |        |         |                    | Reserved                                      |
+|   1    |   wo   |    x    | wdog_timer_bark    | Write 1 to force wdog_timer_bark interrupt    |
+|   0    |   wo   |    x    | wkup_timer_expired | Write 1 to force wkup_timer_expired interrupt |
+
+## WKUP_CAUSE
+Wakeup request status
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cause", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------|
+|  31:1  |        |         |        | Reserved                                     |
+|   0    |  rw0c  |   0x0   | cause  | AON timer requested wakeup, write 0 to clear |
+
diff --git a/docs/um/carfield_full_doc.pdf b/docs/um/carfield_full_doc.pdf
new file mode 100644
index 00000000..6a93a77a
Binary files /dev/null and b/docs/um/carfield_full_doc.pdf differ
diff --git a/docs/um/ip/FP_Cluster/data/spatz_cluster_peripheral_reg.hjson b/docs/um/ip/FP_Cluster/data/spatz_cluster_peripheral_reg.hjson
new file mode 100644
index 00000000..0be5f06a
--- /dev/null
+++ b/docs/um/ip/FP_Cluster/data/spatz_cluster_peripheral_reg.hjson
@@ -0,0 +1,431 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+{
+    param_list: [
+        { name: "NumPerfCounters",
+        desc: "Number of performance counters",
+        type: "int",
+        default: "2"
+        },
+    ],
+    name: "spatz_cluster_peripheral",
+    clock_primary: "clk_i",
+    bus_interfaces: [
+        { protocol: "reg_iface", direction: "device"}
+    ]
+    regwidth: 64,
+    registers: [{
+        multireg: {
+            name: "PERF_COUNTER_ENABLE",
+            desc: "Enable particular performance counter and start tracking.",
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "performance_counter_enable",
+            fields: [{
+                bits: "0:0",
+                resval: "0",
+                name: "CYCLE",
+                desc: '''
+                    Cycle counter. Counts up as long as the cluster is powered.
+                    '''
+            },
+            {
+                bits: "1:1",
+                resval: "0",
+                name: "TCDM_ACCESSED"
+                desc: '''
+                        Increased whenever the TCDM is accessed. Each individual access is tracked,
+                        so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+                        so it doesn't matter whether the cores or the for example the SSR hardware accesses
+                        the TCDM. _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "2:2",
+                resval: "0",
+                name: "TCDM_CONGESTED"
+                desc: '''
+                        Incremented whenever an access twoards the TCDM is made but the arbitration
+                        logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+                        _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "3:3",
+                resval: "0",
+                name: "ISSUE_FPU"
+                desc: '''
+                        Core operations performed in the FPU. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "4:4",
+                resval: "0",
+                name: "ISSUE_FPU_SEQ"
+                desc: '''
+                        Incremented whenever the FPU Sequencer issues an FPU instruction.
+                        Might be non available if the hardware doesn't support FREP.
+                        _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "5:5",
+                resval: "0",
+                name: "ISSUE_CORE_TO_FPU"
+                desc: '''Incremented whenever the core issues an FPU instruction.
+                        _This is a hart-local signal._'''
+            },
+            {
+                bits: "6:6",
+                resval: "0",
+                name: "RETIRED_INSTR"
+                desc: '''
+                        Instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "7:7",
+                resval: "0",
+                name: "RETIRED_LOAD"
+                desc: '''
+                        Load instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "8:8",
+                resval: "0",
+                name: "RETIRED_I"
+                desc: '''
+                        Base instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "9:9",
+                resval: "0",
+                name: "RETIRED_ACC"
+                desc: '''
+                        Offloaded instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "10:10",
+                resval: "0",
+                name: "DMA_AW_STALL"
+                desc: '''
+                        Incremented whenever aw_valid = 1 but aw_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "11:11",
+                resval: "0",
+                name: "DMA_AR_STALL"
+                desc: '''
+                        Incremented whenever ar_valid = 1 but ar_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "12:12",
+                resval: "0",
+                name: "DMA_R_STALL"
+                desc: '''
+                        Incremented whenever r_ready = 1 but r_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "13:13",
+                resval: "0",
+                name: "DMA_W_STALL"
+                desc: '''
+                        Incremented whenever w_valid = 1 but w_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "14:14",
+                resval: "0",
+                name: "DMA_BUF_W_STALL"
+                desc: '''
+                        Incremented whenever w_ready = 1 but w_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "15:15",
+                resval: "0",
+                name: "DMA_BUF_R_STALL"
+                desc: '''
+                        Incremented whenever r_valid = 1 but r_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "16:16",
+                resval: "0",
+                name: "DMA_AW_DONE"
+                desc: '''
+                        Incremented whenever AW handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "17:17",
+                resval: "0",
+                name: "DMA_AW_BW"
+                desc: '''
+                        Whenever AW handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "18:18",
+                resval: "0",
+                name: "DMA_AR_DONE"
+                desc: '''
+                        Incremented whenever AR handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "19:19",
+                resval: "0",
+                name: "DMA_AR_BW"
+                desc: '''
+                        Whenever AR handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "20:20",
+                resval: "0",
+                name: "DMA_R_DONE"
+                desc: '''
+                        Incremented whenever R handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "21:21",
+                resval: "0",
+                name: "DMA_R_BW"
+                desc: '''
+                        Whenever R handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "22:22",
+                resval: "0",
+                name: "DMA_W_DONE"
+                desc: '''
+                        Incremented whenvever W handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "23:23",
+                resval: "0",
+                name: "DMA_W_BW"
+                desc: '''
+                        Whenever W handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "24:24",
+                resval: "0",
+                name: "DMA_B_DONE"
+                desc: '''
+                        Incremented whenever B handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "25:25",
+                resval: "0",
+                name: "DMA_BUSY"
+                desc: '''
+                        Incremented whenever DMA is busy.
+                        _This is a DMA-local signal_
+                        '''
+            },
+                        {
+                bits: "26:26",
+                resval: "0",
+                name: "ICACHE_MISS"
+                desc: '''
+                        Incremented for instruction cache misses.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "27:27",
+                resval: "0",
+                name: "ICACHE_HIT"
+                desc: '''
+                        Incremented for instruction cache hits.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "28:28",
+                resval: "0",
+                name: "ICACHE_PREFETCH"
+                desc: '''
+                        Incremented for instruction cache prefetches.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "29:29",
+                resval: "0",
+                name: "ICACHE_DOUBLE_HIT"
+                desc: '''
+                        Incremented for instruction cache double hit.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "30:30",
+                resval: "0",
+                name: "ICACHE_STALL"
+                desc: '''
+                        Incremented for instruction cache stalls.
+                        _This is a hart-local signal_
+                        '''
+            },
+            ]
+        }
+    },
+    {
+        multireg: {
+            name: "HART_SELECT",
+            desc: '''Select from which hart in the cluster, starting from `0`,
+                     the event should be counted. For each performance counter
+                     the cores can be selected individually. If a hart greater
+                     than the clusters total hart size is selected the selection
+                     will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+                     will be selected.'''
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "hart_select",
+            compact: "false",
+            fields: [{
+                bits: "9:0",
+                name: "HART_SELECT",
+                desc: "Select source of per-hart performance counter"
+            }]
+        }
+    }
+    {
+        multireg: {
+            name: "PERF_COUNTER",
+            desc: '''Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+            performance metric you would like to track.'''
+            swaccess: "rw",
+            hwaccess: "hrw",
+            count: "NumPerfCounters",
+            cname: "performance_counter",
+            hwext: "true",
+            hwqe: "true",
+            fields: [{
+                bits: "47:0",
+                name: "PERF_COUNTER",
+                desc: "Performance counter"
+            }]
+        }
+    },
+    {
+        name: "CL_CLINT_SET",
+        desc: '''
+        Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_SET",
+              desc: "Set cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "CL_CLINT_CLEAR",
+        desc: '''
+        Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_CLEAR",
+              desc: "Clear cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "HW_BARRIER",
+        desc: '''Hardware barrier register. Loads to this register will block until all cores have
+        performed the load. At this stage we know that they reached the same point in the control flow,
+        i.e., the cores are synchronized.'''
+        swaccess: "ro",
+        hwaccess: "hrw",
+        hwext: "true",
+        fields: [{
+            bits: "31:0",
+            name: "HW_BARRIER",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "ICACHE_PREFETCH_ENABLE",
+        desc: '''Controls prefetching of the instruction cache.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        resval: "1",
+        fields: [{
+            bits: "0:0",
+            name: "ICACHE_PREFETCH_ENABLE",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "SPATZ_STATUS",
+        desc: '''Sets the status of the Spatz cluster.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        fields: [{
+            bits: "0:0",
+            resval: "0",
+            name: "SPATZ_CLUSTER_PROBE",
+            desc: "Indicates the cluster is computing a kernel."
+        }]
+    },
+    {
+        name: "CLUSTER_BOOT_CONTROL",
+        desc: '''Controls the cluster boot process.'''
+        swaccess: "rw",
+        hwaccess: "hro",
+        resval: "0",
+        fields: [{
+            bits: "31:0",
+            name: "ENTRY_POINT",
+            desc: "Post-bootstrapping entry point."
+        }]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/FP_Cluster/data/spatz_cluster_peripheral_reg_doc.hjson b/docs/um/ip/FP_Cluster/data/spatz_cluster_peripheral_reg_doc.hjson
new file mode 100644
index 00000000..17337b00
--- /dev/null
+++ b/docs/um/ip/FP_Cluster/data/spatz_cluster_peripheral_reg_doc.hjson
@@ -0,0 +1,435 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+{
+    param_list: [
+        { name: "NumPerfCounters",
+        desc: "Number of performance counters",
+        type: "int",
+        default: "2"
+        },
+    ],
+    name: "spatz_cluster_peripheral",
+    cip_id: "36",
+    version: "0.4.3",
+    clocking: [
+     {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+    ],
+    bus_interfaces: [
+        { protocol: "tlul", direction: "device"}
+    ]
+    regwidth: 64,
+    registers: [{
+        multireg: {
+            name: "PERF_COUNTER_ENABLE",
+            desc: "Enable particular performance counter and start tracking.",
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "performance_counter_enable",
+            fields: [{
+                bits: "0:0",
+                resval: "0",
+                name: "CYCLE",
+                desc: '''
+                    Cycle counter. Counts up as long as the cluster is powered.
+                    '''
+            },
+            {
+                bits: "1:1",
+                resval: "0",
+                name: "TCDM_ACCESSED"
+                desc: '''
+                        Increased whenever the TCDM is accessed. Each individual access is tracked,
+                        so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+                        so it doesn't matter whether the cores or the for example the SSR hardware accesses
+                        the TCDM. _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "2:2",
+                resval: "0",
+                name: "TCDM_CONGESTED"
+                desc: '''
+                        Incremented whenever an access twoards the TCDM is made but the arbitration
+                        logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+                        _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "3:3",
+                resval: "0",
+                name: "ISSUE_FPU"
+                desc: '''
+                        Core operations performed in the FPU. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "4:4",
+                resval: "0",
+                name: "ISSUE_FPU_SEQ"
+                desc: '''
+                        Incremented whenever the FPU Sequencer issues an FPU instruction.
+                        Might be non available if the hardware doesn't support FREP.
+                        _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "5:5",
+                resval: "0",
+                name: "ISSUE_CORE_TO_FPU"
+                desc: '''Incremented whenever the core issues an FPU instruction.
+                        _This is a hart-local signal._'''
+            },
+            {
+                bits: "6:6",
+                resval: "0",
+                name: "RETIRED_INSTR"
+                desc: '''
+                        Instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "7:7",
+                resval: "0",
+                name: "RETIRED_LOAD"
+                desc: '''
+                        Load instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "8:8",
+                resval: "0",
+                name: "RETIRED_I"
+                desc: '''
+                        Base instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "9:9",
+                resval: "0",
+                name: "RETIRED_ACC"
+                desc: '''
+                        Offloaded instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "10:10",
+                resval: "0",
+                name: "DMA_AW_STALL"
+                desc: '''
+                        Incremented whenever aw_valid = 1 but aw_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "11:11",
+                resval: "0",
+                name: "DMA_AR_STALL"
+                desc: '''
+                        Incremented whenever ar_valid = 1 but ar_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "12:12",
+                resval: "0",
+                name: "DMA_R_STALL"
+                desc: '''
+                        Incremented whenever r_ready = 1 but r_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "13:13",
+                resval: "0",
+                name: "DMA_W_STALL"
+                desc: '''
+                        Incremented whenever w_valid = 1 but w_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "14:14",
+                resval: "0",
+                name: "DMA_BUF_W_STALL"
+                desc: '''
+                        Incremented whenever w_ready = 1 but w_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "15:15",
+                resval: "0",
+                name: "DMA_BUF_R_STALL"
+                desc: '''
+                        Incremented whenever r_valid = 1 but r_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "16:16",
+                resval: "0",
+                name: "DMA_AW_DONE"
+                desc: '''
+                        Incremented whenever AW handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "17:17",
+                resval: "0",
+                name: "DMA_AW_BW"
+                desc: '''
+                        Whenever AW handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "18:18",
+                resval: "0",
+                name: "DMA_AR_DONE"
+                desc: '''
+                        Incremented whenever AR handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "19:19",
+                resval: "0",
+                name: "DMA_AR_BW"
+                desc: '''
+                        Whenever AR handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "20:20",
+                resval: "0",
+                name: "DMA_R_DONE"
+                desc: '''
+                        Incremented whenever R handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "21:21",
+                resval: "0",
+                name: "DMA_R_BW"
+                desc: '''
+                        Whenever R handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "22:22",
+                resval: "0",
+                name: "DMA_W_DONE"
+                desc: '''
+                        Incremented whenvever W handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "23:23",
+                resval: "0",
+                name: "DMA_W_BW"
+                desc: '''
+                        Whenever W handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "24:24",
+                resval: "0",
+                name: "DMA_B_DONE"
+                desc: '''
+                        Incremented whenever B handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "25:25",
+                resval: "0",
+                name: "DMA_BUSY"
+                desc: '''
+                        Incremented whenever DMA is busy.
+                        _This is a DMA-local signal_
+                        '''
+            },
+                        {
+                bits: "26:26",
+                resval: "0",
+                name: "ICACHE_MISS"
+                desc: '''
+                        Incremented for instruction cache misses.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "27:27",
+                resval: "0",
+                name: "ICACHE_HIT"
+                desc: '''
+                        Incremented for instruction cache hits.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "28:28",
+                resval: "0",
+                name: "ICACHE_PREFETCH"
+                desc: '''
+                        Incremented for instruction cache prefetches.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "29:29",
+                resval: "0",
+                name: "ICACHE_DOUBLE_HIT"
+                desc: '''
+                        Incremented for instruction cache double hit.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "30:30",
+                resval: "0",
+                name: "ICACHE_STALL"
+                desc: '''
+                        Incremented for instruction cache stalls.
+                        _This is a hart-local signal_
+                        '''
+            },
+            ]
+        }
+    },
+    {
+        multireg: {
+            name: "HART_SELECT",
+            desc: '''Select from which hart in the cluster, starting from `0`,
+                     the event should be counted. For each performance counter
+                     the cores can be selected individually. If a hart greater
+                     than the clusters total hart size is selected the selection
+                     will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+                     will be selected.'''
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "hart_select",
+            compact: "false",
+            fields: [{
+                bits: "9:0",
+                name: "HART_SELECT",
+                desc: "Select source of per-hart performance counter"
+            }]
+        }
+    }
+    {
+        multireg: {
+            name: "PERF_COUNTER",
+            desc: '''Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+            performance metric you would like to track.'''
+            swaccess: "rw",
+            hwaccess: "hrw",
+            count: "NumPerfCounters",
+            cname: "performance_counter",
+            hwext: "true",
+            hwqe: "true",
+            fields: [{
+                bits: "47:0",
+                name: "PERF_COUNTER",
+                desc: "Performance counter"
+            }]
+        }
+    },
+    {
+        name: "CL_CLINT_SET",
+        desc: '''
+        Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_SET",
+              desc: "Set cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "CL_CLINT_CLEAR",
+        desc: '''
+        Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_CLEAR",
+              desc: "Clear cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "HW_BARRIER",
+        desc: '''Hardware barrier register. Loads to this register will block until all cores have
+        performed the load. At this stage we know that they reached the same point in the control flow,
+        i.e., the cores are synchronized.'''
+        swaccess: "ro",
+        hwaccess: "hrw",
+        hwext: "true",
+        fields: [{
+            bits: "31:0",
+            name: "HW_BARRIER",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "ICACHE_PREFETCH_ENABLE",
+        desc: '''Controls prefetching of the instruction cache.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        resval: "1",
+        fields: [{
+            bits: "0:0",
+            name: "ICACHE_PREFETCH_ENABLE",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "SPATZ_STATUS",
+        desc: '''Sets the status of the Spatz cluster.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        fields: [{
+            bits: "0:0",
+            resval: "0",
+            name: "SPATZ_CLUSTER_PROBE",
+            desc: "Indicates the cluster is computing a kernel."
+        }]
+    },
+    {
+        name: "CLUSTER_BOOT_CONTROL",
+        desc: '''Controls the cluster boot process.'''
+        swaccess: "rw",
+        hwaccess: "hro",
+        resval: "0",
+        fields: [{
+            bits: "31:0",
+            name: "ENTRY_POINT",
+            desc: "Post-bootstrapping entry point."
+        }]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/FP_Cluster/doc/registers.md b/docs/um/ip/FP_Cluster/doc/registers.md
new file mode 100644
index 00000000..79bc211c
--- /dev/null
+++ b/docs/um/ip/FP_Cluster/doc/registers.md
@@ -0,0 +1,386 @@
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                                                         |
+|:-----------------------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------|
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_0`](#perf_counter_enable)     | 0x0      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_1`](#perf_counter_enable)     | 0x8      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_0`](#hart_select)                     | 0x10     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_1`](#hart_select)                     | 0x18     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_0`](#perf_counter)                   | 0x20     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`PERF_COUNTER_1`](#perf_counter)                   | 0x28     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`CL_CLINT_SET`](#cl_clint_set)                     | 0x30     |        8 | Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt     |
+| spatz_cluster_peripheral.[`CL_CLINT_CLEAR`](#cl_clint_clear)                 | 0x38     |        8 | Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt |
+| spatz_cluster_peripheral.[`HW_BARRIER`](#hw_barrier)                         | 0x40     |        8 | Hardware barrier register. Loads to this register will block until all cores have                   |
+| spatz_cluster_peripheral.[`ICACHE_PREFETCH_ENABLE`](#icache_prefetch_enable) | 0x48     |        8 | Controls prefetching of the instruction cache.                                                      |
+| spatz_cluster_peripheral.[`SPATZ_STATUS`](#spatz_status)                     | 0x50     |        8 | Sets the status of the Spatz cluster.                                                               |
+| spatz_cluster_peripheral.[`CLUSTER_BOOT_CONTROL`](#cluster_boot_control)     | 0x58     |        8 | Controls the cluster boot process.                                                                  |
+
+## PERF_COUNTER_ENABLE
+Enable particular performance counter and start tracking.
+- Reset default: `0x0`
+- Reset mask: `0x7fffffff`
+
+### Instances
+
+| Name                  | Offset   |
+|:----------------------|:---------|
+| PERF_COUNTER_ENABLE_0 | 0x0      |
+| PERF_COUNTER_ENABLE_1 | 0x8      |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CYCLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_ACCESSED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_CONGESTED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU_SEQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_CORE_TO_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_INSTR", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_LOAD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_I", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_ACC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_B_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUSY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_MISS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_PREFETCH", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_DOUBLE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 33}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                         |
+|:------:|:------:|:-------:|:-------------------------------------------------------------|
+| 63:31  |        |         | Reserved                                                     |
+|   30   |   rw   |   0x0   | [ICACHE_STALL](#perf_counter_enable--icache_stall)           |
+|   29   |   rw   |   0x0   | [ICACHE_DOUBLE_HIT](#perf_counter_enable--icache_double_hit) |
+|   28   |   rw   |   0x0   | [ICACHE_PREFETCH](#perf_counter_enable--icache_prefetch)     |
+|   27   |   rw   |   0x0   | [ICACHE_HIT](#perf_counter_enable--icache_hit)               |
+|   26   |   rw   |   0x0   | [ICACHE_MISS](#perf_counter_enable--icache_miss)             |
+|   25   |   rw   |   0x0   | [DMA_BUSY](#perf_counter_enable--dma_busy)                   |
+|   24   |   rw   |   0x0   | [DMA_B_DONE](#perf_counter_enable--dma_b_done)               |
+|   23   |   rw   |   0x0   | [DMA_W_BW](#perf_counter_enable--dma_w_bw)                   |
+|   22   |   rw   |   0x0   | [DMA_W_DONE](#perf_counter_enable--dma_w_done)               |
+|   21   |   rw   |   0x0   | [DMA_R_BW](#perf_counter_enable--dma_r_bw)                   |
+|   20   |   rw   |   0x0   | [DMA_R_DONE](#perf_counter_enable--dma_r_done)               |
+|   19   |   rw   |   0x0   | [DMA_AR_BW](#perf_counter_enable--dma_ar_bw)                 |
+|   18   |   rw   |   0x0   | [DMA_AR_DONE](#perf_counter_enable--dma_ar_done)             |
+|   17   |   rw   |   0x0   | [DMA_AW_BW](#perf_counter_enable--dma_aw_bw)                 |
+|   16   |   rw   |   0x0   | [DMA_AW_DONE](#perf_counter_enable--dma_aw_done)             |
+|   15   |   rw   |   0x0   | [DMA_BUF_R_STALL](#perf_counter_enable--dma_buf_r_stall)     |
+|   14   |   rw   |   0x0   | [DMA_BUF_W_STALL](#perf_counter_enable--dma_buf_w_stall)     |
+|   13   |   rw   |   0x0   | [DMA_W_STALL](#perf_counter_enable--dma_w_stall)             |
+|   12   |   rw   |   0x0   | [DMA_R_STALL](#perf_counter_enable--dma_r_stall)             |
+|   11   |   rw   |   0x0   | [DMA_AR_STALL](#perf_counter_enable--dma_ar_stall)           |
+|   10   |   rw   |   0x0   | [DMA_AW_STALL](#perf_counter_enable--dma_aw_stall)           |
+|   9    |   rw   |   0x0   | [RETIRED_ACC](#perf_counter_enable--retired_acc)             |
+|   8    |   rw   |   0x0   | [RETIRED_I](#perf_counter_enable--retired_i)                 |
+|   7    |   rw   |   0x0   | [RETIRED_LOAD](#perf_counter_enable--retired_load)           |
+|   6    |   rw   |   0x0   | [RETIRED_INSTR](#perf_counter_enable--retired_instr)         |
+|   5    |   rw   |   0x0   | [ISSUE_CORE_TO_FPU](#perf_counter_enable--issue_core_to_fpu) |
+|   4    |   rw   |   0x0   | [ISSUE_FPU_SEQ](#perf_counter_enable--issue_fpu_seq)         |
+|   3    |   rw   |   0x0   | [ISSUE_FPU](#perf_counter_enable--issue_fpu)                 |
+|   2    |   rw   |   0x0   | [TCDM_CONGESTED](#perf_counter_enable--tcdm_congested)       |
+|   1    |   rw   |   0x0   | [TCDM_ACCESSED](#perf_counter_enable--tcdm_accessed)         |
+|   0    |   rw   |   0x0   | [CYCLE](#perf_counter_enable--cycle)                         |
+
+### PERF_COUNTER_ENABLE . ICACHE_STALL
+  Incremented for instruction cache stalls.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_DOUBLE_HIT
+  Incremented for instruction cache double hit.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_PREFETCH
+  Incremented for instruction cache prefetches.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_HIT
+  Incremented for instruction cache hits.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_MISS
+  Incremented for instruction cache misses.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUSY
+  Incremented whenever DMA is busy.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_B_DONE
+  Incremented whenever B handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_BW
+  Whenever W handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_DONE
+  Incremented whenvever W handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_BW
+  Whenever R handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_DONE
+  Incremented whenever R handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_BW
+  Whenever AR handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_DONE
+  Incremented whenever AR handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_BW
+  Whenever AW handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_DONE
+  Incremented whenever AW handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_R_STALL
+  Incremented whenever r_valid = 1 but r_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_W_STALL
+  Incremented whenever w_ready = 1 but w_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_STALL
+  Incremented whenever w_valid = 1 but w_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_STALL
+  Incremented whenever r_ready = 1 but r_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_STALL
+  Incremented whenever ar_valid = 1 but ar_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_STALL
+  Incremented whenever aw_valid = 1 but aw_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_ACC
+  Offloaded instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_I
+  Base instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_LOAD
+  Load instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_INSTR
+  Instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_CORE_TO_FPU
+Incremented whenever the core issues an FPU instruction.
+  _This is a hart-local signal._
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU_SEQ
+  Incremented whenever the FPU Sequencer issues an FPU instruction.
+  Might be non available if the hardware doesn't support FREP.
+  _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU
+  Core operations performed in the FPU. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_CONGESTED
+  Incremented whenever an access twoards the TCDM is made but the arbitration
+  logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+  _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_ACCESSED
+  Increased whenever the TCDM is accessed. Each individual access is tracked,
+  so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+  so it doesn't matter whether the cores or the for example the SSR hardware accesses
+  the TCDM. _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . CYCLE
+Cycle counter. Counts up as long as the cluster is powered.
+
+## HART_SELECT
+Select from which hart in the cluster, starting from `0`,
+   the event should be counted. For each performance counter
+   the cores can be selected individually. If a hart greater
+   than the clusters total hart size is selected the selection
+   will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+   will be selected.
+- Reset default: `0x0`
+- Reset mask: `0x3ff`
+
+### Instances
+
+| Name          | Offset   |
+|:--------------|:---------|
+| HART_SELECT_0 | 0x10     |
+| HART_SELECT_1 | 0x18     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HART_SELECT", "bits": 10, "attr": ["rw"], "rotate": -90}, {"bits": 54}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                   |
+|:------:|:------:|:-------:|:------------|:----------------------------------------------|
+| 63:10  |        |         |             | Reserved                                      |
+|  9:0   |   rw   |   0x0   | HART_SELECT | Select source of per-hart performance counter |
+
+## PERF_COUNTER
+Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+performance metric you would like to track.
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| PERF_COUNTER_0 | 0x20     |
+| PERF_COUNTER_1 | 0x28     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERF_COUNTER", "bits": 48, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description         |
+|:------:|:------:|:-------:|:-------------|:--------------------|
+| 63:48  |        |         |              | Reserved            |
+|  47:0  |   rw   |    x    | PERF_COUNTER | Performance counter |
+
+## CL_CLINT_SET
+Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_SET", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                           |
+|:------:|:------:|:-------:|:-------------|:--------------------------------------|
+| 63:32  |        |         |              | Reserved                              |
+|  31:0  |   wo   |    x    | CL_CLINT_SET | Set cluster-local interrupt of hart i |
+
+## CL_CLINT_CLEAR
+Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_CLEAR", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                             |
+|:------:|:------:|:-------:|:---------------|:----------------------------------------|
+| 63:32  |        |         |                | Reserved                                |
+|  31:0  |   wo   |    x    | CL_CLINT_CLEAR | Clear cluster-local interrupt of hart i |
+
+## HW_BARRIER
+Hardware barrier register. Loads to this register will block until all cores have
+performed the load. At this stage we know that they reached the same point in the control flow,
+i.e., the cores are synchronized.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HW_BARRIER", "bits": 32, "attr": ["ro"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                |
+|:------:|:------:|:-------:|:-----------|:---------------------------|
+| 63:32  |        |         |            | Reserved                   |
+|  31:0  |   ro   |    x    | HW_BARRIER | Hardware barrier register. |
+
+## ICACHE_PREFETCH_ENABLE
+Controls prefetching of the instruction cache.
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ICACHE_PREFETCH_ENABLE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                |
+|:------:|:------:|:-------:|:-----------------------|:---------------------------|
+|  63:1  |        |         |                        | Reserved                   |
+|   0    |   wo   |   0x1   | ICACHE_PREFETCH_ENABLE | Hardware barrier register. |
+
+## SPATZ_STATUS
+Sets the status of the Spatz cluster.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_PROBE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description                                  |
+|:------:|:------:|:-------:|:--------------------|:---------------------------------------------|
+|  63:1  |        |         |                     | Reserved                                     |
+|   0    |   wo   |   0x0   | SPATZ_CLUSTER_PROBE | Indicates the cluster is computing a kernel. |
+
+## CLUSTER_BOOT_CONTROL
+Controls the cluster boot process.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENTRY_POINT", "bits": 32, "attr": ["rw"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                     |
+|:------:|:------:|:-------:|:------------|:--------------------------------|
+| 63:32  |        |         |             | Reserved                        |
+|  31:0  |   rw   |   0x0   | ENTRY_POINT | Post-bootstrapping entry point. |
+
diff --git a/docs/um/ip/GP_timer1_System_timer/data/timer_unit.hjson b/docs/um/ip/GP_timer1_System_timer/data/timer_unit.hjson
new file mode 100644
index 00000000..2065c2cb
--- /dev/null
+++ b/docs/um/ip/GP_timer1_System_timer/data/timer_unit.hjson
@@ -0,0 +1,282 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Florent Rotenberg <florent.rotenberg@greenwaves-technologies.com>
+# timer unit(system timer) register
+
+{
+  name: "timer_unit"
+  one_paragraph_desc: '''
+  BASIC TIMER component manages the following features:
+  - 2 general purpose 32bits up counter timers
+  - Input trigger sources:
+       - FLL clock
+       - FLL clock + Prescaler
+       - Reference clock at 32kHz
+       - External event
+  - 8bit programmable prescaler to FLL clock
+  - Counting modes:
+       - One shot mode: timer is stopped after first comparison match
+       - Continuous mode: timer continues counting after comparison match
+       - Cycle mode: timer resets to 0 after comparison match and continues counting
+       - 64 bit cascaded mode
+  - Interrupt request generation on comparison match
+  '''
+  cip_id:  "36",
+  version: "1.0.3"
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "CFG_LO"
+      desc: "Timer Low Configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0"
+          name: "ENABLE"
+          resval: 0x0
+          desc: '''Timer low enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+		'''
+        }
+        { bits: "1"
+          name: "RESET"
+          resval: 0x0
+          desc: "Timer low counter reset command bitfield. Cleared after Timer Low reset execution."
+        }
+        { bits: "2"
+          name: "IRQEN"
+          resval: 0x0
+          desc: '''Timer low compare match interrupt enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "3"
+          name: "IEM"
+          resval: 0x0
+          desc: '''Timer low input event mask configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "4"
+          name: "MODE"
+          resval: 0x0
+          desc: '''Timer low continuous mode configuration bitfield:
+                - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs.
+                - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs.
+                '''
+        }
+        { bits: "5"
+          name: "ONE_S"
+          resval: 0x0
+          desc: '''Timer low one shot configuration bitfield:
+                - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs.
+                - 1'b1: disable Timer low when compare match with CMP_LO occurs.
+                '''
+        }
+        { bits: "6"
+          name: "PEN"
+          resval: 0x0
+          desc: '''Timer low prescaler enable configuration bitfield:
+	        - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "7"
+          name: "CCFG"
+          resval: 0x0
+          desc: '''Timer low clock source configuration bitfield:
+                - 1'b0: FLL or FLL+Prescaler
+                - 1'b1: Reference clock at 32kHz
+                '''
+        }
+	{ bits: "15:8"
+          name: "PVAL"
+          resval: 0x0
+          desc: "Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL)"
+        }
+	{ bits: "31"
+          name: "CASC"
+          resval: 0x0
+          desc: "Timer low  + Timer high 64bit cascaded mode configuration bitfield."
+        }
+      ]
+    }
+    { name: "CFG_HI"
+      desc: "Timer HIGH Configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0"
+          name: "ENABLE"
+          resval: 0x0
+          desc: '''Timer high enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "1"
+          name: "RESET"
+	  swaccess: "wo"
+          hwaccess: "hro"
+          resval: 0x0
+          desc: "Timer high counter reset command bitfield. Cleared after Timer high reset execution."
+        }
+        { bits: "2"
+          name: "IRQEN"
+          resval: 0x0
+          desc: '''Timer high compare match interrupt enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "3"
+          name: "IEM"
+          resval: 0x0
+          desc: '''Timer high input event mask configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled	
+                '''
+        }
+        { bits: "4"
+          name: "MODE"
+          resval: 0x0
+          desc: '''Timer high continuous mode configuration bitfield:
+                - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_HI occurs.
+                - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_HI occurs.
+                '''
+        }
+        { bits: "5"
+          name: "ONE_S"
+          resval: 0x0
+          desc: '''Timer high one shot configuration bitfield:
+                - 1'b0: let Timer high enabled counting when compare match with CMP_HI occurs.
+                - 1'b1: disable Timer high when compare match with CMP_HI occurs.
+                '''
+        }
+        { bits: "6"
+          name: "PEN"
+          resval: 0x0
+          desc: '''Timer high prescaler enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "7"
+          name: "CLKCFG"
+          resval: 0x0
+          desc: '''Timer high clock source configuration bitfield:
+                - 1'b0: FLL or FLL+Prescaler
+                - 1'b1: Reference clock at 32kHz
+                '''
+	}	
+      ]
+    }
+    { name: "CNT_LO"
+      desc: "Timer Low counter value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cnt_lo"
+          resval: 0x0
+          desc: "Timer Low counter value bitfield."
+        }
+      ]
+    }
+    { name: "CNT_HI"
+      desc: "Timer High counter value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cnt_hi"
+          resval: 0x0
+          desc: "Timer High counter value bitfield."
+        }
+      ]
+    }
+    { name: "CMP_LO"
+      desc: "Timer Low comparator value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cmp_lo"
+          resval: 0x0
+          desc: "Timer Low comparator value bitfield."
+        }
+      ]
+    }
+    { name: "CMP_HI"
+      desc: "Timer High comparator value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cmp_hi"
+          resval: 0x0
+          desc: "Timer High comparator value bitfield."
+        }
+      ]
+    }
+    { name: "START_LO"
+      desc: "Start Timer Low counting register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "strt_lo"
+          resval: 0x0
+          desc: "Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set."
+        }
+      ]
+    }
+    { name: "START_HI"
+      desc: "Start Timer High counting register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "strt_hi"
+          resval: 0x0
+          desc: "Timer High start command bitfield. When executed, CFG_HI.ENABLE is set."
+        }
+      ]
+    }
+    { name: "RESET_LO"
+      desc: "Reset Timer Low counter register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "rst_lo"
+          resval: 0x0
+          desc: "Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set."
+        }
+      ]
+    }
+    { name: "RESET_HI"
+      desc: "Reset Timer High counter register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "rst_hi"
+          resval: 0x0
+          desc: "Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set."
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/GP_timer1_System_timer/doc/registers.md b/docs/um/ip/GP_timer1_System_timer/doc/registers.md
new file mode 100644
index 00000000..c4dc75d0
--- /dev/null
+++ b/docs/um/ip/GP_timer1_System_timer/doc/registers.md
@@ -0,0 +1,197 @@
+## Summary
+
+| Name                               | Offset   |   Length | Description                           |
+|:-----------------------------------|:---------|---------:|:--------------------------------------|
+| timer_unit.[`CFG_LO`](#cfg_lo)     | 0x0      |        4 | Timer Low Configuration register.     |
+| timer_unit.[`CFG_HI`](#cfg_hi)     | 0x4      |        4 | Timer HIGH Configuration register.    |
+| timer_unit.[`CNT_LO`](#cnt_lo)     | 0x8      |        4 | Timer Low counter value register.     |
+| timer_unit.[`CNT_HI`](#cnt_hi)     | 0xc      |        4 | Timer High counter value register.    |
+| timer_unit.[`CMP_LO`](#cmp_lo)     | 0x10     |        4 | Timer Low comparator value register.  |
+| timer_unit.[`CMP_HI`](#cmp_hi)     | 0x14     |        4 | Timer High comparator value register. |
+| timer_unit.[`START_LO`](#start_lo) | 0x18     |        4 | Start Timer Low counting register.    |
+| timer_unit.[`START_HI`](#start_hi) | 0x1c     |        4 | Start Timer High counting register.   |
+| timer_unit.[`RESET_LO`](#reset_lo) | 0x20     |        4 | Reset Timer Low counter register.     |
+| timer_unit.[`RESET_HI`](#reset_hi) | 0x24     |        4 | Reset Timer High counter register.    |
+
+## CFG_LO
+Timer Low Configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x8000ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PVAL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 15}, {"name": "CASC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | CASC   | Timer low  + Timer high 64bit cascaded mode configuration bitfield.                                                                                                                                                                          |
+| 30:16  |        |         |        | Reserved                                                                                                                                                                                                                                     |
+|  15:8  |   rw   |   0x0   | PVAL   | Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL)                                                                                                                                                                          |
+|   7    |   rw   |   0x0   | CCFG   | Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                 |
+|   6    |   rw   |   0x0   | PEN    | Timer low prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   5    |   rw   |   0x0   | ONE_S  | Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low when compare match with CMP_LO occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer low continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   2    |   rw   |   0x0   | IRQEN  | Timer low compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                            |
+|   1    |   rw   |   0x0   | RESET  | Timer low counter reset command bitfield. Cleared after Timer Low reset execution.                                                                                                                                                           |
+|   0    |   rw   |   0x0   | ENABLE | Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                    |
+
+## CFG_HI
+Timer HIGH Configuration register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLKCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                     |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                                                        |
+|   7    |   rw   |   0x0   | CLKCFG | Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                   |
+|   6    |   rw   |   0x0   | PEN    | Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   5    |   rw   |   0x0   | ONE_S  | Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled counting when compare match with CMP_HI occurs. - 1'b1: disable Timer high when compare match with CMP_HI occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer high continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_HI occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_HI occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   2    |   rw   |   0x0   | IRQEN  | Timer high compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                              |
+|   1    |   wo   |   0x0   | RESET  | Timer high counter reset command bitfield. Cleared after Timer high reset execution.                                                                                                                                                            |
+|   0    |   rw   |   0x0   | ENABLE | Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                      |
+
+## CNT_LO
+Timer Low counter value register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                       |
+|:------:|:------:|:-------:|:-------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_lo | Timer Low counter value bitfield. |
+
+## CNT_HI
+Timer High counter value register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_hi | Timer High counter value bitfield. |
+
+## CMP_LO
+Timer Low comparator value register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                          |
+|:------:|:------:|:-------:|:-------|:-------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_lo | Timer Low comparator value bitfield. |
+
+## CMP_HI
+Timer High comparator value register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_hi | Timer High comparator value bitfield. |
+
+## START_LO
+Start Timer Low counting register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                               |
+|   0    |   wo   |   0x0   | strt_lo | Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set. |
+
+## START_HI
+Start Timer High counting register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                             |
+|:------:|:------:|:-------:|:--------|:------------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                                |
+|   0    |   wo   |   0x0   | strt_hi | Timer High start command bitfield. When executed, CFG_HI.ENABLE is set. |
+
+## RESET_LO
+Reset Timer Low counter register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                   |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                      |
+|   0    |   wo   |   0x0   | rst_lo | Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set. |
+
+## RESET_HI
+Reset Timer High counter register.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                       |
+|   0    |   wo   |   0x0   | rst_hi | Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set. |
+
diff --git a/docs/um/ip/GP_timer2_Advanced_timer/data/apb_adv_timer.hjson b/docs/um/ip/GP_timer2_Advanced_timer/data/apb_adv_timer.hjson
new file mode 100644
index 00000000..016be8a8
--- /dev/null
+++ b/docs/um/ip/GP_timer2_Advanced_timer/data/apb_adv_timer.hjson
@@ -0,0 +1,1020 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Florent Rotenberg <florent.rotenberg@greenwaves-technologies.com>
+# APB Advanced timer register
+{
+  name: "apb_adv_timer"
+  one_paragraph_desc: '''
+  ADV_ TIMER component manages the following features:
+  - 4 advanced timers with 4 output signal channels each. Provides PWM generation functionality
+  - multiple trigger input sources:
+     - output signal channels of all timers
+     - 32 GPIOs
+     - reference clock at 32kHz
+     - FLL clock
+  - configurable input trigger modes
+  - configurable prescaler for each timer
+  - configurable counting mode for each timer
+  - configurable channel threshold action for each timer
+  - 4 configurable output events
+  - configurable clock gating of each timer
+  '''
+  cip_id:  "36",
+  version: "1.0.4"
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "T0_CMD"
+      desc: "ADV_TIMER0 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER0 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER0 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER0 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER0 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER0 arm command bitfield."
+        }
+        { bits: "31:5"
+          name: "RFU"
+          resval: 0x0
+          desc: "?"
+        }
+      ]
+    }
+    { name: "T0_CONFIG"
+      desc: "ADV_TIMER0 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER0 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+	  swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER0 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER0 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+        { bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER0 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.	
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER0 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T0_THRESHOLD"
+      desc: "ADV_TIMER0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value."
+        }
+	{ bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL0"
+      desc: "ADV_TIMER0 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 0 threshold configuration bitfield."
+        }
+	{ bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+	        '''
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL1"
+      desc: "ADV_TIMER0 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc:	'''ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL2"
+      desc: "ADV_TIMER0 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc:	'''ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL3"
+      desc: "ADV_TIMER0 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc:	'''ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T0_COUNTER"
+      desc: "ADV_TIMER0 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER0 counter value."
+        }
+      ]
+    }
+    { name: "T1_CMD"
+      desc: "ADV_TIMER1 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER1 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER1 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER1 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER1 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER1 arm command bitfield."
+        }
+      ]
+    }
+    { name: "T1_CONFIG"
+      desc: "ADV_TIMER1 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER1 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+          swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER1 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER1 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+	{ bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER1 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER1 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T1_THRESHOLD"
+      desc: "ADV_TIMER1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value."
+        }
+        { bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL0"
+      desc: "ADV_TIMER1 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 0 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL1"
+      desc: "ADV_TIMER1 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL2"
+      desc: "ADV_TIMER1 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL3"
+      desc: "ADV_TIMER1 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_COUNTER"
+      desc: "ADV_TIMER1 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER1 counter value."
+        }
+      ]
+    }
+    { name: "T2_CMD"
+      desc: "ADV_TIMER2 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER2 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER2 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER2 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER2 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER2 arm command bitfield."
+        }
+      ]
+    }
+    { name: "T2_CONFIG"
+      desc: "ADV_TIMER2 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER2 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+          swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER2 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER2 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+        { bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER2 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER2 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T2_THRESHOLD"
+      desc: "ADV_TIMER2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value."
+        }
+        { bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL0"
+      desc: "ADV_TIMER2 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 0 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL1"
+      desc: "ADV_TIMER2 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL2"
+      desc: "ADV_TIMER2 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL3"
+      desc: "ADV_TIMER2 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_COUNTER"
+      desc: "ADV_TIMER2 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER2 counter value."
+        }
+      ]
+    }
+    { name: "T3_CMD"
+      desc: "ADV_TIMER3 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER3 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER3 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER3 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER3 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER3 arm command bitfield."
+        }
+      ]
+    }
+    { name: "T3_CONFIG"
+      desc: "ADV_TIMER3 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER3 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+          swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER3 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER3 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+        { bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER3 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER3 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T3_THRESHOLD"
+      desc: "ADV_TIMER3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value."
+        }
+        { bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL0"
+      desc: "ADV_TIMER3 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 0 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL1"
+      desc: "ADV_TIMER3 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL2"
+      desc: "ADV_TIMER3 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL3"
+      desc: "ADV_TIMER3 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_COUNTER"
+      desc: "ADV_TIMER3 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER3 counter value."
+        }
+      ]
+    }
+    { name: "EVENT_CFG"
+      desc: "ADV_TIMERS events configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "3:0"
+          name: "SEL0"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 0 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+	{ bits: "7:4"
+          name: "SEL1"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 1 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+	{ bits: "11:8"
+          name: "SEL2"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 2 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+	{ bits: "15:12"
+          name: "SEL3"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 3 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+        { bits: "19:16"
+          name: "ENA"
+          resval: 0x0
+          desc: "ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation."
+        }
+      ]
+    }
+    { name: "CG"
+      desc: "ADV_TIMERS channels clock gating configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "3:0"
+          name: "ENA"
+          resval: 0x0
+          desc: '''ADV_TIMER clock gating configuration bitfield.
+                - ENA[i]=0: clock gate ADV_TIMERi.
+                - ENA[i]=1: enable ADV_TIMERi.
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/GP_timer2_Advanced_timer/doc/registers.md b/docs/um/ip/GP_timer2_Advanced_timer/doc/registers.md
new file mode 100644
index 00000000..d52b1b7b
--- /dev/null
+++ b/docs/um/ip/GP_timer2_Advanced_timer/doc/registers.md
@@ -0,0 +1,1088 @@
+## Summary
+
+| Name                                              | Offset   |   Length | Description                                              |
+|:--------------------------------------------------|:---------|---------:|:---------------------------------------------------------|
+| apb_adv_timer.[`T0_CMD`](#t0_cmd)                 | 0x0      |        4 | ADV_TIMER0 command register.                             |
+| apb_adv_timer.[`T0_CONFIG`](#t0_config)           | 0x4      |        4 | ADV_TIMER0 configuration register.                       |
+| apb_adv_timer.[`T0_THRESHOLD`](#t0_threshold)     | 0x8      |        4 | ADV_TIMER0 threshold configuration register.             |
+| apb_adv_timer.[`T0_TH_CHANNEL0`](#t0_th_channel0) | 0xc      |        4 | ADV_TIMER0 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL1`](#t0_th_channel1) | 0x10     |        4 | ADV_TIMER0 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL2`](#t0_th_channel2) | 0x14     |        4 | ADV_TIMER0 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL3`](#t0_th_channel3) | 0x18     |        4 | ADV_TIMER0 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T0_COUNTER`](#t0_counter)         | 0x1c     |        4 | ADV_TIMER0 counter register.                             |
+| apb_adv_timer.[`T1_CMD`](#t1_cmd)                 | 0x20     |        4 | ADV_TIMER1 command register.                             |
+| apb_adv_timer.[`T1_CONFIG`](#t1_config)           | 0x24     |        4 | ADV_TIMER1 configuration register.                       |
+| apb_adv_timer.[`T1_THRESHOLD`](#t1_threshold)     | 0x28     |        4 | ADV_TIMER1 threshold configuration register.             |
+| apb_adv_timer.[`T1_TH_CHANNEL0`](#t1_th_channel0) | 0x2c     |        4 | ADV_TIMER1 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL1`](#t1_th_channel1) | 0x30     |        4 | ADV_TIMER1 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL2`](#t1_th_channel2) | 0x34     |        4 | ADV_TIMER1 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL3`](#t1_th_channel3) | 0x38     |        4 | ADV_TIMER1 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T1_COUNTER`](#t1_counter)         | 0x3c     |        4 | ADV_TIMER1 counter register.                             |
+| apb_adv_timer.[`T2_CMD`](#t2_cmd)                 | 0x40     |        4 | ADV_TIMER2 command register.                             |
+| apb_adv_timer.[`T2_CONFIG`](#t2_config)           | 0x44     |        4 | ADV_TIMER2 configuration register.                       |
+| apb_adv_timer.[`T2_THRESHOLD`](#t2_threshold)     | 0x48     |        4 | ADV_TIMER2 threshold configuration register.             |
+| apb_adv_timer.[`T2_TH_CHANNEL0`](#t2_th_channel0) | 0x4c     |        4 | ADV_TIMER2 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL1`](#t2_th_channel1) | 0x50     |        4 | ADV_TIMER2 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL2`](#t2_th_channel2) | 0x54     |        4 | ADV_TIMER2 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL3`](#t2_th_channel3) | 0x58     |        4 | ADV_TIMER2 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T2_COUNTER`](#t2_counter)         | 0x5c     |        4 | ADV_TIMER2 counter register.                             |
+| apb_adv_timer.[`T3_CMD`](#t3_cmd)                 | 0x60     |        4 | ADV_TIMER3 command register.                             |
+| apb_adv_timer.[`T3_CONFIG`](#t3_config)           | 0x64     |        4 | ADV_TIMER3 configuration register.                       |
+| apb_adv_timer.[`T3_THRESHOLD`](#t3_threshold)     | 0x68     |        4 | ADV_TIMER3 threshold configuration register.             |
+| apb_adv_timer.[`T3_TH_CHANNEL0`](#t3_th_channel0) | 0x6c     |        4 | ADV_TIMER3 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL1`](#t3_th_channel1) | 0x70     |        4 | ADV_TIMER3 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL2`](#t3_th_channel2) | 0x74     |        4 | ADV_TIMER3 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL3`](#t3_th_channel3) | 0x78     |        4 | ADV_TIMER3 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T3_COUNTER`](#t3_counter)         | 0x7c     |        4 | ADV_TIMER3 counter register.                             |
+| apb_adv_timer.[`EVENT_CFG`](#event_cfg)           | 0x80     |        4 | ADV_TIMERS events configuration register.                |
+| apb_adv_timer.[`CG`](#cg)                         | 0x84     |        4 | ADV_TIMERS channels clock gating configuration register. |
+
+## T0_CMD
+ADV_TIMER0 command register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RFU", "bits": 27, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |   wo   |   0x0   | RFU    | ?                                   |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER0 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER0 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER0 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER0 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER0 start command bitfield.  |
+
+## T0_CONFIG
+ADV_TIMER0 configuration register.
+- Offset: `0x4`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t0_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t0_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t0_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t0_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t0_config--insel)         |
+
+### T0_CONFIG . PRESC
+ADV_TIMER0 prescaler value configuration bitfield.
+
+### T0_CONFIG . UPDOWNSEL
+ADV_TIMER0 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.	
+
+### T0_CONFIG . CLKSEL
+ADV_TIMER0 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T0_CONFIG . MODE
+ADV_TIMER0 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T0_CONFIG . INSEL
+ADV_TIMER0 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T0_THRESHOLD
+ADV_TIMER0 threshold configuration register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. |
+
+## T0_TH_CHANNEL0
+ADV_TIMER0 channel 0 threshold configuration register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel0--th)     |
+
+### T0_TH_CHANNEL0 . MODE
+ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL0 . TH
+ADV_TIMER0 channel 0 threshold configuration bitfield.
+
+## T0_TH_CHANNEL1
+ADV_TIMER0 channel 1 threshold configuration register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel1--th)     |
+
+### T0_TH_CHANNEL1 . MODE
+ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL1 . TH
+ADV_TIMER0 channel 1 threshold configuration bitfield.
+
+## T0_TH_CHANNEL2
+ADV_TIMER0 channel 2 threshold configuration register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel2--th)     |
+
+### T0_TH_CHANNEL2 . MODE
+ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL2 . TH
+ADV_TIMER0 channel 2 threshold configuration bitfield.
+
+## T0_TH_CHANNEL3
+ADV_TIMER0 channel 3 threshold configuration register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel3--th)     |
+
+### T0_TH_CHANNEL3 . MODE
+ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL3 . TH
+ADV_TIMER0 channel 3 threshold configuration bitfield.
+
+## T0_COUNTER
+ADV_TIMER0 counter register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER0 counter value. |
+
+## T1_CMD
+ADV_TIMER1 command register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER1 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER1 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER1 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER1 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER1 start command bitfield.  |
+
+## T1_CONFIG
+ADV_TIMER1 configuration register.
+- Offset: `0x24`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t1_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t1_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t1_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t1_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t1_config--insel)         |
+
+### T1_CONFIG . PRESC
+ADV_TIMER1 prescaler value configuration bitfield.
+
+### T1_CONFIG . UPDOWNSEL
+ADV_TIMER1 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T1_CONFIG . CLKSEL
+ADV_TIMER1 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T1_CONFIG . MODE
+ADV_TIMER1 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T1_CONFIG . INSEL
+ADV_TIMER1 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T1_THRESHOLD
+ADV_TIMER1 threshold configuration register.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value. |
+
+## T1_TH_CHANNEL0
+ADV_TIMER1 channel 0 threshold configuration register.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel0--th)     |
+
+### T1_TH_CHANNEL0 . MODE
+ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL0 . TH
+ADV_TIMER1 channel 0 threshold configuration bitfield.
+
+## T1_TH_CHANNEL1
+ADV_TIMER1 channel 1 threshold configuration register.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel1--th)     |
+
+### T1_TH_CHANNEL1 . MODE
+ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL1 . TH
+ADV_TIMER1 channel 1 threshold configuration bitfield.
+
+## T1_TH_CHANNEL2
+ADV_TIMER1 channel 2 threshold configuration register.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel2--th)     |
+
+### T1_TH_CHANNEL2 . MODE
+ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL2 . TH
+ADV_TIMER1 channel 2 threshold configuration bitfield.
+
+## T1_TH_CHANNEL3
+ADV_TIMER1 channel 3 threshold configuration register.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel3--th)     |
+
+### T1_TH_CHANNEL3 . MODE
+ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL3 . TH
+ADV_TIMER1 channel 3 threshold configuration bitfield.
+
+## T1_COUNTER
+ADV_TIMER1 counter register.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER1 counter value. |
+
+## T2_CMD
+ADV_TIMER2 command register.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER2 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER2 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER2 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER2 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER2 start command bitfield.  |
+
+## T2_CONFIG
+ADV_TIMER2 configuration register.
+- Offset: `0x44`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t2_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t2_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t2_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t2_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t2_config--insel)         |
+
+### T2_CONFIG . PRESC
+ADV_TIMER2 prescaler value configuration bitfield.
+
+### T2_CONFIG . UPDOWNSEL
+ADV_TIMER2 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T2_CONFIG . CLKSEL
+ADV_TIMER2 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T2_CONFIG . MODE
+ADV_TIMER2 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T2_CONFIG . INSEL
+ADV_TIMER2 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T2_THRESHOLD
+ADV_TIMER2 threshold configuration register.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value. |
+
+## T2_TH_CHANNEL0
+ADV_TIMER2 channel 0 threshold configuration register.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel0--th)     |
+
+### T2_TH_CHANNEL0 . MODE
+ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL0 . TH
+ADV_TIMER2 channel 0 threshold configuration bitfield.
+
+## T2_TH_CHANNEL1
+ADV_TIMER2 channel 1 threshold configuration register.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel1--th)     |
+
+### T2_TH_CHANNEL1 . MODE
+ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL1 . TH
+ADV_TIMER2 channel 1 threshold configuration bitfield.
+
+## T2_TH_CHANNEL2
+ADV_TIMER2 channel 2 threshold configuration register.
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel2--th)     |
+
+### T2_TH_CHANNEL2 . MODE
+ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL2 . TH
+ADV_TIMER2 channel 2 threshold configuration bitfield.
+
+## T2_TH_CHANNEL3
+ADV_TIMER2 channel 3 threshold configuration register.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel3--th)     |
+
+### T2_TH_CHANNEL3 . MODE
+ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL3 . TH
+ADV_TIMER2 channel 3 threshold configuration bitfield.
+
+## T2_COUNTER
+ADV_TIMER2 counter register.
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER2 counter value. |
+
+## T3_CMD
+ADV_TIMER3 command register.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER3 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER3 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER3 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER3 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER3 start command bitfield.  |
+
+## T3_CONFIG
+ADV_TIMER3 configuration register.
+- Offset: `0x64`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t3_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t3_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t3_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t3_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t3_config--insel)         |
+
+### T3_CONFIG . PRESC
+ADV_TIMER3 prescaler value configuration bitfield.
+
+### T3_CONFIG . UPDOWNSEL
+ADV_TIMER3 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T3_CONFIG . CLKSEL
+ADV_TIMER3 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T3_CONFIG . MODE
+ADV_TIMER3 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T3_CONFIG . INSEL
+ADV_TIMER3 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T3_THRESHOLD
+ADV_TIMER3 threshold configuration register.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value. |
+
+## T3_TH_CHANNEL0
+ADV_TIMER3 channel 0 threshold configuration register.
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel0--th)     |
+
+### T3_TH_CHANNEL0 . MODE
+ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL0 . TH
+ADV_TIMER3 channel 0 threshold configuration bitfield.
+
+## T3_TH_CHANNEL1
+ADV_TIMER3 channel 1 threshold configuration register.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel1--th)     |
+
+### T3_TH_CHANNEL1 . MODE
+ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL1 . TH
+ADV_TIMER3 channel 1 threshold configuration bitfield.
+
+## T3_TH_CHANNEL2
+ADV_TIMER3 channel 2 threshold configuration register.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel2--th)     |
+
+### T3_TH_CHANNEL2 . MODE
+ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL2 . TH
+ADV_TIMER3 channel 2 threshold configuration bitfield.
+
+## T3_TH_CHANNEL3
+ADV_TIMER3 channel 3 threshold configuration register.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel3--th)     |
+
+### T3_TH_CHANNEL3 . MODE
+ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL3 . TH
+ADV_TIMER3 channel 3 threshold configuration bitfield.
+
+## T3_COUNTER
+ADV_TIMER3 counter register.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER3 counter value. |
+
+## EVENT_CFG
+ADV_TIMERS events configuration register.
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SEL0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL2", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL3", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     |
+|:------:|:------:|:-------:|:-------------------------|
+| 31:20  |        |         | Reserved                 |
+| 19:16  |   rw   |   0x0   | [ENA](#event_cfg--ena)   |
+| 15:12  |   rw   |   0x0   | [SEL3](#event_cfg--sel3) |
+|  11:8  |   rw   |   0x0   | [SEL2](#event_cfg--sel2) |
+|  7:4   |   rw   |   0x0   | [SEL1](#event_cfg--sel1) |
+|  3:0   |   rw   |   0x0   | [SEL0](#event_cfg--sel0) |
+
+### EVENT_CFG . ENA
+ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation.
+
+### EVENT_CFG . SEL3
+ADV_TIMER output event 3 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL2
+ADV_TIMER output event 2 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL1
+ADV_TIMER output event 1 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL0
+ADV_TIMER output event 0 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+## CG
+ADV_TIMERS channels clock gating configuration register.
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                      |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------|
+|  31:4  |        |         |        | Reserved                                                                                                         |
+|  3:0   |   rw   |   0x0   | ENA    | ADV_TIMER clock gating configuration bitfield. - ENA[i]=0: clock gate ADV_TIMERi. - ENA[i]=1: enable ADV_TIMERi. |
+
diff --git a/docs/um/ip/L2_ECC_Config/data/ecc_sram_wrapper.hjson b/docs/um/ip/L2_ECC_Config/data/ecc_sram_wrapper.hjson
new file mode 100644
index 00000000..412bda5d
--- /dev/null
+++ b/docs/um/ip/L2_ECC_Config/data/ecc_sram_wrapper.hjson
@@ -0,0 +1,86 @@
+{
+  name: "ECC_manager",
+  clock_primary: "clk_i",
+  reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+
+  registers: [
+    { name: "mismatch_count",
+      desc: "Correctable mismatches caught by ecc on access",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on access"
+        }
+      ]
+    },
+    { name: "scrub_interval",
+      desc: "Interval between scrubs",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0"
+          name: "scrub_interval"
+          desc: "Interval between scrubs"
+        }
+      ]
+    },
+    { name: "scrub_fix_count",
+      desc: "Correctable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "scrub_uncorrectable_count",
+      desc: "Uncorrectable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "uncorrectable_mismatches",
+          desc: "Uncorrectable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "write_mask_data_n",
+      desc: "Testing: Inverted write mask for data bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "write_mask_data_n",
+          desc: "Testing: Inverted write mask for data bits"
+        }
+      ]
+    },
+    { name: "write_mask_ecc_n",
+      desc: "Testing: Inverted write mask for ECC bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "6:0",
+          name: "write_mask_ecc_n",
+          desc: "Testing: Inverted write mask for ECC bits"
+        }
+      ]
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/L2_ECC_Config/data/ecc_sram_wrapper_doc.hjson b/docs/um/ip/L2_ECC_Config/data/ecc_sram_wrapper_doc.hjson
new file mode 100644
index 00000000..7a2db8a3
--- /dev/null
+++ b/docs/um/ip/L2_ECC_Config/data/ecc_sram_wrapper_doc.hjson
@@ -0,0 +1,94 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Author: Michael Rogenmoser <michaero@iis.ee.ethz.ch>
+
+{
+  name: "ECC_manager",
+  cip_id: "36",
+  version: "0.0.0", // null, commit 5616a36
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "mismatch_count",
+      desc: "Correctable mismatches caught by ecc on access",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on access"
+        }
+      ]
+    },
+    { name: "scrub_interval",
+      desc: "Interval between scrubs",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0"
+          name: "scrub_interval"
+          desc: "Interval between scrubs"
+        }
+      ]
+    },
+    { name: "scrub_fix_count",
+      desc: "Correctable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "scrub_uncorrectable_count",
+      desc: "Uncorrectable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "uncorrectable_mismatches",
+          desc: "Uncorrectable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "write_mask_data_n",
+      desc: "Testing: Inverted write mask for data bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "write_mask_data_n",
+          desc: "Testing: Inverted write mask for data bits"
+        }
+      ]
+    },
+    { name: "write_mask_ecc_n",
+      desc: "Testing: Inverted write mask for ECC bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "6:0",
+          name: "write_mask_ecc_n",
+          desc: "Testing: Inverted write mask for ECC bits"
+        }
+      ]
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/L2_ECC_Config/doc/registers.md b/docs/um/ip/L2_ECC_Config/doc/registers.md
new file mode 100644
index 00000000..6a6d27df
--- /dev/null
+++ b/docs/um/ip/L2_ECC_Config/doc/registers.md
@@ -0,0 +1,108 @@
+## Summary
+
+| Name                                                                  | Offset   |   Length | Description                                     |
+|:----------------------------------------------------------------------|:---------|---------:|:------------------------------------------------|
+| ECC_manager.[`mismatch_count`](#mismatch_count)                       | 0x0      |        4 | Correctable mismatches caught by ecc on access  |
+| ECC_manager.[`scrub_interval`](#scrub_interval)                       | 0x4      |        4 | Interval between scrubs                         |
+| ECC_manager.[`scrub_fix_count`](#scrub_fix_count)                     | 0x8      |        4 | Correctable mismatches caught by ecc on scrub   |
+| ECC_manager.[`scrub_uncorrectable_count`](#scrub_uncorrectable_count) | 0xc      |        4 | Uncorrectable mismatches caught by ecc on scrub |
+| ECC_manager.[`write_mask_data_n`](#write_mask_data_n)                 | 0x10     |        4 | Testing: Inverted write mask for data bits      |
+| ECC_manager.[`write_mask_ecc_n`](#write_mask_ecc_n)                   | 0x14     |        4 | Testing: Inverted write mask for ECC bits       |
+
+## mismatch_count
+Correctable mismatches caught by ecc on access
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                    |
+|:------:|:------:|:-------:|:-----------------------|:-----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on access |
+
+## scrub_interval
+Interval between scrubs
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "scrub_interval", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description             |
+|:------:|:------:|:-------:|:---------------|:------------------------|
+|  31:0  |   rw   |   0x0   | scrub_interval | Interval between scrubs |
+
+## scrub_fix_count
+Correctable mismatches caught by ecc on scrub
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                   |
+|:------:|:------:|:-------:|:-----------------------|:----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on scrub |
+
+## scrub_uncorrectable_count
+Uncorrectable mismatches caught by ecc on scrub
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "uncorrectable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description                                     |
+|:------:|:------:|:-------:|:-------------------------|:------------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | uncorrectable_mismatches | Uncorrectable mismatches caught by ecc on scrub |
+
+## write_mask_data_n
+Testing: Inverted write mask for data bits
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_data_n", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                                |
+|:------:|:------:|:-------:|:------------------|:-------------------------------------------|
+|  31:0  |   rw   |   0x0   | write_mask_data_n | Testing: Inverted write mask for data bits |
+
+## write_mask_ecc_n
+Testing: Inverted write mask for ECC bits
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_ecc_n", "bits": 7, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                               |
+|:------:|:------:|:-------:|:-----------------|:------------------------------------------|
+|  31:7  |        |         |                  | Reserved                                  |
+|  6:0   |   rw   |   0x0   | write_mask_ecc_n | Testing: Inverted write mask for ECC bits |
+
diff --git a/docs/um/ip/axi_dma_config/data/idma_desc64_frontend.hjson b/docs/um/ip/axi_dma_config/data/idma_desc64_frontend.hjson
new file mode 100644
index 00000000..020cb557
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_desc64_frontend.hjson
@@ -0,0 +1,67 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+// Axel Vanoni <axvanoni@student.ethz.ch>
+
+{
+	name: idma_desc64
+	regwidth: 64
+	clock_primary: clk_i
+	bus_interfaces: [
+		{
+			protocol: reg_iface
+			direction: device
+		}
+	]
+	registers: [
+		{
+			name: desc_addr
+			desc:
+			'''
+			This register specifies the bus address at which the first transfer
+			descriptor can be found. A write to this register starts the transfer.
+			'''
+			swaccess: wo
+			hwaccess: hro
+			hwqe: true
+			resval: 0xFFFFFFFFFFFFFFFF
+			fields: [
+				{
+					bits: "63:0"
+				}
+			]
+		}
+		{
+			name: status
+			desc:
+			'''
+			This register contains status information for the DMA.
+			'''
+			swaccess: ro
+			hwaccess: hwo
+			resval: 0
+			fields: [
+				{
+					name: "busy"
+					desc:
+					'''
+					The DMA is busy
+					'''
+					bits: "0"
+				}
+				{
+					name: "fifo_full"
+					desc:
+					'''
+					If this bit is set, the buffers of the DMA are full. Any further submissions via the
+					desc_addr register may overwrite previously submitted jobs or get lost.
+					'''
+					bits: "1"
+				}
+			]
+		}
+	]
+}
diff --git a/docs/um/ip/axi_dma_config/data/idma_desc64_frontend_doc.hjson b/docs/um/ip/axi_dma_config/data/idma_desc64_frontend_doc.hjson
new file mode 100644
index 00000000..59c619e4
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_desc64_frontend_doc.hjson
@@ -0,0 +1,71 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+// Axel Vanoni <axvanoni@student.ethz.ch>
+
+{
+	name: idma_desc64
+	regwidth: 64
+	cip_id: "36",
+        version: "0.5.1",
+        clocking: [
+         {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+        ],
+	bus_interfaces: [
+		{
+			protocol: tlul
+			direction: device
+		}
+	]
+	registers: [
+		{
+			name: desc_addr
+			desc:
+			'''
+			This register specifies the bus address at which the first transfer
+			descriptor can be found. A write to this register starts the transfer.
+			'''
+			swaccess: wo
+			hwaccess: hro
+			hwqe: true
+			resval: 0xFFFFFFFFFFFFFFFF
+			fields: [
+				{
+					bits: "63:0"
+				}
+			]
+		}
+		{
+			name: status
+			desc:
+			'''
+			This register contains status information for the DMA.
+			'''
+			swaccess: ro
+			hwaccess: hwo
+			resval: 0
+			fields: [
+				{
+					name: "busy"
+					desc:
+					'''
+					The DMA is busy
+					'''
+					bits: "0"
+				}
+				{
+					name: "fifo_full"
+					desc:
+					'''
+					If this bit is set, the buffers of the DMA are full. Any further submissions via the
+					desc_addr register may overwrite previously submitted jobs or get lost.
+					'''
+					bits: "1"
+				}
+			]
+		}
+	]
+}
diff --git a/docs/um/ip/axi_dma_config/data/idma_reg32_2d_frontend.hjson b/docs/um/ip/axi_dma_config/data/idma_reg32_2d_frontend.hjson
new file mode 100644
index 00000000..63e8ff3a
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_reg32_2d_frontend.hjson
@@ -0,0 +1,147 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+{
+  name: "idma_reg32_2d_frontend",
+  clock_primary: "clk_i",
+  reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "src_addr",
+      desc: "Source Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "src_addr",
+          desc: "Source Address"
+        }
+      ]
+    },
+    { name: "dst_addr",
+      desc: "Destination Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "dst_addr",
+          desc: "Destination Address"
+        }
+      ]
+    },
+    { name: "num_bytes",
+      desc: "Number of bytes",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "num_bytes",
+          desc: "Number of bytes"
+        }
+      ]
+    },
+    { name: "conf",
+      desc: "Configuration Register for DMA settings",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "decouple",
+          desc: "Decouple enable"
+        },
+        { bits: "1",
+          name: "deburst",
+          desc: "Deburst enable"
+        },
+        { bits: "2",
+          name: "serialize",
+          desc: "Serialize enable"
+        },
+        { bits: "3",
+          name: "twod",
+          desc: "2D transfer"
+        }
+      ]
+    },
+    { name: "stride_src",
+      desc: "Source Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "stride_src",
+          desc: "Source Stride"
+        }
+      ]
+    },
+    { name: "stride_dst"
+      desc: "Destination Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "stride_dst",
+          desc: "Destination Stride"
+        }
+      ]
+    },
+    { name: "num_repetitions"
+      desc: "Number of 2D repetitions",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "num_repetitions",
+          desc: "Number of 2D repetitions",
+          resval: "1"
+        }
+      ]
+    },
+    { name: "status",
+      desc: "DMA Status",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "15:0",
+          name: "busy",
+          desc: "DMA busy"
+        }
+      ]
+    },
+    { name: "next_id",
+      desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "31:0",
+          name: "next_id",
+          desc: "Next ID, launches transfer, returns 0 if transfer not set up properly."
+        }
+      ]
+    },
+    { name: "done",
+      desc: "Get ID of finished transactions.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "31:0",
+          name: "done",
+          desc: "Get ID of finished transactions."
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_dma_config/data/idma_reg32_2d_frontend_doc.hjson b/docs/um/ip/axi_dma_config/data/idma_reg32_2d_frontend_doc.hjson
new file mode 100644
index 00000000..d3a0bb2b
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_reg32_2d_frontend_doc.hjson
@@ -0,0 +1,150 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+{
+  name: "idma_reg32_2d_frontend",
+  cip_id: "36",
+  version: "0.5.1",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "src_addr",
+      desc: "Source Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "src_addr",
+          desc: "Source Address"
+        }
+      ]
+    },
+    { name: "dst_addr",
+      desc: "Destination Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "dst_addr",
+          desc: "Destination Address"
+        }
+      ]
+    },
+    { name: "num_bytes",
+      desc: "Number of bytes",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "num_bytes",
+          desc: "Number of bytes"
+        }
+      ]
+    },
+    { name: "conf",
+      desc: "Configuration Register for DMA settings",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "decouple",
+          desc: "Decouple enable"
+        },
+        { bits: "1",
+          name: "deburst",
+          desc: "Deburst enable"
+        },
+        { bits: "2",
+          name: "serialize",
+          desc: "Serialize enable"
+        },
+        { bits: "3",
+          name: "twod",
+          desc: "2D transfer"
+        }
+      ]
+    },
+    { name: "stride_src",
+      desc: "Source Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "stride_src",
+          desc: "Source Stride"
+        }
+      ]
+    },
+    { name: "stride_dst"
+      desc: "Destination Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "stride_dst",
+          desc: "Destination Stride"
+        }
+      ]
+    },
+    { name: "num_repetitions"
+      desc: "Number of 2D repetitions",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "num_repetitions",
+          desc: "Number of 2D repetitions",
+          resval: "1"
+        }
+      ]
+    },
+    { name: "status",
+      desc: "DMA Status",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "15:0",
+          name: "busy",
+          desc: "DMA busy"
+        }
+      ]
+    },
+    { name: "next_id",
+      desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "31:0",
+          name: "next_id",
+          desc: "Next ID, launches transfer, returns 0 if transfer not set up properly."
+        }
+      ]
+    },
+    { name: "done",
+      desc: "Get ID of finished transactions.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "31:0",
+          name: "done",
+          desc: "Get ID of finished transactions."
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_dma_config/data/idma_reg64_2d_frontend.hjson b/docs/um/ip/axi_dma_config/data/idma_reg64_2d_frontend.hjson
new file mode 100644
index 00000000..89b602d8
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_reg64_2d_frontend.hjson
@@ -0,0 +1,142 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+{
+  name: "idma_reg64_2d_frontend",
+  clock_primary: "clk_i",
+	reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+  regwidth: "64",
+  registers: [
+    { name: "src_addr",
+      desc: "Source Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "src_addr",
+          desc: "Source Address"
+        }
+      ]
+    },
+    { name: "dst_addr",
+      desc: "Destination Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "dst_addr",
+          desc: "Destination Address"
+        }
+      ]
+    },
+    { name: "num_bytes",
+      desc: "Number of bytes",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "num_bytes",
+          desc: "Number of bytes"
+        }
+      ]
+    },
+    { name: "conf",
+      desc: "Configuration Register for DMA settings",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "decouple",
+          desc: "Decouple enable"
+        },
+        { bits: "1",
+          name: "deburst",
+          desc: "Deburst enable"
+        },
+        { bits: "2",
+          name: "serialize",
+          desc: "Serialize enable"
+        }
+      ]
+    },
+    { name: "status",
+      desc: "DMA Status",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "busy",
+          desc: "DMA busy"
+        }
+      ]
+    },
+    { name: "next_id",
+      desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "next_id",
+          desc: "Next ID, launches transfer, returns 0 if transfer not set up properly."
+        }
+      ]
+    },
+    { name: "done",
+      desc: "Get ID of finished transactions.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "done",
+          desc: "Get ID of finished transactions."
+        }
+      ]
+    },
+    { name: "stride_src",
+      desc: "Source Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "stride_src",
+          desc: "Source Stride"
+        }
+      ]
+    },
+    { name: "stride_dst"
+      desc: "Destination Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "stride_dst",
+          desc: "Destination Stride"
+        }
+      ]
+    },
+    { name: "num_repetitions"
+      desc: "Number of 2D repetitions",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "num_repetitions",
+          desc: "Number of 2D repetitions",
+          resval: "0"
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_dma_config/data/idma_reg64_2d_frontend_doc.hjson b/docs/um/ip/axi_dma_config/data/idma_reg64_2d_frontend_doc.hjson
new file mode 100644
index 00000000..38eaf6b3
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_reg64_2d_frontend_doc.hjson
@@ -0,0 +1,145 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+{
+  name: "idma_reg64_2d_frontend",
+  cip_id: "36",
+  version: "0.5.1",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul",
+      direction: "device"
+    }
+  ],
+  regwidth: "64",
+  registers: [
+    { name: "src_addr",
+      desc: "Source Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "src_addr",
+          desc: "Source Address"
+        }
+      ]
+    },
+    { name: "dst_addr",
+      desc: "Destination Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "dst_addr",
+          desc: "Destination Address"
+        }
+      ]
+    },
+    { name: "num_bytes",
+      desc: "Number of bytes",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "num_bytes",
+          desc: "Number of bytes"
+        }
+      ]
+    },
+    { name: "conf",
+      desc: "Configuration Register for DMA settings",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "decouple",
+          desc: "Decouple enable"
+        },
+        { bits: "1",
+          name: "deburst",
+          desc: "Deburst enable"
+        },
+        { bits: "2",
+          name: "serialize",
+          desc: "Serialize enable"
+        }
+      ]
+    },
+    { name: "status",
+      desc: "DMA Status",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "busy",
+          desc: "DMA busy"
+        }
+      ]
+    },
+    { name: "next_id",
+      desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "next_id",
+          desc: "Next ID, launches transfer, returns 0 if transfer not set up properly."
+        }
+      ]
+    },
+    { name: "done",
+      desc: "Get ID of finished transactions.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "done",
+          desc: "Get ID of finished transactions."
+        }
+      ]
+    },
+    { name: "stride_src",
+      desc: "Source Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "stride_src",
+          desc: "Source Stride"
+        }
+      ]
+    },
+    { name: "stride_dst"
+      desc: "Destination Stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "stride_dst",
+          desc: "Destination Stride"
+        }
+      ]
+    },
+    { name: "num_repetitions"
+      desc: "Number of 2D repetitions",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "num_repetitions",
+          desc: "Number of 2D repetitions",
+          resval: "0"
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_dma_config/data/idma_reg64_frontend.hjson b/docs/um/ip/axi_dma_config/data/idma_reg64_frontend.hjson
new file mode 100644
index 00000000..8516a501
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_reg64_frontend.hjson
@@ -0,0 +1,108 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+{
+  name: "idma_reg64_frontend",
+  clock_primary: "clk_i",
+	reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+  regwidth: "64",
+  registers: [
+    { name: "src_addr",
+      desc: "Source Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "src_addr",
+          desc: "Source Address"
+        }
+      ]
+    },
+    { name: "dst_addr",
+      desc: "Destination Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "dst_addr",
+          desc: "Destination Address"
+        }
+      ]
+    },
+    { name: "num_bytes",
+      desc: "Number of bytes",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "num_bytes",
+          desc: "Number of bytes"
+        }
+      ]
+    },
+    { name: "conf",
+      desc: "Configuration Register for DMA settings",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "decouple",
+          desc: "Decouple enable"
+        },
+        { bits: "1",
+          name: "deburst",
+          desc: "Deburst enable"
+        },
+        { bits: "2",
+          name: "serialize",
+          desc: "Serialize enable"
+        }
+      ]
+    },
+    { name: "status",
+      desc: "DMA Status",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "busy",
+          desc: "DMA busy"
+        }
+      ]
+    },
+    { name: "next_id",
+      desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "next_id",
+          desc: "Next ID, launches transfer, returns 0 if transfer not set up properly."
+        }
+      ]
+    },
+    { name: "done",
+      desc: "Get ID of finished transactions.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "done",
+          desc: "Get ID of finished transactions."
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_dma_config/data/idma_reg64_frontend_doc.hjson b/docs/um/ip/axi_dma_config/data/idma_reg64_frontend_doc.hjson
new file mode 100644
index 00000000..ca0903d1
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/data/idma_reg64_frontend_doc.hjson
@@ -0,0 +1,111 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51
+
+{
+  name: "idma_reg64_frontend",
+  cip_id: "36",
+  version: "0.5.1",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul",
+      direction: "device"
+    }
+  ],
+  regwidth: "64",
+  registers: [
+    { name: "src_addr",
+      desc: "Source Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "src_addr",
+          desc: "Source Address"
+        }
+      ]
+    },
+    { name: "dst_addr",
+      desc: "Destination Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "dst_addr",
+          desc: "Destination Address"
+        }
+      ]
+    },
+    { name: "num_bytes",
+      desc: "Number of bytes",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "63:0",
+          name: "num_bytes",
+          desc: "Number of bytes"
+        }
+      ]
+    },
+    { name: "conf",
+      desc: "Configuration Register for DMA settings",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "decouple",
+          desc: "Decouple enable"
+        },
+        { bits: "1",
+          name: "deburst",
+          desc: "Deburst enable"
+        },
+        { bits: "2",
+          name: "serialize",
+          desc: "Serialize enable"
+        }
+      ]
+    },
+    { name: "status",
+      desc: "DMA Status",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "0",
+          name: "busy",
+          desc: "DMA busy"
+        }
+      ]
+    },
+    { name: "next_id",
+      desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "next_id",
+          desc: "Next ID, launches transfer, returns 0 if transfer not set up properly."
+        }
+      ]
+    },
+    { name: "done",
+      desc: "Get ID of finished transactions.",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "63:0",
+          name: "done",
+          desc: "Get ID of finished transactions."
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_dma_config/doc/idma_desc64_frontend_doc.md b/docs/um/ip/axi_dma_config/doc/idma_desc64_frontend_doc.md
new file mode 100644
index 00000000..50798b23
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/doc/idma_desc64_frontend_doc.md
@@ -0,0 +1,42 @@
+## Summary
+
+| Name                                  | Offset   |   Length | Description                                                         |
+|:--------------------------------------|:---------|---------:|:--------------------------------------------------------------------|
+| idma_desc64.[`desc_addr`](#desc_addr) | 0x0      |        8 | This register specifies the bus address at which the first transfer |
+| idma_desc64.[`status`](#status)       | 0x8      |        8 | This register contains status information for the DMA.              |
+
+## desc_addr
+This register specifies the bus address at which the first transfer
+descriptor can be found. A write to this register starts the transfer.
+- Offset: `0x0`
+- Reset default: `0xffffffffffffffff`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "desc_addr", "bits": 64, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |       Reset        | Name      | Description   |
+|:------:|:------:|:------------------:|:----------|:--------------|
+|  63:0  |   wo   | 0xffffffffffffffff | desc_addr |               |
+
+## status
+This register contains status information for the DMA.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "fifo_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 62}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  63:2  |        |         |           | Reserved                                                                                                                                                     |
+|   1    |   ro   |   0x0   | fifo_full | If this bit is set, the buffers of the DMA are full. Any further submissions via the desc_addr register may overwrite previously submitted jobs or get lost. |
+|   0    |   ro   |   0x0   | busy      | The DMA is busy                                                                                                                                              |
+
diff --git a/docs/um/ip/axi_dma_config/doc/idma_reg32_2d_frontend_doc.md b/docs/um/ip/axi_dma_config/doc/idma_reg32_2d_frontend_doc.md
new file mode 100644
index 00000000..d1e8a969
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/doc/idma_reg32_2d_frontend_doc.md
@@ -0,0 +1,180 @@
+## Summary
+
+| Name                                                         | Offset   |   Length | Description                                                            |
+|:-------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg32_2d_frontend.[`src_addr`](#src_addr)               | 0x0      |        4 | Source Address                                                         |
+| idma_reg32_2d_frontend.[`dst_addr`](#dst_addr)               | 0x4      |        4 | Destination Address                                                    |
+| idma_reg32_2d_frontend.[`num_bytes`](#num_bytes)             | 0x8      |        4 | Number of bytes                                                        |
+| idma_reg32_2d_frontend.[`conf`](#conf)                       | 0xc      |        4 | Configuration Register for DMA settings                                |
+| idma_reg32_2d_frontend.[`stride_src`](#stride_src)           | 0x10     |        4 | Source Stride                                                          |
+| idma_reg32_2d_frontend.[`stride_dst`](#stride_dst)           | 0x14     |        4 | Destination Stride                                                     |
+| idma_reg32_2d_frontend.[`num_repetitions`](#num_repetitions) | 0x18     |        4 | Number of 2D repetitions                                               |
+| idma_reg32_2d_frontend.[`status`](#status)                   | 0x1c     |        4 | DMA Status                                                             |
+| idma_reg32_2d_frontend.[`next_id`](#next_id)                 | 0x20     |        4 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg32_2d_frontend.[`done`](#done)                       | 0x24     |        4 | Get ID of finished transactions.                                       |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  31:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  31:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  31:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "twod", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  31:4  |        |         |           | Reserved         |
+|   3    |   rw   |   0x0   | twod      | 2D transfer      |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## stride_src
+Source Stride
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_src", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   rw   |   0x0   | stride_src | Source Stride |
+
+## stride_dst
+Destination Stride
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_dst", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description        |
+|:------:|:------:|:-------:|:-----------|:-------------------|
+|  31:0  |   rw   |   0x0   | stride_dst | Destination Stride |
+
+## num_repetitions
+Number of 2D repetitions
+- Offset: `0x18`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_repetitions", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description              |
+|:------:|:------:|:-------:|:----------------|:-------------------------|
+|  31:0  |   rw   |   0x1   | num_repetitions | Number of 2D repetitions |
+
+## status
+DMA Status
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+| 31:16  |        |         |        | Reserved      |
+|  15:0  |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  31:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
diff --git a/docs/um/ip/axi_dma_config/doc/idma_reg64_2d_frontend_doc.md b/docs/um/ip/axi_dma_config/doc/idma_reg64_2d_frontend_doc.md
new file mode 100644
index 00000000..b9a35267
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/doc/idma_reg64_2d_frontend_doc.md
@@ -0,0 +1,179 @@
+## Summary
+
+| Name                                                         | Offset   |   Length | Description                                                            |
+|:-------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg64_2d_frontend.[`src_addr`](#src_addr)               | 0x0      |        8 | Source Address                                                         |
+| idma_reg64_2d_frontend.[`dst_addr`](#dst_addr)               | 0x8      |        8 | Destination Address                                                    |
+| idma_reg64_2d_frontend.[`num_bytes`](#num_bytes)             | 0x10     |        8 | Number of bytes                                                        |
+| idma_reg64_2d_frontend.[`conf`](#conf)                       | 0x18     |        8 | Configuration Register for DMA settings                                |
+| idma_reg64_2d_frontend.[`status`](#status)                   | 0x20     |        8 | DMA Status                                                             |
+| idma_reg64_2d_frontend.[`next_id`](#next_id)                 | 0x28     |        8 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg64_2d_frontend.[`done`](#done)                       | 0x30     |        8 | Get ID of finished transactions.                                       |
+| idma_reg64_2d_frontend.[`stride_src`](#stride_src)           | 0x38     |        8 | Source Stride                                                          |
+| idma_reg64_2d_frontend.[`stride_dst`](#stride_dst)           | 0x40     |        8 | Destination Stride                                                     |
+| idma_reg64_2d_frontend.[`num_repetitions`](#num_repetitions) | 0x48     |        8 | Number of 2D repetitions                                               |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  63:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  63:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  63:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 61}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  63:3  |        |         |           | Reserved         |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## status
+DMA Status
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  63:1  |        |         |        | Reserved      |
+|   0    |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  63:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  63:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
+## stride_src
+Source Stride
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_src", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  63:0  |   rw   |   0x0   | stride_src | Source Stride |
+
+## stride_dst
+Destination Stride
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stride_dst", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description        |
+|:------:|:------:|:-------:|:-----------|:-------------------|
+|  63:0  |   rw   |   0x0   | stride_dst | Destination Stride |
+
+## num_repetitions
+Number of 2D repetitions
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_repetitions", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description              |
+|:------:|:------:|:-------:|:----------------|:-------------------------|
+|  63:0  |   rw   |   0x0   | num_repetitions | Number of 2D repetitions |
+
diff --git a/docs/um/ip/axi_dma_config/doc/idma_reg64_frontend_doc.md b/docs/um/ip/axi_dma_config/doc/idma_reg64_frontend_doc.md
new file mode 100644
index 00000000..946466b5
--- /dev/null
+++ b/docs/um/ip/axi_dma_config/doc/idma_reg64_frontend_doc.md
@@ -0,0 +1,128 @@
+## Summary
+
+| Name                                          | Offset   |   Length | Description                                                            |
+|:----------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| idma_reg64_frontend.[`src_addr`](#src_addr)   | 0x0      |        8 | Source Address                                                         |
+| idma_reg64_frontend.[`dst_addr`](#dst_addr)   | 0x8      |        8 | Destination Address                                                    |
+| idma_reg64_frontend.[`num_bytes`](#num_bytes) | 0x10     |        8 | Number of bytes                                                        |
+| idma_reg64_frontend.[`conf`](#conf)           | 0x18     |        8 | Configuration Register for DMA settings                                |
+| idma_reg64_frontend.[`status`](#status)       | 0x20     |        8 | DMA Status                                                             |
+| idma_reg64_frontend.[`next_id`](#next_id)     | 0x28     |        8 | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+| idma_reg64_frontend.[`done`](#done)           | 0x30     |        8 | Get ID of finished transactions.                                       |
+
+## src_addr
+Source Address
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "src_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description    |
+|:------:|:------:|:-------:|:---------|:---------------|
+|  63:0  |   rw   |   0x0   | src_addr | Source Address |
+
+## dst_addr
+Destination Address
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dst_addr", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description         |
+|:------:|:------:|:-------:|:---------|:--------------------|
+|  63:0  |   rw   |   0x0   | dst_addr | Destination Address |
+
+## num_bytes
+Number of bytes
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_bytes", "bits": 64, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description     |
+|:------:|:------:|:-------:|:----------|:----------------|
+|  63:0  |   rw   |   0x0   | num_bytes | Number of bytes |
+
+## conf
+Configuration Register for DMA settings
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "decouple", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "deburst", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "serialize", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 61}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description      |
+|:------:|:------:|:-------:|:----------|:-----------------|
+|  63:3  |        |         |           | Reserved         |
+|   2    |   rw   |   0x0   | serialize | Serialize enable |
+|   1    |   rw   |   0x0   | deburst   | Deburst enable   |
+|   0    |   rw   |   0x0   | decouple  | Decouple enable  |
+
+## status
+DMA Status
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  63:1  |        |         |        | Reserved      |
+|   0    |   ro   |    x    | busy   | DMA busy      |
+
+## next_id
+Next ID, launches transfer, returns 0 if transfer not set up properly.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "next_id", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  63:0  |   ro   |    x    | next_id | Next ID, launches transfer, returns 0 if transfer not set up properly. |
+
+## done
+Get ID of finished transactions.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 64, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  63:0  |   ro   |    x    | done   | Get ID of finished transactions. |
+
diff --git a/docs/um/ip/axi_llc/data/axi_llc_regs.hjson b/docs/um/ip/axi_llc/data/axi_llc_regs.hjson
new file mode 100644
index 00000000..7ba04860
--- /dev/null
+++ b/docs/um/ip/axi_llc/data/axi_llc_regs.hjson
@@ -0,0 +1,166 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Authors: 
+// Nicole Narr <narrn@ethz.ch>
+// Christopher Reinwardt <creinwar@ethz.ch>
+
+
+
+{
+  name: "axi_llc",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: 32,
+  registers: [
+
+    { name: "CFG_SPM_LOW",
+      desc: "SPM Configuration (lower 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", resval: 0, name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "CFG_SPM_HIGH",
+      desc: "SPM Configuration (upper 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "CFG_FLUSH_LOW",
+      desc: "Flush Configuration (lower 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "CFG_FLUSH_HIGH",
+      desc: "Flush Configuration (upper 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "COMMIT_CFG",
+      desc: "Commit the configuration",
+      swaccess: "rw1s",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "0", name: "commit", desc: "commit configuration"}
+      ]
+    },
+    {skipto: "0x18"}
+    { name: "FLUSHED_LOW",
+      desc: "Flushed Flag (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "FLUSHED_HIGH",
+      desc: "Flushed Flag (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "BIST_OUT_LOW",
+      desc: "Tag Storage BIST Result (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "BIST_OUT_HIGH",
+      desc: "Tag Storage BIST Result (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "SET_ASSO_LOW",
+      desc: "Instantiated Set-Associativity (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "SET_ASSO_HIGH",
+      desc: "Instantiated Set-Associativity (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "NUM_LINES_LOW",
+      desc: "Instantiated Number of Cache-Lines (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "NUM_LINES_HIGH",
+      desc: "Instantiated Number of Cache-Lines (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "NUM_BLOCKS_LOW",
+      desc: "Instantiated Number of Blocks (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "NUM_BLOCKS_HIGH",
+      desc: "Instantiated Number of Blocks (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "VERSION_LOW",
+      desc: "AXI LLC Version (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "VERSION_HIGH",
+      desc: "AXI LLC Version (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "BIST_STATUS",
+      desc: "Status register of the BIST",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "0:0", name: "done", desc: "BIST successfully completed"}
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_llc/data/axi_llc_regs_doc.hjson b/docs/um/ip/axi_llc/data/axi_llc_regs_doc.hjson
new file mode 100644
index 00000000..0cb0bb0f
--- /dev/null
+++ b/docs/um/ip/axi_llc/data/axi_llc_regs_doc.hjson
@@ -0,0 +1,168 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Authors: 
+// Nicole Narr <narrn@ethz.ch>
+// Christopher Reinwardt <creinwar@ethz.ch>
+
+{
+  name: "axi_llc",
+  cip_id: "36",
+  version: "0.2.2",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: 32,
+  registers: [
+    { name: "CFG_SPM_LOW",
+      desc: "SPM Configuration (lower 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", resval: "0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "CFG_SPM_HIGH",
+      desc: "SPM Configuration (upper 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "CFG_FLUSH_LOW",
+      desc: "Flush Configuration (lower 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "CFG_FLUSH_HIGH",
+      desc: "Flush Configuration (upper 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "COMMIT_CFG",
+      desc: "Commit the configuration",
+      swaccess: "rw1s",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "0", name: "commit", desc: "commit configuration"}
+      ]
+    },
+    { skipto: "0x18"}
+    { name: "FLUSHED_LOW",
+      desc: "Flushed Flag (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "FLUSHED_HIGH",
+      desc: "Flushed Flag (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "BIST_OUT_LOW",
+      desc: "Tag Storage BIST Result (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "BIST_OUT_HIGH",
+      desc: "Tag Storage BIST Result (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "SET_ASSO_LOW",
+      desc: "Instantiated Set-Associativity (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "SET_ASSO_HIGH",
+      desc: "Instantiated Set-Associativity (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "NUM_LINES_LOW",
+      desc: "Instantiated Number of Cache-Lines (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "NUM_LINES_HIGH",
+      desc: "Instantiated Number of Cache-Lines (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "NUM_BLOCKS_LOW",
+      desc: "Instantiated Number of Blocks (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "NUM_BLOCKS_HIGH",
+      desc: "Instantiated Number of Blocks (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "VERSION_LOW",
+      desc: "AXI LLC Version (lower 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "VERSION_HIGH",
+      desc: "AXI LLC Version (upper 32 bit)",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { name: "BIST_STATUS",
+      desc: "Status register of the BIST",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        {bits: "0:0", name: "done", desc: "BIST successfully completed"}
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/axi_llc/doc/registers.md b/docs/um/ip/axi_llc/doc/registers.md
new file mode 100644
index 00000000..35aaad5c
--- /dev/null
+++ b/docs/um/ip/axi_llc/doc/registers.md
@@ -0,0 +1,313 @@
+## Summary
+
+| Name                                          | Offset   |   Length | Description                                       |
+|:----------------------------------------------|:---------|---------:|:--------------------------------------------------|
+| axi_llc.[`CFG_SPM_LOW`](#cfg_spm_low)         | 0x0      |        4 | SPM Configuration (lower 32 bit)                  |
+| axi_llc.[`CFG_SPM_HIGH`](#cfg_spm_high)       | 0x4      |        4 | SPM Configuration (upper 32 bit)                  |
+| axi_llc.[`CFG_FLUSH_LOW`](#cfg_flush_low)     | 0x8      |        4 | Flush Configuration (lower 32 bit)                |
+| axi_llc.[`CFG_FLUSH_HIGH`](#cfg_flush_high)   | 0xc      |        4 | Flush Configuration (upper 32 bit)                |
+| axi_llc.[`COMMIT_CFG`](#commit_cfg)           | 0x10     |        4 | Commit the configuration                          |
+| axi_llc.[`FLUSHED_LOW`](#flushed_low)         | 0x18     |        4 | Flushed Flag (lower 32 bit)                       |
+| axi_llc.[`FLUSHED_HIGH`](#flushed_high)       | 0x1c     |        4 | Flushed Flag (upper 32 bit)                       |
+| axi_llc.[`BIST_OUT_LOW`](#bist_out_low)       | 0x20     |        4 | Tag Storage BIST Result (lower 32 bit)            |
+| axi_llc.[`BIST_OUT_HIGH`](#bist_out_high)     | 0x24     |        4 | Tag Storage BIST Result (upper 32 bit)            |
+| axi_llc.[`SET_ASSO_LOW`](#set_asso_low)       | 0x28     |        4 | Instantiated Set-Associativity (lower 32 bit)     |
+| axi_llc.[`SET_ASSO_HIGH`](#set_asso_high)     | 0x2c     |        4 | Instantiated Set-Associativity (upper 32 bit)     |
+| axi_llc.[`NUM_LINES_LOW`](#num_lines_low)     | 0x30     |        4 | Instantiated Number of Cache-Lines (lower 32 bit) |
+| axi_llc.[`NUM_LINES_HIGH`](#num_lines_high)   | 0x34     |        4 | Instantiated Number of Cache-Lines (upper 32 bit) |
+| axi_llc.[`NUM_BLOCKS_LOW`](#num_blocks_low)   | 0x38     |        4 | Instantiated Number of Blocks (lower 32 bit)      |
+| axi_llc.[`NUM_BLOCKS_HIGH`](#num_blocks_high) | 0x3c     |        4 | Instantiated Number of Blocks (upper 32 bit)      |
+| axi_llc.[`VERSION_LOW`](#version_low)         | 0x40     |        4 | AXI LLC Version (lower 32 bit)                    |
+| axi_llc.[`VERSION_HIGH`](#version_high)       | 0x44     |        4 | AXI LLC Version (upper 32 bit)                    |
+| axi_llc.[`BIST_STATUS`](#bist_status)         | 0x48     |        4 | Status register of the BIST                       |
+
+## CFG_SPM_LOW
+SPM Configuration (lower 32 bit)
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | low    | lower 32 bit  |
+
+## CFG_SPM_HIGH
+SPM Configuration (upper 32 bit)
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | high   | upper 32 bit  |
+
+## CFG_FLUSH_LOW
+Flush Configuration (lower 32 bit)
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | low    | lower 32 bit  |
+
+## CFG_FLUSH_HIGH
+Flush Configuration (upper 32 bit)
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   rw   |   0x0   | high   | upper 32 bit  |
+
+## COMMIT_CFG
+Commit the configuration
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "commit", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description          |
+|:------:|:------:|:-------:|:-------|:---------------------|
+|  31:1  |        |         |        | Reserved             |
+|   0    |  rw1s  |   0x0   | commit | commit configuration |
+
+## FLUSHED_LOW
+Flushed Flag (lower 32 bit)
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## FLUSHED_HIGH
+Flushed Flag (upper 32 bit)
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## BIST_OUT_LOW
+Tag Storage BIST Result (lower 32 bit)
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## BIST_OUT_HIGH
+Tag Storage BIST Result (upper 32 bit)
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## SET_ASSO_LOW
+Instantiated Set-Associativity (lower 32 bit)
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## SET_ASSO_HIGH
+Instantiated Set-Associativity (upper 32 bit)
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## NUM_LINES_LOW
+Instantiated Number of Cache-Lines (lower 32 bit)
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## NUM_LINES_HIGH
+Instantiated Number of Cache-Lines (upper 32 bit)
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## NUM_BLOCKS_LOW
+Instantiated Number of Blocks (lower 32 bit)
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## NUM_BLOCKS_HIGH
+Instantiated Number of Blocks (upper 32 bit)
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## VERSION_LOW
+AXI LLC Version (lower 32 bit)
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "low", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | low    | lower 32 bit  |
+
+## VERSION_HIGH
+AXI LLC Version (upper 32 bit)
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "high", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:0  |   ro   |   0x0   | high   | upper 32 bit  |
+
+## BIST_STATUS
+Status register of the BIST
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                 |
+|:------:|:------:|:-------:|:-------|:----------------------------|
+|  31:1  |        |         |        | Reserved                    |
+|   0    |   ro   |   0x0   | done   | BIST successfully completed |
+
diff --git a/docs/um/ip/axi_realm/data/axi_rt_regs.hjson b/docs/um/ip/axi_realm/data/axi_rt_regs.hjson
new file mode 100644
index 00000000..218252e5
--- /dev/null
+++ b/docs/um/ip/axi_realm/data/axi_rt_regs.hjson
@@ -0,0 +1,466 @@
+
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Automatically generated by ./src/regs/gen_hjson.py
+//
+// Authors:
+// - Thomas Benz <tbenz@iis.ee.ethz.ch>
+
+
+{
+  name: "axi_rt"
+  clock_primary: "clk_i"
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: 32
+
+  param_list: [
+    { name: "NumMrg",
+      desc: "Maximum number of managers.",
+      type: "int",
+      default: "8"
+    },
+    { name: "NumSub",
+      desc: "Configured number of subordinate regions.",
+      type: "int",
+      default: "2"
+    }
+    { name: "NumReg",
+      desc: "Configured number of required registers.",
+      type: "int",
+      default: "16"
+    }
+  ],
+
+  registers: [
+
+    { name:     "major_version"
+      desc:     "Value of the major_version."
+      swaccess: "ro"
+      resval:   "0"
+      fields: [
+        { bits: "31:0", name: "major_version", desc: "Value of the major_version." }
+      ]
+    }
+
+    { name:     "minor_version"
+      desc:     "Value of the minor_version."
+      swaccess: "ro"
+      resval:   "0"
+      fields: [
+        { bits: "31:0", name: "minor_version", desc: "Value of the minor_version." }
+      ]
+    }
+
+    { name:     "patch_version"
+      desc:     "Value of the patch_version."
+      swaccess: "ro"
+      resval:   "0"
+      fields: [
+        { bits: "31:0", name: "patch_version", desc: "Value of the patch_version." }
+      ]
+    }
+
+    { multireg:
+      { name:     "rt_enable"
+        desc:     "Enable RT feature on master"
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "rt_enable"
+        resval:   "0"
+        fields: [
+          { bits: "0:0", name: "enable", desc: "Enable RT feature on master" }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "rt_bypassed"
+        desc:     "Is the RT inactive?"
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumMrg"
+        cname:    "rt_bypassed"
+        fields: [
+          { bits: "0:0", name: "bypassed", desc: "Is the RT inactive?" }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "len_limit"
+        desc:     "Fragmentation of the bursts in beats."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "len_limit"
+        resval:   "0"
+        fields: [
+          { bits: "7:0", name: "len", desc: "Fragmentation of the bursts in beats." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "imtu_enable"
+        desc:     "Enables the IMTU."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "imtu_enable"
+        resval:   "0"
+        fields: [
+          { bits: "0:0", name: "enable", desc: "Enables the IMTU." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "imtu_abort"
+        desc:     "Resets both the period and the budget."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "imtu_abort"
+        resval:   "0"
+        fields: [
+          { bits: "0:0", name: "abort", desc: "Resets both the period and the budget." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "start_addr_sub_low"
+        desc:     "The lower 32bit of the start address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "start_addr_sub_low"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The lower 32bit of the start address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "start_addr_sub_high"
+        desc:     "The higher 32bit of the start address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "start_addr_sub_high"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The higher 32bit of the start address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "end_addr_sub_low"
+        desc:     "The lower 32bit of the end address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "end_addr_sub_low"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The lower 32bit of the end address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "end_addr_sub_high"
+        desc:     "The higher 32bit of the end address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "end_addr_sub_high"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The higher 32bit of the end address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_budget"
+        desc:     "The budget for writes."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "write_budget"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The budget for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_budget"
+        desc:     "The budget for reads."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "read_budget"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_budget", desc: "The budget for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_period"
+        desc:     "The period for writes."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "write_period"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_period", desc: "The period for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_period"
+        desc:     "The period for reads."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "read_period"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_period", desc: "The period for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_budget_left"
+        desc:     "The budget left for writes."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "write_budget_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget_left", desc: "The budget left for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_budget_left"
+        desc:     "The budget left for reads."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "read_budget_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_budget_left", desc: "The budget left for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_period_left"
+        desc:     "The period left for writes."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "write_period_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_period_left", desc: "The period left for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_period_left"
+        desc:     "The period left for reads."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "read_period_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_period_left", desc: "The period left for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "isolate"
+        desc:     "Is the interface requested to be isolated?"
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumMrg"
+        cname:    "isolate"
+        fields: [
+          { bits: "0:0", name: "isolate", desc: "Is the interface requested to be isolated?" }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "isolated"
+        desc:     "Is the interface isolated?"
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumMrg"
+        cname:    "isolated"
+        fields: [
+          { bits: "0:0", name: "isolated", desc: "Is the interface isolated?" }
+        ]
+      }
+    }
+
+    { name:     "num_managers"
+      desc:     "Value of the num_managers parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "num_managers", desc: "Value of the num_managers parameter." }
+      ]
+    }
+
+    { name:     "addr_width"
+      desc:     "Value of the addr_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "addr_width", desc: "Value of the addr_width parameter." }
+      ]
+    }
+
+    { name:     "data_width"
+      desc:     "Value of the data_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "data_width", desc: "Value of the data_width parameter." }
+      ]
+    }
+
+    { name:     "id_width"
+      desc:     "Value of the id_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "id_width", desc: "Value of the id_width parameter." }
+      ]
+    }
+
+    { name:     "user_width"
+      desc:     "Value of the user_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "user_width", desc: "Value of the user_width parameter." }
+      ]
+    }
+
+    { name:     "num_pending"
+      desc:     "Value of the num_pending parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "num_pending", desc: "Value of the num_pending parameter." }
+      ]
+    }
+
+    { name:     "w_buffer_depth"
+      desc:     "Value of the w_buffer_depth parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "w_buffer_depth", desc: "Value of the w_buffer_depth parameter." }
+      ]
+    }
+
+    { name:     "num_addr_regions"
+      desc:     "Value of the num_addr_regions parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "num_addr_regions", desc: "Value of the num_addr_regions parameter." }
+      ]
+    }
+
+    { name:     "period_width"
+      desc:     "Value of the period_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "period_width", desc: "Value of the period_width parameter." }
+      ]
+    }
+
+    { name:     "budget_width"
+      desc:     "Value of the budget_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "budget_width", desc: "Value of the budget_width parameter." }
+      ]
+    }
+
+    { name:     "max_num_managers"
+      desc:     "Value of the max_num_managers parameter."
+      swaccess: "ro"
+      resval:   "8"
+      fields: [
+        { bits: "31:0", name: "max_num_managers", desc: "Value of the max_num_managers parameter." }
+      ]
+    }
+
+  ]
+}
diff --git a/docs/um/ip/axi_realm/data/axi_rt_regs_doc.hjson b/docs/um/ip/axi_realm/data/axi_rt_regs_doc.hjson
new file mode 100644
index 00000000..46fa10aa
--- /dev/null
+++ b/docs/um/ip/axi_realm/data/axi_rt_regs_doc.hjson
@@ -0,0 +1,470 @@
+
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Automatically generated by ./src/regs/gen_hjson.py
+//
+// Authors:
+// - Thomas Benz <tbenz@iis.ee.ethz.ch>
+
+
+{
+  name: "axi_rt"
+  cip_id: "36",
+  version: "0.0.0-alpha.4", // commit 7d7fc13
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: 32
+
+  param_list: [
+    { name: "NumMrg",
+      desc: "Maximum number of managers.",
+      type: "int",
+      default: "8"
+    },
+    { name: "NumSub",
+      desc: "Configured number of subordinate regions.",
+      type: "int",
+      default: "2"
+    }
+    { name: "NumReg",
+      desc: "Configured number of required registers.",
+      type: "int",
+      default: "16"
+    }
+  ],
+
+  registers: [
+
+    { name:     "major_version"
+      desc:     "Value of the major_version."
+      swaccess: "ro"
+      resval:   "0"
+      fields: [
+        { bits: "31:0", name: "major_version", desc: "Value of the major_version." }
+      ]
+    }
+
+    { name:     "minor_version"
+      desc:     "Value of the minor_version."
+      swaccess: "ro"
+      resval:   "0"
+      fields: [
+        { bits: "31:0", name: "minor_version", desc: "Value of the minor_version." }
+      ]
+    }
+
+    { name:     "patch_version"
+      desc:     "Value of the patch_version."
+      swaccess: "ro"
+      resval:   "0"
+      fields: [
+        { bits: "31:0", name: "patch_version", desc: "Value of the patch_version." }
+      ]
+    }
+
+    { multireg:
+      { name:     "rt_enable"
+        desc:     "Enable RT feature on master"
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "rt_enable"
+        resval:   "0"
+        fields: [
+          { bits: "0:0", name: "enable", desc: "Enable RT feature on master" }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "rt_bypassed"
+        desc:     "Is the RT inactive?"
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumMrg"
+        cname:    "rt_bypassed"
+        fields: [
+          { bits: "0:0", name: "bypassed", desc: "Is the RT inactive?" }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "len_limit"
+        desc:     "Fragmentation of the bursts in beats."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "len_limit"
+        resval:   "0"
+        fields: [
+          { bits: "7:0", name: "len", desc: "Fragmentation of the bursts in beats." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "imtu_enable"
+        desc:     "Enables the IMTU."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "imtu_enable"
+        resval:   "0"
+        fields: [
+          { bits: "0:0", name: "enable", desc: "Enables the IMTU." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "imtu_abort"
+        desc:     "Resets both the period and the budget."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumMrg"
+        cname:    "imtu_abort"
+        resval:   "0"
+        fields: [
+          { bits: "0:0", name: "abort", desc: "Resets both the period and the budget." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "start_addr_sub_low"
+        desc:     "The lower 32bit of the start address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "start_addr_sub_low"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The lower 32bit of the start address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "start_addr_sub_high"
+        desc:     "The higher 32bit of the start address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "start_addr_sub_high"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The higher 32bit of the start address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "end_addr_sub_low"
+        desc:     "The lower 32bit of the end address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "end_addr_sub_low"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The lower 32bit of the end address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "end_addr_sub_high"
+        desc:     "The higher 32bit of the end address."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "end_addr_sub_high"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The higher 32bit of the end address." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_budget"
+        desc:     "The budget for writes."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "write_budget"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget", desc: "The budget for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_budget"
+        desc:     "The budget for reads."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "read_budget"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_budget", desc: "The budget for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_period"
+        desc:     "The period for writes."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "write_period"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_period", desc: "The period for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_period"
+        desc:     "The period for reads."
+        swaccess: "wo"
+        hwaccess: "hro"
+        count:    "NumReg"
+        cname:    "read_period"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_period", desc: "The period for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_budget_left"
+        desc:     "The budget left for writes."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "write_budget_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_budget_left", desc: "The budget left for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_budget_left"
+        desc:     "The budget left for reads."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "read_budget_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_budget_left", desc: "The budget left for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "write_period_left"
+        desc:     "The period left for writes."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "write_period_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "write_period_left", desc: "The period left for writes." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "read_period_left"
+        desc:     "The period left for reads."
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumReg"
+        cname:    "read_period_left"
+        resval:   "0"
+        fields: [
+          { bits: "31:0", name: "read_period_left", desc: "The period left for reads." }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "isolate"
+        desc:     "Is the interface requested to be isolated?"
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumMrg"
+        cname:    "isolate"
+        fields: [
+          { bits: "0:0", name: "isolate", desc: "Is the interface requested to be isolated?" }
+        ]
+      }
+    }
+
+    { multireg:
+      { name:     "isolated"
+        desc:     "Is the interface isolated?"
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwqe:     "true"
+        hwext:    "true"
+        count:    "NumMrg"
+        cname:    "isolated"
+        fields: [
+          { bits: "0:0", name: "isolated", desc: "Is the interface isolated?" }
+        ]
+      }
+    }
+
+    { name:     "num_managers"
+      desc:     "Value of the num_managers parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "num_managers", desc: "Value of the num_managers parameter." }
+      ]
+    }
+
+    { name:     "addr_width"
+      desc:     "Value of the addr_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "addr_width", desc: "Value of the addr_width parameter." }
+      ]
+    }
+
+    { name:     "data_width"
+      desc:     "Value of the data_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "data_width", desc: "Value of the data_width parameter." }
+      ]
+    }
+
+    { name:     "id_width"
+      desc:     "Value of the id_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "id_width", desc: "Value of the id_width parameter." }
+      ]
+    }
+
+    { name:     "user_width"
+      desc:     "Value of the user_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "user_width", desc: "Value of the user_width parameter." }
+      ]
+    }
+
+    { name:     "num_pending"
+      desc:     "Value of the num_pending parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "num_pending", desc: "Value of the num_pending parameter." }
+      ]
+    }
+
+    { name:     "w_buffer_depth"
+      desc:     "Value of the w_buffer_depth parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "w_buffer_depth", desc: "Value of the w_buffer_depth parameter." }
+      ]
+    }
+
+    { name:     "num_addr_regions"
+      desc:     "Value of the num_addr_regions parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "num_addr_regions", desc: "Value of the num_addr_regions parameter." }
+      ]
+    }
+
+    { name:     "period_width"
+      desc:     "Value of the period_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "period_width", desc: "Value of the period_width parameter." }
+      ]
+    }
+
+    { name:     "budget_width"
+      desc:     "Value of the budget_width parameter."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwqe:     "true"
+      hwext:    "true"
+      fields: [
+        { bits: "31:0", name: "budget_width", desc: "Value of the budget_width parameter." }
+      ]
+    }
+
+    { name:     "max_num_managers"
+      desc:     "Value of the max_num_managers parameter."
+      swaccess: "ro"
+      resval:   "8"
+      fields: [
+        { bits: "31:0", name: "max_num_managers", desc: "Value of the max_num_managers parameter." }
+      ]
+    }
+
+  ]
+}
diff --git a/docs/um/ip/axi_realm/doc/registers.md b/docs/um/ip/axi_realm/doc/registers.md
new file mode 100644
index 00000000..14964c68
--- /dev/null
+++ b/docs/um/ip/axi_realm/doc/registers.md
@@ -0,0 +1,1069 @@
+## Summary
+
+| Name                                                    | Offset   |   Length | Description                                |
+|:--------------------------------------------------------|:---------|---------:|:-------------------------------------------|
+| axi_rt.[`major_version`](#major_version)                | 0x0      |        4 | Value of the major_version.                |
+| axi_rt.[`minor_version`](#minor_version)                | 0x4      |        4 | Value of the minor_version.                |
+| axi_rt.[`patch_version`](#patch_version)                | 0x8      |        4 | Value of the patch_version.                |
+| axi_rt.[`rt_enable`](#rt_enable)                        | 0xc      |        4 | Enable RT feature on master                |
+| axi_rt.[`rt_bypassed`](#rt_bypassed)                    | 0x10     |        4 | Is the RT inactive?                        |
+| axi_rt.[`len_limit_0`](#len_limit_0)                    | 0x14     |        4 | Fragmentation of the bursts in beats.      |
+| axi_rt.[`len_limit_1`](#len_limit_1)                    | 0x18     |        4 | Fragmentation of the bursts in beats.      |
+| axi_rt.[`imtu_enable`](#imtu_enable)                    | 0x1c     |        4 | Enables the IMTU.                          |
+| axi_rt.[`imtu_abort`](#imtu_abort)                      | 0x20     |        4 | Resets both the period and the budget.     |
+| axi_rt.[`start_addr_sub_low_0`](#start_addr_sub_low)    | 0x24     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_1`](#start_addr_sub_low)    | 0x28     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_2`](#start_addr_sub_low)    | 0x2c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_3`](#start_addr_sub_low)    | 0x30     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_4`](#start_addr_sub_low)    | 0x34     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_5`](#start_addr_sub_low)    | 0x38     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_6`](#start_addr_sub_low)    | 0x3c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_7`](#start_addr_sub_low)    | 0x40     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_8`](#start_addr_sub_low)    | 0x44     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_9`](#start_addr_sub_low)    | 0x48     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_10`](#start_addr_sub_low)   | 0x4c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_11`](#start_addr_sub_low)   | 0x50     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_12`](#start_addr_sub_low)   | 0x54     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_13`](#start_addr_sub_low)   | 0x58     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_14`](#start_addr_sub_low)   | 0x5c     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_low_15`](#start_addr_sub_low)   | 0x60     |        4 | The lower 32bit of the start address.      |
+| axi_rt.[`start_addr_sub_high_0`](#start_addr_sub_high)  | 0x64     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_1`](#start_addr_sub_high)  | 0x68     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_2`](#start_addr_sub_high)  | 0x6c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_3`](#start_addr_sub_high)  | 0x70     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_4`](#start_addr_sub_high)  | 0x74     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_5`](#start_addr_sub_high)  | 0x78     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_6`](#start_addr_sub_high)  | 0x7c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_7`](#start_addr_sub_high)  | 0x80     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_8`](#start_addr_sub_high)  | 0x84     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_9`](#start_addr_sub_high)  | 0x88     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_10`](#start_addr_sub_high) | 0x8c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_11`](#start_addr_sub_high) | 0x90     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_12`](#start_addr_sub_high) | 0x94     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_13`](#start_addr_sub_high) | 0x98     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_14`](#start_addr_sub_high) | 0x9c     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`start_addr_sub_high_15`](#start_addr_sub_high) | 0xa0     |        4 | The higher 32bit of the start address.     |
+| axi_rt.[`end_addr_sub_low_0`](#end_addr_sub_low)        | 0xa4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_1`](#end_addr_sub_low)        | 0xa8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_2`](#end_addr_sub_low)        | 0xac     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_3`](#end_addr_sub_low)        | 0xb0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_4`](#end_addr_sub_low)        | 0xb4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_5`](#end_addr_sub_low)        | 0xb8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_6`](#end_addr_sub_low)        | 0xbc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_7`](#end_addr_sub_low)        | 0xc0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_8`](#end_addr_sub_low)        | 0xc4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_9`](#end_addr_sub_low)        | 0xc8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_10`](#end_addr_sub_low)       | 0xcc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_11`](#end_addr_sub_low)       | 0xd0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_12`](#end_addr_sub_low)       | 0xd4     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_13`](#end_addr_sub_low)       | 0xd8     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_14`](#end_addr_sub_low)       | 0xdc     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_low_15`](#end_addr_sub_low)       | 0xe0     |        4 | The lower 32bit of the end address.        |
+| axi_rt.[`end_addr_sub_high_0`](#end_addr_sub_high)      | 0xe4     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_1`](#end_addr_sub_high)      | 0xe8     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_2`](#end_addr_sub_high)      | 0xec     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_3`](#end_addr_sub_high)      | 0xf0     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_4`](#end_addr_sub_high)      | 0xf4     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_5`](#end_addr_sub_high)      | 0xf8     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_6`](#end_addr_sub_high)      | 0xfc     |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_7`](#end_addr_sub_high)      | 0x100    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_8`](#end_addr_sub_high)      | 0x104    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_9`](#end_addr_sub_high)      | 0x108    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_10`](#end_addr_sub_high)     | 0x10c    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_11`](#end_addr_sub_high)     | 0x110    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_12`](#end_addr_sub_high)     | 0x114    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_13`](#end_addr_sub_high)     | 0x118    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_14`](#end_addr_sub_high)     | 0x11c    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`end_addr_sub_high_15`](#end_addr_sub_high)     | 0x120    |        4 | The higher 32bit of the end address.       |
+| axi_rt.[`write_budget_0`](#write_budget)                | 0x124    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_1`](#write_budget)                | 0x128    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_2`](#write_budget)                | 0x12c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_3`](#write_budget)                | 0x130    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_4`](#write_budget)                | 0x134    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_5`](#write_budget)                | 0x138    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_6`](#write_budget)                | 0x13c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_7`](#write_budget)                | 0x140    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_8`](#write_budget)                | 0x144    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_9`](#write_budget)                | 0x148    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_10`](#write_budget)               | 0x14c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_11`](#write_budget)               | 0x150    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_12`](#write_budget)               | 0x154    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_13`](#write_budget)               | 0x158    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_14`](#write_budget)               | 0x15c    |        4 | The budget for writes.                     |
+| axi_rt.[`write_budget_15`](#write_budget)               | 0x160    |        4 | The budget for writes.                     |
+| axi_rt.[`read_budget_0`](#read_budget)                  | 0x164    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_1`](#read_budget)                  | 0x168    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_2`](#read_budget)                  | 0x16c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_3`](#read_budget)                  | 0x170    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_4`](#read_budget)                  | 0x174    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_5`](#read_budget)                  | 0x178    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_6`](#read_budget)                  | 0x17c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_7`](#read_budget)                  | 0x180    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_8`](#read_budget)                  | 0x184    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_9`](#read_budget)                  | 0x188    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_10`](#read_budget)                 | 0x18c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_11`](#read_budget)                 | 0x190    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_12`](#read_budget)                 | 0x194    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_13`](#read_budget)                 | 0x198    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_14`](#read_budget)                 | 0x19c    |        4 | The budget for reads.                      |
+| axi_rt.[`read_budget_15`](#read_budget)                 | 0x1a0    |        4 | The budget for reads.                      |
+| axi_rt.[`write_period_0`](#write_period)                | 0x1a4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_1`](#write_period)                | 0x1a8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_2`](#write_period)                | 0x1ac    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_3`](#write_period)                | 0x1b0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_4`](#write_period)                | 0x1b4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_5`](#write_period)                | 0x1b8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_6`](#write_period)                | 0x1bc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_7`](#write_period)                | 0x1c0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_8`](#write_period)                | 0x1c4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_9`](#write_period)                | 0x1c8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_10`](#write_period)               | 0x1cc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_11`](#write_period)               | 0x1d0    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_12`](#write_period)               | 0x1d4    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_13`](#write_period)               | 0x1d8    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_14`](#write_period)               | 0x1dc    |        4 | The period for writes.                     |
+| axi_rt.[`write_period_15`](#write_period)               | 0x1e0    |        4 | The period for writes.                     |
+| axi_rt.[`read_period_0`](#read_period)                  | 0x1e4    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_1`](#read_period)                  | 0x1e8    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_2`](#read_period)                  | 0x1ec    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_3`](#read_period)                  | 0x1f0    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_4`](#read_period)                  | 0x1f4    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_5`](#read_period)                  | 0x1f8    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_6`](#read_period)                  | 0x1fc    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_7`](#read_period)                  | 0x200    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_8`](#read_period)                  | 0x204    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_9`](#read_period)                  | 0x208    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_10`](#read_period)                 | 0x20c    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_11`](#read_period)                 | 0x210    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_12`](#read_period)                 | 0x214    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_13`](#read_period)                 | 0x218    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_14`](#read_period)                 | 0x21c    |        4 | The period for reads.                      |
+| axi_rt.[`read_period_15`](#read_period)                 | 0x220    |        4 | The period for reads.                      |
+| axi_rt.[`write_budget_left_0`](#write_budget_left)      | 0x224    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_1`](#write_budget_left)      | 0x228    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_2`](#write_budget_left)      | 0x22c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_3`](#write_budget_left)      | 0x230    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_4`](#write_budget_left)      | 0x234    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_5`](#write_budget_left)      | 0x238    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_6`](#write_budget_left)      | 0x23c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_7`](#write_budget_left)      | 0x240    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_8`](#write_budget_left)      | 0x244    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_9`](#write_budget_left)      | 0x248    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_10`](#write_budget_left)     | 0x24c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_11`](#write_budget_left)     | 0x250    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_12`](#write_budget_left)     | 0x254    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_13`](#write_budget_left)     | 0x258    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_14`](#write_budget_left)     | 0x25c    |        4 | The budget left for writes.                |
+| axi_rt.[`write_budget_left_15`](#write_budget_left)     | 0x260    |        4 | The budget left for writes.                |
+| axi_rt.[`read_budget_left_0`](#read_budget_left)        | 0x264    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_1`](#read_budget_left)        | 0x268    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_2`](#read_budget_left)        | 0x26c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_3`](#read_budget_left)        | 0x270    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_4`](#read_budget_left)        | 0x274    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_5`](#read_budget_left)        | 0x278    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_6`](#read_budget_left)        | 0x27c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_7`](#read_budget_left)        | 0x280    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_8`](#read_budget_left)        | 0x284    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_9`](#read_budget_left)        | 0x288    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_10`](#read_budget_left)       | 0x28c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_11`](#read_budget_left)       | 0x290    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_12`](#read_budget_left)       | 0x294    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_13`](#read_budget_left)       | 0x298    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_14`](#read_budget_left)       | 0x29c    |        4 | The budget left for reads.                 |
+| axi_rt.[`read_budget_left_15`](#read_budget_left)       | 0x2a0    |        4 | The budget left for reads.                 |
+| axi_rt.[`write_period_left_0`](#write_period_left)      | 0x2a4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_1`](#write_period_left)      | 0x2a8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_2`](#write_period_left)      | 0x2ac    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_3`](#write_period_left)      | 0x2b0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_4`](#write_period_left)      | 0x2b4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_5`](#write_period_left)      | 0x2b8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_6`](#write_period_left)      | 0x2bc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_7`](#write_period_left)      | 0x2c0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_8`](#write_period_left)      | 0x2c4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_9`](#write_period_left)      | 0x2c8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_10`](#write_period_left)     | 0x2cc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_11`](#write_period_left)     | 0x2d0    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_12`](#write_period_left)     | 0x2d4    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_13`](#write_period_left)     | 0x2d8    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_14`](#write_period_left)     | 0x2dc    |        4 | The period left for writes.                |
+| axi_rt.[`write_period_left_15`](#write_period_left)     | 0x2e0    |        4 | The period left for writes.                |
+| axi_rt.[`read_period_left_0`](#read_period_left)        | 0x2e4    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_1`](#read_period_left)        | 0x2e8    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_2`](#read_period_left)        | 0x2ec    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_3`](#read_period_left)        | 0x2f0    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_4`](#read_period_left)        | 0x2f4    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_5`](#read_period_left)        | 0x2f8    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_6`](#read_period_left)        | 0x2fc    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_7`](#read_period_left)        | 0x300    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_8`](#read_period_left)        | 0x304    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_9`](#read_period_left)        | 0x308    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_10`](#read_period_left)       | 0x30c    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_11`](#read_period_left)       | 0x310    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_12`](#read_period_left)       | 0x314    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_13`](#read_period_left)       | 0x318    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_14`](#read_period_left)       | 0x31c    |        4 | The period left for reads.                 |
+| axi_rt.[`read_period_left_15`](#read_period_left)       | 0x320    |        4 | The period left for reads.                 |
+| axi_rt.[`isolate`](#isolate)                            | 0x324    |        4 | Is the interface requested to be isolated? |
+| axi_rt.[`isolated`](#isolated)                          | 0x328    |        4 | Is the interface isolated?                 |
+| axi_rt.[`num_managers`](#num_managers)                  | 0x32c    |        4 | Value of the num_managers parameter.       |
+| axi_rt.[`addr_width`](#addr_width)                      | 0x330    |        4 | Value of the addr_width parameter.         |
+| axi_rt.[`data_width`](#data_width)                      | 0x334    |        4 | Value of the data_width parameter.         |
+| axi_rt.[`id_width`](#id_width)                          | 0x338    |        4 | Value of the id_width parameter.           |
+| axi_rt.[`user_width`](#user_width)                      | 0x33c    |        4 | Value of the user_width parameter.         |
+| axi_rt.[`num_pending`](#num_pending)                    | 0x340    |        4 | Value of the num_pending parameter.        |
+| axi_rt.[`w_buffer_depth`](#w_buffer_depth)              | 0x344    |        4 | Value of the w_buffer_depth parameter.     |
+| axi_rt.[`num_addr_regions`](#num_addr_regions)          | 0x348    |        4 | Value of the num_addr_regions parameter.   |
+| axi_rt.[`period_width`](#period_width)                  | 0x34c    |        4 | Value of the period_width parameter.       |
+| axi_rt.[`budget_width`](#budget_width)                  | 0x350    |        4 | Value of the budget_width parameter.       |
+| axi_rt.[`max_num_managers`](#max_num_managers)          | 0x354    |        4 | Value of the max_num_managers parameter.   |
+
+## major_version
+Value of the major_version.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "major_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | major_version | Value of the major_version. |
+
+## minor_version
+Value of the minor_version.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "minor_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | minor_version | Value of the minor_version. |
+
+## patch_version
+Value of the patch_version.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "patch_version", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                 |
+|:------:|:------:|:-------:|:--------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | patch_version | Value of the patch_version. |
+
+## rt_enable
+Enable RT feature on master
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                 |
+|:------:|:------:|:-------:|:---------|:----------------------------|
+|  31:8  |        |         |          | Reserved                    |
+|   7    |   wo   |   0x0   | enable_7 | Enable RT feature on master |
+|   6    |   wo   |   0x0   | enable_6 | Enable RT feature on master |
+|   5    |   wo   |   0x0   | enable_5 | Enable RT feature on master |
+|   4    |   wo   |   0x0   | enable_4 | Enable RT feature on master |
+|   3    |   wo   |   0x0   | enable_3 | Enable RT feature on master |
+|   2    |   wo   |   0x0   | enable_2 | Enable RT feature on master |
+|   1    |   wo   |   0x0   | enable_1 | Enable RT feature on master |
+|   0    |   wo   |   0x0   | enable_0 | Enable RT feature on master |
+
+## rt_bypassed
+Is the RT inactive?
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypassed_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "bypassed_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description         |
+|:------:|:------:|:-------:|:-----------|:--------------------|
+|  31:8  |        |         |            | Reserved            |
+|   7    |   ro   |    x    | bypassed_7 | Is the RT inactive? |
+|   6    |   ro   |    x    | bypassed_6 | Is the RT inactive? |
+|   5    |   ro   |    x    | bypassed_5 | Is the RT inactive? |
+|   4    |   ro   |    x    | bypassed_4 | Is the RT inactive? |
+|   3    |   ro   |    x    | bypassed_3 | Is the RT inactive? |
+|   2    |   ro   |    x    | bypassed_2 | Is the RT inactive? |
+|   1    |   ro   |    x    | bypassed_1 | Is the RT inactive? |
+|   0    |   ro   |    x    | bypassed_0 | Is the RT inactive? |
+
+## len_limit_0
+Fragmentation of the bursts in beats.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "len_0", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_1", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_2", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_3", "bits": 8, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------|
+| 31:24  |   wo   |   0x0   | len_3  | Fragmentation of the bursts in beats. |
+| 23:16  |   wo   |   0x0   | len_2  | Fragmentation of the bursts in beats. |
+|  15:8  |   wo   |   0x0   | len_1  | Fragmentation of the bursts in beats. |
+|  7:0   |   wo   |   0x0   | len_0  | Fragmentation of the bursts in beats. |
+
+## len_limit_1
+Fragmentation of the bursts in beats.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "len_4", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_5", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_6", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "len_7", "bits": 8, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description    |
+|:------:|:------:|:-------:|:-------|:---------------|
+| 31:24  |   wo   |   0x0   | len_7  | For len_limit1 |
+| 23:16  |   wo   |   0x0   | len_6  | For len_limit1 |
+|  15:8  |   wo   |   0x0   | len_5  | For len_limit1 |
+|  7:0   |   wo   |   0x0   | len_4  | For len_limit1 |
+
+## imtu_enable
+Enables the IMTU.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "enable_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description       |
+|:------:|:------:|:-------:|:---------|:------------------|
+|  31:8  |        |         |          | Reserved          |
+|   7    |   wo   |   0x0   | enable_7 | Enables the IMTU. |
+|   6    |   wo   |   0x0   | enable_6 | Enables the IMTU. |
+|   5    |   wo   |   0x0   | enable_5 | Enables the IMTU. |
+|   4    |   wo   |   0x0   | enable_4 | Enables the IMTU. |
+|   3    |   wo   |   0x0   | enable_3 | Enables the IMTU. |
+|   2    |   wo   |   0x0   | enable_2 | Enables the IMTU. |
+|   1    |   wo   |   0x0   | enable_1 | Enables the IMTU. |
+|   0    |   wo   |   0x0   | enable_0 | Enables the IMTU. |
+
+## imtu_abort
+Resets both the period and the budget.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "abort_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "abort_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                            |
+|:------:|:------:|:-------:|:--------|:---------------------------------------|
+|  31:8  |        |         |         | Reserved                               |
+|   7    |   wo   |   0x0   | abort_7 | Resets both the period and the budget. |
+|   6    |   wo   |   0x0   | abort_6 | Resets both the period and the budget. |
+|   5    |   wo   |   0x0   | abort_5 | Resets both the period and the budget. |
+|   4    |   wo   |   0x0   | abort_4 | Resets both the period and the budget. |
+|   3    |   wo   |   0x0   | abort_3 | Resets both the period and the budget. |
+|   2    |   wo   |   0x0   | abort_2 | Resets both the period and the budget. |
+|   1    |   wo   |   0x0   | abort_1 | Resets both the period and the budget. |
+|   0    |   wo   |   0x0   | abort_0 | Resets both the period and the budget. |
+
+## start_addr_sub_low
+The lower 32bit of the start address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                  | Offset   |
+|:----------------------|:---------|
+| start_addr_sub_low_0  | 0x24     |
+| start_addr_sub_low_1  | 0x28     |
+| start_addr_sub_low_2  | 0x2c     |
+| start_addr_sub_low_3  | 0x30     |
+| start_addr_sub_low_4  | 0x34     |
+| start_addr_sub_low_5  | 0x38     |
+| start_addr_sub_low_6  | 0x3c     |
+| start_addr_sub_low_7  | 0x40     |
+| start_addr_sub_low_8  | 0x44     |
+| start_addr_sub_low_9  | 0x48     |
+| start_addr_sub_low_10 | 0x4c     |
+| start_addr_sub_low_11 | 0x50     |
+| start_addr_sub_low_12 | 0x54     |
+| start_addr_sub_low_13 | 0x58     |
+| start_addr_sub_low_14 | 0x5c     |
+| start_addr_sub_low_15 | 0x60     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                           |
+|:------:|:------:|:-------:|:-------------|:--------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The lower 32bit of the start address. |
+
+## start_addr_sub_high
+The higher 32bit of the start address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                   | Offset   |
+|:-----------------------|:---------|
+| start_addr_sub_high_0  | 0x64     |
+| start_addr_sub_high_1  | 0x68     |
+| start_addr_sub_high_2  | 0x6c     |
+| start_addr_sub_high_3  | 0x70     |
+| start_addr_sub_high_4  | 0x74     |
+| start_addr_sub_high_5  | 0x78     |
+| start_addr_sub_high_6  | 0x7c     |
+| start_addr_sub_high_7  | 0x80     |
+| start_addr_sub_high_8  | 0x84     |
+| start_addr_sub_high_9  | 0x88     |
+| start_addr_sub_high_10 | 0x8c     |
+| start_addr_sub_high_11 | 0x90     |
+| start_addr_sub_high_12 | 0x94     |
+| start_addr_sub_high_13 | 0x98     |
+| start_addr_sub_high_14 | 0x9c     |
+| start_addr_sub_high_15 | 0xa0     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                            |
+|:------:|:------:|:-------:|:-------------|:---------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The higher 32bit of the start address. |
+
+## end_addr_sub_low
+The lower 32bit of the end address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| end_addr_sub_low_0  | 0xa4     |
+| end_addr_sub_low_1  | 0xa8     |
+| end_addr_sub_low_2  | 0xac     |
+| end_addr_sub_low_3  | 0xb0     |
+| end_addr_sub_low_4  | 0xb4     |
+| end_addr_sub_low_5  | 0xb8     |
+| end_addr_sub_low_6  | 0xbc     |
+| end_addr_sub_low_7  | 0xc0     |
+| end_addr_sub_low_8  | 0xc4     |
+| end_addr_sub_low_9  | 0xc8     |
+| end_addr_sub_low_10 | 0xcc     |
+| end_addr_sub_low_11 | 0xd0     |
+| end_addr_sub_low_12 | 0xd4     |
+| end_addr_sub_low_13 | 0xd8     |
+| end_addr_sub_low_14 | 0xdc     |
+| end_addr_sub_low_15 | 0xe0     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                         |
+|:------:|:------:|:-------:|:-------------|:------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The lower 32bit of the end address. |
+
+## end_addr_sub_high
+The higher 32bit of the end address.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| end_addr_sub_high_0  | 0xe4     |
+| end_addr_sub_high_1  | 0xe8     |
+| end_addr_sub_high_2  | 0xec     |
+| end_addr_sub_high_3  | 0xf0     |
+| end_addr_sub_high_4  | 0xf4     |
+| end_addr_sub_high_5  | 0xf8     |
+| end_addr_sub_high_6  | 0xfc     |
+| end_addr_sub_high_7  | 0x100    |
+| end_addr_sub_high_8  | 0x104    |
+| end_addr_sub_high_9  | 0x108    |
+| end_addr_sub_high_10 | 0x10c    |
+| end_addr_sub_high_11 | 0x110    |
+| end_addr_sub_high_12 | 0x114    |
+| end_addr_sub_high_13 | 0x118    |
+| end_addr_sub_high_14 | 0x11c    |
+| end_addr_sub_high_15 | 0x120    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The higher 32bit of the end address. |
+
+## write_budget
+The budget for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name            | Offset   |
+|:----------------|:---------|
+| write_budget_0  | 0x124    |
+| write_budget_1  | 0x128    |
+| write_budget_2  | 0x12c    |
+| write_budget_3  | 0x130    |
+| write_budget_4  | 0x134    |
+| write_budget_5  | 0x138    |
+| write_budget_6  | 0x13c    |
+| write_budget_7  | 0x140    |
+| write_budget_8  | 0x144    |
+| write_budget_9  | 0x148    |
+| write_budget_10 | 0x14c    |
+| write_budget_11 | 0x150    |
+| write_budget_12 | 0x154    |
+| write_budget_13 | 0x158    |
+| write_budget_14 | 0x15c    |
+| write_budget_15 | 0x160    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description            |
+|:------:|:------:|:-------:|:-------------|:-----------------------|
+|  31:0  |   wo   |   0x0   | write_budget | The budget for writes. |
+
+## read_budget
+The budget for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| read_budget_0  | 0x164    |
+| read_budget_1  | 0x168    |
+| read_budget_2  | 0x16c    |
+| read_budget_3  | 0x170    |
+| read_budget_4  | 0x174    |
+| read_budget_5  | 0x178    |
+| read_budget_6  | 0x17c    |
+| read_budget_7  | 0x180    |
+| read_budget_8  | 0x184    |
+| read_budget_9  | 0x188    |
+| read_budget_10 | 0x18c    |
+| read_budget_11 | 0x190    |
+| read_budget_12 | 0x194    |
+| read_budget_13 | 0x198    |
+| read_budget_14 | 0x19c    |
+| read_budget_15 | 0x1a0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_budget", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description           |
+|:------:|:------:|:-------:|:------------|:----------------------|
+|  31:0  |   wo   |   0x0   | read_budget | The budget for reads. |
+
+## write_period
+The period for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name            | Offset   |
+|:----------------|:---------|
+| write_period_0  | 0x1a4    |
+| write_period_1  | 0x1a8    |
+| write_period_2  | 0x1ac    |
+| write_period_3  | 0x1b0    |
+| write_period_4  | 0x1b4    |
+| write_period_5  | 0x1b8    |
+| write_period_6  | 0x1bc    |
+| write_period_7  | 0x1c0    |
+| write_period_8  | 0x1c4    |
+| write_period_9  | 0x1c8    |
+| write_period_10 | 0x1cc    |
+| write_period_11 | 0x1d0    |
+| write_period_12 | 0x1d4    |
+| write_period_13 | 0x1d8    |
+| write_period_14 | 0x1dc    |
+| write_period_15 | 0x1e0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_period", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description            |
+|:------:|:------:|:-------:|:-------------|:-----------------------|
+|  31:0  |   wo   |   0x0   | write_period | The period for writes. |
+
+## read_period
+The period for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| read_period_0  | 0x1e4    |
+| read_period_1  | 0x1e8    |
+| read_period_2  | 0x1ec    |
+| read_period_3  | 0x1f0    |
+| read_period_4  | 0x1f4    |
+| read_period_5  | 0x1f8    |
+| read_period_6  | 0x1fc    |
+| read_period_7  | 0x200    |
+| read_period_8  | 0x204    |
+| read_period_9  | 0x208    |
+| read_period_10 | 0x20c    |
+| read_period_11 | 0x210    |
+| read_period_12 | 0x214    |
+| read_period_13 | 0x218    |
+| read_period_14 | 0x21c    |
+| read_period_15 | 0x220    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_period", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description           |
+|:------:|:------:|:-------:|:------------|:----------------------|
+|  31:0  |   wo   |   0x0   | read_period | The period for reads. |
+
+## write_budget_left
+The budget left for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| write_budget_left_0  | 0x224    |
+| write_budget_left_1  | 0x228    |
+| write_budget_left_2  | 0x22c    |
+| write_budget_left_3  | 0x230    |
+| write_budget_left_4  | 0x234    |
+| write_budget_left_5  | 0x238    |
+| write_budget_left_6  | 0x23c    |
+| write_budget_left_7  | 0x240    |
+| write_budget_left_8  | 0x244    |
+| write_budget_left_9  | 0x248    |
+| write_budget_left_10 | 0x24c    |
+| write_budget_left_11 | 0x250    |
+| write_budget_left_12 | 0x254    |
+| write_budget_left_13 | 0x258    |
+| write_budget_left_14 | 0x25c    |
+| write_budget_left_15 | 0x260    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_budget_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                 |
+|:------:|:------:|:-------:|:------------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | write_budget_left | The budget left for writes. |
+
+## read_budget_left
+The budget left for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| read_budget_left_0  | 0x264    |
+| read_budget_left_1  | 0x268    |
+| read_budget_left_2  | 0x26c    |
+| read_budget_left_3  | 0x270    |
+| read_budget_left_4  | 0x274    |
+| read_budget_left_5  | 0x278    |
+| read_budget_left_6  | 0x27c    |
+| read_budget_left_7  | 0x280    |
+| read_budget_left_8  | 0x284    |
+| read_budget_left_9  | 0x288    |
+| read_budget_left_10 | 0x28c    |
+| read_budget_left_11 | 0x290    |
+| read_budget_left_12 | 0x294    |
+| read_budget_left_13 | 0x298    |
+| read_budget_left_14 | 0x29c    |
+| read_budget_left_15 | 0x2a0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_budget_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------|
+|  31:0  |   ro   |   0x0   | read_budget_left | The budget left for reads. |
+
+## write_period_left
+The period left for writes.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                 | Offset   |
+|:---------------------|:---------|
+| write_period_left_0  | 0x2a4    |
+| write_period_left_1  | 0x2a8    |
+| write_period_left_2  | 0x2ac    |
+| write_period_left_3  | 0x2b0    |
+| write_period_left_4  | 0x2b4    |
+| write_period_left_5  | 0x2b8    |
+| write_period_left_6  | 0x2bc    |
+| write_period_left_7  | 0x2c0    |
+| write_period_left_8  | 0x2c4    |
+| write_period_left_9  | 0x2c8    |
+| write_period_left_10 | 0x2cc    |
+| write_period_left_11 | 0x2d0    |
+| write_period_left_12 | 0x2d4    |
+| write_period_left_13 | 0x2d8    |
+| write_period_left_14 | 0x2dc    |
+| write_period_left_15 | 0x2e0    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_period_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                 |
+|:------:|:------:|:-------:|:------------------|:----------------------------|
+|  31:0  |   ro   |   0x0   | write_period_left | The period left for writes. |
+
+## read_period_left
+The period left for reads.
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| read_period_left_0  | 0x2e4    |
+| read_period_left_1  | 0x2e8    |
+| read_period_left_2  | 0x2ec    |
+| read_period_left_3  | 0x2f0    |
+| read_period_left_4  | 0x2f4    |
+| read_period_left_5  | 0x2f8    |
+| read_period_left_6  | 0x2fc    |
+| read_period_left_7  | 0x300    |
+| read_period_left_8  | 0x304    |
+| read_period_left_9  | 0x308    |
+| read_period_left_10 | 0x30c    |
+| read_period_left_11 | 0x310    |
+| read_period_left_12 | 0x314    |
+| read_period_left_13 | 0x318    |
+| read_period_left_14 | 0x31c    |
+| read_period_left_15 | 0x320    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "read_period_left", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------|
+|  31:0  |   ro   |   0x0   | read_period_left | The period left for reads. |
+
+## isolate
+Is the interface requested to be isolated?
+- Offset: `0x324`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "isolate_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolate_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------|
+|  31:8  |        |         |           | Reserved                                   |
+|   7    |   ro   |    x    | isolate_7 | Is the interface requested to be isolated? |
+|   6    |   ro   |    x    | isolate_6 | Is the interface requested to be isolated? |
+|   5    |   ro   |    x    | isolate_5 | Is the interface requested to be isolated? |
+|   4    |   ro   |    x    | isolate_4 | Is the interface requested to be isolated? |
+|   3    |   ro   |    x    | isolate_3 | Is the interface requested to be isolated? |
+|   2    |   ro   |    x    | isolate_2 | Is the interface requested to be isolated? |
+|   1    |   ro   |    x    | isolate_1 | Is the interface requested to be isolated? |
+|   0    |   ro   |    x    | isolate_0 | Is the interface requested to be isolated? |
+
+## isolated
+Is the interface isolated?
+- Offset: `0x328`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "isolated_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "isolated_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                |
+|:------:|:------:|:-------:|:-----------|:---------------------------|
+|  31:8  |        |         |            | Reserved                   |
+|   7    |   ro   |    x    | isolated_7 | Is the interface isolated? |
+|   6    |   ro   |    x    | isolated_6 | Is the interface isolated? |
+|   5    |   ro   |    x    | isolated_5 | Is the interface isolated? |
+|   4    |   ro   |    x    | isolated_4 | Is the interface isolated? |
+|   3    |   ro   |    x    | isolated_3 | Is the interface isolated? |
+|   2    |   ro   |    x    | isolated_2 | Is the interface isolated? |
+|   1    |   ro   |    x    | isolated_1 | Is the interface isolated? |
+|   0    |   ro   |    x    | isolated_0 | Is the interface isolated? |
+
+## num_managers
+Value of the num_managers parameter.
+- Offset: `0x32c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_managers", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | num_managers | Value of the num_managers parameter. |
+
+## addr_width
+Value of the addr_width parameter.
+- Offset: `0x330`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "addr_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | addr_width | Value of the addr_width parameter. |
+
+## data_width
+Value of the data_width parameter.
+- Offset: `0x334`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | data_width | Value of the data_width parameter. |
+
+## id_width
+Value of the id_width parameter.
+- Offset: `0x338`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "id_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                      |
+|:------:|:------:|:-------:|:---------|:---------------------------------|
+|  31:0  |   ro   |    x    | id_width | Value of the id_width parameter. |
+
+## user_width
+Value of the user_width parameter.
+- Offset: `0x33c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "user_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                        |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------|
+|  31:0  |   ro   |    x    | user_width | Value of the user_width parameter. |
+
+## num_pending
+Value of the num_pending parameter.
+- Offset: `0x340`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_pending", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                         |
+|:------:|:------:|:-------:|:------------|:------------------------------------|
+|  31:0  |   ro   |    x    | num_pending | Value of the num_pending parameter. |
+
+## w_buffer_depth
+Value of the w_buffer_depth parameter.
+- Offset: `0x344`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "w_buffer_depth", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                            |
+|:------:|:------:|:-------:|:---------------|:---------------------------------------|
+|  31:0  |   ro   |    x    | w_buffer_depth | Value of the w_buffer_depth parameter. |
+
+## num_addr_regions
+Value of the num_addr_regions parameter.
+- Offset: `0x348`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "num_addr_regions", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                              |
+|:------:|:------:|:-------:|:-----------------|:-----------------------------------------|
+|  31:0  |   ro   |    x    | num_addr_regions | Value of the num_addr_regions parameter. |
+
+## period_width
+Value of the period_width parameter.
+- Offset: `0x34c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "period_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | period_width | Value of the period_width parameter. |
+
+## budget_width
+Value of the budget_width parameter.
+- Offset: `0x350`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "budget_width", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                          |
+|:------:|:------:|:-------:|:-------------|:-------------------------------------|
+|  31:0  |   ro   |    x    | budget_width | Value of the budget_width parameter. |
+
+## max_num_managers
+Value of the max_num_managers parameter.
+- Offset: `0x354`
+- Reset default: `0x8`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "max_num_managers", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                              |
+|:------:|:------:|:-------:|:-----------------|:-----------------------------------------|
+|  31:0  |   ro   |   0x8   | max_num_managers | Value of the max_num_managers parameter. |
+
diff --git a/docs/um/ip/can_bus/data/can_bus_regs.hjson b/docs/um/ip/can_bus/data/can_bus_regs.hjson
new file mode 100644
index 00000000..15588bf4
--- /dev/null
+++ b/docs/um/ip/can_bus/data/can_bus_regs.hjson
@@ -0,0 +1,11535 @@
+// Copyright 2015-2024 Czech Technical University in Prague
+// Licensed under a dual MIT / Non-commercial license; see LICENSE for details.
+// SPDX-License-Identifier: MIT AND LicenseRef-CTU-NC
+//
+// Developed by:
+//   Ondrej Ille <ondrej.ille@gmail.com>
+//   Martin Jerabek <martin.jerabek01@gmail.com>
+//
+// CTU CAN FD IP Core – Department of Measurement, CTU in Prague
+// Register layout of CAN BUS
+
+{
+  name: "can_bus",
+  human_name: "CAN Bus Controller",
+  one_line_desc: "Controller for CAN Bus communication",
+  one_paragraph_desc: '''The CAN Bus Controller IP facilitates communication over the Controller Area Network (CAN) protocol.
+                      It supports both standard and extended frames, with configurable baud rates, interrupt handling, and filtering capabilities.
+                      ''',
+  cip_id: "36",
+  version: "0.0.0", //null, 0ec0bf8
+  regwidth: "32",
+  clocking: [
+    { clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true }
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  registers: [
+    {
+      name: "ahb_ifc_hsel_valid",
+      desc: "Auto-extracted signal hsel_valid from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_write_acc_d",
+      desc: "Auto-extracted signal write_acc_d from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_write_acc_q",
+      desc: "Auto-extracted signal write_acc_q from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_haddr_q",
+      desc: "Auto-extracted signal haddr_q from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_h_ready_raw",
+      desc: "Auto-extracted signal h_ready_raw from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_sbe_d",
+      desc: "Auto-extracted signal sbe_d from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_sbe_q",
+      desc: "Auto-extracted signal sbe_q from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_swr_i",
+      desc: "Auto-extracted signal swr_i from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ahb_ifc_srd_i",
+      desc: "Auto-extracted signal srd_i from ahb_ifc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_discard_stuff_bit",
+      desc: "Auto-extracted signal discard_stuff_bit from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_non_fix_to_fix_chng",
+      desc: "Auto-extracted signal non_fix_to_fix_chng from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_stuff_lvl_reached",
+      desc: "Auto-extracted signal stuff_lvl_reached from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_stuff_rule_violate",
+      desc: "Auto-extracted signal stuff_rule_violate from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_enable_prev",
+      desc: "Auto-extracted signal enable_prev from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_fixed_prev_q",
+      desc: "Auto-extracted signal fixed_prev_q from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_fixed_prev_d",
+      desc: "Auto-extracted signal fixed_prev_d from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_same_bits_erase",
+      desc: "Auto-extracted signal same_bits_erase from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_destuffed_q",
+      desc: "Auto-extracted signal destuffed_q from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_destuffed_d",
+      desc: "Auto-extracted signal destuffed_d from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_stuff_err_q",
+      desc: "Auto-extracted signal stuff_err_q from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_stuff_err_d",
+      desc: "Auto-extracted signal stuff_err_d from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_prev_val_q",
+      desc: "Auto-extracted signal prev_val_q from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_destuffing_prev_val_d",
+      desc: "Auto-extracted signal prev_val_d from bit_destuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_err_detector_bit_err_d",
+      desc: "Auto-extracted signal bit_err_d from bit_err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_err_detector_bit_err_q",
+      desc: "Auto-extracted signal bit_err_q from bit_err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_err_detector_bit_err_ssp_capt_d",
+      desc: "Auto-extracted signal bit_err_ssp_capt_d from bit_err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_err_detector_bit_err_ssp_capt_q",
+      desc: "Auto-extracted signal bit_err_ssp_capt_q from bit_err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_err_detector_bit_err_ssp_valid",
+      desc: "Auto-extracted signal bit_err_ssp_valid from bit_err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_err_detector_bit_err_ssp_condition",
+      desc: "Auto-extracted signal bit_err_ssp_condition from bit_err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_err_detector_bit_err_norm_valid",
+      desc: "Auto-extracted signal bit_err_norm_valid from bit_err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_filter_masked_input",
+      desc: "Auto-extracted signal masked_input from bit_filter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_filter_masked_value",
+      desc: "Auto-extracted signal masked_value from bit_filter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_sel_tseg1",
+      desc: "Auto-extracted signal sel_tseg1 from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_exp_seg_length_ce",
+      desc: "Auto-extracted signal exp_seg_length_ce from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_phase_err_mt_sjw",
+      desc: "Auto-extracted signal phase_err_mt_sjw from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_phase_err_eq_sjw",
+      desc: "Auto-extracted signal phase_err_eq_sjw from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_exit_ph2_immediate",
+      desc: "Auto-extracted signal exit_ph2_immediate from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_exit_segm_regular",
+      desc: "Auto-extracted signal exit_segm_regular from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_exit_segm_regular_tseg1",
+      desc: "Auto-extracted signal exit_segm_regular_tseg1 from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_exit_segm_regular_tseg2",
+      desc: "Auto-extracted signal exit_segm_regular_tseg2 from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_sjw_mt_zero",
+      desc: "Auto-extracted signal sjw_mt_zero from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_use_basic_segm_length",
+      desc: "Auto-extracted signal use_basic_segm_length from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_phase_err_sjw_by_one",
+      desc: "Auto-extracted signal phase_err_sjw_by_one from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_segment_meter_shorten_tseg1_after_tseg2",
+      desc: "Auto-extracted signal shorten_tseg1_after_tseg2 from bit_segment_meter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_data_out_i",
+      desc: "Auto-extracted signal data_out_i from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_data_halt_q",
+      desc: "Auto-extracted signal data_halt_q from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_data_halt_d",
+      desc: "Auto-extracted signal data_halt_d from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_fixed_reg_q",
+      desc: "Auto-extracted signal fixed_reg_q from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_fixed_reg_d",
+      desc: "Auto-extracted signal fixed_reg_d from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_enable_prev",
+      desc: "Auto-extracted signal enable_prev from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_non_fix_to_fix_chng",
+      desc: "Auto-extracted signal non_fix_to_fix_chng from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_stuff_lvl_reached",
+      desc: "Auto-extracted signal stuff_lvl_reached from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_same_bits_rst_trig",
+      desc: "Auto-extracted signal same_bits_rst_trig from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_same_bits_rst",
+      desc: "Auto-extracted signal same_bits_rst from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_insert_stuff_bit",
+      desc: "Auto-extracted signal insert_stuff_bit from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_data_out_d_ena",
+      desc: "Auto-extracted signal data_out_d_ena from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_data_out_d",
+      desc: "Auto-extracted signal data_out_d from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_stuffing_data_out_ce",
+      desc: "Auto-extracted signal data_out_ce from bit_stuffing.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_tq_nbt",
+      desc: "Auto-extracted signal drv_tq_nbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_prs_nbt",
+      desc: "Auto-extracted signal drv_prs_nbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_ph1_nbt",
+      desc: "Auto-extracted signal drv_ph1_nbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_ph2_nbt",
+      desc: "Auto-extracted signal drv_ph2_nbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_sjw_nbt",
+      desc: "Auto-extracted signal drv_sjw_nbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_tq_dbt",
+      desc: "Auto-extracted signal drv_tq_dbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_prs_dbt",
+      desc: "Auto-extracted signal drv_prs_dbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_ph1_dbt",
+      desc: "Auto-extracted signal drv_ph1_dbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_ph2_dbt",
+      desc: "Auto-extracted signal drv_ph2_dbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_sjw_dbt",
+      desc: "Auto-extracted signal drv_sjw_dbt from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_tseg1_nbt_d",
+      desc: "Auto-extracted signal tseg1_nbt_d from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_tseg1_dbt_d",
+      desc: "Auto-extracted signal tseg1_dbt_d from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_ena",
+      desc: "Auto-extracted signal drv_ena from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_ena_reg",
+      desc: "Auto-extracted signal drv_ena_reg from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_drv_ena_reg_2",
+      desc: "Auto-extracted signal drv_ena_reg_2 from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_cfg_capture_capture",
+      desc: "Auto-extracted signal capture from bit_time_cfg_capture.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_tq_counter_d",
+      desc: "Auto-extracted signal tq_counter_d from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_tq_counter_q",
+      desc: "Auto-extracted signal tq_counter_q from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_tq_counter_ce",
+      desc: "Auto-extracted signal tq_counter_ce from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_tq_counter_allow",
+      desc: "Auto-extracted signal tq_counter_allow from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_tq_edge_i",
+      desc: "Auto-extracted signal tq_edge_i from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_segm_counter_d",
+      desc: "Auto-extracted signal segm_counter_d from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_segm_counter_q",
+      desc: "Auto-extracted signal segm_counter_q from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_counters_segm_counter_ce",
+      desc: "Auto-extracted signal segm_counter_ce from bit_time_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bit_time_fsm_bt_fsm_ce",
+      desc: "Auto-extracted signal bt_fsm_ce from bit_time_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_drv_ena",
+      desc: "Auto-extracted signal drv_ena from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_drv_ssp_offset",
+      desc: "Auto-extracted signal drv_ssp_offset from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_drv_ssp_delay_select",
+      desc: "Auto-extracted signal drv_ssp_delay_select from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_data_rx_synced",
+      desc: "Auto-extracted signal data_rx_synced from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_prev_Sample",
+      desc: "Auto-extracted signal prev_Sample from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_sample_sec_i",
+      desc: "Auto-extracted signal sample_sec_i from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_data_tx_delayed",
+      desc: "Auto-extracted signal data_tx_delayed from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_edge_rx_valid",
+      desc: "Auto-extracted signal edge_rx_valid from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_edge_tx_valid",
+      desc: "Auto-extracted signal edge_tx_valid from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_ssp_delay",
+      desc: "Auto-extracted signal ssp_delay from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_tx_trigger_q",
+      desc: "Auto-extracted signal tx_trigger_q from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_tx_trigger_ssp",
+      desc: "Auto-extracted signal tx_trigger_ssp from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_shift_regs_res_d",
+      desc: "Auto-extracted signal shift_regs_res_d from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_shift_regs_res_q",
+      desc: "Auto-extracted signal shift_regs_res_q from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_shift_regs_res_q_scan",
+      desc: "Auto-extracted signal shift_regs_res_q_scan from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_sampling_ssp_enable",
+      desc: "Auto-extracted signal ssp_enable from bus_sampling.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_tx_ctr_i",
+      desc: "Auto-extracted signal tx_ctr_i from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_rx_ctr_i",
+      desc: "Auto-extracted signal rx_ctr_i from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_tx_ctr_rst_n_d",
+      desc: "Auto-extracted signal tx_ctr_rst_n_d from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_tx_ctr_rst_n_q",
+      desc: "Auto-extracted signal tx_ctr_rst_n_q from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_tx_ctr_rst_n_q_scan",
+      desc: "Auto-extracted signal tx_ctr_rst_n_q_scan from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_rx_ctr_rst_n_d",
+      desc: "Auto-extracted signal rx_ctr_rst_n_d from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_rx_ctr_rst_n_q",
+      desc: "Auto-extracted signal rx_ctr_rst_n_q from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "bus_traffic_counters_rx_ctr_rst_n_q_scan",
+      desc: "Auto-extracted signal rx_ctr_rst_n_q_scan from bus_traffic_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_paddr",
+      desc: "Auto-extracted signal s_apb_paddr from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_penable",
+      desc: "Auto-extracted signal s_apb_penable from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_pprot",
+      desc: "Auto-extracted signal s_apb_pprot from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_prdata",
+      desc: "Auto-extracted signal s_apb_prdata from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_pready",
+      desc: "Auto-extracted signal s_apb_pready from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_psel",
+      desc: "Auto-extracted signal s_apb_psel from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_pslverr",
+      desc: "Auto-extracted signal s_apb_pslverr from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_pstrb",
+      desc: "Auto-extracted signal s_apb_pstrb from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_pwdata",
+      desc: "Auto-extracted signal s_apb_pwdata from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_apb_tb_s_apb_pwrite",
+      desc: "Auto-extracted signal s_apb_pwrite from can_apb_tb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_drv_clr_rx_ctr",
+      desc: "Auto-extracted signal drv_clr_rx_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_drv_clr_tx_ctr",
+      desc: "Auto-extracted signal drv_clr_tx_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_drv_bus_mon_ena",
+      desc: "Auto-extracted signal drv_bus_mon_ena from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_drv_ena",
+      desc: "Auto-extracted signal drv_ena from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_ident_i",
+      desc: "Auto-extracted signal rec_ident_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_dlc_i",
+      desc: "Auto-extracted signal rec_dlc_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_ident_type_i",
+      desc: "Auto-extracted signal rec_ident_type_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_frame_type_i",
+      desc: "Auto-extracted signal rec_frame_type_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_is_rtr_i",
+      desc: "Auto-extracted signal rec_is_rtr_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_brs_i",
+      desc: "Auto-extracted signal rec_brs_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_esi_i",
+      desc: "Auto-extracted signal rec_esi_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_alc",
+      desc: "Auto-extracted signal alc from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_erc_capture",
+      desc: "Auto-extracted signal erc_capture from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_transmitter",
+      desc: "Auto-extracted signal is_transmitter from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_receiver",
+      desc: "Auto-extracted signal is_receiver from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_idle",
+      desc: "Auto-extracted signal is_idle from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_arbitration_lost_i",
+      desc: "Auto-extracted signal arbitration_lost_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_set_transmitter",
+      desc: "Auto-extracted signal set_transmitter from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_set_receiver",
+      desc: "Auto-extracted signal set_receiver from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_set_idle",
+      desc: "Auto-extracted signal set_idle from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_err_active",
+      desc: "Auto-extracted signal is_err_active from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_err_passive",
+      desc: "Auto-extracted signal is_err_passive from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_bus_off_i",
+      desc: "Auto-extracted signal is_bus_off_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_err_detected_i",
+      desc: "Auto-extracted signal err_detected_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_primary_err",
+      desc: "Auto-extracted signal primary_err from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_act_err_ovr_flag",
+      desc: "Auto-extracted signal act_err_ovr_flag from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_err_delim_late",
+      desc: "Auto-extracted signal err_delim_late from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_set_err_active",
+      desc: "Auto-extracted signal set_err_active from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_err_ctrs_unchanged",
+      desc: "Auto-extracted signal err_ctrs_unchanged from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_stuff_enable",
+      desc: "Auto-extracted signal stuff_enable from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_destuff_enable",
+      desc: "Auto-extracted signal destuff_enable from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_fixed_stuff",
+      desc: "Auto-extracted signal fixed_stuff from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_tx_frame_no_sof",
+      desc: "Auto-extracted signal tx_frame_no_sof from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_stuff_length",
+      desc: "Auto-extracted signal stuff_length from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_dst_ctr",
+      desc: "Auto-extracted signal dst_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bst_ctr",
+      desc: "Auto-extracted signal bst_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_stuff_err",
+      desc: "Auto-extracted signal stuff_err from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_enable",
+      desc: "Auto-extracted signal crc_enable from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_spec_enable",
+      desc: "Auto-extracted signal crc_spec_enable from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_calc_from_rx",
+      desc: "Auto-extracted signal crc_calc_from_rx from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_15",
+      desc: "Auto-extracted signal crc_15 from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_17",
+      desc: "Auto-extracted signal crc_17 from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_21",
+      desc: "Auto-extracted signal crc_21 from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_sp_control_i",
+      desc: "Auto-extracted signal sp_control_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_sp_control_q",
+      desc: "Auto-extracted signal sp_control_q from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_sync_control_i",
+      desc: "Auto-extracted signal sync_control_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_ssp_reset_i",
+      desc: "Auto-extracted signal ssp_reset_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_tran_delay_meas_i",
+      desc: "Auto-extracted signal tran_delay_meas_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_tran_valid_i",
+      desc: "Auto-extracted signal tran_valid_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rec_valid_i",
+      desc: "Auto-extracted signal rec_valid_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_br_shifted_i",
+      desc: "Auto-extracted signal br_shifted_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_fcs_changed_i",
+      desc: "Auto-extracted signal fcs_changed_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_err_warning_limit_i",
+      desc: "Auto-extracted signal err_warning_limit_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_tx_err_ctr",
+      desc: "Auto-extracted signal tx_err_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rx_err_ctr",
+      desc: "Auto-extracted signal rx_err_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_norm_err_ctr",
+      desc: "Auto-extracted signal norm_err_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_data_err_ctr",
+      desc: "Auto-extracted signal data_err_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_pc_tx_trigger",
+      desc: "Auto-extracted signal pc_tx_trigger from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_pc_rx_trigger",
+      desc: "Auto-extracted signal pc_rx_trigger from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_pc_tx_data_nbs",
+      desc: "Auto-extracted signal pc_tx_data_nbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_pc_rx_data_nbs",
+      desc: "Auto-extracted signal pc_rx_data_nbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_data_tx_wbs",
+      desc: "Auto-extracted signal crc_data_tx_wbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_data_tx_nbs",
+      desc: "Auto-extracted signal crc_data_tx_nbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_data_rx_wbs",
+      desc: "Auto-extracted signal crc_data_rx_wbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_data_rx_nbs",
+      desc: "Auto-extracted signal crc_data_rx_nbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_trig_tx_wbs",
+      desc: "Auto-extracted signal crc_trig_tx_wbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_trig_tx_nbs",
+      desc: "Auto-extracted signal crc_trig_tx_nbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_trig_rx_wbs",
+      desc: "Auto-extracted signal crc_trig_rx_wbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_trig_rx_nbs",
+      desc: "Auto-extracted signal crc_trig_rx_nbs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bst_data_in",
+      desc: "Auto-extracted signal bst_data_in from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bst_data_out",
+      desc: "Auto-extracted signal bst_data_out from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bst_trigger",
+      desc: "Auto-extracted signal bst_trigger from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_data_halt",
+      desc: "Auto-extracted signal data_halt from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bds_data_in",
+      desc: "Auto-extracted signal bds_data_in from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bds_data_out",
+      desc: "Auto-extracted signal bds_data_out from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bds_trigger",
+      desc: "Auto-extracted signal bds_trigger from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_destuffed",
+      desc: "Auto-extracted signal destuffed from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_tx_ctr",
+      desc: "Auto-extracted signal tx_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_rx_ctr",
+      desc: "Auto-extracted signal rx_ctr from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_tx_data_wbs_i",
+      desc: "Auto-extracted signal tx_data_wbs_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_lpb_dominant",
+      desc: "Auto-extracted signal lpb_dominant from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_form_err",
+      desc: "Auto-extracted signal form_err from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_ack_err",
+      desc: "Auto-extracted signal ack_err from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_crc_err",
+      desc: "Auto-extracted signal crc_err from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_arbitration",
+      desc: "Auto-extracted signal is_arbitration from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_control",
+      desc: "Auto-extracted signal is_control from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_data",
+      desc: "Auto-extracted signal is_data from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_stuff_count",
+      desc: "Auto-extracted signal is_stuff_count from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_crc",
+      desc: "Auto-extracted signal is_crc from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_crc_delim",
+      desc: "Auto-extracted signal is_crc_delim from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_ack_field",
+      desc: "Auto-extracted signal is_ack_field from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_ack_delim",
+      desc: "Auto-extracted signal is_ack_delim from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_eof",
+      desc: "Auto-extracted signal is_eof from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_err_frm",
+      desc: "Auto-extracted signal is_err_frm from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_intermission",
+      desc: "Auto-extracted signal is_intermission from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_suspend",
+      desc: "Auto-extracted signal is_suspend from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_overload_i",
+      desc: "Auto-extracted signal is_overload_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_sof",
+      desc: "Auto-extracted signal is_sof from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_sof_pulse_i",
+      desc: "Auto-extracted signal sof_pulse_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_load_init_vect",
+      desc: "Auto-extracted signal load_init_vect from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_retr_ctr_i",
+      desc: "Auto-extracted signal retr_ctr_i from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_decrement_rec",
+      desc: "Auto-extracted signal decrement_rec from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_bit_err_after_ack_err",
+      desc: "Auto-extracted signal bit_err_after_ack_err from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_core_is_pexs",
+      desc: "Auto-extracted signal is_pexs from can_core.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_drv_fd_type",
+      desc: "Auto-extracted signal drv_fd_type from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_init_vect_15",
+      desc: "Auto-extracted signal init_vect_15 from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_init_vect_17",
+      desc: "Auto-extracted signal init_vect_17 from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_init_vect_21",
+      desc: "Auto-extracted signal init_vect_21 from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_crc_17_21_data_in",
+      desc: "Auto-extracted signal crc_17_21_data_in from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_crc_17_21_trigger",
+      desc: "Auto-extracted signal crc_17_21_trigger from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_crc_15_data_in",
+      desc: "Auto-extracted signal crc_15_data_in from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_crc_15_trigger",
+      desc: "Auto-extracted signal crc_15_trigger from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_crc_ena_15",
+      desc: "Auto-extracted signal crc_ena_15 from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_crc_crc_ena_17_21",
+      desc: "Auto-extracted signal crc_ena_17_21 from can_crc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_ctu_can_data_in",
+      desc: "Auto-extracted signal ctu_can_data_in from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_ctu_can_data_out",
+      desc: "Auto-extracted signal ctu_can_data_out from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_ctu_can_adress",
+      desc: "Auto-extracted signal ctu_can_adress from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_ctu_can_scs",
+      desc: "Auto-extracted signal ctu_can_scs from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_ctu_can_srd",
+      desc: "Auto-extracted signal ctu_can_srd from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_ctu_can_swr",
+      desc: "Auto-extracted signal ctu_can_swr from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_ctu_can_sbe",
+      desc: "Auto-extracted signal ctu_can_sbe from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_ahb_res_n_out_i",
+      desc: "Auto-extracted signal res_n_out_i from can_top_ahb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_apb_reg_data_in",
+      desc: "Auto-extracted signal reg_data_in from can_top_apb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_apb_reg_data_out",
+      desc: "Auto-extracted signal reg_data_out from can_top_apb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_apb_reg_addr",
+      desc: "Auto-extracted signal reg_addr from can_top_apb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_apb_reg_be",
+      desc: "Auto-extracted signal reg_be from can_top_apb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_apb_reg_rden",
+      desc: "Auto-extracted signal reg_rden from can_top_apb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_apb_reg_wren",
+      desc: "Auto-extracted signal reg_wren from can_top_apb.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_drv_bus",
+      desc: "Auto-extracted signal drv_bus from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_stat_bus",
+      desc: "Auto-extracted signal stat_bus from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_res_n_sync",
+      desc: "Auto-extracted signal res_n_sync from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_res_core_n",
+      desc: "Auto-extracted signal res_core_n from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_res_soft_n",
+      desc: "Auto-extracted signal res_soft_n from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_sp_control",
+      desc: "Auto-extracted signal sp_control from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_buf_size",
+      desc: "Auto-extracted signal rx_buf_size from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_full",
+      desc: "Auto-extracted signal rx_full from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_empty",
+      desc: "Auto-extracted signal rx_empty from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_frame_count",
+      desc: "Auto-extracted signal rx_frame_count from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_mem_free",
+      desc: "Auto-extracted signal rx_mem_free from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_read_pointer",
+      desc: "Auto-extracted signal rx_read_pointer from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_write_pointer",
+      desc: "Auto-extracted signal rx_write_pointer from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_data_overrun",
+      desc: "Auto-extracted signal rx_data_overrun from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_read_buff",
+      desc: "Auto-extracted signal rx_read_buff from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_mof",
+      desc: "Auto-extracted signal rx_mof from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_port_a_data",
+      desc: "Auto-extracted signal txtb_port_a_data from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_port_a_address",
+      desc: "Auto-extracted signal txtb_port_a_address from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_port_a_cs",
+      desc: "Auto-extracted signal txtb_port_a_cs from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_port_a_be",
+      desc: "Auto-extracted signal txtb_port_a_be from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_sw_cmd_index",
+      desc: "Auto-extracted signal txtb_sw_cmd_index from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txt_buf_failed_bof",
+      desc: "Auto-extracted signal txt_buf_failed_bof from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_int_vector",
+      desc: "Auto-extracted signal int_vector from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_int_ena",
+      desc: "Auto-extracted signal int_ena from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_int_mask",
+      desc: "Auto-extracted signal int_mask from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_ident",
+      desc: "Auto-extracted signal rec_ident from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_dlc",
+      desc: "Auto-extracted signal rec_dlc from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_ident_type",
+      desc: "Auto-extracted signal rec_ident_type from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_frame_type",
+      desc: "Auto-extracted signal rec_frame_type from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_is_rtr",
+      desc: "Auto-extracted signal rec_is_rtr from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_brs",
+      desc: "Auto-extracted signal rec_brs from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_esi",
+      desc: "Auto-extracted signal rec_esi from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_store_data_word",
+      desc: "Auto-extracted signal store_data_word from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_sof_pulse",
+      desc: "Auto-extracted signal sof_pulse from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_store_metadata",
+      desc: "Auto-extracted signal store_metadata from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_store_data",
+      desc: "Auto-extracted signal store_data from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_valid",
+      desc: "Auto-extracted signal rec_valid from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_abort",
+      desc: "Auto-extracted signal rec_abort from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_store_metadata_f",
+      desc: "Auto-extracted signal store_metadata_f from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_store_data_f",
+      desc: "Auto-extracted signal store_data_f from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_valid_f",
+      desc: "Auto-extracted signal rec_valid_f from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rec_abort_f",
+      desc: "Auto-extracted signal rec_abort_f from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_hw_cmd_int",
+      desc: "Auto-extracted signal txtb_hw_cmd_int from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_is_bus_off",
+      desc: "Auto-extracted signal is_bus_off from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_available",
+      desc: "Auto-extracted signal txtb_available from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_port_b_clk_en",
+      desc: "Auto-extracted signal txtb_port_b_clk_en from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_dlc",
+      desc: "Auto-extracted signal tran_dlc from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_is_rtr",
+      desc: "Auto-extracted signal tran_is_rtr from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_ident_type",
+      desc: "Auto-extracted signal tran_ident_type from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_frame_type",
+      desc: "Auto-extracted signal tran_frame_type from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_brs",
+      desc: "Auto-extracted signal tran_brs from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_identifier",
+      desc: "Auto-extracted signal tran_identifier from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_word",
+      desc: "Auto-extracted signal tran_word from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_frame_valid",
+      desc: "Auto-extracted signal tran_frame_valid from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_changed",
+      desc: "Auto-extracted signal txtb_changed from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_txtb_clk_en",
+      desc: "Auto-extracted signal txtb_clk_en from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_err_detected",
+      desc: "Auto-extracted signal err_detected from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_fcs_changed",
+      desc: "Auto-extracted signal fcs_changed from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_err_warning_limit",
+      desc: "Auto-extracted signal err_warning_limit from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_arbitration_lost",
+      desc: "Auto-extracted signal arbitration_lost from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_valid",
+      desc: "Auto-extracted signal tran_valid from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_br_shifted",
+      desc: "Auto-extracted signal br_shifted from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_is_overload",
+      desc: "Auto-extracted signal is_overload from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_triggers",
+      desc: "Auto-extracted signal rx_triggers from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tx_trigger",
+      desc: "Auto-extracted signal tx_trigger from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_sync_control",
+      desc: "Auto-extracted signal sync_control from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_no_pos_resync",
+      desc: "Auto-extracted signal no_pos_resync from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_nbt_ctrs_en",
+      desc: "Auto-extracted signal nbt_ctrs_en from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_dbt_ctrs_en",
+      desc: "Auto-extracted signal dbt_ctrs_en from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_trv_delay",
+      desc: "Auto-extracted signal trv_delay from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_rx_data_wbs",
+      desc: "Auto-extracted signal rx_data_wbs from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tx_data_wbs",
+      desc: "Auto-extracted signal tx_data_wbs from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_ssp_reset",
+      desc: "Auto-extracted signal ssp_reset from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tran_delay_meas",
+      desc: "Auto-extracted signal tran_delay_meas from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_bit_err",
+      desc: "Auto-extracted signal bit_err from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_sample_sec",
+      desc: "Auto-extracted signal sample_sec from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_btmc_reset",
+      desc: "Auto-extracted signal btmc_reset from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_dbt_measure_start",
+      desc: "Auto-extracted signal dbt_measure_start from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_gen_first_ssp",
+      desc: "Auto-extracted signal gen_first_ssp from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_sync_edge",
+      desc: "Auto-extracted signal sync_edge from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tq_edge",
+      desc: "Auto-extracted signal tq_edge from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "can_top_level_tst_rdata_rx_buf",
+      desc: "Auto-extracted signal tst_rdata_rx_buf from can_top_level.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "clk_gate_clk_en_q",
+      desc: "Auto-extracted signal clk_en_q from clk_gate.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "control_counter_ctrl_ctr_ce",
+      desc: "Auto-extracted signal ctrl_ctr_ce from control_counter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "control_counter_compl_ctr_ce",
+      desc: "Auto-extracted signal compl_ctr_ce from control_counter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "control_registers_reg_map_reg_sel",
+      desc: "Auto-extracted signal reg_sel from control_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "control_registers_reg_map_read_data_mux_in",
+      desc: "Auto-extracted signal read_data_mux_in from control_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "control_registers_reg_map_read_data_mask_n",
+      desc: "Auto-extracted signal read_data_mask_n from control_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "control_registers_reg_map_read_mux_ena",
+      desc: "Auto-extracted signal read_mux_ena from control_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "crc_calc_crc_q",
+      desc: "Auto-extracted signal crc_q from crc_calc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "crc_calc_crc_nxt",
+      desc: "Auto-extracted signal crc_nxt from crc_calc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "crc_calc_crc_shift",
+      desc: "Auto-extracted signal crc_shift from crc_calc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "crc_calc_crc_shift_n_xor",
+      desc: "Auto-extracted signal crc_shift_n_xor from crc_calc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "crc_calc_crc_d",
+      desc: "Auto-extracted signal crc_d from crc_calc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "crc_calc_crc_ce",
+      desc: "Auto-extracted signal crc_ce from crc_calc.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_edge_detector_rx_data_prev",
+      desc: "Auto-extracted signal rx_data_prev from data_edge_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_edge_detector_tx_data_prev",
+      desc: "Auto-extracted signal tx_data_prev from data_edge_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_edge_detector_rx_data_sync_prev",
+      desc: "Auto-extracted signal rx_data_sync_prev from data_edge_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_edge_detector_rx_edge_i",
+      desc: "Auto-extracted signal rx_edge_i from data_edge_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_edge_detector_tx_edge_i",
+      desc: "Auto-extracted signal tx_edge_i from data_edge_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_mux_sel_data",
+      desc: "Auto-extracted signal sel_data from data_mux.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_mux_saturated_data",
+      desc: "Auto-extracted signal saturated_data from data_mux.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "data_mux_masked_data",
+      desc: "Auto-extracted signal masked_data from data_mux.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "dlc_decoder_data_len_8_to_64",
+      desc: "Auto-extracted signal data_len_8_to_64 from dlc_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "dlc_decoder_data_len_can_2_0",
+      desc: "Auto-extracted signal data_len_can_2_0 from dlc_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "dlc_decoder_data_len_can_fd",
+      desc: "Auto-extracted signal data_len_can_fd from dlc_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "endian_swapper_swapped",
+      desc: "Auto-extracted signal swapped from endian_swapper.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_tx_err_ctr_ce",
+      desc: "Auto-extracted signal tx_err_ctr_ce from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_rx_err_ctr_ce",
+      desc: "Auto-extracted signal rx_err_ctr_ce from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_modif_tx_ctr",
+      desc: "Auto-extracted signal modif_tx_ctr from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_modif_rx_ctr",
+      desc: "Auto-extracted signal modif_rx_ctr from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_nom_err_ctr_ce",
+      desc: "Auto-extracted signal nom_err_ctr_ce from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_data_err_ctr_ce",
+      desc: "Auto-extracted signal data_err_ctr_ce from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_res_err_ctrs_d",
+      desc: "Auto-extracted signal res_err_ctrs_d from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_res_err_ctrs_q",
+      desc: "Auto-extracted signal res_err_ctrs_q from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_counters_res_err_ctrs_q_scan",
+      desc: "Auto-extracted signal res_err_ctrs_q_scan from err_counters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_err_frm_req_i",
+      desc: "Auto-extracted signal err_frm_req_i from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_err_type_d",
+      desc: "Auto-extracted signal err_type_d from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_err_type_q",
+      desc: "Auto-extracted signal err_type_q from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_err_pos_q",
+      desc: "Auto-extracted signal err_pos_q from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_form_err_i",
+      desc: "Auto-extracted signal form_err_i from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_crc_match_c",
+      desc: "Auto-extracted signal crc_match_c from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_crc_match_d",
+      desc: "Auto-extracted signal crc_match_d from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_crc_match_q",
+      desc: "Auto-extracted signal crc_match_q from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_dst_ctr_grey",
+      desc: "Auto-extracted signal dst_ctr_grey from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_dst_parity",
+      desc: "Auto-extracted signal dst_parity from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_stuff_count_check",
+      desc: "Auto-extracted signal stuff_count_check from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_crc_15_ok",
+      desc: "Auto-extracted signal crc_15_ok from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_crc_17_ok",
+      desc: "Auto-extracted signal crc_17_ok from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_crc_21_ok",
+      desc: "Auto-extracted signal crc_21_ok from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_stuff_count_ok",
+      desc: "Auto-extracted signal stuff_count_ok from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_rx_crc_15",
+      desc: "Auto-extracted signal rx_crc_15 from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_rx_crc_17",
+      desc: "Auto-extracted signal rx_crc_17 from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "err_detector_rx_crc_21",
+      desc: "Auto-extracted signal rx_crc_21 from err_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_drv_ewl",
+      desc: "Auto-extracted signal drv_ewl from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_drv_erp",
+      desc: "Auto-extracted signal drv_erp from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_drv_ctr_val",
+      desc: "Auto-extracted signal drv_ctr_val from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_drv_ctr_sel",
+      desc: "Auto-extracted signal drv_ctr_sel from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_drv_ena",
+      desc: "Auto-extracted signal drv_ena from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_tx_err_ctr_i",
+      desc: "Auto-extracted signal tx_err_ctr_i from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_rx_err_ctr_i",
+      desc: "Auto-extracted signal rx_err_ctr_i from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_inc_one",
+      desc: "Auto-extracted signal inc_one from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_inc_eight",
+      desc: "Auto-extracted signal inc_eight from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_dec_one",
+      desc: "Auto-extracted signal dec_one from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_drv_rom_ena",
+      desc: "Auto-extracted signal drv_rom_ena from fault_confinement.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_tx_err_ctr_mt_erp",
+      desc: "Auto-extracted signal tx_err_ctr_mt_erp from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_rx_err_ctr_mt_erp",
+      desc: "Auto-extracted signal rx_err_ctr_mt_erp from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_tx_err_ctr_mt_ewl",
+      desc: "Auto-extracted signal tx_err_ctr_mt_ewl from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_rx_err_ctr_mt_ewl",
+      desc: "Auto-extracted signal rx_err_ctr_mt_ewl from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_tx_err_ctr_mt_255",
+      desc: "Auto-extracted signal tx_err_ctr_mt_255 from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_err_warning_limit_d",
+      desc: "Auto-extracted signal err_warning_limit_d from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_err_warning_limit_q",
+      desc: "Auto-extracted signal err_warning_limit_q from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_fc_fsm_res_d",
+      desc: "Auto-extracted signal fc_fsm_res_d from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_fsm_fc_fsm_res_q",
+      desc: "Auto-extracted signal fc_fsm_res_q from fault_confinement_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_rules_inc_one_i",
+      desc: "Auto-extracted signal inc_one_i from fault_confinement_rules.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "fault_confinement_rules_inc_eight_i",
+      desc: "Auto-extracted signal inc_eight_i from fault_confinement_rules.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_A_mask",
+      desc: "Auto-extracted signal drv_filter_A_mask from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_A_ctrl",
+      desc: "Auto-extracted signal drv_filter_A_ctrl from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_A_bits",
+      desc: "Auto-extracted signal drv_filter_A_bits from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_int_filter_A_valid",
+      desc: "Auto-extracted signal int_filter_A_valid from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_B_mask",
+      desc: "Auto-extracted signal drv_filter_B_mask from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_B_ctrl",
+      desc: "Auto-extracted signal drv_filter_B_ctrl from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_B_bits",
+      desc: "Auto-extracted signal drv_filter_B_bits from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_int_filter_B_valid",
+      desc: "Auto-extracted signal int_filter_B_valid from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_C_mask",
+      desc: "Auto-extracted signal drv_filter_C_mask from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_C_ctrl",
+      desc: "Auto-extracted signal drv_filter_C_ctrl from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_C_bits",
+      desc: "Auto-extracted signal drv_filter_C_bits from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_int_filter_C_valid",
+      desc: "Auto-extracted signal int_filter_C_valid from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_ran_ctrl",
+      desc: "Auto-extracted signal drv_filter_ran_ctrl from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_ran_lo_th",
+      desc: "Auto-extracted signal drv_filter_ran_lo_th from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filter_ran_hi_th",
+      desc: "Auto-extracted signal drv_filter_ran_hi_th from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_int_filter_ran_valid",
+      desc: "Auto-extracted signal int_filter_ran_valid from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_filters_ena",
+      desc: "Auto-extracted signal drv_filters_ena from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_int_data_type",
+      desc: "Auto-extracted signal int_data_type from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_int_data_ctrl",
+      desc: "Auto-extracted signal int_data_ctrl from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_filter_A_enable",
+      desc: "Auto-extracted signal filter_A_enable from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_filter_B_enable",
+      desc: "Auto-extracted signal filter_B_enable from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_filter_C_enable",
+      desc: "Auto-extracted signal filter_C_enable from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_filter_range_enable",
+      desc: "Auto-extracted signal filter_range_enable from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_filter_result",
+      desc: "Auto-extracted signal filter_result from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_ident_valid_d",
+      desc: "Auto-extracted signal ident_valid_d from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_ident_valid_q",
+      desc: "Auto-extracted signal ident_valid_q from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drv_drop_remote_frames",
+      desc: "Auto-extracted signal drv_drop_remote_frames from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "frame_filters_drop_rtr_frame",
+      desc: "Auto-extracted signal drop_rtr_frame from frame_filters.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "inf_ram_wrapper_int_read_data",
+      desc: "Auto-extracted signal int_read_data from inf_ram_wrapper.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "inf_ram_wrapper_byte_we",
+      desc: "Auto-extracted signal byte_we from inf_ram_wrapper.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_drv_int_vect_clr",
+      desc: "Auto-extracted signal drv_int_vect_clr from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_drv_int_ena_set",
+      desc: "Auto-extracted signal drv_int_ena_set from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_drv_int_ena_clr",
+      desc: "Auto-extracted signal drv_int_ena_clr from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_drv_int_mask_set",
+      desc: "Auto-extracted signal drv_int_mask_set from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_drv_int_mask_clr",
+      desc: "Auto-extracted signal drv_int_mask_clr from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_int_ena_i",
+      desc: "Auto-extracted signal int_ena_i from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_int_mask_i",
+      desc: "Auto-extracted signal int_mask_i from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_int_vect_i",
+      desc: "Auto-extracted signal int_vect_i from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_int_input_active",
+      desc: "Auto-extracted signal int_input_active from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_manager_int_i",
+      desc: "Auto-extracted signal int_i from int_manager.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_module_int_mask_i",
+      desc: "Auto-extracted signal int_mask_i from int_module.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_module_int_ena_i",
+      desc: "Auto-extracted signal int_ena_i from int_module.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_module_int_mask_load",
+      desc: "Auto-extracted signal int_mask_load from int_module.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "int_module_int_mask_next",
+      desc: "Auto-extracted signal int_mask_next from int_module.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_reg_reg_value_r",
+      desc: "Auto-extracted signal reg_value_r from memory_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_reg_wr_select",
+      desc: "Auto-extracted signal wr_select from memory_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_reg_wr_select_expanded",
+      desc: "Auto-extracted signal wr_select_expanded from memory_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_status_comb",
+      desc: "Auto-extracted signal status_comb from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_can_core_cs",
+      desc: "Auto-extracted signal can_core_cs from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_control_registers_cs",
+      desc: "Auto-extracted signal control_registers_cs from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_control_registers_cs_reg",
+      desc: "Auto-extracted signal control_registers_cs_reg from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_test_registers_cs",
+      desc: "Auto-extracted signal test_registers_cs from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_test_registers_cs_reg",
+      desc: "Auto-extracted signal test_registers_cs_reg from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_control_registers_rdata",
+      desc: "Auto-extracted signal control_registers_rdata from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_test_registers_rdata",
+      desc: "Auto-extracted signal test_registers_rdata from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_is_err_active",
+      desc: "Auto-extracted signal is_err_active from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_is_err_passive",
+      desc: "Auto-extracted signal is_err_passive from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_is_bus_off",
+      desc: "Auto-extracted signal is_bus_off from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_is_transmitter",
+      desc: "Auto-extracted signal is_transmitter from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_is_receiver",
+      desc: "Auto-extracted signal is_receiver from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_is_idle",
+      desc: "Auto-extracted signal is_idle from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_reg_lock_1_active",
+      desc: "Auto-extracted signal reg_lock_1_active from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_reg_lock_2_active",
+      desc: "Auto-extracted signal reg_lock_2_active from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_soft_res_q_n",
+      desc: "Auto-extracted signal soft_res_q_n from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_ewl_padded",
+      desc: "Auto-extracted signal ewl_padded from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_control_regs_clk_en",
+      desc: "Auto-extracted signal control_regs_clk_en from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_test_regs_clk_en",
+      desc: "Auto-extracted signal test_regs_clk_en from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_clk_control_regs",
+      desc: "Auto-extracted signal clk_control_regs from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_clk_test_regs",
+      desc: "Auto-extracted signal clk_test_regs from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_rx_buf_mode",
+      desc: "Auto-extracted signal rx_buf_mode from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_rx_move_cmd",
+      desc: "Auto-extracted signal rx_move_cmd from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "memory_registers_ctr_pres_sel_q",
+      desc: "Auto-extracted signal ctr_pres_sel_q from memory_registers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "operation_control_drv_ena",
+      desc: "Auto-extracted signal drv_ena from operation_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "operation_control_go_to_off",
+      desc: "Auto-extracted signal go_to_off from operation_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_drv_ena",
+      desc: "Auto-extracted signal drv_ena from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_tseg1_nbt",
+      desc: "Auto-extracted signal tseg1_nbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_tseg2_nbt",
+      desc: "Auto-extracted signal tseg2_nbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_brp_nbt",
+      desc: "Auto-extracted signal brp_nbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_sjw_nbt",
+      desc: "Auto-extracted signal sjw_nbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_tseg1_dbt",
+      desc: "Auto-extracted signal tseg1_dbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_tseg2_dbt",
+      desc: "Auto-extracted signal tseg2_dbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_brp_dbt",
+      desc: "Auto-extracted signal brp_dbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_sjw_dbt",
+      desc: "Auto-extracted signal sjw_dbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_segment_end",
+      desc: "Auto-extracted signal segment_end from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_h_sync_valid",
+      desc: "Auto-extracted signal h_sync_valid from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_is_tseg1",
+      desc: "Auto-extracted signal is_tseg1 from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_is_tseg2",
+      desc: "Auto-extracted signal is_tseg2 from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_resync_edge_valid",
+      desc: "Auto-extracted signal resync_edge_valid from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_h_sync_edge_valid",
+      desc: "Auto-extracted signal h_sync_edge_valid from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_segm_counter_nbt",
+      desc: "Auto-extracted signal segm_counter_nbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_segm_counter_dbt",
+      desc: "Auto-extracted signal segm_counter_dbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_exit_segm_req_nbt",
+      desc: "Auto-extracted signal exit_segm_req_nbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_exit_segm_req_dbt",
+      desc: "Auto-extracted signal exit_segm_req_dbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_tq_edge_nbt",
+      desc: "Auto-extracted signal tq_edge_nbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_tq_edge_dbt",
+      desc: "Auto-extracted signal tq_edge_dbt from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_rx_trig_req",
+      desc: "Auto-extracted signal rx_trig_req from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_tx_trig_req",
+      desc: "Auto-extracted signal tx_trig_req from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_start_edge",
+      desc: "Auto-extracted signal start_edge from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "prescaler_bt_ctr_clear",
+      desc: "Auto-extracted signal bt_ctr_clear from prescaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "priority_decoder_l0_valid",
+      desc: "Auto-extracted signal l0_valid from priority_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "priority_decoder_l1_valid",
+      desc: "Auto-extracted signal l1_valid from priority_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "priority_decoder_l1_winner",
+      desc: "Auto-extracted signal l1_winner from priority_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "priority_decoder_l2_valid",
+      desc: "Auto-extracted signal l2_valid from priority_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "priority_decoder_l2_winner",
+      desc: "Auto-extracted signal l2_winner from priority_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "priority_decoder_l3_valid",
+      desc: "Auto-extracted signal l3_valid from priority_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "priority_decoder_l3_winner",
+      desc: "Auto-extracted signal l3_winner from priority_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_can_fd_ena",
+      desc: "Auto-extracted signal drv_can_fd_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_bus_mon_ena",
+      desc: "Auto-extracted signal drv_bus_mon_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_retr_lim_ena",
+      desc: "Auto-extracted signal drv_retr_lim_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_retr_th",
+      desc: "Auto-extracted signal drv_retr_th from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_self_test_ena",
+      desc: "Auto-extracted signal drv_self_test_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_ack_forb",
+      desc: "Auto-extracted signal drv_ack_forb from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_ena",
+      desc: "Auto-extracted signal drv_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_fd_type",
+      desc: "Auto-extracted signal drv_fd_type from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_int_loopback_ena",
+      desc: "Auto-extracted signal drv_int_loopback_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_bus_off_reset",
+      desc: "Auto-extracted signal drv_bus_off_reset from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_ssp_delay_select",
+      desc: "Auto-extracted signal drv_ssp_delay_select from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_pex",
+      desc: "Auto-extracted signal drv_pex from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_cpexs",
+      desc: "Auto-extracted signal drv_cpexs from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tran_word_swapped",
+      desc: "Auto-extracted signal tran_word_swapped from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_err_frm_req",
+      desc: "Auto-extracted signal err_frm_req from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_load_base_id",
+      desc: "Auto-extracted signal tx_load_base_id from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_load_ext_id",
+      desc: "Auto-extracted signal tx_load_ext_id from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_load_dlc",
+      desc: "Auto-extracted signal tx_load_dlc from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_load_data_word",
+      desc: "Auto-extracted signal tx_load_data_word from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_load_stuff_count",
+      desc: "Auto-extracted signal tx_load_stuff_count from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_load_crc",
+      desc: "Auto-extracted signal tx_load_crc from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_shift_ena",
+      desc: "Auto-extracted signal tx_shift_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_dominant",
+      desc: "Auto-extracted signal tx_dominant from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_clear",
+      desc: "Auto-extracted signal rx_clear from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_base_id",
+      desc: "Auto-extracted signal rx_store_base_id from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_ext_id",
+      desc: "Auto-extracted signal rx_store_ext_id from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_ide",
+      desc: "Auto-extracted signal rx_store_ide from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_rtr",
+      desc: "Auto-extracted signal rx_store_rtr from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_edl",
+      desc: "Auto-extracted signal rx_store_edl from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_dlc",
+      desc: "Auto-extracted signal rx_store_dlc from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_esi",
+      desc: "Auto-extracted signal rx_store_esi from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_brs",
+      desc: "Auto-extracted signal rx_store_brs from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_store_stuff_count",
+      desc: "Auto-extracted signal rx_store_stuff_count from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_shift_ena",
+      desc: "Auto-extracted signal rx_shift_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_shift_in_sel",
+      desc: "Auto-extracted signal rx_shift_in_sel from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rec_is_rtr_i",
+      desc: "Auto-extracted signal rec_is_rtr_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rec_dlc_d",
+      desc: "Auto-extracted signal rec_dlc_d from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rec_dlc_q",
+      desc: "Auto-extracted signal rec_dlc_q from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rec_frame_type_i",
+      desc: "Auto-extracted signal rec_frame_type_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_ctr_pload",
+      desc: "Auto-extracted signal ctrl_ctr_pload from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_ctr_pload_val",
+      desc: "Auto-extracted signal ctrl_ctr_pload_val from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_ctr_ena",
+      desc: "Auto-extracted signal ctrl_ctr_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_ctr_zero",
+      desc: "Auto-extracted signal ctrl_ctr_zero from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_ctr_one",
+      desc: "Auto-extracted signal ctrl_ctr_one from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_counted_byte",
+      desc: "Auto-extracted signal ctrl_counted_byte from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_counted_byte_index",
+      desc: "Auto-extracted signal ctrl_counted_byte_index from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ctrl_ctr_mem_index",
+      desc: "Auto-extracted signal ctrl_ctr_mem_index from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_compl_ctr_ena",
+      desc: "Auto-extracted signal compl_ctr_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_reinteg_ctr_clr",
+      desc: "Auto-extracted signal reinteg_ctr_clr from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_reinteg_ctr_enable",
+      desc: "Auto-extracted signal reinteg_ctr_enable from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_reinteg_ctr_expired",
+      desc: "Auto-extracted signal reinteg_ctr_expired from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_retr_ctr_clear",
+      desc: "Auto-extracted signal retr_ctr_clear from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_retr_ctr_add",
+      desc: "Auto-extracted signal retr_ctr_add from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_retr_limit_reached",
+      desc: "Auto-extracted signal retr_limit_reached from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_form_err_i",
+      desc: "Auto-extracted signal form_err_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_ack_err_i",
+      desc: "Auto-extracted signal ack_err_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_crc_check",
+      desc: "Auto-extracted signal crc_check from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_bit_err_arb",
+      desc: "Auto-extracted signal bit_err_arb from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_crc_match",
+      desc: "Auto-extracted signal crc_match from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_crc_err_i",
+      desc: "Auto-extracted signal crc_err_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_crc_clear_match_flag",
+      desc: "Auto-extracted signal crc_clear_match_flag from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_crc_src",
+      desc: "Auto-extracted signal crc_src from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_err_pos",
+      desc: "Auto-extracted signal err_pos from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_is_arbitration_i",
+      desc: "Auto-extracted signal is_arbitration_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_bit_err_enable",
+      desc: "Auto-extracted signal bit_err_enable from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_tx_data_nbs_i",
+      desc: "Auto-extracted signal tx_data_nbs_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_crc",
+      desc: "Auto-extracted signal rx_crc from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_rx_stuff_count",
+      desc: "Auto-extracted signal rx_stuff_count from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fixed_stuff_i",
+      desc: "Auto-extracted signal fixed_stuff_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_arbitration_lost_i",
+      desc: "Auto-extracted signal arbitration_lost_i from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_alc_id_field",
+      desc: "Auto-extracted signal alc_id_field from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_drv_rom_ena",
+      desc: "Auto-extracted signal drv_rom_ena from protocol_control.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_state_reg_ce",
+      desc: "Auto-extracted signal state_reg_ce from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_no_data_transmitter",
+      desc: "Auto-extracted signal no_data_transmitter from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_no_data_receiver",
+      desc: "Auto-extracted signal no_data_receiver from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_no_data_field",
+      desc: "Auto-extracted signal no_data_field from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ctrl_ctr_pload_i",
+      desc: "Auto-extracted signal ctrl_ctr_pload_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ctrl_ctr_pload_unaliged",
+      desc: "Auto-extracted signal ctrl_ctr_pload_unaliged from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_crc_use_21",
+      desc: "Auto-extracted signal crc_use_21 from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_crc_use_17",
+      desc: "Auto-extracted signal crc_use_17 from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_crc_src_i",
+      desc: "Auto-extracted signal crc_src_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_crc_length_i",
+      desc: "Auto-extracted signal crc_length_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tran_data_length",
+      desc: "Auto-extracted signal tran_data_length from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rec_data_length",
+      desc: "Auto-extracted signal rec_data_length from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rec_data_length_c",
+      desc: "Auto-extracted signal rec_data_length_c from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_data_length_c",
+      desc: "Auto-extracted signal data_length_c from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_data_length_shifted_c",
+      desc: "Auto-extracted signal data_length_shifted_c from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_data_length_bits_c",
+      desc: "Auto-extracted signal data_length_bits_c from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_is_fd_frame",
+      desc: "Auto-extracted signal is_fd_frame from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_frame_start",
+      desc: "Auto-extracted signal frame_start from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_frame_ready",
+      desc: "Auto-extracted signal tx_frame_ready from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ide_is_arbitration",
+      desc: "Auto-extracted signal ide_is_arbitration from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_arbitration_lost_condition",
+      desc: "Auto-extracted signal arbitration_lost_condition from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_arbitration_lost_i",
+      desc: "Auto-extracted signal arbitration_lost_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_failed",
+      desc: "Auto-extracted signal tx_failed from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_store_metadata_d",
+      desc: "Auto-extracted signal store_metadata_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_store_data_d",
+      desc: "Auto-extracted signal store_data_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rec_valid_d",
+      desc: "Auto-extracted signal rec_valid_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rec_abort_d",
+      desc: "Auto-extracted signal rec_abort_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_go_to_suspend",
+      desc: "Auto-extracted signal go_to_suspend from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_go_to_stuff_count",
+      desc: "Auto-extracted signal go_to_stuff_count from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_base_id_i",
+      desc: "Auto-extracted signal rx_store_base_id_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_ext_id_i",
+      desc: "Auto-extracted signal rx_store_ext_id_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_ide_i",
+      desc: "Auto-extracted signal rx_store_ide_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_rtr_i",
+      desc: "Auto-extracted signal rx_store_rtr_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_edl_i",
+      desc: "Auto-extracted signal rx_store_edl_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_dlc_i",
+      desc: "Auto-extracted signal rx_store_dlc_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_esi_i",
+      desc: "Auto-extracted signal rx_store_esi_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_brs_i",
+      desc: "Auto-extracted signal rx_store_brs_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_store_stuff_count_i",
+      desc: "Auto-extracted signal rx_store_stuff_count_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_clear_i",
+      desc: "Auto-extracted signal rx_clear_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_load_base_id_i",
+      desc: "Auto-extracted signal tx_load_base_id_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_load_ext_id_i",
+      desc: "Auto-extracted signal tx_load_ext_id_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_load_dlc_i",
+      desc: "Auto-extracted signal tx_load_dlc_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_load_data_word_i",
+      desc: "Auto-extracted signal tx_load_data_word_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_load_stuff_count_i",
+      desc: "Auto-extracted signal tx_load_stuff_count_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_load_crc_i",
+      desc: "Auto-extracted signal tx_load_crc_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_shift_ena_i",
+      desc: "Auto-extracted signal tx_shift_ena_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_form_err_i",
+      desc: "Auto-extracted signal form_err_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ack_err_i",
+      desc: "Auto-extracted signal ack_err_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ack_err_flag",
+      desc: "Auto-extracted signal ack_err_flag from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ack_err_flag_clr",
+      desc: "Auto-extracted signal ack_err_flag_clr from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_crc_err_i",
+      desc: "Auto-extracted signal crc_err_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_bit_err_arb_i",
+      desc: "Auto-extracted signal bit_err_arb_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sp_control_switch_data",
+      desc: "Auto-extracted signal sp_control_switch_data from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sp_control_switch_nominal",
+      desc: "Auto-extracted signal sp_control_switch_nominal from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_switch_to_ssp",
+      desc: "Auto-extracted signal switch_to_ssp from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sp_control_ce",
+      desc: "Auto-extracted signal sp_control_ce from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sp_control_d",
+      desc: "Auto-extracted signal sp_control_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sp_control_q_i",
+      desc: "Auto-extracted signal sp_control_q_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ssp_reset_i",
+      desc: "Auto-extracted signal ssp_reset_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sync_control_d",
+      desc: "Auto-extracted signal sync_control_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sync_control_q",
+      desc: "Auto-extracted signal sync_control_q from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_perform_hsync",
+      desc: "Auto-extracted signal perform_hsync from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_primary_err_i",
+      desc: "Auto-extracted signal primary_err_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_err_delim_late_i",
+      desc: "Auto-extracted signal err_delim_late_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_set_err_active_i",
+      desc: "Auto-extracted signal set_err_active_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_set_transmitter_i",
+      desc: "Auto-extracted signal set_transmitter_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_set_receiver_i",
+      desc: "Auto-extracted signal set_receiver_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_set_idle_i",
+      desc: "Auto-extracted signal set_idle_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_first_err_delim_d",
+      desc: "Auto-extracted signal first_err_delim_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_first_err_delim_q",
+      desc: "Auto-extracted signal first_err_delim_q from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_stuff_enable_set",
+      desc: "Auto-extracted signal stuff_enable_set from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_stuff_enable_clear",
+      desc: "Auto-extracted signal stuff_enable_clear from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_destuff_enable_set",
+      desc: "Auto-extracted signal destuff_enable_set from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_destuff_enable_clear",
+      desc: "Auto-extracted signal destuff_enable_clear from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_bit_err_disable",
+      desc: "Auto-extracted signal bit_err_disable from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_bit_err_disable_receiver",
+      desc: "Auto-extracted signal bit_err_disable_receiver from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_sof_pulse_i",
+      desc: "Auto-extracted signal sof_pulse_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_compl_ctr_ena_i",
+      desc: "Auto-extracted signal compl_ctr_ena_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tick_state_reg",
+      desc: "Auto-extracted signal tick_state_reg from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_br_shifted_i",
+      desc: "Auto-extracted signal br_shifted_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_is_arbitration_i",
+      desc: "Auto-extracted signal is_arbitration_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_crc_spec_enable_i",
+      desc: "Auto-extracted signal crc_spec_enable_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_load_init_vect_i",
+      desc: "Auto-extracted signal load_init_vect_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_drv_bus_off_reset_q",
+      desc: "Auto-extracted signal drv_bus_off_reset_q from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_retr_ctr_clear_i",
+      desc: "Auto-extracted signal retr_ctr_clear_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_retr_ctr_add_i",
+      desc: "Auto-extracted signal retr_ctr_add_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_decrement_rec_i",
+      desc: "Auto-extracted signal decrement_rec_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_retr_ctr_add_block",
+      desc: "Auto-extracted signal retr_ctr_add_block from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_retr_ctr_add_block_clr",
+      desc: "Auto-extracted signal retr_ctr_add_block_clr from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_block_txtb_unlock",
+      desc: "Auto-extracted signal block_txtb_unlock from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_frame_no_sof_d",
+      desc: "Auto-extracted signal tx_frame_no_sof_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tx_frame_no_sof_q",
+      desc: "Auto-extracted signal tx_frame_no_sof_q from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_ctrl_signal_upd",
+      desc: "Auto-extracted signal ctrl_signal_upd from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_clr_bus_off_rst_flg",
+      desc: "Auto-extracted signal clr_bus_off_rst_flg from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_pex_on_fdf_enable",
+      desc: "Auto-extracted signal pex_on_fdf_enable from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_pex_on_res_enable",
+      desc: "Auto-extracted signal pex_on_res_enable from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_rx_data_nbs_prev",
+      desc: "Auto-extracted signal rx_data_nbs_prev from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_pexs_set",
+      desc: "Auto-extracted signal pexs_set from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_tran_frame_type_i",
+      desc: "Auto-extracted signal tran_frame_type_i from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_txtb_clk_en_d",
+      desc: "Auto-extracted signal txtb_clk_en_d from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "protocol_control_fsm_txtb_clk_en_q",
+      desc: "Auto-extracted signal txtb_clk_en_q from protocol_control_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "reintegration_counter_reinteg_ctr_ce",
+      desc: "Auto-extracted signal reinteg_ctr_ce from reintegration_counter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "retransmitt_counter_retr_ctr_ce",
+      desc: "Auto-extracted signal retr_ctr_ce from retransmitt_counter.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rst_sync_rff",
+      desc: "Auto-extracted signal rff from rst_sync.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_drv_erase_rx",
+      desc: "Auto-extracted signal drv_erase_rx from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_drv_read_start",
+      desc: "Auto-extracted signal drv_read_start from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_drv_clr_ovr",
+      desc: "Auto-extracted signal drv_clr_ovr from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_drv_rtsopt",
+      desc: "Auto-extracted signal drv_rtsopt from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_read_pointer",
+      desc: "Auto-extracted signal read_pointer from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_read_pointer_inc_1",
+      desc: "Auto-extracted signal read_pointer_inc_1 from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_write_pointer",
+      desc: "Auto-extracted signal write_pointer from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_write_pointer_raw",
+      desc: "Auto-extracted signal write_pointer_raw from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_write_pointer_ts",
+      desc: "Auto-extracted signal write_pointer_ts from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_rx_mem_free_i",
+      desc: "Auto-extracted signal rx_mem_free_i from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_memory_write_data",
+      desc: "Auto-extracted signal memory_write_data from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_data_overrun_flg",
+      desc: "Auto-extracted signal data_overrun_flg from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_data_overrun_i",
+      desc: "Auto-extracted signal data_overrun_i from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_overrun_condition",
+      desc: "Auto-extracted signal overrun_condition from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_rx_empty_i",
+      desc: "Auto-extracted signal rx_empty_i from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_is_free_word",
+      desc: "Auto-extracted signal is_free_word from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_commit_rx_frame",
+      desc: "Auto-extracted signal commit_rx_frame from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_commit_overrun_abort",
+      desc: "Auto-extracted signal commit_overrun_abort from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_read_increment",
+      desc: "Auto-extracted signal read_increment from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_write_raw_OK",
+      desc: "Auto-extracted signal write_raw_OK from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_write_raw_intent",
+      desc: "Auto-extracted signal write_raw_intent from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_write_ts",
+      desc: "Auto-extracted signal write_ts from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_stored_ts",
+      desc: "Auto-extracted signal stored_ts from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_data_selector",
+      desc: "Auto-extracted signal data_selector from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_store_ts_wr_ptr",
+      desc: "Auto-extracted signal store_ts_wr_ptr from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_inc_ts_wr_ptr",
+      desc: "Auto-extracted signal inc_ts_wr_ptr from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_reset_overrun_flag",
+      desc: "Auto-extracted signal reset_overrun_flag from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_frame_form_w",
+      desc: "Auto-extracted signal frame_form_w from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_timestamp_capture",
+      desc: "Auto-extracted signal timestamp_capture from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_timestamp_capture_ce",
+      desc: "Auto-extracted signal timestamp_capture_ce from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_RAM_write",
+      desc: "Auto-extracted signal RAM_write from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_RAM_data_out",
+      desc: "Auto-extracted signal RAM_data_out from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_RAM_write_address",
+      desc: "Auto-extracted signal RAM_write_address from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_RAM_read_address",
+      desc: "Auto-extracted signal RAM_read_address from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_rx_buf_res_n_d",
+      desc: "Auto-extracted signal rx_buf_res_n_d from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_rx_buf_res_n_q",
+      desc: "Auto-extracted signal rx_buf_res_n_q from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_rx_buf_res_n_q_scan",
+      desc: "Auto-extracted signal rx_buf_res_n_q_scan from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_rx_buf_ram_clk_en",
+      desc: "Auto-extracted signal rx_buf_ram_clk_en from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_clk_ram",
+      desc: "Auto-extracted signal clk_ram from rx_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_fsm_rx_fsm_ce",
+      desc: "Auto-extracted signal rx_fsm_ce from rx_buffer_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_fsm_cmd_join",
+      desc: "Auto-extracted signal cmd_join from rx_buffer_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_pointers_write_pointer_raw_ce",
+      desc: "Auto-extracted signal write_pointer_raw_ce from rx_buffer_pointers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_pointers_write_pointer_ts_ce",
+      desc: "Auto-extracted signal write_pointer_ts_ce from rx_buffer_pointers.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_ram_port_a_address_i",
+      desc: "Auto-extracted signal port_a_address_i from rx_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_ram_port_a_write_i",
+      desc: "Auto-extracted signal port_a_write_i from rx_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_ram_port_a_data_in_i",
+      desc: "Auto-extracted signal port_a_data_in_i from rx_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_ram_port_b_address_i",
+      desc: "Auto-extracted signal port_b_address_i from rx_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_ram_port_b_data_out_i",
+      desc: "Auto-extracted signal port_b_data_out_i from rx_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_ram_tst_ena",
+      desc: "Auto-extracted signal tst_ena from rx_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_buffer_ram_tst_addr",
+      desc: "Auto-extracted signal tst_addr from rx_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_res_n_i_d",
+      desc: "Auto-extracted signal res_n_i_d from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_res_n_i_q",
+      desc: "Auto-extracted signal res_n_i_q from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_res_n_i_q_scan",
+      desc: "Auto-extracted signal res_n_i_q_scan from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_rx_shift_reg_q",
+      desc: "Auto-extracted signal rx_shift_reg_q from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_rx_shift_cmd",
+      desc: "Auto-extracted signal rx_shift_cmd from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_rx_shift_in_sel_demuxed",
+      desc: "Auto-extracted signal rx_shift_in_sel_demuxed from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_rec_is_rtr_i",
+      desc: "Auto-extracted signal rec_is_rtr_i from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "rx_shift_reg_rec_frame_type_i",
+      desc: "Auto-extracted signal rec_frame_type_i from rx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "sample_mux_sample",
+      desc: "Auto-extracted signal sample from sample_mux.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "sample_mux_prev_sample_d",
+      desc: "Auto-extracted signal prev_sample_d from sample_mux.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "sample_mux_prev_sample_q",
+      desc: "Auto-extracted signal prev_sample_q from sample_mux.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_req_input",
+      desc: "Auto-extracted signal req_input from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_req_capt_d",
+      desc: "Auto-extracted signal segm_end_req_capt_d from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_req_capt_q",
+      desc: "Auto-extracted signal segm_end_req_capt_q from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_req_capt_ce",
+      desc: "Auto-extracted signal segm_end_req_capt_ce from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_req_capt_clr",
+      desc: "Auto-extracted signal segm_end_req_capt_clr from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_req_capt_dq",
+      desc: "Auto-extracted signal segm_end_req_capt_dq from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_nbt_valid",
+      desc: "Auto-extracted signal segm_end_nbt_valid from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_dbt_valid",
+      desc: "Auto-extracted signal segm_end_dbt_valid from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segm_end_nbt_dbt_valid",
+      desc: "Auto-extracted signal segm_end_nbt_dbt_valid from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_tseg1_end_req_valid",
+      desc: "Auto-extracted signal tseg1_end_req_valid from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_tseg2_end_req_valid",
+      desc: "Auto-extracted signal tseg2_end_req_valid from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_h_sync_valid_i",
+      desc: "Auto-extracted signal h_sync_valid_i from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_segment_end_i",
+      desc: "Auto-extracted signal segment_end_i from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_nbt_tq_active",
+      desc: "Auto-extracted signal nbt_tq_active from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_dbt_tq_active",
+      desc: "Auto-extracted signal dbt_tq_active from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "segment_end_detector_bt_ctr_clear_i",
+      desc: "Auto-extracted signal bt_ctr_clear_i from segment_end_detector.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "shift_reg_shift_regs",
+      desc: "Auto-extracted signal shift_regs from shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "shift_reg_next_shift_reg_val",
+      desc: "Auto-extracted signal next_shift_reg_val from shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "shift_reg_byte_shift_reg_in",
+      desc: "Auto-extracted signal shift_reg_in from shift_reg_byte.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "shift_reg_preload_shift_regs",
+      desc: "Auto-extracted signal shift_regs from shift_reg_preload.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "shift_reg_preload_next_shift_reg_val",
+      desc: "Auto-extracted signal next_shift_reg_val from shift_reg_preload.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "sig_sync_rff",
+      desc: "Auto-extracted signal rff from sig_sync.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_btmc_d",
+      desc: "Auto-extracted signal btmc_d from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_btmc_q",
+      desc: "Auto-extracted signal btmc_q from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_btmc_add",
+      desc: "Auto-extracted signal btmc_add from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_btmc_ce",
+      desc: "Auto-extracted signal btmc_ce from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_btmc_meas_running_d",
+      desc: "Auto-extracted signal btmc_meas_running_d from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_btmc_meas_running_q",
+      desc: "Auto-extracted signal btmc_meas_running_q from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_d",
+      desc: "Auto-extracted signal sspc_d from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_q",
+      desc: "Auto-extracted signal sspc_q from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_ce",
+      desc: "Auto-extracted signal sspc_ce from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_expired",
+      desc: "Auto-extracted signal sspc_expired from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_threshold",
+      desc: "Auto-extracted signal sspc_threshold from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_add",
+      desc: "Auto-extracted signal sspc_add from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_first_ssp_d",
+      desc: "Auto-extracted signal first_ssp_d from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_first_ssp_q",
+      desc: "Auto-extracted signal first_ssp_q from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_ena_d",
+      desc: "Auto-extracted signal sspc_ena_d from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_sspc_ena_q",
+      desc: "Auto-extracted signal sspc_ena_q from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "ssp_generator_ssp_delay_padded",
+      desc: "Auto-extracted signal ssp_delay_padded from ssp_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "synchronisation_checker_resync_edge",
+      desc: "Auto-extracted signal resync_edge from synchronisation_checker.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "synchronisation_checker_h_sync_edge",
+      desc: "Auto-extracted signal h_sync_edge from synchronisation_checker.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "synchronisation_checker_h_or_re_sync_edge",
+      desc: "Auto-extracted signal h_or_re_sync_edge from synchronisation_checker.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "synchronisation_checker_sync_flag",
+      desc: "Auto-extracted signal sync_flag from synchronisation_checker.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "synchronisation_checker_sync_flag_ce",
+      desc: "Auto-extracted signal sync_flag_ce from synchronisation_checker.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "synchronisation_checker_sync_flag_nxt",
+      desc: "Auto-extracted signal sync_flag_nxt from synchronisation_checker.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "test_registers_reg_map_reg_sel",
+      desc: "Auto-extracted signal reg_sel from test_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "test_registers_reg_map_read_data_mux_in",
+      desc: "Auto-extracted signal read_data_mux_in from test_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "test_registers_reg_map_read_data_mask_n",
+      desc: "Auto-extracted signal read_data_mask_n from test_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "test_registers_reg_map_read_mux_ena",
+      desc: "Auto-extracted signal read_mux_ena from test_registers_reg_map.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trigger_generator_rx_trig_req_q",
+      desc: "Auto-extracted signal rx_trig_req_q from trigger_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trigger_generator_tx_trig_req_flag_d",
+      desc: "Auto-extracted signal tx_trig_req_flag_d from trigger_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trigger_generator_tx_trig_req_flag_q",
+      desc: "Auto-extracted signal tx_trig_req_flag_q from trigger_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trigger_generator_tx_trig_req_flag_dq",
+      desc: "Auto-extracted signal tx_trig_req_flag_dq from trigger_generator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trigger_mux_tx_trigger_q",
+      desc: "Auto-extracted signal tx_trigger_q from trigger_mux.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_meas_progress_d",
+      desc: "Auto-extracted signal trv_meas_progress_d from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_meas_progress_q",
+      desc: "Auto-extracted signal trv_meas_progress_q from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_meas_progress_del",
+      desc: "Auto-extracted signal trv_meas_progress_del from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_ctr_q",
+      desc: "Auto-extracted signal trv_delay_ctr_q from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_ctr_d",
+      desc: "Auto-extracted signal trv_delay_ctr_d from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_ctr_add",
+      desc: "Auto-extracted signal trv_delay_ctr_add from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_ctr_q_padded",
+      desc: "Auto-extracted signal trv_delay_ctr_q_padded from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_ctr_rst_d",
+      desc: "Auto-extracted signal trv_delay_ctr_rst_d from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_ctr_rst_q",
+      desc: "Auto-extracted signal trv_delay_ctr_rst_q from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_ctr_rst_q_scan",
+      desc: "Auto-extracted signal trv_delay_ctr_rst_q_scan from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_ssp_shadow_ce",
+      desc: "Auto-extracted signal ssp_shadow_ce from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_ssp_delay_raw",
+      desc: "Auto-extracted signal ssp_delay_raw from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_ssp_delay_saturated",
+      desc: "Auto-extracted signal ssp_delay_saturated from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "trv_delay_meas_trv_delay_sum",
+      desc: "Auto-extracted signal trv_delay_sum from trv_delay_meas.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_select_buf_avail",
+      desc: "Auto-extracted signal select_buf_avail from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_txtb_selected_input",
+      desc: "Auto-extracted signal txtb_selected_input from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_txtb_timestamp",
+      desc: "Auto-extracted signal txtb_timestamp from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_timestamp_valid",
+      desc: "Auto-extracted signal timestamp_valid from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_select_index_changed",
+      desc: "Auto-extracted signal select_index_changed from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_validated_buffer",
+      desc: "Auto-extracted signal validated_buffer from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_ts_low_internal",
+      desc: "Auto-extracted signal ts_low_internal from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_dlc_dbl_buf",
+      desc: "Auto-extracted signal tran_dlc_dbl_buf from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_is_rtr_dbl_buf",
+      desc: "Auto-extracted signal tran_is_rtr_dbl_buf from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_ident_type_dbl_buf",
+      desc: "Auto-extracted signal tran_ident_type_dbl_buf from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_frame_type_dbl_buf",
+      desc: "Auto-extracted signal tran_frame_type_dbl_buf from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_brs_dbl_buf",
+      desc: "Auto-extracted signal tran_brs_dbl_buf from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_dlc_com",
+      desc: "Auto-extracted signal tran_dlc_com from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_is_rtr_com",
+      desc: "Auto-extracted signal tran_is_rtr_com from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_ident_type_com",
+      desc: "Auto-extracted signal tran_ident_type_com from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_frame_type_com",
+      desc: "Auto-extracted signal tran_frame_type_com from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_brs_com",
+      desc: "Auto-extracted signal tran_brs_com from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_frame_valid_com",
+      desc: "Auto-extracted signal tran_frame_valid_com from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tran_identifier_com",
+      desc: "Auto-extracted signal tran_identifier_com from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_load_ts_lw_addr",
+      desc: "Auto-extracted signal load_ts_lw_addr from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_load_ts_uw_addr",
+      desc: "Auto-extracted signal load_ts_uw_addr from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_load_ffmt_w_addr",
+      desc: "Auto-extracted signal load_ffmt_w_addr from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_load_ident_w_addr",
+      desc: "Auto-extracted signal load_ident_w_addr from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_store_ts_l_w",
+      desc: "Auto-extracted signal store_ts_l_w from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_store_md_w",
+      desc: "Auto-extracted signal store_md_w from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_store_ident_w",
+      desc: "Auto-extracted signal store_ident_w from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_buffer_md_w",
+      desc: "Auto-extracted signal buffer_md_w from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_store_last_txtb_index",
+      desc: "Auto-extracted signal store_last_txtb_index from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_frame_valid_com_set",
+      desc: "Auto-extracted signal frame_valid_com_set from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_frame_valid_com_clear",
+      desc: "Auto-extracted signal frame_valid_com_clear from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_tx_arb_locked",
+      desc: "Auto-extracted signal tx_arb_locked from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_txtb_meta_clk_en",
+      desc: "Auto-extracted signal txtb_meta_clk_en from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_drv_tttm_ena",
+      desc: "Auto-extracted signal drv_tttm_ena from tx_arbitrator.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_fsm_tx_arb_fsm_ce",
+      desc: "Auto-extracted signal tx_arb_fsm_ce from tx_arbitrator_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_fsm_fsm_wait_state_d",
+      desc: "Auto-extracted signal fsm_wait_state_d from tx_arbitrator_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_arbitrator_fsm_fsm_wait_state_q",
+      desc: "Auto-extracted signal fsm_wait_state_q from tx_arbitrator_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_data_cache_tx_cache_mem",
+      desc: "Auto-extracted signal tx_cache_mem from tx_data_cache.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_tx_sr_output",
+      desc: "Auto-extracted signal tx_sr_output from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_tx_sr_ce",
+      desc: "Auto-extracted signal tx_sr_ce from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_tx_sr_pload",
+      desc: "Auto-extracted signal tx_sr_pload from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_tx_sr_pload_val",
+      desc: "Auto-extracted signal tx_sr_pload_val from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_tx_base_id",
+      desc: "Auto-extracted signal tx_base_id from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_tx_ext_id",
+      desc: "Auto-extracted signal tx_ext_id from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_tx_crc",
+      desc: "Auto-extracted signal tx_crc from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_bst_ctr_grey",
+      desc: "Auto-extracted signal bst_ctr_grey from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_bst_parity",
+      desc: "Auto-extracted signal bst_parity from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "tx_shift_reg_stuff_count",
+      desc: "Auto-extracted signal stuff_count from tx_shift_reg.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_txtb_user_accessible",
+      desc: "Auto-extracted signal txtb_user_accessible from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_hw_cbs",
+      desc: "Auto-extracted signal hw_cbs from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_sw_cbs",
+      desc: "Auto-extracted signal sw_cbs from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_txtb_unmask_data_ram",
+      desc: "Auto-extracted signal txtb_unmask_data_ram from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_txtb_port_b_data_i",
+      desc: "Auto-extracted signal txtb_port_b_data_i from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_write",
+      desc: "Auto-extracted signal ram_write from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_read_address",
+      desc: "Auto-extracted signal ram_read_address from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_txtb_ram_clk_en",
+      desc: "Auto-extracted signal txtb_ram_clk_en from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_clk_ram",
+      desc: "Auto-extracted signal clk_ram from txt_buffer.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_fsm_abort_applied",
+      desc: "Auto-extracted signal abort_applied from txt_buffer_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_fsm_txt_fsm_ce",
+      desc: "Auto-extracted signal txt_fsm_ce from txt_buffer_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_fsm_go_to_failed",
+      desc: "Auto-extracted signal go_to_failed from txt_buffer_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_fsm_transient_state",
+      desc: "Auto-extracted signal transient_state from txt_buffer_fsm.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_port_a_address_i",
+      desc: "Auto-extracted signal port_a_address_i from txt_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_port_a_write_i",
+      desc: "Auto-extracted signal port_a_write_i from txt_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_port_a_data_in_i",
+      desc: "Auto-extracted signal port_a_data_in_i from txt_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_port_b_address_i",
+      desc: "Auto-extracted signal port_b_address_i from txt_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_port_b_data_out_i",
+      desc: "Auto-extracted signal port_b_data_out_i from txt_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_tst_ena",
+      desc: "Auto-extracted signal tst_ena from txt_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "txt_buffer_ram_tst_addr",
+      desc: "Auto-extracted signal tst_addr from txt_buffer_ram.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "access_signaler_be_active",
+      desc: "Auto-extracted signal be_active from access_signaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "access_signaler_access_in",
+      desc: "Auto-extracted signal access_in from access_signaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "access_signaler_access_active",
+      desc: "Auto-extracted signal access_active from access_signaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "access_signaler_access_active_reg",
+      desc: "Auto-extracted signal access_active_reg from access_signaler.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "address_decoder_addr_dec_i",
+      desc: "Auto-extracted signal addr_dec_i from address_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    },
+    {
+      name: "address_decoder_addr_dec_enabled_i",
+      desc: "Auto-extracted signal addr_dec_enabled_i from address_decoder.vhd",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {
+          name: "value",
+          bits: "31:0",
+          desc: "Placeholder 32-bit field for extracted signal"
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/can_bus/doc/registers.md b/docs/um/ip/can_bus/doc/registers.md
new file mode 100644
index 00000000..a3c19b02
--- /dev/null
+++ b/docs/um/ip/can_bus/doc/registers.md
@@ -0,0 +1,15050 @@
+## Summary
+
+| Name                                                                                                          | Offset   |   Length | Description                                                                    |
+|:--------------------------------------------------------------------------------------------------------------|:---------|---------:|:-------------------------------------------------------------------------------|
+| can_bus.[`ahb_ifc_hsel_valid`](#ahb_ifc_hsel_valid)                                                           | 0x0      |        4 | Auto-extracted signal hsel_valid from ahb_ifc.vhd                              |
+| can_bus.[`ahb_ifc_write_acc_d`](#ahb_ifc_write_acc_d)                                                         | 0x4      |        4 | Auto-extracted signal write_acc_d from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_write_acc_q`](#ahb_ifc_write_acc_q)                                                         | 0x8      |        4 | Auto-extracted signal write_acc_q from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_haddr_q`](#ahb_ifc_haddr_q)                                                                 | 0xc      |        4 | Auto-extracted signal haddr_q from ahb_ifc.vhd                                 |
+| can_bus.[`ahb_ifc_h_ready_raw`](#ahb_ifc_h_ready_raw)                                                         | 0x10     |        4 | Auto-extracted signal h_ready_raw from ahb_ifc.vhd                             |
+| can_bus.[`ahb_ifc_sbe_d`](#ahb_ifc_sbe_d)                                                                     | 0x14     |        4 | Auto-extracted signal sbe_d from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_sbe_q`](#ahb_ifc_sbe_q)                                                                     | 0x18     |        4 | Auto-extracted signal sbe_q from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_swr_i`](#ahb_ifc_swr_i)                                                                     | 0x1c     |        4 | Auto-extracted signal swr_i from ahb_ifc.vhd                                   |
+| can_bus.[`ahb_ifc_srd_i`](#ahb_ifc_srd_i)                                                                     | 0x20     |        4 | Auto-extracted signal srd_i from ahb_ifc.vhd                                   |
+| can_bus.[`bit_destuffing_discard_stuff_bit`](#bit_destuffing_discard_stuff_bit)                               | 0x24     |        4 | Auto-extracted signal discard_stuff_bit from bit_destuffing.vhd                |
+| can_bus.[`bit_destuffing_non_fix_to_fix_chng`](#bit_destuffing_non_fix_to_fix_chng)                           | 0x28     |        4 | Auto-extracted signal non_fix_to_fix_chng from bit_destuffing.vhd              |
+| can_bus.[`bit_destuffing_stuff_lvl_reached`](#bit_destuffing_stuff_lvl_reached)                               | 0x2c     |        4 | Auto-extracted signal stuff_lvl_reached from bit_destuffing.vhd                |
+| can_bus.[`bit_destuffing_stuff_rule_violate`](#bit_destuffing_stuff_rule_violate)                             | 0x30     |        4 | Auto-extracted signal stuff_rule_violate from bit_destuffing.vhd               |
+| can_bus.[`bit_destuffing_enable_prev`](#bit_destuffing_enable_prev)                                           | 0x34     |        4 | Auto-extracted signal enable_prev from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_fixed_prev_q`](#bit_destuffing_fixed_prev_q)                                         | 0x38     |        4 | Auto-extracted signal fixed_prev_q from bit_destuffing.vhd                     |
+| can_bus.[`bit_destuffing_fixed_prev_d`](#bit_destuffing_fixed_prev_d)                                         | 0x3c     |        4 | Auto-extracted signal fixed_prev_d from bit_destuffing.vhd                     |
+| can_bus.[`bit_destuffing_same_bits_erase`](#bit_destuffing_same_bits_erase)                                   | 0x40     |        4 | Auto-extracted signal same_bits_erase from bit_destuffing.vhd                  |
+| can_bus.[`bit_destuffing_destuffed_q`](#bit_destuffing_destuffed_q)                                           | 0x44     |        4 | Auto-extracted signal destuffed_q from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_destuffed_d`](#bit_destuffing_destuffed_d)                                           | 0x48     |        4 | Auto-extracted signal destuffed_d from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_stuff_err_q`](#bit_destuffing_stuff_err_q)                                           | 0x4c     |        4 | Auto-extracted signal stuff_err_q from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_stuff_err_d`](#bit_destuffing_stuff_err_d)                                           | 0x50     |        4 | Auto-extracted signal stuff_err_d from bit_destuffing.vhd                      |
+| can_bus.[`bit_destuffing_prev_val_q`](#bit_destuffing_prev_val_q)                                             | 0x54     |        4 | Auto-extracted signal prev_val_q from bit_destuffing.vhd                       |
+| can_bus.[`bit_destuffing_prev_val_d`](#bit_destuffing_prev_val_d)                                             | 0x58     |        4 | Auto-extracted signal prev_val_d from bit_destuffing.vhd                       |
+| can_bus.[`bit_err_detector_bit_err_d`](#bit_err_detector_bit_err_d)                                           | 0x5c     |        4 | Auto-extracted signal bit_err_d from bit_err_detector.vhd                      |
+| can_bus.[`bit_err_detector_bit_err_q`](#bit_err_detector_bit_err_q)                                           | 0x60     |        4 | Auto-extracted signal bit_err_q from bit_err_detector.vhd                      |
+| can_bus.[`bit_err_detector_bit_err_ssp_capt_d`](#bit_err_detector_bit_err_ssp_capt_d)                         | 0x64     |        4 | Auto-extracted signal bit_err_ssp_capt_d from bit_err_detector.vhd             |
+| can_bus.[`bit_err_detector_bit_err_ssp_capt_q`](#bit_err_detector_bit_err_ssp_capt_q)                         | 0x68     |        4 | Auto-extracted signal bit_err_ssp_capt_q from bit_err_detector.vhd             |
+| can_bus.[`bit_err_detector_bit_err_ssp_valid`](#bit_err_detector_bit_err_ssp_valid)                           | 0x6c     |        4 | Auto-extracted signal bit_err_ssp_valid from bit_err_detector.vhd              |
+| can_bus.[`bit_err_detector_bit_err_ssp_condition`](#bit_err_detector_bit_err_ssp_condition)                   | 0x70     |        4 | Auto-extracted signal bit_err_ssp_condition from bit_err_detector.vhd          |
+| can_bus.[`bit_err_detector_bit_err_norm_valid`](#bit_err_detector_bit_err_norm_valid)                         | 0x74     |        4 | Auto-extracted signal bit_err_norm_valid from bit_err_detector.vhd             |
+| can_bus.[`bit_filter_masked_input`](#bit_filter_masked_input)                                                 | 0x78     |        4 | Auto-extracted signal masked_input from bit_filter.vhd                         |
+| can_bus.[`bit_filter_masked_value`](#bit_filter_masked_value)                                                 | 0x7c     |        4 | Auto-extracted signal masked_value from bit_filter.vhd                         |
+| can_bus.[`bit_segment_meter_sel_tseg1`](#bit_segment_meter_sel_tseg1)                                         | 0x80     |        4 | Auto-extracted signal sel_tseg1 from bit_segment_meter.vhd                     |
+| can_bus.[`bit_segment_meter_exp_seg_length_ce`](#bit_segment_meter_exp_seg_length_ce)                         | 0x84     |        4 | Auto-extracted signal exp_seg_length_ce from bit_segment_meter.vhd             |
+| can_bus.[`bit_segment_meter_phase_err_mt_sjw`](#bit_segment_meter_phase_err_mt_sjw)                           | 0x88     |        4 | Auto-extracted signal phase_err_mt_sjw from bit_segment_meter.vhd              |
+| can_bus.[`bit_segment_meter_phase_err_eq_sjw`](#bit_segment_meter_phase_err_eq_sjw)                           | 0x8c     |        4 | Auto-extracted signal phase_err_eq_sjw from bit_segment_meter.vhd              |
+| can_bus.[`bit_segment_meter_exit_ph2_immediate`](#bit_segment_meter_exit_ph2_immediate)                       | 0x90     |        4 | Auto-extracted signal exit_ph2_immediate from bit_segment_meter.vhd            |
+| can_bus.[`bit_segment_meter_exit_segm_regular`](#bit_segment_meter_exit_segm_regular)                         | 0x94     |        4 | Auto-extracted signal exit_segm_regular from bit_segment_meter.vhd             |
+| can_bus.[`bit_segment_meter_exit_segm_regular_tseg1`](#bit_segment_meter_exit_segm_regular_tseg1)             | 0x98     |        4 | Auto-extracted signal exit_segm_regular_tseg1 from bit_segment_meter.vhd       |
+| can_bus.[`bit_segment_meter_exit_segm_regular_tseg2`](#bit_segment_meter_exit_segm_regular_tseg2)             | 0x9c     |        4 | Auto-extracted signal exit_segm_regular_tseg2 from bit_segment_meter.vhd       |
+| can_bus.[`bit_segment_meter_sjw_mt_zero`](#bit_segment_meter_sjw_mt_zero)                                     | 0xa0     |        4 | Auto-extracted signal sjw_mt_zero from bit_segment_meter.vhd                   |
+| can_bus.[`bit_segment_meter_use_basic_segm_length`](#bit_segment_meter_use_basic_segm_length)                 | 0xa4     |        4 | Auto-extracted signal use_basic_segm_length from bit_segment_meter.vhd         |
+| can_bus.[`bit_segment_meter_phase_err_sjw_by_one`](#bit_segment_meter_phase_err_sjw_by_one)                   | 0xa8     |        4 | Auto-extracted signal phase_err_sjw_by_one from bit_segment_meter.vhd          |
+| can_bus.[`bit_segment_meter_shorten_tseg1_after_tseg2`](#bit_segment_meter_shorten_tseg1_after_tseg2)         | 0xac     |        4 | Auto-extracted signal shorten_tseg1_after_tseg2 from bit_segment_meter.vhd     |
+| can_bus.[`bit_stuffing_data_out_i`](#bit_stuffing_data_out_i)                                                 | 0xb0     |        4 | Auto-extracted signal data_out_i from bit_stuffing.vhd                         |
+| can_bus.[`bit_stuffing_data_halt_q`](#bit_stuffing_data_halt_q)                                               | 0xb4     |        4 | Auto-extracted signal data_halt_q from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_data_halt_d`](#bit_stuffing_data_halt_d)                                               | 0xb8     |        4 | Auto-extracted signal data_halt_d from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_fixed_reg_q`](#bit_stuffing_fixed_reg_q)                                               | 0xbc     |        4 | Auto-extracted signal fixed_reg_q from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_fixed_reg_d`](#bit_stuffing_fixed_reg_d)                                               | 0xc0     |        4 | Auto-extracted signal fixed_reg_d from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_enable_prev`](#bit_stuffing_enable_prev)                                               | 0xc4     |        4 | Auto-extracted signal enable_prev from bit_stuffing.vhd                        |
+| can_bus.[`bit_stuffing_non_fix_to_fix_chng`](#bit_stuffing_non_fix_to_fix_chng)                               | 0xc8     |        4 | Auto-extracted signal non_fix_to_fix_chng from bit_stuffing.vhd                |
+| can_bus.[`bit_stuffing_stuff_lvl_reached`](#bit_stuffing_stuff_lvl_reached)                                   | 0xcc     |        4 | Auto-extracted signal stuff_lvl_reached from bit_stuffing.vhd                  |
+| can_bus.[`bit_stuffing_same_bits_rst_trig`](#bit_stuffing_same_bits_rst_trig)                                 | 0xd0     |        4 | Auto-extracted signal same_bits_rst_trig from bit_stuffing.vhd                 |
+| can_bus.[`bit_stuffing_same_bits_rst`](#bit_stuffing_same_bits_rst)                                           | 0xd4     |        4 | Auto-extracted signal same_bits_rst from bit_stuffing.vhd                      |
+| can_bus.[`bit_stuffing_insert_stuff_bit`](#bit_stuffing_insert_stuff_bit)                                     | 0xd8     |        4 | Auto-extracted signal insert_stuff_bit from bit_stuffing.vhd                   |
+| can_bus.[`bit_stuffing_data_out_d_ena`](#bit_stuffing_data_out_d_ena)                                         | 0xdc     |        4 | Auto-extracted signal data_out_d_ena from bit_stuffing.vhd                     |
+| can_bus.[`bit_stuffing_data_out_d`](#bit_stuffing_data_out_d)                                                 | 0xe0     |        4 | Auto-extracted signal data_out_d from bit_stuffing.vhd                         |
+| can_bus.[`bit_stuffing_data_out_ce`](#bit_stuffing_data_out_ce)                                               | 0xe4     |        4 | Auto-extracted signal data_out_ce from bit_stuffing.vhd                        |
+| can_bus.[`bit_time_cfg_capture_drv_tq_nbt`](#bit_time_cfg_capture_drv_tq_nbt)                                 | 0xe8     |        4 | Auto-extracted signal drv_tq_nbt from bit_time_cfg_capture.vhd                 |
+| can_bus.[`bit_time_cfg_capture_drv_prs_nbt`](#bit_time_cfg_capture_drv_prs_nbt)                               | 0xec     |        4 | Auto-extracted signal drv_prs_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph1_nbt`](#bit_time_cfg_capture_drv_ph1_nbt)                               | 0xf0     |        4 | Auto-extracted signal drv_ph1_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph2_nbt`](#bit_time_cfg_capture_drv_ph2_nbt)                               | 0xf4     |        4 | Auto-extracted signal drv_ph2_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_sjw_nbt`](#bit_time_cfg_capture_drv_sjw_nbt)                               | 0xf8     |        4 | Auto-extracted signal drv_sjw_nbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_tq_dbt`](#bit_time_cfg_capture_drv_tq_dbt)                                 | 0xfc     |        4 | Auto-extracted signal drv_tq_dbt from bit_time_cfg_capture.vhd                 |
+| can_bus.[`bit_time_cfg_capture_drv_prs_dbt`](#bit_time_cfg_capture_drv_prs_dbt)                               | 0x100    |        4 | Auto-extracted signal drv_prs_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph1_dbt`](#bit_time_cfg_capture_drv_ph1_dbt)                               | 0x104    |        4 | Auto-extracted signal drv_ph1_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ph2_dbt`](#bit_time_cfg_capture_drv_ph2_dbt)                               | 0x108    |        4 | Auto-extracted signal drv_ph2_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_sjw_dbt`](#bit_time_cfg_capture_drv_sjw_dbt)                               | 0x10c    |        4 | Auto-extracted signal drv_sjw_dbt from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_tseg1_nbt_d`](#bit_time_cfg_capture_tseg1_nbt_d)                               | 0x110    |        4 | Auto-extracted signal tseg1_nbt_d from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_tseg1_dbt_d`](#bit_time_cfg_capture_tseg1_dbt_d)                               | 0x114    |        4 | Auto-extracted signal tseg1_dbt_d from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ena`](#bit_time_cfg_capture_drv_ena)                                       | 0x118    |        4 | Auto-extracted signal drv_ena from bit_time_cfg_capture.vhd                    |
+| can_bus.[`bit_time_cfg_capture_drv_ena_reg`](#bit_time_cfg_capture_drv_ena_reg)                               | 0x11c    |        4 | Auto-extracted signal drv_ena_reg from bit_time_cfg_capture.vhd                |
+| can_bus.[`bit_time_cfg_capture_drv_ena_reg_2`](#bit_time_cfg_capture_drv_ena_reg_2)                           | 0x120    |        4 | Auto-extracted signal drv_ena_reg_2 from bit_time_cfg_capture.vhd              |
+| can_bus.[`bit_time_cfg_capture_capture`](#bit_time_cfg_capture_capture)                                       | 0x124    |        4 | Auto-extracted signal capture from bit_time_cfg_capture.vhd                    |
+| can_bus.[`bit_time_counters_tq_counter_d`](#bit_time_counters_tq_counter_d)                                   | 0x128    |        4 | Auto-extracted signal tq_counter_d from bit_time_counters.vhd                  |
+| can_bus.[`bit_time_counters_tq_counter_q`](#bit_time_counters_tq_counter_q)                                   | 0x12c    |        4 | Auto-extracted signal tq_counter_q from bit_time_counters.vhd                  |
+| can_bus.[`bit_time_counters_tq_counter_ce`](#bit_time_counters_tq_counter_ce)                                 | 0x130    |        4 | Auto-extracted signal tq_counter_ce from bit_time_counters.vhd                 |
+| can_bus.[`bit_time_counters_tq_counter_allow`](#bit_time_counters_tq_counter_allow)                           | 0x134    |        4 | Auto-extracted signal tq_counter_allow from bit_time_counters.vhd              |
+| can_bus.[`bit_time_counters_tq_edge_i`](#bit_time_counters_tq_edge_i)                                         | 0x138    |        4 | Auto-extracted signal tq_edge_i from bit_time_counters.vhd                     |
+| can_bus.[`bit_time_counters_segm_counter_d`](#bit_time_counters_segm_counter_d)                               | 0x13c    |        4 | Auto-extracted signal segm_counter_d from bit_time_counters.vhd                |
+| can_bus.[`bit_time_counters_segm_counter_q`](#bit_time_counters_segm_counter_q)                               | 0x140    |        4 | Auto-extracted signal segm_counter_q from bit_time_counters.vhd                |
+| can_bus.[`bit_time_counters_segm_counter_ce`](#bit_time_counters_segm_counter_ce)                             | 0x144    |        4 | Auto-extracted signal segm_counter_ce from bit_time_counters.vhd               |
+| can_bus.[`bit_time_fsm_bt_fsm_ce`](#bit_time_fsm_bt_fsm_ce)                                                   | 0x148    |        4 | Auto-extracted signal bt_fsm_ce from bit_time_fsm.vhd                          |
+| can_bus.[`bus_sampling_drv_ena`](#bus_sampling_drv_ena)                                                       | 0x14c    |        4 | Auto-extracted signal drv_ena from bus_sampling.vhd                            |
+| can_bus.[`bus_sampling_drv_ssp_offset`](#bus_sampling_drv_ssp_offset)                                         | 0x150    |        4 | Auto-extracted signal drv_ssp_offset from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_drv_ssp_delay_select`](#bus_sampling_drv_ssp_delay_select)                             | 0x154    |        4 | Auto-extracted signal drv_ssp_delay_select from bus_sampling.vhd               |
+| can_bus.[`bus_sampling_data_rx_synced`](#bus_sampling_data_rx_synced)                                         | 0x158    |        4 | Auto-extracted signal data_rx_synced from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_prev_Sample`](#bus_sampling_prev_sample)                                               | 0x15c    |        4 | Auto-extracted signal prev_Sample from bus_sampling.vhd                        |
+| can_bus.[`bus_sampling_sample_sec_i`](#bus_sampling_sample_sec_i)                                             | 0x160    |        4 | Auto-extracted signal sample_sec_i from bus_sampling.vhd                       |
+| can_bus.[`bus_sampling_data_tx_delayed`](#bus_sampling_data_tx_delayed)                                       | 0x164    |        4 | Auto-extracted signal data_tx_delayed from bus_sampling.vhd                    |
+| can_bus.[`bus_sampling_edge_rx_valid`](#bus_sampling_edge_rx_valid)                                           | 0x168    |        4 | Auto-extracted signal edge_rx_valid from bus_sampling.vhd                      |
+| can_bus.[`bus_sampling_edge_tx_valid`](#bus_sampling_edge_tx_valid)                                           | 0x16c    |        4 | Auto-extracted signal edge_tx_valid from bus_sampling.vhd                      |
+| can_bus.[`bus_sampling_ssp_delay`](#bus_sampling_ssp_delay)                                                   | 0x170    |        4 | Auto-extracted signal ssp_delay from bus_sampling.vhd                          |
+| can_bus.[`bus_sampling_tx_trigger_q`](#bus_sampling_tx_trigger_q)                                             | 0x174    |        4 | Auto-extracted signal tx_trigger_q from bus_sampling.vhd                       |
+| can_bus.[`bus_sampling_tx_trigger_ssp`](#bus_sampling_tx_trigger_ssp)                                         | 0x178    |        4 | Auto-extracted signal tx_trigger_ssp from bus_sampling.vhd                     |
+| can_bus.[`bus_sampling_shift_regs_res_d`](#bus_sampling_shift_regs_res_d)                                     | 0x17c    |        4 | Auto-extracted signal shift_regs_res_d from bus_sampling.vhd                   |
+| can_bus.[`bus_sampling_shift_regs_res_q`](#bus_sampling_shift_regs_res_q)                                     | 0x180    |        4 | Auto-extracted signal shift_regs_res_q from bus_sampling.vhd                   |
+| can_bus.[`bus_sampling_shift_regs_res_q_scan`](#bus_sampling_shift_regs_res_q_scan)                           | 0x184    |        4 | Auto-extracted signal shift_regs_res_q_scan from bus_sampling.vhd              |
+| can_bus.[`bus_sampling_ssp_enable`](#bus_sampling_ssp_enable)                                                 | 0x188    |        4 | Auto-extracted signal ssp_enable from bus_sampling.vhd                         |
+| can_bus.[`bus_traffic_counters_tx_ctr_i`](#bus_traffic_counters_tx_ctr_i)                                     | 0x18c    |        4 | Auto-extracted signal tx_ctr_i from bus_traffic_counters.vhd                   |
+| can_bus.[`bus_traffic_counters_rx_ctr_i`](#bus_traffic_counters_rx_ctr_i)                                     | 0x190    |        4 | Auto-extracted signal rx_ctr_i from bus_traffic_counters.vhd                   |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_d`](#bus_traffic_counters_tx_ctr_rst_n_d)                         | 0x194    |        4 | Auto-extracted signal tx_ctr_rst_n_d from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_q`](#bus_traffic_counters_tx_ctr_rst_n_q)                         | 0x198    |        4 | Auto-extracted signal tx_ctr_rst_n_q from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_tx_ctr_rst_n_q_scan`](#bus_traffic_counters_tx_ctr_rst_n_q_scan)               | 0x19c    |        4 | Auto-extracted signal tx_ctr_rst_n_q_scan from bus_traffic_counters.vhd        |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_d`](#bus_traffic_counters_rx_ctr_rst_n_d)                         | 0x1a0    |        4 | Auto-extracted signal rx_ctr_rst_n_d from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_q`](#bus_traffic_counters_rx_ctr_rst_n_q)                         | 0x1a4    |        4 | Auto-extracted signal rx_ctr_rst_n_q from bus_traffic_counters.vhd             |
+| can_bus.[`bus_traffic_counters_rx_ctr_rst_n_q_scan`](#bus_traffic_counters_rx_ctr_rst_n_q_scan)               | 0x1a8    |        4 | Auto-extracted signal rx_ctr_rst_n_q_scan from bus_traffic_counters.vhd        |
+| can_bus.[`can_apb_tb_s_apb_paddr`](#can_apb_tb_s_apb_paddr)                                                   | 0x1ac    |        4 | Auto-extracted signal s_apb_paddr from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_penable`](#can_apb_tb_s_apb_penable)                                               | 0x1b0    |        4 | Auto-extracted signal s_apb_penable from can_apb_tb.vhd                        |
+| can_bus.[`can_apb_tb_s_apb_pprot`](#can_apb_tb_s_apb_pprot)                                                   | 0x1b4    |        4 | Auto-extracted signal s_apb_pprot from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_prdata`](#can_apb_tb_s_apb_prdata)                                                 | 0x1b8    |        4 | Auto-extracted signal s_apb_prdata from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_pready`](#can_apb_tb_s_apb_pready)                                                 | 0x1bc    |        4 | Auto-extracted signal s_apb_pready from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_psel`](#can_apb_tb_s_apb_psel)                                                     | 0x1c0    |        4 | Auto-extracted signal s_apb_psel from can_apb_tb.vhd                           |
+| can_bus.[`can_apb_tb_s_apb_pslverr`](#can_apb_tb_s_apb_pslverr)                                               | 0x1c4    |        4 | Auto-extracted signal s_apb_pslverr from can_apb_tb.vhd                        |
+| can_bus.[`can_apb_tb_s_apb_pstrb`](#can_apb_tb_s_apb_pstrb)                                                   | 0x1c8    |        4 | Auto-extracted signal s_apb_pstrb from can_apb_tb.vhd                          |
+| can_bus.[`can_apb_tb_s_apb_pwdata`](#can_apb_tb_s_apb_pwdata)                                                 | 0x1cc    |        4 | Auto-extracted signal s_apb_pwdata from can_apb_tb.vhd                         |
+| can_bus.[`can_apb_tb_s_apb_pwrite`](#can_apb_tb_s_apb_pwrite)                                                 | 0x1d0    |        4 | Auto-extracted signal s_apb_pwrite from can_apb_tb.vhd                         |
+| can_bus.[`can_core_drv_clr_rx_ctr`](#can_core_drv_clr_rx_ctr)                                                 | 0x1d4    |        4 | Auto-extracted signal drv_clr_rx_ctr from can_core.vhd                         |
+| can_bus.[`can_core_drv_clr_tx_ctr`](#can_core_drv_clr_tx_ctr)                                                 | 0x1d8    |        4 | Auto-extracted signal drv_clr_tx_ctr from can_core.vhd                         |
+| can_bus.[`can_core_drv_bus_mon_ena`](#can_core_drv_bus_mon_ena)                                               | 0x1dc    |        4 | Auto-extracted signal drv_bus_mon_ena from can_core.vhd                        |
+| can_bus.[`can_core_drv_ena`](#can_core_drv_ena)                                                               | 0x1e0    |        4 | Auto-extracted signal drv_ena from can_core.vhd                                |
+| can_bus.[`can_core_rec_ident_i`](#can_core_rec_ident_i)                                                       | 0x1e4    |        4 | Auto-extracted signal rec_ident_i from can_core.vhd                            |
+| can_bus.[`can_core_rec_dlc_i`](#can_core_rec_dlc_i)                                                           | 0x1e8    |        4 | Auto-extracted signal rec_dlc_i from can_core.vhd                              |
+| can_bus.[`can_core_rec_ident_type_i`](#can_core_rec_ident_type_i)                                             | 0x1ec    |        4 | Auto-extracted signal rec_ident_type_i from can_core.vhd                       |
+| can_bus.[`can_core_rec_frame_type_i`](#can_core_rec_frame_type_i)                                             | 0x1f0    |        4 | Auto-extracted signal rec_frame_type_i from can_core.vhd                       |
+| can_bus.[`can_core_rec_is_rtr_i`](#can_core_rec_is_rtr_i)                                                     | 0x1f4    |        4 | Auto-extracted signal rec_is_rtr_i from can_core.vhd                           |
+| can_bus.[`can_core_rec_brs_i`](#can_core_rec_brs_i)                                                           | 0x1f8    |        4 | Auto-extracted signal rec_brs_i from can_core.vhd                              |
+| can_bus.[`can_core_rec_esi_i`](#can_core_rec_esi_i)                                                           | 0x1fc    |        4 | Auto-extracted signal rec_esi_i from can_core.vhd                              |
+| can_bus.[`can_core_alc`](#can_core_alc)                                                                       | 0x200    |        4 | Auto-extracted signal alc from can_core.vhd                                    |
+| can_bus.[`can_core_erc_capture`](#can_core_erc_capture)                                                       | 0x204    |        4 | Auto-extracted signal erc_capture from can_core.vhd                            |
+| can_bus.[`can_core_is_transmitter`](#can_core_is_transmitter)                                                 | 0x208    |        4 | Auto-extracted signal is_transmitter from can_core.vhd                         |
+| can_bus.[`can_core_is_receiver`](#can_core_is_receiver)                                                       | 0x20c    |        4 | Auto-extracted signal is_receiver from can_core.vhd                            |
+| can_bus.[`can_core_is_idle`](#can_core_is_idle)                                                               | 0x210    |        4 | Auto-extracted signal is_idle from can_core.vhd                                |
+| can_bus.[`can_core_arbitration_lost_i`](#can_core_arbitration_lost_i)                                         | 0x214    |        4 | Auto-extracted signal arbitration_lost_i from can_core.vhd                     |
+| can_bus.[`can_core_set_transmitter`](#can_core_set_transmitter)                                               | 0x218    |        4 | Auto-extracted signal set_transmitter from can_core.vhd                        |
+| can_bus.[`can_core_set_receiver`](#can_core_set_receiver)                                                     | 0x21c    |        4 | Auto-extracted signal set_receiver from can_core.vhd                           |
+| can_bus.[`can_core_set_idle`](#can_core_set_idle)                                                             | 0x220    |        4 | Auto-extracted signal set_idle from can_core.vhd                               |
+| can_bus.[`can_core_is_err_active`](#can_core_is_err_active)                                                   | 0x224    |        4 | Auto-extracted signal is_err_active from can_core.vhd                          |
+| can_bus.[`can_core_is_err_passive`](#can_core_is_err_passive)                                                 | 0x228    |        4 | Auto-extracted signal is_err_passive from can_core.vhd                         |
+| can_bus.[`can_core_is_bus_off_i`](#can_core_is_bus_off_i)                                                     | 0x22c    |        4 | Auto-extracted signal is_bus_off_i from can_core.vhd                           |
+| can_bus.[`can_core_err_detected_i`](#can_core_err_detected_i)                                                 | 0x230    |        4 | Auto-extracted signal err_detected_i from can_core.vhd                         |
+| can_bus.[`can_core_primary_err`](#can_core_primary_err)                                                       | 0x234    |        4 | Auto-extracted signal primary_err from can_core.vhd                            |
+| can_bus.[`can_core_act_err_ovr_flag`](#can_core_act_err_ovr_flag)                                             | 0x238    |        4 | Auto-extracted signal act_err_ovr_flag from can_core.vhd                       |
+| can_bus.[`can_core_err_delim_late`](#can_core_err_delim_late)                                                 | 0x23c    |        4 | Auto-extracted signal err_delim_late from can_core.vhd                         |
+| can_bus.[`can_core_set_err_active`](#can_core_set_err_active)                                                 | 0x240    |        4 | Auto-extracted signal set_err_active from can_core.vhd                         |
+| can_bus.[`can_core_err_ctrs_unchanged`](#can_core_err_ctrs_unchanged)                                         | 0x244    |        4 | Auto-extracted signal err_ctrs_unchanged from can_core.vhd                     |
+| can_bus.[`can_core_stuff_enable`](#can_core_stuff_enable)                                                     | 0x248    |        4 | Auto-extracted signal stuff_enable from can_core.vhd                           |
+| can_bus.[`can_core_destuff_enable`](#can_core_destuff_enable)                                                 | 0x24c    |        4 | Auto-extracted signal destuff_enable from can_core.vhd                         |
+| can_bus.[`can_core_fixed_stuff`](#can_core_fixed_stuff)                                                       | 0x250    |        4 | Auto-extracted signal fixed_stuff from can_core.vhd                            |
+| can_bus.[`can_core_tx_frame_no_sof`](#can_core_tx_frame_no_sof)                                               | 0x254    |        4 | Auto-extracted signal tx_frame_no_sof from can_core.vhd                        |
+| can_bus.[`can_core_stuff_length`](#can_core_stuff_length)                                                     | 0x258    |        4 | Auto-extracted signal stuff_length from can_core.vhd                           |
+| can_bus.[`can_core_dst_ctr`](#can_core_dst_ctr)                                                               | 0x25c    |        4 | Auto-extracted signal dst_ctr from can_core.vhd                                |
+| can_bus.[`can_core_bst_ctr`](#can_core_bst_ctr)                                                               | 0x260    |        4 | Auto-extracted signal bst_ctr from can_core.vhd                                |
+| can_bus.[`can_core_stuff_err`](#can_core_stuff_err)                                                           | 0x264    |        4 | Auto-extracted signal stuff_err from can_core.vhd                              |
+| can_bus.[`can_core_crc_enable`](#can_core_crc_enable)                                                         | 0x268    |        4 | Auto-extracted signal crc_enable from can_core.vhd                             |
+| can_bus.[`can_core_crc_spec_enable`](#can_core_crc_spec_enable)                                               | 0x26c    |        4 | Auto-extracted signal crc_spec_enable from can_core.vhd                        |
+| can_bus.[`can_core_crc_calc_from_rx`](#can_core_crc_calc_from_rx)                                             | 0x270    |        4 | Auto-extracted signal crc_calc_from_rx from can_core.vhd                       |
+| can_bus.[`can_core_crc_15`](#can_core_crc_15)                                                                 | 0x274    |        4 | Auto-extracted signal crc_15 from can_core.vhd                                 |
+| can_bus.[`can_core_crc_17`](#can_core_crc_17)                                                                 | 0x278    |        4 | Auto-extracted signal crc_17 from can_core.vhd                                 |
+| can_bus.[`can_core_crc_21`](#can_core_crc_21)                                                                 | 0x27c    |        4 | Auto-extracted signal crc_21 from can_core.vhd                                 |
+| can_bus.[`can_core_sp_control_i`](#can_core_sp_control_i)                                                     | 0x280    |        4 | Auto-extracted signal sp_control_i from can_core.vhd                           |
+| can_bus.[`can_core_sp_control_q`](#can_core_sp_control_q)                                                     | 0x284    |        4 | Auto-extracted signal sp_control_q from can_core.vhd                           |
+| can_bus.[`can_core_sync_control_i`](#can_core_sync_control_i)                                                 | 0x288    |        4 | Auto-extracted signal sync_control_i from can_core.vhd                         |
+| can_bus.[`can_core_ssp_reset_i`](#can_core_ssp_reset_i)                                                       | 0x28c    |        4 | Auto-extracted signal ssp_reset_i from can_core.vhd                            |
+| can_bus.[`can_core_tran_delay_meas_i`](#can_core_tran_delay_meas_i)                                           | 0x290    |        4 | Auto-extracted signal tran_delay_meas_i from can_core.vhd                      |
+| can_bus.[`can_core_tran_valid_i`](#can_core_tran_valid_i)                                                     | 0x294    |        4 | Auto-extracted signal tran_valid_i from can_core.vhd                           |
+| can_bus.[`can_core_rec_valid_i`](#can_core_rec_valid_i)                                                       | 0x298    |        4 | Auto-extracted signal rec_valid_i from can_core.vhd                            |
+| can_bus.[`can_core_br_shifted_i`](#can_core_br_shifted_i)                                                     | 0x29c    |        4 | Auto-extracted signal br_shifted_i from can_core.vhd                           |
+| can_bus.[`can_core_fcs_changed_i`](#can_core_fcs_changed_i)                                                   | 0x2a0    |        4 | Auto-extracted signal fcs_changed_i from can_core.vhd                          |
+| can_bus.[`can_core_err_warning_limit_i`](#can_core_err_warning_limit_i)                                       | 0x2a4    |        4 | Auto-extracted signal err_warning_limit_i from can_core.vhd                    |
+| can_bus.[`can_core_tx_err_ctr`](#can_core_tx_err_ctr)                                                         | 0x2a8    |        4 | Auto-extracted signal tx_err_ctr from can_core.vhd                             |
+| can_bus.[`can_core_rx_err_ctr`](#can_core_rx_err_ctr)                                                         | 0x2ac    |        4 | Auto-extracted signal rx_err_ctr from can_core.vhd                             |
+| can_bus.[`can_core_norm_err_ctr`](#can_core_norm_err_ctr)                                                     | 0x2b0    |        4 | Auto-extracted signal norm_err_ctr from can_core.vhd                           |
+| can_bus.[`can_core_data_err_ctr`](#can_core_data_err_ctr)                                                     | 0x2b4    |        4 | Auto-extracted signal data_err_ctr from can_core.vhd                           |
+| can_bus.[`can_core_pc_tx_trigger`](#can_core_pc_tx_trigger)                                                   | 0x2b8    |        4 | Auto-extracted signal pc_tx_trigger from can_core.vhd                          |
+| can_bus.[`can_core_pc_rx_trigger`](#can_core_pc_rx_trigger)                                                   | 0x2bc    |        4 | Auto-extracted signal pc_rx_trigger from can_core.vhd                          |
+| can_bus.[`can_core_pc_tx_data_nbs`](#can_core_pc_tx_data_nbs)                                                 | 0x2c0    |        4 | Auto-extracted signal pc_tx_data_nbs from can_core.vhd                         |
+| can_bus.[`can_core_pc_rx_data_nbs`](#can_core_pc_rx_data_nbs)                                                 | 0x2c4    |        4 | Auto-extracted signal pc_rx_data_nbs from can_core.vhd                         |
+| can_bus.[`can_core_crc_data_tx_wbs`](#can_core_crc_data_tx_wbs)                                               | 0x2c8    |        4 | Auto-extracted signal crc_data_tx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_tx_nbs`](#can_core_crc_data_tx_nbs)                                               | 0x2cc    |        4 | Auto-extracted signal crc_data_tx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_rx_wbs`](#can_core_crc_data_rx_wbs)                                               | 0x2d0    |        4 | Auto-extracted signal crc_data_rx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_data_rx_nbs`](#can_core_crc_data_rx_nbs)                                               | 0x2d4    |        4 | Auto-extracted signal crc_data_rx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_tx_wbs`](#can_core_crc_trig_tx_wbs)                                               | 0x2d8    |        4 | Auto-extracted signal crc_trig_tx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_tx_nbs`](#can_core_crc_trig_tx_nbs)                                               | 0x2dc    |        4 | Auto-extracted signal crc_trig_tx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_rx_wbs`](#can_core_crc_trig_rx_wbs)                                               | 0x2e0    |        4 | Auto-extracted signal crc_trig_rx_wbs from can_core.vhd                        |
+| can_bus.[`can_core_crc_trig_rx_nbs`](#can_core_crc_trig_rx_nbs)                                               | 0x2e4    |        4 | Auto-extracted signal crc_trig_rx_nbs from can_core.vhd                        |
+| can_bus.[`can_core_bst_data_in`](#can_core_bst_data_in)                                                       | 0x2e8    |        4 | Auto-extracted signal bst_data_in from can_core.vhd                            |
+| can_bus.[`can_core_bst_data_out`](#can_core_bst_data_out)                                                     | 0x2ec    |        4 | Auto-extracted signal bst_data_out from can_core.vhd                           |
+| can_bus.[`can_core_bst_trigger`](#can_core_bst_trigger)                                                       | 0x2f0    |        4 | Auto-extracted signal bst_trigger from can_core.vhd                            |
+| can_bus.[`can_core_data_halt`](#can_core_data_halt)                                                           | 0x2f4    |        4 | Auto-extracted signal data_halt from can_core.vhd                              |
+| can_bus.[`can_core_bds_data_in`](#can_core_bds_data_in)                                                       | 0x2f8    |        4 | Auto-extracted signal bds_data_in from can_core.vhd                            |
+| can_bus.[`can_core_bds_data_out`](#can_core_bds_data_out)                                                     | 0x2fc    |        4 | Auto-extracted signal bds_data_out from can_core.vhd                           |
+| can_bus.[`can_core_bds_trigger`](#can_core_bds_trigger)                                                       | 0x300    |        4 | Auto-extracted signal bds_trigger from can_core.vhd                            |
+| can_bus.[`can_core_destuffed`](#can_core_destuffed)                                                           | 0x304    |        4 | Auto-extracted signal destuffed from can_core.vhd                              |
+| can_bus.[`can_core_tx_ctr`](#can_core_tx_ctr)                                                                 | 0x308    |        4 | Auto-extracted signal tx_ctr from can_core.vhd                                 |
+| can_bus.[`can_core_rx_ctr`](#can_core_rx_ctr)                                                                 | 0x30c    |        4 | Auto-extracted signal rx_ctr from can_core.vhd                                 |
+| can_bus.[`can_core_tx_data_wbs_i`](#can_core_tx_data_wbs_i)                                                   | 0x310    |        4 | Auto-extracted signal tx_data_wbs_i from can_core.vhd                          |
+| can_bus.[`can_core_lpb_dominant`](#can_core_lpb_dominant)                                                     | 0x314    |        4 | Auto-extracted signal lpb_dominant from can_core.vhd                           |
+| can_bus.[`can_core_form_err`](#can_core_form_err)                                                             | 0x318    |        4 | Auto-extracted signal form_err from can_core.vhd                               |
+| can_bus.[`can_core_ack_err`](#can_core_ack_err)                                                               | 0x31c    |        4 | Auto-extracted signal ack_err from can_core.vhd                                |
+| can_bus.[`can_core_crc_err`](#can_core_crc_err)                                                               | 0x320    |        4 | Auto-extracted signal crc_err from can_core.vhd                                |
+| can_bus.[`can_core_is_arbitration`](#can_core_is_arbitration)                                                 | 0x324    |        4 | Auto-extracted signal is_arbitration from can_core.vhd                         |
+| can_bus.[`can_core_is_control`](#can_core_is_control)                                                         | 0x328    |        4 | Auto-extracted signal is_control from can_core.vhd                             |
+| can_bus.[`can_core_is_data`](#can_core_is_data)                                                               | 0x32c    |        4 | Auto-extracted signal is_data from can_core.vhd                                |
+| can_bus.[`can_core_is_stuff_count`](#can_core_is_stuff_count)                                                 | 0x330    |        4 | Auto-extracted signal is_stuff_count from can_core.vhd                         |
+| can_bus.[`can_core_is_crc`](#can_core_is_crc)                                                                 | 0x334    |        4 | Auto-extracted signal is_crc from can_core.vhd                                 |
+| can_bus.[`can_core_is_crc_delim`](#can_core_is_crc_delim)                                                     | 0x338    |        4 | Auto-extracted signal is_crc_delim from can_core.vhd                           |
+| can_bus.[`can_core_is_ack_field`](#can_core_is_ack_field)                                                     | 0x33c    |        4 | Auto-extracted signal is_ack_field from can_core.vhd                           |
+| can_bus.[`can_core_is_ack_delim`](#can_core_is_ack_delim)                                                     | 0x340    |        4 | Auto-extracted signal is_ack_delim from can_core.vhd                           |
+| can_bus.[`can_core_is_eof`](#can_core_is_eof)                                                                 | 0x344    |        4 | Auto-extracted signal is_eof from can_core.vhd                                 |
+| can_bus.[`can_core_is_err_frm`](#can_core_is_err_frm)                                                         | 0x348    |        4 | Auto-extracted signal is_err_frm from can_core.vhd                             |
+| can_bus.[`can_core_is_intermission`](#can_core_is_intermission)                                               | 0x34c    |        4 | Auto-extracted signal is_intermission from can_core.vhd                        |
+| can_bus.[`can_core_is_suspend`](#can_core_is_suspend)                                                         | 0x350    |        4 | Auto-extracted signal is_suspend from can_core.vhd                             |
+| can_bus.[`can_core_is_overload_i`](#can_core_is_overload_i)                                                   | 0x354    |        4 | Auto-extracted signal is_overload_i from can_core.vhd                          |
+| can_bus.[`can_core_is_sof`](#can_core_is_sof)                                                                 | 0x358    |        4 | Auto-extracted signal is_sof from can_core.vhd                                 |
+| can_bus.[`can_core_sof_pulse_i`](#can_core_sof_pulse_i)                                                       | 0x35c    |        4 | Auto-extracted signal sof_pulse_i from can_core.vhd                            |
+| can_bus.[`can_core_load_init_vect`](#can_core_load_init_vect)                                                 | 0x360    |        4 | Auto-extracted signal load_init_vect from can_core.vhd                         |
+| can_bus.[`can_core_retr_ctr_i`](#can_core_retr_ctr_i)                                                         | 0x364    |        4 | Auto-extracted signal retr_ctr_i from can_core.vhd                             |
+| can_bus.[`can_core_decrement_rec`](#can_core_decrement_rec)                                                   | 0x368    |        4 | Auto-extracted signal decrement_rec from can_core.vhd                          |
+| can_bus.[`can_core_bit_err_after_ack_err`](#can_core_bit_err_after_ack_err)                                   | 0x36c    |        4 | Auto-extracted signal bit_err_after_ack_err from can_core.vhd                  |
+| can_bus.[`can_core_is_pexs`](#can_core_is_pexs)                                                               | 0x370    |        4 | Auto-extracted signal is_pexs from can_core.vhd                                |
+| can_bus.[`can_crc_drv_fd_type`](#can_crc_drv_fd_type)                                                         | 0x374    |        4 | Auto-extracted signal drv_fd_type from can_crc.vhd                             |
+| can_bus.[`can_crc_init_vect_15`](#can_crc_init_vect_15)                                                       | 0x378    |        4 | Auto-extracted signal init_vect_15 from can_crc.vhd                            |
+| can_bus.[`can_crc_init_vect_17`](#can_crc_init_vect_17)                                                       | 0x37c    |        4 | Auto-extracted signal init_vect_17 from can_crc.vhd                            |
+| can_bus.[`can_crc_init_vect_21`](#can_crc_init_vect_21)                                                       | 0x380    |        4 | Auto-extracted signal init_vect_21 from can_crc.vhd                            |
+| can_bus.[`can_crc_crc_17_21_data_in`](#can_crc_crc_17_21_data_in)                                             | 0x384    |        4 | Auto-extracted signal crc_17_21_data_in from can_crc.vhd                       |
+| can_bus.[`can_crc_crc_17_21_trigger`](#can_crc_crc_17_21_trigger)                                             | 0x388    |        4 | Auto-extracted signal crc_17_21_trigger from can_crc.vhd                       |
+| can_bus.[`can_crc_crc_15_data_in`](#can_crc_crc_15_data_in)                                                   | 0x38c    |        4 | Auto-extracted signal crc_15_data_in from can_crc.vhd                          |
+| can_bus.[`can_crc_crc_15_trigger`](#can_crc_crc_15_trigger)                                                   | 0x390    |        4 | Auto-extracted signal crc_15_trigger from can_crc.vhd                          |
+| can_bus.[`can_crc_crc_ena_15`](#can_crc_crc_ena_15)                                                           | 0x394    |        4 | Auto-extracted signal crc_ena_15 from can_crc.vhd                              |
+| can_bus.[`can_crc_crc_ena_17_21`](#can_crc_crc_ena_17_21)                                                     | 0x398    |        4 | Auto-extracted signal crc_ena_17_21 from can_crc.vhd                           |
+| can_bus.[`can_top_ahb_ctu_can_data_in`](#can_top_ahb_ctu_can_data_in)                                         | 0x39c    |        4 | Auto-extracted signal ctu_can_data_in from can_top_ahb.vhd                     |
+| can_bus.[`can_top_ahb_ctu_can_data_out`](#can_top_ahb_ctu_can_data_out)                                       | 0x3a0    |        4 | Auto-extracted signal ctu_can_data_out from can_top_ahb.vhd                    |
+| can_bus.[`can_top_ahb_ctu_can_adress`](#can_top_ahb_ctu_can_adress)                                           | 0x3a4    |        4 | Auto-extracted signal ctu_can_adress from can_top_ahb.vhd                      |
+| can_bus.[`can_top_ahb_ctu_can_scs`](#can_top_ahb_ctu_can_scs)                                                 | 0x3a8    |        4 | Auto-extracted signal ctu_can_scs from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_srd`](#can_top_ahb_ctu_can_srd)                                                 | 0x3ac    |        4 | Auto-extracted signal ctu_can_srd from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_swr`](#can_top_ahb_ctu_can_swr)                                                 | 0x3b0    |        4 | Auto-extracted signal ctu_can_swr from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_ctu_can_sbe`](#can_top_ahb_ctu_can_sbe)                                                 | 0x3b4    |        4 | Auto-extracted signal ctu_can_sbe from can_top_ahb.vhd                         |
+| can_bus.[`can_top_ahb_res_n_out_i`](#can_top_ahb_res_n_out_i)                                                 | 0x3b8    |        4 | Auto-extracted signal res_n_out_i from can_top_ahb.vhd                         |
+| can_bus.[`can_top_apb_reg_data_in`](#can_top_apb_reg_data_in)                                                 | 0x3bc    |        4 | Auto-extracted signal reg_data_in from can_top_apb.vhd                         |
+| can_bus.[`can_top_apb_reg_data_out`](#can_top_apb_reg_data_out)                                               | 0x3c0    |        4 | Auto-extracted signal reg_data_out from can_top_apb.vhd                        |
+| can_bus.[`can_top_apb_reg_addr`](#can_top_apb_reg_addr)                                                       | 0x3c4    |        4 | Auto-extracted signal reg_addr from can_top_apb.vhd                            |
+| can_bus.[`can_top_apb_reg_be`](#can_top_apb_reg_be)                                                           | 0x3c8    |        4 | Auto-extracted signal reg_be from can_top_apb.vhd                              |
+| can_bus.[`can_top_apb_reg_rden`](#can_top_apb_reg_rden)                                                       | 0x3cc    |        4 | Auto-extracted signal reg_rden from can_top_apb.vhd                            |
+| can_bus.[`can_top_apb_reg_wren`](#can_top_apb_reg_wren)                                                       | 0x3d0    |        4 | Auto-extracted signal reg_wren from can_top_apb.vhd                            |
+| can_bus.[`can_top_level_drv_bus`](#can_top_level_drv_bus)                                                     | 0x3d4    |        4 | Auto-extracted signal drv_bus from can_top_level.vhd                           |
+| can_bus.[`can_top_level_stat_bus`](#can_top_level_stat_bus)                                                   | 0x3d8    |        4 | Auto-extracted signal stat_bus from can_top_level.vhd                          |
+| can_bus.[`can_top_level_res_n_sync`](#can_top_level_res_n_sync)                                               | 0x3dc    |        4 | Auto-extracted signal res_n_sync from can_top_level.vhd                        |
+| can_bus.[`can_top_level_res_core_n`](#can_top_level_res_core_n)                                               | 0x3e0    |        4 | Auto-extracted signal res_core_n from can_top_level.vhd                        |
+| can_bus.[`can_top_level_res_soft_n`](#can_top_level_res_soft_n)                                               | 0x3e4    |        4 | Auto-extracted signal res_soft_n from can_top_level.vhd                        |
+| can_bus.[`can_top_level_sp_control`](#can_top_level_sp_control)                                               | 0x3e8    |        4 | Auto-extracted signal sp_control from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rx_buf_size`](#can_top_level_rx_buf_size)                                             | 0x3ec    |        4 | Auto-extracted signal rx_buf_size from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_full`](#can_top_level_rx_full)                                                     | 0x3f0    |        4 | Auto-extracted signal rx_full from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rx_empty`](#can_top_level_rx_empty)                                                   | 0x3f4    |        4 | Auto-extracted signal rx_empty from can_top_level.vhd                          |
+| can_bus.[`can_top_level_rx_frame_count`](#can_top_level_rx_frame_count)                                       | 0x3f8    |        4 | Auto-extracted signal rx_frame_count from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rx_mem_free`](#can_top_level_rx_mem_free)                                             | 0x3fc    |        4 | Auto-extracted signal rx_mem_free from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_read_pointer`](#can_top_level_rx_read_pointer)                                     | 0x400    |        4 | Auto-extracted signal rx_read_pointer from can_top_level.vhd                   |
+| can_bus.[`can_top_level_rx_write_pointer`](#can_top_level_rx_write_pointer)                                   | 0x404    |        4 | Auto-extracted signal rx_write_pointer from can_top_level.vhd                  |
+| can_bus.[`can_top_level_rx_data_overrun`](#can_top_level_rx_data_overrun)                                     | 0x408    |        4 | Auto-extracted signal rx_data_overrun from can_top_level.vhd                   |
+| can_bus.[`can_top_level_rx_read_buff`](#can_top_level_rx_read_buff)                                           | 0x40c    |        4 | Auto-extracted signal rx_read_buff from can_top_level.vhd                      |
+| can_bus.[`can_top_level_rx_mof`](#can_top_level_rx_mof)                                                       | 0x410    |        4 | Auto-extracted signal rx_mof from can_top_level.vhd                            |
+| can_bus.[`can_top_level_txtb_port_a_data`](#can_top_level_txtb_port_a_data)                                   | 0x414    |        4 | Auto-extracted signal txtb_port_a_data from can_top_level.vhd                  |
+| can_bus.[`can_top_level_txtb_port_a_address`](#can_top_level_txtb_port_a_address)                             | 0x418    |        4 | Auto-extracted signal txtb_port_a_address from can_top_level.vhd               |
+| can_bus.[`can_top_level_txtb_port_a_cs`](#can_top_level_txtb_port_a_cs)                                       | 0x41c    |        4 | Auto-extracted signal txtb_port_a_cs from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_port_a_be`](#can_top_level_txtb_port_a_be)                                       | 0x420    |        4 | Auto-extracted signal txtb_port_a_be from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_sw_cmd_index`](#can_top_level_txtb_sw_cmd_index)                                 | 0x424    |        4 | Auto-extracted signal txtb_sw_cmd_index from can_top_level.vhd                 |
+| can_bus.[`can_top_level_txt_buf_failed_bof`](#can_top_level_txt_buf_failed_bof)                               | 0x428    |        4 | Auto-extracted signal txt_buf_failed_bof from can_top_level.vhd                |
+| can_bus.[`can_top_level_int_vector`](#can_top_level_int_vector)                                               | 0x42c    |        4 | Auto-extracted signal int_vector from can_top_level.vhd                        |
+| can_bus.[`can_top_level_int_ena`](#can_top_level_int_ena)                                                     | 0x430    |        4 | Auto-extracted signal int_ena from can_top_level.vhd                           |
+| can_bus.[`can_top_level_int_mask`](#can_top_level_int_mask)                                                   | 0x434    |        4 | Auto-extracted signal int_mask from can_top_level.vhd                          |
+| can_bus.[`can_top_level_rec_ident`](#can_top_level_rec_ident)                                                 | 0x438    |        4 | Auto-extracted signal rec_ident from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rec_dlc`](#can_top_level_rec_dlc)                                                     | 0x43c    |        4 | Auto-extracted signal rec_dlc from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rec_ident_type`](#can_top_level_rec_ident_type)                                       | 0x440    |        4 | Auto-extracted signal rec_ident_type from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rec_frame_type`](#can_top_level_rec_frame_type)                                       | 0x444    |        4 | Auto-extracted signal rec_frame_type from can_top_level.vhd                    |
+| can_bus.[`can_top_level_rec_is_rtr`](#can_top_level_rec_is_rtr)                                               | 0x448    |        4 | Auto-extracted signal rec_is_rtr from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rec_brs`](#can_top_level_rec_brs)                                                     | 0x44c    |        4 | Auto-extracted signal rec_brs from can_top_level.vhd                           |
+| can_bus.[`can_top_level_rec_esi`](#can_top_level_rec_esi)                                                     | 0x450    |        4 | Auto-extracted signal rec_esi from can_top_level.vhd                           |
+| can_bus.[`can_top_level_store_data_word`](#can_top_level_store_data_word)                                     | 0x454    |        4 | Auto-extracted signal store_data_word from can_top_level.vhd                   |
+| can_bus.[`can_top_level_sof_pulse`](#can_top_level_sof_pulse)                                                 | 0x458    |        4 | Auto-extracted signal sof_pulse from can_top_level.vhd                         |
+| can_bus.[`can_top_level_store_metadata`](#can_top_level_store_metadata)                                       | 0x45c    |        4 | Auto-extracted signal store_metadata from can_top_level.vhd                    |
+| can_bus.[`can_top_level_store_data`](#can_top_level_store_data)                                               | 0x460    |        4 | Auto-extracted signal store_data from can_top_level.vhd                        |
+| can_bus.[`can_top_level_rec_valid`](#can_top_level_rec_valid)                                                 | 0x464    |        4 | Auto-extracted signal rec_valid from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rec_abort`](#can_top_level_rec_abort)                                                 | 0x468    |        4 | Auto-extracted signal rec_abort from can_top_level.vhd                         |
+| can_bus.[`can_top_level_store_metadata_f`](#can_top_level_store_metadata_f)                                   | 0x46c    |        4 | Auto-extracted signal store_metadata_f from can_top_level.vhd                  |
+| can_bus.[`can_top_level_store_data_f`](#can_top_level_store_data_f)                                           | 0x470    |        4 | Auto-extracted signal store_data_f from can_top_level.vhd                      |
+| can_bus.[`can_top_level_rec_valid_f`](#can_top_level_rec_valid_f)                                             | 0x474    |        4 | Auto-extracted signal rec_valid_f from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rec_abort_f`](#can_top_level_rec_abort_f)                                             | 0x478    |        4 | Auto-extracted signal rec_abort_f from can_top_level.vhd                       |
+| can_bus.[`can_top_level_txtb_hw_cmd_int`](#can_top_level_txtb_hw_cmd_int)                                     | 0x47c    |        4 | Auto-extracted signal txtb_hw_cmd_int from can_top_level.vhd                   |
+| can_bus.[`can_top_level_is_bus_off`](#can_top_level_is_bus_off)                                               | 0x480    |        4 | Auto-extracted signal is_bus_off from can_top_level.vhd                        |
+| can_bus.[`can_top_level_txtb_available`](#can_top_level_txtb_available)                                       | 0x484    |        4 | Auto-extracted signal txtb_available from can_top_level.vhd                    |
+| can_bus.[`can_top_level_txtb_port_b_clk_en`](#can_top_level_txtb_port_b_clk_en)                               | 0x488    |        4 | Auto-extracted signal txtb_port_b_clk_en from can_top_level.vhd                |
+| can_bus.[`can_top_level_tran_dlc`](#can_top_level_tran_dlc)                                                   | 0x48c    |        4 | Auto-extracted signal tran_dlc from can_top_level.vhd                          |
+| can_bus.[`can_top_level_tran_is_rtr`](#can_top_level_tran_is_rtr)                                             | 0x490    |        4 | Auto-extracted signal tran_is_rtr from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tran_ident_type`](#can_top_level_tran_ident_type)                                     | 0x494    |        4 | Auto-extracted signal tran_ident_type from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_frame_type`](#can_top_level_tran_frame_type)                                     | 0x498    |        4 | Auto-extracted signal tran_frame_type from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_brs`](#can_top_level_tran_brs)                                                   | 0x49c    |        4 | Auto-extracted signal tran_brs from can_top_level.vhd                          |
+| can_bus.[`can_top_level_tran_identifier`](#can_top_level_tran_identifier)                                     | 0x4a0    |        4 | Auto-extracted signal tran_identifier from can_top_level.vhd                   |
+| can_bus.[`can_top_level_tran_word`](#can_top_level_tran_word)                                                 | 0x4a4    |        4 | Auto-extracted signal tran_word from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tran_frame_valid`](#can_top_level_tran_frame_valid)                                   | 0x4a8    |        4 | Auto-extracted signal tran_frame_valid from can_top_level.vhd                  |
+| can_bus.[`can_top_level_txtb_changed`](#can_top_level_txtb_changed)                                           | 0x4ac    |        4 | Auto-extracted signal txtb_changed from can_top_level.vhd                      |
+| can_bus.[`can_top_level_txtb_clk_en`](#can_top_level_txtb_clk_en)                                             | 0x4b0    |        4 | Auto-extracted signal txtb_clk_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_err_detected`](#can_top_level_err_detected)                                           | 0x4b4    |        4 | Auto-extracted signal err_detected from can_top_level.vhd                      |
+| can_bus.[`can_top_level_fcs_changed`](#can_top_level_fcs_changed)                                             | 0x4b8    |        4 | Auto-extracted signal fcs_changed from can_top_level.vhd                       |
+| can_bus.[`can_top_level_err_warning_limit`](#can_top_level_err_warning_limit)                                 | 0x4bc    |        4 | Auto-extracted signal err_warning_limit from can_top_level.vhd                 |
+| can_bus.[`can_top_level_arbitration_lost`](#can_top_level_arbitration_lost)                                   | 0x4c0    |        4 | Auto-extracted signal arbitration_lost from can_top_level.vhd                  |
+| can_bus.[`can_top_level_tran_valid`](#can_top_level_tran_valid)                                               | 0x4c4    |        4 | Auto-extracted signal tran_valid from can_top_level.vhd                        |
+| can_bus.[`can_top_level_br_shifted`](#can_top_level_br_shifted)                                               | 0x4c8    |        4 | Auto-extracted signal br_shifted from can_top_level.vhd                        |
+| can_bus.[`can_top_level_is_overload`](#can_top_level_is_overload)                                             | 0x4cc    |        4 | Auto-extracted signal is_overload from can_top_level.vhd                       |
+| can_bus.[`can_top_level_rx_triggers`](#can_top_level_rx_triggers)                                             | 0x4d0    |        4 | Auto-extracted signal rx_triggers from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tx_trigger`](#can_top_level_tx_trigger)                                               | 0x4d4    |        4 | Auto-extracted signal tx_trigger from can_top_level.vhd                        |
+| can_bus.[`can_top_level_sync_control`](#can_top_level_sync_control)                                           | 0x4d8    |        4 | Auto-extracted signal sync_control from can_top_level.vhd                      |
+| can_bus.[`can_top_level_no_pos_resync`](#can_top_level_no_pos_resync)                                         | 0x4dc    |        4 | Auto-extracted signal no_pos_resync from can_top_level.vhd                     |
+| can_bus.[`can_top_level_nbt_ctrs_en`](#can_top_level_nbt_ctrs_en)                                             | 0x4e0    |        4 | Auto-extracted signal nbt_ctrs_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_dbt_ctrs_en`](#can_top_level_dbt_ctrs_en)                                             | 0x4e4    |        4 | Auto-extracted signal dbt_ctrs_en from can_top_level.vhd                       |
+| can_bus.[`can_top_level_trv_delay`](#can_top_level_trv_delay)                                                 | 0x4e8    |        4 | Auto-extracted signal trv_delay from can_top_level.vhd                         |
+| can_bus.[`can_top_level_rx_data_wbs`](#can_top_level_rx_data_wbs)                                             | 0x4ec    |        4 | Auto-extracted signal rx_data_wbs from can_top_level.vhd                       |
+| can_bus.[`can_top_level_tx_data_wbs`](#can_top_level_tx_data_wbs)                                             | 0x4f0    |        4 | Auto-extracted signal tx_data_wbs from can_top_level.vhd                       |
+| can_bus.[`can_top_level_ssp_reset`](#can_top_level_ssp_reset)                                                 | 0x4f4    |        4 | Auto-extracted signal ssp_reset from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tran_delay_meas`](#can_top_level_tran_delay_meas)                                     | 0x4f8    |        4 | Auto-extracted signal tran_delay_meas from can_top_level.vhd                   |
+| can_bus.[`can_top_level_bit_err`](#can_top_level_bit_err)                                                     | 0x4fc    |        4 | Auto-extracted signal bit_err from can_top_level.vhd                           |
+| can_bus.[`can_top_level_sample_sec`](#can_top_level_sample_sec)                                               | 0x500    |        4 | Auto-extracted signal sample_sec from can_top_level.vhd                        |
+| can_bus.[`can_top_level_btmc_reset`](#can_top_level_btmc_reset)                                               | 0x504    |        4 | Auto-extracted signal btmc_reset from can_top_level.vhd                        |
+| can_bus.[`can_top_level_dbt_measure_start`](#can_top_level_dbt_measure_start)                                 | 0x508    |        4 | Auto-extracted signal dbt_measure_start from can_top_level.vhd                 |
+| can_bus.[`can_top_level_gen_first_ssp`](#can_top_level_gen_first_ssp)                                         | 0x50c    |        4 | Auto-extracted signal gen_first_ssp from can_top_level.vhd                     |
+| can_bus.[`can_top_level_sync_edge`](#can_top_level_sync_edge)                                                 | 0x510    |        4 | Auto-extracted signal sync_edge from can_top_level.vhd                         |
+| can_bus.[`can_top_level_tq_edge`](#can_top_level_tq_edge)                                                     | 0x514    |        4 | Auto-extracted signal tq_edge from can_top_level.vhd                           |
+| can_bus.[`can_top_level_tst_rdata_rx_buf`](#can_top_level_tst_rdata_rx_buf)                                   | 0x518    |        4 | Auto-extracted signal tst_rdata_rx_buf from can_top_level.vhd                  |
+| can_bus.[`clk_gate_clk_en_q`](#clk_gate_clk_en_q)                                                             | 0x51c    |        4 | Auto-extracted signal clk_en_q from clk_gate.vhd                               |
+| can_bus.[`control_counter_ctrl_ctr_ce`](#control_counter_ctrl_ctr_ce)                                         | 0x520    |        4 | Auto-extracted signal ctrl_ctr_ce from control_counter.vhd                     |
+| can_bus.[`control_counter_compl_ctr_ce`](#control_counter_compl_ctr_ce)                                       | 0x524    |        4 | Auto-extracted signal compl_ctr_ce from control_counter.vhd                    |
+| can_bus.[`control_registers_reg_map_reg_sel`](#control_registers_reg_map_reg_sel)                             | 0x528    |        4 | Auto-extracted signal reg_sel from control_registers_reg_map.vhd               |
+| can_bus.[`control_registers_reg_map_read_data_mux_in`](#control_registers_reg_map_read_data_mux_in)           | 0x52c    |        4 | Auto-extracted signal read_data_mux_in from control_registers_reg_map.vhd      |
+| can_bus.[`control_registers_reg_map_read_data_mask_n`](#control_registers_reg_map_read_data_mask_n)           | 0x530    |        4 | Auto-extracted signal read_data_mask_n from control_registers_reg_map.vhd      |
+| can_bus.[`control_registers_reg_map_read_mux_ena`](#control_registers_reg_map_read_mux_ena)                   | 0x534    |        4 | Auto-extracted signal read_mux_ena from control_registers_reg_map.vhd          |
+| can_bus.[`crc_calc_crc_q`](#crc_calc_crc_q)                                                                   | 0x538    |        4 | Auto-extracted signal crc_q from crc_calc.vhd                                  |
+| can_bus.[`crc_calc_crc_nxt`](#crc_calc_crc_nxt)                                                               | 0x53c    |        4 | Auto-extracted signal crc_nxt from crc_calc.vhd                                |
+| can_bus.[`crc_calc_crc_shift`](#crc_calc_crc_shift)                                                           | 0x540    |        4 | Auto-extracted signal crc_shift from crc_calc.vhd                              |
+| can_bus.[`crc_calc_crc_shift_n_xor`](#crc_calc_crc_shift_n_xor)                                               | 0x544    |        4 | Auto-extracted signal crc_shift_n_xor from crc_calc.vhd                        |
+| can_bus.[`crc_calc_crc_d`](#crc_calc_crc_d)                                                                   | 0x548    |        4 | Auto-extracted signal crc_d from crc_calc.vhd                                  |
+| can_bus.[`crc_calc_crc_ce`](#crc_calc_crc_ce)                                                                 | 0x54c    |        4 | Auto-extracted signal crc_ce from crc_calc.vhd                                 |
+| can_bus.[`data_edge_detector_rx_data_prev`](#data_edge_detector_rx_data_prev)                                 | 0x550    |        4 | Auto-extracted signal rx_data_prev from data_edge_detector.vhd                 |
+| can_bus.[`data_edge_detector_tx_data_prev`](#data_edge_detector_tx_data_prev)                                 | 0x554    |        4 | Auto-extracted signal tx_data_prev from data_edge_detector.vhd                 |
+| can_bus.[`data_edge_detector_rx_data_sync_prev`](#data_edge_detector_rx_data_sync_prev)                       | 0x558    |        4 | Auto-extracted signal rx_data_sync_prev from data_edge_detector.vhd            |
+| can_bus.[`data_edge_detector_rx_edge_i`](#data_edge_detector_rx_edge_i)                                       | 0x55c    |        4 | Auto-extracted signal rx_edge_i from data_edge_detector.vhd                    |
+| can_bus.[`data_edge_detector_tx_edge_i`](#data_edge_detector_tx_edge_i)                                       | 0x560    |        4 | Auto-extracted signal tx_edge_i from data_edge_detector.vhd                    |
+| can_bus.[`data_mux_sel_data`](#data_mux_sel_data)                                                             | 0x564    |        4 | Auto-extracted signal sel_data from data_mux.vhd                               |
+| can_bus.[`data_mux_saturated_data`](#data_mux_saturated_data)                                                 | 0x568    |        4 | Auto-extracted signal saturated_data from data_mux.vhd                         |
+| can_bus.[`data_mux_masked_data`](#data_mux_masked_data)                                                       | 0x56c    |        4 | Auto-extracted signal masked_data from data_mux.vhd                            |
+| can_bus.[`dlc_decoder_data_len_8_to_64`](#dlc_decoder_data_len_8_to_64)                                       | 0x570    |        4 | Auto-extracted signal data_len_8_to_64 from dlc_decoder.vhd                    |
+| can_bus.[`dlc_decoder_data_len_can_2_0`](#dlc_decoder_data_len_can_2_0)                                       | 0x574    |        4 | Auto-extracted signal data_len_can_2_0 from dlc_decoder.vhd                    |
+| can_bus.[`dlc_decoder_data_len_can_fd`](#dlc_decoder_data_len_can_fd)                                         | 0x578    |        4 | Auto-extracted signal data_len_can_fd from dlc_decoder.vhd                     |
+| can_bus.[`endian_swapper_swapped`](#endian_swapper_swapped)                                                   | 0x57c    |        4 | Auto-extracted signal swapped from endian_swapper.vhd                          |
+| can_bus.[`err_counters_tx_err_ctr_ce`](#err_counters_tx_err_ctr_ce)                                           | 0x580    |        4 | Auto-extracted signal tx_err_ctr_ce from err_counters.vhd                      |
+| can_bus.[`err_counters_rx_err_ctr_ce`](#err_counters_rx_err_ctr_ce)                                           | 0x584    |        4 | Auto-extracted signal rx_err_ctr_ce from err_counters.vhd                      |
+| can_bus.[`err_counters_modif_tx_ctr`](#err_counters_modif_tx_ctr)                                             | 0x588    |        4 | Auto-extracted signal modif_tx_ctr from err_counters.vhd                       |
+| can_bus.[`err_counters_modif_rx_ctr`](#err_counters_modif_rx_ctr)                                             | 0x58c    |        4 | Auto-extracted signal modif_rx_ctr from err_counters.vhd                       |
+| can_bus.[`err_counters_nom_err_ctr_ce`](#err_counters_nom_err_ctr_ce)                                         | 0x590    |        4 | Auto-extracted signal nom_err_ctr_ce from err_counters.vhd                     |
+| can_bus.[`err_counters_data_err_ctr_ce`](#err_counters_data_err_ctr_ce)                                       | 0x594    |        4 | Auto-extracted signal data_err_ctr_ce from err_counters.vhd                    |
+| can_bus.[`err_counters_res_err_ctrs_d`](#err_counters_res_err_ctrs_d)                                         | 0x598    |        4 | Auto-extracted signal res_err_ctrs_d from err_counters.vhd                     |
+| can_bus.[`err_counters_res_err_ctrs_q`](#err_counters_res_err_ctrs_q)                                         | 0x59c    |        4 | Auto-extracted signal res_err_ctrs_q from err_counters.vhd                     |
+| can_bus.[`err_counters_res_err_ctrs_q_scan`](#err_counters_res_err_ctrs_q_scan)                               | 0x5a0    |        4 | Auto-extracted signal res_err_ctrs_q_scan from err_counters.vhd                |
+| can_bus.[`err_detector_err_frm_req_i`](#err_detector_err_frm_req_i)                                           | 0x5a4    |        4 | Auto-extracted signal err_frm_req_i from err_detector.vhd                      |
+| can_bus.[`err_detector_err_type_d`](#err_detector_err_type_d)                                                 | 0x5a8    |        4 | Auto-extracted signal err_type_d from err_detector.vhd                         |
+| can_bus.[`err_detector_err_type_q`](#err_detector_err_type_q)                                                 | 0x5ac    |        4 | Auto-extracted signal err_type_q from err_detector.vhd                         |
+| can_bus.[`err_detector_err_pos_q`](#err_detector_err_pos_q)                                                   | 0x5b0    |        4 | Auto-extracted signal err_pos_q from err_detector.vhd                          |
+| can_bus.[`err_detector_form_err_i`](#err_detector_form_err_i)                                                 | 0x5b4    |        4 | Auto-extracted signal form_err_i from err_detector.vhd                         |
+| can_bus.[`err_detector_crc_match_c`](#err_detector_crc_match_c)                                               | 0x5b8    |        4 | Auto-extracted signal crc_match_c from err_detector.vhd                        |
+| can_bus.[`err_detector_crc_match_d`](#err_detector_crc_match_d)                                               | 0x5bc    |        4 | Auto-extracted signal crc_match_d from err_detector.vhd                        |
+| can_bus.[`err_detector_crc_match_q`](#err_detector_crc_match_q)                                               | 0x5c0    |        4 | Auto-extracted signal crc_match_q from err_detector.vhd                        |
+| can_bus.[`err_detector_dst_ctr_grey`](#err_detector_dst_ctr_grey)                                             | 0x5c4    |        4 | Auto-extracted signal dst_ctr_grey from err_detector.vhd                       |
+| can_bus.[`err_detector_dst_parity`](#err_detector_dst_parity)                                                 | 0x5c8    |        4 | Auto-extracted signal dst_parity from err_detector.vhd                         |
+| can_bus.[`err_detector_stuff_count_check`](#err_detector_stuff_count_check)                                   | 0x5cc    |        4 | Auto-extracted signal stuff_count_check from err_detector.vhd                  |
+| can_bus.[`err_detector_crc_15_ok`](#err_detector_crc_15_ok)                                                   | 0x5d0    |        4 | Auto-extracted signal crc_15_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_crc_17_ok`](#err_detector_crc_17_ok)                                                   | 0x5d4    |        4 | Auto-extracted signal crc_17_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_crc_21_ok`](#err_detector_crc_21_ok)                                                   | 0x5d8    |        4 | Auto-extracted signal crc_21_ok from err_detector.vhd                          |
+| can_bus.[`err_detector_stuff_count_ok`](#err_detector_stuff_count_ok)                                         | 0x5dc    |        4 | Auto-extracted signal stuff_count_ok from err_detector.vhd                     |
+| can_bus.[`err_detector_rx_crc_15`](#err_detector_rx_crc_15)                                                   | 0x5e0    |        4 | Auto-extracted signal rx_crc_15 from err_detector.vhd                          |
+| can_bus.[`err_detector_rx_crc_17`](#err_detector_rx_crc_17)                                                   | 0x5e4    |        4 | Auto-extracted signal rx_crc_17 from err_detector.vhd                          |
+| can_bus.[`err_detector_rx_crc_21`](#err_detector_rx_crc_21)                                                   | 0x5e8    |        4 | Auto-extracted signal rx_crc_21 from err_detector.vhd                          |
+| can_bus.[`fault_confinement_drv_ewl`](#fault_confinement_drv_ewl)                                             | 0x5ec    |        4 | Auto-extracted signal drv_ewl from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_erp`](#fault_confinement_drv_erp)                                             | 0x5f0    |        4 | Auto-extracted signal drv_erp from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_ctr_val`](#fault_confinement_drv_ctr_val)                                     | 0x5f4    |        4 | Auto-extracted signal drv_ctr_val from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_drv_ctr_sel`](#fault_confinement_drv_ctr_sel)                                     | 0x5f8    |        4 | Auto-extracted signal drv_ctr_sel from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_drv_ena`](#fault_confinement_drv_ena)                                             | 0x5fc    |        4 | Auto-extracted signal drv_ena from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_tx_err_ctr_i`](#fault_confinement_tx_err_ctr_i)                                   | 0x600    |        4 | Auto-extracted signal tx_err_ctr_i from fault_confinement.vhd                  |
+| can_bus.[`fault_confinement_rx_err_ctr_i`](#fault_confinement_rx_err_ctr_i)                                   | 0x604    |        4 | Auto-extracted signal rx_err_ctr_i from fault_confinement.vhd                  |
+| can_bus.[`fault_confinement_inc_one`](#fault_confinement_inc_one)                                             | 0x608    |        4 | Auto-extracted signal inc_one from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_inc_eight`](#fault_confinement_inc_eight)                                         | 0x60c    |        4 | Auto-extracted signal inc_eight from fault_confinement.vhd                     |
+| can_bus.[`fault_confinement_dec_one`](#fault_confinement_dec_one)                                             | 0x610    |        4 | Auto-extracted signal dec_one from fault_confinement.vhd                       |
+| can_bus.[`fault_confinement_drv_rom_ena`](#fault_confinement_drv_rom_ena)                                     | 0x614    |        4 | Auto-extracted signal drv_rom_ena from fault_confinement.vhd                   |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_erp`](#fault_confinement_fsm_tx_err_ctr_mt_erp)                 | 0x618    |        4 | Auto-extracted signal tx_err_ctr_mt_erp from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_rx_err_ctr_mt_erp`](#fault_confinement_fsm_rx_err_ctr_mt_erp)                 | 0x61c    |        4 | Auto-extracted signal rx_err_ctr_mt_erp from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_ewl`](#fault_confinement_fsm_tx_err_ctr_mt_ewl)                 | 0x620    |        4 | Auto-extracted signal tx_err_ctr_mt_ewl from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_rx_err_ctr_mt_ewl`](#fault_confinement_fsm_rx_err_ctr_mt_ewl)                 | 0x624    |        4 | Auto-extracted signal rx_err_ctr_mt_ewl from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_tx_err_ctr_mt_255`](#fault_confinement_fsm_tx_err_ctr_mt_255)                 | 0x628    |        4 | Auto-extracted signal tx_err_ctr_mt_255 from fault_confinement_fsm.vhd         |
+| can_bus.[`fault_confinement_fsm_err_warning_limit_d`](#fault_confinement_fsm_err_warning_limit_d)             | 0x62c    |        4 | Auto-extracted signal err_warning_limit_d from fault_confinement_fsm.vhd       |
+| can_bus.[`fault_confinement_fsm_err_warning_limit_q`](#fault_confinement_fsm_err_warning_limit_q)             | 0x630    |        4 | Auto-extracted signal err_warning_limit_q from fault_confinement_fsm.vhd       |
+| can_bus.[`fault_confinement_fsm_fc_fsm_res_d`](#fault_confinement_fsm_fc_fsm_res_d)                           | 0x634    |        4 | Auto-extracted signal fc_fsm_res_d from fault_confinement_fsm.vhd              |
+| can_bus.[`fault_confinement_fsm_fc_fsm_res_q`](#fault_confinement_fsm_fc_fsm_res_q)                           | 0x638    |        4 | Auto-extracted signal fc_fsm_res_q from fault_confinement_fsm.vhd              |
+| can_bus.[`fault_confinement_rules_inc_one_i`](#fault_confinement_rules_inc_one_i)                             | 0x63c    |        4 | Auto-extracted signal inc_one_i from fault_confinement_rules.vhd               |
+| can_bus.[`fault_confinement_rules_inc_eight_i`](#fault_confinement_rules_inc_eight_i)                         | 0x640    |        4 | Auto-extracted signal inc_eight_i from fault_confinement_rules.vhd             |
+| can_bus.[`frame_filters_drv_filter_A_mask`](#frame_filters_drv_filter_a_mask)                                 | 0x644    |        4 | Auto-extracted signal drv_filter_A_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_A_ctrl`](#frame_filters_drv_filter_a_ctrl)                                 | 0x648    |        4 | Auto-extracted signal drv_filter_A_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_A_bits`](#frame_filters_drv_filter_a_bits)                                 | 0x64c    |        4 | Auto-extracted signal drv_filter_A_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_A_valid`](#frame_filters_int_filter_a_valid)                               | 0x650    |        4 | Auto-extracted signal int_filter_A_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_B_mask`](#frame_filters_drv_filter_b_mask)                                 | 0x654    |        4 | Auto-extracted signal drv_filter_B_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_B_ctrl`](#frame_filters_drv_filter_b_ctrl)                                 | 0x658    |        4 | Auto-extracted signal drv_filter_B_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_B_bits`](#frame_filters_drv_filter_b_bits)                                 | 0x65c    |        4 | Auto-extracted signal drv_filter_B_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_B_valid`](#frame_filters_int_filter_b_valid)                               | 0x660    |        4 | Auto-extracted signal int_filter_B_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_C_mask`](#frame_filters_drv_filter_c_mask)                                 | 0x664    |        4 | Auto-extracted signal drv_filter_C_mask from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_C_ctrl`](#frame_filters_drv_filter_c_ctrl)                                 | 0x668    |        4 | Auto-extracted signal drv_filter_C_ctrl from frame_filters.vhd                 |
+| can_bus.[`frame_filters_drv_filter_C_bits`](#frame_filters_drv_filter_c_bits)                                 | 0x66c    |        4 | Auto-extracted signal drv_filter_C_bits from frame_filters.vhd                 |
+| can_bus.[`frame_filters_int_filter_C_valid`](#frame_filters_int_filter_c_valid)                               | 0x670    |        4 | Auto-extracted signal int_filter_C_valid from frame_filters.vhd                |
+| can_bus.[`frame_filters_drv_filter_ran_ctrl`](#frame_filters_drv_filter_ran_ctrl)                             | 0x674    |        4 | Auto-extracted signal drv_filter_ran_ctrl from frame_filters.vhd               |
+| can_bus.[`frame_filters_drv_filter_ran_lo_th`](#frame_filters_drv_filter_ran_lo_th)                           | 0x678    |        4 | Auto-extracted signal drv_filter_ran_lo_th from frame_filters.vhd              |
+| can_bus.[`frame_filters_drv_filter_ran_hi_th`](#frame_filters_drv_filter_ran_hi_th)                           | 0x67c    |        4 | Auto-extracted signal drv_filter_ran_hi_th from frame_filters.vhd              |
+| can_bus.[`frame_filters_int_filter_ran_valid`](#frame_filters_int_filter_ran_valid)                           | 0x680    |        4 | Auto-extracted signal int_filter_ran_valid from frame_filters.vhd              |
+| can_bus.[`frame_filters_drv_filters_ena`](#frame_filters_drv_filters_ena)                                     | 0x684    |        4 | Auto-extracted signal drv_filters_ena from frame_filters.vhd                   |
+| can_bus.[`frame_filters_int_data_type`](#frame_filters_int_data_type)                                         | 0x688    |        4 | Auto-extracted signal int_data_type from frame_filters.vhd                     |
+| can_bus.[`frame_filters_int_data_ctrl`](#frame_filters_int_data_ctrl)                                         | 0x68c    |        4 | Auto-extracted signal int_data_ctrl from frame_filters.vhd                     |
+| can_bus.[`frame_filters_filter_A_enable`](#frame_filters_filter_a_enable)                                     | 0x690    |        4 | Auto-extracted signal filter_A_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_B_enable`](#frame_filters_filter_b_enable)                                     | 0x694    |        4 | Auto-extracted signal filter_B_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_C_enable`](#frame_filters_filter_c_enable)                                     | 0x698    |        4 | Auto-extracted signal filter_C_enable from frame_filters.vhd                   |
+| can_bus.[`frame_filters_filter_range_enable`](#frame_filters_filter_range_enable)                             | 0x69c    |        4 | Auto-extracted signal filter_range_enable from frame_filters.vhd               |
+| can_bus.[`frame_filters_filter_result`](#frame_filters_filter_result)                                         | 0x6a0    |        4 | Auto-extracted signal filter_result from frame_filters.vhd                     |
+| can_bus.[`frame_filters_ident_valid_d`](#frame_filters_ident_valid_d)                                         | 0x6a4    |        4 | Auto-extracted signal ident_valid_d from frame_filters.vhd                     |
+| can_bus.[`frame_filters_ident_valid_q`](#frame_filters_ident_valid_q)                                         | 0x6a8    |        4 | Auto-extracted signal ident_valid_q from frame_filters.vhd                     |
+| can_bus.[`frame_filters_drv_drop_remote_frames`](#frame_filters_drv_drop_remote_frames)                       | 0x6ac    |        4 | Auto-extracted signal drv_drop_remote_frames from frame_filters.vhd            |
+| can_bus.[`frame_filters_drop_rtr_frame`](#frame_filters_drop_rtr_frame)                                       | 0x6b0    |        4 | Auto-extracted signal drop_rtr_frame from frame_filters.vhd                    |
+| can_bus.[`inf_ram_wrapper_int_read_data`](#inf_ram_wrapper_int_read_data)                                     | 0x6b4    |        4 | Auto-extracted signal int_read_data from inf_ram_wrapper.vhd                   |
+| can_bus.[`inf_ram_wrapper_byte_we`](#inf_ram_wrapper_byte_we)                                                 | 0x6b8    |        4 | Auto-extracted signal byte_we from inf_ram_wrapper.vhd                         |
+| can_bus.[`int_manager_drv_int_vect_clr`](#int_manager_drv_int_vect_clr)                                       | 0x6bc    |        4 | Auto-extracted signal drv_int_vect_clr from int_manager.vhd                    |
+| can_bus.[`int_manager_drv_int_ena_set`](#int_manager_drv_int_ena_set)                                         | 0x6c0    |        4 | Auto-extracted signal drv_int_ena_set from int_manager.vhd                     |
+| can_bus.[`int_manager_drv_int_ena_clr`](#int_manager_drv_int_ena_clr)                                         | 0x6c4    |        4 | Auto-extracted signal drv_int_ena_clr from int_manager.vhd                     |
+| can_bus.[`int_manager_drv_int_mask_set`](#int_manager_drv_int_mask_set)                                       | 0x6c8    |        4 | Auto-extracted signal drv_int_mask_set from int_manager.vhd                    |
+| can_bus.[`int_manager_drv_int_mask_clr`](#int_manager_drv_int_mask_clr)                                       | 0x6cc    |        4 | Auto-extracted signal drv_int_mask_clr from int_manager.vhd                    |
+| can_bus.[`int_manager_int_ena_i`](#int_manager_int_ena_i)                                                     | 0x6d0    |        4 | Auto-extracted signal int_ena_i from int_manager.vhd                           |
+| can_bus.[`int_manager_int_mask_i`](#int_manager_int_mask_i)                                                   | 0x6d4    |        4 | Auto-extracted signal int_mask_i from int_manager.vhd                          |
+| can_bus.[`int_manager_int_vect_i`](#int_manager_int_vect_i)                                                   | 0x6d8    |        4 | Auto-extracted signal int_vect_i from int_manager.vhd                          |
+| can_bus.[`int_manager_int_input_active`](#int_manager_int_input_active)                                       | 0x6dc    |        4 | Auto-extracted signal int_input_active from int_manager.vhd                    |
+| can_bus.[`int_manager_int_i`](#int_manager_int_i)                                                             | 0x6e0    |        4 | Auto-extracted signal int_i from int_manager.vhd                               |
+| can_bus.[`int_module_int_mask_i`](#int_module_int_mask_i)                                                     | 0x6e4    |        4 | Auto-extracted signal int_mask_i from int_module.vhd                           |
+| can_bus.[`int_module_int_ena_i`](#int_module_int_ena_i)                                                       | 0x6e8    |        4 | Auto-extracted signal int_ena_i from int_module.vhd                            |
+| can_bus.[`int_module_int_mask_load`](#int_module_int_mask_load)                                               | 0x6ec    |        4 | Auto-extracted signal int_mask_load from int_module.vhd                        |
+| can_bus.[`int_module_int_mask_next`](#int_module_int_mask_next)                                               | 0x6f0    |        4 | Auto-extracted signal int_mask_next from int_module.vhd                        |
+| can_bus.[`memory_reg_reg_value_r`](#memory_reg_reg_value_r)                                                   | 0x6f4    |        4 | Auto-extracted signal reg_value_r from memory_reg.vhd                          |
+| can_bus.[`memory_reg_wr_select`](#memory_reg_wr_select)                                                       | 0x6f8    |        4 | Auto-extracted signal wr_select from memory_reg.vhd                            |
+| can_bus.[`memory_reg_wr_select_expanded`](#memory_reg_wr_select_expanded)                                     | 0x6fc    |        4 | Auto-extracted signal wr_select_expanded from memory_reg.vhd                   |
+| can_bus.[`memory_registers_status_comb`](#memory_registers_status_comb)                                       | 0x700    |        4 | Auto-extracted signal status_comb from memory_registers.vhd                    |
+| can_bus.[`memory_registers_can_core_cs`](#memory_registers_can_core_cs)                                       | 0x704    |        4 | Auto-extracted signal can_core_cs from memory_registers.vhd                    |
+| can_bus.[`memory_registers_control_registers_cs`](#memory_registers_control_registers_cs)                     | 0x708    |        4 | Auto-extracted signal control_registers_cs from memory_registers.vhd           |
+| can_bus.[`memory_registers_control_registers_cs_reg`](#memory_registers_control_registers_cs_reg)             | 0x70c    |        4 | Auto-extracted signal control_registers_cs_reg from memory_registers.vhd       |
+| can_bus.[`memory_registers_test_registers_cs`](#memory_registers_test_registers_cs)                           | 0x710    |        4 | Auto-extracted signal test_registers_cs from memory_registers.vhd              |
+| can_bus.[`memory_registers_test_registers_cs_reg`](#memory_registers_test_registers_cs_reg)                   | 0x714    |        4 | Auto-extracted signal test_registers_cs_reg from memory_registers.vhd          |
+| can_bus.[`memory_registers_control_registers_rdata`](#memory_registers_control_registers_rdata)               | 0x718    |        4 | Auto-extracted signal control_registers_rdata from memory_registers.vhd        |
+| can_bus.[`memory_registers_test_registers_rdata`](#memory_registers_test_registers_rdata)                     | 0x71c    |        4 | Auto-extracted signal test_registers_rdata from memory_registers.vhd           |
+| can_bus.[`memory_registers_is_err_active`](#memory_registers_is_err_active)                                   | 0x720    |        4 | Auto-extracted signal is_err_active from memory_registers.vhd                  |
+| can_bus.[`memory_registers_is_err_passive`](#memory_registers_is_err_passive)                                 | 0x724    |        4 | Auto-extracted signal is_err_passive from memory_registers.vhd                 |
+| can_bus.[`memory_registers_is_bus_off`](#memory_registers_is_bus_off)                                         | 0x728    |        4 | Auto-extracted signal is_bus_off from memory_registers.vhd                     |
+| can_bus.[`memory_registers_is_transmitter`](#memory_registers_is_transmitter)                                 | 0x72c    |        4 | Auto-extracted signal is_transmitter from memory_registers.vhd                 |
+| can_bus.[`memory_registers_is_receiver`](#memory_registers_is_receiver)                                       | 0x730    |        4 | Auto-extracted signal is_receiver from memory_registers.vhd                    |
+| can_bus.[`memory_registers_is_idle`](#memory_registers_is_idle)                                               | 0x734    |        4 | Auto-extracted signal is_idle from memory_registers.vhd                        |
+| can_bus.[`memory_registers_reg_lock_1_active`](#memory_registers_reg_lock_1_active)                           | 0x738    |        4 | Auto-extracted signal reg_lock_1_active from memory_registers.vhd              |
+| can_bus.[`memory_registers_reg_lock_2_active`](#memory_registers_reg_lock_2_active)                           | 0x73c    |        4 | Auto-extracted signal reg_lock_2_active from memory_registers.vhd              |
+| can_bus.[`memory_registers_soft_res_q_n`](#memory_registers_soft_res_q_n)                                     | 0x740    |        4 | Auto-extracted signal soft_res_q_n from memory_registers.vhd                   |
+| can_bus.[`memory_registers_ewl_padded`](#memory_registers_ewl_padded)                                         | 0x744    |        4 | Auto-extracted signal ewl_padded from memory_registers.vhd                     |
+| can_bus.[`memory_registers_control_regs_clk_en`](#memory_registers_control_regs_clk_en)                       | 0x748    |        4 | Auto-extracted signal control_regs_clk_en from memory_registers.vhd            |
+| can_bus.[`memory_registers_test_regs_clk_en`](#memory_registers_test_regs_clk_en)                             | 0x74c    |        4 | Auto-extracted signal test_regs_clk_en from memory_registers.vhd               |
+| can_bus.[`memory_registers_clk_control_regs`](#memory_registers_clk_control_regs)                             | 0x750    |        4 | Auto-extracted signal clk_control_regs from memory_registers.vhd               |
+| can_bus.[`memory_registers_clk_test_regs`](#memory_registers_clk_test_regs)                                   | 0x754    |        4 | Auto-extracted signal clk_test_regs from memory_registers.vhd                  |
+| can_bus.[`memory_registers_rx_buf_mode`](#memory_registers_rx_buf_mode)                                       | 0x758    |        4 | Auto-extracted signal rx_buf_mode from memory_registers.vhd                    |
+| can_bus.[`memory_registers_rx_move_cmd`](#memory_registers_rx_move_cmd)                                       | 0x75c    |        4 | Auto-extracted signal rx_move_cmd from memory_registers.vhd                    |
+| can_bus.[`memory_registers_ctr_pres_sel_q`](#memory_registers_ctr_pres_sel_q)                                 | 0x760    |        4 | Auto-extracted signal ctr_pres_sel_q from memory_registers.vhd                 |
+| can_bus.[`operation_control_drv_ena`](#operation_control_drv_ena)                                             | 0x764    |        4 | Auto-extracted signal drv_ena from operation_control.vhd                       |
+| can_bus.[`operation_control_go_to_off`](#operation_control_go_to_off)                                         | 0x768    |        4 | Auto-extracted signal go_to_off from operation_control.vhd                     |
+| can_bus.[`prescaler_drv_ena`](#prescaler_drv_ena)                                                             | 0x76c    |        4 | Auto-extracted signal drv_ena from prescaler.vhd                               |
+| can_bus.[`prescaler_tseg1_nbt`](#prescaler_tseg1_nbt)                                                         | 0x770    |        4 | Auto-extracted signal tseg1_nbt from prescaler.vhd                             |
+| can_bus.[`prescaler_tseg2_nbt`](#prescaler_tseg2_nbt)                                                         | 0x774    |        4 | Auto-extracted signal tseg2_nbt from prescaler.vhd                             |
+| can_bus.[`prescaler_brp_nbt`](#prescaler_brp_nbt)                                                             | 0x778    |        4 | Auto-extracted signal brp_nbt from prescaler.vhd                               |
+| can_bus.[`prescaler_sjw_nbt`](#prescaler_sjw_nbt)                                                             | 0x77c    |        4 | Auto-extracted signal sjw_nbt from prescaler.vhd                               |
+| can_bus.[`prescaler_tseg1_dbt`](#prescaler_tseg1_dbt)                                                         | 0x780    |        4 | Auto-extracted signal tseg1_dbt from prescaler.vhd                             |
+| can_bus.[`prescaler_tseg2_dbt`](#prescaler_tseg2_dbt)                                                         | 0x784    |        4 | Auto-extracted signal tseg2_dbt from prescaler.vhd                             |
+| can_bus.[`prescaler_brp_dbt`](#prescaler_brp_dbt)                                                             | 0x788    |        4 | Auto-extracted signal brp_dbt from prescaler.vhd                               |
+| can_bus.[`prescaler_sjw_dbt`](#prescaler_sjw_dbt)                                                             | 0x78c    |        4 | Auto-extracted signal sjw_dbt from prescaler.vhd                               |
+| can_bus.[`prescaler_segment_end`](#prescaler_segment_end)                                                     | 0x790    |        4 | Auto-extracted signal segment_end from prescaler.vhd                           |
+| can_bus.[`prescaler_h_sync_valid`](#prescaler_h_sync_valid)                                                   | 0x794    |        4 | Auto-extracted signal h_sync_valid from prescaler.vhd                          |
+| can_bus.[`prescaler_is_tseg1`](#prescaler_is_tseg1)                                                           | 0x798    |        4 | Auto-extracted signal is_tseg1 from prescaler.vhd                              |
+| can_bus.[`prescaler_is_tseg2`](#prescaler_is_tseg2)                                                           | 0x79c    |        4 | Auto-extracted signal is_tseg2 from prescaler.vhd                              |
+| can_bus.[`prescaler_resync_edge_valid`](#prescaler_resync_edge_valid)                                         | 0x7a0    |        4 | Auto-extracted signal resync_edge_valid from prescaler.vhd                     |
+| can_bus.[`prescaler_h_sync_edge_valid`](#prescaler_h_sync_edge_valid)                                         | 0x7a4    |        4 | Auto-extracted signal h_sync_edge_valid from prescaler.vhd                     |
+| can_bus.[`prescaler_segm_counter_nbt`](#prescaler_segm_counter_nbt)                                           | 0x7a8    |        4 | Auto-extracted signal segm_counter_nbt from prescaler.vhd                      |
+| can_bus.[`prescaler_segm_counter_dbt`](#prescaler_segm_counter_dbt)                                           | 0x7ac    |        4 | Auto-extracted signal segm_counter_dbt from prescaler.vhd                      |
+| can_bus.[`prescaler_exit_segm_req_nbt`](#prescaler_exit_segm_req_nbt)                                         | 0x7b0    |        4 | Auto-extracted signal exit_segm_req_nbt from prescaler.vhd                     |
+| can_bus.[`prescaler_exit_segm_req_dbt`](#prescaler_exit_segm_req_dbt)                                         | 0x7b4    |        4 | Auto-extracted signal exit_segm_req_dbt from prescaler.vhd                     |
+| can_bus.[`prescaler_tq_edge_nbt`](#prescaler_tq_edge_nbt)                                                     | 0x7b8    |        4 | Auto-extracted signal tq_edge_nbt from prescaler.vhd                           |
+| can_bus.[`prescaler_tq_edge_dbt`](#prescaler_tq_edge_dbt)                                                     | 0x7bc    |        4 | Auto-extracted signal tq_edge_dbt from prescaler.vhd                           |
+| can_bus.[`prescaler_rx_trig_req`](#prescaler_rx_trig_req)                                                     | 0x7c0    |        4 | Auto-extracted signal rx_trig_req from prescaler.vhd                           |
+| can_bus.[`prescaler_tx_trig_req`](#prescaler_tx_trig_req)                                                     | 0x7c4    |        4 | Auto-extracted signal tx_trig_req from prescaler.vhd                           |
+| can_bus.[`prescaler_start_edge`](#prescaler_start_edge)                                                       | 0x7c8    |        4 | Auto-extracted signal start_edge from prescaler.vhd                            |
+| can_bus.[`prescaler_bt_ctr_clear`](#prescaler_bt_ctr_clear)                                                   | 0x7cc    |        4 | Auto-extracted signal bt_ctr_clear from prescaler.vhd                          |
+| can_bus.[`priority_decoder_l0_valid`](#priority_decoder_l0_valid)                                             | 0x7d0    |        4 | Auto-extracted signal l0_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l1_valid`](#priority_decoder_l1_valid)                                             | 0x7d4    |        4 | Auto-extracted signal l1_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l1_winner`](#priority_decoder_l1_winner)                                           | 0x7d8    |        4 | Auto-extracted signal l1_winner from priority_decoder.vhd                      |
+| can_bus.[`priority_decoder_l2_valid`](#priority_decoder_l2_valid)                                             | 0x7dc    |        4 | Auto-extracted signal l2_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l2_winner`](#priority_decoder_l2_winner)                                           | 0x7e0    |        4 | Auto-extracted signal l2_winner from priority_decoder.vhd                      |
+| can_bus.[`priority_decoder_l3_valid`](#priority_decoder_l3_valid)                                             | 0x7e4    |        4 | Auto-extracted signal l3_valid from priority_decoder.vhd                       |
+| can_bus.[`priority_decoder_l3_winner`](#priority_decoder_l3_winner)                                           | 0x7e8    |        4 | Auto-extracted signal l3_winner from priority_decoder.vhd                      |
+| can_bus.[`protocol_control_drv_can_fd_ena`](#protocol_control_drv_can_fd_ena)                                 | 0x7ec    |        4 | Auto-extracted signal drv_can_fd_ena from protocol_control.vhd                 |
+| can_bus.[`protocol_control_drv_bus_mon_ena`](#protocol_control_drv_bus_mon_ena)                               | 0x7f0    |        4 | Auto-extracted signal drv_bus_mon_ena from protocol_control.vhd                |
+| can_bus.[`protocol_control_drv_retr_lim_ena`](#protocol_control_drv_retr_lim_ena)                             | 0x7f4    |        4 | Auto-extracted signal drv_retr_lim_ena from protocol_control.vhd               |
+| can_bus.[`protocol_control_drv_retr_th`](#protocol_control_drv_retr_th)                                       | 0x7f8    |        4 | Auto-extracted signal drv_retr_th from protocol_control.vhd                    |
+| can_bus.[`protocol_control_drv_self_test_ena`](#protocol_control_drv_self_test_ena)                           | 0x7fc    |        4 | Auto-extracted signal drv_self_test_ena from protocol_control.vhd              |
+| can_bus.[`protocol_control_drv_ack_forb`](#protocol_control_drv_ack_forb)                                     | 0x800    |        4 | Auto-extracted signal drv_ack_forb from protocol_control.vhd                   |
+| can_bus.[`protocol_control_drv_ena`](#protocol_control_drv_ena)                                               | 0x804    |        4 | Auto-extracted signal drv_ena from protocol_control.vhd                        |
+| can_bus.[`protocol_control_drv_fd_type`](#protocol_control_drv_fd_type)                                       | 0x808    |        4 | Auto-extracted signal drv_fd_type from protocol_control.vhd                    |
+| can_bus.[`protocol_control_drv_int_loopback_ena`](#protocol_control_drv_int_loopback_ena)                     | 0x80c    |        4 | Auto-extracted signal drv_int_loopback_ena from protocol_control.vhd           |
+| can_bus.[`protocol_control_drv_bus_off_reset`](#protocol_control_drv_bus_off_reset)                           | 0x810    |        4 | Auto-extracted signal drv_bus_off_reset from protocol_control.vhd              |
+| can_bus.[`protocol_control_drv_ssp_delay_select`](#protocol_control_drv_ssp_delay_select)                     | 0x814    |        4 | Auto-extracted signal drv_ssp_delay_select from protocol_control.vhd           |
+| can_bus.[`protocol_control_drv_pex`](#protocol_control_drv_pex)                                               | 0x818    |        4 | Auto-extracted signal drv_pex from protocol_control.vhd                        |
+| can_bus.[`protocol_control_drv_cpexs`](#protocol_control_drv_cpexs)                                           | 0x81c    |        4 | Auto-extracted signal drv_cpexs from protocol_control.vhd                      |
+| can_bus.[`protocol_control_tran_word_swapped`](#protocol_control_tran_word_swapped)                           | 0x820    |        4 | Auto-extracted signal tran_word_swapped from protocol_control.vhd              |
+| can_bus.[`protocol_control_err_frm_req`](#protocol_control_err_frm_req)                                       | 0x824    |        4 | Auto-extracted signal err_frm_req from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_load_base_id`](#protocol_control_tx_load_base_id)                               | 0x828    |        4 | Auto-extracted signal tx_load_base_id from protocol_control.vhd                |
+| can_bus.[`protocol_control_tx_load_ext_id`](#protocol_control_tx_load_ext_id)                                 | 0x82c    |        4 | Auto-extracted signal tx_load_ext_id from protocol_control.vhd                 |
+| can_bus.[`protocol_control_tx_load_dlc`](#protocol_control_tx_load_dlc)                                       | 0x830    |        4 | Auto-extracted signal tx_load_dlc from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_load_data_word`](#protocol_control_tx_load_data_word)                           | 0x834    |        4 | Auto-extracted signal tx_load_data_word from protocol_control.vhd              |
+| can_bus.[`protocol_control_tx_load_stuff_count`](#protocol_control_tx_load_stuff_count)                       | 0x838    |        4 | Auto-extracted signal tx_load_stuff_count from protocol_control.vhd            |
+| can_bus.[`protocol_control_tx_load_crc`](#protocol_control_tx_load_crc)                                       | 0x83c    |        4 | Auto-extracted signal tx_load_crc from protocol_control.vhd                    |
+| can_bus.[`protocol_control_tx_shift_ena`](#protocol_control_tx_shift_ena)                                     | 0x840    |        4 | Auto-extracted signal tx_shift_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_tx_dominant`](#protocol_control_tx_dominant)                                       | 0x844    |        4 | Auto-extracted signal tx_dominant from protocol_control.vhd                    |
+| can_bus.[`protocol_control_rx_clear`](#protocol_control_rx_clear)                                             | 0x848    |        4 | Auto-extracted signal rx_clear from protocol_control.vhd                       |
+| can_bus.[`protocol_control_rx_store_base_id`](#protocol_control_rx_store_base_id)                             | 0x84c    |        4 | Auto-extracted signal rx_store_base_id from protocol_control.vhd               |
+| can_bus.[`protocol_control_rx_store_ext_id`](#protocol_control_rx_store_ext_id)                               | 0x850    |        4 | Auto-extracted signal rx_store_ext_id from protocol_control.vhd                |
+| can_bus.[`protocol_control_rx_store_ide`](#protocol_control_rx_store_ide)                                     | 0x854    |        4 | Auto-extracted signal rx_store_ide from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_rtr`](#protocol_control_rx_store_rtr)                                     | 0x858    |        4 | Auto-extracted signal rx_store_rtr from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_edl`](#protocol_control_rx_store_edl)                                     | 0x85c    |        4 | Auto-extracted signal rx_store_edl from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_dlc`](#protocol_control_rx_store_dlc)                                     | 0x860    |        4 | Auto-extracted signal rx_store_dlc from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_esi`](#protocol_control_rx_store_esi)                                     | 0x864    |        4 | Auto-extracted signal rx_store_esi from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_brs`](#protocol_control_rx_store_brs)                                     | 0x868    |        4 | Auto-extracted signal rx_store_brs from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_store_stuff_count`](#protocol_control_rx_store_stuff_count)                     | 0x86c    |        4 | Auto-extracted signal rx_store_stuff_count from protocol_control.vhd           |
+| can_bus.[`protocol_control_rx_shift_ena`](#protocol_control_rx_shift_ena)                                     | 0x870    |        4 | Auto-extracted signal rx_shift_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rx_shift_in_sel`](#protocol_control_rx_shift_in_sel)                               | 0x874    |        4 | Auto-extracted signal rx_shift_in_sel from protocol_control.vhd                |
+| can_bus.[`protocol_control_rec_is_rtr_i`](#protocol_control_rec_is_rtr_i)                                     | 0x878    |        4 | Auto-extracted signal rec_is_rtr_i from protocol_control.vhd                   |
+| can_bus.[`protocol_control_rec_dlc_d`](#protocol_control_rec_dlc_d)                                           | 0x87c    |        4 | Auto-extracted signal rec_dlc_d from protocol_control.vhd                      |
+| can_bus.[`protocol_control_rec_dlc_q`](#protocol_control_rec_dlc_q)                                           | 0x880    |        4 | Auto-extracted signal rec_dlc_q from protocol_control.vhd                      |
+| can_bus.[`protocol_control_rec_frame_type_i`](#protocol_control_rec_frame_type_i)                             | 0x884    |        4 | Auto-extracted signal rec_frame_type_i from protocol_control.vhd               |
+| can_bus.[`protocol_control_ctrl_ctr_pload`](#protocol_control_ctrl_ctr_pload)                                 | 0x888    |        4 | Auto-extracted signal ctrl_ctr_pload from protocol_control.vhd                 |
+| can_bus.[`protocol_control_ctrl_ctr_pload_val`](#protocol_control_ctrl_ctr_pload_val)                         | 0x88c    |        4 | Auto-extracted signal ctrl_ctr_pload_val from protocol_control.vhd             |
+| can_bus.[`protocol_control_ctrl_ctr_ena`](#protocol_control_ctrl_ctr_ena)                                     | 0x890    |        4 | Auto-extracted signal ctrl_ctr_ena from protocol_control.vhd                   |
+| can_bus.[`protocol_control_ctrl_ctr_zero`](#protocol_control_ctrl_ctr_zero)                                   | 0x894    |        4 | Auto-extracted signal ctrl_ctr_zero from protocol_control.vhd                  |
+| can_bus.[`protocol_control_ctrl_ctr_one`](#protocol_control_ctrl_ctr_one)                                     | 0x898    |        4 | Auto-extracted signal ctrl_ctr_one from protocol_control.vhd                   |
+| can_bus.[`protocol_control_ctrl_counted_byte`](#protocol_control_ctrl_counted_byte)                           | 0x89c    |        4 | Auto-extracted signal ctrl_counted_byte from protocol_control.vhd              |
+| can_bus.[`protocol_control_ctrl_counted_byte_index`](#protocol_control_ctrl_counted_byte_index)               | 0x8a0    |        4 | Auto-extracted signal ctrl_counted_byte_index from protocol_control.vhd        |
+| can_bus.[`protocol_control_ctrl_ctr_mem_index`](#protocol_control_ctrl_ctr_mem_index)                         | 0x8a4    |        4 | Auto-extracted signal ctrl_ctr_mem_index from protocol_control.vhd             |
+| can_bus.[`protocol_control_compl_ctr_ena`](#protocol_control_compl_ctr_ena)                                   | 0x8a8    |        4 | Auto-extracted signal compl_ctr_ena from protocol_control.vhd                  |
+| can_bus.[`protocol_control_reinteg_ctr_clr`](#protocol_control_reinteg_ctr_clr)                               | 0x8ac    |        4 | Auto-extracted signal reinteg_ctr_clr from protocol_control.vhd                |
+| can_bus.[`protocol_control_reinteg_ctr_enable`](#protocol_control_reinteg_ctr_enable)                         | 0x8b0    |        4 | Auto-extracted signal reinteg_ctr_enable from protocol_control.vhd             |
+| can_bus.[`protocol_control_reinteg_ctr_expired`](#protocol_control_reinteg_ctr_expired)                       | 0x8b4    |        4 | Auto-extracted signal reinteg_ctr_expired from protocol_control.vhd            |
+| can_bus.[`protocol_control_retr_ctr_clear`](#protocol_control_retr_ctr_clear)                                 | 0x8b8    |        4 | Auto-extracted signal retr_ctr_clear from protocol_control.vhd                 |
+| can_bus.[`protocol_control_retr_ctr_add`](#protocol_control_retr_ctr_add)                                     | 0x8bc    |        4 | Auto-extracted signal retr_ctr_add from protocol_control.vhd                   |
+| can_bus.[`protocol_control_retr_limit_reached`](#protocol_control_retr_limit_reached)                         | 0x8c0    |        4 | Auto-extracted signal retr_limit_reached from protocol_control.vhd             |
+| can_bus.[`protocol_control_form_err_i`](#protocol_control_form_err_i)                                         | 0x8c4    |        4 | Auto-extracted signal form_err_i from protocol_control.vhd                     |
+| can_bus.[`protocol_control_ack_err_i`](#protocol_control_ack_err_i)                                           | 0x8c8    |        4 | Auto-extracted signal ack_err_i from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_check`](#protocol_control_crc_check)                                           | 0x8cc    |        4 | Auto-extracted signal crc_check from protocol_control.vhd                      |
+| can_bus.[`protocol_control_bit_err_arb`](#protocol_control_bit_err_arb)                                       | 0x8d0    |        4 | Auto-extracted signal bit_err_arb from protocol_control.vhd                    |
+| can_bus.[`protocol_control_crc_match`](#protocol_control_crc_match)                                           | 0x8d4    |        4 | Auto-extracted signal crc_match from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_err_i`](#protocol_control_crc_err_i)                                           | 0x8d8    |        4 | Auto-extracted signal crc_err_i from protocol_control.vhd                      |
+| can_bus.[`protocol_control_crc_clear_match_flag`](#protocol_control_crc_clear_match_flag)                     | 0x8dc    |        4 | Auto-extracted signal crc_clear_match_flag from protocol_control.vhd           |
+| can_bus.[`protocol_control_crc_src`](#protocol_control_crc_src)                                               | 0x8e0    |        4 | Auto-extracted signal crc_src from protocol_control.vhd                        |
+| can_bus.[`protocol_control_err_pos`](#protocol_control_err_pos)                                               | 0x8e4    |        4 | Auto-extracted signal err_pos from protocol_control.vhd                        |
+| can_bus.[`protocol_control_is_arbitration_i`](#protocol_control_is_arbitration_i)                             | 0x8e8    |        4 | Auto-extracted signal is_arbitration_i from protocol_control.vhd               |
+| can_bus.[`protocol_control_bit_err_enable`](#protocol_control_bit_err_enable)                                 | 0x8ec    |        4 | Auto-extracted signal bit_err_enable from protocol_control.vhd                 |
+| can_bus.[`protocol_control_tx_data_nbs_i`](#protocol_control_tx_data_nbs_i)                                   | 0x8f0    |        4 | Auto-extracted signal tx_data_nbs_i from protocol_control.vhd                  |
+| can_bus.[`protocol_control_rx_crc`](#protocol_control_rx_crc)                                                 | 0x8f4    |        4 | Auto-extracted signal rx_crc from protocol_control.vhd                         |
+| can_bus.[`protocol_control_rx_stuff_count`](#protocol_control_rx_stuff_count)                                 | 0x8f8    |        4 | Auto-extracted signal rx_stuff_count from protocol_control.vhd                 |
+| can_bus.[`protocol_control_fixed_stuff_i`](#protocol_control_fixed_stuff_i)                                   | 0x8fc    |        4 | Auto-extracted signal fixed_stuff_i from protocol_control.vhd                  |
+| can_bus.[`protocol_control_arbitration_lost_i`](#protocol_control_arbitration_lost_i)                         | 0x900    |        4 | Auto-extracted signal arbitration_lost_i from protocol_control.vhd             |
+| can_bus.[`protocol_control_alc_id_field`](#protocol_control_alc_id_field)                                     | 0x904    |        4 | Auto-extracted signal alc_id_field from protocol_control.vhd                   |
+| can_bus.[`protocol_control_drv_rom_ena`](#protocol_control_drv_rom_ena)                                       | 0x908    |        4 | Auto-extracted signal drv_rom_ena from protocol_control.vhd                    |
+| can_bus.[`protocol_control_fsm_state_reg_ce`](#protocol_control_fsm_state_reg_ce)                             | 0x90c    |        4 | Auto-extracted signal state_reg_ce from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_no_data_transmitter`](#protocol_control_fsm_no_data_transmitter)               | 0x910    |        4 | Auto-extracted signal no_data_transmitter from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_no_data_receiver`](#protocol_control_fsm_no_data_receiver)                     | 0x914    |        4 | Auto-extracted signal no_data_receiver from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_no_data_field`](#protocol_control_fsm_no_data_field)                           | 0x918    |        4 | Auto-extracted signal no_data_field from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_ctrl_ctr_pload_i`](#protocol_control_fsm_ctrl_ctr_pload_i)                     | 0x91c    |        4 | Auto-extracted signal ctrl_ctr_pload_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_ctrl_ctr_pload_unaliged`](#protocol_control_fsm_ctrl_ctr_pload_unaliged)       | 0x920    |        4 | Auto-extracted signal ctrl_ctr_pload_unaliged from protocol_control_fsm.vhd    |
+| can_bus.[`protocol_control_fsm_crc_use_21`](#protocol_control_fsm_crc_use_21)                                 | 0x924    |        4 | Auto-extracted signal crc_use_21 from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_crc_use_17`](#protocol_control_fsm_crc_use_17)                                 | 0x928    |        4 | Auto-extracted signal crc_use_17 from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_crc_src_i`](#protocol_control_fsm_crc_src_i)                                   | 0x92c    |        4 | Auto-extracted signal crc_src_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_crc_length_i`](#protocol_control_fsm_crc_length_i)                             | 0x930    |        4 | Auto-extracted signal crc_length_i from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_tran_data_length`](#protocol_control_fsm_tran_data_length)                     | 0x934    |        4 | Auto-extracted signal tran_data_length from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_rec_data_length`](#protocol_control_fsm_rec_data_length)                       | 0x938    |        4 | Auto-extracted signal rec_data_length from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_rec_data_length_c`](#protocol_control_fsm_rec_data_length_c)                   | 0x93c    |        4 | Auto-extracted signal rec_data_length_c from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_data_length_c`](#protocol_control_fsm_data_length_c)                           | 0x940    |        4 | Auto-extracted signal data_length_c from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_data_length_shifted_c`](#protocol_control_fsm_data_length_shifted_c)           | 0x944    |        4 | Auto-extracted signal data_length_shifted_c from protocol_control_fsm.vhd      |
+| can_bus.[`protocol_control_fsm_data_length_bits_c`](#protocol_control_fsm_data_length_bits_c)                 | 0x948    |        4 | Auto-extracted signal data_length_bits_c from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_is_fd_frame`](#protocol_control_fsm_is_fd_frame)                               | 0x94c    |        4 | Auto-extracted signal is_fd_frame from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_frame_start`](#protocol_control_fsm_frame_start)                               | 0x950    |        4 | Auto-extracted signal frame_start from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_tx_frame_ready`](#protocol_control_fsm_tx_frame_ready)                         | 0x954    |        4 | Auto-extracted signal tx_frame_ready from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_ide_is_arbitration`](#protocol_control_fsm_ide_is_arbitration)                 | 0x958    |        4 | Auto-extracted signal ide_is_arbitration from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_arbitration_lost_condition`](#protocol_control_fsm_arbitration_lost_condition) | 0x95c    |        4 | Auto-extracted signal arbitration_lost_condition from protocol_control_fsm.vhd |
+| can_bus.[`protocol_control_fsm_arbitration_lost_i`](#protocol_control_fsm_arbitration_lost_i)                 | 0x960    |        4 | Auto-extracted signal arbitration_lost_i from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_tx_failed`](#protocol_control_fsm_tx_failed)                                   | 0x964    |        4 | Auto-extracted signal tx_failed from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_store_metadata_d`](#protocol_control_fsm_store_metadata_d)                     | 0x968    |        4 | Auto-extracted signal store_metadata_d from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_store_data_d`](#protocol_control_fsm_store_data_d)                             | 0x96c    |        4 | Auto-extracted signal store_data_d from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_rec_valid_d`](#protocol_control_fsm_rec_valid_d)                               | 0x970    |        4 | Auto-extracted signal rec_valid_d from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_rec_abort_d`](#protocol_control_fsm_rec_abort_d)                               | 0x974    |        4 | Auto-extracted signal rec_abort_d from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_go_to_suspend`](#protocol_control_fsm_go_to_suspend)                           | 0x978    |        4 | Auto-extracted signal go_to_suspend from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_go_to_stuff_count`](#protocol_control_fsm_go_to_stuff_count)                   | 0x97c    |        4 | Auto-extracted signal go_to_stuff_count from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_store_base_id_i`](#protocol_control_fsm_rx_store_base_id_i)                 | 0x980    |        4 | Auto-extracted signal rx_store_base_id_i from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_rx_store_ext_id_i`](#protocol_control_fsm_rx_store_ext_id_i)                   | 0x984    |        4 | Auto-extracted signal rx_store_ext_id_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_store_ide_i`](#protocol_control_fsm_rx_store_ide_i)                         | 0x988    |        4 | Auto-extracted signal rx_store_ide_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_rtr_i`](#protocol_control_fsm_rx_store_rtr_i)                         | 0x98c    |        4 | Auto-extracted signal rx_store_rtr_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_edl_i`](#protocol_control_fsm_rx_store_edl_i)                         | 0x990    |        4 | Auto-extracted signal rx_store_edl_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_dlc_i`](#protocol_control_fsm_rx_store_dlc_i)                         | 0x994    |        4 | Auto-extracted signal rx_store_dlc_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_esi_i`](#protocol_control_fsm_rx_store_esi_i)                         | 0x998    |        4 | Auto-extracted signal rx_store_esi_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_brs_i`](#protocol_control_fsm_rx_store_brs_i)                         | 0x99c    |        4 | Auto-extracted signal rx_store_brs_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_rx_store_stuff_count_i`](#protocol_control_fsm_rx_store_stuff_count_i)         | 0x9a0    |        4 | Auto-extracted signal rx_store_stuff_count_i from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_rx_clear_i`](#protocol_control_fsm_rx_clear_i)                                 | 0x9a4    |        4 | Auto-extracted signal rx_clear_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_tx_load_base_id_i`](#protocol_control_fsm_tx_load_base_id_i)                   | 0x9a8    |        4 | Auto-extracted signal tx_load_base_id_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_load_ext_id_i`](#protocol_control_fsm_tx_load_ext_id_i)                     | 0x9ac    |        4 | Auto-extracted signal tx_load_ext_id_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_tx_load_dlc_i`](#protocol_control_fsm_tx_load_dlc_i)                           | 0x9b0    |        4 | Auto-extracted signal tx_load_dlc_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_tx_load_data_word_i`](#protocol_control_fsm_tx_load_data_word_i)               | 0x9b4    |        4 | Auto-extracted signal tx_load_data_word_i from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_tx_load_stuff_count_i`](#protocol_control_fsm_tx_load_stuff_count_i)           | 0x9b8    |        4 | Auto-extracted signal tx_load_stuff_count_i from protocol_control_fsm.vhd      |
+| can_bus.[`protocol_control_fsm_tx_load_crc_i`](#protocol_control_fsm_tx_load_crc_i)                           | 0x9bc    |        4 | Auto-extracted signal tx_load_crc_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_tx_shift_ena_i`](#protocol_control_fsm_tx_shift_ena_i)                         | 0x9c0    |        4 | Auto-extracted signal tx_shift_ena_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_form_err_i`](#protocol_control_fsm_form_err_i)                                 | 0x9c4    |        4 | Auto-extracted signal form_err_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_ack_err_i`](#protocol_control_fsm_ack_err_i)                                   | 0x9c8    |        4 | Auto-extracted signal ack_err_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_ack_err_flag`](#protocol_control_fsm_ack_err_flag)                             | 0x9cc    |        4 | Auto-extracted signal ack_err_flag from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_ack_err_flag_clr`](#protocol_control_fsm_ack_err_flag_clr)                     | 0x9d0    |        4 | Auto-extracted signal ack_err_flag_clr from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_crc_err_i`](#protocol_control_fsm_crc_err_i)                                   | 0x9d4    |        4 | Auto-extracted signal crc_err_i from protocol_control_fsm.vhd                  |
+| can_bus.[`protocol_control_fsm_bit_err_arb_i`](#protocol_control_fsm_bit_err_arb_i)                           | 0x9d8    |        4 | Auto-extracted signal bit_err_arb_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_switch_data`](#protocol_control_fsm_sp_control_switch_data)         | 0x9dc    |        4 | Auto-extracted signal sp_control_switch_data from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_sp_control_switch_nominal`](#protocol_control_fsm_sp_control_switch_nominal)   | 0x9e0    |        4 | Auto-extracted signal sp_control_switch_nominal from protocol_control_fsm.vhd  |
+| can_bus.[`protocol_control_fsm_switch_to_ssp`](#protocol_control_fsm_switch_to_ssp)                           | 0x9e4    |        4 | Auto-extracted signal switch_to_ssp from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_ce`](#protocol_control_fsm_sp_control_ce)                           | 0x9e8    |        4 | Auto-extracted signal sp_control_ce from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_sp_control_d`](#protocol_control_fsm_sp_control_d)                             | 0x9ec    |        4 | Auto-extracted signal sp_control_d from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_sp_control_q_i`](#protocol_control_fsm_sp_control_q_i)                         | 0x9f0    |        4 | Auto-extracted signal sp_control_q_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_ssp_reset_i`](#protocol_control_fsm_ssp_reset_i)                               | 0x9f4    |        4 | Auto-extracted signal ssp_reset_i from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_sync_control_d`](#protocol_control_fsm_sync_control_d)                         | 0x9f8    |        4 | Auto-extracted signal sync_control_d from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_sync_control_q`](#protocol_control_fsm_sync_control_q)                         | 0x9fc    |        4 | Auto-extracted signal sync_control_q from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_perform_hsync`](#protocol_control_fsm_perform_hsync)                           | 0xa00    |        4 | Auto-extracted signal perform_hsync from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_primary_err_i`](#protocol_control_fsm_primary_err_i)                           | 0xa04    |        4 | Auto-extracted signal primary_err_i from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_err_delim_late_i`](#protocol_control_fsm_err_delim_late_i)                     | 0xa08    |        4 | Auto-extracted signal err_delim_late_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_set_err_active_i`](#protocol_control_fsm_set_err_active_i)                     | 0xa0c    |        4 | Auto-extracted signal set_err_active_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_set_transmitter_i`](#protocol_control_fsm_set_transmitter_i)                   | 0xa10    |        4 | Auto-extracted signal set_transmitter_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_set_receiver_i`](#protocol_control_fsm_set_receiver_i)                         | 0xa14    |        4 | Auto-extracted signal set_receiver_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_set_idle_i`](#protocol_control_fsm_set_idle_i)                                 | 0xa18    |        4 | Auto-extracted signal set_idle_i from protocol_control_fsm.vhd                 |
+| can_bus.[`protocol_control_fsm_first_err_delim_d`](#protocol_control_fsm_first_err_delim_d)                   | 0xa1c    |        4 | Auto-extracted signal first_err_delim_d from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_first_err_delim_q`](#protocol_control_fsm_first_err_delim_q)                   | 0xa20    |        4 | Auto-extracted signal first_err_delim_q from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_stuff_enable_set`](#protocol_control_fsm_stuff_enable_set)                     | 0xa24    |        4 | Auto-extracted signal stuff_enable_set from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_stuff_enable_clear`](#protocol_control_fsm_stuff_enable_clear)                 | 0xa28    |        4 | Auto-extracted signal stuff_enable_clear from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_destuff_enable_set`](#protocol_control_fsm_destuff_enable_set)                 | 0xa2c    |        4 | Auto-extracted signal destuff_enable_set from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_destuff_enable_clear`](#protocol_control_fsm_destuff_enable_clear)             | 0xa30    |        4 | Auto-extracted signal destuff_enable_clear from protocol_control_fsm.vhd       |
+| can_bus.[`protocol_control_fsm_bit_err_disable`](#protocol_control_fsm_bit_err_disable)                       | 0xa34    |        4 | Auto-extracted signal bit_err_disable from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_bit_err_disable_receiver`](#protocol_control_fsm_bit_err_disable_receiver)     | 0xa38    |        4 | Auto-extracted signal bit_err_disable_receiver from protocol_control_fsm.vhd   |
+| can_bus.[`protocol_control_fsm_sof_pulse_i`](#protocol_control_fsm_sof_pulse_i)                               | 0xa3c    |        4 | Auto-extracted signal sof_pulse_i from protocol_control_fsm.vhd                |
+| can_bus.[`protocol_control_fsm_compl_ctr_ena_i`](#protocol_control_fsm_compl_ctr_ena_i)                       | 0xa40    |        4 | Auto-extracted signal compl_ctr_ena_i from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_tick_state_reg`](#protocol_control_fsm_tick_state_reg)                         | 0xa44    |        4 | Auto-extracted signal tick_state_reg from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_br_shifted_i`](#protocol_control_fsm_br_shifted_i)                             | 0xa48    |        4 | Auto-extracted signal br_shifted_i from protocol_control_fsm.vhd               |
+| can_bus.[`protocol_control_fsm_is_arbitration_i`](#protocol_control_fsm_is_arbitration_i)                     | 0xa4c    |        4 | Auto-extracted signal is_arbitration_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_crc_spec_enable_i`](#protocol_control_fsm_crc_spec_enable_i)                   | 0xa50    |        4 | Auto-extracted signal crc_spec_enable_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_load_init_vect_i`](#protocol_control_fsm_load_init_vect_i)                     | 0xa54    |        4 | Auto-extracted signal load_init_vect_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_drv_bus_off_reset_q`](#protocol_control_fsm_drv_bus_off_reset_q)               | 0xa58    |        4 | Auto-extracted signal drv_bus_off_reset_q from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_retr_ctr_clear_i`](#protocol_control_fsm_retr_ctr_clear_i)                     | 0xa5c    |        4 | Auto-extracted signal retr_ctr_clear_i from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_i`](#protocol_control_fsm_retr_ctr_add_i)                         | 0xa60    |        4 | Auto-extracted signal retr_ctr_add_i from protocol_control_fsm.vhd             |
+| can_bus.[`protocol_control_fsm_decrement_rec_i`](#protocol_control_fsm_decrement_rec_i)                       | 0xa64    |        4 | Auto-extracted signal decrement_rec_i from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_block`](#protocol_control_fsm_retr_ctr_add_block)                 | 0xa68    |        4 | Auto-extracted signal retr_ctr_add_block from protocol_control_fsm.vhd         |
+| can_bus.[`protocol_control_fsm_retr_ctr_add_block_clr`](#protocol_control_fsm_retr_ctr_add_block_clr)         | 0xa6c    |        4 | Auto-extracted signal retr_ctr_add_block_clr from protocol_control_fsm.vhd     |
+| can_bus.[`protocol_control_fsm_block_txtb_unlock`](#protocol_control_fsm_block_txtb_unlock)                   | 0xa70    |        4 | Auto-extracted signal block_txtb_unlock from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_frame_no_sof_d`](#protocol_control_fsm_tx_frame_no_sof_d)                   | 0xa74    |        4 | Auto-extracted signal tx_frame_no_sof_d from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_tx_frame_no_sof_q`](#protocol_control_fsm_tx_frame_no_sof_q)                   | 0xa78    |        4 | Auto-extracted signal tx_frame_no_sof_q from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_ctrl_signal_upd`](#protocol_control_fsm_ctrl_signal_upd)                       | 0xa7c    |        4 | Auto-extracted signal ctrl_signal_upd from protocol_control_fsm.vhd            |
+| can_bus.[`protocol_control_fsm_clr_bus_off_rst_flg`](#protocol_control_fsm_clr_bus_off_rst_flg)               | 0xa80    |        4 | Auto-extracted signal clr_bus_off_rst_flg from protocol_control_fsm.vhd        |
+| can_bus.[`protocol_control_fsm_pex_on_fdf_enable`](#protocol_control_fsm_pex_on_fdf_enable)                   | 0xa84    |        4 | Auto-extracted signal pex_on_fdf_enable from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_pex_on_res_enable`](#protocol_control_fsm_pex_on_res_enable)                   | 0xa88    |        4 | Auto-extracted signal pex_on_res_enable from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_rx_data_nbs_prev`](#protocol_control_fsm_rx_data_nbs_prev)                     | 0xa8c    |        4 | Auto-extracted signal rx_data_nbs_prev from protocol_control_fsm.vhd           |
+| can_bus.[`protocol_control_fsm_pexs_set`](#protocol_control_fsm_pexs_set)                                     | 0xa90    |        4 | Auto-extracted signal pexs_set from protocol_control_fsm.vhd                   |
+| can_bus.[`protocol_control_fsm_tran_frame_type_i`](#protocol_control_fsm_tran_frame_type_i)                   | 0xa94    |        4 | Auto-extracted signal tran_frame_type_i from protocol_control_fsm.vhd          |
+| can_bus.[`protocol_control_fsm_txtb_clk_en_d`](#protocol_control_fsm_txtb_clk_en_d)                           | 0xa98    |        4 | Auto-extracted signal txtb_clk_en_d from protocol_control_fsm.vhd              |
+| can_bus.[`protocol_control_fsm_txtb_clk_en_q`](#protocol_control_fsm_txtb_clk_en_q)                           | 0xa9c    |        4 | Auto-extracted signal txtb_clk_en_q from protocol_control_fsm.vhd              |
+| can_bus.[`reintegration_counter_reinteg_ctr_ce`](#reintegration_counter_reinteg_ctr_ce)                       | 0xaa0    |        4 | Auto-extracted signal reinteg_ctr_ce from reintegration_counter.vhd            |
+| can_bus.[`retransmitt_counter_retr_ctr_ce`](#retransmitt_counter_retr_ctr_ce)                                 | 0xaa4    |        4 | Auto-extracted signal retr_ctr_ce from retransmitt_counter.vhd                 |
+| can_bus.[`rst_sync_rff`](#rst_sync_rff)                                                                       | 0xaa8    |        4 | Auto-extracted signal rff from rst_sync.vhd                                    |
+| can_bus.[`rx_buffer_drv_erase_rx`](#rx_buffer_drv_erase_rx)                                                   | 0xaac    |        4 | Auto-extracted signal drv_erase_rx from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_drv_read_start`](#rx_buffer_drv_read_start)                                               | 0xab0    |        4 | Auto-extracted signal drv_read_start from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_drv_clr_ovr`](#rx_buffer_drv_clr_ovr)                                                     | 0xab4    |        4 | Auto-extracted signal drv_clr_ovr from rx_buffer.vhd                           |
+| can_bus.[`rx_buffer_drv_rtsopt`](#rx_buffer_drv_rtsopt)                                                       | 0xab8    |        4 | Auto-extracted signal drv_rtsopt from rx_buffer.vhd                            |
+| can_bus.[`rx_buffer_read_pointer`](#rx_buffer_read_pointer)                                                   | 0xabc    |        4 | Auto-extracted signal read_pointer from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_read_pointer_inc_1`](#rx_buffer_read_pointer_inc_1)                                       | 0xac0    |        4 | Auto-extracted signal read_pointer_inc_1 from rx_buffer.vhd                    |
+| can_bus.[`rx_buffer_write_pointer`](#rx_buffer_write_pointer)                                                 | 0xac4    |        4 | Auto-extracted signal write_pointer from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_write_pointer_raw`](#rx_buffer_write_pointer_raw)                                         | 0xac8    |        4 | Auto-extracted signal write_pointer_raw from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_write_pointer_ts`](#rx_buffer_write_pointer_ts)                                           | 0xacc    |        4 | Auto-extracted signal write_pointer_ts from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_rx_mem_free_i`](#rx_buffer_rx_mem_free_i)                                                 | 0xad0    |        4 | Auto-extracted signal rx_mem_free_i from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_memory_write_data`](#rx_buffer_memory_write_data)                                         | 0xad4    |        4 | Auto-extracted signal memory_write_data from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_data_overrun_flg`](#rx_buffer_data_overrun_flg)                                           | 0xad8    |        4 | Auto-extracted signal data_overrun_flg from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_data_overrun_i`](#rx_buffer_data_overrun_i)                                               | 0xadc    |        4 | Auto-extracted signal data_overrun_i from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_overrun_condition`](#rx_buffer_overrun_condition)                                         | 0xae0    |        4 | Auto-extracted signal overrun_condition from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_rx_empty_i`](#rx_buffer_rx_empty_i)                                                       | 0xae4    |        4 | Auto-extracted signal rx_empty_i from rx_buffer.vhd                            |
+| can_bus.[`rx_buffer_is_free_word`](#rx_buffer_is_free_word)                                                   | 0xae8    |        4 | Auto-extracted signal is_free_word from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_commit_rx_frame`](#rx_buffer_commit_rx_frame)                                             | 0xaec    |        4 | Auto-extracted signal commit_rx_frame from rx_buffer.vhd                       |
+| can_bus.[`rx_buffer_commit_overrun_abort`](#rx_buffer_commit_overrun_abort)                                   | 0xaf0    |        4 | Auto-extracted signal commit_overrun_abort from rx_buffer.vhd                  |
+| can_bus.[`rx_buffer_read_increment`](#rx_buffer_read_increment)                                               | 0xaf4    |        4 | Auto-extracted signal read_increment from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_write_raw_OK`](#rx_buffer_write_raw_ok)                                                   | 0xaf8    |        4 | Auto-extracted signal write_raw_OK from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_write_raw_intent`](#rx_buffer_write_raw_intent)                                           | 0xafc    |        4 | Auto-extracted signal write_raw_intent from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_write_ts`](#rx_buffer_write_ts)                                                           | 0xb00    |        4 | Auto-extracted signal write_ts from rx_buffer.vhd                              |
+| can_bus.[`rx_buffer_stored_ts`](#rx_buffer_stored_ts)                                                         | 0xb04    |        4 | Auto-extracted signal stored_ts from rx_buffer.vhd                             |
+| can_bus.[`rx_buffer_data_selector`](#rx_buffer_data_selector)                                                 | 0xb08    |        4 | Auto-extracted signal data_selector from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_store_ts_wr_ptr`](#rx_buffer_store_ts_wr_ptr)                                             | 0xb0c    |        4 | Auto-extracted signal store_ts_wr_ptr from rx_buffer.vhd                       |
+| can_bus.[`rx_buffer_inc_ts_wr_ptr`](#rx_buffer_inc_ts_wr_ptr)                                                 | 0xb10    |        4 | Auto-extracted signal inc_ts_wr_ptr from rx_buffer.vhd                         |
+| can_bus.[`rx_buffer_reset_overrun_flag`](#rx_buffer_reset_overrun_flag)                                       | 0xb14    |        4 | Auto-extracted signal reset_overrun_flag from rx_buffer.vhd                    |
+| can_bus.[`rx_buffer_frame_form_w`](#rx_buffer_frame_form_w)                                                   | 0xb18    |        4 | Auto-extracted signal frame_form_w from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_timestamp_capture`](#rx_buffer_timestamp_capture)                                         | 0xb1c    |        4 | Auto-extracted signal timestamp_capture from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_timestamp_capture_ce`](#rx_buffer_timestamp_capture_ce)                                   | 0xb20    |        4 | Auto-extracted signal timestamp_capture_ce from rx_buffer.vhd                  |
+| can_bus.[`rx_buffer_RAM_write`](#rx_buffer_ram_write)                                                         | 0xb24    |        4 | Auto-extracted signal RAM_write from rx_buffer.vhd                             |
+| can_bus.[`rx_buffer_RAM_data_out`](#rx_buffer_ram_data_out)                                                   | 0xb28    |        4 | Auto-extracted signal RAM_data_out from rx_buffer.vhd                          |
+| can_bus.[`rx_buffer_RAM_write_address`](#rx_buffer_ram_write_address)                                         | 0xb2c    |        4 | Auto-extracted signal RAM_write_address from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_RAM_read_address`](#rx_buffer_ram_read_address)                                           | 0xb30    |        4 | Auto-extracted signal RAM_read_address from rx_buffer.vhd                      |
+| can_bus.[`rx_buffer_rx_buf_res_n_d`](#rx_buffer_rx_buf_res_n_d)                                               | 0xb34    |        4 | Auto-extracted signal rx_buf_res_n_d from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_rx_buf_res_n_q`](#rx_buffer_rx_buf_res_n_q)                                               | 0xb38    |        4 | Auto-extracted signal rx_buf_res_n_q from rx_buffer.vhd                        |
+| can_bus.[`rx_buffer_rx_buf_res_n_q_scan`](#rx_buffer_rx_buf_res_n_q_scan)                                     | 0xb3c    |        4 | Auto-extracted signal rx_buf_res_n_q_scan from rx_buffer.vhd                   |
+| can_bus.[`rx_buffer_rx_buf_ram_clk_en`](#rx_buffer_rx_buf_ram_clk_en)                                         | 0xb40    |        4 | Auto-extracted signal rx_buf_ram_clk_en from rx_buffer.vhd                     |
+| can_bus.[`rx_buffer_clk_ram`](#rx_buffer_clk_ram)                                                             | 0xb44    |        4 | Auto-extracted signal clk_ram from rx_buffer.vhd                               |
+| can_bus.[`rx_buffer_fsm_rx_fsm_ce`](#rx_buffer_fsm_rx_fsm_ce)                                                 | 0xb48    |        4 | Auto-extracted signal rx_fsm_ce from rx_buffer_fsm.vhd                         |
+| can_bus.[`rx_buffer_fsm_cmd_join`](#rx_buffer_fsm_cmd_join)                                                   | 0xb4c    |        4 | Auto-extracted signal cmd_join from rx_buffer_fsm.vhd                          |
+| can_bus.[`rx_buffer_pointers_write_pointer_raw_ce`](#rx_buffer_pointers_write_pointer_raw_ce)                 | 0xb50    |        4 | Auto-extracted signal write_pointer_raw_ce from rx_buffer_pointers.vhd         |
+| can_bus.[`rx_buffer_pointers_write_pointer_ts_ce`](#rx_buffer_pointers_write_pointer_ts_ce)                   | 0xb54    |        4 | Auto-extracted signal write_pointer_ts_ce from rx_buffer_pointers.vhd          |
+| can_bus.[`rx_buffer_ram_port_a_address_i`](#rx_buffer_ram_port_a_address_i)                                   | 0xb58    |        4 | Auto-extracted signal port_a_address_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_a_write_i`](#rx_buffer_ram_port_a_write_i)                                       | 0xb5c    |        4 | Auto-extracted signal port_a_write_i from rx_buffer_ram.vhd                    |
+| can_bus.[`rx_buffer_ram_port_a_data_in_i`](#rx_buffer_ram_port_a_data_in_i)                                   | 0xb60    |        4 | Auto-extracted signal port_a_data_in_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_b_address_i`](#rx_buffer_ram_port_b_address_i)                                   | 0xb64    |        4 | Auto-extracted signal port_b_address_i from rx_buffer_ram.vhd                  |
+| can_bus.[`rx_buffer_ram_port_b_data_out_i`](#rx_buffer_ram_port_b_data_out_i)                                 | 0xb68    |        4 | Auto-extracted signal port_b_data_out_i from rx_buffer_ram.vhd                 |
+| can_bus.[`rx_buffer_ram_tst_ena`](#rx_buffer_ram_tst_ena)                                                     | 0xb6c    |        4 | Auto-extracted signal tst_ena from rx_buffer_ram.vhd                           |
+| can_bus.[`rx_buffer_ram_tst_addr`](#rx_buffer_ram_tst_addr)                                                   | 0xb70    |        4 | Auto-extracted signal tst_addr from rx_buffer_ram.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_d`](#rx_shift_reg_res_n_i_d)                                                   | 0xb74    |        4 | Auto-extracted signal res_n_i_d from rx_shift_reg.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_q`](#rx_shift_reg_res_n_i_q)                                                   | 0xb78    |        4 | Auto-extracted signal res_n_i_q from rx_shift_reg.vhd                          |
+| can_bus.[`rx_shift_reg_res_n_i_q_scan`](#rx_shift_reg_res_n_i_q_scan)                                         | 0xb7c    |        4 | Auto-extracted signal res_n_i_q_scan from rx_shift_reg.vhd                     |
+| can_bus.[`rx_shift_reg_rx_shift_reg_q`](#rx_shift_reg_rx_shift_reg_q)                                         | 0xb80    |        4 | Auto-extracted signal rx_shift_reg_q from rx_shift_reg.vhd                     |
+| can_bus.[`rx_shift_reg_rx_shift_cmd`](#rx_shift_reg_rx_shift_cmd)                                             | 0xb84    |        4 | Auto-extracted signal rx_shift_cmd from rx_shift_reg.vhd                       |
+| can_bus.[`rx_shift_reg_rx_shift_in_sel_demuxed`](#rx_shift_reg_rx_shift_in_sel_demuxed)                       | 0xb88    |        4 | Auto-extracted signal rx_shift_in_sel_demuxed from rx_shift_reg.vhd            |
+| can_bus.[`rx_shift_reg_rec_is_rtr_i`](#rx_shift_reg_rec_is_rtr_i)                                             | 0xb8c    |        4 | Auto-extracted signal rec_is_rtr_i from rx_shift_reg.vhd                       |
+| can_bus.[`rx_shift_reg_rec_frame_type_i`](#rx_shift_reg_rec_frame_type_i)                                     | 0xb90    |        4 | Auto-extracted signal rec_frame_type_i from rx_shift_reg.vhd                   |
+| can_bus.[`sample_mux_sample`](#sample_mux_sample)                                                             | 0xb94    |        4 | Auto-extracted signal sample from sample_mux.vhd                               |
+| can_bus.[`sample_mux_prev_sample_d`](#sample_mux_prev_sample_d)                                               | 0xb98    |        4 | Auto-extracted signal prev_sample_d from sample_mux.vhd                        |
+| can_bus.[`sample_mux_prev_sample_q`](#sample_mux_prev_sample_q)                                               | 0xb9c    |        4 | Auto-extracted signal prev_sample_q from sample_mux.vhd                        |
+| can_bus.[`segment_end_detector_req_input`](#segment_end_detector_req_input)                                   | 0xba0    |        4 | Auto-extracted signal req_input from segment_end_detector.vhd                  |
+| can_bus.[`segment_end_detector_segm_end_req_capt_d`](#segment_end_detector_segm_end_req_capt_d)               | 0xba4    |        4 | Auto-extracted signal segm_end_req_capt_d from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_segm_end_req_capt_q`](#segment_end_detector_segm_end_req_capt_q)               | 0xba8    |        4 | Auto-extracted signal segm_end_req_capt_q from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_segm_end_req_capt_ce`](#segment_end_detector_segm_end_req_capt_ce)             | 0xbac    |        4 | Auto-extracted signal segm_end_req_capt_ce from segment_end_detector.vhd       |
+| can_bus.[`segment_end_detector_segm_end_req_capt_clr`](#segment_end_detector_segm_end_req_capt_clr)           | 0xbb0    |        4 | Auto-extracted signal segm_end_req_capt_clr from segment_end_detector.vhd      |
+| can_bus.[`segment_end_detector_segm_end_req_capt_dq`](#segment_end_detector_segm_end_req_capt_dq)             | 0xbb4    |        4 | Auto-extracted signal segm_end_req_capt_dq from segment_end_detector.vhd       |
+| can_bus.[`segment_end_detector_segm_end_nbt_valid`](#segment_end_detector_segm_end_nbt_valid)                 | 0xbb8    |        4 | Auto-extracted signal segm_end_nbt_valid from segment_end_detector.vhd         |
+| can_bus.[`segment_end_detector_segm_end_dbt_valid`](#segment_end_detector_segm_end_dbt_valid)                 | 0xbbc    |        4 | Auto-extracted signal segm_end_dbt_valid from segment_end_detector.vhd         |
+| can_bus.[`segment_end_detector_segm_end_nbt_dbt_valid`](#segment_end_detector_segm_end_nbt_dbt_valid)         | 0xbc0    |        4 | Auto-extracted signal segm_end_nbt_dbt_valid from segment_end_detector.vhd     |
+| can_bus.[`segment_end_detector_tseg1_end_req_valid`](#segment_end_detector_tseg1_end_req_valid)               | 0xbc4    |        4 | Auto-extracted signal tseg1_end_req_valid from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_tseg2_end_req_valid`](#segment_end_detector_tseg2_end_req_valid)               | 0xbc8    |        4 | Auto-extracted signal tseg2_end_req_valid from segment_end_detector.vhd        |
+| can_bus.[`segment_end_detector_h_sync_valid_i`](#segment_end_detector_h_sync_valid_i)                         | 0xbcc    |        4 | Auto-extracted signal h_sync_valid_i from segment_end_detector.vhd             |
+| can_bus.[`segment_end_detector_segment_end_i`](#segment_end_detector_segment_end_i)                           | 0xbd0    |        4 | Auto-extracted signal segment_end_i from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_nbt_tq_active`](#segment_end_detector_nbt_tq_active)                           | 0xbd4    |        4 | Auto-extracted signal nbt_tq_active from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_dbt_tq_active`](#segment_end_detector_dbt_tq_active)                           | 0xbd8    |        4 | Auto-extracted signal dbt_tq_active from segment_end_detector.vhd              |
+| can_bus.[`segment_end_detector_bt_ctr_clear_i`](#segment_end_detector_bt_ctr_clear_i)                         | 0xbdc    |        4 | Auto-extracted signal bt_ctr_clear_i from segment_end_detector.vhd             |
+| can_bus.[`shift_reg_shift_regs`](#shift_reg_shift_regs)                                                       | 0xbe0    |        4 | Auto-extracted signal shift_regs from shift_reg.vhd                            |
+| can_bus.[`shift_reg_next_shift_reg_val`](#shift_reg_next_shift_reg_val)                                       | 0xbe4    |        4 | Auto-extracted signal next_shift_reg_val from shift_reg.vhd                    |
+| can_bus.[`shift_reg_byte_shift_reg_in`](#shift_reg_byte_shift_reg_in)                                         | 0xbe8    |        4 | Auto-extracted signal shift_reg_in from shift_reg_byte.vhd                     |
+| can_bus.[`shift_reg_preload_shift_regs`](#shift_reg_preload_shift_regs)                                       | 0xbec    |        4 | Auto-extracted signal shift_regs from shift_reg_preload.vhd                    |
+| can_bus.[`shift_reg_preload_next_shift_reg_val`](#shift_reg_preload_next_shift_reg_val)                       | 0xbf0    |        4 | Auto-extracted signal next_shift_reg_val from shift_reg_preload.vhd            |
+| can_bus.[`sig_sync_rff`](#sig_sync_rff)                                                                       | 0xbf4    |        4 | Auto-extracted signal rff from sig_sync.vhd                                    |
+| can_bus.[`ssp_generator_btmc_d`](#ssp_generator_btmc_d)                                                       | 0xbf8    |        4 | Auto-extracted signal btmc_d from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_btmc_q`](#ssp_generator_btmc_q)                                                       | 0xbfc    |        4 | Auto-extracted signal btmc_q from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_btmc_add`](#ssp_generator_btmc_add)                                                   | 0xc00    |        4 | Auto-extracted signal btmc_add from ssp_generator.vhd                          |
+| can_bus.[`ssp_generator_btmc_ce`](#ssp_generator_btmc_ce)                                                     | 0xc04    |        4 | Auto-extracted signal btmc_ce from ssp_generator.vhd                           |
+| can_bus.[`ssp_generator_btmc_meas_running_d`](#ssp_generator_btmc_meas_running_d)                             | 0xc08    |        4 | Auto-extracted signal btmc_meas_running_d from ssp_generator.vhd               |
+| can_bus.[`ssp_generator_btmc_meas_running_q`](#ssp_generator_btmc_meas_running_q)                             | 0xc0c    |        4 | Auto-extracted signal btmc_meas_running_q from ssp_generator.vhd               |
+| can_bus.[`ssp_generator_sspc_d`](#ssp_generator_sspc_d)                                                       | 0xc10    |        4 | Auto-extracted signal sspc_d from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_sspc_q`](#ssp_generator_sspc_q)                                                       | 0xc14    |        4 | Auto-extracted signal sspc_q from ssp_generator.vhd                            |
+| can_bus.[`ssp_generator_sspc_ce`](#ssp_generator_sspc_ce)                                                     | 0xc18    |        4 | Auto-extracted signal sspc_ce from ssp_generator.vhd                           |
+| can_bus.[`ssp_generator_sspc_expired`](#ssp_generator_sspc_expired)                                           | 0xc1c    |        4 | Auto-extracted signal sspc_expired from ssp_generator.vhd                      |
+| can_bus.[`ssp_generator_sspc_threshold`](#ssp_generator_sspc_threshold)                                       | 0xc20    |        4 | Auto-extracted signal sspc_threshold from ssp_generator.vhd                    |
+| can_bus.[`ssp_generator_sspc_add`](#ssp_generator_sspc_add)                                                   | 0xc24    |        4 | Auto-extracted signal sspc_add from ssp_generator.vhd                          |
+| can_bus.[`ssp_generator_first_ssp_d`](#ssp_generator_first_ssp_d)                                             | 0xc28    |        4 | Auto-extracted signal first_ssp_d from ssp_generator.vhd                       |
+| can_bus.[`ssp_generator_first_ssp_q`](#ssp_generator_first_ssp_q)                                             | 0xc2c    |        4 | Auto-extracted signal first_ssp_q from ssp_generator.vhd                       |
+| can_bus.[`ssp_generator_sspc_ena_d`](#ssp_generator_sspc_ena_d)                                               | 0xc30    |        4 | Auto-extracted signal sspc_ena_d from ssp_generator.vhd                        |
+| can_bus.[`ssp_generator_sspc_ena_q`](#ssp_generator_sspc_ena_q)                                               | 0xc34    |        4 | Auto-extracted signal sspc_ena_q from ssp_generator.vhd                        |
+| can_bus.[`ssp_generator_ssp_delay_padded`](#ssp_generator_ssp_delay_padded)                                   | 0xc38    |        4 | Auto-extracted signal ssp_delay_padded from ssp_generator.vhd                  |
+| can_bus.[`synchronisation_checker_resync_edge`](#synchronisation_checker_resync_edge)                         | 0xc3c    |        4 | Auto-extracted signal resync_edge from synchronisation_checker.vhd             |
+| can_bus.[`synchronisation_checker_h_sync_edge`](#synchronisation_checker_h_sync_edge)                         | 0xc40    |        4 | Auto-extracted signal h_sync_edge from synchronisation_checker.vhd             |
+| can_bus.[`synchronisation_checker_h_or_re_sync_edge`](#synchronisation_checker_h_or_re_sync_edge)             | 0xc44    |        4 | Auto-extracted signal h_or_re_sync_edge from synchronisation_checker.vhd       |
+| can_bus.[`synchronisation_checker_sync_flag`](#synchronisation_checker_sync_flag)                             | 0xc48    |        4 | Auto-extracted signal sync_flag from synchronisation_checker.vhd               |
+| can_bus.[`synchronisation_checker_sync_flag_ce`](#synchronisation_checker_sync_flag_ce)                       | 0xc4c    |        4 | Auto-extracted signal sync_flag_ce from synchronisation_checker.vhd            |
+| can_bus.[`synchronisation_checker_sync_flag_nxt`](#synchronisation_checker_sync_flag_nxt)                     | 0xc50    |        4 | Auto-extracted signal sync_flag_nxt from synchronisation_checker.vhd           |
+| can_bus.[`test_registers_reg_map_reg_sel`](#test_registers_reg_map_reg_sel)                                   | 0xc54    |        4 | Auto-extracted signal reg_sel from test_registers_reg_map.vhd                  |
+| can_bus.[`test_registers_reg_map_read_data_mux_in`](#test_registers_reg_map_read_data_mux_in)                 | 0xc58    |        4 | Auto-extracted signal read_data_mux_in from test_registers_reg_map.vhd         |
+| can_bus.[`test_registers_reg_map_read_data_mask_n`](#test_registers_reg_map_read_data_mask_n)                 | 0xc5c    |        4 | Auto-extracted signal read_data_mask_n from test_registers_reg_map.vhd         |
+| can_bus.[`test_registers_reg_map_read_mux_ena`](#test_registers_reg_map_read_mux_ena)                         | 0xc60    |        4 | Auto-extracted signal read_mux_ena from test_registers_reg_map.vhd             |
+| can_bus.[`trigger_generator_rx_trig_req_q`](#trigger_generator_rx_trig_req_q)                                 | 0xc64    |        4 | Auto-extracted signal rx_trig_req_q from trigger_generator.vhd                 |
+| can_bus.[`trigger_generator_tx_trig_req_flag_d`](#trigger_generator_tx_trig_req_flag_d)                       | 0xc68    |        4 | Auto-extracted signal tx_trig_req_flag_d from trigger_generator.vhd            |
+| can_bus.[`trigger_generator_tx_trig_req_flag_q`](#trigger_generator_tx_trig_req_flag_q)                       | 0xc6c    |        4 | Auto-extracted signal tx_trig_req_flag_q from trigger_generator.vhd            |
+| can_bus.[`trigger_generator_tx_trig_req_flag_dq`](#trigger_generator_tx_trig_req_flag_dq)                     | 0xc70    |        4 | Auto-extracted signal tx_trig_req_flag_dq from trigger_generator.vhd           |
+| can_bus.[`trigger_mux_tx_trigger_q`](#trigger_mux_tx_trigger_q)                                               | 0xc74    |        4 | Auto-extracted signal tx_trigger_q from trigger_mux.vhd                        |
+| can_bus.[`trv_delay_meas_trv_meas_progress_d`](#trv_delay_meas_trv_meas_progress_d)                           | 0xc78    |        4 | Auto-extracted signal trv_meas_progress_d from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_meas_progress_q`](#trv_delay_meas_trv_meas_progress_q)                           | 0xc7c    |        4 | Auto-extracted signal trv_meas_progress_q from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_meas_progress_del`](#trv_delay_meas_trv_meas_progress_del)                       | 0xc80    |        4 | Auto-extracted signal trv_meas_progress_del from trv_delay_meas.vhd            |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_q`](#trv_delay_meas_trv_delay_ctr_q)                                   | 0xc84    |        4 | Auto-extracted signal trv_delay_ctr_q from trv_delay_meas.vhd                  |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_d`](#trv_delay_meas_trv_delay_ctr_d)                                   | 0xc88    |        4 | Auto-extracted signal trv_delay_ctr_d from trv_delay_meas.vhd                  |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_add`](#trv_delay_meas_trv_delay_ctr_add)                               | 0xc8c    |        4 | Auto-extracted signal trv_delay_ctr_add from trv_delay_meas.vhd                |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_q_padded`](#trv_delay_meas_trv_delay_ctr_q_padded)                     | 0xc90    |        4 | Auto-extracted signal trv_delay_ctr_q_padded from trv_delay_meas.vhd           |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_d`](#trv_delay_meas_trv_delay_ctr_rst_d)                           | 0xc94    |        4 | Auto-extracted signal trv_delay_ctr_rst_d from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_q`](#trv_delay_meas_trv_delay_ctr_rst_q)                           | 0xc98    |        4 | Auto-extracted signal trv_delay_ctr_rst_q from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_ctr_rst_q_scan`](#trv_delay_meas_trv_delay_ctr_rst_q_scan)                 | 0xc9c    |        4 | Auto-extracted signal trv_delay_ctr_rst_q_scan from trv_delay_meas.vhd         |
+| can_bus.[`trv_delay_meas_ssp_shadow_ce`](#trv_delay_meas_ssp_shadow_ce)                                       | 0xca0    |        4 | Auto-extracted signal ssp_shadow_ce from trv_delay_meas.vhd                    |
+| can_bus.[`trv_delay_meas_ssp_delay_raw`](#trv_delay_meas_ssp_delay_raw)                                       | 0xca4    |        4 | Auto-extracted signal ssp_delay_raw from trv_delay_meas.vhd                    |
+| can_bus.[`trv_delay_meas_ssp_delay_saturated`](#trv_delay_meas_ssp_delay_saturated)                           | 0xca8    |        4 | Auto-extracted signal ssp_delay_saturated from trv_delay_meas.vhd              |
+| can_bus.[`trv_delay_meas_trv_delay_sum`](#trv_delay_meas_trv_delay_sum)                                       | 0xcac    |        4 | Auto-extracted signal trv_delay_sum from trv_delay_meas.vhd                    |
+| can_bus.[`tx_arbitrator_select_buf_avail`](#tx_arbitrator_select_buf_avail)                                   | 0xcb0    |        4 | Auto-extracted signal select_buf_avail from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_txtb_selected_input`](#tx_arbitrator_txtb_selected_input)                             | 0xcb4    |        4 | Auto-extracted signal txtb_selected_input from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_txtb_timestamp`](#tx_arbitrator_txtb_timestamp)                                       | 0xcb8    |        4 | Auto-extracted signal txtb_timestamp from tx_arbitrator.vhd                    |
+| can_bus.[`tx_arbitrator_timestamp_valid`](#tx_arbitrator_timestamp_valid)                                     | 0xcbc    |        4 | Auto-extracted signal timestamp_valid from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_select_index_changed`](#tx_arbitrator_select_index_changed)                           | 0xcc0    |        4 | Auto-extracted signal select_index_changed from tx_arbitrator.vhd              |
+| can_bus.[`tx_arbitrator_validated_buffer`](#tx_arbitrator_validated_buffer)                                   | 0xcc4    |        4 | Auto-extracted signal validated_buffer from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_ts_low_internal`](#tx_arbitrator_ts_low_internal)                                     | 0xcc8    |        4 | Auto-extracted signal ts_low_internal from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_tran_dlc_dbl_buf`](#tx_arbitrator_tran_dlc_dbl_buf)                                   | 0xccc    |        4 | Auto-extracted signal tran_dlc_dbl_buf from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_tran_is_rtr_dbl_buf`](#tx_arbitrator_tran_is_rtr_dbl_buf)                             | 0xcd0    |        4 | Auto-extracted signal tran_is_rtr_dbl_buf from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_ident_type_dbl_buf`](#tx_arbitrator_tran_ident_type_dbl_buf)                     | 0xcd4    |        4 | Auto-extracted signal tran_ident_type_dbl_buf from tx_arbitrator.vhd           |
+| can_bus.[`tx_arbitrator_tran_frame_type_dbl_buf`](#tx_arbitrator_tran_frame_type_dbl_buf)                     | 0xcd8    |        4 | Auto-extracted signal tran_frame_type_dbl_buf from tx_arbitrator.vhd           |
+| can_bus.[`tx_arbitrator_tran_brs_dbl_buf`](#tx_arbitrator_tran_brs_dbl_buf)                                   | 0xcdc    |        4 | Auto-extracted signal tran_brs_dbl_buf from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_tran_dlc_com`](#tx_arbitrator_tran_dlc_com)                                           | 0xce0    |        4 | Auto-extracted signal tran_dlc_com from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_tran_is_rtr_com`](#tx_arbitrator_tran_is_rtr_com)                                     | 0xce4    |        4 | Auto-extracted signal tran_is_rtr_com from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_tran_ident_type_com`](#tx_arbitrator_tran_ident_type_com)                             | 0xce8    |        4 | Auto-extracted signal tran_ident_type_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_frame_type_com`](#tx_arbitrator_tran_frame_type_com)                             | 0xcec    |        4 | Auto-extracted signal tran_frame_type_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_tran_brs_com`](#tx_arbitrator_tran_brs_com)                                           | 0xcf0    |        4 | Auto-extracted signal tran_brs_com from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_tran_frame_valid_com`](#tx_arbitrator_tran_frame_valid_com)                           | 0xcf4    |        4 | Auto-extracted signal tran_frame_valid_com from tx_arbitrator.vhd              |
+| can_bus.[`tx_arbitrator_tran_identifier_com`](#tx_arbitrator_tran_identifier_com)                             | 0xcf8    |        4 | Auto-extracted signal tran_identifier_com from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_load_ts_lw_addr`](#tx_arbitrator_load_ts_lw_addr)                                     | 0xcfc    |        4 | Auto-extracted signal load_ts_lw_addr from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_load_ts_uw_addr`](#tx_arbitrator_load_ts_uw_addr)                                     | 0xd00    |        4 | Auto-extracted signal load_ts_uw_addr from tx_arbitrator.vhd                   |
+| can_bus.[`tx_arbitrator_load_ffmt_w_addr`](#tx_arbitrator_load_ffmt_w_addr)                                   | 0xd04    |        4 | Auto-extracted signal load_ffmt_w_addr from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_load_ident_w_addr`](#tx_arbitrator_load_ident_w_addr)                                 | 0xd08    |        4 | Auto-extracted signal load_ident_w_addr from tx_arbitrator.vhd                 |
+| can_bus.[`tx_arbitrator_store_ts_l_w`](#tx_arbitrator_store_ts_l_w)                                           | 0xd0c    |        4 | Auto-extracted signal store_ts_l_w from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_store_md_w`](#tx_arbitrator_store_md_w)                                               | 0xd10    |        4 | Auto-extracted signal store_md_w from tx_arbitrator.vhd                        |
+| can_bus.[`tx_arbitrator_store_ident_w`](#tx_arbitrator_store_ident_w)                                         | 0xd14    |        4 | Auto-extracted signal store_ident_w from tx_arbitrator.vhd                     |
+| can_bus.[`tx_arbitrator_buffer_md_w`](#tx_arbitrator_buffer_md_w)                                             | 0xd18    |        4 | Auto-extracted signal buffer_md_w from tx_arbitrator.vhd                       |
+| can_bus.[`tx_arbitrator_store_last_txtb_index`](#tx_arbitrator_store_last_txtb_index)                         | 0xd1c    |        4 | Auto-extracted signal store_last_txtb_index from tx_arbitrator.vhd             |
+| can_bus.[`tx_arbitrator_frame_valid_com_set`](#tx_arbitrator_frame_valid_com_set)                             | 0xd20    |        4 | Auto-extracted signal frame_valid_com_set from tx_arbitrator.vhd               |
+| can_bus.[`tx_arbitrator_frame_valid_com_clear`](#tx_arbitrator_frame_valid_com_clear)                         | 0xd24    |        4 | Auto-extracted signal frame_valid_com_clear from tx_arbitrator.vhd             |
+| can_bus.[`tx_arbitrator_tx_arb_locked`](#tx_arbitrator_tx_arb_locked)                                         | 0xd28    |        4 | Auto-extracted signal tx_arb_locked from tx_arbitrator.vhd                     |
+| can_bus.[`tx_arbitrator_txtb_meta_clk_en`](#tx_arbitrator_txtb_meta_clk_en)                                   | 0xd2c    |        4 | Auto-extracted signal txtb_meta_clk_en from tx_arbitrator.vhd                  |
+| can_bus.[`tx_arbitrator_drv_tttm_ena`](#tx_arbitrator_drv_tttm_ena)                                           | 0xd30    |        4 | Auto-extracted signal drv_tttm_ena from tx_arbitrator.vhd                      |
+| can_bus.[`tx_arbitrator_fsm_tx_arb_fsm_ce`](#tx_arbitrator_fsm_tx_arb_fsm_ce)                                 | 0xd34    |        4 | Auto-extracted signal tx_arb_fsm_ce from tx_arbitrator_fsm.vhd                 |
+| can_bus.[`tx_arbitrator_fsm_fsm_wait_state_d`](#tx_arbitrator_fsm_fsm_wait_state_d)                           | 0xd38    |        4 | Auto-extracted signal fsm_wait_state_d from tx_arbitrator_fsm.vhd              |
+| can_bus.[`tx_arbitrator_fsm_fsm_wait_state_q`](#tx_arbitrator_fsm_fsm_wait_state_q)                           | 0xd3c    |        4 | Auto-extracted signal fsm_wait_state_q from tx_arbitrator_fsm.vhd              |
+| can_bus.[`tx_data_cache_tx_cache_mem`](#tx_data_cache_tx_cache_mem)                                           | 0xd40    |        4 | Auto-extracted signal tx_cache_mem from tx_data_cache.vhd                      |
+| can_bus.[`tx_shift_reg_tx_sr_output`](#tx_shift_reg_tx_sr_output)                                             | 0xd44    |        4 | Auto-extracted signal tx_sr_output from tx_shift_reg.vhd                       |
+| can_bus.[`tx_shift_reg_tx_sr_ce`](#tx_shift_reg_tx_sr_ce)                                                     | 0xd48    |        4 | Auto-extracted signal tx_sr_ce from tx_shift_reg.vhd                           |
+| can_bus.[`tx_shift_reg_tx_sr_pload`](#tx_shift_reg_tx_sr_pload)                                               | 0xd4c    |        4 | Auto-extracted signal tx_sr_pload from tx_shift_reg.vhd                        |
+| can_bus.[`tx_shift_reg_tx_sr_pload_val`](#tx_shift_reg_tx_sr_pload_val)                                       | 0xd50    |        4 | Auto-extracted signal tx_sr_pload_val from tx_shift_reg.vhd                    |
+| can_bus.[`tx_shift_reg_tx_base_id`](#tx_shift_reg_tx_base_id)                                                 | 0xd54    |        4 | Auto-extracted signal tx_base_id from tx_shift_reg.vhd                         |
+| can_bus.[`tx_shift_reg_tx_ext_id`](#tx_shift_reg_tx_ext_id)                                                   | 0xd58    |        4 | Auto-extracted signal tx_ext_id from tx_shift_reg.vhd                          |
+| can_bus.[`tx_shift_reg_tx_crc`](#tx_shift_reg_tx_crc)                                                         | 0xd5c    |        4 | Auto-extracted signal tx_crc from tx_shift_reg.vhd                             |
+| can_bus.[`tx_shift_reg_bst_ctr_grey`](#tx_shift_reg_bst_ctr_grey)                                             | 0xd60    |        4 | Auto-extracted signal bst_ctr_grey from tx_shift_reg.vhd                       |
+| can_bus.[`tx_shift_reg_bst_parity`](#tx_shift_reg_bst_parity)                                                 | 0xd64    |        4 | Auto-extracted signal bst_parity from tx_shift_reg.vhd                         |
+| can_bus.[`tx_shift_reg_stuff_count`](#tx_shift_reg_stuff_count)                                               | 0xd68    |        4 | Auto-extracted signal stuff_count from tx_shift_reg.vhd                        |
+| can_bus.[`txt_buffer_txtb_user_accessible`](#txt_buffer_txtb_user_accessible)                                 | 0xd6c    |        4 | Auto-extracted signal txtb_user_accessible from txt_buffer.vhd                 |
+| can_bus.[`txt_buffer_hw_cbs`](#txt_buffer_hw_cbs)                                                             | 0xd70    |        4 | Auto-extracted signal hw_cbs from txt_buffer.vhd                               |
+| can_bus.[`txt_buffer_sw_cbs`](#txt_buffer_sw_cbs)                                                             | 0xd74    |        4 | Auto-extracted signal sw_cbs from txt_buffer.vhd                               |
+| can_bus.[`txt_buffer_txtb_unmask_data_ram`](#txt_buffer_txtb_unmask_data_ram)                                 | 0xd78    |        4 | Auto-extracted signal txtb_unmask_data_ram from txt_buffer.vhd                 |
+| can_bus.[`txt_buffer_txtb_port_b_data_i`](#txt_buffer_txtb_port_b_data_i)                                     | 0xd7c    |        4 | Auto-extracted signal txtb_port_b_data_i from txt_buffer.vhd                   |
+| can_bus.[`txt_buffer_ram_write`](#txt_buffer_ram_write)                                                       | 0xd80    |        4 | Auto-extracted signal ram_write from txt_buffer.vhd                            |
+| can_bus.[`txt_buffer_ram_read_address`](#txt_buffer_ram_read_address)                                         | 0xd84    |        4 | Auto-extracted signal ram_read_address from txt_buffer.vhd                     |
+| can_bus.[`txt_buffer_txtb_ram_clk_en`](#txt_buffer_txtb_ram_clk_en)                                           | 0xd88    |        4 | Auto-extracted signal txtb_ram_clk_en from txt_buffer.vhd                      |
+| can_bus.[`txt_buffer_clk_ram`](#txt_buffer_clk_ram)                                                           | 0xd8c    |        4 | Auto-extracted signal clk_ram from txt_buffer.vhd                              |
+| can_bus.[`txt_buffer_fsm_abort_applied`](#txt_buffer_fsm_abort_applied)                                       | 0xd90    |        4 | Auto-extracted signal abort_applied from txt_buffer_fsm.vhd                    |
+| can_bus.[`txt_buffer_fsm_txt_fsm_ce`](#txt_buffer_fsm_txt_fsm_ce)                                             | 0xd94    |        4 | Auto-extracted signal txt_fsm_ce from txt_buffer_fsm.vhd                       |
+| can_bus.[`txt_buffer_fsm_go_to_failed`](#txt_buffer_fsm_go_to_failed)                                         | 0xd98    |        4 | Auto-extracted signal go_to_failed from txt_buffer_fsm.vhd                     |
+| can_bus.[`txt_buffer_fsm_transient_state`](#txt_buffer_fsm_transient_state)                                   | 0xd9c    |        4 | Auto-extracted signal transient_state from txt_buffer_fsm.vhd                  |
+| can_bus.[`txt_buffer_ram_port_a_address_i`](#txt_buffer_ram_port_a_address_i)                                 | 0xda0    |        4 | Auto-extracted signal port_a_address_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_a_write_i`](#txt_buffer_ram_port_a_write_i)                                     | 0xda4    |        4 | Auto-extracted signal port_a_write_i from txt_buffer_ram.vhd                   |
+| can_bus.[`txt_buffer_ram_port_a_data_in_i`](#txt_buffer_ram_port_a_data_in_i)                                 | 0xda8    |        4 | Auto-extracted signal port_a_data_in_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_b_address_i`](#txt_buffer_ram_port_b_address_i)                                 | 0xdac    |        4 | Auto-extracted signal port_b_address_i from txt_buffer_ram.vhd                 |
+| can_bus.[`txt_buffer_ram_port_b_data_out_i`](#txt_buffer_ram_port_b_data_out_i)                               | 0xdb0    |        4 | Auto-extracted signal port_b_data_out_i from txt_buffer_ram.vhd                |
+| can_bus.[`txt_buffer_ram_tst_ena`](#txt_buffer_ram_tst_ena)                                                   | 0xdb4    |        4 | Auto-extracted signal tst_ena from txt_buffer_ram.vhd                          |
+| can_bus.[`txt_buffer_ram_tst_addr`](#txt_buffer_ram_tst_addr)                                                 | 0xdb8    |        4 | Auto-extracted signal tst_addr from txt_buffer_ram.vhd                         |
+| can_bus.[`access_signaler_be_active`](#access_signaler_be_active)                                             | 0xdbc    |        4 | Auto-extracted signal be_active from access_signaler.vhd                       |
+| can_bus.[`access_signaler_access_in`](#access_signaler_access_in)                                             | 0xdc0    |        4 | Auto-extracted signal access_in from access_signaler.vhd                       |
+| can_bus.[`access_signaler_access_active`](#access_signaler_access_active)                                     | 0xdc4    |        4 | Auto-extracted signal access_active from access_signaler.vhd                   |
+| can_bus.[`access_signaler_access_active_reg`](#access_signaler_access_active_reg)                             | 0xdc8    |        4 | Auto-extracted signal access_active_reg from access_signaler.vhd               |
+| can_bus.[`address_decoder_addr_dec_i`](#address_decoder_addr_dec_i)                                           | 0xdcc    |        4 | Auto-extracted signal addr_dec_i from address_decoder.vhd                      |
+| can_bus.[`address_decoder_addr_dec_enabled_i`](#address_decoder_addr_dec_enabled_i)                           | 0xdd0    |        4 | Auto-extracted signal addr_dec_enabled_i from address_decoder.vhd              |
+
+## ahb_ifc_hsel_valid
+Auto-extracted signal hsel_valid from ahb_ifc.vhd
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_write_acc_d
+Auto-extracted signal write_acc_d from ahb_ifc.vhd
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_write_acc_q
+Auto-extracted signal write_acc_q from ahb_ifc.vhd
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_haddr_q
+Auto-extracted signal haddr_q from ahb_ifc.vhd
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_h_ready_raw
+Auto-extracted signal h_ready_raw from ahb_ifc.vhd
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_sbe_d
+Auto-extracted signal sbe_d from ahb_ifc.vhd
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_sbe_q
+Auto-extracted signal sbe_q from ahb_ifc.vhd
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_swr_i
+Auto-extracted signal swr_i from ahb_ifc.vhd
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ahb_ifc_srd_i
+Auto-extracted signal srd_i from ahb_ifc.vhd
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_discard_stuff_bit
+Auto-extracted signal discard_stuff_bit from bit_destuffing.vhd
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_non_fix_to_fix_chng
+Auto-extracted signal non_fix_to_fix_chng from bit_destuffing.vhd
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_lvl_reached
+Auto-extracted signal stuff_lvl_reached from bit_destuffing.vhd
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_rule_violate
+Auto-extracted signal stuff_rule_violate from bit_destuffing.vhd
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_enable_prev
+Auto-extracted signal enable_prev from bit_destuffing.vhd
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_fixed_prev_q
+Auto-extracted signal fixed_prev_q from bit_destuffing.vhd
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_fixed_prev_d
+Auto-extracted signal fixed_prev_d from bit_destuffing.vhd
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_same_bits_erase
+Auto-extracted signal same_bits_erase from bit_destuffing.vhd
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_destuffed_q
+Auto-extracted signal destuffed_q from bit_destuffing.vhd
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_destuffed_d
+Auto-extracted signal destuffed_d from bit_destuffing.vhd
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_err_q
+Auto-extracted signal stuff_err_q from bit_destuffing.vhd
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_stuff_err_d
+Auto-extracted signal stuff_err_d from bit_destuffing.vhd
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_prev_val_q
+Auto-extracted signal prev_val_q from bit_destuffing.vhd
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_destuffing_prev_val_d
+Auto-extracted signal prev_val_d from bit_destuffing.vhd
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_d
+Auto-extracted signal bit_err_d from bit_err_detector.vhd
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_q
+Auto-extracted signal bit_err_q from bit_err_detector.vhd
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_capt_d
+Auto-extracted signal bit_err_ssp_capt_d from bit_err_detector.vhd
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_capt_q
+Auto-extracted signal bit_err_ssp_capt_q from bit_err_detector.vhd
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_valid
+Auto-extracted signal bit_err_ssp_valid from bit_err_detector.vhd
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_ssp_condition
+Auto-extracted signal bit_err_ssp_condition from bit_err_detector.vhd
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_err_detector_bit_err_norm_valid
+Auto-extracted signal bit_err_norm_valid from bit_err_detector.vhd
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_filter_masked_input
+Auto-extracted signal masked_input from bit_filter.vhd
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_filter_masked_value
+Auto-extracted signal masked_value from bit_filter.vhd
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_sel_tseg1
+Auto-extracted signal sel_tseg1 from bit_segment_meter.vhd
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exp_seg_length_ce
+Auto-extracted signal exp_seg_length_ce from bit_segment_meter.vhd
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_mt_sjw
+Auto-extracted signal phase_err_mt_sjw from bit_segment_meter.vhd
+- Offset: `0x88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_eq_sjw
+Auto-extracted signal phase_err_eq_sjw from bit_segment_meter.vhd
+- Offset: `0x8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_ph2_immediate
+Auto-extracted signal exit_ph2_immediate from bit_segment_meter.vhd
+- Offset: `0x90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular
+Auto-extracted signal exit_segm_regular from bit_segment_meter.vhd
+- Offset: `0x94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular_tseg1
+Auto-extracted signal exit_segm_regular_tseg1 from bit_segment_meter.vhd
+- Offset: `0x98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_exit_segm_regular_tseg2
+Auto-extracted signal exit_segm_regular_tseg2 from bit_segment_meter.vhd
+- Offset: `0x9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_sjw_mt_zero
+Auto-extracted signal sjw_mt_zero from bit_segment_meter.vhd
+- Offset: `0xa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_use_basic_segm_length
+Auto-extracted signal use_basic_segm_length from bit_segment_meter.vhd
+- Offset: `0xa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_phase_err_sjw_by_one
+Auto-extracted signal phase_err_sjw_by_one from bit_segment_meter.vhd
+- Offset: `0xa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_segment_meter_shorten_tseg1_after_tseg2
+Auto-extracted signal shorten_tseg1_after_tseg2 from bit_segment_meter.vhd
+- Offset: `0xac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_i
+Auto-extracted signal data_out_i from bit_stuffing.vhd
+- Offset: `0xb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_halt_q
+Auto-extracted signal data_halt_q from bit_stuffing.vhd
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_halt_d
+Auto-extracted signal data_halt_d from bit_stuffing.vhd
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_fixed_reg_q
+Auto-extracted signal fixed_reg_q from bit_stuffing.vhd
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_fixed_reg_d
+Auto-extracted signal fixed_reg_d from bit_stuffing.vhd
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_enable_prev
+Auto-extracted signal enable_prev from bit_stuffing.vhd
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_non_fix_to_fix_chng
+Auto-extracted signal non_fix_to_fix_chng from bit_stuffing.vhd
+- Offset: `0xc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_stuff_lvl_reached
+Auto-extracted signal stuff_lvl_reached from bit_stuffing.vhd
+- Offset: `0xcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_same_bits_rst_trig
+Auto-extracted signal same_bits_rst_trig from bit_stuffing.vhd
+- Offset: `0xd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_same_bits_rst
+Auto-extracted signal same_bits_rst from bit_stuffing.vhd
+- Offset: `0xd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_insert_stuff_bit
+Auto-extracted signal insert_stuff_bit from bit_stuffing.vhd
+- Offset: `0xd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_d_ena
+Auto-extracted signal data_out_d_ena from bit_stuffing.vhd
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_d
+Auto-extracted signal data_out_d from bit_stuffing.vhd
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_stuffing_data_out_ce
+Auto-extracted signal data_out_ce from bit_stuffing.vhd
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_tq_nbt
+Auto-extracted signal drv_tq_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_prs_nbt
+Auto-extracted signal drv_prs_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph1_nbt
+Auto-extracted signal drv_ph1_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph2_nbt
+Auto-extracted signal drv_ph2_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_sjw_nbt
+Auto-extracted signal drv_sjw_nbt from bit_time_cfg_capture.vhd
+- Offset: `0xf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_tq_dbt
+Auto-extracted signal drv_tq_dbt from bit_time_cfg_capture.vhd
+- Offset: `0xfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_prs_dbt
+Auto-extracted signal drv_prs_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x100`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph1_dbt
+Auto-extracted signal drv_ph1_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x104`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ph2_dbt
+Auto-extracted signal drv_ph2_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x108`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_sjw_dbt
+Auto-extracted signal drv_sjw_dbt from bit_time_cfg_capture.vhd
+- Offset: `0x10c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_tseg1_nbt_d
+Auto-extracted signal tseg1_nbt_d from bit_time_cfg_capture.vhd
+- Offset: `0x110`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_tseg1_dbt_d
+Auto-extracted signal tseg1_dbt_d from bit_time_cfg_capture.vhd
+- Offset: `0x114`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena
+Auto-extracted signal drv_ena from bit_time_cfg_capture.vhd
+- Offset: `0x118`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena_reg
+Auto-extracted signal drv_ena_reg from bit_time_cfg_capture.vhd
+- Offset: `0x11c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_drv_ena_reg_2
+Auto-extracted signal drv_ena_reg_2 from bit_time_cfg_capture.vhd
+- Offset: `0x120`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_cfg_capture_capture
+Auto-extracted signal capture from bit_time_cfg_capture.vhd
+- Offset: `0x124`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_d
+Auto-extracted signal tq_counter_d from bit_time_counters.vhd
+- Offset: `0x128`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_q
+Auto-extracted signal tq_counter_q from bit_time_counters.vhd
+- Offset: `0x12c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_ce
+Auto-extracted signal tq_counter_ce from bit_time_counters.vhd
+- Offset: `0x130`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_counter_allow
+Auto-extracted signal tq_counter_allow from bit_time_counters.vhd
+- Offset: `0x134`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_tq_edge_i
+Auto-extracted signal tq_edge_i from bit_time_counters.vhd
+- Offset: `0x138`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_d
+Auto-extracted signal segm_counter_d from bit_time_counters.vhd
+- Offset: `0x13c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_q
+Auto-extracted signal segm_counter_q from bit_time_counters.vhd
+- Offset: `0x140`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_counters_segm_counter_ce
+Auto-extracted signal segm_counter_ce from bit_time_counters.vhd
+- Offset: `0x144`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bit_time_fsm_bt_fsm_ce
+Auto-extracted signal bt_fsm_ce from bit_time_fsm.vhd
+- Offset: `0x148`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ena
+Auto-extracted signal drv_ena from bus_sampling.vhd
+- Offset: `0x14c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ssp_offset
+Auto-extracted signal drv_ssp_offset from bus_sampling.vhd
+- Offset: `0x150`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_drv_ssp_delay_select
+Auto-extracted signal drv_ssp_delay_select from bus_sampling.vhd
+- Offset: `0x154`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_data_rx_synced
+Auto-extracted signal data_rx_synced from bus_sampling.vhd
+- Offset: `0x158`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_prev_Sample
+Auto-extracted signal prev_Sample from bus_sampling.vhd
+- Offset: `0x15c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_sample_sec_i
+Auto-extracted signal sample_sec_i from bus_sampling.vhd
+- Offset: `0x160`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_data_tx_delayed
+Auto-extracted signal data_tx_delayed from bus_sampling.vhd
+- Offset: `0x164`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_edge_rx_valid
+Auto-extracted signal edge_rx_valid from bus_sampling.vhd
+- Offset: `0x168`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_edge_tx_valid
+Auto-extracted signal edge_tx_valid from bus_sampling.vhd
+- Offset: `0x16c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_ssp_delay
+Auto-extracted signal ssp_delay from bus_sampling.vhd
+- Offset: `0x170`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_tx_trigger_q
+Auto-extracted signal tx_trigger_q from bus_sampling.vhd
+- Offset: `0x174`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_tx_trigger_ssp
+Auto-extracted signal tx_trigger_ssp from bus_sampling.vhd
+- Offset: `0x178`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_d
+Auto-extracted signal shift_regs_res_d from bus_sampling.vhd
+- Offset: `0x17c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_q
+Auto-extracted signal shift_regs_res_q from bus_sampling.vhd
+- Offset: `0x180`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_shift_regs_res_q_scan
+Auto-extracted signal shift_regs_res_q_scan from bus_sampling.vhd
+- Offset: `0x184`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_sampling_ssp_enable
+Auto-extracted signal ssp_enable from bus_sampling.vhd
+- Offset: `0x188`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_i
+Auto-extracted signal tx_ctr_i from bus_traffic_counters.vhd
+- Offset: `0x18c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_i
+Auto-extracted signal rx_ctr_i from bus_traffic_counters.vhd
+- Offset: `0x190`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_d
+Auto-extracted signal tx_ctr_rst_n_d from bus_traffic_counters.vhd
+- Offset: `0x194`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_q
+Auto-extracted signal tx_ctr_rst_n_q from bus_traffic_counters.vhd
+- Offset: `0x198`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_tx_ctr_rst_n_q_scan
+Auto-extracted signal tx_ctr_rst_n_q_scan from bus_traffic_counters.vhd
+- Offset: `0x19c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_d
+Auto-extracted signal rx_ctr_rst_n_d from bus_traffic_counters.vhd
+- Offset: `0x1a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_q
+Auto-extracted signal rx_ctr_rst_n_q from bus_traffic_counters.vhd
+- Offset: `0x1a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## bus_traffic_counters_rx_ctr_rst_n_q_scan
+Auto-extracted signal rx_ctr_rst_n_q_scan from bus_traffic_counters.vhd
+- Offset: `0x1a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_paddr
+Auto-extracted signal s_apb_paddr from can_apb_tb.vhd
+- Offset: `0x1ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_penable
+Auto-extracted signal s_apb_penable from can_apb_tb.vhd
+- Offset: `0x1b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pprot
+Auto-extracted signal s_apb_pprot from can_apb_tb.vhd
+- Offset: `0x1b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_prdata
+Auto-extracted signal s_apb_prdata from can_apb_tb.vhd
+- Offset: `0x1b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pready
+Auto-extracted signal s_apb_pready from can_apb_tb.vhd
+- Offset: `0x1bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_psel
+Auto-extracted signal s_apb_psel from can_apb_tb.vhd
+- Offset: `0x1c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pslverr
+Auto-extracted signal s_apb_pslverr from can_apb_tb.vhd
+- Offset: `0x1c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pstrb
+Auto-extracted signal s_apb_pstrb from can_apb_tb.vhd
+- Offset: `0x1c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pwdata
+Auto-extracted signal s_apb_pwdata from can_apb_tb.vhd
+- Offset: `0x1cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_apb_tb_s_apb_pwrite
+Auto-extracted signal s_apb_pwrite from can_apb_tb.vhd
+- Offset: `0x1d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_clr_rx_ctr
+Auto-extracted signal drv_clr_rx_ctr from can_core.vhd
+- Offset: `0x1d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_clr_tx_ctr
+Auto-extracted signal drv_clr_tx_ctr from can_core.vhd
+- Offset: `0x1d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_bus_mon_ena
+Auto-extracted signal drv_bus_mon_ena from can_core.vhd
+- Offset: `0x1dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_drv_ena
+Auto-extracted signal drv_ena from can_core.vhd
+- Offset: `0x1e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_ident_i
+Auto-extracted signal rec_ident_i from can_core.vhd
+- Offset: `0x1e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_dlc_i
+Auto-extracted signal rec_dlc_i from can_core.vhd
+- Offset: `0x1e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_ident_type_i
+Auto-extracted signal rec_ident_type_i from can_core.vhd
+- Offset: `0x1ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from can_core.vhd
+- Offset: `0x1f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from can_core.vhd
+- Offset: `0x1f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_brs_i
+Auto-extracted signal rec_brs_i from can_core.vhd
+- Offset: `0x1f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_esi_i
+Auto-extracted signal rec_esi_i from can_core.vhd
+- Offset: `0x1fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_alc
+Auto-extracted signal alc from can_core.vhd
+- Offset: `0x200`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_erc_capture
+Auto-extracted signal erc_capture from can_core.vhd
+- Offset: `0x204`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_transmitter
+Auto-extracted signal is_transmitter from can_core.vhd
+- Offset: `0x208`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_receiver
+Auto-extracted signal is_receiver from can_core.vhd
+- Offset: `0x20c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_idle
+Auto-extracted signal is_idle from can_core.vhd
+- Offset: `0x210`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from can_core.vhd
+- Offset: `0x214`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_transmitter
+Auto-extracted signal set_transmitter from can_core.vhd
+- Offset: `0x218`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_receiver
+Auto-extracted signal set_receiver from can_core.vhd
+- Offset: `0x21c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_idle
+Auto-extracted signal set_idle from can_core.vhd
+- Offset: `0x220`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_active
+Auto-extracted signal is_err_active from can_core.vhd
+- Offset: `0x224`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_passive
+Auto-extracted signal is_err_passive from can_core.vhd
+- Offset: `0x228`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_bus_off_i
+Auto-extracted signal is_bus_off_i from can_core.vhd
+- Offset: `0x22c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_detected_i
+Auto-extracted signal err_detected_i from can_core.vhd
+- Offset: `0x230`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_primary_err
+Auto-extracted signal primary_err from can_core.vhd
+- Offset: `0x234`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_act_err_ovr_flag
+Auto-extracted signal act_err_ovr_flag from can_core.vhd
+- Offset: `0x238`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_delim_late
+Auto-extracted signal err_delim_late from can_core.vhd
+- Offset: `0x23c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_set_err_active
+Auto-extracted signal set_err_active from can_core.vhd
+- Offset: `0x240`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_ctrs_unchanged
+Auto-extracted signal err_ctrs_unchanged from can_core.vhd
+- Offset: `0x244`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_enable
+Auto-extracted signal stuff_enable from can_core.vhd
+- Offset: `0x248`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_destuff_enable
+Auto-extracted signal destuff_enable from can_core.vhd
+- Offset: `0x24c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_fixed_stuff
+Auto-extracted signal fixed_stuff from can_core.vhd
+- Offset: `0x250`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_frame_no_sof
+Auto-extracted signal tx_frame_no_sof from can_core.vhd
+- Offset: `0x254`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_length
+Auto-extracted signal stuff_length from can_core.vhd
+- Offset: `0x258`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_dst_ctr
+Auto-extracted signal dst_ctr from can_core.vhd
+- Offset: `0x25c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_ctr
+Auto-extracted signal bst_ctr from can_core.vhd
+- Offset: `0x260`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_stuff_err
+Auto-extracted signal stuff_err from can_core.vhd
+- Offset: `0x264`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_enable
+Auto-extracted signal crc_enable from can_core.vhd
+- Offset: `0x268`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_spec_enable
+Auto-extracted signal crc_spec_enable from can_core.vhd
+- Offset: `0x26c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_calc_from_rx
+Auto-extracted signal crc_calc_from_rx from can_core.vhd
+- Offset: `0x270`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_15
+Auto-extracted signal crc_15 from can_core.vhd
+- Offset: `0x274`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_17
+Auto-extracted signal crc_17 from can_core.vhd
+- Offset: `0x278`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_21
+Auto-extracted signal crc_21 from can_core.vhd
+- Offset: `0x27c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sp_control_i
+Auto-extracted signal sp_control_i from can_core.vhd
+- Offset: `0x280`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sp_control_q
+Auto-extracted signal sp_control_q from can_core.vhd
+- Offset: `0x284`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sync_control_i
+Auto-extracted signal sync_control_i from can_core.vhd
+- Offset: `0x288`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_ssp_reset_i
+Auto-extracted signal ssp_reset_i from can_core.vhd
+- Offset: `0x28c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tran_delay_meas_i
+Auto-extracted signal tran_delay_meas_i from can_core.vhd
+- Offset: `0x290`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tran_valid_i
+Auto-extracted signal tran_valid_i from can_core.vhd
+- Offset: `0x294`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rec_valid_i
+Auto-extracted signal rec_valid_i from can_core.vhd
+- Offset: `0x298`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_br_shifted_i
+Auto-extracted signal br_shifted_i from can_core.vhd
+- Offset: `0x29c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_fcs_changed_i
+Auto-extracted signal fcs_changed_i from can_core.vhd
+- Offset: `0x2a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_err_warning_limit_i
+Auto-extracted signal err_warning_limit_i from can_core.vhd
+- Offset: `0x2a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_err_ctr
+Auto-extracted signal tx_err_ctr from can_core.vhd
+- Offset: `0x2a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rx_err_ctr
+Auto-extracted signal rx_err_ctr from can_core.vhd
+- Offset: `0x2ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_norm_err_ctr
+Auto-extracted signal norm_err_ctr from can_core.vhd
+- Offset: `0x2b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_data_err_ctr
+Auto-extracted signal data_err_ctr from can_core.vhd
+- Offset: `0x2b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_tx_trigger
+Auto-extracted signal pc_tx_trigger from can_core.vhd
+- Offset: `0x2b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_rx_trigger
+Auto-extracted signal pc_rx_trigger from can_core.vhd
+- Offset: `0x2bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_tx_data_nbs
+Auto-extracted signal pc_tx_data_nbs from can_core.vhd
+- Offset: `0x2c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_pc_rx_data_nbs
+Auto-extracted signal pc_rx_data_nbs from can_core.vhd
+- Offset: `0x2c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_tx_wbs
+Auto-extracted signal crc_data_tx_wbs from can_core.vhd
+- Offset: `0x2c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_tx_nbs
+Auto-extracted signal crc_data_tx_nbs from can_core.vhd
+- Offset: `0x2cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_rx_wbs
+Auto-extracted signal crc_data_rx_wbs from can_core.vhd
+- Offset: `0x2d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_data_rx_nbs
+Auto-extracted signal crc_data_rx_nbs from can_core.vhd
+- Offset: `0x2d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_tx_wbs
+Auto-extracted signal crc_trig_tx_wbs from can_core.vhd
+- Offset: `0x2d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_tx_nbs
+Auto-extracted signal crc_trig_tx_nbs from can_core.vhd
+- Offset: `0x2dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_rx_wbs
+Auto-extracted signal crc_trig_rx_wbs from can_core.vhd
+- Offset: `0x2e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_trig_rx_nbs
+Auto-extracted signal crc_trig_rx_nbs from can_core.vhd
+- Offset: `0x2e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_data_in
+Auto-extracted signal bst_data_in from can_core.vhd
+- Offset: `0x2e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_data_out
+Auto-extracted signal bst_data_out from can_core.vhd
+- Offset: `0x2ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bst_trigger
+Auto-extracted signal bst_trigger from can_core.vhd
+- Offset: `0x2f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_data_halt
+Auto-extracted signal data_halt from can_core.vhd
+- Offset: `0x2f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_data_in
+Auto-extracted signal bds_data_in from can_core.vhd
+- Offset: `0x2f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_data_out
+Auto-extracted signal bds_data_out from can_core.vhd
+- Offset: `0x2fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bds_trigger
+Auto-extracted signal bds_trigger from can_core.vhd
+- Offset: `0x300`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_destuffed
+Auto-extracted signal destuffed from can_core.vhd
+- Offset: `0x304`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_ctr
+Auto-extracted signal tx_ctr from can_core.vhd
+- Offset: `0x308`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_rx_ctr
+Auto-extracted signal rx_ctr from can_core.vhd
+- Offset: `0x30c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_tx_data_wbs_i
+Auto-extracted signal tx_data_wbs_i from can_core.vhd
+- Offset: `0x310`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_lpb_dominant
+Auto-extracted signal lpb_dominant from can_core.vhd
+- Offset: `0x314`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_form_err
+Auto-extracted signal form_err from can_core.vhd
+- Offset: `0x318`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_ack_err
+Auto-extracted signal ack_err from can_core.vhd
+- Offset: `0x31c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_crc_err
+Auto-extracted signal crc_err from can_core.vhd
+- Offset: `0x320`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_arbitration
+Auto-extracted signal is_arbitration from can_core.vhd
+- Offset: `0x324`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_control
+Auto-extracted signal is_control from can_core.vhd
+- Offset: `0x328`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_data
+Auto-extracted signal is_data from can_core.vhd
+- Offset: `0x32c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_stuff_count
+Auto-extracted signal is_stuff_count from can_core.vhd
+- Offset: `0x330`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_crc
+Auto-extracted signal is_crc from can_core.vhd
+- Offset: `0x334`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_crc_delim
+Auto-extracted signal is_crc_delim from can_core.vhd
+- Offset: `0x338`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_ack_field
+Auto-extracted signal is_ack_field from can_core.vhd
+- Offset: `0x33c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_ack_delim
+Auto-extracted signal is_ack_delim from can_core.vhd
+- Offset: `0x340`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_eof
+Auto-extracted signal is_eof from can_core.vhd
+- Offset: `0x344`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_err_frm
+Auto-extracted signal is_err_frm from can_core.vhd
+- Offset: `0x348`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_intermission
+Auto-extracted signal is_intermission from can_core.vhd
+- Offset: `0x34c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_suspend
+Auto-extracted signal is_suspend from can_core.vhd
+- Offset: `0x350`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_overload_i
+Auto-extracted signal is_overload_i from can_core.vhd
+- Offset: `0x354`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_sof
+Auto-extracted signal is_sof from can_core.vhd
+- Offset: `0x358`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_sof_pulse_i
+Auto-extracted signal sof_pulse_i from can_core.vhd
+- Offset: `0x35c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_load_init_vect
+Auto-extracted signal load_init_vect from can_core.vhd
+- Offset: `0x360`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_retr_ctr_i
+Auto-extracted signal retr_ctr_i from can_core.vhd
+- Offset: `0x364`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_decrement_rec
+Auto-extracted signal decrement_rec from can_core.vhd
+- Offset: `0x368`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_bit_err_after_ack_err
+Auto-extracted signal bit_err_after_ack_err from can_core.vhd
+- Offset: `0x36c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_core_is_pexs
+Auto-extracted signal is_pexs from can_core.vhd
+- Offset: `0x370`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_drv_fd_type
+Auto-extracted signal drv_fd_type from can_crc.vhd
+- Offset: `0x374`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_15
+Auto-extracted signal init_vect_15 from can_crc.vhd
+- Offset: `0x378`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_17
+Auto-extracted signal init_vect_17 from can_crc.vhd
+- Offset: `0x37c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_init_vect_21
+Auto-extracted signal init_vect_21 from can_crc.vhd
+- Offset: `0x380`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_17_21_data_in
+Auto-extracted signal crc_17_21_data_in from can_crc.vhd
+- Offset: `0x384`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_17_21_trigger
+Auto-extracted signal crc_17_21_trigger from can_crc.vhd
+- Offset: `0x388`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_15_data_in
+Auto-extracted signal crc_15_data_in from can_crc.vhd
+- Offset: `0x38c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_15_trigger
+Auto-extracted signal crc_15_trigger from can_crc.vhd
+- Offset: `0x390`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_ena_15
+Auto-extracted signal crc_ena_15 from can_crc.vhd
+- Offset: `0x394`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_crc_crc_ena_17_21
+Auto-extracted signal crc_ena_17_21 from can_crc.vhd
+- Offset: `0x398`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_data_in
+Auto-extracted signal ctu_can_data_in from can_top_ahb.vhd
+- Offset: `0x39c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_data_out
+Auto-extracted signal ctu_can_data_out from can_top_ahb.vhd
+- Offset: `0x3a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_adress
+Auto-extracted signal ctu_can_adress from can_top_ahb.vhd
+- Offset: `0x3a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_scs
+Auto-extracted signal ctu_can_scs from can_top_ahb.vhd
+- Offset: `0x3a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_srd
+Auto-extracted signal ctu_can_srd from can_top_ahb.vhd
+- Offset: `0x3ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_swr
+Auto-extracted signal ctu_can_swr from can_top_ahb.vhd
+- Offset: `0x3b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_ctu_can_sbe
+Auto-extracted signal ctu_can_sbe from can_top_ahb.vhd
+- Offset: `0x3b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_ahb_res_n_out_i
+Auto-extracted signal res_n_out_i from can_top_ahb.vhd
+- Offset: `0x3b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_data_in
+Auto-extracted signal reg_data_in from can_top_apb.vhd
+- Offset: `0x3bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_data_out
+Auto-extracted signal reg_data_out from can_top_apb.vhd
+- Offset: `0x3c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_addr
+Auto-extracted signal reg_addr from can_top_apb.vhd
+- Offset: `0x3c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_be
+Auto-extracted signal reg_be from can_top_apb.vhd
+- Offset: `0x3c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_rden
+Auto-extracted signal reg_rden from can_top_apb.vhd
+- Offset: `0x3cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_apb_reg_wren
+Auto-extracted signal reg_wren from can_top_apb.vhd
+- Offset: `0x3d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_drv_bus
+Auto-extracted signal drv_bus from can_top_level.vhd
+- Offset: `0x3d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_stat_bus
+Auto-extracted signal stat_bus from can_top_level.vhd
+- Offset: `0x3d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_n_sync
+Auto-extracted signal res_n_sync from can_top_level.vhd
+- Offset: `0x3dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_core_n
+Auto-extracted signal res_core_n from can_top_level.vhd
+- Offset: `0x3e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_res_soft_n
+Auto-extracted signal res_soft_n from can_top_level.vhd
+- Offset: `0x3e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sp_control
+Auto-extracted signal sp_control from can_top_level.vhd
+- Offset: `0x3e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_buf_size
+Auto-extracted signal rx_buf_size from can_top_level.vhd
+- Offset: `0x3ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_full
+Auto-extracted signal rx_full from can_top_level.vhd
+- Offset: `0x3f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_empty
+Auto-extracted signal rx_empty from can_top_level.vhd
+- Offset: `0x3f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_frame_count
+Auto-extracted signal rx_frame_count from can_top_level.vhd
+- Offset: `0x3f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_mem_free
+Auto-extracted signal rx_mem_free from can_top_level.vhd
+- Offset: `0x3fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_read_pointer
+Auto-extracted signal rx_read_pointer from can_top_level.vhd
+- Offset: `0x400`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_write_pointer
+Auto-extracted signal rx_write_pointer from can_top_level.vhd
+- Offset: `0x404`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_data_overrun
+Auto-extracted signal rx_data_overrun from can_top_level.vhd
+- Offset: `0x408`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_read_buff
+Auto-extracted signal rx_read_buff from can_top_level.vhd
+- Offset: `0x40c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_mof
+Auto-extracted signal rx_mof from can_top_level.vhd
+- Offset: `0x410`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_data
+Auto-extracted signal txtb_port_a_data from can_top_level.vhd
+- Offset: `0x414`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_address
+Auto-extracted signal txtb_port_a_address from can_top_level.vhd
+- Offset: `0x418`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_cs
+Auto-extracted signal txtb_port_a_cs from can_top_level.vhd
+- Offset: `0x41c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_a_be
+Auto-extracted signal txtb_port_a_be from can_top_level.vhd
+- Offset: `0x420`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_sw_cmd_index
+Auto-extracted signal txtb_sw_cmd_index from can_top_level.vhd
+- Offset: `0x424`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txt_buf_failed_bof
+Auto-extracted signal txt_buf_failed_bof from can_top_level.vhd
+- Offset: `0x428`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_vector
+Auto-extracted signal int_vector from can_top_level.vhd
+- Offset: `0x42c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_ena
+Auto-extracted signal int_ena from can_top_level.vhd
+- Offset: `0x430`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_int_mask
+Auto-extracted signal int_mask from can_top_level.vhd
+- Offset: `0x434`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_ident
+Auto-extracted signal rec_ident from can_top_level.vhd
+- Offset: `0x438`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_dlc
+Auto-extracted signal rec_dlc from can_top_level.vhd
+- Offset: `0x43c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_ident_type
+Auto-extracted signal rec_ident_type from can_top_level.vhd
+- Offset: `0x440`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_frame_type
+Auto-extracted signal rec_frame_type from can_top_level.vhd
+- Offset: `0x444`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_is_rtr
+Auto-extracted signal rec_is_rtr from can_top_level.vhd
+- Offset: `0x448`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_brs
+Auto-extracted signal rec_brs from can_top_level.vhd
+- Offset: `0x44c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_esi
+Auto-extracted signal rec_esi from can_top_level.vhd
+- Offset: `0x450`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data_word
+Auto-extracted signal store_data_word from can_top_level.vhd
+- Offset: `0x454`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sof_pulse
+Auto-extracted signal sof_pulse from can_top_level.vhd
+- Offset: `0x458`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_metadata
+Auto-extracted signal store_metadata from can_top_level.vhd
+- Offset: `0x45c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data
+Auto-extracted signal store_data from can_top_level.vhd
+- Offset: `0x460`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_valid
+Auto-extracted signal rec_valid from can_top_level.vhd
+- Offset: `0x464`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_abort
+Auto-extracted signal rec_abort from can_top_level.vhd
+- Offset: `0x468`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_metadata_f
+Auto-extracted signal store_metadata_f from can_top_level.vhd
+- Offset: `0x46c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_store_data_f
+Auto-extracted signal store_data_f from can_top_level.vhd
+- Offset: `0x470`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_valid_f
+Auto-extracted signal rec_valid_f from can_top_level.vhd
+- Offset: `0x474`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rec_abort_f
+Auto-extracted signal rec_abort_f from can_top_level.vhd
+- Offset: `0x478`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_hw_cmd_int
+Auto-extracted signal txtb_hw_cmd_int from can_top_level.vhd
+- Offset: `0x47c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_is_bus_off
+Auto-extracted signal is_bus_off from can_top_level.vhd
+- Offset: `0x480`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_available
+Auto-extracted signal txtb_available from can_top_level.vhd
+- Offset: `0x484`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_port_b_clk_en
+Auto-extracted signal txtb_port_b_clk_en from can_top_level.vhd
+- Offset: `0x488`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_dlc
+Auto-extracted signal tran_dlc from can_top_level.vhd
+- Offset: `0x48c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_is_rtr
+Auto-extracted signal tran_is_rtr from can_top_level.vhd
+- Offset: `0x490`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_ident_type
+Auto-extracted signal tran_ident_type from can_top_level.vhd
+- Offset: `0x494`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_frame_type
+Auto-extracted signal tran_frame_type from can_top_level.vhd
+- Offset: `0x498`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_brs
+Auto-extracted signal tran_brs from can_top_level.vhd
+- Offset: `0x49c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_identifier
+Auto-extracted signal tran_identifier from can_top_level.vhd
+- Offset: `0x4a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_word
+Auto-extracted signal tran_word from can_top_level.vhd
+- Offset: `0x4a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_frame_valid
+Auto-extracted signal tran_frame_valid from can_top_level.vhd
+- Offset: `0x4a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_changed
+Auto-extracted signal txtb_changed from can_top_level.vhd
+- Offset: `0x4ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_txtb_clk_en
+Auto-extracted signal txtb_clk_en from can_top_level.vhd
+- Offset: `0x4b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_err_detected
+Auto-extracted signal err_detected from can_top_level.vhd
+- Offset: `0x4b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_fcs_changed
+Auto-extracted signal fcs_changed from can_top_level.vhd
+- Offset: `0x4b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_err_warning_limit
+Auto-extracted signal err_warning_limit from can_top_level.vhd
+- Offset: `0x4bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_arbitration_lost
+Auto-extracted signal arbitration_lost from can_top_level.vhd
+- Offset: `0x4c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_valid
+Auto-extracted signal tran_valid from can_top_level.vhd
+- Offset: `0x4c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_br_shifted
+Auto-extracted signal br_shifted from can_top_level.vhd
+- Offset: `0x4c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_is_overload
+Auto-extracted signal is_overload from can_top_level.vhd
+- Offset: `0x4cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_triggers
+Auto-extracted signal rx_triggers from can_top_level.vhd
+- Offset: `0x4d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tx_trigger
+Auto-extracted signal tx_trigger from can_top_level.vhd
+- Offset: `0x4d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sync_control
+Auto-extracted signal sync_control from can_top_level.vhd
+- Offset: `0x4d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_no_pos_resync
+Auto-extracted signal no_pos_resync from can_top_level.vhd
+- Offset: `0x4dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_nbt_ctrs_en
+Auto-extracted signal nbt_ctrs_en from can_top_level.vhd
+- Offset: `0x4e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_dbt_ctrs_en
+Auto-extracted signal dbt_ctrs_en from can_top_level.vhd
+- Offset: `0x4e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_trv_delay
+Auto-extracted signal trv_delay from can_top_level.vhd
+- Offset: `0x4e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_rx_data_wbs
+Auto-extracted signal rx_data_wbs from can_top_level.vhd
+- Offset: `0x4ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tx_data_wbs
+Auto-extracted signal tx_data_wbs from can_top_level.vhd
+- Offset: `0x4f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_ssp_reset
+Auto-extracted signal ssp_reset from can_top_level.vhd
+- Offset: `0x4f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tran_delay_meas
+Auto-extracted signal tran_delay_meas from can_top_level.vhd
+- Offset: `0x4f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_bit_err
+Auto-extracted signal bit_err from can_top_level.vhd
+- Offset: `0x4fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sample_sec
+Auto-extracted signal sample_sec from can_top_level.vhd
+- Offset: `0x500`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_btmc_reset
+Auto-extracted signal btmc_reset from can_top_level.vhd
+- Offset: `0x504`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_dbt_measure_start
+Auto-extracted signal dbt_measure_start from can_top_level.vhd
+- Offset: `0x508`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_gen_first_ssp
+Auto-extracted signal gen_first_ssp from can_top_level.vhd
+- Offset: `0x50c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_sync_edge
+Auto-extracted signal sync_edge from can_top_level.vhd
+- Offset: `0x510`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tq_edge
+Auto-extracted signal tq_edge from can_top_level.vhd
+- Offset: `0x514`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## can_top_level_tst_rdata_rx_buf
+Auto-extracted signal tst_rdata_rx_buf from can_top_level.vhd
+- Offset: `0x518`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## clk_gate_clk_en_q
+Auto-extracted signal clk_en_q from clk_gate.vhd
+- Offset: `0x51c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_counter_ctrl_ctr_ce
+Auto-extracted signal ctrl_ctr_ce from control_counter.vhd
+- Offset: `0x520`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_counter_compl_ctr_ce
+Auto-extracted signal compl_ctr_ce from control_counter.vhd
+- Offset: `0x524`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_reg_sel
+Auto-extracted signal reg_sel from control_registers_reg_map.vhd
+- Offset: `0x528`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_data_mux_in
+Auto-extracted signal read_data_mux_in from control_registers_reg_map.vhd
+- Offset: `0x52c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_data_mask_n
+Auto-extracted signal read_data_mask_n from control_registers_reg_map.vhd
+- Offset: `0x530`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## control_registers_reg_map_read_mux_ena
+Auto-extracted signal read_mux_ena from control_registers_reg_map.vhd
+- Offset: `0x534`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_q
+Auto-extracted signal crc_q from crc_calc.vhd
+- Offset: `0x538`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_nxt
+Auto-extracted signal crc_nxt from crc_calc.vhd
+- Offset: `0x53c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_shift
+Auto-extracted signal crc_shift from crc_calc.vhd
+- Offset: `0x540`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_shift_n_xor
+Auto-extracted signal crc_shift_n_xor from crc_calc.vhd
+- Offset: `0x544`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_d
+Auto-extracted signal crc_d from crc_calc.vhd
+- Offset: `0x548`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## crc_calc_crc_ce
+Auto-extracted signal crc_ce from crc_calc.vhd
+- Offset: `0x54c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_data_prev
+Auto-extracted signal rx_data_prev from data_edge_detector.vhd
+- Offset: `0x550`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_tx_data_prev
+Auto-extracted signal tx_data_prev from data_edge_detector.vhd
+- Offset: `0x554`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_data_sync_prev
+Auto-extracted signal rx_data_sync_prev from data_edge_detector.vhd
+- Offset: `0x558`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_rx_edge_i
+Auto-extracted signal rx_edge_i from data_edge_detector.vhd
+- Offset: `0x55c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_edge_detector_tx_edge_i
+Auto-extracted signal tx_edge_i from data_edge_detector.vhd
+- Offset: `0x560`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_sel_data
+Auto-extracted signal sel_data from data_mux.vhd
+- Offset: `0x564`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_saturated_data
+Auto-extracted signal saturated_data from data_mux.vhd
+- Offset: `0x568`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## data_mux_masked_data
+Auto-extracted signal masked_data from data_mux.vhd
+- Offset: `0x56c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_8_to_64
+Auto-extracted signal data_len_8_to_64 from dlc_decoder.vhd
+- Offset: `0x570`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_can_2_0
+Auto-extracted signal data_len_can_2_0 from dlc_decoder.vhd
+- Offset: `0x574`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## dlc_decoder_data_len_can_fd
+Auto-extracted signal data_len_can_fd from dlc_decoder.vhd
+- Offset: `0x578`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## endian_swapper_swapped
+Auto-extracted signal swapped from endian_swapper.vhd
+- Offset: `0x57c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_tx_err_ctr_ce
+Auto-extracted signal tx_err_ctr_ce from err_counters.vhd
+- Offset: `0x580`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_rx_err_ctr_ce
+Auto-extracted signal rx_err_ctr_ce from err_counters.vhd
+- Offset: `0x584`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_modif_tx_ctr
+Auto-extracted signal modif_tx_ctr from err_counters.vhd
+- Offset: `0x588`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_modif_rx_ctr
+Auto-extracted signal modif_rx_ctr from err_counters.vhd
+- Offset: `0x58c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_nom_err_ctr_ce
+Auto-extracted signal nom_err_ctr_ce from err_counters.vhd
+- Offset: `0x590`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_data_err_ctr_ce
+Auto-extracted signal data_err_ctr_ce from err_counters.vhd
+- Offset: `0x594`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_d
+Auto-extracted signal res_err_ctrs_d from err_counters.vhd
+- Offset: `0x598`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_q
+Auto-extracted signal res_err_ctrs_q from err_counters.vhd
+- Offset: `0x59c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_counters_res_err_ctrs_q_scan
+Auto-extracted signal res_err_ctrs_q_scan from err_counters.vhd
+- Offset: `0x5a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_frm_req_i
+Auto-extracted signal err_frm_req_i from err_detector.vhd
+- Offset: `0x5a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_type_d
+Auto-extracted signal err_type_d from err_detector.vhd
+- Offset: `0x5a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_type_q
+Auto-extracted signal err_type_q from err_detector.vhd
+- Offset: `0x5ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_err_pos_q
+Auto-extracted signal err_pos_q from err_detector.vhd
+- Offset: `0x5b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_form_err_i
+Auto-extracted signal form_err_i from err_detector.vhd
+- Offset: `0x5b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_c
+Auto-extracted signal crc_match_c from err_detector.vhd
+- Offset: `0x5b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_d
+Auto-extracted signal crc_match_d from err_detector.vhd
+- Offset: `0x5bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_match_q
+Auto-extracted signal crc_match_q from err_detector.vhd
+- Offset: `0x5c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_dst_ctr_grey
+Auto-extracted signal dst_ctr_grey from err_detector.vhd
+- Offset: `0x5c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_dst_parity
+Auto-extracted signal dst_parity from err_detector.vhd
+- Offset: `0x5c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_stuff_count_check
+Auto-extracted signal stuff_count_check from err_detector.vhd
+- Offset: `0x5cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_15_ok
+Auto-extracted signal crc_15_ok from err_detector.vhd
+- Offset: `0x5d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_17_ok
+Auto-extracted signal crc_17_ok from err_detector.vhd
+- Offset: `0x5d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_crc_21_ok
+Auto-extracted signal crc_21_ok from err_detector.vhd
+- Offset: `0x5d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_stuff_count_ok
+Auto-extracted signal stuff_count_ok from err_detector.vhd
+- Offset: `0x5dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_15
+Auto-extracted signal rx_crc_15 from err_detector.vhd
+- Offset: `0x5e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_17
+Auto-extracted signal rx_crc_17 from err_detector.vhd
+- Offset: `0x5e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## err_detector_rx_crc_21
+Auto-extracted signal rx_crc_21 from err_detector.vhd
+- Offset: `0x5e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ewl
+Auto-extracted signal drv_ewl from fault_confinement.vhd
+- Offset: `0x5ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_erp
+Auto-extracted signal drv_erp from fault_confinement.vhd
+- Offset: `0x5f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ctr_val
+Auto-extracted signal drv_ctr_val from fault_confinement.vhd
+- Offset: `0x5f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ctr_sel
+Auto-extracted signal drv_ctr_sel from fault_confinement.vhd
+- Offset: `0x5f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_ena
+Auto-extracted signal drv_ena from fault_confinement.vhd
+- Offset: `0x5fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_tx_err_ctr_i
+Auto-extracted signal tx_err_ctr_i from fault_confinement.vhd
+- Offset: `0x600`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rx_err_ctr_i
+Auto-extracted signal rx_err_ctr_i from fault_confinement.vhd
+- Offset: `0x604`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_inc_one
+Auto-extracted signal inc_one from fault_confinement.vhd
+- Offset: `0x608`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_inc_eight
+Auto-extracted signal inc_eight from fault_confinement.vhd
+- Offset: `0x60c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_dec_one
+Auto-extracted signal dec_one from fault_confinement.vhd
+- Offset: `0x610`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_drv_rom_ena
+Auto-extracted signal drv_rom_ena from fault_confinement.vhd
+- Offset: `0x614`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_erp
+Auto-extracted signal tx_err_ctr_mt_erp from fault_confinement_fsm.vhd
+- Offset: `0x618`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_rx_err_ctr_mt_erp
+Auto-extracted signal rx_err_ctr_mt_erp from fault_confinement_fsm.vhd
+- Offset: `0x61c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_ewl
+Auto-extracted signal tx_err_ctr_mt_ewl from fault_confinement_fsm.vhd
+- Offset: `0x620`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_rx_err_ctr_mt_ewl
+Auto-extracted signal rx_err_ctr_mt_ewl from fault_confinement_fsm.vhd
+- Offset: `0x624`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_tx_err_ctr_mt_255
+Auto-extracted signal tx_err_ctr_mt_255 from fault_confinement_fsm.vhd
+- Offset: `0x628`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_err_warning_limit_d
+Auto-extracted signal err_warning_limit_d from fault_confinement_fsm.vhd
+- Offset: `0x62c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_err_warning_limit_q
+Auto-extracted signal err_warning_limit_q from fault_confinement_fsm.vhd
+- Offset: `0x630`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_fc_fsm_res_d
+Auto-extracted signal fc_fsm_res_d from fault_confinement_fsm.vhd
+- Offset: `0x634`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_fsm_fc_fsm_res_q
+Auto-extracted signal fc_fsm_res_q from fault_confinement_fsm.vhd
+- Offset: `0x638`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rules_inc_one_i
+Auto-extracted signal inc_one_i from fault_confinement_rules.vhd
+- Offset: `0x63c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## fault_confinement_rules_inc_eight_i
+Auto-extracted signal inc_eight_i from fault_confinement_rules.vhd
+- Offset: `0x640`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_mask
+Auto-extracted signal drv_filter_A_mask from frame_filters.vhd
+- Offset: `0x644`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_ctrl
+Auto-extracted signal drv_filter_A_ctrl from frame_filters.vhd
+- Offset: `0x648`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_A_bits
+Auto-extracted signal drv_filter_A_bits from frame_filters.vhd
+- Offset: `0x64c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_A_valid
+Auto-extracted signal int_filter_A_valid from frame_filters.vhd
+- Offset: `0x650`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_mask
+Auto-extracted signal drv_filter_B_mask from frame_filters.vhd
+- Offset: `0x654`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_ctrl
+Auto-extracted signal drv_filter_B_ctrl from frame_filters.vhd
+- Offset: `0x658`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_B_bits
+Auto-extracted signal drv_filter_B_bits from frame_filters.vhd
+- Offset: `0x65c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_B_valid
+Auto-extracted signal int_filter_B_valid from frame_filters.vhd
+- Offset: `0x660`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_mask
+Auto-extracted signal drv_filter_C_mask from frame_filters.vhd
+- Offset: `0x664`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_ctrl
+Auto-extracted signal drv_filter_C_ctrl from frame_filters.vhd
+- Offset: `0x668`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_C_bits
+Auto-extracted signal drv_filter_C_bits from frame_filters.vhd
+- Offset: `0x66c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_C_valid
+Auto-extracted signal int_filter_C_valid from frame_filters.vhd
+- Offset: `0x670`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_ctrl
+Auto-extracted signal drv_filter_ran_ctrl from frame_filters.vhd
+- Offset: `0x674`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_lo_th
+Auto-extracted signal drv_filter_ran_lo_th from frame_filters.vhd
+- Offset: `0x678`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filter_ran_hi_th
+Auto-extracted signal drv_filter_ran_hi_th from frame_filters.vhd
+- Offset: `0x67c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_filter_ran_valid
+Auto-extracted signal int_filter_ran_valid from frame_filters.vhd
+- Offset: `0x680`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_filters_ena
+Auto-extracted signal drv_filters_ena from frame_filters.vhd
+- Offset: `0x684`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_data_type
+Auto-extracted signal int_data_type from frame_filters.vhd
+- Offset: `0x688`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_int_data_ctrl
+Auto-extracted signal int_data_ctrl from frame_filters.vhd
+- Offset: `0x68c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_A_enable
+Auto-extracted signal filter_A_enable from frame_filters.vhd
+- Offset: `0x690`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_B_enable
+Auto-extracted signal filter_B_enable from frame_filters.vhd
+- Offset: `0x694`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_C_enable
+Auto-extracted signal filter_C_enable from frame_filters.vhd
+- Offset: `0x698`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_range_enable
+Auto-extracted signal filter_range_enable from frame_filters.vhd
+- Offset: `0x69c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_filter_result
+Auto-extracted signal filter_result from frame_filters.vhd
+- Offset: `0x6a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_ident_valid_d
+Auto-extracted signal ident_valid_d from frame_filters.vhd
+- Offset: `0x6a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_ident_valid_q
+Auto-extracted signal ident_valid_q from frame_filters.vhd
+- Offset: `0x6a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drv_drop_remote_frames
+Auto-extracted signal drv_drop_remote_frames from frame_filters.vhd
+- Offset: `0x6ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## frame_filters_drop_rtr_frame
+Auto-extracted signal drop_rtr_frame from frame_filters.vhd
+- Offset: `0x6b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## inf_ram_wrapper_int_read_data
+Auto-extracted signal int_read_data from inf_ram_wrapper.vhd
+- Offset: `0x6b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## inf_ram_wrapper_byte_we
+Auto-extracted signal byte_we from inf_ram_wrapper.vhd
+- Offset: `0x6b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_vect_clr
+Auto-extracted signal drv_int_vect_clr from int_manager.vhd
+- Offset: `0x6bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_ena_set
+Auto-extracted signal drv_int_ena_set from int_manager.vhd
+- Offset: `0x6c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_ena_clr
+Auto-extracted signal drv_int_ena_clr from int_manager.vhd
+- Offset: `0x6c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_mask_set
+Auto-extracted signal drv_int_mask_set from int_manager.vhd
+- Offset: `0x6c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_drv_int_mask_clr
+Auto-extracted signal drv_int_mask_clr from int_manager.vhd
+- Offset: `0x6cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_ena_i
+Auto-extracted signal int_ena_i from int_manager.vhd
+- Offset: `0x6d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_mask_i
+Auto-extracted signal int_mask_i from int_manager.vhd
+- Offset: `0x6d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_vect_i
+Auto-extracted signal int_vect_i from int_manager.vhd
+- Offset: `0x6d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_input_active
+Auto-extracted signal int_input_active from int_manager.vhd
+- Offset: `0x6dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_manager_int_i
+Auto-extracted signal int_i from int_manager.vhd
+- Offset: `0x6e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_i
+Auto-extracted signal int_mask_i from int_module.vhd
+- Offset: `0x6e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_ena_i
+Auto-extracted signal int_ena_i from int_module.vhd
+- Offset: `0x6e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_load
+Auto-extracted signal int_mask_load from int_module.vhd
+- Offset: `0x6ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## int_module_int_mask_next
+Auto-extracted signal int_mask_next from int_module.vhd
+- Offset: `0x6f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_reg_value_r
+Auto-extracted signal reg_value_r from memory_reg.vhd
+- Offset: `0x6f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_wr_select
+Auto-extracted signal wr_select from memory_reg.vhd
+- Offset: `0x6f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_reg_wr_select_expanded
+Auto-extracted signal wr_select_expanded from memory_reg.vhd
+- Offset: `0x6fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_status_comb
+Auto-extracted signal status_comb from memory_registers.vhd
+- Offset: `0x700`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_can_core_cs
+Auto-extracted signal can_core_cs from memory_registers.vhd
+- Offset: `0x704`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_cs
+Auto-extracted signal control_registers_cs from memory_registers.vhd
+- Offset: `0x708`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_cs_reg
+Auto-extracted signal control_registers_cs_reg from memory_registers.vhd
+- Offset: `0x70c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_cs
+Auto-extracted signal test_registers_cs from memory_registers.vhd
+- Offset: `0x710`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_cs_reg
+Auto-extracted signal test_registers_cs_reg from memory_registers.vhd
+- Offset: `0x714`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_registers_rdata
+Auto-extracted signal control_registers_rdata from memory_registers.vhd
+- Offset: `0x718`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_registers_rdata
+Auto-extracted signal test_registers_rdata from memory_registers.vhd
+- Offset: `0x71c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_err_active
+Auto-extracted signal is_err_active from memory_registers.vhd
+- Offset: `0x720`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_err_passive
+Auto-extracted signal is_err_passive from memory_registers.vhd
+- Offset: `0x724`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_bus_off
+Auto-extracted signal is_bus_off from memory_registers.vhd
+- Offset: `0x728`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_transmitter
+Auto-extracted signal is_transmitter from memory_registers.vhd
+- Offset: `0x72c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_receiver
+Auto-extracted signal is_receiver from memory_registers.vhd
+- Offset: `0x730`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_is_idle
+Auto-extracted signal is_idle from memory_registers.vhd
+- Offset: `0x734`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_reg_lock_1_active
+Auto-extracted signal reg_lock_1_active from memory_registers.vhd
+- Offset: `0x738`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_reg_lock_2_active
+Auto-extracted signal reg_lock_2_active from memory_registers.vhd
+- Offset: `0x73c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_soft_res_q_n
+Auto-extracted signal soft_res_q_n from memory_registers.vhd
+- Offset: `0x740`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_ewl_padded
+Auto-extracted signal ewl_padded from memory_registers.vhd
+- Offset: `0x744`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_control_regs_clk_en
+Auto-extracted signal control_regs_clk_en from memory_registers.vhd
+- Offset: `0x748`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_test_regs_clk_en
+Auto-extracted signal test_regs_clk_en from memory_registers.vhd
+- Offset: `0x74c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_clk_control_regs
+Auto-extracted signal clk_control_regs from memory_registers.vhd
+- Offset: `0x750`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_clk_test_regs
+Auto-extracted signal clk_test_regs from memory_registers.vhd
+- Offset: `0x754`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_rx_buf_mode
+Auto-extracted signal rx_buf_mode from memory_registers.vhd
+- Offset: `0x758`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_rx_move_cmd
+Auto-extracted signal rx_move_cmd from memory_registers.vhd
+- Offset: `0x75c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## memory_registers_ctr_pres_sel_q
+Auto-extracted signal ctr_pres_sel_q from memory_registers.vhd
+- Offset: `0x760`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## operation_control_drv_ena
+Auto-extracted signal drv_ena from operation_control.vhd
+- Offset: `0x764`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## operation_control_go_to_off
+Auto-extracted signal go_to_off from operation_control.vhd
+- Offset: `0x768`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_drv_ena
+Auto-extracted signal drv_ena from prescaler.vhd
+- Offset: `0x76c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg1_nbt
+Auto-extracted signal tseg1_nbt from prescaler.vhd
+- Offset: `0x770`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg2_nbt
+Auto-extracted signal tseg2_nbt from prescaler.vhd
+- Offset: `0x774`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_brp_nbt
+Auto-extracted signal brp_nbt from prescaler.vhd
+- Offset: `0x778`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_sjw_nbt
+Auto-extracted signal sjw_nbt from prescaler.vhd
+- Offset: `0x77c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg1_dbt
+Auto-extracted signal tseg1_dbt from prescaler.vhd
+- Offset: `0x780`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tseg2_dbt
+Auto-extracted signal tseg2_dbt from prescaler.vhd
+- Offset: `0x784`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_brp_dbt
+Auto-extracted signal brp_dbt from prescaler.vhd
+- Offset: `0x788`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_sjw_dbt
+Auto-extracted signal sjw_dbt from prescaler.vhd
+- Offset: `0x78c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segment_end
+Auto-extracted signal segment_end from prescaler.vhd
+- Offset: `0x790`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_h_sync_valid
+Auto-extracted signal h_sync_valid from prescaler.vhd
+- Offset: `0x794`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_is_tseg1
+Auto-extracted signal is_tseg1 from prescaler.vhd
+- Offset: `0x798`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_is_tseg2
+Auto-extracted signal is_tseg2 from prescaler.vhd
+- Offset: `0x79c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_resync_edge_valid
+Auto-extracted signal resync_edge_valid from prescaler.vhd
+- Offset: `0x7a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_h_sync_edge_valid
+Auto-extracted signal h_sync_edge_valid from prescaler.vhd
+- Offset: `0x7a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segm_counter_nbt
+Auto-extracted signal segm_counter_nbt from prescaler.vhd
+- Offset: `0x7a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_segm_counter_dbt
+Auto-extracted signal segm_counter_dbt from prescaler.vhd
+- Offset: `0x7ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_exit_segm_req_nbt
+Auto-extracted signal exit_segm_req_nbt from prescaler.vhd
+- Offset: `0x7b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_exit_segm_req_dbt
+Auto-extracted signal exit_segm_req_dbt from prescaler.vhd
+- Offset: `0x7b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tq_edge_nbt
+Auto-extracted signal tq_edge_nbt from prescaler.vhd
+- Offset: `0x7b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tq_edge_dbt
+Auto-extracted signal tq_edge_dbt from prescaler.vhd
+- Offset: `0x7bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_rx_trig_req
+Auto-extracted signal rx_trig_req from prescaler.vhd
+- Offset: `0x7c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_tx_trig_req
+Auto-extracted signal tx_trig_req from prescaler.vhd
+- Offset: `0x7c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_start_edge
+Auto-extracted signal start_edge from prescaler.vhd
+- Offset: `0x7c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## prescaler_bt_ctr_clear
+Auto-extracted signal bt_ctr_clear from prescaler.vhd
+- Offset: `0x7cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l0_valid
+Auto-extracted signal l0_valid from priority_decoder.vhd
+- Offset: `0x7d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l1_valid
+Auto-extracted signal l1_valid from priority_decoder.vhd
+- Offset: `0x7d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l1_winner
+Auto-extracted signal l1_winner from priority_decoder.vhd
+- Offset: `0x7d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l2_valid
+Auto-extracted signal l2_valid from priority_decoder.vhd
+- Offset: `0x7dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l2_winner
+Auto-extracted signal l2_winner from priority_decoder.vhd
+- Offset: `0x7e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l3_valid
+Auto-extracted signal l3_valid from priority_decoder.vhd
+- Offset: `0x7e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## priority_decoder_l3_winner
+Auto-extracted signal l3_winner from priority_decoder.vhd
+- Offset: `0x7e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_can_fd_ena
+Auto-extracted signal drv_can_fd_ena from protocol_control.vhd
+- Offset: `0x7ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_bus_mon_ena
+Auto-extracted signal drv_bus_mon_ena from protocol_control.vhd
+- Offset: `0x7f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_retr_lim_ena
+Auto-extracted signal drv_retr_lim_ena from protocol_control.vhd
+- Offset: `0x7f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_retr_th
+Auto-extracted signal drv_retr_th from protocol_control.vhd
+- Offset: `0x7f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_self_test_ena
+Auto-extracted signal drv_self_test_ena from protocol_control.vhd
+- Offset: `0x7fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ack_forb
+Auto-extracted signal drv_ack_forb from protocol_control.vhd
+- Offset: `0x800`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ena
+Auto-extracted signal drv_ena from protocol_control.vhd
+- Offset: `0x804`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_fd_type
+Auto-extracted signal drv_fd_type from protocol_control.vhd
+- Offset: `0x808`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_int_loopback_ena
+Auto-extracted signal drv_int_loopback_ena from protocol_control.vhd
+- Offset: `0x80c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_bus_off_reset
+Auto-extracted signal drv_bus_off_reset from protocol_control.vhd
+- Offset: `0x810`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_ssp_delay_select
+Auto-extracted signal drv_ssp_delay_select from protocol_control.vhd
+- Offset: `0x814`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_pex
+Auto-extracted signal drv_pex from protocol_control.vhd
+- Offset: `0x818`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_cpexs
+Auto-extracted signal drv_cpexs from protocol_control.vhd
+- Offset: `0x81c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tran_word_swapped
+Auto-extracted signal tran_word_swapped from protocol_control.vhd
+- Offset: `0x820`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_err_frm_req
+Auto-extracted signal err_frm_req from protocol_control.vhd
+- Offset: `0x824`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_base_id
+Auto-extracted signal tx_load_base_id from protocol_control.vhd
+- Offset: `0x828`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_ext_id
+Auto-extracted signal tx_load_ext_id from protocol_control.vhd
+- Offset: `0x82c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_dlc
+Auto-extracted signal tx_load_dlc from protocol_control.vhd
+- Offset: `0x830`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_data_word
+Auto-extracted signal tx_load_data_word from protocol_control.vhd
+- Offset: `0x834`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_stuff_count
+Auto-extracted signal tx_load_stuff_count from protocol_control.vhd
+- Offset: `0x838`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_load_crc
+Auto-extracted signal tx_load_crc from protocol_control.vhd
+- Offset: `0x83c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_shift_ena
+Auto-extracted signal tx_shift_ena from protocol_control.vhd
+- Offset: `0x840`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_dominant
+Auto-extracted signal tx_dominant from protocol_control.vhd
+- Offset: `0x844`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_clear
+Auto-extracted signal rx_clear from protocol_control.vhd
+- Offset: `0x848`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_base_id
+Auto-extracted signal rx_store_base_id from protocol_control.vhd
+- Offset: `0x84c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_ext_id
+Auto-extracted signal rx_store_ext_id from protocol_control.vhd
+- Offset: `0x850`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_ide
+Auto-extracted signal rx_store_ide from protocol_control.vhd
+- Offset: `0x854`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_rtr
+Auto-extracted signal rx_store_rtr from protocol_control.vhd
+- Offset: `0x858`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_edl
+Auto-extracted signal rx_store_edl from protocol_control.vhd
+- Offset: `0x85c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_dlc
+Auto-extracted signal rx_store_dlc from protocol_control.vhd
+- Offset: `0x860`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_esi
+Auto-extracted signal rx_store_esi from protocol_control.vhd
+- Offset: `0x864`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_brs
+Auto-extracted signal rx_store_brs from protocol_control.vhd
+- Offset: `0x868`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_store_stuff_count
+Auto-extracted signal rx_store_stuff_count from protocol_control.vhd
+- Offset: `0x86c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_shift_ena
+Auto-extracted signal rx_shift_ena from protocol_control.vhd
+- Offset: `0x870`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_shift_in_sel
+Auto-extracted signal rx_shift_in_sel from protocol_control.vhd
+- Offset: `0x874`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from protocol_control.vhd
+- Offset: `0x878`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_dlc_d
+Auto-extracted signal rec_dlc_d from protocol_control.vhd
+- Offset: `0x87c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_dlc_q
+Auto-extracted signal rec_dlc_q from protocol_control.vhd
+- Offset: `0x880`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from protocol_control.vhd
+- Offset: `0x884`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_pload
+Auto-extracted signal ctrl_ctr_pload from protocol_control.vhd
+- Offset: `0x888`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_pload_val
+Auto-extracted signal ctrl_ctr_pload_val from protocol_control.vhd
+- Offset: `0x88c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_ena
+Auto-extracted signal ctrl_ctr_ena from protocol_control.vhd
+- Offset: `0x890`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_zero
+Auto-extracted signal ctrl_ctr_zero from protocol_control.vhd
+- Offset: `0x894`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_one
+Auto-extracted signal ctrl_ctr_one from protocol_control.vhd
+- Offset: `0x898`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_counted_byte
+Auto-extracted signal ctrl_counted_byte from protocol_control.vhd
+- Offset: `0x89c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_counted_byte_index
+Auto-extracted signal ctrl_counted_byte_index from protocol_control.vhd
+- Offset: `0x8a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ctrl_ctr_mem_index
+Auto-extracted signal ctrl_ctr_mem_index from protocol_control.vhd
+- Offset: `0x8a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_compl_ctr_ena
+Auto-extracted signal compl_ctr_ena from protocol_control.vhd
+- Offset: `0x8a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_clr
+Auto-extracted signal reinteg_ctr_clr from protocol_control.vhd
+- Offset: `0x8ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_enable
+Auto-extracted signal reinteg_ctr_enable from protocol_control.vhd
+- Offset: `0x8b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_reinteg_ctr_expired
+Auto-extracted signal reinteg_ctr_expired from protocol_control.vhd
+- Offset: `0x8b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_ctr_clear
+Auto-extracted signal retr_ctr_clear from protocol_control.vhd
+- Offset: `0x8b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_ctr_add
+Auto-extracted signal retr_ctr_add from protocol_control.vhd
+- Offset: `0x8bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_retr_limit_reached
+Auto-extracted signal retr_limit_reached from protocol_control.vhd
+- Offset: `0x8c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_form_err_i
+Auto-extracted signal form_err_i from protocol_control.vhd
+- Offset: `0x8c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_ack_err_i
+Auto-extracted signal ack_err_i from protocol_control.vhd
+- Offset: `0x8c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_check
+Auto-extracted signal crc_check from protocol_control.vhd
+- Offset: `0x8cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_bit_err_arb
+Auto-extracted signal bit_err_arb from protocol_control.vhd
+- Offset: `0x8d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_match
+Auto-extracted signal crc_match from protocol_control.vhd
+- Offset: `0x8d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_err_i
+Auto-extracted signal crc_err_i from protocol_control.vhd
+- Offset: `0x8d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_clear_match_flag
+Auto-extracted signal crc_clear_match_flag from protocol_control.vhd
+- Offset: `0x8dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_crc_src
+Auto-extracted signal crc_src from protocol_control.vhd
+- Offset: `0x8e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_err_pos
+Auto-extracted signal err_pos from protocol_control.vhd
+- Offset: `0x8e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_is_arbitration_i
+Auto-extracted signal is_arbitration_i from protocol_control.vhd
+- Offset: `0x8e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_bit_err_enable
+Auto-extracted signal bit_err_enable from protocol_control.vhd
+- Offset: `0x8ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_tx_data_nbs_i
+Auto-extracted signal tx_data_nbs_i from protocol_control.vhd
+- Offset: `0x8f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_crc
+Auto-extracted signal rx_crc from protocol_control.vhd
+- Offset: `0x8f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_rx_stuff_count
+Auto-extracted signal rx_stuff_count from protocol_control.vhd
+- Offset: `0x8f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fixed_stuff_i
+Auto-extracted signal fixed_stuff_i from protocol_control.vhd
+- Offset: `0x8fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from protocol_control.vhd
+- Offset: `0x900`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_alc_id_field
+Auto-extracted signal alc_id_field from protocol_control.vhd
+- Offset: `0x904`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_drv_rom_ena
+Auto-extracted signal drv_rom_ena from protocol_control.vhd
+- Offset: `0x908`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_state_reg_ce
+Auto-extracted signal state_reg_ce from protocol_control_fsm.vhd
+- Offset: `0x90c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_transmitter
+Auto-extracted signal no_data_transmitter from protocol_control_fsm.vhd
+- Offset: `0x910`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_receiver
+Auto-extracted signal no_data_receiver from protocol_control_fsm.vhd
+- Offset: `0x914`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_no_data_field
+Auto-extracted signal no_data_field from protocol_control_fsm.vhd
+- Offset: `0x918`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_ctr_pload_i
+Auto-extracted signal ctrl_ctr_pload_i from protocol_control_fsm.vhd
+- Offset: `0x91c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_ctr_pload_unaliged
+Auto-extracted signal ctrl_ctr_pload_unaliged from protocol_control_fsm.vhd
+- Offset: `0x920`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_use_21
+Auto-extracted signal crc_use_21 from protocol_control_fsm.vhd
+- Offset: `0x924`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_use_17
+Auto-extracted signal crc_use_17 from protocol_control_fsm.vhd
+- Offset: `0x928`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_src_i
+Auto-extracted signal crc_src_i from protocol_control_fsm.vhd
+- Offset: `0x92c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_length_i
+Auto-extracted signal crc_length_i from protocol_control_fsm.vhd
+- Offset: `0x930`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tran_data_length
+Auto-extracted signal tran_data_length from protocol_control_fsm.vhd
+- Offset: `0x934`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_data_length
+Auto-extracted signal rec_data_length from protocol_control_fsm.vhd
+- Offset: `0x938`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_data_length_c
+Auto-extracted signal rec_data_length_c from protocol_control_fsm.vhd
+- Offset: `0x93c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_c
+Auto-extracted signal data_length_c from protocol_control_fsm.vhd
+- Offset: `0x940`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_shifted_c
+Auto-extracted signal data_length_shifted_c from protocol_control_fsm.vhd
+- Offset: `0x944`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_data_length_bits_c
+Auto-extracted signal data_length_bits_c from protocol_control_fsm.vhd
+- Offset: `0x948`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_is_fd_frame
+Auto-extracted signal is_fd_frame from protocol_control_fsm.vhd
+- Offset: `0x94c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_frame_start
+Auto-extracted signal frame_start from protocol_control_fsm.vhd
+- Offset: `0x950`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_ready
+Auto-extracted signal tx_frame_ready from protocol_control_fsm.vhd
+- Offset: `0x954`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ide_is_arbitration
+Auto-extracted signal ide_is_arbitration from protocol_control_fsm.vhd
+- Offset: `0x958`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_arbitration_lost_condition
+Auto-extracted signal arbitration_lost_condition from protocol_control_fsm.vhd
+- Offset: `0x95c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_arbitration_lost_i
+Auto-extracted signal arbitration_lost_i from protocol_control_fsm.vhd
+- Offset: `0x960`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_failed
+Auto-extracted signal tx_failed from protocol_control_fsm.vhd
+- Offset: `0x964`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_store_metadata_d
+Auto-extracted signal store_metadata_d from protocol_control_fsm.vhd
+- Offset: `0x968`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_store_data_d
+Auto-extracted signal store_data_d from protocol_control_fsm.vhd
+- Offset: `0x96c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_valid_d
+Auto-extracted signal rec_valid_d from protocol_control_fsm.vhd
+- Offset: `0x970`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rec_abort_d
+Auto-extracted signal rec_abort_d from protocol_control_fsm.vhd
+- Offset: `0x974`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_go_to_suspend
+Auto-extracted signal go_to_suspend from protocol_control_fsm.vhd
+- Offset: `0x978`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_go_to_stuff_count
+Auto-extracted signal go_to_stuff_count from protocol_control_fsm.vhd
+- Offset: `0x97c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_base_id_i
+Auto-extracted signal rx_store_base_id_i from protocol_control_fsm.vhd
+- Offset: `0x980`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_ext_id_i
+Auto-extracted signal rx_store_ext_id_i from protocol_control_fsm.vhd
+- Offset: `0x984`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_ide_i
+Auto-extracted signal rx_store_ide_i from protocol_control_fsm.vhd
+- Offset: `0x988`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_rtr_i
+Auto-extracted signal rx_store_rtr_i from protocol_control_fsm.vhd
+- Offset: `0x98c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_edl_i
+Auto-extracted signal rx_store_edl_i from protocol_control_fsm.vhd
+- Offset: `0x990`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_dlc_i
+Auto-extracted signal rx_store_dlc_i from protocol_control_fsm.vhd
+- Offset: `0x994`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_esi_i
+Auto-extracted signal rx_store_esi_i from protocol_control_fsm.vhd
+- Offset: `0x998`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_brs_i
+Auto-extracted signal rx_store_brs_i from protocol_control_fsm.vhd
+- Offset: `0x99c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_store_stuff_count_i
+Auto-extracted signal rx_store_stuff_count_i from protocol_control_fsm.vhd
+- Offset: `0x9a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_clear_i
+Auto-extracted signal rx_clear_i from protocol_control_fsm.vhd
+- Offset: `0x9a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_base_id_i
+Auto-extracted signal tx_load_base_id_i from protocol_control_fsm.vhd
+- Offset: `0x9a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_ext_id_i
+Auto-extracted signal tx_load_ext_id_i from protocol_control_fsm.vhd
+- Offset: `0x9ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_dlc_i
+Auto-extracted signal tx_load_dlc_i from protocol_control_fsm.vhd
+- Offset: `0x9b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_data_word_i
+Auto-extracted signal tx_load_data_word_i from protocol_control_fsm.vhd
+- Offset: `0x9b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_stuff_count_i
+Auto-extracted signal tx_load_stuff_count_i from protocol_control_fsm.vhd
+- Offset: `0x9b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_load_crc_i
+Auto-extracted signal tx_load_crc_i from protocol_control_fsm.vhd
+- Offset: `0x9bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_shift_ena_i
+Auto-extracted signal tx_shift_ena_i from protocol_control_fsm.vhd
+- Offset: `0x9c0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_form_err_i
+Auto-extracted signal form_err_i from protocol_control_fsm.vhd
+- Offset: `0x9c4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_i
+Auto-extracted signal ack_err_i from protocol_control_fsm.vhd
+- Offset: `0x9c8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_flag
+Auto-extracted signal ack_err_flag from protocol_control_fsm.vhd
+- Offset: `0x9cc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ack_err_flag_clr
+Auto-extracted signal ack_err_flag_clr from protocol_control_fsm.vhd
+- Offset: `0x9d0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_err_i
+Auto-extracted signal crc_err_i from protocol_control_fsm.vhd
+- Offset: `0x9d4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_arb_i
+Auto-extracted signal bit_err_arb_i from protocol_control_fsm.vhd
+- Offset: `0x9d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_switch_data
+Auto-extracted signal sp_control_switch_data from protocol_control_fsm.vhd
+- Offset: `0x9dc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_switch_nominal
+Auto-extracted signal sp_control_switch_nominal from protocol_control_fsm.vhd
+- Offset: `0x9e0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_switch_to_ssp
+Auto-extracted signal switch_to_ssp from protocol_control_fsm.vhd
+- Offset: `0x9e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_ce
+Auto-extracted signal sp_control_ce from protocol_control_fsm.vhd
+- Offset: `0x9e8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_d
+Auto-extracted signal sp_control_d from protocol_control_fsm.vhd
+- Offset: `0x9ec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sp_control_q_i
+Auto-extracted signal sp_control_q_i from protocol_control_fsm.vhd
+- Offset: `0x9f0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ssp_reset_i
+Auto-extracted signal ssp_reset_i from protocol_control_fsm.vhd
+- Offset: `0x9f4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sync_control_d
+Auto-extracted signal sync_control_d from protocol_control_fsm.vhd
+- Offset: `0x9f8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sync_control_q
+Auto-extracted signal sync_control_q from protocol_control_fsm.vhd
+- Offset: `0x9fc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_perform_hsync
+Auto-extracted signal perform_hsync from protocol_control_fsm.vhd
+- Offset: `0xa00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_primary_err_i
+Auto-extracted signal primary_err_i from protocol_control_fsm.vhd
+- Offset: `0xa04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_err_delim_late_i
+Auto-extracted signal err_delim_late_i from protocol_control_fsm.vhd
+- Offset: `0xa08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_err_active_i
+Auto-extracted signal set_err_active_i from protocol_control_fsm.vhd
+- Offset: `0xa0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_transmitter_i
+Auto-extracted signal set_transmitter_i from protocol_control_fsm.vhd
+- Offset: `0xa10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_receiver_i
+Auto-extracted signal set_receiver_i from protocol_control_fsm.vhd
+- Offset: `0xa14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_set_idle_i
+Auto-extracted signal set_idle_i from protocol_control_fsm.vhd
+- Offset: `0xa18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_first_err_delim_d
+Auto-extracted signal first_err_delim_d from protocol_control_fsm.vhd
+- Offset: `0xa1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_first_err_delim_q
+Auto-extracted signal first_err_delim_q from protocol_control_fsm.vhd
+- Offset: `0xa20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_stuff_enable_set
+Auto-extracted signal stuff_enable_set from protocol_control_fsm.vhd
+- Offset: `0xa24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_stuff_enable_clear
+Auto-extracted signal stuff_enable_clear from protocol_control_fsm.vhd
+- Offset: `0xa28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_destuff_enable_set
+Auto-extracted signal destuff_enable_set from protocol_control_fsm.vhd
+- Offset: `0xa2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_destuff_enable_clear
+Auto-extracted signal destuff_enable_clear from protocol_control_fsm.vhd
+- Offset: `0xa30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_disable
+Auto-extracted signal bit_err_disable from protocol_control_fsm.vhd
+- Offset: `0xa34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_bit_err_disable_receiver
+Auto-extracted signal bit_err_disable_receiver from protocol_control_fsm.vhd
+- Offset: `0xa38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_sof_pulse_i
+Auto-extracted signal sof_pulse_i from protocol_control_fsm.vhd
+- Offset: `0xa3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_compl_ctr_ena_i
+Auto-extracted signal compl_ctr_ena_i from protocol_control_fsm.vhd
+- Offset: `0xa40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tick_state_reg
+Auto-extracted signal tick_state_reg from protocol_control_fsm.vhd
+- Offset: `0xa44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_br_shifted_i
+Auto-extracted signal br_shifted_i from protocol_control_fsm.vhd
+- Offset: `0xa48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_is_arbitration_i
+Auto-extracted signal is_arbitration_i from protocol_control_fsm.vhd
+- Offset: `0xa4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_crc_spec_enable_i
+Auto-extracted signal crc_spec_enable_i from protocol_control_fsm.vhd
+- Offset: `0xa50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_load_init_vect_i
+Auto-extracted signal load_init_vect_i from protocol_control_fsm.vhd
+- Offset: `0xa54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_drv_bus_off_reset_q
+Auto-extracted signal drv_bus_off_reset_q from protocol_control_fsm.vhd
+- Offset: `0xa58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_clear_i
+Auto-extracted signal retr_ctr_clear_i from protocol_control_fsm.vhd
+- Offset: `0xa5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_i
+Auto-extracted signal retr_ctr_add_i from protocol_control_fsm.vhd
+- Offset: `0xa60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_decrement_rec_i
+Auto-extracted signal decrement_rec_i from protocol_control_fsm.vhd
+- Offset: `0xa64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_block
+Auto-extracted signal retr_ctr_add_block from protocol_control_fsm.vhd
+- Offset: `0xa68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_retr_ctr_add_block_clr
+Auto-extracted signal retr_ctr_add_block_clr from protocol_control_fsm.vhd
+- Offset: `0xa6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_block_txtb_unlock
+Auto-extracted signal block_txtb_unlock from protocol_control_fsm.vhd
+- Offset: `0xa70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_no_sof_d
+Auto-extracted signal tx_frame_no_sof_d from protocol_control_fsm.vhd
+- Offset: `0xa74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tx_frame_no_sof_q
+Auto-extracted signal tx_frame_no_sof_q from protocol_control_fsm.vhd
+- Offset: `0xa78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_ctrl_signal_upd
+Auto-extracted signal ctrl_signal_upd from protocol_control_fsm.vhd
+- Offset: `0xa7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_clr_bus_off_rst_flg
+Auto-extracted signal clr_bus_off_rst_flg from protocol_control_fsm.vhd
+- Offset: `0xa80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pex_on_fdf_enable
+Auto-extracted signal pex_on_fdf_enable from protocol_control_fsm.vhd
+- Offset: `0xa84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pex_on_res_enable
+Auto-extracted signal pex_on_res_enable from protocol_control_fsm.vhd
+- Offset: `0xa88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_rx_data_nbs_prev
+Auto-extracted signal rx_data_nbs_prev from protocol_control_fsm.vhd
+- Offset: `0xa8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_pexs_set
+Auto-extracted signal pexs_set from protocol_control_fsm.vhd
+- Offset: `0xa90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_tran_frame_type_i
+Auto-extracted signal tran_frame_type_i from protocol_control_fsm.vhd
+- Offset: `0xa94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_txtb_clk_en_d
+Auto-extracted signal txtb_clk_en_d from protocol_control_fsm.vhd
+- Offset: `0xa98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## protocol_control_fsm_txtb_clk_en_q
+Auto-extracted signal txtb_clk_en_q from protocol_control_fsm.vhd
+- Offset: `0xa9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## reintegration_counter_reinteg_ctr_ce
+Auto-extracted signal reinteg_ctr_ce from reintegration_counter.vhd
+- Offset: `0xaa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## retransmitt_counter_retr_ctr_ce
+Auto-extracted signal retr_ctr_ce from retransmitt_counter.vhd
+- Offset: `0xaa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rst_sync_rff
+Auto-extracted signal rff from rst_sync.vhd
+- Offset: `0xaa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_erase_rx
+Auto-extracted signal drv_erase_rx from rx_buffer.vhd
+- Offset: `0xaac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_read_start
+Auto-extracted signal drv_read_start from rx_buffer.vhd
+- Offset: `0xab0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_clr_ovr
+Auto-extracted signal drv_clr_ovr from rx_buffer.vhd
+- Offset: `0xab4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_drv_rtsopt
+Auto-extracted signal drv_rtsopt from rx_buffer.vhd
+- Offset: `0xab8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_pointer
+Auto-extracted signal read_pointer from rx_buffer.vhd
+- Offset: `0xabc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_pointer_inc_1
+Auto-extracted signal read_pointer_inc_1 from rx_buffer.vhd
+- Offset: `0xac0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer
+Auto-extracted signal write_pointer from rx_buffer.vhd
+- Offset: `0xac4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer_raw
+Auto-extracted signal write_pointer_raw from rx_buffer.vhd
+- Offset: `0xac8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_pointer_ts
+Auto-extracted signal write_pointer_ts from rx_buffer.vhd
+- Offset: `0xacc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_mem_free_i
+Auto-extracted signal rx_mem_free_i from rx_buffer.vhd
+- Offset: `0xad0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_memory_write_data
+Auto-extracted signal memory_write_data from rx_buffer.vhd
+- Offset: `0xad4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_overrun_flg
+Auto-extracted signal data_overrun_flg from rx_buffer.vhd
+- Offset: `0xad8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_overrun_i
+Auto-extracted signal data_overrun_i from rx_buffer.vhd
+- Offset: `0xadc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_overrun_condition
+Auto-extracted signal overrun_condition from rx_buffer.vhd
+- Offset: `0xae0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_empty_i
+Auto-extracted signal rx_empty_i from rx_buffer.vhd
+- Offset: `0xae4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_is_free_word
+Auto-extracted signal is_free_word from rx_buffer.vhd
+- Offset: `0xae8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_commit_rx_frame
+Auto-extracted signal commit_rx_frame from rx_buffer.vhd
+- Offset: `0xaec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_commit_overrun_abort
+Auto-extracted signal commit_overrun_abort from rx_buffer.vhd
+- Offset: `0xaf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_read_increment
+Auto-extracted signal read_increment from rx_buffer.vhd
+- Offset: `0xaf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_raw_OK
+Auto-extracted signal write_raw_OK from rx_buffer.vhd
+- Offset: `0xaf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_raw_intent
+Auto-extracted signal write_raw_intent from rx_buffer.vhd
+- Offset: `0xafc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_write_ts
+Auto-extracted signal write_ts from rx_buffer.vhd
+- Offset: `0xb00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_stored_ts
+Auto-extracted signal stored_ts from rx_buffer.vhd
+- Offset: `0xb04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_data_selector
+Auto-extracted signal data_selector from rx_buffer.vhd
+- Offset: `0xb08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_store_ts_wr_ptr
+Auto-extracted signal store_ts_wr_ptr from rx_buffer.vhd
+- Offset: `0xb0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_inc_ts_wr_ptr
+Auto-extracted signal inc_ts_wr_ptr from rx_buffer.vhd
+- Offset: `0xb10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_reset_overrun_flag
+Auto-extracted signal reset_overrun_flag from rx_buffer.vhd
+- Offset: `0xb14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_frame_form_w
+Auto-extracted signal frame_form_w from rx_buffer.vhd
+- Offset: `0xb18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_timestamp_capture
+Auto-extracted signal timestamp_capture from rx_buffer.vhd
+- Offset: `0xb1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_timestamp_capture_ce
+Auto-extracted signal timestamp_capture_ce from rx_buffer.vhd
+- Offset: `0xb20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_write
+Auto-extracted signal RAM_write from rx_buffer.vhd
+- Offset: `0xb24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_data_out
+Auto-extracted signal RAM_data_out from rx_buffer.vhd
+- Offset: `0xb28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_write_address
+Auto-extracted signal RAM_write_address from rx_buffer.vhd
+- Offset: `0xb2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_RAM_read_address
+Auto-extracted signal RAM_read_address from rx_buffer.vhd
+- Offset: `0xb30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_d
+Auto-extracted signal rx_buf_res_n_d from rx_buffer.vhd
+- Offset: `0xb34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_q
+Auto-extracted signal rx_buf_res_n_q from rx_buffer.vhd
+- Offset: `0xb38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_res_n_q_scan
+Auto-extracted signal rx_buf_res_n_q_scan from rx_buffer.vhd
+- Offset: `0xb3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_rx_buf_ram_clk_en
+Auto-extracted signal rx_buf_ram_clk_en from rx_buffer.vhd
+- Offset: `0xb40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_clk_ram
+Auto-extracted signal clk_ram from rx_buffer.vhd
+- Offset: `0xb44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_fsm_rx_fsm_ce
+Auto-extracted signal rx_fsm_ce from rx_buffer_fsm.vhd
+- Offset: `0xb48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_fsm_cmd_join
+Auto-extracted signal cmd_join from rx_buffer_fsm.vhd
+- Offset: `0xb4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_pointers_write_pointer_raw_ce
+Auto-extracted signal write_pointer_raw_ce from rx_buffer_pointers.vhd
+- Offset: `0xb50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_pointers_write_pointer_ts_ce
+Auto-extracted signal write_pointer_ts_ce from rx_buffer_pointers.vhd
+- Offset: `0xb54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_address_i
+Auto-extracted signal port_a_address_i from rx_buffer_ram.vhd
+- Offset: `0xb58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_write_i
+Auto-extracted signal port_a_write_i from rx_buffer_ram.vhd
+- Offset: `0xb5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_a_data_in_i
+Auto-extracted signal port_a_data_in_i from rx_buffer_ram.vhd
+- Offset: `0xb60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_b_address_i
+Auto-extracted signal port_b_address_i from rx_buffer_ram.vhd
+- Offset: `0xb64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_port_b_data_out_i
+Auto-extracted signal port_b_data_out_i from rx_buffer_ram.vhd
+- Offset: `0xb68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_tst_ena
+Auto-extracted signal tst_ena from rx_buffer_ram.vhd
+- Offset: `0xb6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_buffer_ram_tst_addr
+Auto-extracted signal tst_addr from rx_buffer_ram.vhd
+- Offset: `0xb70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_d
+Auto-extracted signal res_n_i_d from rx_shift_reg.vhd
+- Offset: `0xb74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_q
+Auto-extracted signal res_n_i_q from rx_shift_reg.vhd
+- Offset: `0xb78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_res_n_i_q_scan
+Auto-extracted signal res_n_i_q_scan from rx_shift_reg.vhd
+- Offset: `0xb7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_reg_q
+Auto-extracted signal rx_shift_reg_q from rx_shift_reg.vhd
+- Offset: `0xb80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_cmd
+Auto-extracted signal rx_shift_cmd from rx_shift_reg.vhd
+- Offset: `0xb84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rx_shift_in_sel_demuxed
+Auto-extracted signal rx_shift_in_sel_demuxed from rx_shift_reg.vhd
+- Offset: `0xb88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rec_is_rtr_i
+Auto-extracted signal rec_is_rtr_i from rx_shift_reg.vhd
+- Offset: `0xb8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## rx_shift_reg_rec_frame_type_i
+Auto-extracted signal rec_frame_type_i from rx_shift_reg.vhd
+- Offset: `0xb90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_sample
+Auto-extracted signal sample from sample_mux.vhd
+- Offset: `0xb94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_prev_sample_d
+Auto-extracted signal prev_sample_d from sample_mux.vhd
+- Offset: `0xb98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sample_mux_prev_sample_q
+Auto-extracted signal prev_sample_q from sample_mux.vhd
+- Offset: `0xb9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_req_input
+Auto-extracted signal req_input from segment_end_detector.vhd
+- Offset: `0xba0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_d
+Auto-extracted signal segm_end_req_capt_d from segment_end_detector.vhd
+- Offset: `0xba4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_q
+Auto-extracted signal segm_end_req_capt_q from segment_end_detector.vhd
+- Offset: `0xba8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_ce
+Auto-extracted signal segm_end_req_capt_ce from segment_end_detector.vhd
+- Offset: `0xbac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_clr
+Auto-extracted signal segm_end_req_capt_clr from segment_end_detector.vhd
+- Offset: `0xbb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_req_capt_dq
+Auto-extracted signal segm_end_req_capt_dq from segment_end_detector.vhd
+- Offset: `0xbb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_nbt_valid
+Auto-extracted signal segm_end_nbt_valid from segment_end_detector.vhd
+- Offset: `0xbb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_dbt_valid
+Auto-extracted signal segm_end_dbt_valid from segment_end_detector.vhd
+- Offset: `0xbbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segm_end_nbt_dbt_valid
+Auto-extracted signal segm_end_nbt_dbt_valid from segment_end_detector.vhd
+- Offset: `0xbc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_tseg1_end_req_valid
+Auto-extracted signal tseg1_end_req_valid from segment_end_detector.vhd
+- Offset: `0xbc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_tseg2_end_req_valid
+Auto-extracted signal tseg2_end_req_valid from segment_end_detector.vhd
+- Offset: `0xbc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_h_sync_valid_i
+Auto-extracted signal h_sync_valid_i from segment_end_detector.vhd
+- Offset: `0xbcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_segment_end_i
+Auto-extracted signal segment_end_i from segment_end_detector.vhd
+- Offset: `0xbd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_nbt_tq_active
+Auto-extracted signal nbt_tq_active from segment_end_detector.vhd
+- Offset: `0xbd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_dbt_tq_active
+Auto-extracted signal dbt_tq_active from segment_end_detector.vhd
+- Offset: `0xbd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## segment_end_detector_bt_ctr_clear_i
+Auto-extracted signal bt_ctr_clear_i from segment_end_detector.vhd
+- Offset: `0xbdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_shift_regs
+Auto-extracted signal shift_regs from shift_reg.vhd
+- Offset: `0xbe0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_next_shift_reg_val
+Auto-extracted signal next_shift_reg_val from shift_reg.vhd
+- Offset: `0xbe4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_byte_shift_reg_in
+Auto-extracted signal shift_reg_in from shift_reg_byte.vhd
+- Offset: `0xbe8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_preload_shift_regs
+Auto-extracted signal shift_regs from shift_reg_preload.vhd
+- Offset: `0xbec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## shift_reg_preload_next_shift_reg_val
+Auto-extracted signal next_shift_reg_val from shift_reg_preload.vhd
+- Offset: `0xbf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## sig_sync_rff
+Auto-extracted signal rff from sig_sync.vhd
+- Offset: `0xbf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_d
+Auto-extracted signal btmc_d from ssp_generator.vhd
+- Offset: `0xbf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_q
+Auto-extracted signal btmc_q from ssp_generator.vhd
+- Offset: `0xbfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_add
+Auto-extracted signal btmc_add from ssp_generator.vhd
+- Offset: `0xc00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_ce
+Auto-extracted signal btmc_ce from ssp_generator.vhd
+- Offset: `0xc04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_meas_running_d
+Auto-extracted signal btmc_meas_running_d from ssp_generator.vhd
+- Offset: `0xc08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_btmc_meas_running_q
+Auto-extracted signal btmc_meas_running_q from ssp_generator.vhd
+- Offset: `0xc0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_d
+Auto-extracted signal sspc_d from ssp_generator.vhd
+- Offset: `0xc10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_q
+Auto-extracted signal sspc_q from ssp_generator.vhd
+- Offset: `0xc14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ce
+Auto-extracted signal sspc_ce from ssp_generator.vhd
+- Offset: `0xc18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_expired
+Auto-extracted signal sspc_expired from ssp_generator.vhd
+- Offset: `0xc1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_threshold
+Auto-extracted signal sspc_threshold from ssp_generator.vhd
+- Offset: `0xc20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_add
+Auto-extracted signal sspc_add from ssp_generator.vhd
+- Offset: `0xc24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_first_ssp_d
+Auto-extracted signal first_ssp_d from ssp_generator.vhd
+- Offset: `0xc28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_first_ssp_q
+Auto-extracted signal first_ssp_q from ssp_generator.vhd
+- Offset: `0xc2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ena_d
+Auto-extracted signal sspc_ena_d from ssp_generator.vhd
+- Offset: `0xc30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_sspc_ena_q
+Auto-extracted signal sspc_ena_q from ssp_generator.vhd
+- Offset: `0xc34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## ssp_generator_ssp_delay_padded
+Auto-extracted signal ssp_delay_padded from ssp_generator.vhd
+- Offset: `0xc38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_resync_edge
+Auto-extracted signal resync_edge from synchronisation_checker.vhd
+- Offset: `0xc3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_h_sync_edge
+Auto-extracted signal h_sync_edge from synchronisation_checker.vhd
+- Offset: `0xc40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_h_or_re_sync_edge
+Auto-extracted signal h_or_re_sync_edge from synchronisation_checker.vhd
+- Offset: `0xc44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag
+Auto-extracted signal sync_flag from synchronisation_checker.vhd
+- Offset: `0xc48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag_ce
+Auto-extracted signal sync_flag_ce from synchronisation_checker.vhd
+- Offset: `0xc4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## synchronisation_checker_sync_flag_nxt
+Auto-extracted signal sync_flag_nxt from synchronisation_checker.vhd
+- Offset: `0xc50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_reg_sel
+Auto-extracted signal reg_sel from test_registers_reg_map.vhd
+- Offset: `0xc54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_data_mux_in
+Auto-extracted signal read_data_mux_in from test_registers_reg_map.vhd
+- Offset: `0xc58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_data_mask_n
+Auto-extracted signal read_data_mask_n from test_registers_reg_map.vhd
+- Offset: `0xc5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## test_registers_reg_map_read_mux_ena
+Auto-extracted signal read_mux_ena from test_registers_reg_map.vhd
+- Offset: `0xc60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_rx_trig_req_q
+Auto-extracted signal rx_trig_req_q from trigger_generator.vhd
+- Offset: `0xc64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_d
+Auto-extracted signal tx_trig_req_flag_d from trigger_generator.vhd
+- Offset: `0xc68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_q
+Auto-extracted signal tx_trig_req_flag_q from trigger_generator.vhd
+- Offset: `0xc6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_generator_tx_trig_req_flag_dq
+Auto-extracted signal tx_trig_req_flag_dq from trigger_generator.vhd
+- Offset: `0xc70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trigger_mux_tx_trigger_q
+Auto-extracted signal tx_trigger_q from trigger_mux.vhd
+- Offset: `0xc74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_d
+Auto-extracted signal trv_meas_progress_d from trv_delay_meas.vhd
+- Offset: `0xc78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_q
+Auto-extracted signal trv_meas_progress_q from trv_delay_meas.vhd
+- Offset: `0xc7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_meas_progress_del
+Auto-extracted signal trv_meas_progress_del from trv_delay_meas.vhd
+- Offset: `0xc80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_q
+Auto-extracted signal trv_delay_ctr_q from trv_delay_meas.vhd
+- Offset: `0xc84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_d
+Auto-extracted signal trv_delay_ctr_d from trv_delay_meas.vhd
+- Offset: `0xc88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_add
+Auto-extracted signal trv_delay_ctr_add from trv_delay_meas.vhd
+- Offset: `0xc8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_q_padded
+Auto-extracted signal trv_delay_ctr_q_padded from trv_delay_meas.vhd
+- Offset: `0xc90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_d
+Auto-extracted signal trv_delay_ctr_rst_d from trv_delay_meas.vhd
+- Offset: `0xc94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_q
+Auto-extracted signal trv_delay_ctr_rst_q from trv_delay_meas.vhd
+- Offset: `0xc98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_ctr_rst_q_scan
+Auto-extracted signal trv_delay_ctr_rst_q_scan from trv_delay_meas.vhd
+- Offset: `0xc9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_shadow_ce
+Auto-extracted signal ssp_shadow_ce from trv_delay_meas.vhd
+- Offset: `0xca0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_delay_raw
+Auto-extracted signal ssp_delay_raw from trv_delay_meas.vhd
+- Offset: `0xca4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_ssp_delay_saturated
+Auto-extracted signal ssp_delay_saturated from trv_delay_meas.vhd
+- Offset: `0xca8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## trv_delay_meas_trv_delay_sum
+Auto-extracted signal trv_delay_sum from trv_delay_meas.vhd
+- Offset: `0xcac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_select_buf_avail
+Auto-extracted signal select_buf_avail from tx_arbitrator.vhd
+- Offset: `0xcb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_selected_input
+Auto-extracted signal txtb_selected_input from tx_arbitrator.vhd
+- Offset: `0xcb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_timestamp
+Auto-extracted signal txtb_timestamp from tx_arbitrator.vhd
+- Offset: `0xcb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_timestamp_valid
+Auto-extracted signal timestamp_valid from tx_arbitrator.vhd
+- Offset: `0xcbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_select_index_changed
+Auto-extracted signal select_index_changed from tx_arbitrator.vhd
+- Offset: `0xcc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_validated_buffer
+Auto-extracted signal validated_buffer from tx_arbitrator.vhd
+- Offset: `0xcc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_ts_low_internal
+Auto-extracted signal ts_low_internal from tx_arbitrator.vhd
+- Offset: `0xcc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_dlc_dbl_buf
+Auto-extracted signal tran_dlc_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xccc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_is_rtr_dbl_buf
+Auto-extracted signal tran_is_rtr_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_ident_type_dbl_buf
+Auto-extracted signal tran_ident_type_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_type_dbl_buf
+Auto-extracted signal tran_frame_type_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcd8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_brs_dbl_buf
+Auto-extracted signal tran_brs_dbl_buf from tx_arbitrator.vhd
+- Offset: `0xcdc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_dlc_com
+Auto-extracted signal tran_dlc_com from tx_arbitrator.vhd
+- Offset: `0xce0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_is_rtr_com
+Auto-extracted signal tran_is_rtr_com from tx_arbitrator.vhd
+- Offset: `0xce4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_ident_type_com
+Auto-extracted signal tran_ident_type_com from tx_arbitrator.vhd
+- Offset: `0xce8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_type_com
+Auto-extracted signal tran_frame_type_com from tx_arbitrator.vhd
+- Offset: `0xcec`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_brs_com
+Auto-extracted signal tran_brs_com from tx_arbitrator.vhd
+- Offset: `0xcf0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_frame_valid_com
+Auto-extracted signal tran_frame_valid_com from tx_arbitrator.vhd
+- Offset: `0xcf4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tran_identifier_com
+Auto-extracted signal tran_identifier_com from tx_arbitrator.vhd
+- Offset: `0xcf8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ts_lw_addr
+Auto-extracted signal load_ts_lw_addr from tx_arbitrator.vhd
+- Offset: `0xcfc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ts_uw_addr
+Auto-extracted signal load_ts_uw_addr from tx_arbitrator.vhd
+- Offset: `0xd00`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ffmt_w_addr
+Auto-extracted signal load_ffmt_w_addr from tx_arbitrator.vhd
+- Offset: `0xd04`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_load_ident_w_addr
+Auto-extracted signal load_ident_w_addr from tx_arbitrator.vhd
+- Offset: `0xd08`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_ts_l_w
+Auto-extracted signal store_ts_l_w from tx_arbitrator.vhd
+- Offset: `0xd0c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_md_w
+Auto-extracted signal store_md_w from tx_arbitrator.vhd
+- Offset: `0xd10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_ident_w
+Auto-extracted signal store_ident_w from tx_arbitrator.vhd
+- Offset: `0xd14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_buffer_md_w
+Auto-extracted signal buffer_md_w from tx_arbitrator.vhd
+- Offset: `0xd18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_store_last_txtb_index
+Auto-extracted signal store_last_txtb_index from tx_arbitrator.vhd
+- Offset: `0xd1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_frame_valid_com_set
+Auto-extracted signal frame_valid_com_set from tx_arbitrator.vhd
+- Offset: `0xd20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_frame_valid_com_clear
+Auto-extracted signal frame_valid_com_clear from tx_arbitrator.vhd
+- Offset: `0xd24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_tx_arb_locked
+Auto-extracted signal tx_arb_locked from tx_arbitrator.vhd
+- Offset: `0xd28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_txtb_meta_clk_en
+Auto-extracted signal txtb_meta_clk_en from tx_arbitrator.vhd
+- Offset: `0xd2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_drv_tttm_ena
+Auto-extracted signal drv_tttm_ena from tx_arbitrator.vhd
+- Offset: `0xd30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_tx_arb_fsm_ce
+Auto-extracted signal tx_arb_fsm_ce from tx_arbitrator_fsm.vhd
+- Offset: `0xd34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_fsm_wait_state_d
+Auto-extracted signal fsm_wait_state_d from tx_arbitrator_fsm.vhd
+- Offset: `0xd38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_arbitrator_fsm_fsm_wait_state_q
+Auto-extracted signal fsm_wait_state_q from tx_arbitrator_fsm.vhd
+- Offset: `0xd3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_data_cache_tx_cache_mem
+Auto-extracted signal tx_cache_mem from tx_data_cache.vhd
+- Offset: `0xd40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_output
+Auto-extracted signal tx_sr_output from tx_shift_reg.vhd
+- Offset: `0xd44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_ce
+Auto-extracted signal tx_sr_ce from tx_shift_reg.vhd
+- Offset: `0xd48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_pload
+Auto-extracted signal tx_sr_pload from tx_shift_reg.vhd
+- Offset: `0xd4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_sr_pload_val
+Auto-extracted signal tx_sr_pload_val from tx_shift_reg.vhd
+- Offset: `0xd50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_base_id
+Auto-extracted signal tx_base_id from tx_shift_reg.vhd
+- Offset: `0xd54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_ext_id
+Auto-extracted signal tx_ext_id from tx_shift_reg.vhd
+- Offset: `0xd58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_tx_crc
+Auto-extracted signal tx_crc from tx_shift_reg.vhd
+- Offset: `0xd5c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_bst_ctr_grey
+Auto-extracted signal bst_ctr_grey from tx_shift_reg.vhd
+- Offset: `0xd60`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_bst_parity
+Auto-extracted signal bst_parity from tx_shift_reg.vhd
+- Offset: `0xd64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## tx_shift_reg_stuff_count
+Auto-extracted signal stuff_count from tx_shift_reg.vhd
+- Offset: `0xd68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_user_accessible
+Auto-extracted signal txtb_user_accessible from txt_buffer.vhd
+- Offset: `0xd6c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_hw_cbs
+Auto-extracted signal hw_cbs from txt_buffer.vhd
+- Offset: `0xd70`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_sw_cbs
+Auto-extracted signal sw_cbs from txt_buffer.vhd
+- Offset: `0xd74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_unmask_data_ram
+Auto-extracted signal txtb_unmask_data_ram from txt_buffer.vhd
+- Offset: `0xd78`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_port_b_data_i
+Auto-extracted signal txtb_port_b_data_i from txt_buffer.vhd
+- Offset: `0xd7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_write
+Auto-extracted signal ram_write from txt_buffer.vhd
+- Offset: `0xd80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_read_address
+Auto-extracted signal ram_read_address from txt_buffer.vhd
+- Offset: `0xd84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_txtb_ram_clk_en
+Auto-extracted signal txtb_ram_clk_en from txt_buffer.vhd
+- Offset: `0xd88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_clk_ram
+Auto-extracted signal clk_ram from txt_buffer.vhd
+- Offset: `0xd8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_abort_applied
+Auto-extracted signal abort_applied from txt_buffer_fsm.vhd
+- Offset: `0xd90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_txt_fsm_ce
+Auto-extracted signal txt_fsm_ce from txt_buffer_fsm.vhd
+- Offset: `0xd94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_go_to_failed
+Auto-extracted signal go_to_failed from txt_buffer_fsm.vhd
+- Offset: `0xd98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_fsm_transient_state
+Auto-extracted signal transient_state from txt_buffer_fsm.vhd
+- Offset: `0xd9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_address_i
+Auto-extracted signal port_a_address_i from txt_buffer_ram.vhd
+- Offset: `0xda0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_write_i
+Auto-extracted signal port_a_write_i from txt_buffer_ram.vhd
+- Offset: `0xda4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_a_data_in_i
+Auto-extracted signal port_a_data_in_i from txt_buffer_ram.vhd
+- Offset: `0xda8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_b_address_i
+Auto-extracted signal port_b_address_i from txt_buffer_ram.vhd
+- Offset: `0xdac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_port_b_data_out_i
+Auto-extracted signal port_b_data_out_i from txt_buffer_ram.vhd
+- Offset: `0xdb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_tst_ena
+Auto-extracted signal tst_ena from txt_buffer_ram.vhd
+- Offset: `0xdb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## txt_buffer_ram_tst_addr
+Auto-extracted signal tst_addr from txt_buffer_ram.vhd
+- Offset: `0xdb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_be_active
+Auto-extracted signal be_active from access_signaler.vhd
+- Offset: `0xdbc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_in
+Auto-extracted signal access_in from access_signaler.vhd
+- Offset: `0xdc0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_active
+Auto-extracted signal access_active from access_signaler.vhd
+- Offset: `0xdc4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## access_signaler_access_active_reg
+Auto-extracted signal access_active_reg from access_signaler.vhd
+- Offset: `0xdc8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## address_decoder_addr_dec_i
+Auto-extracted signal addr_dec_i from address_decoder.vhd
+- Offset: `0xdcc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
+## address_decoder_addr_dec_enabled_i
+Auto-extracted signal addr_dec_enabled_i from address_decoder.vhd
+- Offset: `0xdd0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "value", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:0  |   rw   |   0x0   | value  | Placeholder 32-bit field for extracted signal |
+
diff --git a/docs/um/ip/carfield_regs/data/carfield_regs_Doc.hjson b/docs/um/ip/carfield_regs/data/carfield_regs_Doc.hjson
new file mode 100644
index 00000000..dad20d5d
--- /dev/null
+++ b/docs/um/ip/carfield_regs/data/carfield_regs_Doc.hjson
@@ -0,0 +1,713 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Robert Balas <balasr@iis.ee.ethz.ch>
+// Luca Valente <luca.valente@unibo.it>
+{
+  name: "carfield",
+  cip_id: "2",
+  version: "1.0.1",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32",
+  registers :[
+
+    { name: "VERSION0",
+      desc: "Cheshire sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION1",
+      desc: "Safety Island sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION2",
+      desc: "Security Island sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION3",
+      desc: "PULP Cluster sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION4",
+      desc: "Spatz CLuster sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "JEDEC_IDCODE",
+      desc: "JEDEC ID CODE -TODO assign-",
+      swaccess: "rw",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "GENERIC_SCRATCH0",
+      desc: "Scratch",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "GENERIC_SCRATCH1",
+      desc: "Scratch",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "HOST_RST",
+      desc: "Host Domain reset -active high, inverted in HW-",
+      swaccess: "ro",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_RST",
+      desc: "Periph Domain reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_RST",
+      desc: "Safety Island reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_RST",
+      desc: "Security Island reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_RST",
+      desc: "PULP Cluster reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_RST",
+      desc: "Spatz Cluster reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_RST",
+      desc: "L2 reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_ISOLATE",
+      desc: "Periph Domain  AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_ISOLATE",
+      desc: "Safety Island AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_ISOLATE",
+      desc: "Security Island AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_ISOLATE",
+      desc: "PULP Cluster AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_ISOLATE",
+      desc: "Spatz Cluster AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_ISOLATE",
+      desc: "L2 AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_ISOLATE_STATUS",
+      desc: "Periph Domain AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_ISOLATE_STATUS",
+      desc: "Safety Island AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_ISOLATE_STATUS",
+      desc: "Security Island AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_ISOLATE_STATUS",
+      desc: "PULP Cluster AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_ISOLATE_STATUS",
+      desc: "Spatz Cluster AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_ISOLATE_STATUS",
+      desc: "L2 AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_CLK_EN",
+      desc: "Periph Domain clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_CLK_EN",
+      desc: "Safety Island clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_CLK_EN",
+      desc: "Security Island clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_CLK_EN",
+      desc: "PULP Cluster clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_CLK_EN",
+      desc: "Spatz Cluster clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_CLK_EN",
+      desc: "Shared L2 memory clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_CLK_SEL",
+      desc: "Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "2",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_CLK_SEL",
+      desc: "Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_CLK_SEL",
+      desc: "Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_CLK_SEL",
+      desc: "PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_CLK_SEL",
+      desc: "Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "L2_CLK_SEL",
+      desc: "L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "PERIPH_CLK_DIV_VALUE",
+      desc: "Periph Domain clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_CLK_DIV_VALUE",
+      desc: "Safety Island clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_CLK_DIV_VALUE",
+      desc: "Security Island clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_CLK_DIV_VALUE",
+      desc: "PULP Cluster clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_CLK_DIV_VALUE",
+      desc: "Spatz Cluster clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "L2_CLK_DIV_VALUE",
+      desc: "L2 Memory clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "HOST_FETCH_ENABLE",
+      desc: "Host Domain fetch enable",
+      swaccess: "ro",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_FETCH_ENABLE",
+      desc: "Safety Island fetch enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_FETCH_ENABLE",
+      desc: "Security Island fetch enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_FETCH_ENABLE",
+      desc: "PULP Cluster fetch enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_DEBUG_REQ",
+      desc: "Spatz Cluster debug req",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "HOST_BOOT_ADDR",
+      desc: "Host boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x1000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_BOOT_ADDR",
+      desc: "Safety Island boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_BOOT_ADDR",
+      desc: "Security Island boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_BOOT_ADDR",
+      desc: "PULP Cluster boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_BOOT_ADDR",
+      desc: "Spatz Cluster boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_BOOT_ENABLE",
+      desc: "PULP Cluster boot enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_BUSY",
+      desc: "Spatz Cluster busy",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_BUSY",
+      desc: "PULP Cluster busy",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_EOC",
+      desc: "PULP Cluster end of computation",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "ETH_RGMII_PHY_CLK_DIV_EN",
+      desc: "Ethernet RGMII PHY clock divider enable bit",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "ETH_RGMII_PHY_CLK_DIV_VALUE",
+      desc: "Ethernet RGMII PHY clock divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "100",
+      hwqe: "1",
+      fields: [
+        { bits: "19:0" }
+      ],
+    }
+
+    { name: "ETH_MDIO_CLK_DIV_EN",
+      desc: "Ethernet MDIO clock divider enable bit",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "ETH_MDIO_CLK_DIV_VALUE",
+      desc: "Ethernet MDIO clock divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "100",
+      hwqe: "1",
+      fields: [
+        { bits: "19:0" }
+      ],
+    }
+  ],
+}
diff --git a/docs/um/ip/carfield_regs/doc/carfield_regs.md b/docs/um/ip/carfield_regs/doc/carfield_regs.md
new file mode 100644
index 00000000..d4e1fa9e
--- /dev/null
+++ b/docs/um/ip/carfield_regs/doc/carfield_regs.md
@@ -0,0 +1,1126 @@
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                            |
+|:-----------------------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------|
+| carfield.[`VERSION0`](#version0)                                             | 0x0      |        4 | Cheshire sha256 commit                                                 |
+| carfield.[`VERSION1`](#version1)                                             | 0x4      |        4 | Safety Island sha256 commit                                            |
+| carfield.[`VERSION2`](#version2)                                             | 0x8      |        4 | Security Island sha256 commit                                          |
+| carfield.[`VERSION3`](#version3)                                             | 0xc      |        4 | PULP Cluster sha256 commit                                             |
+| carfield.[`VERSION4`](#version4)                                             | 0x10     |        4 | Spatz CLuster sha256 commit                                            |
+| carfield.[`JEDEC_IDCODE`](#jedec_idcode)                                     | 0x14     |        4 | JEDEC ID CODE -TODO assign-                                            |
+| carfield.[`GENERIC_SCRATCH0`](#generic_scratch0)                             | 0x18     |        4 | Scratch                                                                |
+| carfield.[`GENERIC_SCRATCH1`](#generic_scratch1)                             | 0x1c     |        4 | Scratch                                                                |
+| carfield.[`HOST_RST`](#host_rst)                                             | 0x20     |        4 | Host Domain reset -active high, inverted in HW-                        |
+| carfield.[`PERIPH_RST`](#periph_rst)                                         | 0x24     |        4 | Periph Domain reset -active high, inverted in HW-                      |
+| carfield.[`SAFETY_ISLAND_RST`](#safety_island_rst)                           | 0x28     |        4 | Safety Island reset -active high, inverted in HW-                      |
+| carfield.[`SECURITY_ISLAND_RST`](#security_island_rst)                       | 0x2c     |        4 | Security Island reset -active high, inverted in HW-                    |
+| carfield.[`PULP_CLUSTER_RST`](#pulp_cluster_rst)                             | 0x30     |        4 | PULP Cluster reset -active high, inverted in HW-                       |
+| carfield.[`SPATZ_CLUSTER_RST`](#spatz_cluster_rst)                           | 0x34     |        4 | Spatz Cluster reset -active high, inverted in HW-                      |
+| carfield.[`L2_RST`](#l2_rst)                                                 | 0x38     |        4 | L2 reset -active high, inverted in HW-                                 |
+| carfield.[`PERIPH_ISOLATE`](#periph_isolate)                                 | 0x3c     |        4 | Periph Domain  AXI isolate                                             |
+| carfield.[`SAFETY_ISLAND_ISOLATE`](#safety_island_isolate)                   | 0x40     |        4 | Safety Island AXI isolate                                              |
+| carfield.[`SECURITY_ISLAND_ISOLATE`](#security_island_isolate)               | 0x44     |        4 | Security Island AXI isolate                                            |
+| carfield.[`PULP_CLUSTER_ISOLATE`](#pulp_cluster_isolate)                     | 0x48     |        4 | PULP Cluster AXI isolate                                               |
+| carfield.[`SPATZ_CLUSTER_ISOLATE`](#spatz_cluster_isolate)                   | 0x4c     |        4 | Spatz Cluster AXI isolate                                              |
+| carfield.[`L2_ISOLATE`](#l2_isolate)                                         | 0x50     |        4 | L2 AXI isolate                                                         |
+| carfield.[`PERIPH_ISOLATE_STATUS`](#periph_isolate_status)                   | 0x54     |        4 | Periph Domain AXI isolate status                                       |
+| carfield.[`SAFETY_ISLAND_ISOLATE_STATUS`](#safety_island_isolate_status)     | 0x58     |        4 | Safety Island AXI isolate status                                       |
+| carfield.[`SECURITY_ISLAND_ISOLATE_STATUS`](#security_island_isolate_status) | 0x5c     |        4 | Security Island AXI isolate status                                     |
+| carfield.[`PULP_CLUSTER_ISOLATE_STATUS`](#pulp_cluster_isolate_status)       | 0x60     |        4 | PULP Cluster AXI isolate status                                        |
+| carfield.[`SPATZ_CLUSTER_ISOLATE_STATUS`](#spatz_cluster_isolate_status)     | 0x64     |        4 | Spatz Cluster AXI isolate status                                       |
+| carfield.[`L2_ISOLATE_STATUS`](#l2_isolate_status)                           | 0x68     |        4 | L2 AXI isolate status                                                  |
+| carfield.[`PERIPH_CLK_EN`](#periph_clk_en)                                   | 0x6c     |        4 | Periph Domain clk gate enable                                          |
+| carfield.[`SAFETY_ISLAND_CLK_EN`](#safety_island_clk_en)                     | 0x70     |        4 | Safety Island clk gate enable                                          |
+| carfield.[`SECURITY_ISLAND_CLK_EN`](#security_island_clk_en)                 | 0x74     |        4 | Security Island clk gate enable                                        |
+| carfield.[`PULP_CLUSTER_CLK_EN`](#pulp_cluster_clk_en)                       | 0x78     |        4 | PULP Cluster clk gate enable                                           |
+| carfield.[`SPATZ_CLUSTER_CLK_EN`](#spatz_cluster_clk_en)                     | 0x7c     |        4 | Spatz Cluster clk gate enable                                          |
+| carfield.[`L2_CLK_EN`](#l2_clk_en)                                           | 0x80     |        4 | Shared L2 memory clk gate enable                                       |
+| carfield.[`PERIPH_CLK_SEL`](#periph_clk_sel)                                 | 0x84     |        4 | Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SAFETY_ISLAND_CLK_SEL`](#safety_island_clk_sel)                   | 0x88     |        4 | Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`SECURITY_ISLAND_CLK_SEL`](#security_island_clk_sel)               | 0x8c     |        4 | Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) |
+| carfield.[`PULP_CLUSTER_CLK_SEL`](#pulp_cluster_clk_sel)                     | 0x90     |        4 | PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)    |
+| carfield.[`SPATZ_CLUSTER_CLK_SEL`](#spatz_cluster_clk_sel)                   | 0x94     |        4 | Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)   |
+| carfield.[`L2_CLK_SEL`](#l2_clk_sel)                                         | 0x98     |        4 | L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)       |
+| carfield.[`PERIPH_CLK_DIV_VALUE`](#periph_clk_div_value)                     | 0x9c     |        4 | Periph Domain clk divider value                                        |
+| carfield.[`SAFETY_ISLAND_CLK_DIV_VALUE`](#safety_island_clk_div_value)       | 0xa0     |        4 | Safety Island clk divider value                                        |
+| carfield.[`SECURITY_ISLAND_CLK_DIV_VALUE`](#security_island_clk_div_value)   | 0xa4     |        4 | Security Island clk divider value                                      |
+| carfield.[`PULP_CLUSTER_CLK_DIV_VALUE`](#pulp_cluster_clk_div_value)         | 0xa8     |        4 | PULP Cluster clk divider value                                         |
+| carfield.[`SPATZ_CLUSTER_CLK_DIV_VALUE`](#spatz_cluster_clk_div_value)       | 0xac     |        4 | Spatz Cluster clk divider value                                        |
+| carfield.[`L2_CLK_DIV_VALUE`](#l2_clk_div_value)                             | 0xb0     |        4 | L2 Memory clk divider value                                            |
+| carfield.[`HOST_FETCH_ENABLE`](#host_fetch_enable)                           | 0xb4     |        4 | Host Domain fetch enable                                               |
+| carfield.[`SAFETY_ISLAND_FETCH_ENABLE`](#safety_island_fetch_enable)         | 0xb8     |        4 | Safety Island fetch enable                                             |
+| carfield.[`SECURITY_ISLAND_FETCH_ENABLE`](#security_island_fetch_enable)     | 0xbc     |        4 | Security Island fetch enable                                           |
+| carfield.[`PULP_CLUSTER_FETCH_ENABLE`](#pulp_cluster_fetch_enable)           | 0xc0     |        4 | PULP Cluster fetch enable                                              |
+| carfield.[`SPATZ_CLUSTER_DEBUG_REQ`](#spatz_cluster_debug_req)               | 0xc4     |        4 | Spatz Cluster debug req                                                |
+| carfield.[`HOST_BOOT_ADDR`](#host_boot_addr)                                 | 0xc8     |        4 | Host boot address                                                      |
+| carfield.[`SAFETY_ISLAND_BOOT_ADDR`](#safety_island_boot_addr)               | 0xcc     |        4 | Safety Island boot address                                             |
+| carfield.[`SECURITY_ISLAND_BOOT_ADDR`](#security_island_boot_addr)           | 0xd0     |        4 | Security Island boot address                                           |
+| carfield.[`PULP_CLUSTER_BOOT_ADDR`](#pulp_cluster_boot_addr)                 | 0xd4     |        4 | PULP Cluster boot address                                              |
+| carfield.[`SPATZ_CLUSTER_BOOT_ADDR`](#spatz_cluster_boot_addr)               | 0xd8     |        4 | Spatz Cluster boot address                                             |
+| carfield.[`PULP_CLUSTER_BOOT_ENABLE`](#pulp_cluster_boot_enable)             | 0xdc     |        4 | PULP Cluster boot enable                                               |
+| carfield.[`SPATZ_CLUSTER_BUSY`](#spatz_cluster_busy)                         | 0xe0     |        4 | Spatz Cluster busy                                                     |
+| carfield.[`PULP_CLUSTER_BUSY`](#pulp_cluster_busy)                           | 0xe4     |        4 | PULP Cluster busy                                                      |
+| carfield.[`PULP_CLUSTER_EOC`](#pulp_cluster_eoc)                             | 0xe8     |        4 | PULP Cluster end of computation                                        |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_EN`](#eth_rgmii_phy_clk_div_en)             | 0xec     |        4 | Ethernet RGMII PHY clock divider enable bit                            |
+| carfield.[`ETH_RGMII_PHY_CLK_DIV_VALUE`](#eth_rgmii_phy_clk_div_value)       | 0xf0     |        4 | Ethernet RGMII PHY clock divider value                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_EN`](#eth_mdio_clk_div_en)                       | 0xf4     |        4 | Ethernet MDIO clock divider enable bit                                 |
+| carfield.[`ETH_MDIO_CLK_DIV_VALUE`](#eth_mdio_clk_div_value)                 | 0xf8     |        4 | Ethernet MDIO clock divider value                                      |
+
+## VERSION0
+Cheshire sha256 commit
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION0", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION0 |               |
+
+## VERSION1
+Safety Island sha256 commit
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION1", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION1 |               |
+
+## VERSION2
+Security Island sha256 commit
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION2", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION2 |               |
+
+## VERSION3
+PULP Cluster sha256 commit
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION3", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION3 |               |
+
+## VERSION4
+Spatz CLuster sha256 commit
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VERSION4", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:0  |   ro   |   0x0   | VERSION4 |               |
+
+## JEDEC_IDCODE
+JEDEC ID CODE -TODO assign-
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "JEDEC_IDCODE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description   |
+|:------:|:------:|:-------:|:-------------|:--------------|
+|  31:0  |   rw   |   0x0   | JEDEC_IDCODE |               |
+
+## GENERIC_SCRATCH0
+Scratch
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH0 |               |
+
+## GENERIC_SCRATCH1
+Scratch
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "GENERIC_SCRATCH1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:0  |   rw   |   0x0   | GENERIC_SCRATCH1 |               |
+
+## HOST_RST
+Host Domain reset -active high, inverted in HW-
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_RST", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:1  |        |         |          | Reserved      |
+|   0    |   ro   |   0x0   | HOST_RST |               |
+
+## PERIPH_RST
+Periph Domain reset -active high, inverted in HW-
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_RST |               |
+
+## SAFETY_ISLAND_RST
+Safety Island reset -active high, inverted in HW-
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_RST |               |
+
+## SECURITY_ISLAND_RST
+Security Island reset -active high, inverted in HW-
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_RST |               |
+
+## PULP_CLUSTER_RST
+PULP Cluster reset -active high, inverted in HW-
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_RST |               |
+
+## SPATZ_CLUSTER_RST
+Spatz Cluster reset -active high, inverted in HW-
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_RST |               |
+
+## L2_RST
+L2 reset -active high, inverted in HW-
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:1  |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | L2_RST |               |
+
+## PERIPH_ISOLATE
+Periph Domain  AXI isolate
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:1  |        |         |                | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE |               |
+
+## SAFETY_ISLAND_ISOLATE
+Safety Island AXI isolate
+- Offset: `0x40`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SAFETY_ISLAND_ISOLATE |               |
+
+## SECURITY_ISLAND_ISOLATE
+Security Island AXI isolate
+- Offset: `0x44`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   rw   |   0x1   | SECURITY_ISLAND_ISOLATE |               |
+
+## PULP_CLUSTER_ISOLATE
+PULP Cluster AXI isolate
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x1   | PULP_CLUSTER_ISOLATE |               |
+
+## SPATZ_CLUSTER_ISOLATE
+Spatz Cluster AXI isolate
+- Offset: `0x4c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x1   | SPATZ_CLUSTER_ISOLATE |               |
+
+## L2_ISOLATE
+L2 AXI isolate
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:1  |        |         |            | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE |               |
+
+## PERIPH_ISOLATE_STATUS
+Periph Domain AXI isolate status
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:1  |        |         |                       | Reserved      |
+|   0    |   rw   |   0x0   | PERIPH_ISOLATE_STATUS |               |
+
+## SAFETY_ISLAND_ISOLATE_STATUS
+Safety Island AXI isolate status
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_ISOLATE_STATUS |               |
+
+## SECURITY_ISLAND_ISOLATE_STATUS
+Security Island AXI isolate status
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                           | Description   |
+|:------:|:------:|:-------:|:-------------------------------|:--------------|
+|  31:1  |        |         |                                | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_ISOLATE_STATUS |               |
+
+## PULP_CLUSTER_ISOLATE_STATUS
+PULP Cluster AXI isolate status
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+|  31:1  |        |         |                             | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_ISOLATE_STATUS |               |
+
+## SPATZ_CLUSTER_ISOLATE_STATUS
+Spatz Cluster AXI isolate status
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_ISOLATE_STATUS |               |
+
+## L2_ISOLATE_STATUS
+L2 AXI isolate status
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_ISOLATE_STATUS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   rw   |   0x0   | L2_ISOLATE_STATUS |               |
+
+## PERIPH_CLK_EN
+Periph Domain clk gate enable
+- Offset: `0x6c`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x1   | PERIPH_CLK_EN |               |
+
+## SAFETY_ISLAND_CLK_EN
+Safety Island clk gate enable
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_CLK_EN |               |
+
+## SECURITY_ISLAND_CLK_EN
+Security Island clk gate enable
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+|  31:1  |        |         |                        | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_CLK_EN |               |
+
+## PULP_CLUSTER_CLK_EN
+PULP Cluster clk gate enable
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_CLK_EN |               |
+
+## SPATZ_CLUSTER_CLK_EN
+Spatz Cluster clk gate enable
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:1  |        |         |                      | Reserved      |
+|   0    |   rw   |   0x0   | SPATZ_CLUSTER_CLK_EN |               |
+
+## L2_CLK_EN
+Shared L2 memory clk gate enable
+- Offset: `0x80`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:1  |        |         |           | Reserved      |
+|   0    |   rw   |   0x1   | L2_CLK_EN |               |
+
+## PERIPH_CLK_SEL
+Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x84`
+- Reset default: `0x2`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:2  |        |         |                | Reserved      |
+|  1:0   |   rw   |   0x2   | PERIPH_CLK_SEL |               |
+
+## SAFETY_ISLAND_CLK_SEL
+Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x88`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SAFETY_ISLAND_CLK_SEL |               |
+
+## SECURITY_ISLAND_CLK_SEL
+Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x8c`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x1   | SECURITY_ISLAND_CLK_SEL |               |
+
+## PULP_CLUSTER_CLK_SEL
+PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x90`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:2  |        |         |                      | Reserved      |
+|  1:0   |   rw   |   0x1   | PULP_CLUSTER_CLK_SEL |               |
+
+## SPATZ_CLUSTER_CLK_SEL
+Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x94`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description   |
+|:------:|:------:|:-------:|:----------------------|:--------------|
+|  31:2  |        |         |                       | Reserved      |
+|  1:0   |   rw   |   0x1   | SPATZ_CLUSTER_CLK_SEL |               |
+
+## L2_CLK_SEL
+L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)
+- Offset: `0x98`
+- Reset default: `0x1`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_SEL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:2  |        |         |            | Reserved      |
+|  1:0   |   rw   |   0x1   | L2_CLK_SEL |               |
+
+## PERIPH_CLK_DIV_VALUE
+Periph Domain clk divider value
+- Offset: `0x9c`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERIPH_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+| 31:24  |        |         |                      | Reserved      |
+|  23:0  |   rw   |   0x1   | PERIPH_CLK_DIV_VALUE |               |
+
+## SAFETY_ISLAND_CLK_DIV_VALUE
+Safety Island clk divider value
+- Offset: `0xa0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SAFETY_ISLAND_CLK_DIV_VALUE |               |
+
+## SECURITY_ISLAND_CLK_DIV_VALUE
+Security Island clk divider value
+- Offset: `0xa4`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          | Description   |
+|:------:|:------:|:-------:|:------------------------------|:--------------|
+| 31:24  |        |         |                               | Reserved      |
+|  23:0  |   rw   |   0x1   | SECURITY_ISLAND_CLK_DIV_VALUE |               |
+
+## PULP_CLUSTER_CLK_DIV_VALUE
+PULP Cluster clk divider value
+- Offset: `0xa8`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+| 31:24  |        |         |                            | Reserved      |
+|  23:0  |   rw   |   0x1   | PULP_CLUSTER_CLK_DIV_VALUE |               |
+
+## SPATZ_CLUSTER_CLK_DIV_VALUE
+Spatz Cluster clk divider value
+- Offset: `0xac`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:24  |        |         |                             | Reserved      |
+|  23:0  |   rw   |   0x1   | SPATZ_CLUSTER_CLK_DIV_VALUE |               |
+
+## L2_CLK_DIV_VALUE
+L2 Memory clk divider value
+- Offset: `0xb0`
+- Reset default: `0x1`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L2_CLK_DIV_VALUE", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:24  |        |         |                  | Reserved      |
+|  23:0  |   rw   |   0x1   | L2_CLK_DIV_VALUE |               |
+
+## HOST_FETCH_ENABLE
+Host Domain fetch enable
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_FETCH_ENABLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | HOST_FETCH_ENABLE |               |
+
+## SAFETY_ISLAND_FETCH_ENABLE
+Safety Island fetch enable
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       | Description   |
+|:------:|:------:|:-------:|:---------------------------|:--------------|
+|  31:1  |        |         |                            | Reserved      |
+|   0    |   rw   |   0x0   | SAFETY_ISLAND_FETCH_ENABLE |               |
+
+## SECURITY_ISLAND_FETCH_ENABLE
+Security Island fetch enable
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         | Description   |
+|:------:|:------:|:-------:|:-----------------------------|:--------------|
+|  31:1  |        |         |                              | Reserved      |
+|   0    |   rw   |   0x0   | SECURITY_ISLAND_FETCH_ENABLE |               |
+
+## PULP_CLUSTER_FETCH_ENABLE
+PULP Cluster fetch enable
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_FETCH_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|  31:1  |        |         |                           | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_FETCH_ENABLE |               |
+
+## SPATZ_CLUSTER_DEBUG_REQ
+Spatz Cluster debug req
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_DEBUG_REQ", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:2  |        |         |                         | Reserved      |
+|  1:0   |   rw   |   0x0   | SPATZ_CLUSTER_DEBUG_REQ |               |
+
+## HOST_BOOT_ADDR
+Host boot address
+- Offset: `0xc8`
+- Reset default: `0x1000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description   |
+|:------:|:------:|:-------:|:---------------|:--------------|
+|  31:0  |   rw   | 0x1000  | HOST_BOOT_ADDR |               |
+
+## SAFETY_ISLAND_BOOT_ADDR
+Safety Island boot address
+- Offset: `0xcc`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SAFETY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SAFETY_ISLAND_BOOT_ADDR |               |
+
+## SECURITY_ISLAND_BOOT_ADDR
+Security Island boot address
+- Offset: `0xd0`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SECURITY_ISLAND_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                      | Description   |
+|:------:|:------:|:----------:|:--------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SECURITY_ISLAND_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ADDR
+PULP Cluster boot address
+- Offset: `0xd4`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                   | Description   |
+|:------:|:------:|:----------:|:-----------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | PULP_CLUSTER_BOOT_ADDR |               |
+
+## SPATZ_CLUSTER_BOOT_ADDR
+Spatz Cluster boot address
+- Offset: `0xd8`
+- Reset default: `0x70000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BOOT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name                    | Description   |
+|:------:|:------:|:----------:|:------------------------|:--------------|
+|  31:0  |   rw   | 0x70000000 | SPATZ_CLUSTER_BOOT_ADDR |               |
+
+## PULP_CLUSTER_BOOT_ENABLE
+PULP Cluster boot enable
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BOOT_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x0   | PULP_CLUSTER_BOOT_ENABLE |               |
+
+## SPATZ_CLUSTER_BUSY
+Spatz Cluster busy
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:1  |        |         |                    | Reserved      |
+|   0    |   ro   |   0x0   | SPATZ_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_BUSY
+PULP Cluster busy
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_BUSY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:1  |        |         |                   | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_BUSY |               |
+
+## PULP_CLUSTER_EOC
+PULP Cluster end of computation
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PULP_CLUSTER_EOC", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:1  |        |         |                  | Reserved      |
+|   0    |   ro   |   0x0   | PULP_CLUSTER_EOC |               |
+
+## ETH_RGMII_PHY_CLK_DIV_EN
+Ethernet RGMII PHY clock divider enable bit
+- Offset: `0xec`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description   |
+|:------:|:------:|:-------:|:-------------------------|:--------------|
+|  31:1  |        |         |                          | Reserved      |
+|   0    |   rw   |   0x1   | ETH_RGMII_PHY_CLK_DIV_EN |               |
+
+## ETH_RGMII_PHY_CLK_DIV_VALUE
+Ethernet RGMII PHY clock divider value
+- Offset: `0xf0`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_RGMII_PHY_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        | Description   |
+|:------:|:------:|:-------:|:----------------------------|:--------------|
+| 31:20  |        |         |                             | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_RGMII_PHY_CLK_DIV_VALUE |               |
+
+## ETH_MDIO_CLK_DIV_EN
+Ethernet MDIO clock divider enable bit
+- Offset: `0xf4`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:1  |        |         |                     | Reserved      |
+|   0    |   rw   |   0x1   | ETH_MDIO_CLK_DIV_EN |               |
+
+## ETH_MDIO_CLK_DIV_VALUE
+Ethernet MDIO clock divider value
+- Offset: `0xf8`
+- Reset default: `0x64`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ETH_MDIO_CLK_DIV_VALUE", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:20  |        |         |                        | Reserved      |
+|  19:0  |   rw   |  0x64   | ETH_MDIO_CLK_DIV_VALUE |               |
+
diff --git a/docs/um/ip/clic/data/clicint.hjson b/docs/um/ip/clic/data/clicint.hjson
new file mode 100644
index 00000000..72fed33d
--- /dev/null
+++ b/docs/um/ip/clic/data/clicint.hjson
@@ -0,0 +1,40 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+// CLIC interrupt register
+{
+  name: "CLICINT",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "CLICINT",
+      desc: "CLIC interrupt pending, enable, attribute and control",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:24", name: "CTL", desc: "interrupt control for interrupt" },
+        { bits: "23:22", name: "ATTR_MODE", desc: "privilege mode of this interrupt", resval: 3},
+        //{ bits: "21:19", name: "reserved" },
+        { bits: "18:17", name: "ATTR_TRIG", desc: "specify trigger type for this interrupt" },
+        { bits: "16", name: "ATTR_SHV", desc: "enable hardware vectoring for this interrupt" },
+
+        { bits: "8", name: "IE", desc: "interrupt enable for interrupt" },
+
+        { bits: "0", name: "IP", desc: "interrupt pending for interrupt", hwaccess: "hrw" },
+      ],
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/clic/data/clicint_doc.hjson b/docs/um/ip/clic/data/clicint_doc.hjson
new file mode 100644
index 00000000..c7b75aba
--- /dev/null
+++ b/docs/um/ip/clic/data/clicint_doc.hjson
@@ -0,0 +1,45 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+// CLIC interrupt register
+{
+  name: "CLICINT",
+  cip_id: "36",
+  version: "3.0.0", //3.0.0-for-carfield 
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "CLICINT",
+      desc: "CLIC interrupt pending, enable, attribute and control",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:24", name: "CTL", desc: "interrupt control for interrupt" },
+        { bits: "23:22", name: "ATTR_MODE", desc: "privilege mode of this interrupt", resval: 3},
+        //{ bits: "21:19", name: "reserved" },
+        { bits: "18:17", name: "ATTR_TRIG", desc: "specify trigger type for this interrupt" },
+        { bits: "16", name: "ATTR_SHV", desc: "enable hardware vectoring for this interrupt" },
+
+        { bits: "8", name: "IE", desc: "interrupt enable for interrupt" },
+
+        { bits: "0", name: "IP", desc: "interrupt pending for interrupt", hwaccess: "hrw" },
+      ],
+    }
+  ]
+}
diff --git a/docs/um/ip/clic/data/clictv.hjson b/docs/um/ip/clic/data/clictv.hjson
new file mode 100644
index 00000000..6f4b8c9f
--- /dev/null
+++ b/docs/um/ip/clic/data/clictv.hjson
@@ -0,0 +1,40 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+// CLIC virtual supervisor interrupt register
+{
+  name: "CLICINTV",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "CLICINTV",
+      desc: "CLIC interrupt virtualization",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:26", name: "VSID3", desc: "interrupt VS id" },
+        { bits: "24", name: "V3", desc: "interrupt delegated to VS-mode"},
+        { bits: "23:18", name: "VSID2", desc: "interrupt VS id" },
+        { bits: "16", name: "V2", desc: "interrupt delegated to VS-mode"},
+        { bits: "15:10", name: "VSID1", desc: "interrupt VS id" },
+        { bits: "8", name: "V1", desc: "interrupt delegated to VS-mode"},
+        { bits: "7:2", name: "VSID0", desc: "interrupt VS id" },
+        { bits: "0", name: "V0", desc: "interrupt delegated to VS-mode"},
+      ],
+    }
+  ]
+}
diff --git a/docs/um/ip/clic/data/clictv_doc.hjson b/docs/um/ip/clic/data/clictv_doc.hjson
new file mode 100644
index 00000000..2f5eb771
--- /dev/null
+++ b/docs/um/ip/clic/data/clictv_doc.hjson
@@ -0,0 +1,42 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+// CLIC virtual supervisor interrupt register
+{
+  name: "CLICINTV",
+  cip_id: "36",
+  version: "3.0.0", //3.0.0-for-carfield
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32",
+  registers: [
+    { name: "CLICINTV",
+      desc: "CLIC interrupt virtualization",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:26", name: "VSID3", desc: "interrupt VS id" },
+        { bits: "24", name: "V3", desc: "interrupt delegated to VS-mode"},
+        { bits: "23:18", name: "VSID2", desc: "interrupt VS id" },
+        { bits: "16", name: "V2", desc: "interrupt delegated to VS-mode"},
+        { bits: "15:10", name: "VSID1", desc: "interrupt VS id" },
+        { bits: "8", name: "V1", desc: "interrupt delegated to VS-mode"},
+        { bits: "7:2", name: "VSID0", desc: "interrupt VS id" },
+        { bits: "0", name: "V0", desc: "interrupt delegated to VS-mode"},
+      ],
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/clic/data/clicvs.hjson b/docs/um/ip/clic/data/clicvs.hjson
new file mode 100644
index 00000000..8cd2c357
--- /dev/null
+++ b/docs/um/ip/clic/data/clicvs.hjson
@@ -0,0 +1,36 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+// CLIC virtual supervisor configuration register
+{
+  name: "CLICVS",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "vsprio",
+      desc: "CLIC virtual supervisor priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "24", name: "prio3", desc: "VS3 priority" },
+        { bits: "16", name: "prio2", desc: "VS2 priority" },
+        { bits:  "8", name: "prio1", desc: "VS1 priority" },
+        { bits:  "0", name: "prio0", desc: "VS0 priority" },
+      ],
+    }
+  ]
+}
diff --git a/docs/um/ip/clic/data/clicvs_doc.hjson b/docs/um/ip/clic/data/clicvs_doc.hjson
new file mode 100644
index 00000000..39420d5f
--- /dev/null
+++ b/docs/um/ip/clic/data/clicvs_doc.hjson
@@ -0,0 +1,40 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+// CLIC virtual supervisor configuration register
+{
+  name: "CLICVS",
+  cip_id: "36",
+  version: "3.0.0", //3.0.0-for-carfield
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "vsprio",
+      desc: "CLIC virtual supervisor priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "24", name: "prio3", desc: "VS3 priority" },
+        { bits: "16", name: "prio2", desc: "VS2 priority" },
+        { bits:  "8", name: "prio1", desc: "VS1 priority" },
+        { bits:  "0", name: "prio0", desc: "VS0 priority" },
+      ],
+    }
+  ]
+}
diff --git a/docs/um/ip/clic/data/mclic.hjson b/docs/um/ip/clic/data/mclic.hjson
new file mode 100644
index 00000000..a136919d
--- /dev/null
+++ b/docs/um/ip/clic/data/mclic.hjson
@@ -0,0 +1,47 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+# CLIC m-mode registers
+{
+  name: "MCLIC",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "MCLICCFG",
+      desc: "CLIC configuration",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:28", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none" },  # workaround for full 32-bit access
+        { bits: "27:24", name: "unlbits", desc: "number of privilege mode bits in user mode" },
+        //{ bits: "23:20", name: "reserved" },
+        { bits: "19:16", name: "snlbits", desc: "number of privilege mode bits in supervisor mode" },
+        //{ bits: "15:6", name: "reserved" },
+        { bits: "5:4", name: "nmbits", desc: "number of privilege mode bits" },
+        { bits: "3:0", name: "mnlbits", desc: "number of interrupt level bits in machine mode" },
+      ],
+    },
+    { name: "CLICMNXTICONF",
+      desc: "CLIC enable mnxti irq forwarding logic",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0" }
+      ],
+    },
+  ]
+}
diff --git a/docs/um/ip/clic/data/mclic_doc.hjson b/docs/um/ip/clic/data/mclic_doc.hjson
new file mode 100644
index 00000000..272de2cd
--- /dev/null
+++ b/docs/um/ip/clic/data/mclic_doc.hjson
@@ -0,0 +1,51 @@
+
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// SPDX-License-Identifier: Apache-2.0
+
+# CLIC m-mode registers
+{
+  name: "MCLIC",
+  cip_id: "36",
+  version: "3.0.0", //3.0.0-for-carfield
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "MCLICCFG",
+      desc: "CLIC configuration",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:28", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none" },  # workaround for full 32-bit access
+        { bits: "27:24", name: "unlbits", desc: "number of privilege mode bits in user mode" },
+        //{ bits: "23:20", name: "reserved" },
+        { bits: "19:16", name: "snlbits", desc: "number of privilege mode bits in supervisor mode" },
+        //{ bits: "15:6", name: "reserved" },
+        { bits: "5:4", name: "nmbits", desc: "number of privilege mode bits" },
+        { bits: "3:0", name: "mnlbits", desc: "number of interrupt level bits in machine mode" },
+      ],
+    },
+    { name: "CLICMNXTICONF",
+      desc: "CLIC enable mnxti irq forwarding logic",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0" }
+      ],
+    },
+  ]
+}
diff --git a/docs/um/ip/clic/doc/clicint_registers.md b/docs/um/ip/clic/doc/clicint_registers.md
new file mode 100644
index 00000000..063ddf9b
--- /dev/null
+++ b/docs/um/ip/clic/doc/clicint_registers.md
@@ -0,0 +1,30 @@
+## Summary
+
+| Name                          | Offset   |   Length | Description                                           |
+|:------------------------------|:---------|---------:|:------------------------------------------------------|
+| CLICINT.[`CLICINT`](#clicint) | 0x0      |        4 | CLIC interrupt pending, enable, attribute and control |
+
+## CLICINT
+CLIC interrupt pending, enable, attribute and control
+- Offset: `0x0`
+- Reset default: `0xc00000`
+- Reset mask: `0xffc70101`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "IE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "ATTR_SHV", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ATTR_TRIG", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "ATTR_MODE", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "CTL", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                  |
+|:------:|:------:|:-------:|:----------|:---------------------------------------------|
+| 31:24  |   rw   |   0x0   | CTL       | interrupt control for interrupt              |
+| 23:22  |   rw   |   0x3   | ATTR_MODE | privilege mode of this interrupt             |
+| 21:19  |        |         |           | Reserved                                     |
+| 18:17  |   rw   |   0x0   | ATTR_TRIG | specify trigger type for this interrupt      |
+|   16   |   rw   |   0x0   | ATTR_SHV  | enable hardware vectoring for this interrupt |
+|  15:9  |        |         |           | Reserved                                     |
+|   8    |   rw   |   0x0   | IE        | interrupt enable for interrupt               |
+|  7:1   |        |         |           | Reserved                                     |
+|   0    |   rw   |   0x0   | IP        | interrupt pending for interrupt              |
+
diff --git a/docs/um/ip/clic/doc/clictv_registers.md b/docs/um/ip/clic/doc/clictv_registers.md
new file mode 100644
index 00000000..08e3109e
--- /dev/null
+++ b/docs/um/ip/clic/doc/clictv_registers.md
@@ -0,0 +1,33 @@
+## Summary
+
+| Name                             | Offset   |   Length | Description                   |
+|:---------------------------------|:---------|---------:|:------------------------------|
+| CLICINTV.[`CLICINTV`](#clicintv) | 0x0      |        4 | CLIC interrupt virtualization |
+
+## CLICINTV
+CLIC interrupt virtualization
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xfdfdfdfd`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "V0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID0", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID1", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID2", "bits": 6, "attr": ["rw"], "rotate": 0}, {"name": "V3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "VSID3", "bits": 6, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:26  |   rw   |   0x0   | VSID3  | interrupt VS id                |
+|   25   |        |         |        | Reserved                       |
+|   24   |   rw   |   0x0   | V3     | interrupt delegated to VS-mode |
+| 23:18  |   rw   |   0x0   | VSID2  | interrupt VS id                |
+|   17   |        |         |        | Reserved                       |
+|   16   |   rw   |   0x0   | V2     | interrupt delegated to VS-mode |
+| 15:10  |   rw   |   0x0   | VSID1  | interrupt VS id                |
+|   9    |        |         |        | Reserved                       |
+|   8    |   rw   |   0x0   | V1     | interrupt delegated to VS-mode |
+|  7:2   |   rw   |   0x0   | VSID0  | interrupt VS id                |
+|   1    |        |         |        | Reserved                       |
+|   0    |   rw   |   0x0   | V0     | interrupt delegated to VS-mode |
+
diff --git a/docs/um/ip/clic/doc/clicvs_registers.md b/docs/um/ip/clic/doc/clicvs_registers.md
new file mode 100644
index 00000000..f4c54193
--- /dev/null
+++ b/docs/um/ip/clic/doc/clicvs_registers.md
@@ -0,0 +1,29 @@
+## Summary
+
+| Name                       | Offset   |   Length | Description                      |
+|:---------------------------|:---------|---------:|:---------------------------------|
+| CLICVS.[`vsprio`](#vsprio) | 0x0      |        4 | CLIC virtual supervisor priority |
+
+## vsprio
+CLIC virtual supervisor priority
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1010101`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "prio0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "prio3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+| 31:25  |        |         |        | Reserved      |
+|   24   |   rw   |   0x0   | prio3  | VS3 priority  |
+| 23:17  |        |         |        | Reserved      |
+|   16   |   rw   |   0x0   | prio2  | VS2 priority  |
+|  15:9  |        |         |        | Reserved      |
+|   8    |   rw   |   0x0   | prio1  | VS1 priority  |
+|  7:1   |        |         |        | Reserved      |
+|   0    |   rw   |   0x0   | prio0  | VS0 priority  |
+
diff --git a/docs/um/ip/clic/doc/mclic_registers.md b/docs/um/ip/clic/doc/mclic_registers.md
new file mode 100644
index 00000000..8c70c34f
--- /dev/null
+++ b/docs/um/ip/clic/doc/mclic_registers.md
@@ -0,0 +1,46 @@
+## Summary
+
+| Name                                    | Offset   |   Length | Description                            |
+|:----------------------------------------|:---------|---------:|:---------------------------------------|
+| MCLIC.[`MCLICCFG`](#mcliccfg)           | 0x0      |        4 | CLIC configuration                     |
+| MCLIC.[`CLICMNXTICONF`](#clicmnxticonf) | 0x4      |        4 | CLIC enable mnxti irq forwarding logic |
+
+## MCLICCFG
+CLIC configuration
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xff0f003f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "mnlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "nmbits", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 10}, {"name": "snlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 4}, {"name": "unlbits", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 4, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                      |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------|
+| 31:28  |   ro   |   0x0   | reserved | reserved                                         |
+| 27:24  |   rw   |   0x0   | unlbits  | number of privilege mode bits in user mode       |
+| 23:20  |        |         |          | Reserved                                         |
+| 19:16  |   rw   |   0x0   | snlbits  | number of privilege mode bits in supervisor mode |
+|  15:6  |        |         |          | Reserved                                         |
+|  5:4   |   rw   |   0x0   | nmbits   | number of privilege mode bits                    |
+|  3:0   |   rw   |   0x0   | mnlbits  | number of interrupt level bits in machine mode   |
+
+## CLICMNXTICONF
+CLIC enable mnxti irq forwarding logic
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CLICMNXTICONF", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description   |
+|:------:|:------:|:-------:|:--------------|:--------------|
+|  31:1  |        |         |               | Reserved      |
+|   0    |   rw   |   0x0   | CLICMNXTICONF |               |
+
diff --git a/docs/um/ip/clint/data/clint.hjson b/docs/um/ip/clint/data/clint.hjson
new file mode 100644
index 00000000..6692b7cb
--- /dev/null
+++ b/docs/um/ip/clint/data/clint.hjson
@@ -0,0 +1,76 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+
+{
+  name: "CLINT",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: "32",
+  param_list: [
+    { name: "NumCores",
+      desc: "Number of cores",
+      type: "int",
+      default: "${cores}",
+      local: "true"
+    }
+  ],
+  registers: [
+    { multireg: {
+        name: "MSIP",
+        desc: "Machine Software Interrupt Pending ",
+        count: "NumCores",
+        cname: "MSIP",
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "0", name: "P", desc: "Machine Software Interrupt Pending" },
+          { bits: "31:1", name: "RSVD", desc: "Reserved", resval: "0", swaccess: "ro", hwaccess: "none" }
+        ]
+      }
+    },
+    { skipto: "0x4000" },
+% for i in range(cores):
+    {   name: "MTIMECMP_LOW${i}",
+        desc: "Machine Timer Compare",
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "31:0", name: "MTIMECMP_LOW", desc: "Machine Time Compare (Low) Core ${i}" }
+        ]
+    },
+    {
+        name: "MTIMECMP_HIGH${i}",
+        desc: "Machine Timer Compare",
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "31:0", name: "MTIMECMP_HIGH", desc: "Machine Time Compare (High) Core ${i}" }
+        ]
+    },
+% endfor
+    { skipto: "0xBFF8" },
+    {
+        name: "MTIME_LOW",
+        desc: "Timer Register Low",
+        swaccess: "rw",
+        hwaccess: "hrw",
+        fields: [
+          { bits: "31:0", name: "MTIME_LOW", desc: "Machine Time (Low)" }
+        ]
+    },
+    {
+        name: "MTIME_HIGH",
+        desc: "Timer Register High",
+        swaccess: "rw",
+        hwaccess: "hrw",
+        fields: [
+          { bits: "31:0", name: "MTIME_HIGH", desc: "Machine Time (High)" }
+        ]
+    },
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/clint/data/clint.hjson~ b/docs/um/ip/clint/data/clint.hjson~
new file mode 100644
index 00000000..e69de29b
diff --git a/docs/um/ip/clint/data/clint_Doc.hjson b/docs/um/ip/clint/data/clint_Doc.hjson
new file mode 100644
index 00000000..285ce1ac
--- /dev/null
+++ b/docs/um/ip/clint/data/clint_Doc.hjson
@@ -0,0 +1,97 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+
+{
+  name: "CLINT",
+  cip_id: "2",
+  version:            "0.2.0",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32",
+  param_list: [
+    { name: "NumCores",
+      desc: "Number of cores",
+      type: "int",
+      default: "2",
+      local: "true"
+    }
+  ],
+  registers: [
+    { multireg: {
+        name: "MSIP",
+        desc: "Machine Software Interrupt Pending",
+        count: "2",   // Number of cores
+        cname: "MSIP",
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "0", name: "P", desc: "Machine Software Interrupt Pending" },
+          { bits: "31:1", name: "RSVD", desc: "Reserved", resval: "0", swaccess: "ro", hwaccess: "none" }
+        ]
+      }
+    },
+    { skipto: "0x4000" },
+
+    // Core 0 MTIMECMP Registers
+    { name: "MTIMECMP_LOW0",
+      desc: "Machine Timer Compare for Core 0",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "MTIMECMP_LOW", desc: "Machine Time Compare (Low) Core 0" }
+      ]
+    },
+    { name: "MTIMECMP_HIGH0",
+      desc: "Machine Timer Compare for Core 0",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "MTIMECMP_HIGH", desc: "Machine Time Compare (High) Core 0" }
+      ]
+    },
+
+    // Core 1 MTIMECMP Registers
+    { name: "MTIMECMP_LOW1",
+      desc: "Machine Timer Compare for Core 1",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "MTIMECMP_LOW", desc: "Machine Time Compare (Low) Core 1" }
+      ]
+    },
+    { name: "MTIMECMP_HIGH1",
+      desc: "Machine Timer Compare for Core 1",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "MTIMECMP_HIGH", desc: "Machine Time Compare (High) Core 1" }
+      ]
+    },
+
+    { skipto: "0xBFF8" },
+
+    { name: "MTIME_LOW",
+      desc: "Timer Register Low",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "31:0", name: "MTIME_LOW", desc: "Machine Time (Low)" }
+      ]
+    },
+    { name: "MTIME_HIGH",
+      desc: "Timer Register High",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "31:0", name: "MTIME_HIGH", desc: "Machine Time (High)" }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/clint/doc/registers.md b/docs/um/ip/clint/doc/registers.md
new file mode 100644
index 00000000..78fe425d
--- /dev/null
+++ b/docs/um/ip/clint/doc/registers.md
@@ -0,0 +1,133 @@
+## Summary
+
+| Name                                      | Offset   |   Length | Description                        |
+|:------------------------------------------|:---------|---------:|:-----------------------------------|
+| CLINT.[`MSIP_0`](#msip)                   | 0x0      |        4 | Machine Software Interrupt Pending |
+| CLINT.[`MSIP_1`](#msip)                   | 0x4      |        4 | Machine Software Interrupt Pending |
+| CLINT.[`MTIMECMP_LOW0`](#mtimecmp_low0)   | 0x4000   |        4 | Machine Timer Compare for Core 0   |
+| CLINT.[`MTIMECMP_HIGH0`](#mtimecmp_high0) | 0x4004   |        4 | Machine Timer Compare for Core 0   |
+| CLINT.[`MTIMECMP_LOW1`](#mtimecmp_low1)   | 0x4008   |        4 | Machine Timer Compare for Core 1   |
+| CLINT.[`MTIMECMP_HIGH1`](#mtimecmp_high1) | 0x400c   |        4 | Machine Timer Compare for Core 1   |
+| CLINT.[`MTIME_LOW`](#mtime_low)           | 0xbff8   |        4 | Timer Register Low                 |
+| CLINT.[`MTIME_HIGH`](#mtime_high)         | 0xbffc   |        4 | Timer Register High                |
+
+## MSIP
+Machine Software Interrupt Pending
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name   | Offset   |
+|:-------|:---------|
+| MSIP_0 | 0x0      |
+| MSIP_1 | 0x4      |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "P", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RSVD", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:1  |   ro   |   0x0   | RSVD   | Reserved                           |
+|   0    |   rw   |   0x0   | P      | Machine Software Interrupt Pending |
+
+## MTIMECMP_LOW0
+Machine Timer Compare for Core 0
+- Offset: `0x4000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                       |
+|:------:|:------:|:-------:|:-------------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_LOW | Machine Time Compare (Low) Core 0 |
+
+## MTIMECMP_HIGH0
+Machine Timer Compare for Core 0
+- Offset: `0x4004`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                        |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_HIGH | Machine Time Compare (High) Core 0 |
+
+## MTIMECMP_LOW1
+Machine Timer Compare for Core 1
+- Offset: `0x4008`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                       |
+|:------:|:------:|:-------:|:-------------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_LOW | Machine Time Compare (Low) Core 1 |
+
+## MTIMECMP_HIGH1
+Machine Timer Compare for Core 1
+- Offset: `0x400c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIMECMP_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                        |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | MTIMECMP_HIGH | Machine Time Compare (High) Core 1 |
+
+## MTIME_LOW
+Timer Register Low
+- Offset: `0xbff8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIME_LOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description        |
+|:------:|:------:|:-------:|:----------|:-------------------|
+|  31:0  |   rw   |   0x0   | MTIME_LOW | Machine Time (Low) |
+
+## MTIME_HIGH
+Timer Register High
+- Offset: `0xbffc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MTIME_HIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description         |
+|:------:|:------:|:-------:|:-----------|:--------------------|
+|  31:0  |   rw   |   0x0   | MTIME_HIGH | Machine Time (High) |
+
diff --git a/docs/um/ip/cluster_peripherals/cl_dma/Data/CL_DMA.hjson b/docs/um/ip/cluster_peripherals/cl_dma/Data/CL_DMA.hjson
new file mode 100644
index 00000000..4777ef75
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cl_dma/Data/CL_DMA.hjson
@@ -0,0 +1,327 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# DMA register template
+{
+  name:               "dma"
+  human_name:         "DMA Controller"
+  one_line_desc:      "DMA Controller for the integrated OpenTitan."
+  one_paragraph_desc: '''
+  Cluster DMA component manages the following features:
+  - parametric number of RX/TX full-duplex channels
+  - Up to 16 outstanding transfers between L1 and L2 memories
+  - Linear or 2D transfers modes on both TCDM or EXT (L2) sides
+  '''
+  cip_id:             "36",
+  design_spec:        "../doc"
+  dv_doc:             "../doc/dv"
+  version:            "1.0.0"
+
+  clocking: [{clock: "clk_i", reset: "rst_ni", primary: true}]
+  scan: "true"        // Enable `scanmode_i` port
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device", hier_path: "u_dma_reg" }
+    { protocol: "tlul", direction: "host", name: "host" }
+  ]
+  param_list: [
+    { name: "NumIntClearSources",
+      desc: "Number of interrupt clearing sources to process",
+      type: "int",
+      default: "11",
+      local: "true"
+    },
+    { name: "EnableDataIntgGen",
+      desc: "Compute integrity bits for A channel data on all TL-UL host ports",
+      type: "bit",
+      default: "1'b1",
+      local: "false",
+      expose: "true",
+    },
+    { name: "EnableRspDataIntgCheck",
+      desc: "Enable integrity checks on the response TL-UL D channel",
+      type: "bit",
+      default: "1'b1",
+      local: "false",
+      expose: "true",
+    },
+    { name: "TlUserRsvd",
+      desc: "Value of `rsvd` field in A channel of all TL-UL host ports",
+      type: "logic [tlul_pkg::RsvdWidth-1:0]"
+      default: "'0",
+      local: "false",
+      expose: "true",
+    },
+    { name: "SysRacl",
+      desc: "Value of `racl_vec` field in `sys` output",
+      type: "logic [dma_pkg::SYS_RACL_WIDTH-1:0]"
+      default: "'0",
+      local: "false",
+      expose: "true",
+    },
+    { name: "OtAgentId",
+      desc: "OT Agent ID"
+      type: "int unsigned"
+      default: "0",
+      local: "false",
+      expose: "true",
+    },
+  ],
+  inter_signal_list: [
+    { name: "lsio_trigger"
+      type: "uni",
+      act: "rcv",
+      package: "dma_pkg",
+      struct: "lsio_trigger",
+      width: "1"
+    }
+    { name: "sys"
+      type: "req_rsp"
+      struct: "sys"
+      package: "dma_pkg"
+      act: "req"
+      width: "1"
+    }
+    { struct:  "tl_h2d"
+      package: "tlul_pkg"
+      type:    "uni"
+      name:    "ctn_tl_h2d"
+      act:     "req"
+      desc:    "TL-UL host port for egress into CTN (request part), synchronous"
+    }
+    { struct:  "tl_d2h"
+      package: "tlul_pkg"
+      type:    "uni"
+      name:    "ctn_tl_d2h"
+      act:     "rcv"
+      desc:    "TL-UL host port for egress into CTN (response part), synchronous"
+    }
+  ]
+  interrupt_list: [
+    { name: "dma_done"
+      desc: "DMA operation has been completed."
+      type: "status"
+    }
+    { name: "dma_chunk_done"
+      desc: "Indicates the transfer of a single chunk has been completed."
+      type: "status"
+    }
+    { name: "dma_error"
+      desc: "DMA error has occurred. DMA_STATUS.error_code register shows the details."
+      type: "status"
+    }
+  ]
+  alert_list: [
+    { name: "fatal_fault"
+      desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected."
+    }
+  ]
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+    { name: "ASID.INTERSIG.MUBI",
+      desc: "Destination and source ASID signals are multibit encoded."
+    }
+    { name: "RANGE.CONFIG.REGWEN_MUBI",
+      desc: "DMA enabled memory range is software multibit lockable."
+    }
+  ]
+  regwidth: "32"
+  registers: [
+    { name: "CMD"
+      desc: '''
+            ?
+            ?
+            ?
+            '''
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "16:0"
+          name: "LEN"
+          resval: 0x0
+          desc: "Transfer length in bytes configuration bitfield."
+        }
+        { bits: "17"
+          name: "TYPE"
+          resval: 0x0
+          desc: '''Transfer direction configuration bitfield:
+                -1'b0: L1 to L2
+                -1'b1: L2 to L1
+                '''
+        }
+        { bits: "18"
+          name: "INC"
+          resval: 0x0
+          desc: '''Transfer incremental configuration bitfield:
+                -1'b0: non incremental.
+                -1'b1: incremental.
+                '''
+        }
+        { bits: "19"
+          name: "EXT_2D"
+          resval: 0x0
+          desc: '''Transfer type configuration bitfield:
+                -1'b0: linear transfer in EXT interface.
+                -1'b1: 2D transfer in EXT interface.
+                '''
+        }
+        { bits: "20"
+          name: "ELE"
+          resval: 0x0
+          desc: '''Transfer event generation configuration bitfield:
+                -1'b0: disabled.
+                -1'b1: enabled.
+                '''
+        }
+        { bits: "21"
+          name: "ILE"
+          resval: 0x0
+          desc: '''Transfer interrupt generation configuration bitfield:
+                -1'b0: disabled.
+                -1'b1: enabled.
+                '''
+        }
+        { bits: "22"
+          name: "BLE"
+          resval: 0x0
+          desc: '''Transfer event or interrupt broadcast configuration bitfield:
+                1'b0: event or interrupt is routed to the cluster core who initiated the transfer.
+                1'b1: event or interrupt are broadcasted to all cluster cores.
+                '''
+        }
+        { bits: "23"
+          name: "TCDM_2D"
+          resval: 0x0
+          desc: '''Transfer type configuration bitfield:
+                -1'b0: linear transfer in TCDM interface
+                -1'b1: 2D transfer in TCDM interface
+                '''
+        }
+      ]
+    }
+    { name: "TID"
+      desc: "Transfer identifier value bitfield."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "3:0"
+          name: "get_tid"
+          resval: 0x0
+          desc: "Transfer identifier value bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_ADDR"
+      desc: "Transfer L1 base address configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "tcdm_addr"
+          resval: 0x0
+          desc: "Transfer L1 base address configuration bitfield."
+        }
+      ]
+    }
+    { name: "EXT_ADDR"
+      desc: "Transfer L2 base address configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ext_addr"
+          resval: 0x0
+          desc: "Transfer L2 base address configuration bitfield."
+        }
+      ]
+    }
+    { name: "EXT_COUNT_2D"
+      desc: "EXT 2D transfer conut value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ext_count_2D"
+          resval: 0x0
+          desc: "EXT 2D transfer conut value configuration bitfield."
+        }
+      ]
+    }
+    { name: "EXT_STRIDE_2D"
+      desc: "EXT 2D transfer stride value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ext_stride_2D"
+          resval: 0x0
+          desc: "EXT 2D transfer stride value configuration bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_COUNT_2D"
+      desc: "TCDM 2D transfer conut value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "tcdm_count_2D"
+          resval: 0x0
+          desc: "TCDM 2D transfer conut value configuration bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_STRIDE_2D"
+      desc: "TCDM 2D transfer stride value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "tcdm_stride_2D"
+          resval: 0x0
+          desc: "TCDM 2D transfer stride value configuration bitfield."
+        }
+      ]
+    }
+    { name: "STATUS"
+      desc: '''
+            ?
+            ?
+            ?
+            '''
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "TID_TR"
+          resval: 0x0
+          desc: '''Transfer status bitfield:
+                TID_TR[i]=1'b1 means that transfer with TID i is active.
+		'''
+        }
+        { bits: "31:16"
+          name: "TID_ALLOC"
+          resval: 0x0
+          desc: '''Transfer status bitfield:
+                - TID_TR[i]=1'b0 means that transfer allocator with TID i-16 is free.
+                - TID_TR[i]=1'b1 means that transfer allocator with TID i-16 is reserved.
+                '''
+        }
+      ]
+    }
+    { name: "TID_FREE"
+      desc: "Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "15:0"
+          name: "tid_free"
+          resval: 0x0
+          desc: "Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i."
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/cluster_peripherals/cl_dma/Doc/CL_DMA.md b/docs/um/ip/cluster_peripherals/cl_dma/Doc/CL_DMA.md
new file mode 100644
index 00000000..541f1c7f
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cl_dma/Doc/CL_DMA.md
@@ -0,0 +1,268 @@
+## Summary
+
+| Name                                    | Offset   |   Length | Description                                                                                             |
+|:----------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------------------------------|
+| dma.[`INTR_STATE`](#intr_state)         | 0x0      |        4 | Interrupt State Register                                                                                |
+| dma.[`INTR_ENABLE`](#intr_enable)       | 0x4      |        4 | Interrupt Enable Register                                                                               |
+| dma.[`INTR_TEST`](#intr_test)           | 0x8      |        4 | Interrupt Test Register                                                                                 |
+| dma.[`ALERT_TEST`](#alert_test)         | 0xc      |        4 | Alert Test Register                                                                                     |
+| dma.[`CMD`](#cmd)                       | 0x10     |        4 | ?                                                                                                       |
+| dma.[`TID`](#tid)                       | 0x14     |        4 | Transfer identifier value bitfield.                                                                     |
+| dma.[`TCDM_ADDR`](#tcdm_addr)           | 0x18     |        4 | Transfer L1 base address configuration bitfield.                                                        |
+| dma.[`EXT_ADDR`](#ext_addr)             | 0x1c     |        4 | Transfer L2 base address configuration bitfield.                                                        |
+| dma.[`EXT_COUNT_2D`](#ext_count_2d)     | 0x20     |        4 | EXT 2D transfer conut value configuration bitfield.                                                     |
+| dma.[`EXT_STRIDE_2D`](#ext_stride_2d)   | 0x24     |        4 | EXT 2D transfer stride value configuration bitfield.                                                    |
+| dma.[`TCDM_COUNT_2D`](#tcdm_count_2d)   | 0x28     |        4 | TCDM 2D transfer conut value configuration bitfield.                                                    |
+| dma.[`TCDM_STRIDE_2D`](#tcdm_stride_2d) | 0x2c     |        4 | TCDM 2D transfer stride value configuration bitfield.                                                   |
+| dma.[`STATUS`](#status)                 | 0x30     |        4 | ?                                                                                                       |
+| dma.[`TID_FREE`](#tid_free)             | 0x34     |        4 | Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dma_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "dma_chunk_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                               |
+|:------:|:------:|:-------:|:---------------|:--------------------------------------------------------------------------|
+|  31:3  |        |         |                | Reserved                                                                  |
+|   2    |   ro   |   0x0   | dma_error      | DMA error has occurred. DMA_STATUS.error_code register shows the details. |
+|   1    |   ro   |   0x0   | dma_chunk_done | Indicates the transfer of a single chunk has been completed.              |
+|   0    |   ro   |   0x0   | dma_done       | DMA operation has been completed.                                         |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dma_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dma_chunk_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                              |
+|:------:|:------:|:-------:|:---------------|:-------------------------------------------------------------------------|
+|  31:3  |        |         |                | Reserved                                                                 |
+|   2    |   rw   |   0x0   | dma_error      | Enable interrupt when [`INTR_STATE.dma_error`](#intr_state) is set.      |
+|   1    |   rw   |   0x0   | dma_chunk_done | Enable interrupt when [`INTR_STATE.dma_chunk_done`](#intr_state) is set. |
+|   0    |   rw   |   0x0   | dma_done       | Enable interrupt when [`INTR_STATE.dma_done`](#intr_state) is set.       |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "dma_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "dma_chunk_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "dma_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                       |
+|:------:|:------:|:-------:|:---------------|:------------------------------------------------------------------|
+|  31:3  |        |         |                | Reserved                                                          |
+|   2    |   wo   |   0x0   | dma_error      | Write 1 to force [`INTR_STATE.dma_error`](#intr_state) to 1.      |
+|   1    |   wo   |   0x0   | dma_chunk_done | Write 1 to force [`INTR_STATE.dma_chunk_done`](#intr_state) to 1. |
+|   0    |   wo   |   0x0   | dma_done       | Write 1 to force [`INTR_STATE.dma_done`](#intr_state) to 1.       |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CMD
+?
+?
+?
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LEN", "bits": 17, "attr": ["wo"], "rotate": 0}, {"name": "TYPE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "INC", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "EXT_2D", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ELE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ILE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "BLE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TCDM_2D", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                                                                     |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:24  |        |         |         | Reserved                                                                                                                                                                                                        |
+|   23   |   wo   |   0x0   | TCDM_2D | Transfer type configuration bitfield: -1'b0: linear transfer in TCDM interface -1'b1: 2D transfer in TCDM interface                                                                                             |
+|   22   |   wo   |   0x0   | BLE     | Transfer event or interrupt broadcast configuration bitfield: 1'b0: event or interrupt is routed to the cluster core who initiated the transfer. 1'b1: event or interrupt are broadcasted to all cluster cores. |
+|   21   |   wo   |   0x0   | ILE     | Transfer interrupt generation configuration bitfield: -1'b0: disabled. -1'b1: enabled.                                                                                                                          |
+|   20   |   wo   |   0x0   | ELE     | Transfer event generation configuration bitfield: -1'b0: disabled. -1'b1: enabled.                                                                                                                              |
+|   19   |   wo   |   0x0   | EXT_2D  | Transfer type configuration bitfield: -1'b0: linear transfer in EXT interface. -1'b1: 2D transfer in EXT interface.                                                                                             |
+|   18   |   wo   |   0x0   | INC     | Transfer incremental configuration bitfield: -1'b0: non incremental. -1'b1: incremental.                                                                                                                        |
+|   17   |   wo   |   0x0   | TYPE    | Transfer direction configuration bitfield: -1'b0: L1 to L2 -1'b1: L2 to L1                                                                                                                                      |
+|  16:0  |   wo   |   0x0   | LEN     | Transfer length in bytes configuration bitfield.                                                                                                                                                                |
+
+## TID
+Transfer identifier value bitfield.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "get_tid", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                         |
+|:------:|:------:|:-------:|:--------|:------------------------------------|
+|  31:4  |        |         |         | Reserved                            |
+|  3:0   |   ro   |   0x0   | get_tid | Transfer identifier value bitfield. |
+
+## TCDM_ADDR
+Transfer L1 base address configuration bitfield.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tcdm_addr", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                      |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------|
+|  31:0  |   wo   |   0x0   | tcdm_addr | Transfer L1 base address configuration bitfield. |
+
+## EXT_ADDR
+Transfer L2 base address configuration bitfield.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ext_addr", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                      |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------|
+|  31:0  |   wo   |   0x0   | ext_addr | Transfer L2 base address configuration bitfield. |
+
+## EXT_COUNT_2D
+EXT 2D transfer conut value configuration bitfield.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ext_count_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                                         |
+|:------:|:------:|:-------:|:-------------|:----------------------------------------------------|
+|  31:0  |   wo   |   0x0   | ext_count_2D | EXT 2D transfer conut value configuration bitfield. |
+
+## EXT_STRIDE_2D
+EXT 2D transfer stride value configuration bitfield.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ext_stride_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                          |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------------------------|
+|  31:0  |   wo   |   0x0   | ext_stride_2D | EXT 2D transfer stride value configuration bitfield. |
+
+## TCDM_COUNT_2D
+TCDM 2D transfer conut value configuration bitfield.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tcdm_count_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                          |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------------------------|
+|  31:0  |   wo   |   0x0   | tcdm_count_2D | TCDM 2D transfer conut value configuration bitfield. |
+
+## TCDM_STRIDE_2D
+TCDM 2D transfer stride value configuration bitfield.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tcdm_stride_2D", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                           |
+|:------:|:------:|:-------:|:---------------|:------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | tcdm_stride_2D | TCDM 2D transfer stride value configuration bitfield. |
+
+## STATUS
+?
+?
+?
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TID_TR", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "TID_ALLOC", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                               |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:16  |   ro   |   0x0   | TID_ALLOC | Transfer status bitfield: - TID_TR[i]=1'b0 means that transfer allocator with TID i-16 is free. - TID_TR[i]=1'b1 means that transfer allocator with TID i-16 is reserved. |
+|  15:0  |   ro   |   0x0   | TID_TR    | Transfer status bitfield: TID_TR[i]=1'b1 means that transfer with TID i is active.                                                                                        |
+
+## TID_FREE
+Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tid_free", "bits": 16, "attr": ["wo"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                             |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------------------------------------|
+| 31:16  |        |         |          | Reserved                                                                                                |
+|  15:0  |   wo   |   0x0   | tid_free | Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i. |
+
diff --git a/docs/um/ip/cluster_peripherals/cl_event_unit/data/cl_event_unit_regs.hjson b/docs/um/ip/cluster_peripherals/cl_event_unit/data/cl_event_unit_regs.hjson
new file mode 100644
index 00000000..acb68128
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cl_event_unit/data/cl_event_unit_regs.hjson
@@ -0,0 +1,1588 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Michael Gautschi  <gautschi@iis.ee.ethz.ch>
+
+{
+  name: "cluster_event_unit"
+  one_paragraph_desc: '''
+  Cluster event unit component manages the following features:
+   - Cluster software events generation
+   - Cluster cores clock gate control
+   - Wait for event functionality
+   - Input event mask configuration
+   - Cluster cores IRQ generation
+   - 2 hardware mutex
+   - 8 hardware barriers
+   - 1 message dispatcher
+  Events managed by Cluster event unit are:
+   - 1 SoC peripheral event: when this event occurs, the SoC peripheral events fifo must be read to get the SoC event ID.
+   - 1 message dispatcher event
+   - 1 barrier event
+   - up to 4 hardware accelerator events
+   - 2 Cluster timer events
+   - 2 DMA events
+   - 8 software events that can come from cluster cores directly or external triggering.
+  '''
+  cip_id:  "36",
+  version: "0.0.0" // null, commit c015839
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "EVT_MASK" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x0
+      desc: "Input event mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "29:0"
+          name: "EMCL"
+          resval: 0x0
+          desc: '''Cluster internal input event mask configuration bitfield:
+                - EMCL[i]=1'b0: Input event request i is masked
+                - EMCL[i]=1'b1: Input event request i is not masked
+                '''
+        }
+	{ bits: "30:30"
+          name: "EMINTCL"
+          resval: 0x0
+          desc: '''Inter-cluster input event mask configuration bitfield:
+                - EMINTCL[i]=1'b0: Input event request i is masked
+                - EMINTCL[i]=1'b1: Input event request i is not masked
+                '''
+        }
+        { bits: "31:31"
+          name: "EMSOC"
+          resval: 0x0
+          desc: '''Soc peripheral input event mask configuration bitfield:
+                - EMSOC[i]=1'b0: Input event request i is masked
+                - EMSOC[i]=1'b1: Input event request i is not masked
+                '''
+        }
+      ]
+    }
+    { name: "EVT_MASK_AND" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x4
+      desc: "Input event mask update command register with bitwise AND operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "EMA"
+          resval: 0x0
+          desc: '''Input event mask configuration bitfield update with bitwise AND operation.
+	        It allows clearing EMCL[i], EMINTCL[i] or EMSOC[i] if EMA[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "EVT_MASK_OR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x8
+      desc: "Input event mask update command register with bitwise OR operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "EMO"
+          resval: 0x0
+          desc: '''Input event mask configuration bitfield update with bitwise OR operation.
+	        It allows setting EMCL[i], EMINTCL[i] or EMSOC[i] if EMO[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "IRQ_MASK" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset	: 0x0, Address : 0xC
+      desc: "Interrupt request mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "29:0"
+          name: "IMCL"
+          resval: 0x0
+          desc: '''Cluster internal interrupt request mask configuration bitfield:
+                - bit[i]=1'b0: Interrupt request i is masked
+                - bit[i]=1'b1: Interrupt request i is not masked
+                '''
+        }
+        { bits: "30:30"
+          name: "IMINTCL"
+          resval: 0x0
+          desc: '''Inter-cluster interrupt request mask configuration bitfield:
+                - bit[i]=1'b0: Interrupt request i is masked
+                - bit[i]=1'b1: Interrupt request i is not masked
+                '''
+        }
+        { bits: "31:31"
+          name: "IMSOC"
+          resval: 0x0
+          desc: '''Soc peripheral interrupt request mask configuration bitfield:
+                - bit[i]=1'b0: Interrupt request i is masked
+                - bit[i]=1'b1: Interrupt request i is not masked
+                '''
+        }
+      ]	
+    }
+    { name: "IRQ_MASK_AND" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x10
+      desc: "Interrupt request mask update command register with bitwise AND operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "IMA"
+          resval: 0x0
+          desc: '''Interrupt request mask configuration bitfield update with bitwise AND operation.
+	        It allows clearing IMCL[i], IMINTCL[i] or IMSOC[i] if IMA[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "IRQ_MASK_OR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x14
+      desc: "Interrupt request mask update command register with bitwise OR operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "IMO"
+          resval: 0x0
+          desc: '''Interrupt request mask configuration bitfield update with bitwise OR operation.
+	        It allows setting IMCL[i], IMINTCL[i] or IMSOC[i] if IMO[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "CLOCK_STATUS" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x18
+      desc: "Cluster cores clock status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0:0"
+          name: "CS"
+          resval: 0x0
+          desc: '''Cluster core clock status bitfield:
+                - 1'b0: Cluster core clocked is gated
+                - 1'b1: Cluster core clocked is running
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x1C
+      desc: "Pending input events status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EB"
+          resval: 0x0
+          desc: '''Pending input events status bitfield.
+                EB[i]=1'b1: one or more input event i request are pending.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER_MASKED" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x20
+      desc: "Pending input events status register with EVT_MASK applied."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Pending input events status bitfield with EVT_MASK applied.
+                EBM[i]=1'b1: one or more input event i request are pending.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER_IRQ_MASKED" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x24
+      desc: "Pending input events status register with IRQ_MASK applied."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "IBM"
+          resval: 0x0
+          desc: '''Pending input events status bitfield with IRQ_MASK applied.
+                IBM[i]=1'b1:  one or more input events i are pending.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER_CLEAR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x28
+      desc: "Pending input events status clear command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "31:0"
+          name: "EBC"
+          resval: 0x0
+          desc: '''Pending input events status clear command bitfield.
+                It allows clearing EB[i] if EBC[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_MASK" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x2C
+      desc: "Software events cluster cores destination mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SWEM"
+          resval: 0x0
+          desc: '''Software events mask configuration bitfield:
+                - bit[i]=1'b0: software events are masked for CL_CORE[i]
+                - bit[i]=1'b1: software events are not masked for CL_CORE[i]
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_MASK_AND" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x30
+      desc: "Software events cluster cores destination mask update command register with bitwise AND operation."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "7:0"
+          name: "SWEMA"
+          resval: 0x0
+          desc: '''Software event mask configuration bitfield update with bitwise AND operation.
+	        It allows clearing SWEM[i] if SWEMA[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_MASK_OR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x34
+      desc: "Software events cluster cores destination mask update command register with bitwise OR operation."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "7:0"
+          name: "SWEMO"
+          resval: 0x0
+          desc: '''Software event mask configuration bitfield update with bitwise OR operation.
+	        It allows setting SWEM[i] if SWEMO[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_WAIT" // demux base address offset : 0x0, Address : 0x38
+      desc: "Input event wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Reading this register will gate the Cluster core clock until at least one unmasked event occurs.
+	        The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+	}
+      ]
+    }
+    { name: "EVENT_WAIT_CLEAR" // demux base address offset : 0x0, Address : 0x3C 
+      desc: "Input event wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Reading this register has the same effect as reading EVENT_WAIT.EBM.
+	        In addition, EVENT_BUFFER.EB[i] bits are cleared if EVT_MASK[i]=1'b1.
+		The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+	}
+      ]
+    }
+    { name: "HW_DISPATCH_PUSH_TASK" // demux base address offset : 0x80, Address : 0x0
+      desc: "Hardware task dispatcher push command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message to dispatch to all cluster cores selected in HW_DISPATCH_PUSH_TEAM_CONFIG.CT configuration bitfield."
+        }
+      ]
+    }
+    { name: "HW_DISPATCH_POP_TASK" // demux base address offset : 0x80, Address : 0x0
+      desc: "Hardware task dispatcher pop command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message dispatched using HW_DISPATCH_PUSH_TASK command and popped by cluster core who issued HW_DISPATCH_POP_TASK command."
+        }
+      ]
+    }
+    { name: "HW_DISPATCH_PUSH_TEAM_CONFIG" // demux base address offset : 0x80, Address : 0x4
+      desc: "Hardware task dispatcher cluster core team configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "CT"
+          resval: 0x0
+          desc: '''Cluster cores team selection configuration bitfield.
+	        It allows to transmit HW_DISPATCH_PUSH_TASK.MSG to cluster core i if CT[i]=1'b1.
+		'''
+        }
+      ]
+    }
+    { name: "HW_MUTEX_0_MSG_PUT" // demux base address offset : 0xC0, Address : 0x0
+      desc: "Hardware mutex 0 non-blocking put command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message pushed when releasing hardware mutex 0 configuration bitfiled. It is a non-blocking access."
+        }
+      ]
+    }
+    { name: "HW_MUTEX_0_MSG_GET" // demux base address offset : 0xC0, Address : 0x0
+      desc: "Hardware mutex 0 blocking get command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc:	"Message popped when taking hardware mutex 0 data bitfiled. It is a blocking access."
+        }
+      ]
+    }
+    { name: "HW_MUTEX_1_MSG_PUT" // demux base address offset : 0xC0, Address : 0x4
+      desc: "Hardware mutex 1 non-blocking put command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc:	"Message pushed when releasing hardware mutex 1 configuration bitfiled. It is a non-blocking access."
+        }
+      ]
+    }
+    { name: "HW_MUTEX_1_MSG_GET" // demux base address offset : 0xC0, Address : 0x4
+      desc: "Hardware mutex 1 blocking get command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message popped when taking hardware mutex 1 data bitfiled. It is a blocking access."
+        }
+      ]
+    }
+    { name: "SW_EVENT_0_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x0
+      desc: "Cluster Software event 0 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW0T"
+          resval: 0x0
+          desc: "Triggers software event 0 for cluster core i if SW0T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_1_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x4
+      desc: "Cluster Software event 1 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW1T"
+          resval: 0x0
+          desc: "Triggers software event 1 for cluster core i if SW1T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_2_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x8
+      desc: "Cluster Software event 2 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW2T"
+          resval: 0x0
+          desc: "Triggers software event 2 for cluster core i if SW2T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_3_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0xC
+      desc: "Cluster Software event 3 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW3T"
+          resval: 0x0
+          desc: "Triggers software event 3 for cluster core i if SW3T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_4_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x10
+      desc: "Cluster Software event 4 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW4T"
+          resval: 0x0
+          desc: "Triggers software event 4 for cluster core i if SW4T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_5_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x14
+      desc: "Cluster Software event 5 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW5T"
+          resval: 0x0
+          desc: "Triggers software event 5 for cluster core i if SW5T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_6_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x18
+      desc: "Cluster Software event 6 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW6T"
+          resval: 0x0
+          desc: "Triggers software event 6 for cluster core i if SW6T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_7_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x1C
+      desc: "Cluster Software event 7 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW7T"
+          resval: 0x0
+          desc: "Triggers software event 7 for cluster core i if SW7T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_0_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x0
+      desc: "Cluster Software event 0 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+	        The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_1_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x4
+      desc: "Cluster Software event 1 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_2_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x8
+      desc: "Cluster Software event 2 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_3_TRIG_WAIT" // demux base address offset : 0x140, Address : 0xC
+      desc: "Cluster Software event 3 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_4_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x10
+      desc: "Cluster Software event 4 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_5_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x14
+      desc: "Cluster Software event 5 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_6_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x18
+      desc: "Cluster Software event 6 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_7_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x1C
+      desc: "Cluster Software event 7 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_0_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x0
+      desc: "Cluster Software event 0 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+	        In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_1_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x4
+      desc: "Cluster Software event 1 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_2_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x8
+      desc: "Cluster Software event 2 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_3_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0xC
+      desc: "Cluster Software event 3 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_4_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x10
+      desc: "Cluster Software event 4 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_5_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x14
+      desc: "Cluster Software event 5 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_6_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x18
+      desc: "Cluster Software event 6 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_7_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x1C
+      desc: "Cluster Software event 7 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SOC_PERIPH_EVENT_ID" // periph base address offset: 0x700, Address : 0x0
+      desc: "Cluster SoC peripheral event ID status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "7:0"
+          name: "ID"
+          resval: 0x0
+          desc: "Oldest SoC peripheral event ID status bitfield."
+        }
+	{ bits: "31:31"
+          name: "VALID"
+          resval: 0x0
+          desc:	"Validity bit of SOC_PERIPH_EVENT_ID.ID bitfield."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x0
+      desc: "Cluster hardware barrier 0 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB0TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 0 bitfield.
+	        Hardware barrier 0 will be triggered only if for all HB0TM[i] = 1'b1,  HW_BARRIER_0_STATUS.HB0S[i]=1'b1.
+		HB0TM=0 means that hardware barrier 0 is disabled.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x20
+      desc: "Cluster hardware barrier 1 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB1TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 1 bitfield.
+                Hardware barrier 1 will be triggered only if for all HB1TM[i] = 1'b1,  HW_BARRIER_1_STATUS.HB1S[i]=1'b1.
+		HB1TM=0 means that hardware barrier 1 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_2_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x40
+      desc: "Cluster hardware barrier 2 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB2TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 2 bitfield.
+                Hardware barrier 2 will be triggered only if for all HB2TM[i] = 1'b1,  HW_BARRIER_2_STATUS.HB2S[i]=1'b1.
+		HB2TM=0 means that hardware barrier 2 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_3_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x60
+      desc: "Cluster hardware barrier 3 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB3TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 3 bitfield.
+                Hardware barrier 3 will be triggered only if for all HB3TM[i] = 1'b1,  HW_BARRIER_3_STATUS.HB3S[i]=1'b1.
+		HB3TM=0 means that hardware barrier 3 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_4_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x80
+      desc: "Cluster hardware barrier 4 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB4TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 4 bitfield.
+                Hardware barrier 4 will be triggered only if for all HB4TM[i] = 1'b1,  HW_BARRIER_4_STATUS.HB4S[i]=1'b1.
+		HB4TM=0 means that hardware barrier 4 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_5_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xA0
+      desc: "Cluster hardware barrier 5 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB5TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 5 bitfield.
+                Hardware barrier 5 will be triggered only if for all HB5TM[i] = 1'b1,  HW_BARRIER_5_STATUS.HB5S[i]=1'b1.
+		HB5TM=0 means that hardware barrier 5 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_6_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xC0
+      desc: "Cluster hardware barrier 6 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB6TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 6 bitfield.
+                Hardware barrier 6 will be triggered only if for all HB6TM[i] = 1'b1,  HW_BARRIER_6_STATUS.HB6S[i]=1'b1.
+		HB6TM=0 means that hardware barrier 6 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_7_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xE0
+      desc: "Cluster hardware barrier 7 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB7TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 7 bitfield.
+                Hardware barrier 7 will be triggered only if for all HB7TM[i] = 1'b1,  HW_BARRIER_7_STATUS.HB7S[i]=1'b1.
+		HB7TM=0 means that hardware barrier 7 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x4
+      desc: "Cluster hardware barrier 0 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 0 bitfield.
+	        HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 0.
+		It is cleared when HBS matches HW_BARRIER_0_TRIG_MASK.HB0TM.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x24
+      desc: "Cluster hardware barrier 1 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 1 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 1.
+	        It is cleared when HBS matches HW_BARRIER_1_TRIG_MASK.HB1TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_2_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x44
+      desc: "Cluster hardware barrier 2 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 2 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 2.
+	        It is cleared when HBS matches HW_BARRIER_2_TRIG_MASK.HB2TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_3_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x64
+      desc: "Cluster hardware barrier 3 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 3 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 3.
+	        It is cleared when HBS matches HW_BARRIER_3_TRIG_MASK.HB3TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_4_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x84
+      desc: "Cluster hardware barrier 4 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 4 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 4.
+	        It is cleared when HBS matches HW_BARRIER_4_TRIG_MASK.HB4TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_5_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xA4
+      desc: "Cluster hardware barrier 5 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 5 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 5.
+	        It is cleared when HBS matches HW_BARRIER_5_TRIG_MASK.HB5TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_6_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xC4
+      desc: "Cluster hardware barrier 6 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 6 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 6.
+	        It is cleared when HBS matches HW_BARRIER_6_TRIG_MASK.HB6TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_7_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xE4
+      desc: "Cluster hardware barrier 7 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 7 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 7.
+	        It is cleared when HBS matches HW_BARRIER_7_TRIG_MASK.HB7TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 0. HBSS[i] represents a summary of the barrier status for core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x28
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 1. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_2_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x48
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 2. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_3_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x68
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 3. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_4_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x88
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 4. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_5_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xA8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 5. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_6_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xC8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 6. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_7_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xE8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 7. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_0_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xC
+      desc: "Cluster hardware barrier 0 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc: '''Cluster hardware barrier 0 target mask configuration bitfield.
+	        HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 0 event when HW_BARRIER_0_STATUS will match HW_BARRIER_0_TRIG_MASK.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x2C
+      desc: "Cluster hardware barrier 1 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc:	'''Cluster hardware barrier 1 target mask configuration bitfield.
+                HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 1 event when HW_BARRIER_1_STATUS will match HW_BARRIER_1_TRIG_MASK.
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_2_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x4C
+      desc: "Cluster hardware barrier 2 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc:	'''Cluster hardware barrier 2 target mask configuration bitfield.
+                HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 2 event when HW_BARRIER_2_STATUS will match HW_BARRIER_2_TRIG_MASK.
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_3_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x6C
+      desc: "Cluster hardware barrier 3 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc:	'''Cluster hardware barrier 3 target mask configuration bitfield.
+                HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 3 event when HW_BARRIER_3_STATUS will match HW_BARRIER_3_TRIG_MASK.
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_4_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x8C
+      desc: "Cluster hardware barrier 4 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc:	'''Cluster hardware barrier 4 target mask configuration bitfield.
+                HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 4 event when HW_BARRIER_4_STATUS will match HW_BARRIER_4_TRIG_MASK.
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_5_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xAC
+      desc: "Cluster hardware barrier 5 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc:	'''Cluster hardware barrier 5 target mask configuration bitfield.
+                HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 5 event when HW_BARRIER_5_STATUS will match HW_BARRIER_5_TRIG_MASK.
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_6_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xCC
+      desc: "Cluster hardware barrier 6 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc:	'''Cluster hardware barrier 6 target mask configuration bitfield.
+                HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 6 event when HW_BARRIER_6_STATUS will match HW_BARRIER_6_TRIG_MASK.
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_7_TARGET_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xEC
+      desc: "Cluster hardware barrier 7 target mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "HBTAM"
+          resval: 0x0
+          desc:	'''Cluster hardware barrier 7 target mask configuration bitfield.
+                HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 7 event when HW_BARRIER_7_STATUS will match HW_BARRIER_7_TRIG_MASK.
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_0_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x10
+      desc: "Cluster hardware barrier 0 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_0_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_1_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x30
+      desc: "Cluster hardware barrier 1 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_1_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_2_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x50
+      desc: "Cluster hardware barrier 2 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_2_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_3_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x70
+      desc: "Cluster hardware barrier 3 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_3_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_4_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x90
+      desc: "Cluster hardware barrier 4 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_4_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_5_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xB0
+      desc: "Cluster hardware barrier 5 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_5_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_6_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xD0
+      desc: "Cluster hardware barrier 6 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_6_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_7_TRIG" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xF0
+      desc: "Cluster hardware barrier 7 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_7_STATUS.HBS[i] to 1'b1 when T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_SELF_TRIG" // demux base address offset : 0x200, Address : 0x14
+      desc: "Cluster hardware barrier 0 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_0_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_SELF_TRIG" // demux base address offset : 0x200, Address : 0x34
+      desc: "Cluster hardware barrier 1 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_1_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_2_SELF_TRIG" // demux base address offset : 0x200, Address : 0x54
+      desc: "Cluster hardware barrier 2 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_2_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_3_SELF_TRIG" // demux base address offset : 0x200, Address : 0x74
+      desc: "Cluster hardware barrier 3 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_3_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_4_SELF_TRIG" // demux base address offset : 0x200, Address : 0x94
+      desc: "Cluster hardware barrier 4 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_4_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_5_SELF_TRIG" // demux base address offset : 0x200, Address : 0xB4
+      desc: "Cluster hardware barrier 5 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_5_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_6_SELF_TRIG" // demux base address offset : 0x200, Address : 0xD4
+      desc: "Cluster hardware barrier 6 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_6_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_7_SELF_TRIG" // demux base address offset : 0x200, Address : 0xF4
+      desc: "Cluster hardware barrier 7 self trigger command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "T"
+          resval: 0x0
+          desc:	"Sets HW_BARRIER_7_STATUS.HBS[i] to 1'b1 when issued by cluster core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_TRIG_WAIT" // demux base address offset : 0x200, Address : 0x18
+      desc: "Cluster hardware barrier 0 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_0[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_0 is released.
+	        The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+	}
+      ]
+    }
+    { name: "HW_BARRIER_1_TRIG_WAIT" // demux base address offset : 0x200, Address : 0x38
+      desc: "Cluster hardware barrier 1 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_1[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_1 is released.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_2_TRIG_WAIT" // demux base address offset : 0x200, Address : 0x58
+      desc: "Cluster hardware barrier 2 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_2[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_2 is released.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_3_TRIG_WAIT" // demux base address offset : 0x200, Address : 0x78
+      desc: "Cluster hardware barrier 3 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_3[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_3 is released.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_4_TRIG_WAIT" // demux base address offset : 0x200, Address : 0x98
+      desc: "Cluster hardware barrier 4 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_4[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_4 is released.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_5_TRIG_WAIT" // demux base address offset : 0x200, Address : 0xB8
+      desc: "Cluster hardware barrier 5 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_5[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_5 is released.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_6_TRIG_WAIT" // demux base address offset : 0x200, Address : 0xD8
+      desc: "Cluster hardware barrier 6 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_6[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_6 is released.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_7_TRIG_WAIT" // demux base address offset : 0x200, Address : 0xF8
+      desc: "Cluster hardware barrier 7 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_7[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_7 is released.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_0_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0x1C
+      desc: "Cluster hardware barrier 0 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc:	'''Set HW_BARRIER_0[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_0 is released.
+	        In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+      	      	'''
+        }
+      ]	
+    }
+    { name: "HW_BARRIER_1_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0x3C
+      desc: "Cluster hardware barrier 1 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_1[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_1 is released.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_2_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0x5C
+      desc: "Cluster hardware barrier 2 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_2[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_2 is released.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_3_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0x7C
+      desc: "Cluster hardware barrier 3 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_3[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_3 is released.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_4_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0x9C
+      desc: "Cluster hardware barrier 4 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_4[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_4 is released.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_5_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0xBC
+      desc: "Cluster hardware barrier 5 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_5[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_5 is released.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_6_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0xDC
+      desc: "Cluster hardware barrier 6 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_6[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_6 is released.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_7_TRIG_WAIT_CLEAR" // demux base address offset : 0x200, Address : 0xFC
+      desc: "Cluster hardware barrier 7 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Set HW_BARRIER_7[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_7 is released.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/cluster_peripherals/cl_event_unit/data/cl_event_unit_regs.hjson~ b/docs/um/ip/cluster_peripherals/cl_event_unit/data/cl_event_unit_regs.hjson~
new file mode 100644
index 00000000..28f5c05f
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cl_event_unit/data/cl_event_unit_regs.hjson~
@@ -0,0 +1,1500 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Michael Gautschi  <gautschi@iis.ee.ethz.ch>
+
+{
+  name: "cluster_event_unit"
+  one_paragraph_desc: '''
+  Cluster event unit component manages the following features:
+   - Cluster software events generation
+   - Cluster cores clock gate control
+   - Wait for event functionality
+   - Input event mask configuration
+   - Cluster cores IRQ generation
+   - 2 hardware mutex
+   - 8 hardware barriers
+   - 1 message dispatcher
+  Events managed by Cluster event unit are:
+   - 1 SoC peripheral event: when this event occurs, the SoC peripheral events fifo must be read to get the SoC event ID.
+   - 1 message dispatcher event
+   - 1 barrier event
+   - up to 4 hardware accelerator events
+   - 2 Cluster timer events
+   - 2 DMA events
+   - 8 software events that can come from cluster cores directly or external triggering.
+  '''
+  cip_id:  "36",
+  version: "0.0.0" // null, commit c015839
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "EVT_MASK" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x0
+      desc: "Input event mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "29:0"
+          name: "EMCL"
+          resval: 0x0
+          desc: '''Cluster internal input event mask configuration bitfield:
+                - EMCL[i]=1'b0: Input event request i is masked
+                - EMCL[i]=1'b1: Input event request i is not masked
+                '''
+        }
+	{ bits: "30:30"
+          name: "EMINTCL"
+          resval: 0x0
+          desc: '''Inter-cluster input event mask configuration bitfield:
+                - EMINTCL[i]=1'b0: Input event request i is masked
+                - EMINTCL[i]=1'b1: Input event request i is not masked
+                '''
+        }
+        { bits: "31:31"
+          name: "EMSOC"
+          resval: 0x0
+          desc: '''Soc peripheral input event mask configuration bitfield:
+                - EMSOC[i]=1'b0: Input event request i is masked
+                - EMSOC[i]=1'b1: Input event request i is not masked
+                '''
+        }
+      ]
+    }
+    { name: "EVT_MASK_AND" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x4
+      desc: "Input event mask update command register with bitwise AND operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "EMA"
+          resval: 0x0
+          desc: '''Input event mask configuration bitfield update with bitwise AND operation.
+	        It allows clearing EMCL[i], EMINTCL[i] or EMSOC[i] if EMA[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "EVT_MASK_OR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x8
+      desc: "Input event mask update command register with bitwise OR operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "EMO"
+          resval: 0x0
+          desc: '''Input event mask configuration bitfield update with bitwise OR operation.
+	        It allows setting EMCL[i], EMINTCL[i] or EMSOC[i] if EMO[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "IRQ_MASK" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset	: 0x0, Address : 0xC
+      desc: "Interrupt request mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "29:0"
+          name: "IMCL"
+          resval: 0x0
+          desc: '''Cluster internal interrupt request mask configuration bitfield:
+                - bit[i]=1'b0: Interrupt request i is masked
+                - bit[i]=1'b1: Interrupt request i is not masked
+                '''
+        }
+        { bits: "30:30"
+          name: "IMINTCL"
+          resval: 0x0
+          desc: '''Inter-cluster interrupt request mask configuration bitfield:
+                - bit[i]=1'b0: Interrupt request i is masked
+                - bit[i]=1'b1: Interrupt request i is not masked
+                '''
+        }
+        { bits: "31:31"
+          name: "IMSOC"
+          resval: 0x0
+          desc: '''Soc peripheral interrupt request mask configuration bitfield:
+                - bit[i]=1'b0: Interrupt request i is masked
+                - bit[i]=1'b1: Interrupt request i is not masked
+                '''
+        }
+      ]	
+    }
+    { name: "IRQ_MASK_AND" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x10
+      desc: "Interrupt request mask update command register with bitwise AND operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "IMA"
+          resval: 0x0
+          desc: '''Interrupt request mask configuration bitfield update with bitwise AND operation.
+	        It allows clearing IMCL[i], IMINTCL[i] or IMSOC[i] if IMA[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "IRQ_MASK_OR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x14
+      desc: "Interrupt request mask update command register with bitwise OR operation."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "IMO"
+          resval: 0x0
+          desc: '''Interrupt request mask configuration bitfield update with bitwise OR operation.
+	        It allows setting IMCL[i], IMINTCL[i] or IMSOC[i] if IMO[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "CLOCK_STATUS" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x18
+      desc: "Cluster cores clock status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0:0"
+          name: "CS"
+          resval: 0x0
+          desc: '''Cluster core clock status bitfield:
+                - 1'b0: Cluster core clocked is gated
+                - 1'b1: Cluster core clocked is running
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x1C
+      desc: "Pending input events status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EB"
+          resval: 0x0
+          desc: '''Pending input events status bitfield.
+                EB[i]=1'b1: one or more input event i request are pending.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER_MASKED" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x20
+      desc: "Pending input events status register with EVT_MASK applied."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Pending input events status bitfield with EVT_MASK applied.
+                EBM[i]=1'b1: one or more input event i request are pending.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER_IRQ_MASKED" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x24
+      desc: "Pending input events status register with IRQ_MASK applied."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "IBM"
+          resval: 0x0
+          desc: '''Pending input events status bitfield with IRQ_MASK applied.
+                IBM[i]=1'b1:  one or more input events i are pending.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_BUFFER_CLEAR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x28
+      desc: "Pending input events status clear command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "31:0"
+          name: "EBC"
+          resval: 0x0
+          desc: '''Pending input events status clear command bitfield.
+                It allows clearing EB[i] if EBC[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_MASK" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x2C
+      desc: "Software events cluster cores destination mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SWEM"
+          resval: 0x0
+          desc: '''Software events mask configuration bitfield:
+                - bit[i]=1'b0: software events are masked for CL_CORE[i]
+                - bit[i]=1'b1: software events are not masked for CL_CORE[i]
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_MASK_AND" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x30
+      desc: "Software events cluster cores destination mask update command register with bitwise AND operation."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "7:0"
+          name: "SWEMA"
+          resval: 0x0
+          desc: '''Software event mask configuration bitfield update with bitwise AND operation.
+	        It allows clearing SWEM[i] if SWEMA[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_MASK_OR" // periph base address core id offset : 0x40, periph base address offset : 0x0, demux base address offset : 0x0, Address : 0x34
+      desc: "Software events cluster cores destination mask update command register with bitwise OR operation."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "7:0"
+          name: "SWEMO"
+          resval: 0x0
+          desc: '''Software event mask configuration bitfield update with bitwise OR operation.
+	        It allows setting SWEM[i] if SWEMO[i]=1'b1.
+                '''
+        }
+      ]
+    }
+    { name: "EVENT_WAIT" // demux base address offset : 0x0, Address : 0x38
+      desc: "Input event wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Reading this register will gate the Cluster core clock until at least one unmasked event occurs.
+	        The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+	}
+      ]
+    }
+    { name: "EVENT_WAIT_CLEAR" // demux base address offset : 0x0, Address : 0x3C 
+      desc: "Input event wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Reading this register has the same effect as reading EVENT_WAIT.EBM.
+	        In addition, EVENT_BUFFER.EB[i] bits are cleared if EVT_MASK[i]=1'b1.
+		The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+	}
+      ]
+    }
+    { name: "HW_DISPATCH_PUSH_TASK" // demux base address offset : 0x80, Address : 0x0
+      desc: "Hardware task dispatcher push command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message to dispatch to all cluster cores selected in HW_DISPATCH_PUSH_TEAM_CONFIG.CT configuration bitfield."
+        }
+      ]
+    }
+    { name: "HW_DISPATCH_POP_TASK" // demux base address offset : 0x80, Address : 0x0
+      desc: "Hardware task dispatcher pop command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message dispatched using HW_DISPATCH_PUSH_TASK command and popped by cluster core who issued HW_DISPATCH_POP_TASK command."
+        }
+      ]
+    }
+    { name: "HW_DISPATCH_PUSH_TEAM_CONFIG" // demux base address offset : 0x80, Address : 0x4
+      desc: "Hardware task dispatcher cluster core team configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+	{ bits: "7:0"
+          name: "CT"
+          resval: 0x0
+          desc: '''Cluster cores team selection configuration bitfield.
+	        It allows to transmit HW_DISPATCH_PUSH_TASK.MSG to cluster core i if CT[i]=1'b1.
+		'''
+        }
+      ]
+    }
+    { name: "HW_MUTEX_0_MSG_PUT" // demux base address offset : 0xC0, Address : 0x0
+      desc: "Hardware mutex 0 non-blocking put command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message pushed when releasing hardware mutex 0 configuration bitfiled. It is a non-blocking access."
+        }
+      ]
+    }
+    { name: "HW_MUTEX_0_MSG_GET" // demux base address offset : 0xC0, Address : 0x0
+      desc: "Hardware mutex 0 blocking get command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc:	"Message popped when taking hardware mutex 0 data bitfiled. It is a blocking access."
+        }
+      ]
+    }
+    { name: "HW_MUTEX_1_MSG_PUT" // demux base address offset : 0xC0, Address : 0x4
+      desc: "Hardware mutex 1 non-blocking put command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc:	"Message pushed when releasing hardware mutex 1 configuration bitfiled. It is a non-blocking access."
+        }
+      ]
+    }
+    { name: "HW_MUTEX_1_MSG_GET" // demux base address offset : 0xC0, Address : 0x4
+      desc: "Hardware mutex 1 blocking get command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "MSG"
+          resval: 0x0
+          desc: "Message popped when taking hardware mutex 1 data bitfiled. It is a blocking access."
+        }
+      ]
+    }
+    { name: "SW_EVENT_0_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x0
+      desc: "Cluster Software event 0 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW0T"
+          resval: 0x0
+          desc: "Triggers software event 0 for cluster core i if SW0T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_1_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x4
+      desc: "Cluster Software event 1 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW1T"
+          resval: 0x0
+          desc: "Triggers software event 1 for cluster core i if SW1T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_2_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x8
+      desc: "Cluster Software event 2 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW2T"
+          resval: 0x0
+          desc: "Triggers software event 2 for cluster core i if SW2T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_3_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0xC
+      desc: "Cluster Software event 3 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW3T"
+          resval: 0x0
+          desc: "Triggers software event 3 for cluster core i if SW3T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_4_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x10
+      desc: "Cluster Software event 4 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW4T"
+          resval: 0x0
+          desc: "Triggers software event 4 for cluster core i if SW4T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_5_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x14
+      desc: "Cluster Software event 5 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW5T"
+          resval: 0x0
+          desc: "Triggers software event 5 for cluster core i if SW5T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_6_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x18
+      desc: "Cluster Software event 6 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW6T"
+          resval: 0x0
+          desc: "Triggers software event 6 for cluster core i if SW6T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_7_TRIG" // periph base address offset : 0x600, demux base address offset : 0x100, Address : 0x1C
+      desc: "Cluster Software event 7 trigger command register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "SW7T"
+          resval: 0x0
+          desc: "Triggers software event 7 for cluster core i if SW7T[i]=1'b1."
+        }
+      ]
+    }
+    { name: "SW_EVENT_0_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x0
+      desc: "Cluster Software event 0 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+	        The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_1_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x4
+      desc: "Cluster Software event 1 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_2_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x8
+      desc: "Cluster Software event 2 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_3_TRIG_WAIT" // demux base address offset : 0x140, Address : 0xC
+      desc: "Cluster Software event 3 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_4_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x10
+      desc: "Cluster Software event 4 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_5_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x14
+      desc: "Cluster Software event 5 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_6_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x18
+      desc: "Cluster Software event 6 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_7_TRIG_WAIT" // demux base address offset : 0x140, Address : 0x1C
+      desc: "Cluster Software event 7 trigger and wait command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]	
+    }
+    { name: "SW_EVENT_0_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x0
+      desc: "Cluster Software event 0 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+	        In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+                '''
+        }
+      ]
+    }
+    { name: "SW_EVENT_1_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x4
+      desc: "Cluster Software event 1 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_2_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x8
+      desc: "Cluster Software event 2 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_3_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0xC
+      desc: "Cluster Software event 3 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_4_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x10
+      desc: "Cluster Software event 4 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_5_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x14
+      desc: "Cluster Software event 5 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_6_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x18
+      desc: "Cluster Software event 6 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SW_EVENT_7_TRIG_WAIT_CLEAR" // demux base address offset : 0x180, Address : 0x1C
+      desc: "Cluster Software event 7 trigger, wait and clear command register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "31:0"
+          name: "EBM"
+          resval: 0x0
+          desc: '''Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+                In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+		'''
+        }
+      ]
+    }
+    { name: "SOC_PERIPH_EVENT_ID" // periph base address offset: 0x700, Address : 0x0
+      desc: "Cluster SoC peripheral event ID status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+	{ bits: "7:0"
+          name: "ID"
+          resval: 0x0
+          desc: "Oldest SoC peripheral event ID status bitfield."
+        }
+	{ bits: "31:31"
+          name: "VALID"
+          resval: 0x0
+          desc:	"Validity bit of SOC_PERIPH_EVENT_ID.ID bitfield."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x0
+      desc: "Cluster hardware barrier 0 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB0TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 0 bitfield.
+	        Hardware barrier 0 will be triggered only if for all HB0TM[i] = 1'b1,  HW_BARRIER_0_STATUS.HB0S[i]=1'b1.
+		HB0TM=0 means that hardware barrier 0 is disabled.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x20
+      desc: "Cluster hardware barrier 1 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB1TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 1 bitfield.
+                Hardware barrier 1 will be triggered only if for all HB1TM[i] = 1'b1,  HW_BARRIER_1_STATUS.HB1S[i]=1'b1.
+		HB1TM=0 means that hardware barrier 1 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_2_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x40
+      desc: "Cluster hardware barrier 2 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB2TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 2 bitfield.
+                Hardware barrier 2 will be triggered only if for all HB2TM[i] = 1'b1,  HW_BARRIER_2_STATUS.HB2S[i]=1'b1.
+		HB2TM=0 means that hardware barrier 2 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_3_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x60
+      desc: "Cluster hardware barrier 3 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB3TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 3 bitfield.
+                Hardware barrier 3 will be triggered only if for all HB3TM[i] = 1'b1,  HW_BARRIER_3_STATUS.HB3S[i]=1'b1.
+		HB3TM=0 means that hardware barrier 3 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_4_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x80
+      desc: "Cluster hardware barrier 4 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB4TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 4 bitfield.
+                Hardware barrier 4 will be triggered only if for all HB4TM[i] = 1'b1,  HW_BARRIER_4_STATUS.HB4S[i]=1'b1.
+		HB4TM=0 means that hardware barrier 4 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_5_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xA0
+      desc: "Cluster hardware barrier 5 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB5TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 5 bitfield.
+                Hardware barrier 5 will be triggered only if for all HB5TM[i] = 1'b1,  HW_BARRIER_5_STATUS.HB5S[i]=1'b1.
+		HB5TM=0 means that hardware barrier 5 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_6_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xC0
+      desc: "Cluster hardware barrier 6 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB6TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 6 bitfield.
+                Hardware barrier 6 will be triggered only if for all HB6TM[i] = 1'b1,  HW_BARRIER_6_STATUS.HB6S[i]=1'b1.
+		HB6TM=0 means that hardware barrier 6 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_7_TRIG_MASK" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xE0
+      desc: "Cluster hardware barrier 7 trigger mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "7:0"
+          name: "HB7TM"
+          resval: 0x0
+          desc: '''Trigger mask for hardware barrier 7 bitfield.
+                Hardware barrier 7 will be triggered only if for all HB7TM[i] = 1'b1,  HW_BARRIER_7_STATUS.HB7S[i]=1'b1.
+		HB7TM=0 means that hardware barrier 7 is disabled.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x4
+      desc: "Cluster hardware barrier 0 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 0 bitfield.
+	        HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 0.
+		It is cleared when HBS matches HW_BARRIER_0_TRIG_MASK.HB0TM.
+		'''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x24
+      desc: "Cluster hardware barrier 1 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 1 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 1.
+	        It is cleared when HBS matches HW_BARRIER_1_TRIG_MASK.HB1TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_2_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x44
+      desc: "Cluster hardware barrier 2 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 2 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 2.
+	        It is cleared when HBS matches HW_BARRIER_2_TRIG_MASK.HB2TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_3_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x64
+      desc: "Cluster hardware barrier 3 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 3 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 3.
+	        It is cleared when HBS matches HW_BARRIER_3_TRIG_MASK.HB3TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_4_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x84
+      desc: "Cluster hardware barrier 4 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 4 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 4.
+	        It is cleared when HBS matches HW_BARRIER_4_TRIG_MASK.HB4TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_5_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xA4
+      desc: "Cluster hardware barrier 5 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 5 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 5.
+	        It is cleared when HBS matches HW_BARRIER_5_TRIG_MASK.HB5TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_6_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xC4
+      desc: "Cluster hardware barrier 6 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 6 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 6.
+	        It is cleared when HBS matches HW_BARRIER_6_TRIG_MASK.HB6TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_7_STATUS" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xE4
+      desc: "Cluster hardware barrier 7 status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBS"
+          resval: 0x0
+          desc: '''Current status of hardware barrier 7 bitfield.
+                HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 7.
+	        It is cleared when HBS matches HW_BARRIER_7_TRIG_MASK.HB7TM.
+                '''
+        }
+      ]
+    }
+    { name: "HW_BARRIER_0_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 0. HBSS[i] represents a summary of the barrier status for core i."
+        }
+      ]
+    }
+    { name: "HW_BARRIER_1_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x28
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 1. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_2_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x48
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 2. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_3_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x68
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 3. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_4_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0x88
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 4. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_5_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xA8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 5. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_6_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xC8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 6. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+    { name: "HW_BARRIER_7_STATUS_SUM" // periph base address offset : 0x400, demux base address offset : 0x200, Address : 0xE8
+      desc: "Cluster hardware barrier summary status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "7:0"
+          name: "HBSS"
+          resval: 0x0
+          desc: "Current status of hardware barrier 7. HBSS[i] represents a summary of the barrier status for core i."
+	}	
+      ]
+    }
+
+
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+
+
+    { name: "FETCH_EN"
+      desc: "Cluster cores fetch enable configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+      ]
+    }
+    { name: "CLOCK_GATE"
+      desc: "Cluster clock gate configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "EN"
+          resval: 0x0
+          desc: '''Cluster clock gate configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+      ]
+    }
+    { name: "DBG_RESUME"
+      desc: "Cluster cores debug resume register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 0
+                '''
+        }
+	{ bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 1
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 2
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 3
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 4
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 5
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 6
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 7
+                '''
+        }
+      ]
+    }
+    { name: "DBG_HALT_STATUS"
+      desc: "Cluster cores debug halt status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 debug halt status flag bitfield:
+                - 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+        { bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 debug halt status flag bitfield:
+                - 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+      ]
+    }
+    { name: "DBG_HALT_MASK"
+      desc: "Cluster cores debug halt mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 debug halt mask bitfield. When bit is set,
+	        core will be part of mask group and stopped when one
+		of the members of the group stops.
+		'''
+        }
+	{ bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc:	'''Core 1 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc:	'''Core 2 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc:	'''Core 3 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc:	'''Core 4 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc:	'''Core 5 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc:	'''Core 6 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc:	'''Core 7 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+      ]
+    }
+    { name: "BOOT_ADDR0"
+      desc: "Cluster core 0 boot address configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "BA"
+          resval: 0x0
+          desc: "Cluster core 0 boot address configuration bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH0"
+      desc: "TCDM arbitration policy ch0 for cluster cores configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc: '''TCDM arbitration policy for cluster cores configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+                '''
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH1"
+      desc: "TCDM arbitration policy ch1 for DMA/HWCE configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc:	'''TCDM arbitration policy for DMA/HWCE configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+      	      	'''
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH0_REP"
+      desc: "Read only duplicate of TCDM_ARB_POLICY_CH0 register"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc: '''TCDM arbitration policy for cluster cores configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+                '''
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH1_REP"
+      desc: "Read only duplicate of TCDM_ARB_POLICY_CH1 register"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc: '''TCDM arbitration policy for DMA/HWCE configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/cluster_peripherals/cl_event_unit/doc/registers.md b/docs/um/ip/cluster_peripherals/cl_event_unit/doc/registers.md
new file mode 100644
index 00000000..b894546f
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cl_event_unit/doc/registers.md
@@ -0,0 +1,2032 @@
+## Summary
+
+| Name                                                                               | Offset   |   Length | Description                                                                                        |
+|:-----------------------------------------------------------------------------------|:---------|---------:|:---------------------------------------------------------------------------------------------------|
+| cluster_event_unit.[`EVT_MASK`](#evt_mask)                                         | 0x0      |        4 | Input event mask configuration register.                                                           |
+| cluster_event_unit.[`EVT_MASK_AND`](#evt_mask_and)                                 | 0x4      |        4 | Input event mask update command register with bitwise AND operation.                               |
+| cluster_event_unit.[`EVT_MASK_OR`](#evt_mask_or)                                   | 0x8      |        4 | Input event mask update command register with bitwise OR operation.                                |
+| cluster_event_unit.[`IRQ_MASK`](#irq_mask)                                         | 0xc      |        4 | Interrupt request mask configuration register.                                                     |
+| cluster_event_unit.[`IRQ_MASK_AND`](#irq_mask_and)                                 | 0x10     |        4 | Interrupt request mask update command register with bitwise AND operation.                         |
+| cluster_event_unit.[`IRQ_MASK_OR`](#irq_mask_or)                                   | 0x14     |        4 | Interrupt request mask update command register with bitwise OR operation.                          |
+| cluster_event_unit.[`CLOCK_STATUS`](#clock_status)                                 | 0x18     |        4 | Cluster cores clock status register.                                                               |
+| cluster_event_unit.[`EVENT_BUFFER`](#event_buffer)                                 | 0x1c     |        4 | Pending input events status register.                                                              |
+| cluster_event_unit.[`EVENT_BUFFER_MASKED`](#event_buffer_masked)                   | 0x20     |        4 | Pending input events status register with EVT_MASK applied.                                        |
+| cluster_event_unit.[`EVENT_BUFFER_IRQ_MASKED`](#event_buffer_irq_masked)           | 0x24     |        4 | Pending input events status register with IRQ_MASK applied.                                        |
+| cluster_event_unit.[`EVENT_BUFFER_CLEAR`](#event_buffer_clear)                     | 0x28     |        4 | Pending input events status clear command register.                                                |
+| cluster_event_unit.[`SW_EVENT_MASK`](#sw_event_mask)                               | 0x2c     |        4 | Software events cluster cores destination mask configuration register.                             |
+| cluster_event_unit.[`SW_EVENT_MASK_AND`](#sw_event_mask_and)                       | 0x30     |        4 | Software events cluster cores destination mask update command register with bitwise AND operation. |
+| cluster_event_unit.[`SW_EVENT_MASK_OR`](#sw_event_mask_or)                         | 0x34     |        4 | Software events cluster cores destination mask update command register with bitwise OR operation.  |
+| cluster_event_unit.[`EVENT_WAIT`](#event_wait)                                     | 0x38     |        4 | Input event wait command register.                                                                 |
+| cluster_event_unit.[`EVENT_WAIT_CLEAR`](#event_wait_clear)                         | 0x3c     |        4 | Input event wait and clear command register.                                                       |
+| cluster_event_unit.[`HW_DISPATCH_PUSH_TASK`](#hw_dispatch_push_task)               | 0x40     |        4 | Hardware task dispatcher push command register.                                                    |
+| cluster_event_unit.[`HW_DISPATCH_POP_TASK`](#hw_dispatch_pop_task)                 | 0x44     |        4 | Hardware task dispatcher pop command register.                                                     |
+| cluster_event_unit.[`HW_DISPATCH_PUSH_TEAM_CONFIG`](#hw_dispatch_push_team_config) | 0x48     |        4 | Hardware task dispatcher cluster core team configuration register.                                 |
+| cluster_event_unit.[`HW_MUTEX_0_MSG_PUT`](#hw_mutex_0_msg_put)                     | 0x4c     |        4 | Hardware mutex 0 non-blocking put command register.                                                |
+| cluster_event_unit.[`HW_MUTEX_0_MSG_GET`](#hw_mutex_0_msg_get)                     | 0x50     |        4 | Hardware mutex 0 blocking get command register.                                                    |
+| cluster_event_unit.[`HW_MUTEX_1_MSG_PUT`](#hw_mutex_1_msg_put)                     | 0x54     |        4 | Hardware mutex 1 non-blocking put command register.                                                |
+| cluster_event_unit.[`HW_MUTEX_1_MSG_GET`](#hw_mutex_1_msg_get)                     | 0x58     |        4 | Hardware mutex 1 blocking get command register.                                                    |
+| cluster_event_unit.[`SW_EVENT_0_TRIG`](#sw_event_0_trig)                           | 0x5c     |        4 | Cluster Software event 0 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_1_TRIG`](#sw_event_1_trig)                           | 0x60     |        4 | Cluster Software event 1 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_2_TRIG`](#sw_event_2_trig)                           | 0x64     |        4 | Cluster Software event 2 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_3_TRIG`](#sw_event_3_trig)                           | 0x68     |        4 | Cluster Software event 3 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_4_TRIG`](#sw_event_4_trig)                           | 0x6c     |        4 | Cluster Software event 4 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_5_TRIG`](#sw_event_5_trig)                           | 0x70     |        4 | Cluster Software event 5 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_6_TRIG`](#sw_event_6_trig)                           | 0x74     |        4 | Cluster Software event 6 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_7_TRIG`](#sw_event_7_trig)                           | 0x78     |        4 | Cluster Software event 7 trigger command register.                                                 |
+| cluster_event_unit.[`SW_EVENT_0_TRIG_WAIT`](#sw_event_0_trig_wait)                 | 0x7c     |        4 | Cluster Software event 0 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_1_TRIG_WAIT`](#sw_event_1_trig_wait)                 | 0x80     |        4 | Cluster Software event 1 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_2_TRIG_WAIT`](#sw_event_2_trig_wait)                 | 0x84     |        4 | Cluster Software event 2 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_3_TRIG_WAIT`](#sw_event_3_trig_wait)                 | 0x88     |        4 | Cluster Software event 3 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_4_TRIG_WAIT`](#sw_event_4_trig_wait)                 | 0x8c     |        4 | Cluster Software event 4 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_5_TRIG_WAIT`](#sw_event_5_trig_wait)                 | 0x90     |        4 | Cluster Software event 5 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_6_TRIG_WAIT`](#sw_event_6_trig_wait)                 | 0x94     |        4 | Cluster Software event 6 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_7_TRIG_WAIT`](#sw_event_7_trig_wait)                 | 0x98     |        4 | Cluster Software event 7 trigger and wait command register.                                        |
+| cluster_event_unit.[`SW_EVENT_0_TRIG_WAIT_CLEAR`](#sw_event_0_trig_wait_clear)     | 0x9c     |        4 | Cluster Software event 0 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_1_TRIG_WAIT_CLEAR`](#sw_event_1_trig_wait_clear)     | 0xa0     |        4 | Cluster Software event 1 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_2_TRIG_WAIT_CLEAR`](#sw_event_2_trig_wait_clear)     | 0xa4     |        4 | Cluster Software event 2 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_3_TRIG_WAIT_CLEAR`](#sw_event_3_trig_wait_clear)     | 0xa8     |        4 | Cluster Software event 3 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_4_TRIG_WAIT_CLEAR`](#sw_event_4_trig_wait_clear)     | 0xac     |        4 | Cluster Software event 4 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_5_TRIG_WAIT_CLEAR`](#sw_event_5_trig_wait_clear)     | 0xb0     |        4 | Cluster Software event 5 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_6_TRIG_WAIT_CLEAR`](#sw_event_6_trig_wait_clear)     | 0xb4     |        4 | Cluster Software event 6 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SW_EVENT_7_TRIG_WAIT_CLEAR`](#sw_event_7_trig_wait_clear)     | 0xb8     |        4 | Cluster Software event 7 trigger, wait and clear command register.                                 |
+| cluster_event_unit.[`SOC_PERIPH_EVENT_ID`](#soc_periph_event_id)                   | 0xbc     |        4 | Cluster SoC peripheral event ID status register.                                                   |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG_MASK`](#hw_barrier_0_trig_mask)             | 0xc0     |        4 | Cluster hardware barrier 0 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG_MASK`](#hw_barrier_1_trig_mask)             | 0xc4     |        4 | Cluster hardware barrier 1 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG_MASK`](#hw_barrier_2_trig_mask)             | 0xc8     |        4 | Cluster hardware barrier 2 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG_MASK`](#hw_barrier_3_trig_mask)             | 0xcc     |        4 | Cluster hardware barrier 3 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG_MASK`](#hw_barrier_4_trig_mask)             | 0xd0     |        4 | Cluster hardware barrier 4 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG_MASK`](#hw_barrier_5_trig_mask)             | 0xd4     |        4 | Cluster hardware barrier 5 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG_MASK`](#hw_barrier_6_trig_mask)             | 0xd8     |        4 | Cluster hardware barrier 6 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG_MASK`](#hw_barrier_7_trig_mask)             | 0xdc     |        4 | Cluster hardware barrier 7 trigger mask configuration register.                                    |
+| cluster_event_unit.[`HW_BARRIER_0_STATUS`](#hw_barrier_0_status)                   | 0xe0     |        4 | Cluster hardware barrier 0 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_1_STATUS`](#hw_barrier_1_status)                   | 0xe4     |        4 | Cluster hardware barrier 1 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_2_STATUS`](#hw_barrier_2_status)                   | 0xe8     |        4 | Cluster hardware barrier 2 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_3_STATUS`](#hw_barrier_3_status)                   | 0xec     |        4 | Cluster hardware barrier 3 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_4_STATUS`](#hw_barrier_4_status)                   | 0xf0     |        4 | Cluster hardware barrier 4 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_5_STATUS`](#hw_barrier_5_status)                   | 0xf4     |        4 | Cluster hardware barrier 5 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_6_STATUS`](#hw_barrier_6_status)                   | 0xf8     |        4 | Cluster hardware barrier 6 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_7_STATUS`](#hw_barrier_7_status)                   | 0xfc     |        4 | Cluster hardware barrier 7 status register.                                                        |
+| cluster_event_unit.[`HW_BARRIER_0_STATUS_SUM`](#hw_barrier_0_status_sum)           | 0x100    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_1_STATUS_SUM`](#hw_barrier_1_status_sum)           | 0x104    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_2_STATUS_SUM`](#hw_barrier_2_status_sum)           | 0x108    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_3_STATUS_SUM`](#hw_barrier_3_status_sum)           | 0x10c    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_4_STATUS_SUM`](#hw_barrier_4_status_sum)           | 0x110    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_5_STATUS_SUM`](#hw_barrier_5_status_sum)           | 0x114    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_6_STATUS_SUM`](#hw_barrier_6_status_sum)           | 0x118    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_7_STATUS_SUM`](#hw_barrier_7_status_sum)           | 0x11c    |        4 | Cluster hardware barrier summary status register.                                                  |
+| cluster_event_unit.[`HW_BARRIER_0_TARGET_MASK`](#hw_barrier_0_target_mask)         | 0x120    |        4 | Cluster hardware barrier 0 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_1_TARGET_MASK`](#hw_barrier_1_target_mask)         | 0x124    |        4 | Cluster hardware barrier 1 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_2_TARGET_MASK`](#hw_barrier_2_target_mask)         | 0x128    |        4 | Cluster hardware barrier 2 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_3_TARGET_MASK`](#hw_barrier_3_target_mask)         | 0x12c    |        4 | Cluster hardware barrier 3 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_4_TARGET_MASK`](#hw_barrier_4_target_mask)         | 0x130    |        4 | Cluster hardware barrier 4 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_5_TARGET_MASK`](#hw_barrier_5_target_mask)         | 0x134    |        4 | Cluster hardware barrier 5 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_6_TARGET_MASK`](#hw_barrier_6_target_mask)         | 0x138    |        4 | Cluster hardware barrier 6 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_7_TARGET_MASK`](#hw_barrier_7_target_mask)         | 0x13c    |        4 | Cluster hardware barrier 7 target mask configuration register.                                     |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG`](#hw_barrier_0_trig)                       | 0x140    |        4 | Cluster hardware barrier 0 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG`](#hw_barrier_1_trig)                       | 0x144    |        4 | Cluster hardware barrier 1 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG`](#hw_barrier_2_trig)                       | 0x148    |        4 | Cluster hardware barrier 2 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG`](#hw_barrier_3_trig)                       | 0x14c    |        4 | Cluster hardware barrier 3 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG`](#hw_barrier_4_trig)                       | 0x150    |        4 | Cluster hardware barrier 4 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG`](#hw_barrier_5_trig)                       | 0x154    |        4 | Cluster hardware barrier 5 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG`](#hw_barrier_6_trig)                       | 0x158    |        4 | Cluster hardware barrier 6 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG`](#hw_barrier_7_trig)                       | 0x15c    |        4 | Cluster hardware barrier 7 trigger command register.                                               |
+| cluster_event_unit.[`HW_BARRIER_0_SELF_TRIG`](#hw_barrier_0_self_trig)             | 0x160    |        4 | Cluster hardware barrier 0 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_1_SELF_TRIG`](#hw_barrier_1_self_trig)             | 0x164    |        4 | Cluster hardware barrier 1 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_2_SELF_TRIG`](#hw_barrier_2_self_trig)             | 0x168    |        4 | Cluster hardware barrier 2 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_3_SELF_TRIG`](#hw_barrier_3_self_trig)             | 0x16c    |        4 | Cluster hardware barrier 3 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_4_SELF_TRIG`](#hw_barrier_4_self_trig)             | 0x170    |        4 | Cluster hardware barrier 4 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_5_SELF_TRIG`](#hw_barrier_5_self_trig)             | 0x174    |        4 | Cluster hardware barrier 5 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_6_SELF_TRIG`](#hw_barrier_6_self_trig)             | 0x178    |        4 | Cluster hardware barrier 6 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_7_SELF_TRIG`](#hw_barrier_7_self_trig)             | 0x17c    |        4 | Cluster hardware barrier 7 self trigger command register.                                          |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG_WAIT`](#hw_barrier_0_trig_wait)             | 0x180    |        4 | Cluster hardware barrier 0 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG_WAIT`](#hw_barrier_1_trig_wait)             | 0x184    |        4 | Cluster hardware barrier 1 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG_WAIT`](#hw_barrier_2_trig_wait)             | 0x188    |        4 | Cluster hardware barrier 2 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG_WAIT`](#hw_barrier_3_trig_wait)             | 0x18c    |        4 | Cluster hardware barrier 3 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG_WAIT`](#hw_barrier_4_trig_wait)             | 0x190    |        4 | Cluster hardware barrier 4 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG_WAIT`](#hw_barrier_5_trig_wait)             | 0x194    |        4 | Cluster hardware barrier 5 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG_WAIT`](#hw_barrier_6_trig_wait)             | 0x198    |        4 | Cluster hardware barrier 6 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG_WAIT`](#hw_barrier_7_trig_wait)             | 0x19c    |        4 | Cluster hardware barrier 7 trigger and wait command register.                                      |
+| cluster_event_unit.[`HW_BARRIER_0_TRIG_WAIT_CLEAR`](#hw_barrier_0_trig_wait_clear) | 0x1a0    |        4 | Cluster hardware barrier 0 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_1_TRIG_WAIT_CLEAR`](#hw_barrier_1_trig_wait_clear) | 0x1a4    |        4 | Cluster hardware barrier 1 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_2_TRIG_WAIT_CLEAR`](#hw_barrier_2_trig_wait_clear) | 0x1a8    |        4 | Cluster hardware barrier 2 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_3_TRIG_WAIT_CLEAR`](#hw_barrier_3_trig_wait_clear) | 0x1ac    |        4 | Cluster hardware barrier 3 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_4_TRIG_WAIT_CLEAR`](#hw_barrier_4_trig_wait_clear) | 0x1b0    |        4 | Cluster hardware barrier 4 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_5_TRIG_WAIT_CLEAR`](#hw_barrier_5_trig_wait_clear) | 0x1b4    |        4 | Cluster hardware barrier 5 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_6_TRIG_WAIT_CLEAR`](#hw_barrier_6_trig_wait_clear) | 0x1b8    |        4 | Cluster hardware barrier 6 trigger, wait and clear command register.                               |
+| cluster_event_unit.[`HW_BARRIER_7_TRIG_WAIT_CLEAR`](#hw_barrier_7_trig_wait_clear) | 0x1bc    |        4 | Cluster hardware barrier 7 trigger, wait and clear command register.                               |
+
+## EVT_MASK
+Input event mask configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EMCL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "EMINTCL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EMSOC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                      |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EMSOC   | Soc peripheral input event mask configuration bitfield: - EMSOC[i]=1'b0: Input event request i is masked - EMSOC[i]=1'b1: Input event request i is not masked    |
+|   30   |   rw   |   0x0   | EMINTCL | Inter-cluster input event mask configuration bitfield: - EMINTCL[i]=1'b0: Input event request i is masked - EMINTCL[i]=1'b1: Input event request i is not masked |
+|  29:0  |   rw   |   0x0   | EMCL    | Cluster internal input event mask configuration bitfield: - EMCL[i]=1'b0: Input event request i is masked - EMCL[i]=1'b1: Input event request i is not masked    |
+
+## EVT_MASK_AND
+Input event mask update command register with bitwise AND operation.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EMA", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | EMA    | Input event mask configuration bitfield update with bitwise AND operation. It allows clearing EMCL[i], EMINTCL[i] or EMSOC[i] if EMA[i]=1'b1. |
+
+## EVT_MASK_OR
+Input event mask update command register with bitwise OR operation.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EMO", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                 |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | EMO    | Input event mask configuration bitfield update with bitwise OR operation. It allows setting EMCL[i], EMINTCL[i] or EMSOC[i] if EMO[i]=1'b1. |
+
+## IRQ_MASK
+Interrupt request mask configuration register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IMCL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "IMINTCL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IMSOC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                   |
+|:------:|:------:|:-------:|:--------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | IMSOC   | Soc peripheral interrupt request mask configuration bitfield: - bit[i]=1'b0: Interrupt request i is masked - bit[i]=1'b1: Interrupt request i is not masked   |
+|   30   |   rw   |   0x0   | IMINTCL | Inter-cluster interrupt request mask configuration bitfield: - bit[i]=1'b0: Interrupt request i is masked - bit[i]=1'b1: Interrupt request i is not masked    |
+|  29:0  |   rw   |   0x0   | IMCL    | Cluster internal interrupt request mask configuration bitfield: - bit[i]=1'b0: Interrupt request i is masked - bit[i]=1'b1: Interrupt request i is not masked |
+
+## IRQ_MASK_AND
+Interrupt request mask update command register with bitwise AND operation.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IMA", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | IMA    | Interrupt request mask configuration bitfield update with bitwise AND operation. It allows clearing IMCL[i], IMINTCL[i] or IMSOC[i] if IMA[i]=1'b1. |
+
+## IRQ_MASK_OR
+Interrupt request mask update command register with bitwise OR operation.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IMO", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                       |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | IMO    | Interrupt request mask configuration bitfield update with bitwise OR operation. It allows setting IMCL[i], IMINTCL[i] or IMSOC[i] if IMO[i]=1'b1. |
+
+## CLOCK_STATUS
+Cluster cores clock status register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                       |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                          |
+|   0    |   ro   |   0x0   | CS     | Cluster core clock status bitfield: - 1'b0: Cluster core clocked is gated - 1'b1: Cluster core clocked is running |
+
+## EVENT_BUFFER
+Pending input events status register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EB", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                      |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EB     | Pending input events status bitfield. EB[i]=1'b1: one or more input event i request are pending. |
+
+## EVENT_BUFFER_MASKED
+Pending input events status register with EVT_MASK applied.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                             |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Pending input events status bitfield with EVT_MASK applied. EBM[i]=1'b1: one or more input event i request are pending. |
+
+## EVENT_BUFFER_IRQ_MASKED
+Pending input events status register with IRQ_MASK applied.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "IBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                       |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | IBM    | Pending input events status bitfield with IRQ_MASK applied. IBM[i]=1'b1:  one or more input events i are pending. |
+
+## EVENT_BUFFER_CLEAR
+Pending input events status clear command register.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBC", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | EBC    | Pending input events status clear command bitfield. It allows clearing EB[i] if EBC[i]=1'b1. |
+
+## SW_EVENT_MASK
+Software events cluster cores destination mask configuration register.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SWEM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                        |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                           |
+|  7:0   |   rw   |   0x0   | SWEM   | Software events mask configuration bitfield: - bit[i]=1'b0: software events are masked for CL_CORE[i] - bit[i]=1'b1: software events are not masked for CL_CORE[i] |
+
+## SW_EVENT_MASK_AND
+Software events cluster cores destination mask update command register with bitwise AND operation.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SWEMA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                   |
+|  7:0   |   wo   |   0x0   | SWEMA  | Software event mask configuration bitfield update with bitwise AND operation. It allows clearing SWEM[i] if SWEMA[i]=1'b1. |
+
+## SW_EVENT_MASK_OR
+Software events cluster cores destination mask update command register with bitwise OR operation.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SWEMO", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                 |
+|  7:0   |   wo   |   0x0   | SWEMO  | Software event mask configuration bitfield update with bitwise OR operation. It allows setting SWEM[i] if SWEMO[i]=1'b1. |
+
+## EVENT_WAIT
+Input event wait command register.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                 |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Reading this register will gate the Cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## EVENT_WAIT_CLEAR
+Input event wait and clear command register.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Reading this register has the same effect as reading EVENT_WAIT.EBM. In addition, EVENT_BUFFER.EB[i] bits are cleared if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_DISPATCH_PUSH_TASK
+Hardware task dispatcher push command register.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                  |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | MSG    | Message to dispatch to all cluster cores selected in HW_DISPATCH_PUSH_TEAM_CONFIG.CT configuration bitfield. |
+
+## HW_DISPATCH_POP_TASK
+Hardware task dispatcher pop command register.
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | MSG    | Message dispatched using HW_DISPATCH_PUSH_TASK command and popped by cluster core who issued HW_DISPATCH_POP_TASK command. |
+
+## HW_DISPATCH_PUSH_TEAM_CONFIG
+Hardware task dispatcher cluster core team configuration register.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CT", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                              |
+|  7:0   |   rw   |   0x0   | CT     | Cluster cores team selection configuration bitfield. It allows to transmit HW_DISPATCH_PUSH_TASK.MSG to cluster core i if CT[i]=1'b1. |
+
+## HW_MUTEX_0_MSG_PUT
+Hardware mutex 0 non-blocking put command register.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | MSG    | Message pushed when releasing hardware mutex 0 configuration bitfiled. It is a non-blocking access. |
+
+## HW_MUTEX_0_MSG_GET
+Hardware mutex 0 blocking get command register.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | MSG    | Message popped when taking hardware mutex 0 data bitfiled. It is a blocking access. |
+
+## HW_MUTEX_1_MSG_PUT
+Hardware mutex 1 non-blocking put command register.
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | MSG    | Message pushed when releasing hardware mutex 1 configuration bitfiled. It is a non-blocking access. |
+
+## HW_MUTEX_1_MSG_GET
+Hardware mutex 1 blocking get command register.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSG", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | MSG    | Message popped when taking hardware mutex 1 data bitfiled. It is a blocking access. |
+
+## SW_EVENT_0_TRIG
+Cluster Software event 0 trigger command register.
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW0T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW0T   | Triggers software event 0 for cluster core i if SW0T[i]=1'b1. |
+
+## SW_EVENT_1_TRIG
+Cluster Software event 1 trigger command register.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW1T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW1T   | Triggers software event 1 for cluster core i if SW1T[i]=1'b1. |
+
+## SW_EVENT_2_TRIG
+Cluster Software event 2 trigger command register.
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW2T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW2T   | Triggers software event 2 for cluster core i if SW2T[i]=1'b1. |
+
+## SW_EVENT_3_TRIG
+Cluster Software event 3 trigger command register.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW3T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW3T   | Triggers software event 3 for cluster core i if SW3T[i]=1'b1. |
+
+## SW_EVENT_4_TRIG
+Cluster Software event 4 trigger command register.
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW4T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW4T   | Triggers software event 4 for cluster core i if SW4T[i]=1'b1. |
+
+## SW_EVENT_5_TRIG
+Cluster Software event 5 trigger command register.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW5T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW5T   | Triggers software event 5 for cluster core i if SW5T[i]=1'b1. |
+
+## SW_EVENT_6_TRIG
+Cluster Software event 6 trigger command register.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW6T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW6T   | Triggers software event 6 for cluster core i if SW6T[i]=1'b1. |
+
+## SW_EVENT_7_TRIG
+Cluster Software event 7 trigger command register.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SW7T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                   |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                      |
+|  7:0   |   wo   |   0x0   | SW7T   | Triggers software event 7 for cluster core i if SW7T[i]=1'b1. |
+
+## SW_EVENT_0_TRIG_WAIT
+Cluster Software event 0 trigger and wait command register.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_1_TRIG_WAIT
+Cluster Software event 1 trigger and wait command register.
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_2_TRIG_WAIT
+Cluster Software event 2 trigger and wait command register.
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_3_TRIG_WAIT
+Cluster Software event 3 trigger and wait command register.
+- Offset: `0x88`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_4_TRIG_WAIT
+Cluster Software event 4 trigger and wait command register.
+- Offset: `0x8c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_5_TRIG_WAIT
+Cluster Software event 5 trigger and wait command register.
+- Offset: `0x90`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_6_TRIG_WAIT
+Cluster Software event 6 trigger and wait command register.
+- Offset: `0x94`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_7_TRIG_WAIT
+Cluster Software event 7 trigger and wait command register.
+- Offset: `0x98`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## SW_EVENT_0_TRIG_WAIT_CLEAR
+Cluster Software event 0 trigger, wait and clear command register.
+- Offset: `0x9c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_0_trig_wait_clear--ebm) |
+
+### SW_EVENT_0_TRIG_WAIT_CLEAR . EBM
+Triggers software event 0 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_1_TRIG_WAIT_CLEAR
+Cluster Software event 1 trigger, wait and clear command register.
+- Offset: `0xa0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_1_trig_wait_clear--ebm) |
+
+### SW_EVENT_1_TRIG_WAIT_CLEAR . EBM
+Triggers software event 1 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_2_TRIG_WAIT_CLEAR
+Cluster Software event 2 trigger, wait and clear command register.
+- Offset: `0xa4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_2_trig_wait_clear--ebm) |
+
+### SW_EVENT_2_TRIG_WAIT_CLEAR . EBM
+Triggers software event 2 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_3_TRIG_WAIT_CLEAR
+Cluster Software event 3 trigger, wait and clear command register.
+- Offset: `0xa8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_3_trig_wait_clear--ebm) |
+
+### SW_EVENT_3_TRIG_WAIT_CLEAR . EBM
+Triggers software event 3 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_4_TRIG_WAIT_CLEAR
+Cluster Software event 4 trigger, wait and clear command register.
+- Offset: `0xac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_4_trig_wait_clear--ebm) |
+
+### SW_EVENT_4_TRIG_WAIT_CLEAR . EBM
+Triggers software event 4 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_5_TRIG_WAIT_CLEAR
+Cluster Software event 5 trigger, wait and clear command register.
+- Offset: `0xb0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_5_trig_wait_clear--ebm) |
+
+### SW_EVENT_5_TRIG_WAIT_CLEAR . EBM
+Triggers software event 5 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_6_TRIG_WAIT_CLEAR
+Cluster Software event 6 trigger, wait and clear command register.
+- Offset: `0xb4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_6_trig_wait_clear--ebm) |
+
+### SW_EVENT_6_TRIG_WAIT_CLEAR . EBM
+Triggers software event 6 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SW_EVENT_7_TRIG_WAIT_CLEAR
+Cluster Software event 7 trigger, wait and clear command register.
+- Offset: `0xb8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#sw_event_7_trig_wait_clear--ebm) |
+
+### SW_EVENT_7_TRIG_WAIT_CLEAR . EBM
+Triggers software event 7 to all cluster cores targeted in SW_EVENT_MASK and gate the issuing cluster core clock until at least one unmasked event occurs.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## SOC_PERIPH_EVENT_ID
+Cluster SoC peripheral event ID status register.
+- Offset: `0xbc`
+- Reset default: `0x0`
+- Reset mask: `0x800000ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 23}, {"name": "VALID", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                      |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------|
+|   31   |   ro   |   0x0   | VALID  | Validity bit of SOC_PERIPH_EVENT_ID.ID bitfield. |
+|  30:8  |        |         |        | Reserved                                         |
+|  7:0   |   ro   |   0x0   | ID     | Oldest SoC peripheral event ID status bitfield.  |
+
+## HW_BARRIER_0_TRIG_MASK
+Cluster hardware barrier 0 trigger mask configuration register.
+- Offset: `0xc0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB0TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB0TM  | Trigger mask for hardware barrier 0 bitfield. Hardware barrier 0 will be triggered only if for all HB0TM[i] = 1'b1,  HW_BARRIER_0_STATUS.HB0S[i]=1'b1. HB0TM=0 means that hardware barrier 0 is disabled. |
+
+## HW_BARRIER_1_TRIG_MASK
+Cluster hardware barrier 1 trigger mask configuration register.
+- Offset: `0xc4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB1TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB1TM  | Trigger mask for hardware barrier 1 bitfield. Hardware barrier 1 will be triggered only if for all HB1TM[i] = 1'b1,  HW_BARRIER_1_STATUS.HB1S[i]=1'b1. HB1TM=0 means that hardware barrier 1 is disabled. |
+
+## HW_BARRIER_2_TRIG_MASK
+Cluster hardware barrier 2 trigger mask configuration register.
+- Offset: `0xc8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB2TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB2TM  | Trigger mask for hardware barrier 2 bitfield. Hardware barrier 2 will be triggered only if for all HB2TM[i] = 1'b1,  HW_BARRIER_2_STATUS.HB2S[i]=1'b1. HB2TM=0 means that hardware barrier 2 is disabled. |
+
+## HW_BARRIER_3_TRIG_MASK
+Cluster hardware barrier 3 trigger mask configuration register.
+- Offset: `0xcc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB3TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB3TM  | Trigger mask for hardware barrier 3 bitfield. Hardware barrier 3 will be triggered only if for all HB3TM[i] = 1'b1,  HW_BARRIER_3_STATUS.HB3S[i]=1'b1. HB3TM=0 means that hardware barrier 3 is disabled. |
+
+## HW_BARRIER_4_TRIG_MASK
+Cluster hardware barrier 4 trigger mask configuration register.
+- Offset: `0xd0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB4TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB4TM  | Trigger mask for hardware barrier 4 bitfield. Hardware barrier 4 will be triggered only if for all HB4TM[i] = 1'b1,  HW_BARRIER_4_STATUS.HB4S[i]=1'b1. HB4TM=0 means that hardware barrier 4 is disabled. |
+
+## HW_BARRIER_5_TRIG_MASK
+Cluster hardware barrier 5 trigger mask configuration register.
+- Offset: `0xd4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB5TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB5TM  | Trigger mask for hardware barrier 5 bitfield. Hardware barrier 5 will be triggered only if for all HB5TM[i] = 1'b1,  HW_BARRIER_5_STATUS.HB5S[i]=1'b1. HB5TM=0 means that hardware barrier 5 is disabled. |
+
+## HW_BARRIER_6_TRIG_MASK
+Cluster hardware barrier 6 trigger mask configuration register.
+- Offset: `0xd8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB6TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB6TM  | Trigger mask for hardware barrier 6 bitfield. Hardware barrier 6 will be triggered only if for all HB6TM[i] = 1'b1,  HW_BARRIER_6_STATUS.HB6S[i]=1'b1. HB6TM=0 means that hardware barrier 6 is disabled. |
+
+## HW_BARRIER_7_TRIG_MASK
+Cluster hardware barrier 7 trigger mask configuration register.
+- Offset: `0xdc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HB7TM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                  |
+|  7:0   |   rw   |   0x0   | HB7TM  | Trigger mask for hardware barrier 7 bitfield. Hardware barrier 7 will be triggered only if for all HB7TM[i] = 1'b1,  HW_BARRIER_7_STATUS.HB7S[i]=1'b1. HB7TM=0 means that hardware barrier 7 is disabled. |
+
+## HW_BARRIER_0_STATUS
+Cluster hardware barrier 0 status register.
+- Offset: `0xe0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 0 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 0. It is cleared when HBS matches HW_BARRIER_0_TRIG_MASK.HB0TM. |
+
+## HW_BARRIER_1_STATUS
+Cluster hardware barrier 1 status register.
+- Offset: `0xe4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 1 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 1. It is cleared when HBS matches HW_BARRIER_1_TRIG_MASK.HB1TM. |
+
+## HW_BARRIER_2_STATUS
+Cluster hardware barrier 2 status register.
+- Offset: `0xe8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 2 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 2. It is cleared when HBS matches HW_BARRIER_2_TRIG_MASK.HB2TM. |
+
+## HW_BARRIER_3_STATUS
+Cluster hardware barrier 3 status register.
+- Offset: `0xec`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 3 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 3. It is cleared when HBS matches HW_BARRIER_3_TRIG_MASK.HB3TM. |
+
+## HW_BARRIER_4_STATUS
+Cluster hardware barrier 4 status register.
+- Offset: `0xf0`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 4 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 4. It is cleared when HBS matches HW_BARRIER_4_TRIG_MASK.HB4TM. |
+
+## HW_BARRIER_5_STATUS
+Cluster hardware barrier 5 status register.
+- Offset: `0xf4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 5 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 5. It is cleared when HBS matches HW_BARRIER_5_TRIG_MASK.HB5TM. |
+
+## HW_BARRIER_6_STATUS
+Cluster hardware barrier 6 status register.
+- Offset: `0xf8`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 6 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 6. It is cleared when HBS matches HW_BARRIER_6_TRIG_MASK.HB6TM. |
+
+## HW_BARRIER_7_STATUS
+Cluster hardware barrier 7 status register.
+- Offset: `0xfc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                            |
+|  7:0   |   ro   |   0x0   | HBS    | Current status of hardware barrier 7 bitfield. HBS[i]=1'b1 means that cluster core i has triggered hardware barrier 7. It is cleared when HBS matches HW_BARRIER_7_TRIG_MASK.HB7TM. |
+
+## HW_BARRIER_0_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x100`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 0. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_1_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x104`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 1. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_2_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x108`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 2. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_3_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x10c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 3. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_4_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x110`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 4. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_5_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x114`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 5. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_6_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x118`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 6. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_7_STATUS_SUM
+Cluster hardware barrier summary status register.
+- Offset: `0x11c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBSS", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                          |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                             |
+|  7:0   |   ro   |   0x0   | HBSS   | Current status of hardware barrier 7. HBSS[i] represents a summary of the barrier status for core i. |
+
+## HW_BARRIER_0_TARGET_MASK
+Cluster hardware barrier 0 target mask configuration register.
+- Offset: `0x120`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 0 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 0 event when HW_BARRIER_0_STATUS will match HW_BARRIER_0_TRIG_MASK. |
+
+## HW_BARRIER_1_TARGET_MASK
+Cluster hardware barrier 1 target mask configuration register.
+- Offset: `0x124`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 1 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 1 event when HW_BARRIER_1_STATUS will match HW_BARRIER_1_TRIG_MASK. |
+
+## HW_BARRIER_2_TARGET_MASK
+Cluster hardware barrier 2 target mask configuration register.
+- Offset: `0x128`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 2 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 2 event when HW_BARRIER_2_STATUS will match HW_BARRIER_2_TRIG_MASK. |
+
+## HW_BARRIER_3_TARGET_MASK
+Cluster hardware barrier 3 target mask configuration register.
+- Offset: `0x12c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 3 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 3 event when HW_BARRIER_3_STATUS will match HW_BARRIER_3_TRIG_MASK. |
+
+## HW_BARRIER_4_TARGET_MASK
+Cluster hardware barrier 4 target mask configuration register.
+- Offset: `0x130`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 4 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 4 event when HW_BARRIER_4_STATUS will match HW_BARRIER_4_TRIG_MASK. |
+
+## HW_BARRIER_5_TARGET_MASK
+Cluster hardware barrier 5 target mask configuration register.
+- Offset: `0x134`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 5 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 5 event when HW_BARRIER_5_STATUS will match HW_BARRIER_5_TRIG_MASK. |
+
+## HW_BARRIER_6_TARGET_MASK
+Cluster hardware barrier 6 target mask configuration register.
+- Offset: `0x138`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 6 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 6 event when HW_BARRIER_6_STATUS will match HW_BARRIER_6_TRIG_MASK. |
+
+## HW_BARRIER_7_TARGET_MASK
+Cluster hardware barrier 7 target mask configuration register.
+- Offset: `0x13c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HBTAM", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                              |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                 |
+|  7:0   |   rw   |   0x0   | HBTAM  | Cluster hardware barrier 7 target mask configuration bitfield. HBATM[i]=1'b1 means that cluster core i will receive hardware barrier 7 event when HW_BARRIER_7_STATUS will match HW_BARRIER_7_TRIG_MASK. |
+
+## HW_BARRIER_0_TRIG
+Cluster hardware barrier 0 trigger command register.
+- Offset: `0x140`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_0_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_1_TRIG
+Cluster hardware barrier 1 trigger command register.
+- Offset: `0x144`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_1_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_2_TRIG
+Cluster hardware barrier 2 trigger command register.
+- Offset: `0x148`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_2_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_3_TRIG
+Cluster hardware barrier 3 trigger command register.
+- Offset: `0x14c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_3_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_4_TRIG
+Cluster hardware barrier 4 trigger command register.
+- Offset: `0x150`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_4_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_5_TRIG
+Cluster hardware barrier 5 trigger command register.
+- Offset: `0x154`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_5_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_6_TRIG
+Cluster hardware barrier 6 trigger command register.
+- Offset: `0x158`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_6_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_7_TRIG
+Cluster hardware barrier 7 trigger command register.
+- Offset: `0x15c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                             |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                |
+|  7:0   |   wo   |   0x0   | T      | Sets HW_BARRIER_7_STATUS.HBS[i] to 1'b1 when T[i]=1'b1. |
+
+## HW_BARRIER_0_SELF_TRIG
+Cluster hardware barrier 0 self trigger command register.
+- Offset: `0x160`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_0_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_1_SELF_TRIG
+Cluster hardware barrier 1 self trigger command register.
+- Offset: `0x164`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_1_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_2_SELF_TRIG
+Cluster hardware barrier 2 self trigger command register.
+- Offset: `0x168`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_2_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_3_SELF_TRIG
+Cluster hardware barrier 3 self trigger command register.
+- Offset: `0x16c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_3_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_4_SELF_TRIG
+Cluster hardware barrier 4 self trigger command register.
+- Offset: `0x170`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_4_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_5_SELF_TRIG
+Cluster hardware barrier 5 self trigger command register.
+- Offset: `0x174`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_5_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_6_SELF_TRIG
+Cluster hardware barrier 6 self trigger command register.
+- Offset: `0x178`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_6_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_7_SELF_TRIG
+Cluster hardware barrier 7 self trigger command register.
+- Offset: `0x17c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | T      | Sets HW_BARRIER_7_STATUS.HBS[i] to 1'b1 when issued by cluster core i. |
+
+## HW_BARRIER_0_TRIG_WAIT
+Cluster hardware barrier 0 trigger and wait command register.
+- Offset: `0x180`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_0[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_0 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_1_TRIG_WAIT
+Cluster hardware barrier 1 trigger and wait command register.
+- Offset: `0x184`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_1[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_1 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_2_TRIG_WAIT
+Cluster hardware barrier 2 trigger and wait command register.
+- Offset: `0x188`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_2[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_2 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_3_TRIG_WAIT
+Cluster hardware barrier 3 trigger and wait command register.
+- Offset: `0x18c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_3[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_3 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_4_TRIG_WAIT
+Cluster hardware barrier 4 trigger and wait command register.
+- Offset: `0x190`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_4[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_4 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_5_TRIG_WAIT
+Cluster hardware barrier 5 trigger and wait command register.
+- Offset: `0x194`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_5[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_5 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_6_TRIG_WAIT
+Cluster hardware barrier 6 trigger and wait command register.
+- Offset: `0x198`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_6[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_6 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_7_TRIG_WAIT
+Cluster hardware barrier 7 trigger and wait command register.
+- Offset: `0x19c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:0  |   ro   |   0x0   | EBM    | Set HW_BARRIER_7[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_7 is released. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM |
+
+## HW_BARRIER_0_TRIG_WAIT_CLEAR
+Cluster hardware barrier 0 trigger, wait and clear command register.
+- Offset: `0x1a0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_0_trig_wait_clear--ebm) |
+
+### HW_BARRIER_0_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_0[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_0 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_1_TRIG_WAIT_CLEAR
+Cluster hardware barrier 1 trigger, wait and clear command register.
+- Offset: `0x1a4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_1_trig_wait_clear--ebm) |
+
+### HW_BARRIER_1_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_1[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_1 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_2_TRIG_WAIT_CLEAR
+Cluster hardware barrier 2 trigger, wait and clear command register.
+- Offset: `0x1a8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_2_trig_wait_clear--ebm) |
+
+### HW_BARRIER_2_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_2[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_2 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_3_TRIG_WAIT_CLEAR
+Cluster hardware barrier 3 trigger, wait and clear command register.
+- Offset: `0x1ac`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_3_trig_wait_clear--ebm) |
+
+### HW_BARRIER_3_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_3[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_3 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_4_TRIG_WAIT_CLEAR
+Cluster hardware barrier 4 trigger, wait and clear command register.
+- Offset: `0x1b0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_4_trig_wait_clear--ebm) |
+
+### HW_BARRIER_4_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_4[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_4 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_5_TRIG_WAIT_CLEAR
+Cluster hardware barrier 5 trigger, wait and clear command register.
+- Offset: `0x1b4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_5_trig_wait_clear--ebm) |
+
+### HW_BARRIER_5_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_5[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_5 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_6_TRIG_WAIT_CLEAR
+Cluster hardware barrier 6 trigger, wait and clear command register.
+- Offset: `0x1b8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_6_trig_wait_clear--ebm) |
+
+### HW_BARRIER_6_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_6[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_6 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
+## HW_BARRIER_7_TRIG_WAIT_CLEAR
+Cluster hardware barrier 7 trigger, wait and clear command register.
+- Offset: `0x1bc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EBM", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                      |
+|:------:|:------:|:-------:|:------------------------------------------|
+|  31:0  |   ro   |   0x0   | [EBM](#hw_barrier_7_trig_wait_clear--ebm) |
+
+### HW_BARRIER_7_TRIG_WAIT_CLEAR . EBM
+Set HW_BARRIER_7[i] when issued by cluster core i and gate the issuing cluster core i clock until HW_BARRIER_7 is released.
+In addition, EVENT_BUFFER.EB[i] bits are cleared after the read if EVT_MASK[i]=1'b1. The read content of this bitfield is equivalent to EVENT_BUFFER_MASKED.EBM
+
diff --git a/docs/um/ip/cluster_peripherals/cluster_ctrl_unit/data/cluster_crtl_unit_regs.hjson b/docs/um/ip/cluster_peripherals/cluster_ctrl_unit/data/cluster_crtl_unit_regs.hjson
new file mode 100644
index 00000000..0130c267
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cluster_ctrl_unit/data/cluster_crtl_unit_regs.hjson
@@ -0,0 +1,418 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Davide Rossi  <davide.rossi@unibo.it>
+
+{
+  name: "cluster_control_unit"
+  one_paragraph_desc: '''
+  CL_CTRL_UNIT component manages the following features:
+   - End of Computation status flag
+   - Configurable fetch activation for all cores of the Cluster
+   - Configurable core 0 boot address to define where to fetch first instruction in CL_CORE_0 after releasing the reset
+   - Configurable full cluster clock gating
+   - Configurable Cluster L1 memory arbitration policy
+   - Cluster cores resume command control
+   - Cluster cores halt status flags
+   - Configurable cluster cores debug halt command group mask policy
+  '''
+  cip_id:  "36",
+  version: "0.0.0" // null, commit c015839
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "EOC"
+      desc: "End Of Computation status register."
+      swaccess: "rw"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0:0"
+          name: "eoc"
+          resval: 0x0
+          desc: '''End of computation status flag bitfield:
+                - 1'b0: program execution under going
+                - 1'b1: end of computation reached
+		'''
+        }
+      ]
+    }
+    { name: "FETCH_EN"
+      desc: "Cluster cores fetch enable configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 fetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+      ]
+    }
+    { name: "CLOCK_GATE"
+      desc: "Cluster clock gate configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "EN"
+          resval: 0x0
+          desc: '''Cluster clock gate configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+      ]
+    }
+    { name: "DBG_RESUME"
+      desc: "Cluster cores debug resume register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 0
+                '''
+        }
+	{ bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 1
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 2
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 3
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 4
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 5
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 6
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 debug resume configuration bitfield:
+                - 1'b0: stay halted
+                - 1'b1: resume core 7
+                '''
+        }
+      ]
+    }
+    { name: "DBG_HALT_STATUS"
+      desc: "Cluster cores debug halt status register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 debug halt status flag bitfield:
+                - 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+        { bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 debug halt status flag bitfield:
+                - 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 debug halt status flag bitfield:
+		- 1'b0: running
+                - 1'b1: halted
+                '''
+        }
+      ]
+    }
+    { name: "DBG_HALT_MASK"
+      desc: "Cluster cores debug halt mask configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 debug halt mask bitfield. When bit is set,
+	        core will be part of mask group and stopped when one
+		of the members of the group stops.
+		'''
+        }
+	{ bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc:	'''Core 1 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc:	'''Core 2 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc:	'''Core 3 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc:	'''Core 4 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc:	'''Core 5 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc:	'''Core 6 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc:	'''Core 7 debug halt mask bitfield. When bit is set,
+                core will be part of mask group and stopped when one
+                of the members of the group stops.
+                '''
+        }
+      ]
+    }
+    { name: "BOOT_ADDR0"
+      desc: "Cluster core 0 boot address configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "BA"
+          resval: 0x0
+          desc: "Cluster core 0 boot address configuration bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH0"
+      desc: "TCDM arbitration policy ch0 for cluster cores configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc: '''TCDM arbitration policy for cluster cores configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+                '''
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH1"
+      desc: "TCDM arbitration policy ch1 for DMA/HWCE configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc:	'''TCDM arbitration policy for DMA/HWCE configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+      	      	'''
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH0_REP"
+      desc: "Read only duplicate of TCDM_ARB_POLICY_CH0 register"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc: '''TCDM arbitration policy for cluster cores configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+                '''
+        }
+      ]
+    }
+    { name: "TCDM_ARB_POLICY_CH1_REP"
+      desc: "Read only duplicate of TCDM_ARB_POLICY_CH1 register"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "POL"
+          resval: 0x0
+          desc: '''TCDM arbitration policy for DMA/HWCE configuration bitfield:
+                - 1'b0: fair round robin
+                - 1'b1: fixed order
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/cluster_peripherals/cluster_ctrl_unit/doc/registers.md b/docs/um/ip/cluster_peripherals/cluster_ctrl_unit/doc/registers.md
new file mode 100644
index 00000000..67fcdc95
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cluster_ctrl_unit/doc/registers.md
@@ -0,0 +1,230 @@
+## Summary
+
+| Name                                                                       | Offset   |   Length | Description                                                           |
+|:---------------------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------|
+| cluster_control_unit.[`EOC`](#eoc)                                         | 0x0      |        4 | End Of Computation status register.                                   |
+| cluster_control_unit.[`FETCH_EN`](#fetch_en)                               | 0x4      |        4 | Cluster cores fetch enable configuration register.                    |
+| cluster_control_unit.[`CLOCK_GATE`](#clock_gate)                           | 0x8      |        4 | Cluster clock gate configuration register.                            |
+| cluster_control_unit.[`DBG_RESUME`](#dbg_resume)                           | 0xc      |        4 | Cluster cores debug resume register.                                  |
+| cluster_control_unit.[`DBG_HALT_STATUS`](#dbg_halt_status)                 | 0x10     |        4 | Cluster cores debug halt status register.                             |
+| cluster_control_unit.[`DBG_HALT_MASK`](#dbg_halt_mask)                     | 0x14     |        4 | Cluster cores debug halt mask configuration register.                 |
+| cluster_control_unit.[`BOOT_ADDR0`](#boot_addr0)                           | 0x18     |        4 | Cluster core 0 boot address configuration register.                   |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH0`](#tcdm_arb_policy_ch0)         | 0x1c     |        4 | TCDM arbitration policy ch0 for cluster cores configuration register. |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH1`](#tcdm_arb_policy_ch1)         | 0x20     |        4 | TCDM arbitration policy ch1 for DMA/HWCE configuration register.      |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH0_REP`](#tcdm_arb_policy_ch0_rep) | 0x24     |        4 | Read only duplicate of TCDM_ARB_POLICY_CH0 register                   |
+| cluster_control_unit.[`TCDM_ARB_POLICY_CH1_REP`](#tcdm_arb_policy_ch1_rep) | 0x28     |        4 | Read only duplicate of TCDM_ARB_POLICY_CH1 register                   |
+
+## EOC
+End Of Computation status register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "eoc", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                       |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                          |
+|   0    |   rw   |   0x0   | eoc    | End of computation status flag bitfield: - 1'b0: program execution under going - 1'b1: end of computation reached |
+
+## FETCH_EN
+Cluster cores fetch enable configuration register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                     |
+|   7    |   rw   |   0x0   | CORE7  | Core 7 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   6    |   rw   |   0x0   | CORE6  | Core 6 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   5    |   rw   |   0x0   | CORE5  | Core 5 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   4    |   rw   |   0x0   | CORE4  | Core 4 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   3    |   rw   |   0x0   | CORE3  | Core 3 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   2    |   rw   |   0x0   | CORE2  | Core 2 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   1    |   rw   |   0x0   | CORE1  | Core 1 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   0    |   rw   |   0x0   | CORE0  | Core 0 fetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
+## CLOCK_GATE
+Cluster clock gate configuration register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                 |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                    |
+|   0    |   rw   |   0x0   | EN     | Cluster clock gate configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
+## DBG_RESUME
+Cluster cores debug resume register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                              |
+|   7    |   wo   |   0x0   | CORE7  | Core 7 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 7 |
+|   6    |   wo   |   0x0   | CORE6  | Core 6 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 6 |
+|   5    |   wo   |   0x0   | CORE5  | Core 5 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 5 |
+|   4    |   wo   |   0x0   | CORE4  | Core 4 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 4 |
+|   3    |   wo   |   0x0   | CORE3  | Core 3 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 3 |
+|   2    |   wo   |   0x0   | CORE2  | Core 2 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 2 |
+|   1    |   wo   |   0x0   | CORE1  | Core 1 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 1 |
+|   0    |   wo   |   0x0   | CORE0  | Core 0 debug resume configuration bitfield: - 1'b0: stay halted - 1'b1: resume core 0 |
+
+## DBG_HALT_STATUS
+Cluster cores debug halt status register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                               |
+|   7    |   ro   |   0x0   | CORE7  | Core 7 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   6    |   ro   |   0x0   | CORE6  | Core 6 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   5    |   ro   |   0x0   | CORE5  | Core 5 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   4    |   ro   |   0x0   | CORE4  | Core 4 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   3    |   ro   |   0x0   | CORE3  | Core 3 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   2    |   ro   |   0x0   | CORE2  | Core 2 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   1    |   ro   |   0x0   | CORE1  | Core 1 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+|   0    |   ro   |   0x0   | CORE0  | Core 0 debug halt status flag bitfield: - 1'b0: running - 1'b1: halted |
+
+## DBG_HALT_MASK
+Cluster cores debug halt mask configuration register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                               |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                  |
+|   7    |   rw   |   0x0   | CORE7  | Core 7 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   6    |   rw   |   0x0   | CORE6  | Core 6 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   5    |   rw   |   0x0   | CORE5  | Core 5 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   4    |   rw   |   0x0   | CORE4  | Core 4 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   3    |   rw   |   0x0   | CORE3  | Core 3 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   2    |   rw   |   0x0   | CORE2  | Core 2 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   1    |   rw   |   0x0   | CORE1  | Core 1 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+|   0    |   rw   |   0x0   | CORE0  | Core 0 debug halt mask bitfield. When bit is set, core will be part of mask group and stopped when one of the members of the group stops. |
+
+## BOOT_ADDR0
+Cluster core 0 boot address configuration register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "BA", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------|
+|  31:0  |   rw   |   0x0   | BA     | Cluster core 0 boot address configuration bitfield. |
+
+## TCDM_ARB_POLICY_CH0
+TCDM arbitration policy ch0 for cluster cores configuration register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                    |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                       |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for cluster cores configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
+## TCDM_ARB_POLICY_CH1
+TCDM arbitration policy ch1 for DMA/HWCE configuration register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                  |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for DMA/HWCE configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
+## TCDM_ARB_POLICY_CH0_REP
+Read only duplicate of TCDM_ARB_POLICY_CH0 register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                    |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                       |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for cluster cores configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
+## TCDM_ARB_POLICY_CH1_REP
+Read only duplicate of TCDM_ARB_POLICY_CH1 register
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "POL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                                  |
+|   0    |   rw   |   0x0   | POL    | TCDM arbitration policy for DMA/HWCE configuration bitfield: - 1'b0: fair round robin - 1'b1: fixed order |
+
diff --git a/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/data/cluster_icache_ctrl_regs.hjson b/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/data/cluster_icache_ctrl_regs.hjson
new file mode 100644
index 00000000..609ea93c
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/data/cluster_icache_ctrl_regs.hjson
@@ -0,0 +1,150 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Igor Loi  <igor.loi@unibo.it >
+
+
+{
+  name: "cluster_icache_ctrl"
+  one_paragraph_desc: '''CL_ICACHE_CTRL component manages the following features:
+                      - Bypassable Cluster instruction cache controller
+                      - Flush and selective flush commands   
+                      '''
+  cip_id:  "36",
+  version: "0.0.0" // null, commit c015839
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "ENABLE" // Address : 0x0
+      desc: "Cluster instruction cache unit enable configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "EN"
+          resval: 0x0
+          desc: '''Cluster instruction cache enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+		'''
+        }
+      ]
+    }
+    { name: "FLUSH" // Address : 0x4
+      desc: "Cluster instruction cache unit flush command register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "FL"
+          resval: 0x0
+          desc: "Cluster instruction cache full flush command."
+        }
+      ]
+    }
+    { name: "L0_FLUSH" // Address : 0x8
+      desc: "Cluster level 0 instruction cache unit flush command register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "L0_FL"
+          resval: 0x0
+          desc:	"Cluster level 0 instruction cache full flush command."
+        }
+      ]
+    }
+    { name: "SEL_FLUSH" // Address : 0xC
+      desc: "Cluster instruction cache unit selective flush command register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ADDR"
+          resval: 0x0
+          desc: "Cluster instruction cache selective flush address configuration bitfield."
+        }
+      ]
+    }
+
+
+    { name: "L1_L15_PREFETCH" // Address : 0x1C
+      desc: "Enable L1 and L1.5 prefetch register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 icache prefetch enable configuration bitfield:
+                 - 1'b0: disabled
+                 - 1'b1: enabled
+                '''
+        }
+        { bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/data/cluster_icache_ctrl_regs.hjson~ b/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/data/cluster_icache_ctrl_regs.hjson~
new file mode 100644
index 00000000..ca9a0299
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/data/cluster_icache_ctrl_regs.hjson~
@@ -0,0 +1,150 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Michael Gautschi  <gautschi@iis.ee.ethz.ch>
+
+
+{
+  name: "cluster_icache_ctrl"
+  one_paragraph_desc: '''CL_ICACHE_CTRL component manages the following features:
+                      - Bypassable Cluster instruction cache controller
+                      - Flush and selective flush commands   
+                      '''
+  cip_id:  "36",
+  version: "0.0.0" // null, commit c015839
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "ENABLE" // Address : 0x0
+      desc: "Cluster instruction cache unit enable configuration register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "EN"
+          resval: 0x0
+          desc: '''Cluster instruction cache enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+		'''
+        }
+      ]
+    }
+    { name: "FLUSH" // Address : 0x4
+      desc: "Cluster instruction cache unit flush command register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "FL"
+          resval: 0x0
+          desc: "Cluster instruction cache full flush command."
+        }
+      ]
+    }
+    { name: "L0_FLUSH" // Address : 0x8
+      desc: "Cluster level 0 instruction cache unit flush command register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "L0_FL"
+          resval: 0x0
+          desc:	"Cluster level 0 instruction cache full flush command."
+        }
+      ]
+    }
+    { name: "SEL_FLUSH" // Address : 0xC
+      desc: "Cluster instruction cache unit selective flush command register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ADDR"
+          resval: 0x0
+          desc: "Cluster instruction cache selective flush address configuration bitfield."
+        }
+      ]
+    }
+
+
+    { name: "L1_L15_PREFETCH" // Address : 0x1C
+      desc: "Enable L1 and L1.5 prefetch register."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          name: "CORE0"
+          resval: 0x0
+          desc: '''Core 0 icache prefetch enable configuration bitfield:
+                 - 1'b0: disabled
+                 - 1'b1: enabled
+                '''
+        }
+        { bits: "1"
+          name: "CORE1"
+          resval: 0x0
+          desc: '''Core 1 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "2"
+          name: "CORE2"
+          resval: 0x0
+          desc: '''Core 2 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "3"
+          name: "CORE3"
+          resval: 0x0
+          desc: '''Core 3 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "4"
+          name: "CORE4"
+          resval: 0x0
+          desc: '''Core 4 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "5"
+          name: "CORE5"
+          resval: 0x0
+          desc: '''Core 5 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "6"
+          name: "CORE6"
+          resval: 0x0
+          desc: '''Core 6 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+	{ bits: "7"
+          name: "CORE7"
+          resval: 0x0
+          desc: '''Core 7 icache prefetch enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/doc/registers.md b/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/doc/registers.md
new file mode 100644
index 00000000..0b62aa39
--- /dev/null
+++ b/docs/um/ip/cluster_peripherals/cluster_icache_ctrl/doc/registers.md
@@ -0,0 +1,101 @@
+## Summary
+
+| Name                                                      | Offset   |   Length | Description                                                      |
+|:----------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------|
+| cluster_icache_ctrl.[`ENABLE`](#enable)                   | 0x0      |        4 | Cluster instruction cache unit enable configuration register.    |
+| cluster_icache_ctrl.[`FLUSH`](#flush)                     | 0x4      |        4 | Cluster instruction cache unit flush command register.           |
+| cluster_icache_ctrl.[`L0_FLUSH`](#l0_flush)               | 0x8      |        4 | Cluster level 0 instruction cache unit flush command register.   |
+| cluster_icache_ctrl.[`SEL_FLUSH`](#sel_flush)             | 0xc      |        4 | Cluster instruction cache unit selective flush command register. |
+| cluster_icache_ctrl.[`L1_L15_PREFETCH`](#l1_l15_prefetch) | 0x10     |        4 | Enable L1 and L1.5 prefetch register.                            |
+
+## ENABLE
+Cluster instruction cache unit enable configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                               |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                                  |
+|   0    |   rw   |   0x0   | EN     | Cluster instruction cache enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
+## FLUSH
+Cluster instruction cache unit flush command register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                   |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------|
+|  31:1  |        |         |        | Reserved                                      |
+|   0    |   rw   |   0x0   | FL     | Cluster instruction cache full flush command. |
+
+## L0_FLUSH
+Cluster level 0 instruction cache unit flush command register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "L0_FL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                           |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                              |
+|   0    |   rw   |   0x0   | L0_FL  | Cluster level 0 instruction cache full flush command. |
+
+## SEL_FLUSH
+Cluster instruction cache unit selective flush command register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                               |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | ADDR   | Cluster instruction cache selective flush address configuration bitfield. |
+
+## L1_L15_PREFETCH
+Enable L1 and L1.5 prefetch register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CORE0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CORE7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                            |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                               |
+|   7    |   rw   |   0x0   | CORE7  | Core 7 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   6    |   rw   |   0x0   | CORE6  | Core 6 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   5    |   rw   |   0x0   | CORE5  | Core 5 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   4    |   rw   |   0x0   | CORE4  | Core 4 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   3    |   rw   |   0x0   | CORE3  | Core 3 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   2    |   rw   |   0x0   | CORE2  | Core 2 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   1    |   rw   |   0x0   | CORE1  | Core 1 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+|   0    |   rw   |   0x0   | CORE0  | Core 0 icache prefetch enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled |
+
diff --git a/docs/um/ip/ethernet/data/eth_framing_regs.hjson b/docs/um/ip/ethernet/data/eth_framing_regs.hjson
new file mode 100644
index 00000000..b025661c
--- /dev/null
+++ b/docs/um/ip/ethernet/data/eth_framing_regs.hjson
@@ -0,0 +1,65 @@
+{
+    name: "eth_framing",
+    clock_primary: "msoc_clk",
+    reset_primary: "rst_int",
+    bus_interfaces: [
+        { protocol: "reg_iface", direction: "device"}
+    ]
+    regwidth: "32",
+    registers: [
+        { name: "CONFIG0",
+          desc: "Configures the lower 4 bytes of the devices MAC address",
+          swaccess: "rw",
+          hwaccess: "hro",
+          fields: [
+              { bits: "31:0", name: "lower_mac_address",
+                desc: "Lower 32 bit of the devices MAC address"
+                resval: "8980226"
+              }
+          ]
+        },
+        { name: "CONFIG1",
+          desc: "Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface",
+          swaccess: "rw",
+          hwaccess: "hro",
+          fields: [
+              { bits: "15:0", name: "upper_mac_address",
+                desc: "Upper 16 bit of the devices MAC address"
+                resval: "8961"
+              },
+              { bits: "16", name: "promiscuous",
+                desc: "promiscuous flag"
+              },
+              { bits: "17", name: "phy_mdclk",
+                desc: "MDIO clock"
+              },
+              { bits: "18", name: "phy_mdio_o",
+                desc: "MDIO output"
+              },
+              { bits: "19", name: "phy_mdio_oe",
+                desc: "MDIO output enable"
+              }
+          ]
+        },
+        { name: "CONFIG2",
+          desc: "The FCS TX status",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          fields: [
+              { bits: "31:0", name: "tx_fcs_reg",
+                desc: "FCS TX status"
+              }
+          ]
+        },
+        { name: "CONFIG3",
+          desc: "The FCS RX status",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          fields: [
+              { bits: "31:0", name: "rx_fcs_reg",
+                desc: "FCS RX status"
+              }
+          ]
+        }
+    ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/ethernet/data/eth_framing_regs_doc.hjson b/docs/um/ip/ethernet/data/eth_framing_regs_doc.hjson
new file mode 100644
index 00000000..702fac60
--- /dev/null
+++ b/docs/um/ip/ethernet/data/eth_framing_regs_doc.hjson
@@ -0,0 +1,75 @@
+// Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Authors:
+
+{
+    name: "eth_framing",
+    cip_id: "36",
+    version: "0.0.0", // null, bdc8031
+    clocking: [
+    {clock: "clk_i", reset: "rst_int", idle: "idle_o", primary: true}
+    ],
+    bus_interfaces: [
+        { protocol: "tlul", direction: "device"}
+    ]
+    regwidth: "32",
+    registers: [
+        { name: "CONFIG0",
+          desc: "Configures the lower 4 bytes of the devices MAC address",
+          swaccess: "rw",
+          hwaccess: "hro",
+          fields: [
+              { bits: "31:0", name: "lower_mac_address",
+                desc: "Lower 32 bit of the devices MAC address"
+                resval: "8980226"
+              }
+          ]
+        },
+        { name: "CONFIG1",
+          desc: "Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface",
+          swaccess: "rw",
+          hwaccess: "hro",
+          fields: [
+              { bits: "15:0", name: "upper_mac_address",
+                desc: "Upper 16 bit of the devices MAC address"
+                resval: "8961"
+              },
+              { bits: "16", name: "promiscuous",
+                desc: "promiscuous flag"
+              },
+              { bits: "17", name: "phy_mdclk",
+                desc: "MDIO clock"
+              },
+              { bits: "18", name: "phy_mdio_o",
+                desc: "MDIO output"
+              },
+              { bits: "19", name: "phy_mdio_oe",
+                desc: "MDIO output enable"
+              }
+          ]
+        },
+        { name: "CONFIG2",
+          desc: "The FCS TX status",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          fields: [
+              { bits: "31:0", name: "tx_fcs_reg",
+                desc: "FCS TX status"
+              }
+          ]
+        },
+        { name: "CONFIG3",
+          desc: "The FCS RX status",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          fields: [
+              { bits: "31:0", name: "rx_fcs_reg",
+                desc: "FCS RX status"
+              }
+          ]
+        }
+    ]
+}
diff --git a/docs/um/ip/ethernet/data/eth_framing_regs_doc.hjson~ b/docs/um/ip/ethernet/data/eth_framing_regs_doc.hjson~
new file mode 100644
index 00000000..e4eadcf7
--- /dev/null
+++ b/docs/um/ip/ethernet/data/eth_framing_regs_doc.hjson~
@@ -0,0 +1,75 @@
+// Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Authors:
+
+{
+    name: "eth_framing",
+    cip_id: "36",
+    version: "0.0.0", // null
+    clocking: [
+    {clock: "clk_i", reset: "rst_int", idle: "idle_o", primary: true}
+    ],
+    bus_interfaces: [
+        { protocol: "tlul", direction: "device"}
+    ]
+    regwidth: "32",
+    registers: [
+        { name: "CONFIG0",
+          desc: "Configures the lower 4 bytes of the devices MAC address",
+          swaccess: "rw",
+          hwaccess: "hro",
+          fields: [
+              { bits: "31:0", name: "lower_mac_address",
+                desc: "Lower 32 bit of the devices MAC address"
+                resval: "8980226"
+              }
+          ]
+        },
+        { name: "CONFIG1",
+          desc: "Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface",
+          swaccess: "rw",
+          hwaccess: "hro",
+          fields: [
+              { bits: "15:0", name: "upper_mac_address",
+                desc: "Upper 16 bit of the devices MAC address"
+                resval: "8961"
+              },
+              { bits: "16", name: "promiscuous",
+                desc: "promiscuous flag"
+              },
+              { bits: "17", name: "phy_mdclk",
+                desc: "MDIO clock"
+              },
+              { bits: "18", name: "phy_mdio_o",
+                desc: "MDIO output"
+              },
+              { bits: "19", name: "phy_mdio_oe",
+                desc: "MDIO output enable"
+              }
+          ]
+        },
+        { name: "CONFIG2",
+          desc: "The FCS TX status",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          fields: [
+              { bits: "31:0", name: "tx_fcs_reg",
+                desc: "FCS TX status"
+              }
+          ]
+        },
+        { name: "CONFIG3",
+          desc: "The FCS RX status",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          fields: [
+              { bits: "31:0", name: "rx_fcs_reg",
+                desc: "FCS RX status"
+              }
+          ]
+        }
+    ]
+}
diff --git a/docs/um/ip/ethernet/doc/registers.md b/docs/um/ip/ethernet/doc/registers.md
new file mode 100644
index 00000000..e47d8063
--- /dev/null
+++ b/docs/um/ip/ethernet/doc/registers.md
@@ -0,0 +1,78 @@
+## Summary
+
+| Name                              | Offset   |   Length | Description                                                                                |
+|:----------------------------------|:---------|---------:|:-------------------------------------------------------------------------------------------|
+| eth_framing.[`CONFIG0`](#config0) | 0x0      |        4 | Configures the lower 4 bytes of the devices MAC address                                    |
+| eth_framing.[`CONFIG1`](#config1) | 0x4      |        4 | Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface |
+| eth_framing.[`CONFIG2`](#config2) | 0x8      |        4 | The FCS TX status                                                                          |
+| eth_framing.[`CONFIG3`](#config3) | 0xc      |        4 | The FCS RX status                                                                          |
+
+## CONFIG0
+Configures the lower 4 bytes of the devices MAC address
+- Offset: `0x0`
+- Reset default: `0x890702`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "lower_mac_address", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset   | Name              | Description                             |
+|:------:|:------:|:--------:|:------------------|:----------------------------------------|
+|  31:0  |   rw   | 0x890702 | lower_mac_address | Lower 32 bit of the devices MAC address |
+
+## CONFIG1
+Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface
+- Offset: `0x4`
+- Reset default: `0x2301`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "upper_mac_address", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "promiscuous", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdclk", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdio_o", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "phy_mdio_oe", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                             |
+|:------:|:------:|:-------:|:------------------|:----------------------------------------|
+| 31:20  |        |         |                   | Reserved                                |
+|   19   |   rw   |   0x0   | phy_mdio_oe       | MDIO output enable                      |
+|   18   |   rw   |   0x0   | phy_mdio_o        | MDIO output                             |
+|   17   |   rw   |   0x0   | phy_mdclk         | MDIO clock                              |
+|   16   |   rw   |   0x0   | promiscuous       | promiscuous flag                        |
+|  15:0  |   rw   | 0x2301  | upper_mac_address | Upper 16 bit of the devices MAC address |
+
+## CONFIG2
+The FCS TX status
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_fcs_reg", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   ro   |   0x0   | tx_fcs_reg | FCS TX status |
+
+## CONFIG3
+The FCS RX status
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rx_fcs_reg", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   ro   |   0x0   | rx_fcs_reg | FCS RX status |
+
diff --git a/docs/um/ip/fp_cluster/data/spatz_cluster_peripheral_reg.hjson b/docs/um/ip/fp_cluster/data/spatz_cluster_peripheral_reg.hjson
new file mode 100644
index 00000000..0be5f06a
--- /dev/null
+++ b/docs/um/ip/fp_cluster/data/spatz_cluster_peripheral_reg.hjson
@@ -0,0 +1,431 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+{
+    param_list: [
+        { name: "NumPerfCounters",
+        desc: "Number of performance counters",
+        type: "int",
+        default: "2"
+        },
+    ],
+    name: "spatz_cluster_peripheral",
+    clock_primary: "clk_i",
+    bus_interfaces: [
+        { protocol: "reg_iface", direction: "device"}
+    ]
+    regwidth: 64,
+    registers: [{
+        multireg: {
+            name: "PERF_COUNTER_ENABLE",
+            desc: "Enable particular performance counter and start tracking.",
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "performance_counter_enable",
+            fields: [{
+                bits: "0:0",
+                resval: "0",
+                name: "CYCLE",
+                desc: '''
+                    Cycle counter. Counts up as long as the cluster is powered.
+                    '''
+            },
+            {
+                bits: "1:1",
+                resval: "0",
+                name: "TCDM_ACCESSED"
+                desc: '''
+                        Increased whenever the TCDM is accessed. Each individual access is tracked,
+                        so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+                        so it doesn't matter whether the cores or the for example the SSR hardware accesses
+                        the TCDM. _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "2:2",
+                resval: "0",
+                name: "TCDM_CONGESTED"
+                desc: '''
+                        Incremented whenever an access twoards the TCDM is made but the arbitration
+                        logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+                        _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "3:3",
+                resval: "0",
+                name: "ISSUE_FPU"
+                desc: '''
+                        Core operations performed in the FPU. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "4:4",
+                resval: "0",
+                name: "ISSUE_FPU_SEQ"
+                desc: '''
+                        Incremented whenever the FPU Sequencer issues an FPU instruction.
+                        Might be non available if the hardware doesn't support FREP.
+                        _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "5:5",
+                resval: "0",
+                name: "ISSUE_CORE_TO_FPU"
+                desc: '''Incremented whenever the core issues an FPU instruction.
+                        _This is a hart-local signal._'''
+            },
+            {
+                bits: "6:6",
+                resval: "0",
+                name: "RETIRED_INSTR"
+                desc: '''
+                        Instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "7:7",
+                resval: "0",
+                name: "RETIRED_LOAD"
+                desc: '''
+                        Load instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "8:8",
+                resval: "0",
+                name: "RETIRED_I"
+                desc: '''
+                        Base instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "9:9",
+                resval: "0",
+                name: "RETIRED_ACC"
+                desc: '''
+                        Offloaded instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "10:10",
+                resval: "0",
+                name: "DMA_AW_STALL"
+                desc: '''
+                        Incremented whenever aw_valid = 1 but aw_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "11:11",
+                resval: "0",
+                name: "DMA_AR_STALL"
+                desc: '''
+                        Incremented whenever ar_valid = 1 but ar_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "12:12",
+                resval: "0",
+                name: "DMA_R_STALL"
+                desc: '''
+                        Incremented whenever r_ready = 1 but r_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "13:13",
+                resval: "0",
+                name: "DMA_W_STALL"
+                desc: '''
+                        Incremented whenever w_valid = 1 but w_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "14:14",
+                resval: "0",
+                name: "DMA_BUF_W_STALL"
+                desc: '''
+                        Incremented whenever w_ready = 1 but w_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "15:15",
+                resval: "0",
+                name: "DMA_BUF_R_STALL"
+                desc: '''
+                        Incremented whenever r_valid = 1 but r_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "16:16",
+                resval: "0",
+                name: "DMA_AW_DONE"
+                desc: '''
+                        Incremented whenever AW handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "17:17",
+                resval: "0",
+                name: "DMA_AW_BW"
+                desc: '''
+                        Whenever AW handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "18:18",
+                resval: "0",
+                name: "DMA_AR_DONE"
+                desc: '''
+                        Incremented whenever AR handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "19:19",
+                resval: "0",
+                name: "DMA_AR_BW"
+                desc: '''
+                        Whenever AR handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "20:20",
+                resval: "0",
+                name: "DMA_R_DONE"
+                desc: '''
+                        Incremented whenever R handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "21:21",
+                resval: "0",
+                name: "DMA_R_BW"
+                desc: '''
+                        Whenever R handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "22:22",
+                resval: "0",
+                name: "DMA_W_DONE"
+                desc: '''
+                        Incremented whenvever W handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "23:23",
+                resval: "0",
+                name: "DMA_W_BW"
+                desc: '''
+                        Whenever W handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "24:24",
+                resval: "0",
+                name: "DMA_B_DONE"
+                desc: '''
+                        Incremented whenever B handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "25:25",
+                resval: "0",
+                name: "DMA_BUSY"
+                desc: '''
+                        Incremented whenever DMA is busy.
+                        _This is a DMA-local signal_
+                        '''
+            },
+                        {
+                bits: "26:26",
+                resval: "0",
+                name: "ICACHE_MISS"
+                desc: '''
+                        Incremented for instruction cache misses.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "27:27",
+                resval: "0",
+                name: "ICACHE_HIT"
+                desc: '''
+                        Incremented for instruction cache hits.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "28:28",
+                resval: "0",
+                name: "ICACHE_PREFETCH"
+                desc: '''
+                        Incremented for instruction cache prefetches.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "29:29",
+                resval: "0",
+                name: "ICACHE_DOUBLE_HIT"
+                desc: '''
+                        Incremented for instruction cache double hit.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "30:30",
+                resval: "0",
+                name: "ICACHE_STALL"
+                desc: '''
+                        Incremented for instruction cache stalls.
+                        _This is a hart-local signal_
+                        '''
+            },
+            ]
+        }
+    },
+    {
+        multireg: {
+            name: "HART_SELECT",
+            desc: '''Select from which hart in the cluster, starting from `0`,
+                     the event should be counted. For each performance counter
+                     the cores can be selected individually. If a hart greater
+                     than the clusters total hart size is selected the selection
+                     will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+                     will be selected.'''
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "hart_select",
+            compact: "false",
+            fields: [{
+                bits: "9:0",
+                name: "HART_SELECT",
+                desc: "Select source of per-hart performance counter"
+            }]
+        }
+    }
+    {
+        multireg: {
+            name: "PERF_COUNTER",
+            desc: '''Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+            performance metric you would like to track.'''
+            swaccess: "rw",
+            hwaccess: "hrw",
+            count: "NumPerfCounters",
+            cname: "performance_counter",
+            hwext: "true",
+            hwqe: "true",
+            fields: [{
+                bits: "47:0",
+                name: "PERF_COUNTER",
+                desc: "Performance counter"
+            }]
+        }
+    },
+    {
+        name: "CL_CLINT_SET",
+        desc: '''
+        Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_SET",
+              desc: "Set cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "CL_CLINT_CLEAR",
+        desc: '''
+        Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_CLEAR",
+              desc: "Clear cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "HW_BARRIER",
+        desc: '''Hardware barrier register. Loads to this register will block until all cores have
+        performed the load. At this stage we know that they reached the same point in the control flow,
+        i.e., the cores are synchronized.'''
+        swaccess: "ro",
+        hwaccess: "hrw",
+        hwext: "true",
+        fields: [{
+            bits: "31:0",
+            name: "HW_BARRIER",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "ICACHE_PREFETCH_ENABLE",
+        desc: '''Controls prefetching of the instruction cache.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        resval: "1",
+        fields: [{
+            bits: "0:0",
+            name: "ICACHE_PREFETCH_ENABLE",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "SPATZ_STATUS",
+        desc: '''Sets the status of the Spatz cluster.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        fields: [{
+            bits: "0:0",
+            resval: "0",
+            name: "SPATZ_CLUSTER_PROBE",
+            desc: "Indicates the cluster is computing a kernel."
+        }]
+    },
+    {
+        name: "CLUSTER_BOOT_CONTROL",
+        desc: '''Controls the cluster boot process.'''
+        swaccess: "rw",
+        hwaccess: "hro",
+        resval: "0",
+        fields: [{
+            bits: "31:0",
+            name: "ENTRY_POINT",
+            desc: "Post-bootstrapping entry point."
+        }]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/fp_cluster/data/spatz_cluster_peripheral_reg_doc.hjson b/docs/um/ip/fp_cluster/data/spatz_cluster_peripheral_reg_doc.hjson
new file mode 100644
index 00000000..17337b00
--- /dev/null
+++ b/docs/um/ip/fp_cluster/data/spatz_cluster_peripheral_reg_doc.hjson
@@ -0,0 +1,435 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+{
+    param_list: [
+        { name: "NumPerfCounters",
+        desc: "Number of performance counters",
+        type: "int",
+        default: "2"
+        },
+    ],
+    name: "spatz_cluster_peripheral",
+    cip_id: "36",
+    version: "0.4.3",
+    clocking: [
+     {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+    ],
+    bus_interfaces: [
+        { protocol: "tlul", direction: "device"}
+    ]
+    regwidth: 64,
+    registers: [{
+        multireg: {
+            name: "PERF_COUNTER_ENABLE",
+            desc: "Enable particular performance counter and start tracking.",
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "performance_counter_enable",
+            fields: [{
+                bits: "0:0",
+                resval: "0",
+                name: "CYCLE",
+                desc: '''
+                    Cycle counter. Counts up as long as the cluster is powered.
+                    '''
+            },
+            {
+                bits: "1:1",
+                resval: "0",
+                name: "TCDM_ACCESSED"
+                desc: '''
+                        Increased whenever the TCDM is accessed. Each individual access is tracked,
+                        so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+                        so it doesn't matter whether the cores or the for example the SSR hardware accesses
+                        the TCDM. _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "2:2",
+                resval: "0",
+                name: "TCDM_CONGESTED"
+                desc: '''
+                        Incremented whenever an access twoards the TCDM is made but the arbitration
+                        logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+                        _This is a cluster-global signal._
+                        '''
+            },
+            {
+                bits: "3:3",
+                resval: "0",
+                name: "ISSUE_FPU"
+                desc: '''
+                        Core operations performed in the FPU. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "4:4",
+                resval: "0",
+                name: "ISSUE_FPU_SEQ"
+                desc: '''
+                        Incremented whenever the FPU Sequencer issues an FPU instruction.
+                        Might be non available if the hardware doesn't support FREP.
+                        _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "5:5",
+                resval: "0",
+                name: "ISSUE_CORE_TO_FPU"
+                desc: '''Incremented whenever the core issues an FPU instruction.
+                        _This is a hart-local signal._'''
+            },
+            {
+                bits: "6:6",
+                resval: "0",
+                name: "RETIRED_INSTR"
+                desc: '''
+                        Instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "7:7",
+                resval: "0",
+                name: "RETIRED_LOAD"
+                desc: '''
+                        Load instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "8:8",
+                resval: "0",
+                name: "RETIRED_I"
+                desc: '''
+                        Base instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "9:9",
+                resval: "0",
+                name: "RETIRED_ACC"
+                desc: '''
+                        Offloaded instructions retired by the core. _This is a hart-local signal._
+                        '''
+            },
+            {
+                bits: "10:10",
+                resval: "0",
+                name: "DMA_AW_STALL"
+                desc: '''
+                        Incremented whenever aw_valid = 1 but aw_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "11:11",
+                resval: "0",
+                name: "DMA_AR_STALL"
+                desc: '''
+                        Incremented whenever ar_valid = 1 but ar_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "12:12",
+                resval: "0",
+                name: "DMA_R_STALL"
+                desc: '''
+                        Incremented whenever r_ready = 1 but r_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "13:13",
+                resval: "0",
+                name: "DMA_W_STALL"
+                desc: '''
+                        Incremented whenever w_valid = 1 but w_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "14:14",
+                resval: "0",
+                name: "DMA_BUF_W_STALL"
+                desc: '''
+                        Incremented whenever w_ready = 1 but w_valid = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "15:15",
+                resval: "0",
+                name: "DMA_BUF_R_STALL"
+                desc: '''
+                        Incremented whenever r_valid = 1 but r_ready = 0.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "16:16",
+                resval: "0",
+                name: "DMA_AW_DONE"
+                desc: '''
+                        Incremented whenever AW handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "17:17",
+                resval: "0",
+                name: "DMA_AW_BW"
+                desc: '''
+                        Whenever AW handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "18:18",
+                resval: "0",
+                name: "DMA_AR_DONE"
+                desc: '''
+                        Incremented whenever AR handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "19:19",
+                resval: "0",
+                name: "DMA_AR_BW"
+                desc: '''
+                        Whenever AR handshake occurs, the counter is incremented
+                        by the number of bytes transfered for this transaction
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "20:20",
+                resval: "0",
+                name: "DMA_R_DONE"
+                desc: '''
+                        Incremented whenever R handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "21:21",
+                resval: "0",
+                name: "DMA_R_BW"
+                desc: '''
+                        Whenever R handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "22:22",
+                resval: "0",
+                name: "DMA_W_DONE"
+                desc: '''
+                        Incremented whenvever W handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "23:23",
+                resval: "0",
+                name: "DMA_W_BW"
+                desc: '''
+                        Whenever W handshake occurs, the counter is incremented
+                        by the number of bytes transfered in this cycle
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "24:24",
+                resval: "0",
+                name: "DMA_B_DONE"
+                desc: '''
+                        Incremented whenever B handshake occurs.
+                        _This is a DMA-local signal_
+                        '''
+            },
+            {
+                bits: "25:25",
+                resval: "0",
+                name: "DMA_BUSY"
+                desc: '''
+                        Incremented whenever DMA is busy.
+                        _This is a DMA-local signal_
+                        '''
+            },
+                        {
+                bits: "26:26",
+                resval: "0",
+                name: "ICACHE_MISS"
+                desc: '''
+                        Incremented for instruction cache misses.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "27:27",
+                resval: "0",
+                name: "ICACHE_HIT"
+                desc: '''
+                        Incremented for instruction cache hits.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "28:28",
+                resval: "0",
+                name: "ICACHE_PREFETCH"
+                desc: '''
+                        Incremented for instruction cache prefetches.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "29:29",
+                resval: "0",
+                name: "ICACHE_DOUBLE_HIT"
+                desc: '''
+                        Incremented for instruction cache double hit.
+                        _This is a hart-local signal_
+                        '''
+            },
+                        {
+                bits: "30:30",
+                resval: "0",
+                name: "ICACHE_STALL"
+                desc: '''
+                        Incremented for instruction cache stalls.
+                        _This is a hart-local signal_
+                        '''
+            },
+            ]
+        }
+    },
+    {
+        multireg: {
+            name: "HART_SELECT",
+            desc: '''Select from which hart in the cluster, starting from `0`,
+                     the event should be counted. For each performance counter
+                     the cores can be selected individually. If a hart greater
+                     than the clusters total hart size is selected the selection
+                     will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+                     will be selected.'''
+            swaccess: "rw",
+            hwaccess: "hro",
+            count: "NumPerfCounters",
+            cname: "hart_select",
+            compact: "false",
+            fields: [{
+                bits: "9:0",
+                name: "HART_SELECT",
+                desc: "Select source of per-hart performance counter"
+            }]
+        }
+    }
+    {
+        multireg: {
+            name: "PERF_COUNTER",
+            desc: '''Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+            performance metric you would like to track.'''
+            swaccess: "rw",
+            hwaccess: "hrw",
+            count: "NumPerfCounters",
+            cname: "performance_counter",
+            hwext: "true",
+            hwqe: "true",
+            fields: [{
+                bits: "47:0",
+                name: "PERF_COUNTER",
+                desc: "Performance counter"
+            }]
+        }
+    },
+    {
+        name: "CL_CLINT_SET",
+        desc: '''
+        Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_SET",
+              desc: "Set cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "CL_CLINT_CLEAR",
+        desc: '''
+        Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+        of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+        '''
+        hwext: "true",
+        hwqe: "true",
+        swaccess: "wo",
+        hwaccess: "hro",
+          fields: [{
+              bits: "31:0",
+              name: "CL_CLINT_CLEAR",
+              desc: "Clear cluster-local interrupt of hart i"
+          }]
+    },
+    {
+        name: "HW_BARRIER",
+        desc: '''Hardware barrier register. Loads to this register will block until all cores have
+        performed the load. At this stage we know that they reached the same point in the control flow,
+        i.e., the cores are synchronized.'''
+        swaccess: "ro",
+        hwaccess: "hrw",
+        hwext: "true",
+        fields: [{
+            bits: "31:0",
+            name: "HW_BARRIER",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "ICACHE_PREFETCH_ENABLE",
+        desc: '''Controls prefetching of the instruction cache.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        resval: "1",
+        fields: [{
+            bits: "0:0",
+            name: "ICACHE_PREFETCH_ENABLE",
+            desc: "Hardware barrier register."
+        }]
+    },
+    {
+        name: "SPATZ_STATUS",
+        desc: '''Sets the status of the Spatz cluster.'''
+        swaccess: "wo",
+        hwaccess: "hro",
+        fields: [{
+            bits: "0:0",
+            resval: "0",
+            name: "SPATZ_CLUSTER_PROBE",
+            desc: "Indicates the cluster is computing a kernel."
+        }]
+    },
+    {
+        name: "CLUSTER_BOOT_CONTROL",
+        desc: '''Controls the cluster boot process.'''
+        swaccess: "rw",
+        hwaccess: "hro",
+        resval: "0",
+        fields: [{
+            bits: "31:0",
+            name: "ENTRY_POINT",
+            desc: "Post-bootstrapping entry point."
+        }]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/fp_cluster/doc/registers.md b/docs/um/ip/fp_cluster/doc/registers.md
new file mode 100644
index 00000000..79bc211c
--- /dev/null
+++ b/docs/um/ip/fp_cluster/doc/registers.md
@@ -0,0 +1,386 @@
+## Summary
+
+| Name                                                                         | Offset   |   Length | Description                                                                                         |
+|:-----------------------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------|
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_0`](#perf_counter_enable)     | 0x0      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_ENABLE_1`](#perf_counter_enable)     | 0x8      |        8 | Enable particular performance counter and start tracking.                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_0`](#hart_select)                     | 0x10     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`HART_SELECT_1`](#hart_select)                     | 0x18     |        8 | Select from which hart in the cluster, starting from `0`,                                           |
+| spatz_cluster_peripheral.[`PERF_COUNTER_0`](#perf_counter)                   | 0x20     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`PERF_COUNTER_1`](#perf_counter)                   | 0x28     |        8 | Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what                   |
+| spatz_cluster_peripheral.[`CL_CLINT_SET`](#cl_clint_set)                     | 0x30     |        8 | Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt     |
+| spatz_cluster_peripheral.[`CL_CLINT_CLEAR`](#cl_clint_clear)                 | 0x38     |        8 | Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt |
+| spatz_cluster_peripheral.[`HW_BARRIER`](#hw_barrier)                         | 0x40     |        8 | Hardware barrier register. Loads to this register will block until all cores have                   |
+| spatz_cluster_peripheral.[`ICACHE_PREFETCH_ENABLE`](#icache_prefetch_enable) | 0x48     |        8 | Controls prefetching of the instruction cache.                                                      |
+| spatz_cluster_peripheral.[`SPATZ_STATUS`](#spatz_status)                     | 0x50     |        8 | Sets the status of the Spatz cluster.                                                               |
+| spatz_cluster_peripheral.[`CLUSTER_BOOT_CONTROL`](#cluster_boot_control)     | 0x58     |        8 | Controls the cluster boot process.                                                                  |
+
+## PERF_COUNTER_ENABLE
+Enable particular performance counter and start tracking.
+- Reset default: `0x0`
+- Reset mask: `0x7fffffff`
+
+### Instances
+
+| Name                  | Offset   |
+|:----------------------|:---------|
+| PERF_COUNTER_ENABLE_0 | 0x0      |
+| PERF_COUNTER_ENABLE_1 | 0x8      |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CYCLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_ACCESSED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCDM_CONGESTED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_FPU_SEQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ISSUE_CORE_TO_FPU", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_INSTR", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_LOAD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_I", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RETIRED_ACC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_W_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUF_R_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AW_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_AR_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_R_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_W_BW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_B_DONE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DMA_BUSY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_MISS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_PREFETCH", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_DOUBLE_HIT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ICACHE_STALL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 33}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                         |
+|:------:|:------:|:-------:|:-------------------------------------------------------------|
+| 63:31  |        |         | Reserved                                                     |
+|   30   |   rw   |   0x0   | [ICACHE_STALL](#perf_counter_enable--icache_stall)           |
+|   29   |   rw   |   0x0   | [ICACHE_DOUBLE_HIT](#perf_counter_enable--icache_double_hit) |
+|   28   |   rw   |   0x0   | [ICACHE_PREFETCH](#perf_counter_enable--icache_prefetch)     |
+|   27   |   rw   |   0x0   | [ICACHE_HIT](#perf_counter_enable--icache_hit)               |
+|   26   |   rw   |   0x0   | [ICACHE_MISS](#perf_counter_enable--icache_miss)             |
+|   25   |   rw   |   0x0   | [DMA_BUSY](#perf_counter_enable--dma_busy)                   |
+|   24   |   rw   |   0x0   | [DMA_B_DONE](#perf_counter_enable--dma_b_done)               |
+|   23   |   rw   |   0x0   | [DMA_W_BW](#perf_counter_enable--dma_w_bw)                   |
+|   22   |   rw   |   0x0   | [DMA_W_DONE](#perf_counter_enable--dma_w_done)               |
+|   21   |   rw   |   0x0   | [DMA_R_BW](#perf_counter_enable--dma_r_bw)                   |
+|   20   |   rw   |   0x0   | [DMA_R_DONE](#perf_counter_enable--dma_r_done)               |
+|   19   |   rw   |   0x0   | [DMA_AR_BW](#perf_counter_enable--dma_ar_bw)                 |
+|   18   |   rw   |   0x0   | [DMA_AR_DONE](#perf_counter_enable--dma_ar_done)             |
+|   17   |   rw   |   0x0   | [DMA_AW_BW](#perf_counter_enable--dma_aw_bw)                 |
+|   16   |   rw   |   0x0   | [DMA_AW_DONE](#perf_counter_enable--dma_aw_done)             |
+|   15   |   rw   |   0x0   | [DMA_BUF_R_STALL](#perf_counter_enable--dma_buf_r_stall)     |
+|   14   |   rw   |   0x0   | [DMA_BUF_W_STALL](#perf_counter_enable--dma_buf_w_stall)     |
+|   13   |   rw   |   0x0   | [DMA_W_STALL](#perf_counter_enable--dma_w_stall)             |
+|   12   |   rw   |   0x0   | [DMA_R_STALL](#perf_counter_enable--dma_r_stall)             |
+|   11   |   rw   |   0x0   | [DMA_AR_STALL](#perf_counter_enable--dma_ar_stall)           |
+|   10   |   rw   |   0x0   | [DMA_AW_STALL](#perf_counter_enable--dma_aw_stall)           |
+|   9    |   rw   |   0x0   | [RETIRED_ACC](#perf_counter_enable--retired_acc)             |
+|   8    |   rw   |   0x0   | [RETIRED_I](#perf_counter_enable--retired_i)                 |
+|   7    |   rw   |   0x0   | [RETIRED_LOAD](#perf_counter_enable--retired_load)           |
+|   6    |   rw   |   0x0   | [RETIRED_INSTR](#perf_counter_enable--retired_instr)         |
+|   5    |   rw   |   0x0   | [ISSUE_CORE_TO_FPU](#perf_counter_enable--issue_core_to_fpu) |
+|   4    |   rw   |   0x0   | [ISSUE_FPU_SEQ](#perf_counter_enable--issue_fpu_seq)         |
+|   3    |   rw   |   0x0   | [ISSUE_FPU](#perf_counter_enable--issue_fpu)                 |
+|   2    |   rw   |   0x0   | [TCDM_CONGESTED](#perf_counter_enable--tcdm_congested)       |
+|   1    |   rw   |   0x0   | [TCDM_ACCESSED](#perf_counter_enable--tcdm_accessed)         |
+|   0    |   rw   |   0x0   | [CYCLE](#perf_counter_enable--cycle)                         |
+
+### PERF_COUNTER_ENABLE . ICACHE_STALL
+  Incremented for instruction cache stalls.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_DOUBLE_HIT
+  Incremented for instruction cache double hit.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_PREFETCH
+  Incremented for instruction cache prefetches.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_HIT
+  Incremented for instruction cache hits.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . ICACHE_MISS
+  Incremented for instruction cache misses.
+  _This is a hart-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUSY
+  Incremented whenever DMA is busy.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_B_DONE
+  Incremented whenever B handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_BW
+  Whenever W handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_DONE
+  Incremented whenvever W handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_BW
+  Whenever R handshake occurs, the counter is incremented
+  by the number of bytes transfered in this cycle
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_DONE
+  Incremented whenever R handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_BW
+  Whenever AR handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_DONE
+  Incremented whenever AR handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_BW
+  Whenever AW handshake occurs, the counter is incremented
+  by the number of bytes transfered for this transaction
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_DONE
+  Incremented whenever AW handshake occurs.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_R_STALL
+  Incremented whenever r_valid = 1 but r_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_BUF_W_STALL
+  Incremented whenever w_ready = 1 but w_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_W_STALL
+  Incremented whenever w_valid = 1 but w_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_R_STALL
+  Incremented whenever r_ready = 1 but r_valid = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AR_STALL
+  Incremented whenever ar_valid = 1 but ar_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . DMA_AW_STALL
+  Incremented whenever aw_valid = 1 but aw_ready = 0.
+  _This is a DMA-local signal_
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_ACC
+  Offloaded instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_I
+  Base instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_LOAD
+  Load instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . RETIRED_INSTR
+  Instructions retired by the core. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_CORE_TO_FPU
+Incremented whenever the core issues an FPU instruction.
+  _This is a hart-local signal._
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU_SEQ
+  Incremented whenever the FPU Sequencer issues an FPU instruction.
+  Might be non available if the hardware doesn't support FREP.
+  _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . ISSUE_FPU
+  Core operations performed in the FPU. _This is a hart-local signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_CONGESTED
+  Incremented whenever an access twoards the TCDM is made but the arbitration
+  logic didn't grant the access (due to congestion). Is strictly less than TCDM_ACCESSED.
+  _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . TCDM_ACCESSED
+  Increased whenever the TCDM is accessed. Each individual access is tracked,
+  so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM,
+  so it doesn't matter whether the cores or the for example the SSR hardware accesses
+  the TCDM. _This is a cluster-global signal._
+  
+
+### PERF_COUNTER_ENABLE . CYCLE
+Cycle counter. Counts up as long as the cluster is powered.
+
+## HART_SELECT
+Select from which hart in the cluster, starting from `0`,
+   the event should be counted. For each performance counter
+   the cores can be selected individually. If a hart greater
+   than the clusters total hart size is selected the selection
+   will wrap and the hart corresponding to `hart_select % total_harts_in_cluster`
+   will be selected.
+- Reset default: `0x0`
+- Reset mask: `0x3ff`
+
+### Instances
+
+| Name          | Offset   |
+|:--------------|:---------|
+| HART_SELECT_0 | 0x10     |
+| HART_SELECT_1 | 0x18     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HART_SELECT", "bits": 10, "attr": ["rw"], "rotate": -90}, {"bits": 54}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                   |
+|:------:|:------:|:-------:|:------------|:----------------------------------------------|
+| 63:10  |        |         |             | Reserved                                      |
+|  9:0   |   rw   |   0x0   | HART_SELECT | Select source of per-hart performance counter |
+
+## PERF_COUNTER
+Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what
+performance metric you would like to track.
+- Reset default: `0x0`
+- Reset mask: `0xffffffffffff`
+
+### Instances
+
+| Name           | Offset   |
+|:---------------|:---------|
+| PERF_COUNTER_0 | 0x20     |
+| PERF_COUNTER_1 | 0x28     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PERF_COUNTER", "bits": 48, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description         |
+|:------:|:------:|:-------:|:-------------|:--------------------|
+| 63:48  |        |         |              | Reserved            |
+|  47:0  |   rw   |    x    | PERF_COUNTER | Performance counter |
+
+## CL_CLINT_SET
+Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_SET", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name         | Description                           |
+|:------:|:------:|:-------:|:-------------|:--------------------------------------|
+| 63:32  |        |         |              | Reserved                              |
+|  31:0  |   wo   |    x    | CL_CLINT_SET | Set cluster-local interrupt of hart i |
+
+## CL_CLINT_CLEAR
+Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
+of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CL_CLINT_CLEAR", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                             |
+|:------:|:------:|:-------:|:---------------|:----------------------------------------|
+| 63:32  |        |         |                | Reserved                                |
+|  31:0  |   wo   |    x    | CL_CLINT_CLEAR | Clear cluster-local interrupt of hart i |
+
+## HW_BARRIER
+Hardware barrier register. Loads to this register will block until all cores have
+performed the load. At this stage we know that they reached the same point in the control flow,
+i.e., the cores are synchronized.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HW_BARRIER", "bits": 32, "attr": ["ro"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                |
+|:------:|:------:|:-------:|:-----------|:---------------------------|
+| 63:32  |        |         |            | Reserved                   |
+|  31:0  |   ro   |    x    | HW_BARRIER | Hardware barrier register. |
+
+## ICACHE_PREFETCH_ENABLE
+Controls prefetching of the instruction cache.
+- Offset: `0x48`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ICACHE_PREFETCH_ENABLE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                |
+|:------:|:------:|:-------:|:-----------------------|:---------------------------|
+|  63:1  |        |         |                        | Reserved                   |
+|   0    |   wo   |   0x1   | ICACHE_PREFETCH_ENABLE | Hardware barrier register. |
+
+## SPATZ_STATUS
+Sets the status of the Spatz cluster.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SPATZ_CLUSTER_PROBE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description                                  |
+|:------:|:------:|:-------:|:--------------------|:---------------------------------------------|
+|  63:1  |        |         |                     | Reserved                                     |
+|   0    |   wo   |   0x0   | SPATZ_CLUSTER_PROBE | Indicates the cluster is computing a kernel. |
+
+## CLUSTER_BOOT_CONTROL
+Controls the cluster boot process.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENTRY_POINT", "bits": 32, "attr": ["rw"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                     |
+|:------:|:------:|:-------:|:------------|:--------------------------------|
+| 63:32  |        |         |             | Reserved                        |
+|  31:0  |   rw   |   0x0   | ENTRY_POINT | Post-bootstrapping entry point. |
+
diff --git a/docs/um/ip/gp_timer1_system_timer/data/timer_unit.hjson b/docs/um/ip/gp_timer1_system_timer/data/timer_unit.hjson
new file mode 100644
index 00000000..2065c2cb
--- /dev/null
+++ b/docs/um/ip/gp_timer1_system_timer/data/timer_unit.hjson
@@ -0,0 +1,282 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Florent Rotenberg <florent.rotenberg@greenwaves-technologies.com>
+# timer unit(system timer) register
+
+{
+  name: "timer_unit"
+  one_paragraph_desc: '''
+  BASIC TIMER component manages the following features:
+  - 2 general purpose 32bits up counter timers
+  - Input trigger sources:
+       - FLL clock
+       - FLL clock + Prescaler
+       - Reference clock at 32kHz
+       - External event
+  - 8bit programmable prescaler to FLL clock
+  - Counting modes:
+       - One shot mode: timer is stopped after first comparison match
+       - Continuous mode: timer continues counting after comparison match
+       - Cycle mode: timer resets to 0 after comparison match and continues counting
+       - 64 bit cascaded mode
+  - Interrupt request generation on comparison match
+  '''
+  cip_id:  "36",
+  version: "1.0.3"
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "CFG_LO"
+      desc: "Timer Low Configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0"
+          name: "ENABLE"
+          resval: 0x0
+          desc: '''Timer low enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+		'''
+        }
+        { bits: "1"
+          name: "RESET"
+          resval: 0x0
+          desc: "Timer low counter reset command bitfield. Cleared after Timer Low reset execution."
+        }
+        { bits: "2"
+          name: "IRQEN"
+          resval: 0x0
+          desc: '''Timer low compare match interrupt enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "3"
+          name: "IEM"
+          resval: 0x0
+          desc: '''Timer low input event mask configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "4"
+          name: "MODE"
+          resval: 0x0
+          desc: '''Timer low continuous mode configuration bitfield:
+                - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs.
+                - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs.
+                '''
+        }
+        { bits: "5"
+          name: "ONE_S"
+          resval: 0x0
+          desc: '''Timer low one shot configuration bitfield:
+                - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs.
+                - 1'b1: disable Timer low when compare match with CMP_LO occurs.
+                '''
+        }
+        { bits: "6"
+          name: "PEN"
+          resval: 0x0
+          desc: '''Timer low prescaler enable configuration bitfield:
+	        - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "7"
+          name: "CCFG"
+          resval: 0x0
+          desc: '''Timer low clock source configuration bitfield:
+                - 1'b0: FLL or FLL+Prescaler
+                - 1'b1: Reference clock at 32kHz
+                '''
+        }
+	{ bits: "15:8"
+          name: "PVAL"
+          resval: 0x0
+          desc: "Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL)"
+        }
+	{ bits: "31"
+          name: "CASC"
+          resval: 0x0
+          desc: "Timer low  + Timer high 64bit cascaded mode configuration bitfield."
+        }
+      ]
+    }
+    { name: "CFG_HI"
+      desc: "Timer HIGH Configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0"
+          name: "ENABLE"
+          resval: 0x0
+          desc: '''Timer high enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "1"
+          name: "RESET"
+	  swaccess: "wo"
+          hwaccess: "hro"
+          resval: 0x0
+          desc: "Timer high counter reset command bitfield. Cleared after Timer high reset execution."
+        }
+        { bits: "2"
+          name: "IRQEN"
+          resval: 0x0
+          desc: '''Timer high compare match interrupt enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "3"
+          name: "IEM"
+          resval: 0x0
+          desc: '''Timer high input event mask configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled	
+                '''
+        }
+        { bits: "4"
+          name: "MODE"
+          resval: 0x0
+          desc: '''Timer high continuous mode configuration bitfield:
+                - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_HI occurs.
+                - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_HI occurs.
+                '''
+        }
+        { bits: "5"
+          name: "ONE_S"
+          resval: 0x0
+          desc: '''Timer high one shot configuration bitfield:
+                - 1'b0: let Timer high enabled counting when compare match with CMP_HI occurs.
+                - 1'b1: disable Timer high when compare match with CMP_HI occurs.
+                '''
+        }
+        { bits: "6"
+          name: "PEN"
+          resval: 0x0
+          desc: '''Timer high prescaler enable configuration bitfield:
+                - 1'b0: disabled
+                - 1'b1: enabled
+                '''
+        }
+        { bits: "7"
+          name: "CLKCFG"
+          resval: 0x0
+          desc: '''Timer high clock source configuration bitfield:
+                - 1'b0: FLL or FLL+Prescaler
+                - 1'b1: Reference clock at 32kHz
+                '''
+	}	
+      ]
+    }
+    { name: "CNT_LO"
+      desc: "Timer Low counter value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cnt_lo"
+          resval: 0x0
+          desc: "Timer Low counter value bitfield."
+        }
+      ]
+    }
+    { name: "CNT_HI"
+      desc: "Timer High counter value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cnt_hi"
+          resval: 0x0
+          desc: "Timer High counter value bitfield."
+        }
+      ]
+    }
+    { name: "CMP_LO"
+      desc: "Timer Low comparator value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cmp_lo"
+          resval: 0x0
+          desc: "Timer Low comparator value bitfield."
+        }
+      ]
+    }
+    { name: "CMP_HI"
+      desc: "Timer High comparator value register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "cmp_hi"
+          resval: 0x0
+          desc: "Timer High comparator value bitfield."
+        }
+      ]
+    }
+    { name: "START_LO"
+      desc: "Start Timer Low counting register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "strt_lo"
+          resval: 0x0
+          desc: "Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set."
+        }
+      ]
+    }
+    { name: "START_HI"
+      desc: "Start Timer High counting register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "strt_hi"
+          resval: 0x0
+          desc: "Timer High start command bitfield. When executed, CFG_HI.ENABLE is set."
+        }
+      ]
+    }
+    { name: "RESET_LO"
+      desc: "Reset Timer Low counter register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "rst_lo"
+          resval: 0x0
+          desc: "Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set."
+        }
+      ]
+    }
+    { name: "RESET_HI"
+      desc: "Reset Timer High counter register."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0:0"
+          name: "rst_hi"
+          resval: 0x0
+          desc: "Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set."
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/gp_timer1_system_timer/doc/registers.md b/docs/um/ip/gp_timer1_system_timer/doc/registers.md
new file mode 100644
index 00000000..c4dc75d0
--- /dev/null
+++ b/docs/um/ip/gp_timer1_system_timer/doc/registers.md
@@ -0,0 +1,197 @@
+## Summary
+
+| Name                               | Offset   |   Length | Description                           |
+|:-----------------------------------|:---------|---------:|:--------------------------------------|
+| timer_unit.[`CFG_LO`](#cfg_lo)     | 0x0      |        4 | Timer Low Configuration register.     |
+| timer_unit.[`CFG_HI`](#cfg_hi)     | 0x4      |        4 | Timer HIGH Configuration register.    |
+| timer_unit.[`CNT_LO`](#cnt_lo)     | 0x8      |        4 | Timer Low counter value register.     |
+| timer_unit.[`CNT_HI`](#cnt_hi)     | 0xc      |        4 | Timer High counter value register.    |
+| timer_unit.[`CMP_LO`](#cmp_lo)     | 0x10     |        4 | Timer Low comparator value register.  |
+| timer_unit.[`CMP_HI`](#cmp_hi)     | 0x14     |        4 | Timer High comparator value register. |
+| timer_unit.[`START_LO`](#start_lo) | 0x18     |        4 | Start Timer Low counting register.    |
+| timer_unit.[`START_HI`](#start_hi) | 0x1c     |        4 | Start Timer High counting register.   |
+| timer_unit.[`RESET_LO`](#reset_lo) | 0x20     |        4 | Reset Timer Low counter register.     |
+| timer_unit.[`RESET_HI`](#reset_hi) | 0x24     |        4 | Reset Timer High counter register.    |
+
+## CFG_LO
+Timer Low Configuration register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x8000ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PVAL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 15}, {"name": "CASC", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | CASC   | Timer low  + Timer high 64bit cascaded mode configuration bitfield.                                                                                                                                                                          |
+| 30:16  |        |         |        | Reserved                                                                                                                                                                                                                                     |
+|  15:8  |   rw   |   0x0   | PVAL   | Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL)                                                                                                                                                                          |
+|   7    |   rw   |   0x0   | CCFG   | Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                 |
+|   6    |   rw   |   0x0   | PEN    | Timer low prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   5    |   rw   |   0x0   | ONE_S  | Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low when compare match with CMP_LO occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer low continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                          |
+|   2    |   rw   |   0x0   | IRQEN  | Timer low compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                            |
+|   1    |   rw   |   0x0   | RESET  | Timer low counter reset command bitfield. Cleared after Timer Low reset execution.                                                                                                                                                           |
+|   0    |   rw   |   0x0   | ENABLE | Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                    |
+
+## CFG_HI
+Timer HIGH Configuration register.
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "IRQEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IEM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONE_S", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLKCFG", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                                                                                     |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |        | Reserved                                                                                                                                                                                                                                        |
+|   7    |   rw   |   0x0   | CLKCFG | Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz                                                                                                                                   |
+|   6    |   rw   |   0x0   | PEN    | Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   5    |   rw   |   0x0   | ONE_S  | Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled counting when compare match with CMP_HI occurs. - 1'b1: disable Timer high when compare match with CMP_HI occurs.                                                    |
+|   4    |   rw   |   0x0   | MODE   | Timer high continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_HI occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_HI occurs. |
+|   3    |   rw   |   0x0   | IEM    | Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                            |
+|   2    |   rw   |   0x0   | IRQEN  | Timer high compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                              |
+|   1    |   wo   |   0x0   | RESET  | Timer high counter reset command bitfield. Cleared after Timer high reset execution.                                                                                                                                                            |
+|   0    |   rw   |   0x0   | ENABLE | Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled                                                                                                                                                                      |
+
+## CNT_LO
+Timer Low counter value register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                       |
+|:------:|:------:|:-------:|:-------|:----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_lo | Timer Low counter value bitfield. |
+
+## CNT_HI
+Timer High counter value register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cnt_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | cnt_hi | Timer High counter value bitfield. |
+
+## CMP_LO
+Timer Low comparator value register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_lo", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                          |
+|:------:|:------:|:-------:|:-------|:-------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_lo | Timer Low comparator value bitfield. |
+
+## CMP_HI
+Timer High comparator value register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cmp_hi", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------|
+|  31:0  |   rw   |   0x0   | cmp_hi | Timer High comparator value bitfield. |
+
+## START_LO
+Start Timer Low counting register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                            |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                               |
+|   0    |   wo   |   0x0   | strt_lo | Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set. |
+
+## START_HI
+Start Timer High counting register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "strt_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                             |
+|:------:|:------:|:-------:|:--------|:------------------------------------------------------------------------|
+|  31:1  |        |         |         | Reserved                                                                |
+|   0    |   wo   |   0x0   | strt_hi | Timer High start command bitfield. When executed, CFG_HI.ENABLE is set. |
+
+## RESET_LO
+Reset Timer Low counter register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_lo", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                   |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                      |
+|   0    |   wo   |   0x0   | rst_lo | Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set. |
+
+## RESET_HI
+Reset Timer High counter register.
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "rst_hi", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                       |
+|   0    |   wo   |   0x0   | rst_hi | Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set. |
+
diff --git a/docs/um/ip/gp_timer2_advanced_timer/data/apb_adv_timer.hjson b/docs/um/ip/gp_timer2_advanced_timer/data/apb_adv_timer.hjson
new file mode 100644
index 00000000..016be8a8
--- /dev/null
+++ b/docs/um/ip/gp_timer2_advanced_timer/data/apb_adv_timer.hjson
@@ -0,0 +1,1020 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Florent Rotenberg <florent.rotenberg@greenwaves-technologies.com>
+# APB Advanced timer register
+{
+  name: "apb_adv_timer"
+  one_paragraph_desc: '''
+  ADV_ TIMER component manages the following features:
+  - 4 advanced timers with 4 output signal channels each. Provides PWM generation functionality
+  - multiple trigger input sources:
+     - output signal channels of all timers
+     - 32 GPIOs
+     - reference clock at 32kHz
+     - FLL clock
+  - configurable input trigger modes
+  - configurable prescaler for each timer
+  - configurable counting mode for each timer
+  - configurable channel threshold action for each timer
+  - 4 configurable output events
+  - configurable clock gating of each timer
+  '''
+  cip_id:  "36",
+  version: "1.0.4"
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32"
+  registers: [
+    { name: "T0_CMD"
+      desc: "ADV_TIMER0 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER0 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER0 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER0 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER0 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER0 arm command bitfield."
+        }
+        { bits: "31:5"
+          name: "RFU"
+          resval: 0x0
+          desc: "?"
+        }
+      ]
+    }
+    { name: "T0_CONFIG"
+      desc: "ADV_TIMER0 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER0 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+	  swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER0 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER0 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+        { bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER0 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.	
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER0 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T0_THRESHOLD"
+      desc: "ADV_TIMER0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value."
+        }
+	{ bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL0"
+      desc: "ADV_TIMER0 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 0 threshold configuration bitfield."
+        }
+	{ bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+	        '''
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL1"
+      desc: "ADV_TIMER0 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc:	'''ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL2"
+      desc: "ADV_TIMER0 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc:	'''ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T0_TH_CHANNEL3"
+      desc: "ADV_TIMER0 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER0 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc:	'''ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T0_COUNTER"
+      desc: "ADV_TIMER0 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER0 counter value."
+        }
+      ]
+    }
+    { name: "T1_CMD"
+      desc: "ADV_TIMER1 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER1 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER1 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER1 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER1 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER1 arm command bitfield."
+        }
+      ]
+    }
+    { name: "T1_CONFIG"
+      desc: "ADV_TIMER1 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER1 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+          swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER1 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER1 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+	{ bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER1 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER1 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T1_THRESHOLD"
+      desc: "ADV_TIMER1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value."
+        }
+        { bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL0"
+      desc: "ADV_TIMER1 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 0 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL1"
+      desc: "ADV_TIMER1 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL2"
+      desc: "ADV_TIMER1 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_TH_CHANNEL3"
+      desc: "ADV_TIMER1 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER1 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T1_COUNTER"
+      desc: "ADV_TIMER1 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER1 counter value."
+        }
+      ]
+    }
+    { name: "T2_CMD"
+      desc: "ADV_TIMER2 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER2 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER2 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER2 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER2 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER2 arm command bitfield."
+        }
+      ]
+    }
+    { name: "T2_CONFIG"
+      desc: "ADV_TIMER2 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER2 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+          swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER2 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER2 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+        { bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER2 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER2 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T2_THRESHOLD"
+      desc: "ADV_TIMER2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value."
+        }
+        { bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL0"
+      desc: "ADV_TIMER2 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 0 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL1"
+      desc: "ADV_TIMER2 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL2"
+      desc: "ADV_TIMER2 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_TH_CHANNEL3"
+      desc: "ADV_TIMER2 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER2 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T2_COUNTER"
+      desc: "ADV_TIMER2 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER2 counter value."
+        }
+      ]
+    }
+    { name: "T3_CMD"
+      desc: "ADV_TIMER3 command register."
+      swaccess: "wo"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0"
+          name: "START"
+          resval: 0x0
+          desc: "ADV_TIMER3 start command bitfield."
+        }
+        { bits: "1"
+          name: "STOP"
+          resval: 0x0
+          desc: "ADV_TIMER3 stop command bitfield."
+        }
+        { bits: "2"
+          name: "UPDATE"
+          resval: 0x0
+          desc: "ADV_TIMER3 update command bitfield."
+        }
+        { bits: "3"
+          name: "RESET"
+          resval: 0x0
+          desc: "ADV_TIMER3 reset command bitfield."
+        }
+        { bits: "4"
+          name: "ARM"
+          resval: 0x0
+          desc: "ADV_TIMER3 arm command bitfield."
+        }
+      ]
+    }
+    { name: "T3_CONFIG"
+      desc: "ADV_TIMER3 configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0"
+          name: "INSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER3 input source configuration bitfield:
+                - 0-31: GPIO[0] to GPIO[31]
+                - 32-35: Channel 0 to 3 of ADV_TIMER0
+                - 36-39: Channel 0 to 3 of ADV_TIMER1
+                - 40-43: Channel 0 to 3 of ADV_TIMER2
+                - 44-47: Channel 0 to 3 of ADV_TIMER3
+                '''
+        }
+        { bits: "10:8"
+          name: "MODE"
+          swaccess: "rw"
+          hwaccess: "hrw"
+          resval: 0x0
+          desc: '''ADV_TIMER3 trigger mode configuration bitfield:
+                - 3'h0: trigger event at each clock cycle.
+                - 3'h1: trigger event if input source is 0
+                - 3'h2: trigger event if input source is 1
+                - 3'h3: trigger event on input source rising edge
+                - 3'h4: trigger event on input source falling edge
+                - 3'h5: trigger event on input source falling or rising edge
+                - 3'h6: trigger event on input source rising edge when armed
+                - 3'h7: trigger event on input source falling edge when armed
+                '''
+        }
+        { bits: "11"
+          name: "CLKSEL"
+          resval: 0x0
+          desc: '''ADV_TIMER3 clock source configuration bitfield:
+                - 1'b0: FLL
+                - 1'b1: reference clock at 32kHz
+                '''
+        }
+        { bits: "12"
+          name: "UPDOWNSEL"
+          resval: 0x1
+          desc: '''ADV_TIMER3 center-aligned mode configuration bitfield:
+                - 1'b0: The counter counts up and down alternatively.
+                - 1'b1: The counter counts up and resets to 0 when reach threshold.
+                '''
+        }
+        { bits: "23:16"
+          name: "PRESC"
+          resval: 0x0
+          desc: "ADV_TIMER3 prescaler value configuration bitfield."
+        }
+      ]
+    }
+    { name: "T3_THRESHOLD"
+      desc: "ADV_TIMER3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH_LO"
+          resval: 0x0
+          desc: "ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value."
+        }
+        { bits: "31:16"
+          name: "TH_HI"
+          resval: 0x0
+          desc: "ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value."
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL0"
+      desc: "ADV_TIMER3 channel 0 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 0 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL1"
+      desc: "ADV_TIMER3 channel 1 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 1 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL2"
+      desc: "ADV_TIMER3 channel 2 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 2 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_TH_CHANNEL3"
+      desc: "ADV_TIMER3 channel 3 threshold configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "15:0"
+          name: "TH"
+          resval: 0x0
+          desc: "ADV_TIMER3 channel 3 threshold configuration bitfield."
+        }
+        { bits: "18:16"
+          name: "MODE"
+          resval: 0x0
+          desc: '''ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield:
+                - 3'h0: set.
+                - 3'h1: toggle then next threshold match action is clear.
+                - 3'h2: set then next threshold match action is clear.
+                - 3'h3: toggle.
+                - 3'h4: clear.
+                - 3'h5: toggle then next threshold match action is set.
+                - 3'h6: clear then next threshold match action is set.
+                '''
+        }
+      ]
+    }
+    { name: "T3_COUNTER"
+      desc: "ADV_TIMER3 counter register."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "COUNTER"
+          resval: 0x0
+          desc: "ADV_TIMER3 counter value."
+        }
+      ]
+    }
+    { name: "EVENT_CFG"
+      desc: "ADV_TIMERS events configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "3:0"
+          name: "SEL0"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 0 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+	{ bits: "7:4"
+          name: "SEL1"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 1 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+	{ bits: "11:8"
+          name: "SEL2"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 2 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+	{ bits: "15:12"
+          name: "SEL3"
+          resval: 0x0
+          desc: '''ADV_TIMER output event 3 source configuration bitfiled:
+                - 4'h0: ADV_TIMER0 channel 0.
+                - 4'h1: ADV_TIMER0 channel 1.
+                - 4'h2: ADV_TIMER0 channel 2.
+                - 4'h3: ADV_TIMER0 channel 3.
+                - 4'h4: ADV_TIMER1 channel 0.
+                - 4'h5: ADV_TIMER1 channel 1.
+                - 4'h6: ADV_TIMER1 channel 2.
+                - 4'h7: ADV_TIMER1 channel 3.
+                - 4'h8: ADV_TIMER2 channel 0.
+                - 4'h9: ADV_TIMER2 channel 1.
+                - 4'hA: ADV_TIMER2 channel 2.
+                - 4'hB: ADV_TIMER2 channel 3.
+                - 4'hC: ADV_TIMER3 channel 0.
+                - 4'hD: ADV_TIMER3 channel 1.
+                - 4'hE: ADV_TIMER3 channel 2.
+                - 4'hF: ADV_TIMER3 channel 3.
+                '''
+        }
+        { bits: "19:16"
+          name: "ENA"
+          resval: 0x0
+          desc: "ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation."
+        }
+      ]
+    }
+    { name: "CG"
+      desc: "ADV_TIMERS channels clock gating configuration register."
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "3:0"
+          name: "ENA"
+          resval: 0x0
+          desc: '''ADV_TIMER clock gating configuration bitfield.
+                - ENA[i]=0: clock gate ADV_TIMERi.
+                - ENA[i]=1: enable ADV_TIMERi.
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/gp_timer2_advanced_timer/doc/registers.md b/docs/um/ip/gp_timer2_advanced_timer/doc/registers.md
new file mode 100644
index 00000000..d52b1b7b
--- /dev/null
+++ b/docs/um/ip/gp_timer2_advanced_timer/doc/registers.md
@@ -0,0 +1,1088 @@
+## Summary
+
+| Name                                              | Offset   |   Length | Description                                              |
+|:--------------------------------------------------|:---------|---------:|:---------------------------------------------------------|
+| apb_adv_timer.[`T0_CMD`](#t0_cmd)                 | 0x0      |        4 | ADV_TIMER0 command register.                             |
+| apb_adv_timer.[`T0_CONFIG`](#t0_config)           | 0x4      |        4 | ADV_TIMER0 configuration register.                       |
+| apb_adv_timer.[`T0_THRESHOLD`](#t0_threshold)     | 0x8      |        4 | ADV_TIMER0 threshold configuration register.             |
+| apb_adv_timer.[`T0_TH_CHANNEL0`](#t0_th_channel0) | 0xc      |        4 | ADV_TIMER0 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL1`](#t0_th_channel1) | 0x10     |        4 | ADV_TIMER0 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL2`](#t0_th_channel2) | 0x14     |        4 | ADV_TIMER0 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T0_TH_CHANNEL3`](#t0_th_channel3) | 0x18     |        4 | ADV_TIMER0 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T0_COUNTER`](#t0_counter)         | 0x1c     |        4 | ADV_TIMER0 counter register.                             |
+| apb_adv_timer.[`T1_CMD`](#t1_cmd)                 | 0x20     |        4 | ADV_TIMER1 command register.                             |
+| apb_adv_timer.[`T1_CONFIG`](#t1_config)           | 0x24     |        4 | ADV_TIMER1 configuration register.                       |
+| apb_adv_timer.[`T1_THRESHOLD`](#t1_threshold)     | 0x28     |        4 | ADV_TIMER1 threshold configuration register.             |
+| apb_adv_timer.[`T1_TH_CHANNEL0`](#t1_th_channel0) | 0x2c     |        4 | ADV_TIMER1 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL1`](#t1_th_channel1) | 0x30     |        4 | ADV_TIMER1 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL2`](#t1_th_channel2) | 0x34     |        4 | ADV_TIMER1 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T1_TH_CHANNEL3`](#t1_th_channel3) | 0x38     |        4 | ADV_TIMER1 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T1_COUNTER`](#t1_counter)         | 0x3c     |        4 | ADV_TIMER1 counter register.                             |
+| apb_adv_timer.[`T2_CMD`](#t2_cmd)                 | 0x40     |        4 | ADV_TIMER2 command register.                             |
+| apb_adv_timer.[`T2_CONFIG`](#t2_config)           | 0x44     |        4 | ADV_TIMER2 configuration register.                       |
+| apb_adv_timer.[`T2_THRESHOLD`](#t2_threshold)     | 0x48     |        4 | ADV_TIMER2 threshold configuration register.             |
+| apb_adv_timer.[`T2_TH_CHANNEL0`](#t2_th_channel0) | 0x4c     |        4 | ADV_TIMER2 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL1`](#t2_th_channel1) | 0x50     |        4 | ADV_TIMER2 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL2`](#t2_th_channel2) | 0x54     |        4 | ADV_TIMER2 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T2_TH_CHANNEL3`](#t2_th_channel3) | 0x58     |        4 | ADV_TIMER2 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T2_COUNTER`](#t2_counter)         | 0x5c     |        4 | ADV_TIMER2 counter register.                             |
+| apb_adv_timer.[`T3_CMD`](#t3_cmd)                 | 0x60     |        4 | ADV_TIMER3 command register.                             |
+| apb_adv_timer.[`T3_CONFIG`](#t3_config)           | 0x64     |        4 | ADV_TIMER3 configuration register.                       |
+| apb_adv_timer.[`T3_THRESHOLD`](#t3_threshold)     | 0x68     |        4 | ADV_TIMER3 threshold configuration register.             |
+| apb_adv_timer.[`T3_TH_CHANNEL0`](#t3_th_channel0) | 0x6c     |        4 | ADV_TIMER3 channel 0 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL1`](#t3_th_channel1) | 0x70     |        4 | ADV_TIMER3 channel 1 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL2`](#t3_th_channel2) | 0x74     |        4 | ADV_TIMER3 channel 2 threshold configuration register.   |
+| apb_adv_timer.[`T3_TH_CHANNEL3`](#t3_th_channel3) | 0x78     |        4 | ADV_TIMER3 channel 3 threshold configuration register.   |
+| apb_adv_timer.[`T3_COUNTER`](#t3_counter)         | 0x7c     |        4 | ADV_TIMER3 counter register.                             |
+| apb_adv_timer.[`EVENT_CFG`](#event_cfg)           | 0x80     |        4 | ADV_TIMERS events configuration register.                |
+| apb_adv_timer.[`CG`](#cg)                         | 0x84     |        4 | ADV_TIMERS channels clock gating configuration register. |
+
+## T0_CMD
+ADV_TIMER0 command register.
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RFU", "bits": 27, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |   wo   |   0x0   | RFU    | ?                                   |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER0 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER0 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER0 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER0 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER0 start command bitfield.  |
+
+## T0_CONFIG
+ADV_TIMER0 configuration register.
+- Offset: `0x4`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t0_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t0_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t0_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t0_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t0_config--insel)         |
+
+### T0_CONFIG . PRESC
+ADV_TIMER0 prescaler value configuration bitfield.
+
+### T0_CONFIG . UPDOWNSEL
+ADV_TIMER0 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.	
+
+### T0_CONFIG . CLKSEL
+ADV_TIMER0 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T0_CONFIG . MODE
+ADV_TIMER0 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T0_CONFIG . INSEL
+ADV_TIMER0 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T0_THRESHOLD
+ADV_TIMER0 threshold configuration register.
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. |
+
+## T0_TH_CHANNEL0
+ADV_TIMER0 channel 0 threshold configuration register.
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel0--th)     |
+
+### T0_TH_CHANNEL0 . MODE
+ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL0 . TH
+ADV_TIMER0 channel 0 threshold configuration bitfield.
+
+## T0_TH_CHANNEL1
+ADV_TIMER0 channel 1 threshold configuration register.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel1--th)     |
+
+### T0_TH_CHANNEL1 . MODE
+ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL1 . TH
+ADV_TIMER0 channel 1 threshold configuration bitfield.
+
+## T0_TH_CHANNEL2
+ADV_TIMER0 channel 2 threshold configuration register.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel2--th)     |
+
+### T0_TH_CHANNEL2 . MODE
+ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL2 . TH
+ADV_TIMER0 channel 2 threshold configuration bitfield.
+
+## T0_TH_CHANNEL3
+ADV_TIMER0 channel 3 threshold configuration register.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t0_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t0_th_channel3--th)     |
+
+### T0_TH_CHANNEL3 . MODE
+ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T0_TH_CHANNEL3 . TH
+ADV_TIMER0 channel 3 threshold configuration bitfield.
+
+## T0_COUNTER
+ADV_TIMER0 counter register.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER0 counter value. |
+
+## T1_CMD
+ADV_TIMER1 command register.
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER1 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER1 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER1 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER1 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER1 start command bitfield.  |
+
+## T1_CONFIG
+ADV_TIMER1 configuration register.
+- Offset: `0x24`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t1_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t1_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t1_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t1_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t1_config--insel)         |
+
+### T1_CONFIG . PRESC
+ADV_TIMER1 prescaler value configuration bitfield.
+
+### T1_CONFIG . UPDOWNSEL
+ADV_TIMER1 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T1_CONFIG . CLKSEL
+ADV_TIMER1 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T1_CONFIG . MODE
+ADV_TIMER1 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T1_CONFIG . INSEL
+ADV_TIMER1 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T1_THRESHOLD
+ADV_TIMER1 threshold configuration register.
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value. |
+
+## T1_TH_CHANNEL0
+ADV_TIMER1 channel 0 threshold configuration register.
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel0--th)     |
+
+### T1_TH_CHANNEL0 . MODE
+ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL0 . TH
+ADV_TIMER1 channel 0 threshold configuration bitfield.
+
+## T1_TH_CHANNEL1
+ADV_TIMER1 channel 1 threshold configuration register.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel1--th)     |
+
+### T1_TH_CHANNEL1 . MODE
+ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL1 . TH
+ADV_TIMER1 channel 1 threshold configuration bitfield.
+
+## T1_TH_CHANNEL2
+ADV_TIMER1 channel 2 threshold configuration register.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel2--th)     |
+
+### T1_TH_CHANNEL2 . MODE
+ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL2 . TH
+ADV_TIMER1 channel 2 threshold configuration bitfield.
+
+## T1_TH_CHANNEL3
+ADV_TIMER1 channel 3 threshold configuration register.
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t1_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t1_th_channel3--th)     |
+
+### T1_TH_CHANNEL3 . MODE
+ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T1_TH_CHANNEL3 . TH
+ADV_TIMER1 channel 3 threshold configuration bitfield.
+
+## T1_COUNTER
+ADV_TIMER1 counter register.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER1 counter value. |
+
+## T2_CMD
+ADV_TIMER2 command register.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER2 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER2 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER2 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER2 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER2 start command bitfield.  |
+
+## T2_CONFIG
+ADV_TIMER2 configuration register.
+- Offset: `0x44`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t2_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t2_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t2_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t2_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t2_config--insel)         |
+
+### T2_CONFIG . PRESC
+ADV_TIMER2 prescaler value configuration bitfield.
+
+### T2_CONFIG . UPDOWNSEL
+ADV_TIMER2 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T2_CONFIG . CLKSEL
+ADV_TIMER2 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T2_CONFIG . MODE
+ADV_TIMER2 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T2_CONFIG . INSEL
+ADV_TIMER2 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T2_THRESHOLD
+ADV_TIMER2 threshold configuration register.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value. |
+
+## T2_TH_CHANNEL0
+ADV_TIMER2 channel 0 threshold configuration register.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel0--th)     |
+
+### T2_TH_CHANNEL0 . MODE
+ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL0 . TH
+ADV_TIMER2 channel 0 threshold configuration bitfield.
+
+## T2_TH_CHANNEL1
+ADV_TIMER2 channel 1 threshold configuration register.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel1--th)     |
+
+### T2_TH_CHANNEL1 . MODE
+ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL1 . TH
+ADV_TIMER2 channel 1 threshold configuration bitfield.
+
+## T2_TH_CHANNEL2
+ADV_TIMER2 channel 2 threshold configuration register.
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel2--th)     |
+
+### T2_TH_CHANNEL2 . MODE
+ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL2 . TH
+ADV_TIMER2 channel 2 threshold configuration bitfield.
+
+## T2_TH_CHANNEL3
+ADV_TIMER2 channel 3 threshold configuration register.
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t2_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t2_th_channel3--th)     |
+
+### T2_TH_CHANNEL3 . MODE
+ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T2_TH_CHANNEL3 . TH
+ADV_TIMER2 channel 3 threshold configuration bitfield.
+
+## T2_COUNTER
+ADV_TIMER2 counter register.
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER2 counter value. |
+
+## T3_CMD
+ADV_TIMER3 command register.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "UPDATE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "ARM", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:5  |        |         |        | Reserved                            |
+|   4    |   wo   |   0x0   | ARM    | ADV_TIMER3 arm command bitfield.    |
+|   3    |   wo   |   0x0   | RESET  | ADV_TIMER3 reset command bitfield.  |
+|   2    |   wo   |   0x0   | UPDATE | ADV_TIMER3 update command bitfield. |
+|   1    |   wo   |   0x0   | STOP   | ADV_TIMER3 stop command bitfield.   |
+|   0    |   wo   |   0x0   | START  | ADV_TIMER3 start command bitfield.  |
+
+## T3_CONFIG
+ADV_TIMER3 configuration register.
+- Offset: `0x64`
+- Reset default: `0x1000`
+- Reset mask: `0xff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INSEL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "CLKSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UPDOWNSEL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "PRESC", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+| 31:24  |        |         | Reserved                           |
+| 23:16  |   rw   |   0x0   | [PRESC](#t3_config--presc)         |
+| 15:13  |        |         | Reserved                           |
+|   12   |   rw   |   0x1   | [UPDOWNSEL](#t3_config--updownsel) |
+|   11   |   rw   |   0x0   | [CLKSEL](#t3_config--clksel)       |
+|  10:8  |   rw   |   0x0   | [MODE](#t3_config--mode)           |
+|  7:0   |   rw   |   0x0   | [INSEL](#t3_config--insel)         |
+
+### T3_CONFIG . PRESC
+ADV_TIMER3 prescaler value configuration bitfield.
+
+### T3_CONFIG . UPDOWNSEL
+ADV_TIMER3 center-aligned mode configuration bitfield:
+- 1'b0: The counter counts up and down alternatively.
+- 1'b1: The counter counts up and resets to 0 when reach threshold.
+
+### T3_CONFIG . CLKSEL
+ADV_TIMER3 clock source configuration bitfield:
+- 1'b0: FLL
+- 1'b1: reference clock at 32kHz
+
+### T3_CONFIG . MODE
+ADV_TIMER3 trigger mode configuration bitfield:
+- 3'h0: trigger event at each clock cycle.
+- 3'h1: trigger event if input source is 0
+- 3'h2: trigger event if input source is 1
+- 3'h3: trigger event on input source rising edge
+- 3'h4: trigger event on input source falling edge
+- 3'h5: trigger event on input source falling or rising edge
+- 3'h6: trigger event on input source rising edge when armed
+- 3'h7: trigger event on input source falling edge when armed
+
+### T3_CONFIG . INSEL
+ADV_TIMER3 input source configuration bitfield:
+- 0-31: GPIO[0] to GPIO[31]
+- 32-35: Channel 0 to 3 of ADV_TIMER0
+- 36-39: Channel 0 to 3 of ADV_TIMER1
+- 40-43: Channel 0 to 3 of ADV_TIMER2
+- 44-47: Channel 0 to 3 of ADV_TIMER3
+
+## T3_THRESHOLD
+ADV_TIMER3 threshold configuration register.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH_LO", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "TH_HI", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                           |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------|
+| 31:16  |   rw   |   0x0   | TH_HI  | ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value.  |
+|  15:0  |   rw   |   0x0   | TH_LO  | ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value. |
+
+## T3_TH_CHANNEL0
+ADV_TIMER3 channel 0 threshold configuration register.
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel0--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel0--th)     |
+
+### T3_TH_CHANNEL0 . MODE
+ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL0 . TH
+ADV_TIMER3 channel 0 threshold configuration bitfield.
+
+## T3_TH_CHANNEL1
+ADV_TIMER3 channel 1 threshold configuration register.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel1--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel1--th)     |
+
+### T3_TH_CHANNEL1 . MODE
+ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL1 . TH
+ADV_TIMER3 channel 1 threshold configuration bitfield.
+
+## T3_TH_CHANNEL2
+ADV_TIMER3 channel 2 threshold configuration register.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel2--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel2--th)     |
+
+### T3_TH_CHANNEL2 . MODE
+ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL2 . TH
+ADV_TIMER3 channel 2 threshold configuration bitfield.
+
+## T3_TH_CHANNEL3
+ADV_TIMER3 channel 3 threshold configuration register.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TH", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                          |
+|:------:|:------:|:-------:|:------------------------------|
+| 31:19  |        |         | Reserved                      |
+| 18:16  |   rw   |   0x0   | [MODE](#t3_th_channel3--mode) |
+|  15:0  |   rw   |   0x0   | [TH](#t3_th_channel3--th)     |
+
+### T3_TH_CHANNEL3 . MODE
+ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield:
+- 3'h0: set.
+- 3'h1: toggle then next threshold match action is clear.
+- 3'h2: set then next threshold match action is clear.
+- 3'h3: toggle.
+- 3'h4: clear.
+- 3'h5: toggle then next threshold match action is set.
+- 3'h6: clear then next threshold match action is set.
+
+### T3_TH_CHANNEL3 . TH
+ADV_TIMER3 channel 3 threshold configuration bitfield.
+
+## T3_COUNTER
+ADV_TIMER3 counter register.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "COUNTER", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description               |
+|:------:|:------:|:-------:|:--------|:--------------------------|
+| 31:16  |        |         |         | Reserved                  |
+|  15:0  |   ro   |   0x0   | COUNTER | ADV_TIMER3 counter value. |
+
+## EVENT_CFG
+ADV_TIMERS events configuration register.
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SEL0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL2", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SEL3", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     |
+|:------:|:------:|:-------:|:-------------------------|
+| 31:20  |        |         | Reserved                 |
+| 19:16  |   rw   |   0x0   | [ENA](#event_cfg--ena)   |
+| 15:12  |   rw   |   0x0   | [SEL3](#event_cfg--sel3) |
+|  11:8  |   rw   |   0x0   | [SEL2](#event_cfg--sel2) |
+|  7:4   |   rw   |   0x0   | [SEL1](#event_cfg--sel1) |
+|  3:0   |   rw   |   0x0   | [SEL0](#event_cfg--sel0) |
+
+### EVENT_CFG . ENA
+ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation.
+
+### EVENT_CFG . SEL3
+ADV_TIMER output event 3 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL2
+ADV_TIMER output event 2 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL1
+ADV_TIMER output event 1 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+### EVENT_CFG . SEL0
+ADV_TIMER output event 0 source configuration bitfiled:
+- 4'h0: ADV_TIMER0 channel 0.
+- 4'h1: ADV_TIMER0 channel 1.
+- 4'h2: ADV_TIMER0 channel 2.
+- 4'h3: ADV_TIMER0 channel 3.
+- 4'h4: ADV_TIMER1 channel 0.
+- 4'h5: ADV_TIMER1 channel 1.
+- 4'h6: ADV_TIMER1 channel 2.
+- 4'h7: ADV_TIMER1 channel 3.
+- 4'h8: ADV_TIMER2 channel 0.
+- 4'h9: ADV_TIMER2 channel 1.
+- 4'hA: ADV_TIMER2 channel 2.
+- 4'hB: ADV_TIMER2 channel 3.
+- 4'hC: ADV_TIMER3 channel 0.
+- 4'hD: ADV_TIMER3 channel 1.
+- 4'hE: ADV_TIMER3 channel 2.
+- 4'hF: ADV_TIMER3 channel 3.
+
+## CG
+ADV_TIMERS channels clock gating configuration register.
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENA", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                      |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------|
+|  31:4  |        |         |        | Reserved                                                                                                         |
+|  3:0   |   rw   |   0x0   | ENA    | ADV_TIMER clock gating configuration bitfield. - ENA[i]=0: clock gate ADV_TIMERi. - ENA[i]=1: enable ADV_TIMERi. |
+
diff --git a/docs/um/ip/gpio/data/gpio.hjson b/docs/um/ip/gpio/data/gpio.hjson
new file mode 100644
index 00000000..01eed81d
--- /dev/null
+++ b/docs/um/ip/gpio/data/gpio.hjson
@@ -0,0 +1,290 @@
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name:               "gpio",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  available_inout_list: [
+    { name: "gpio",
+      width: 32,
+      desc: "GPIO inout to/from PAD"
+    }
+  ],
+  interrupt_list: [
+    { name: "gpio",
+      width: 32,
+      desc: "raised if any of GPIO pin detects configured interrupt mode"
+    }
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  param_list: [
+    { name:    "GpioAsyncOn",
+      type:    "bit",
+      default: "1'b1",
+      desc:    '''
+      Instantiates 2-flop synchronizers on all GPIO inputs if set to 1.
+      '''
+      local:   "false",
+      expose:  "true"
+    },
+  ]
+
+  regwidth: "32",
+  registers: [
+    { name: "DATA_IN",
+      desc: "GPIO Input data read value",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      tags: [// data_in is ro register, so exclude its readback check
+             "excl:CsrNonInitTests:CsrExclWriteCheck"],
+      fields: [
+        { bits: "31:0",
+          resval: "x"
+        }
+      ],
+    },
+    { name: "DIRECT_OUT",
+      desc: "GPIO direct output data write value",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "MASKED_OUT_LOWER",
+      desc: '''GPIO write data lower with mask.
+
+            Masked write for DATA_OUT[15:0].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OUT[15:0] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OUT[15:0].
+            '''
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_out* registers as they affect direct_out value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write data value[15:0].
+
+                Value to write into DATA_OUT[i], valid in the presence of mask[i]==1
+                '''
+        },
+        { bits: "31:16",
+          name: "mask",
+          desc: '''Write data mask[15:0].
+
+                A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15
+                '''
+          swaccess: "wo"
+        },
+      ],
+    },
+    { name: "MASKED_OUT_UPPER",
+      desc: '''GPIO write data upper with mask.
+
+            Masked write for DATA_OUT[31:16].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OUT[31:16] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OUT[31:16].
+            '''
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_out* registers as they affect direct_out value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write data value[31:16].
+
+                   Value to write into DATA_OUT[i], valid in the presence of mask[i]==1
+                '''
+        },
+        { bits: "31:16",
+          name: "mask",
+          desc: '''Write data mask[31:16].
+
+                A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31
+                '''
+          swaccess: "wo"
+        },
+      ],
+    },
+    { name: "DIRECT_OE",
+      desc: '''GPIO Output Enable.
+
+            Setting direct_oe[i] to 1 enables output mode for GPIO[i]
+            ''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:0",
+        }
+      ],
+    },
+    { name: "MASKED_OE_LOWER",
+      desc: '''GPIO write Output Enable lower with mask.
+
+            Masked write for DATA_OE[15:0], the register that controls
+            output mode for GPIO pins [15:0].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OE[15:0] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OE[15:0].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_oe* registers as they affect direct_oe value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write OE value[15:0].
+
+                Value to write into DATA_OE[i], valid in the presence of mask[i]==1
+                ''',
+        },
+        { name: "mask",
+          desc: '''Write OE mask[15:0].
+
+                A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15
+                ''',
+          bits: "31:16"
+        },
+      ],
+    },
+    { name: "MASKED_OE_UPPER",
+      desc: '''GPIO write Output Enable upper with mask.
+
+            Masked write for DATA_OE[31:16], the register that controls
+            output mode for GPIO pins [31:16].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OE[31:16] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OE[31:16].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_oe* registers as they affect direct_oe value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write OE value[31:16].
+
+                Value to write into DATA_OE[i], valid in the presence of mask[i]==1
+                ''',
+        },
+        { name: "mask",
+          desc: '''Write OE mask[31:16].
+
+                A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31
+                ''',
+          bits: "31:16"
+        },
+      ],
+    },
+
+    { name: "INTR_CTRL_EN_RISING",
+      desc: '''GPIO interrupt enable for GPIO, rising edge.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_RISING[i]
+            enables rising-edge interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "INTR_CTRL_EN_FALLING",
+      desc: '''GPIO interrupt enable for GPIO, falling edge.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_FALLING[i]
+            enables falling-edge interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "INTR_CTRL_EN_LVLHIGH",
+      desc: '''GPIO interrupt enable for GPIO, level high.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_LVLHIGH[i]
+            enables level high interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "INTR_CTRL_EN_LVLLOW",
+      desc: '''GPIO interrupt enable for GPIO, level low.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_LVLLOW[i]
+            enables level low interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "CTRL_EN_INPUT_FILTER",
+      desc: '''filter enable for GPIO input bits.
+
+            If !!CTRL_EN_INPUT_FILTER[i] is true, a value of input bit [i]
+            must be stable for 16 cycles before transitioning.
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+  ],
+}
diff --git a/docs/um/ip/gpio/data/gpio_doc.hjson b/docs/um/ip/gpio/data/gpio_doc.hjson
new file mode 100644
index 00000000..623fbc23
--- /dev/null
+++ b/docs/um/ip/gpio/data/gpio_doc.hjson
@@ -0,0 +1,294 @@
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name: "gpio",
+  cip_id: "36",
+  version: "0.0.0", // used in opentitan_peripheral repo from pulp platform
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  available_inout_list: [
+    { name: "gpio",
+      width: 32,
+      desc: "GPIO inout to/from PAD"
+    }
+  ],
+  interrupt_list: [
+    { name: "gpio",
+      width: 32,
+      desc: "raised if any of GPIO pin detects configured interrupt mode"
+    }
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  param_list: [
+    { name:    "GpioAsyncOn",
+      type:    "bit",
+      default: "1'b1",
+      desc:    '''
+      Instantiates 2-flop synchronizers on all GPIO inputs if set to 1.
+      '''
+      local:   "false",
+      expose:  "true"
+    },
+  ]
+
+  regwidth: "32",
+  registers: [
+    { name: "DATA_IN",
+      desc: "GPIO Input data read value",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      tags: [// data_in is ro register, so exclude its readback check
+             "excl:CsrNonInitTests:CsrExclWriteCheck"],
+      fields: [
+        { bits: "31:0",
+          resval: "x"
+        }
+      ],
+    },
+    { name: "DIRECT_OUT",
+      desc: "GPIO direct output data write value",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "MASKED_OUT_LOWER",
+      desc: '''GPIO write data lower with mask.
+
+            Masked write for DATA_OUT[15:0].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OUT[15:0] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OUT[15:0].
+            '''
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_out* registers as they affect direct_out value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write data value[15:0].
+
+                Value to write into DATA_OUT[i], valid in the presence of mask[i]==1
+                '''
+        },
+        { bits: "31:16",
+          name: "mask",
+          desc: '''Write data mask[15:0].
+
+                A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15
+                '''
+          swaccess: "wo"
+        },
+      ],
+    },
+    { name: "MASKED_OUT_UPPER",
+      desc: '''GPIO write data upper with mask.
+
+            Masked write for DATA_OUT[31:16].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OUT[31:16] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OUT[31:16].
+            '''
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_out* registers as they affect direct_out value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write data value[31:16].
+
+                   Value to write into DATA_OUT[i], valid in the presence of mask[i]==1
+                '''
+        },
+        { bits: "31:16",
+          name: "mask",
+          desc: '''Write data mask[31:16].
+
+                A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31
+                '''
+          swaccess: "wo"
+        },
+      ],
+    },
+    { name: "DIRECT_OE",
+      desc: '''GPIO Output Enable.
+
+            Setting direct_oe[i] to 1 enables output mode for GPIO[i]
+            ''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:0",
+        }
+      ],
+    },
+    { name: "MASKED_OE_LOWER",
+      desc: '''GPIO write Output Enable lower with mask.
+
+            Masked write for DATA_OE[15:0], the register that controls
+            output mode for GPIO pins [15:0].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OE[15:0] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OE[15:0].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_oe* registers as they affect direct_oe value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write OE value[15:0].
+
+                Value to write into DATA_OE[i], valid in the presence of mask[i]==1
+                ''',
+        },
+        { name: "mask",
+          desc: '''Write OE mask[15:0].
+
+                A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15
+                ''',
+          bits: "31:16"
+        },
+      ],
+    },
+    { name: "MASKED_OE_UPPER",
+      desc: '''GPIO write Output Enable upper with mask.
+
+            Masked write for DATA_OE[31:16], the register that controls
+            output mode for GPIO pins [31:16].
+
+            Upper 16 bits of this register are used as mask. Writing
+            lower 16 bits of the register changes DATA_OE[31:16] value
+            if mask bits are set.
+
+            Read-back of this register returns upper 16 bits as zero
+            and lower 16 bits as DATA_OE[31:16].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      tags: [// read value of masked_* registers yield a different value than written
+             // avoid writing to masked_oe* registers as they affect direct_oe value
+             "excl:CsrNonInitTests:CsrExclAll"],
+      fields: [
+        { bits: "15:0",
+          name: "data",
+          desc: '''Write OE value[31:16].
+
+                Value to write into DATA_OE[i], valid in the presence of mask[i]==1
+                ''',
+        },
+        { name: "mask",
+          desc: '''Write OE mask[31:16].
+
+                A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31
+                ''',
+          bits: "31:16"
+        },
+      ],
+    },
+
+    { name: "INTR_CTRL_EN_RISING",
+      desc: '''GPIO interrupt enable for GPIO, rising edge.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_RISING[i]
+            enables rising-edge interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "INTR_CTRL_EN_FALLING",
+      desc: '''GPIO interrupt enable for GPIO, falling edge.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_FALLING[i]
+            enables falling-edge interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "INTR_CTRL_EN_LVLHIGH",
+      desc: '''GPIO interrupt enable for GPIO, level high.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_LVLHIGH[i]
+            enables level high interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "INTR_CTRL_EN_LVLLOW",
+      desc: '''GPIO interrupt enable for GPIO, level low.
+
+            If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_LVLLOW[i]
+            enables level low interrupt detection on GPIO[i].
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "CTRL_EN_INPUT_FILTER",
+      desc: '''filter enable for GPIO input bits.
+
+            If !!CTRL_EN_INPUT_FILTER[i] is true, a value of input bit [i]
+            must be stable for 16 cycles before transitioning.
+            ''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+  ],
+}
diff --git a/docs/um/ip/gpio/doc/registers.md b/docs/um/ip/gpio/doc/registers.md
new file mode 100644
index 00000000..3d590b06
--- /dev/null
+++ b/docs/um/ip/gpio/doc/registers.md
@@ -0,0 +1,337 @@
+## Summary
+
+| Name                                                 | Offset   |   Length | Description                                   |
+|:-----------------------------------------------------|:---------|---------:|:----------------------------------------------|
+| gpio.[`INTR_STATE`](#intr_state)                     | 0x0      |        4 | Interrupt State Register                      |
+| gpio.[`INTR_ENABLE`](#intr_enable)                   | 0x4      |        4 | Interrupt Enable Register                     |
+| gpio.[`INTR_TEST`](#intr_test)                       | 0x8      |        4 | Interrupt Test Register                       |
+| gpio.[`ALERT_TEST`](#alert_test)                     | 0xc      |        4 | Alert Test Register                           |
+| gpio.[`DATA_IN`](#data_in)                           | 0x10     |        4 | GPIO Input data read value                    |
+| gpio.[`DIRECT_OUT`](#direct_out)                     | 0x14     |        4 | GPIO direct output data write value           |
+| gpio.[`MASKED_OUT_LOWER`](#masked_out_lower)         | 0x18     |        4 | GPIO write data lower with mask.              |
+| gpio.[`MASKED_OUT_UPPER`](#masked_out_upper)         | 0x1c     |        4 | GPIO write data upper with mask.              |
+| gpio.[`DIRECT_OE`](#direct_oe)                       | 0x20     |        4 | GPIO Output Enable.                           |
+| gpio.[`MASKED_OE_LOWER`](#masked_oe_lower)           | 0x24     |        4 | GPIO write Output Enable lower with mask.     |
+| gpio.[`MASKED_OE_UPPER`](#masked_oe_upper)           | 0x28     |        4 | GPIO write Output Enable upper with mask.     |
+| gpio.[`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising)   | 0x2c     |        4 | GPIO interrupt enable for GPIO, rising edge.  |
+| gpio.[`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling) | 0x30     |        4 | GPIO interrupt enable for GPIO, falling edge. |
+| gpio.[`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh) | 0x34     |        4 | GPIO interrupt enable for GPIO, level high.   |
+| gpio.[`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow)   | 0x38     |        4 | GPIO interrupt enable for GPIO, level low.    |
+| gpio.[`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter) | 0x3c     |        4 | filter enable for GPIO input bits.            |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw1c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                 |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------|
+|  31:0  |  rw1c  |   0x0   | gpio   | raised if any of GPIO pin detects configured interrupt mode |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | gpio   | Enable interrupt when corresponding bit in [`INTR_STATE.gpio`](#intr_state) is set. |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "gpio", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:0  |   wo   |   0x0   | gpio   | Write 1 to force corresponding bit in [`INTR_STATE.gpio`](#intr_state) to 1. |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## DATA_IN
+GPIO Input data read value
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   ro   |    x    | DATA_IN |               |
+
+## DIRECT_OUT
+GPIO direct output data write value
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DIRECT_OUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:0  |   rw   |    x    | DIRECT_OUT |               |
+
+## MASKED_OUT_LOWER
+GPIO write data lower with mask.
+
+Masked write for DATA_OUT[15:0].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OUT[15:0] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OUT[15:0].
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                     |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------|
+| 31:16  |   wo   |    x    | mask   | Write data mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15 |
+|  15:0  |   rw   |    x    | data   | Write data value[15:0]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1    |
+
+## MASKED_OUT_UPPER
+GPIO write data upper with mask.
+
+Masked write for DATA_OUT[31:16].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OUT[31:16] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OUT[31:16].
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                       |
+|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------|
+| 31:16  |   wo   |    x    | mask   | Write data mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31 |
+|  15:0  |   rw   |    x    | data   | Write data value[31:16]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1     |
+
+## DIRECT_OE
+GPIO Output Enable.
+
+Setting direct_oe[i] to 1 enables output mode for GPIO[i]
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "DIRECT_OE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description   |
+|:------:|:------:|:-------:|:----------|:--------------|
+|  31:0  |   rw   |    x    | DIRECT_OE |               |
+
+## MASKED_OE_LOWER
+GPIO write Output Enable lower with mask.
+
+Masked write for DATA_OE[15:0], the register that controls
+output mode for GPIO pins [15:0].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OE[15:0] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OE[15:0].
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------|
+| 31:16  |   rw   |    x    | mask   | Write OE mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15 |
+|  15:0  |   rw   |    x    | data   | Write OE value[15:0]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1    |
+
+## MASKED_OE_UPPER
+GPIO write Output Enable upper with mask.
+
+Masked write for DATA_OE[31:16], the register that controls
+output mode for GPIO pins [31:16].
+
+Upper 16 bits of this register are used as mask. Writing
+lower 16 bits of the register changes DATA_OE[31:16] value
+if mask bits are set.
+
+Read-back of this register returns upper 16 bits as zero
+and lower 16 bits as DATA_OE[31:16].
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                    |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------|
+| 31:16  |   rw   |    x    | mask   | Write OE mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31 |
+|  15:0  |   rw   |    x    | data   | Write OE value[31:16]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1     |
+
+## INTR_CTRL_EN_RISING
+GPIO interrupt enable for GPIO, rising edge.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising)[i]
+enables rising-edge interrupt detection on GPIO[i].
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_RISING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_RISING |               |
+
+## INTR_CTRL_EN_FALLING
+GPIO interrupt enable for GPIO, falling edge.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling)[i]
+enables falling-edge interrupt detection on GPIO[i].
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_FALLING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_FALLING |               |
+
+## INTR_CTRL_EN_LVLHIGH
+GPIO interrupt enable for GPIO, level high.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh)[i]
+enables level high interrupt detection on GPIO[i].
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_LVLHIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_LVLHIGH |               |
+
+## INTR_CTRL_EN_LVLLOW
+GPIO interrupt enable for GPIO, level low.
+
+If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow)[i]
+enables level low interrupt detection on GPIO[i].
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "INTR_CTRL_EN_LVLLOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                | Description   |
+|:------:|:------:|:-------:|:--------------------|:--------------|
+|  31:0  |   rw   |   0x0   | INTR_CTRL_EN_LVLLOW |               |
+
+## CTRL_EN_INPUT_FILTER
+filter enable for GPIO input bits.
+
+If [`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter)[i] is true, a value of input bit [i]
+must be stable for 16 cycles before transitioning.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CTRL_EN_INPUT_FILTER", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description   |
+|:------:|:------:|:-------:|:---------------------|:--------------|
+|  31:0  |   rw   |   0x0   | CTRL_EN_INPUT_FILTER |               |
+
diff --git a/docs/um/ip/hyperbus/data/hyperbus.hjson b/docs/um/ip/hyperbus/data/hyperbus.hjson
new file mode 100644
index 00000000..40fe5e6b
--- /dev/null
+++ b/docs/um/ip/hyperbus/data/hyperbus.hjson
@@ -0,0 +1,273 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// Part of the PULP platform project: https://pulp-platform.org
+// This file defines the register map for the HyperBus memory interface.
+
+// Register layout of hyperbus
+
+{
+  name: "hyperbus"
+  human_name: "HyperBus Controller"
+  one_line_desc: "HyperBus controller for interfacing with HyperRAM/Flash devices",
+  one_paragraph_desc: '''The HyperBus controller IP provides a flexible and programmable interface for communicating with external HyperRAM and HyperFlash memory devices. It supports AXI access, fine-grained
+                      clock and delay configuration, and physical interface control to meet timing closure and integration requirements.
+                      '''
+  cip_id: "36",
+  version: "0.0.0", //null
+
+  clocking: [
+    { clock: "clk_i", reset: "rst_ni", primary: true },
+    { clock: "clk_sys_i", reset: "rst_sys_ni" },
+    { clock: "clk_phy_i", reset: "rst_phy_ni" }
+  ],
+
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+   
+  regwidth: "32",
+  registers: [
+    {
+      name: "T_LATENCY_ACCESS"
+      desc: "Initial latency"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "3:0"
+          name: "T_LATENCY_ACCESS"
+          resval: 0x6
+          desc: "Initial latency"
+        }
+      ]
+    },
+    {
+      name: "EN_LATENCY_ADDITIONAL"
+      desc: "Force 2x Latency count"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:0"
+          name: "EN_LATENCY_ADDITIONAL"
+          resval: 0x0
+          desc: "Force 2x Latency count"
+        }
+      ]
+    },
+    {
+      name: "T_BURST_MAX"
+      desc: "Max burst Length between two memory refresh"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+       { bits: "15:0"
+          name: "T_BURST_MAX"
+          resval: 0x15E
+          desc: "Max burst Length between two memory refresh"
+        }
+      ]
+    },
+    {
+      name: "T_READ_WRITE_RECOVERY"
+      desc: "Idle time between transactions"
+      swaccess: "rw"
+      hwaccess:	"hrw"
+      fields: [
+       { bits: "3:0"
+          name: "T_READ_WRITE_RECOVERY"
+          resval: 0x6
+          desc: "Idle time between transactions"
+        }
+      ]
+    },
+    {
+      name: "T_RX_CLOCK_DELAY"
+      desc: "RX Delay Line"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "3:0"
+          name: "T_RX_CLOCK_DELAY"
+          resval: 0x8
+          desc: "RX Delay Line"
+	}
+      ]
+    },
+    {
+      name: "T_TX_CLOCK_DELAY"
+      desc: "TX Delay Line"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "3:0"
+          name: "T_TX_CLOCK_DELAY"
+          resval: 0x8
+          desc: "TX Delay Line"
+	}
+      ]
+    },
+    {
+      name: "ADDRESS_MASK_MSB"
+      desc: "Address Mask MSB"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "18:0"
+          name: "ADDRESS_MASK_MSB"
+          resval: 0x19
+          desc: "Address Mask MSB"
+        }
+      ]
+    },
+    {
+      name: "ADDRESS_SPACE"
+      desc: "L2 sleep configuration register"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:0"
+          name: "ADDRESS_SPACE"
+          resval: 0x0
+          desc: "L2 sleep configuration register"
+        }
+      ]
+    },
+    {
+      name: "PHYS_IN_USE"
+      desc: "Number of PHYs on use"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:0"
+          name: "PHYS_IN_USE"
+          resval: 0x1
+          desc: '''Number of PHYs on use:
+                - 1'b0: Uses 1 PHY
+                - 1'b1: Uses 2 PHYs
+                '''
+        }
+      ]
+    },
+    {
+      name: "WHICH_PHY"
+      desc: "PHY used in single PHY mode"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:0"
+          name: "WHICH_PHY"
+          resval: 0x1
+          desc:	'''PHY used in single PHY mode:
+                - 1'b0: PHY 0 is used
+                - 1'b1: PHY 1 is used
+      	      	'''
+        }
+      ]
+    },
+    {
+      name: "CS0_BASE"
+      desc: "CS0 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "31:0"
+          name: "CS0_BASE"
+          resval: 0x80000000
+          desc: "CS0 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS0_END"
+      desc: "CS0 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "31:0"
+          name: "CS0_END"
+          resval: 0x81000000
+          desc:	"CS0 End address range"
+        }
+      ]
+    },
+    {
+      name: "CS1_BASE"
+      desc: "CS1 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "31:0"
+          name: "CS1_BASE"
+          resval: 0x81000000
+          desc:	"CS1 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS1_END"
+      desc: "CS1 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "31:0"
+          name: "CS1_END"
+          resval: 0x82000000
+          desc: "CS1 End address range"
+        }
+      ]
+    },
+    {
+      name: "CS2_BASE"
+      desc: "CS2 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "31:0"
+          name: "CS2_BASE"
+          resval: 0x82000000
+          desc:	"CS2 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS2_END"
+      desc: "CS2 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "31:0"
+          name: "CS2_END"
+          resval: 0x83000000
+          desc: "CS2 End address range"
+        }
+      ]
+    },
+    {
+      name: "CS3_BASE"
+      desc: "CS3 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "31:0"
+          name: "CS3_BASE"
+          resval: 0x83000000
+          desc:	"CS3 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS3_END"
+      desc: "CS3 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "31:0"
+          name: "CS3_END"
+          resval: 0x84000000
+          desc: "CS3 End address range"
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/hyperbus/data/hyperbus.hjson~ b/docs/um/ip/hyperbus/data/hyperbus.hjson~
new file mode 100644
index 00000000..4bf4982e
--- /dev/null
+++ b/docs/um/ip/hyperbus/data/hyperbus.hjson~
@@ -0,0 +1,273 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// Part of the PULP platform project: https://pulp-platform.org
+// This file defines the register map for the HyperBus memory interface.
+
+// Register layout of hyperbus
+
+{
+  name: "hyperbus"
+  human_name: "HyperBus Controller"
+  one_line_desc: "HyperBus controller for interfacing with HyperRAM/Flash devices",
+  one_paragraph_desc: '''The HyperBus controller IP provides a flexible and programmable interface for communicating with external HyperRAM and HyperFlash memory devices. It supports AXI access, fine-grained
+                      clock and delay configuration, and physical interface control to meet timing closure and integration requirements.
+                      '''
+  cip_id: "36",
+  version: "0.0.0", //null
+
+  clocking: [
+    { clock: "clk_i", reset: "rst_ni", primary: true },
+    { clock: "clk_sys_i", reset: "rst_sys_ni" },
+    { clock: "clk_phy_i", reset: "rst_phy_ni" }
+  ],
+
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+   
+  regwidth: "32",
+  registers: [
+    {
+      name: "T_LATENCY_ACCESS"
+      desc: "Initial latency"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:3"
+          name: "T_LATENCY_ACCESS"
+          resval: 0x6
+          desc: "Initial latency"
+        }
+      ]
+    },
+    {
+      name: "EN_LATENCY_ADDITIONAL"
+      desc: "Force 2x Latency count"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:0"
+          name: "EN_LATENCY_ADDITIONAL"
+          resval: 0x0
+          desc: "Force 2x Latency count"
+        }
+      ]
+    },
+    {
+      name: "T_BURST_MAX"
+      desc: "Max burst Length between two memory refresh"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+       { bits: "0:15"
+          name: "T_BURST_MAX"
+          resval: 0x15E
+          desc: "Max burst Length between two memory refresh"
+        }
+      ]
+    },
+    {
+      name: "T_READ_WRITE_RECOVERY"
+      desc: "Idle time between transactions"
+      swaccess: "rw"
+      hwaccess:	"hrw"
+      fields: [
+       { bits: "0:3"
+          name: "T_READ_WRITE_RECOVERY"
+          resval: 0x6
+          desc: "Idle time between transactions"
+        }
+      ]
+    },
+    {
+      name: "T_RX_CLOCK_DELAY"
+      desc: "RX Delay Line"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:3"
+          name: "T_RX_CLOCK_DELAY"
+          resval: 0x8
+          desc: "RX Delay Line"
+	}
+      ]
+    },
+    {
+      name: "T_TX_CLOCK_DELAY"
+      desc: "TX Delay Line"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:3"
+          name: "T_TX_CLOCK_DELAY"
+          resval: 0x8
+          desc: "TX Delay Line"
+	}
+      ]
+    },
+    {
+      name: "ADDRESS_MASK_MSB"
+      desc: "Address Mask MSB"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:18"
+          name: "ADDRESS_MASK_MSB"
+          resval: 0x19
+          desc: "Address Mask MSB"
+        }
+      ]
+    },
+    {
+      name: "ADDRESS_SPACE"
+      desc: "L2 sleep configuration register"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:0"
+          name: "ADDRESS_SPACE"
+          resval: 0x0
+          desc: "L2 sleep configuration register"
+        }
+      ]
+    },
+    {
+      name: "PHYS_IN_USE"
+      desc: "Number of PHYs on use"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:0"
+          name: "PHYS_IN_USE"
+          resval: 0x1
+          desc: '''Number of PHYs on use:
+                - 1'b0: Uses 1 PHY
+                - 1'b1: Uses 2 PHYs
+                '''
+        }
+      ]
+    },
+    {
+      name: "WHICH_PHY"
+      desc: "PHY used in single PHY mode"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:0"
+          name: "WHICH_PHY"
+          resval: 0x1
+          desc:	'''PHY used in single PHY mode:
+                - 1'b0: PHY 0 is used
+                - 1'b1: PHY 1 is used
+      	      	'''
+        }
+      ]
+    },
+    {
+      name: "CS0_BASE"
+      desc: "CS0 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0:31"
+          name: "CS0_BASE"
+          resval: 0x80000000
+          desc: "CS0 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS0_END"
+      desc: "CS0 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:31"
+          name: "CS0_END"
+          resval: 0x81000000
+          desc:	"CS0 End address range"
+        }
+      ]
+    },
+    {
+      name: "CS1_BASE"
+      desc: "CS1 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:31"
+          name: "CS1_BASE"
+          resval: 0x81000000
+          desc:	"CS1 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS1_END"
+      desc: "CS1 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:31"
+          name: "CS1_END"
+          resval: 0x82000000
+          desc: "CS1 End address range"
+        }
+      ]
+    },
+    {
+      name: "CS2_BASE"
+      desc: "CS2 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:31"
+          name: "CS2_BASE"
+          resval: 0x82000000
+          desc:	"CS2 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS2_END"
+      desc: "CS2 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:31"
+          name: "CS2_END"
+          resval: 0x83000000
+          desc: "CS2 End address range"
+        }
+      ]
+    },
+    {
+      name: "CS3_BASE"
+      desc: "CS3 Base address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:31"
+          name: "CS3_BASE"
+          resval: 0x83000000
+          desc:	"CS3 Base address range"
+        }
+      ]
+    },
+    {
+      name: "CS3_END"
+      desc: "CS3 End address range"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      fields: [
+	{ bits: "0:31"
+          name: "CS3_END"
+          resval: 0x84000000
+          desc: "CS3 End address range"
+        }
+      ]
+    }
+  ]
+}
diff --git a/docs/um/ip/hyperbus/doc/registers.md b/docs/um/ip/hyperbus/doc/registers.md
new file mode 100644
index 00000000..56d265d0
--- /dev/null
+++ b/docs/um/ip/hyperbus/doc/registers.md
@@ -0,0 +1,321 @@
+## Summary
+
+| Name                                                       | Offset   |   Length | Description                                 |
+|:-----------------------------------------------------------|:---------|---------:|:--------------------------------------------|
+| hyperbus.[`T_LATENCY_ACCESS`](#t_latency_access)           | 0x0      |        4 | Initial latency                             |
+| hyperbus.[`EN_LATENCY_ADDITIONAL`](#en_latency_additional) | 0x4      |        4 | Force 2x Latency count                      |
+| hyperbus.[`T_BURST_MAX`](#t_burst_max)                     | 0x8      |        4 | Max burst Length between two memory refresh |
+| hyperbus.[`T_READ_WRITE_RECOVERY`](#t_read_write_recovery) | 0xc      |        4 | Idle time between transactions              |
+| hyperbus.[`T_RX_CLOCK_DELAY`](#t_rx_clock_delay)           | 0x10     |        4 | RX Delay Line                               |
+| hyperbus.[`T_TX_CLOCK_DELAY`](#t_tx_clock_delay)           | 0x14     |        4 | TX Delay Line                               |
+| hyperbus.[`ADDRESS_MASK_MSB`](#address_mask_msb)           | 0x18     |        4 | Address Mask MSB                            |
+| hyperbus.[`ADDRESS_SPACE`](#address_space)                 | 0x1c     |        4 | L2 sleep configuration register             |
+| hyperbus.[`PHYS_IN_USE`](#phys_in_use)                     | 0x20     |        4 | Number of PHYs on use                       |
+| hyperbus.[`WHICH_PHY`](#which_phy)                         | 0x24     |        4 | PHY used in single PHY mode                 |
+| hyperbus.[`CS0_BASE`](#cs0_base)                           | 0x28     |        4 | CS0 Base address range                      |
+| hyperbus.[`CS0_END`](#cs0_end)                             | 0x2c     |        4 | CS0 End address range                       |
+| hyperbus.[`CS1_BASE`](#cs1_base)                           | 0x30     |        4 | CS1 Base address range                      |
+| hyperbus.[`CS1_END`](#cs1_end)                             | 0x34     |        4 | CS1 End address range                       |
+| hyperbus.[`CS2_BASE`](#cs2_base)                           | 0x38     |        4 | CS2 Base address range                      |
+| hyperbus.[`CS2_END`](#cs2_end)                             | 0x3c     |        4 | CS2 End address range                       |
+| hyperbus.[`CS3_BASE`](#cs3_base)                           | 0x40     |        4 | CS3 Base address range                      |
+| hyperbus.[`CS3_END`](#cs3_end)                             | 0x44     |        4 | CS3 End address range                       |
+
+## T_LATENCY_ACCESS
+Initial latency
+- Offset: `0x0`
+- Reset default: `0x6`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_LATENCY_ACCESS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description     |
+|:------:|:------:|:-------:|:-----------------|:----------------|
+|  31:4  |        |         |                  | Reserved        |
+|  3:0   |   rw   |   0x6   | T_LATENCY_ACCESS | Initial latency |
+
+## EN_LATENCY_ADDITIONAL
+Force 2x Latency count
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "EN_LATENCY_ADDITIONAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description            |
+|:------:|:------:|:-------:|:----------------------|:-----------------------|
+|  31:1  |        |         |                       | Reserved               |
+|   0    |   rw   |   0x0   | EN_LATENCY_ADDITIONAL | Force 2x Latency count |
+
+## T_BURST_MAX
+Max burst Length between two memory refresh
+- Offset: `0x8`
+- Reset default: `0x15e`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_BURST_MAX", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                 |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------|
+| 31:16  |        |         |             | Reserved                                    |
+|  15:0  |   rw   |  0x15e  | T_BURST_MAX | Max burst Length between two memory refresh |
+
+## T_READ_WRITE_RECOVERY
+Idle time between transactions
+- Offset: `0xc`
+- Reset default: `0x6`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_READ_WRITE_RECOVERY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                    |
+|:------:|:------:|:-------:|:----------------------|:-------------------------------|
+|  31:4  |        |         |                       | Reserved                       |
+|  3:0   |   rw   |   0x6   | T_READ_WRITE_RECOVERY | Idle time between transactions |
+
+## T_RX_CLOCK_DELAY
+RX Delay Line
+- Offset: `0x10`
+- Reset default: `0x8`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_RX_CLOCK_DELAY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:4  |        |         |                  | Reserved      |
+|  3:0   |   rw   |   0x8   | T_RX_CLOCK_DELAY | RX Delay Line |
+
+## T_TX_CLOCK_DELAY
+TX Delay Line
+- Offset: `0x14`
+- Reset default: `0x8`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_TX_CLOCK_DELAY", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+|  31:4  |        |         |                  | Reserved      |
+|  3:0   |   rw   |   0x8   | T_TX_CLOCK_DELAY | TX Delay Line |
+
+## ADDRESS_MASK_MSB
+Address Mask MSB
+- Offset: `0x18`
+- Reset default: `0x19`
+- Reset mask: `0x7ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS_MASK_MSB", "bits": 19, "attr": ["rw"], "rotate": 0}, {"bits": 13}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description      |
+|:------:|:------:|:-------:|:-----------------|:-----------------|
+| 31:19  |        |         |                  | Reserved         |
+|  18:0  |   rw   |  0x19   | ADDRESS_MASK_MSB | Address Mask MSB |
+
+## ADDRESS_SPACE
+L2 sleep configuration register
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS_SPACE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                     |
+|:------:|:------:|:-------:|:--------------|:--------------------------------|
+|  31:1  |        |         |               | Reserved                        |
+|   0    |   rw   |   0x0   | ADDRESS_SPACE | L2 sleep configuration register |
+
+## PHYS_IN_USE
+Number of PHYs on use
+- Offset: `0x20`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PHYS_IN_USE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                                   |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                                      |
+|   0    |   rw   |   0x1   | PHYS_IN_USE | Number of PHYs on use: - 1'b0: Uses 1 PHY - 1'b1: Uses 2 PHYs |
+
+## WHICH_PHY
+PHY used in single PHY mode
+- Offset: `0x24`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "WHICH_PHY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                              |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------------------|
+|  31:1  |        |         |           | Reserved                                                                 |
+|   0    |   rw   |   0x1   | WHICH_PHY | PHY used in single PHY mode: - 1'b0: PHY 0 is used - 1'b1: PHY 1 is used |
+
+## CS0_BASE
+CS0 Base address range
+- Offset: `0x28`
+- Reset default: `0x80000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS0_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x80000000 | CS0_BASE | CS0 Base address range |
+
+## CS0_END
+CS0 End address range
+- Offset: `0x2c`
+- Reset default: `0x81000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS0_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x81000000 | CS0_END | CS0 End address range |
+
+## CS1_BASE
+CS1 Base address range
+- Offset: `0x30`
+- Reset default: `0x81000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS1_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x81000000 | CS1_BASE | CS1 Base address range |
+
+## CS1_END
+CS1 End address range
+- Offset: `0x34`
+- Reset default: `0x82000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS1_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x82000000 | CS1_END | CS1 End address range |
+
+## CS2_BASE
+CS2 Base address range
+- Offset: `0x38`
+- Reset default: `0x82000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS2_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x82000000 | CS2_BASE | CS2 Base address range |
+
+## CS2_END
+CS2 End address range
+- Offset: `0x3c`
+- Reset default: `0x83000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS2_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x83000000 | CS2_END | CS2 End address range |
+
+## CS3_BASE
+CS3 Base address range
+- Offset: `0x40`
+- Reset default: `0x83000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS3_BASE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description            |
+|:------:|:------:|:----------:|:---------|:-----------------------|
+|  31:0  |   rw   | 0x83000000 | CS3_BASE | CS3 Base address range |
+
+## CS3_END
+CS3 End address range
+- Offset: `0x44`
+- Reset default: `0x84000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CS3_END", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name    | Description           |
+|:------:|:------:|:----------:|:--------|:----------------------|
+|  31:0  |   rw   | 0x84000000 | CS3_END | CS3 End address range |
+
diff --git a/docs/um/ip/i2c/data/i2c_ot.hjson b/docs/um/ip/i2c/data/i2c_ot.hjson
new file mode 100644
index 00000000..a7c2f542
--- /dev/null
+++ b/docs/um/ip/i2c/data/i2c_ot.hjson
@@ -0,0 +1,1138 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{
+  name:               "i2c",
+  human_name:         "I2C Interface",
+  one_line_desc:      "I2C interface for host and device mode, supporting up to 1 Mbaud data rates",
+  one_paragraph_desc: '''
+  I2C Interface implements the I2C serial communication protocol.
+  It can be configured in host (master) or device (slave) mode and supports standard data rate (100 kbaud), fast data rate (400 kbaud), and fast plus data rate (1 Mbaud).
+  In addition to supporting all mandatory I2C features, this block supports clock stretching in host mode and automatic clock stretching in device mode.
+  I2C Interface uses a 7-bit address space and is compatible with any device covered by I2C specification operating at speeds up to 1 Mbaud.
+  '''
+  // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
+  cip_id:             "11",
+  design_spec:        "../doc",
+  dv_doc:             "../doc/dv",
+  hw_checklist:       "../doc/checklist",
+  sw_checklist:       "/sw/device/lib/dif/dif_i2c",
+  revisions: [
+    {
+      version:            "2.1.0",
+      life_stage:         "L1",
+      design_stage:       "D2S",
+      verification_stage: "V2S",
+      dif_stage:          "S2",
+      notes:              "Verification Stage is V2S qualified by the given exceptions in PR#22108. This broadly excludes verif. of multi-controller features."
+    }
+  ]
+  clocking: [{clock: "clk_i", reset: "rst_ni"}],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device", racl_support: true }
+  ],
+  // INPUT pins
+  available_inout_list: [
+    { name: "sda", desc: "Serial input data bit" }
+    { name: "scl", desc: "Serial input clock bit" }
+  ]
+  // INTERRUPT pins
+  interrupt_list: [
+    { name: "fmt_threshold"
+      desc: "host mode interrupt: asserted whilst the FMT FIFO level is below the low threshold. This is a level status interrupt."
+      type: "status"
+    }
+    { name: "rx_threshold"
+      desc: "host mode interrupt: asserted whilst the RX FIFO level is above the high threshold. This is a level status interrupt."
+      type: "status"
+    }
+    { name: "acq_threshold"
+      desc: "target mode interrupt: asserted whilst the ACQ FIFO level is above the high threshold. This is a level status interrupt."
+      type: "status"
+    }
+    { name: "rx_overflow"
+      desc: "host mode interrupt: raised if the RX FIFO has overflowed."
+    }
+    { name: "controller_halt"
+      desc: '''
+            host mode interrupt: raised if the controller FSM is halted, such as on an unexpected NACK or lost arbitration.
+            Check !!CONTROLLER_EVENTS for the reason.
+            The interrupt will be released when the bits in !!CONTROLLER_EVENTS are cleared.
+            '''
+      type: "status"
+    }
+    { name: "scl_interference"
+      desc: "host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization)."
+    }
+    { name: "sda_interference"
+      desc: "host mode interrupt: raised if the SDA line goes low when host is trying to assert high"
+    }
+    { name: "stretch_timeout"
+      desc: "host mode interrupt: raised if target stretches the clock beyond the allowed timeout period"
+    }
+    { name: "sda_unstable"
+      desc: "host mode interrupt: raised if the target does not assert a constant value of SDA during transmission."
+    }
+    { name: "cmd_complete"
+      desc: '''
+        host and target mode interrupt.
+        In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP.
+        In target mode, raised if the external host issues a STOP or repeated START.
+      '''
+    }
+    { name: "tx_stretch"
+      desc: "target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt."
+      type: "status"
+    }
+    { name: "tx_threshold"
+      desc: "target mode interrupt: asserted whilst the TX FIFO level is below the low threshold. This is a level status interrupt."
+      type: "status"
+    }
+    { name: "acq_stretch"
+      desc: "target mode interrupt: raised if the target is stretching clocks due to full ACQ FIFO or zero count in !!TARGET_ACK_CTRL.NBYTES (if enabled). This is a level status interrupt."
+      type: "status"
+    }
+    { name: "unexp_stop"
+      desc: "target mode interrupt: raised if STOP is received without a preceding NACK during an external host read."
+    }
+    { name: "host_timeout"
+      desc: "target mode interrupt: raised if the host stops sending the clock during an ongoing transaction."
+    }
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  inter_signal_list: [
+    // RAM configuration
+    { struct:  "ram_1p_cfg"
+      package: "prim_ram_1p_pkg"
+      type:    "uni"
+      name:    "ram_cfg"
+      act:     "rcv"
+    }
+    { struct:  "ram_1p_cfg_rsp"
+      package: "prim_ram_1p_pkg"
+      type:    "uni"
+      name:    "ram_cfg_rsp"
+      act:     "req"
+    }
+    { struct: "logic"
+      type:   "uni"
+      name:   "lsio_trigger"
+      desc: '''
+            Self-clearing status trigger for the DMA.
+            Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour.
+      '''
+      act:    "req"
+    }
+    { struct:  "racl_policy_vec",
+      type:    "uni",
+      name:    "racl_policies",
+      act:     "rcv",
+      package: "top_racl_pkg",
+      desc:    '''
+        Incoming RACL policy vector from a racl_ctrl instance.
+        The policy selection vector (parameter) selects the policy for each register.
+      '''
+    }
+    { struct:  "racl_error_log",
+      type:    "uni",
+      name:    "racl_error",
+      act:     "req",
+      width:   "1"
+      package: "top_racl_pkg",
+      desc:    '''
+        RACL error log information of this module.
+      '''
+    }
+  ]
+  param_list: [
+    { name: "FifoDepth",
+      desc: '''
+            Depth of FMT, RX, and TX FIFOs.
+            The maximum supported value is 2^12-1, although much lower values are recommended to keep area requirements reasonable.
+            ''',
+      type: "int",
+      default: "64",
+    }
+    { name: "AcqFifoDepth",
+      desc: '''
+            Depth of ACQ FIFO.
+            The maximum supported value is 2^12-1, although much lower values are recommended to keep area requirements reasonable.
+            ''',
+      type: int
+      default: "268",
+    }
+    { name:    "InputDelayCycles",
+      type:    "int",
+      default: "0",
+      desc:    '''
+               Maximum number of cycles of propagation delay between a change on the cio_scl_en_o or cio_sda_en_o pins and sensing the new values on the corresponding input pins, not including the rise/fall times.
+               For the purposes of this calculation, an input delay of 0 cycles means an output pin changing at the beginning of clock edge N will be sampled and observed on the input pins at clock edge N+1.
+               '''
+      local:   "false",
+      expose:  "true"
+    }
+  ],
+  features: [
+    { name: "I2C.MODE.HOST",
+      desc: '''
+            The I2C block can be configued in host mode.
+            '''
+    },
+    { name: "I2C.MODE.TARGET",
+      desc: '''
+            The I2C block can be configured in target mode.
+            '''
+    },
+    { name: "I2C.MODE.ACKCONTROL",
+      desc: '''
+            The I2C Target module can be configured to support N-byte ACK Control Mode.
+            With ACK Control Mode off, software provides no protocol-level control of deciding whether to ACK or NACK bytes.
+            With ACK Control Mode on, software may choose whether to ACK Write data bytes.
+            Software may program the Target module to ACK up to N bytes without software intervention.
+            The configuration resets to 0 for the next transfer.
+            '''
+    },
+    { name: "I2C.SPEED.STANDARD",
+      desc: '''
+            Standard-mode of 100 kbaud is supported.
+            '''
+    },
+    { name: "I2C.SPEED.FAST",
+      desc: '''
+            Fast-mode of 400 kbaud is supported.
+            '''
+    },
+    { name: "I2C.SPEED.FASTPLUS",
+      desc: '''
+            Fast-mode Plus of 1 Mbaud is supported.
+            '''
+    },
+    { name: "I2C.OVERRIDE",
+      desc: '''
+            Software can override the values of SCL and SDA.
+            '''
+    },
+    { name: "I2C.OPERATION.READ",
+      desc: '''
+            Hosts can read from targets.
+            '''
+    },
+    { name: "I2C.OPERATION.WRITE",
+      desc: '''
+            Hosts can write to targets.
+            '''
+    },
+    { name: "I2C.PROTOCOL.CLOCKSTRETCHING",
+      desc: '''
+            Clock stretching is a way for a target to buy time.
+            There are three scenarios when clock stretching occurs:
+            - After an address read.
+            - During a write.
+            - During a read.
+            '''
+    },
+    { name: "I2C.PROTOCOL.NACK",
+      desc: '''
+            Whenever a byte is sent, it must be accompanied by an acknowledgement (ack), unless NAKOK is high.
+            When no ack is received, this is a nack.
+            '''
+    },
+    { name: "I2C.PROTOCOL.REPEATEDSTART",
+      desc: '''
+            Instead of doing a stop and then a start to start the next transaction, a host can choose to perform a repeated start to begin a new transaction without stopping the previous one.
+            '''
+    },
+  ],
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+  ]
+
+  // REGISTER definition
+  regwidth: "32"
+  registers: [
+    // CTRL register
+    { name: "CTRL"
+      desc: "I2C Control Register"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0"
+          resval: "0"
+          name: "ENABLEHOST"
+          desc: '''
+                Enable Host I2C functionality
+                '''
+        }
+        { bits: "1"
+          resval: "0"
+          name: "ENABLETARGET"
+          desc: '''
+                Enable Target I2C functionality
+                '''
+        }
+        { bits: "2"
+          resval: "0"
+          name: "LLPBK"
+          desc: '''
+                Enable I2C line loopback test
+                If line loopback is enabled, the internal design sees ACQ and RX data as "1"
+                '''
+          tags: [// Exclude from write-checks: writing 1'b1 to this bit causes interrupts unexpectedly asserted
+                "excl:CsrAllTests:CsrExclWrite"]
+        }
+        { bits: "3"
+          resval: "0"
+          name: "NACK_ADDR_AFTER_TIMEOUT"
+          desc: '''
+                Enable NACKing the address on a stretch timeout.
+
+                This is a Target mode feature.
+                If enabled (1), a stretch timeout will cause the device to NACK the address byte.
+                If disabled (0), a stretch timeout will cause the device to ACK the address byte.
+                SMBus requires that devices always ACK their address, even for read commands.
+                However, non-SMBus protocols may have a different approach and can choose to NACK instead.
+
+                Note that both cases handle data bytes the same way.
+                For writes, the Target module will NACK all subsequent data bytes until it receives a Stop.
+                For reads, the Target module will release SDA, causing 0xff to be returned for all data bytes until it receives a Stop.
+                '''
+        }
+        { bits: "4"
+          resval: "0"
+          name: "ACK_CTRL_EN"
+          desc: '''
+                Enable I2C Target ACK Control Mode.
+
+                ACK Control Mode works together with !!TARGET_ACK_CTRL.NBYTES to allow software to control upper-layer protocol (N)ACKing (e.g. as in SMBus).
+                This bit enables the mode when 1, and !!TARGET_ACK_CTRL.NBYTES limits how many bytes may be automatically ACK'd while the ACQ FIFO has space.
+                If it is 0, the decision to ACK or NACK is made only from stretching timeouts and !!CTRL.NACK_ADDR_AFTER_TIMEOUT.
+                '''
+        }
+        { bits: "5"
+          resval: "0"
+          name: "MULTI_CONTROLLER_MONITOR_EN"
+          desc: '''
+                Enable the bus monitor in multi-controller mode.
+
+                If a 0->1 transition happens while !!CTRL.ENABLEHOST and !!CTRL.ENABLETARGET are both 0, the bus monitor will enable and begin in the "bus busy" state.
+                To transition to a bus free state, !!HOST_TIMEOUT_CTRL must be nonzero, so the bus monitor may count out idle cycles to confirm the freedom to transmit.
+                In addition, the bus monitor will track whether the bus is free based on the enabled timeouts and detected Stop symbols.
+                For multi-controller mode, ensure !!CTRL.MULTI_CONTROLLER_MONITOR_EN becomes 1 no later than !!CTRL.ENABLEHOST or !!CTRL.ENABLETARGET.
+                This bit can be set at the same time as either or both of the other two, though.
+
+                Note that if !!CTRL.MULTI_CONTROLLER_MONITOR_EN is set after !!CTRL.ENABLEHOST or !!CTRL.ENABLETARGET, the bus monitor will begin in the "bus free" state instead.
+                This would violate the proper protocol for a controller to join a multi-controller environment.
+                However, if this controller is known to be the first to join, this ordering will enable skipping the idle wait.
+
+                When 0, the bus monitor will report that the bus is always free, so the controller FSM is never blocked from transmitting.
+                '''
+        }
+        { bits: "6"
+          resval: "0"
+          name: "TX_STRETCH_CTRL_EN"
+          desc: '''
+                If set to 1, this bit causes a read transfer addressed to this target to set the corresponding bit in !!TARGET_EVENTS.
+
+                While !!TARGET_EVENTS.TX_PENDING is 1, subsequent read transactions will stretch the clock, even if there is data in the TX FIFO.
+
+                If enabled, this function allows software to confirm the data in the TX FIFO should be released for the current read.
+                This may be useful for cases where the TX FIFO has data that does not apply to the current transfer.
+                For example, the transaction could've targeted an alternate function via another address.
+                '''
+        }
+      ]
+    }
+    { name:     "STATUS"
+      desc:     "I2C Live Status Register for Host and Target modes"
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwext:    "true"
+      fields: [
+        { bits: "0"
+          name: "FMTFULL"
+          desc: "Host mode FMT FIFO is full"
+        }
+        { bits: "1"
+          name: "RXFULL"
+          desc: "Host mode RX FIFO is full"
+        }
+        { bits: "2"
+          name: "FMTEMPTY"
+          desc: "Host mode FMT FIFO is empty"
+          resval: "1"
+        }
+        { bits: "5"
+          name: "RXEMPTY"
+          desc: "Host mode RX FIFO is empty"
+          resval: "1"
+        }
+        { bits: "3"
+          name: "HOSTIDLE"
+          desc: "Host functionality is idle. No Host transaction is in progress"
+          resval: "1"
+        }
+        { bits: "4"
+          name: "TARGETIDLE"
+          desc: "Target functionality is idle. No Target transaction is in progress"
+          resval: "1"
+        }
+        { bits: "6"
+          name: "TXFULL"
+          desc: "Target mode TX FIFO is full"
+        }
+        { bits: "7"
+          name: "ACQFULL"
+          desc: "Target mode receive FIFO is full"
+        }
+        { bits: "8"
+          name: "TXEMPTY"
+          desc: "Target mode TX FIFO is empty"
+          resval: "1"
+        }
+        { bits: "9"
+          name: "ACQEMPTY"
+          desc: "Target mode receive FIFO is empty"
+          resval: "1"
+        }
+        { bits: "10"
+          name: "ACK_CTRL_STRETCH"
+          desc: "Target mode stretching at (N)ACK phase due to zero count in !!TARGET_ACK_CTRL.NBYTES"
+        }
+      ]
+      tags: [// Updated by the hw. Exclude from write-checks.
+             "excl:CsrNonInitTests:CsrExclWriteCheck"]
+    }
+    { name: "RDATA"
+      desc: "I2C Read Data"
+      swaccess: "ro"
+      hwaccess: "hrw"
+      hwext: "true"
+      hwre: "true"
+      fields: [
+        {bits: "7:0"}
+      ]
+      tags: [// Updated by the hw. Exclude from init and write-checks.
+             "excl:CsrAllTests:CsrExclCheck"]
+    }
+    { name: "FDATA"
+      desc: '''I2C Host Format Data
+
+            Writes to this register are used to define and drive Controller-Mode transactions.
+            '''
+      swaccess: "wo"
+      hwaccess: "hro"
+      hwqe: "true"
+      fields: [
+        { bits: "7:0"
+          name: "FBYTE"
+          desc: '''Format Byte.
+
+                If no flags are set, hardware will transmit this byte directly.
+
+                If READB is set, this field becomes the number of bytes hardware will automatically
+                read from the bus.
+                '''
+        }
+        { bits: "8"
+          name: "START"
+          desc: "Issue a START condition before transmitting FBYTE."
+        }
+        { bits: "9"
+          name: "STOP"
+          desc: "Issue a STOP condition after transmitting FBYTE."
+        }
+        { bits: "10"
+          name: "READB"
+          desc: '''Transfer Direction Indicator.
+
+                If unset, this write to FDATA defines a controller-transmitter operation (WRITE).
+                A single byte of data (FBYTE) is written to the bus.
+
+                If set, this write to FDATA defines a controller-receiver operation (READ).
+                The value of FBYTE defines the number of bytes read from the bus. (256 if FBYTE==0)"
+                After this number of bytes are read, the final byte will be NACKed to end the transfer
+                unless RCONT is also set.
+                '''
+        }
+        { bits: "11"
+          name: "RCONT"
+          desc: "Do not NACK the last byte read, let the read operation continue."
+        }
+        { bits: "12"
+          name: "NAKOK"
+          desc: '''
+                For the currrent controller-transmitter byte (WRITE), do not halt via CONTROLLER_EVENTS
+                or assert the 'controller_halt' interrupt if the current byte is not ACK'd.
+                '''
+        }
+      ]
+      tags: [// FIFO can fill up due to write check accesses, and then fail an assertion upon timeout on full.
+             "excl:CsrNonInitTests:CsrExclWriteCheck"]
+    }
+    { name: "FIFO_CTRL"
+      desc: "I2C FIFO control register"
+      swaccess: "rw"
+      hwaccess: "hro"
+      hwqe: "true"
+      fields: [
+        { bits: "0"
+          swaccess: "wo"
+          name: "RXRST"
+          desc: "RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0"
+        }
+        { bits: "1"
+          swaccess: "wo"
+          name: "FMTRST"
+          desc: "FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0"
+        }
+        { bits: "7"
+          swaccess: "wo"
+          name: "ACQRST"
+          desc: "ACQ FIFO reset. Write 1 to the register resets it. Read returns 0"
+        }
+        { bits: "8"
+          swaccess: "wo"
+          name: "TXRST"
+          desc: "TX FIFO reset. Write 1 to the register resets it. Read returns 0"
+        }
+      ]
+    }
+    {
+      name: "HOST_FIFO_CONFIG"
+      desc: "Host mode FIFO configuration"
+      swaccess: "rw"
+      hwaccess: "hro"
+      hwqe: "true"
+      fields: [
+        { bits: "11:0"
+          name: "RX_THRESH"
+          desc: '''Threshold level for RX interrupts. Whilst the level of data in the RX FIFO
+                is above this setting, the rx_threshold interrupt will be asserted.
+                '''
+          resval: "0"
+        }
+        { bits: "27:16"
+          name: "FMT_THRESH"
+          desc: '''Threshold level for FMT interrupts. Whilst the number of used entries in the
+                FMT FIFO is below this setting, the fmt_threshold interrupt will be asserted.
+                '''
+          resval: "0"
+        }
+      ]
+    }
+    {
+      name: "TARGET_FIFO_CONFIG"
+      desc: "Target mode FIFO configuration"
+      swaccess: "rw"
+      hwaccess: "hro"
+      hwqe: "true"
+      fields: [
+        { bits: "11:0"
+          name: "TX_THRESH"
+          desc: '''Threshold level for TX interrupts. Whilst the number of used entries in the
+                TX FIFO is below this setting, the tx_threshold interrupt will be asserted.
+                '''
+          resval: "0"
+        }
+        { bits: "27:16"
+          name: "ACQ_THRESH"
+          desc: '''Threshold level for ACQ interrupts. Whilst the level of data in the ACQ FIFO
+                is above this setting, the acq_threshold interrupt will be asserted.
+                '''
+          resval: "0"
+        }
+      ]
+    }
+    { name: "HOST_FIFO_STATUS"
+      desc: "Host mode FIFO status register"
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwext: "true"
+      fields: [
+        { bits: "11:0"
+          name: "FMTLVL"
+          desc: "Current fill level of FMT fifo"
+        }
+        { bits: "27:16"
+          name: "RXLVL"
+          desc: "Current fill level of RX fifo"
+        }
+      ]
+      tags: [// Updated by the hw. Exclude from write-checks.
+             "excl:CsrNonInitTests:CsrExclWriteCheck"]
+    }
+    { name: "TARGET_FIFO_STATUS"
+      desc: "Target mode FIFO status register"
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwext: "true"
+      fields: [
+        { bits: "11:0"
+          name: "TXLVL"
+          desc: "Current fill level of TX fifo"
+        }
+        { bits: "27:16"
+          name: "ACQLVL"
+          desc: "Current fill level of ACQ fifo"
+        }
+      ]
+      tags: [// Updated by the hw. Exclude from write-checks.
+             "excl:CsrNonInitTests:CsrExclWriteCheck"]
+    }
+    { name: "OVRD"
+      desc: "I2C Override Control Register"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "0",
+          name: "TXOVRDEN",
+          desc: "Override the SDA and SCL TX signals."
+        }
+        { bits: "1",
+          name: "SCLVAL",
+          desc: "Value for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z"
+        }
+        { bits: "2",
+          name: "SDAVAL",
+          desc: "Value for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z"
+        }
+      ]
+      tags: [// Overriding can cause sda/scl_interference interrupts to trigger continously.
+             // These then become unclearable interrupts at the end of csr_tests (clear_all_interrupts() fails).
+             "excl:CsrRwTest:CsrExclWriteCheck"]
+    }
+    { name: "VAL"
+      desc: "Oversampled RX values"
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwext:    "true"
+      fields: [
+        { bits: "15:0"
+          name: "SCL_RX"
+          desc: '''
+                Last 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.
+                '''
+        }
+        { bits: "31:16"
+          name: "SDA_RX"
+          desc: '''
+                Last 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31.
+                '''
+        }
+      ]
+      tags: [// Affected by IO pins - exclude from init and write checks.
+             "excl:CsrAllTests:CsrExclCheck"]
+    }
+
+    { name: "TIMING0"
+      desc: '''
+            Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+            All values are expressed in units of the input clock period.
+            These must be greater than 2 in order for the change in SCL to propagate to the input of the FSM so that acknowledgements are detected correctly.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "12:0"
+          name: "THIGH"
+          desc: '''
+                The actual time to hold SCL high in a given pulse.
+                This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.
+                '''
+        }
+        { bits: "28:16"
+          name: "TLOW"
+          desc: '''
+                The actual time to hold SCL low between any two SCL pulses.
+                This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz.
+                '''
+        }
+      ]
+    }
+    { name: "TIMING1",
+      desc: '''
+            Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+            All values are expressed in units of the input clock period.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "9:0"
+          name: "T_R"
+          desc: '''
+                The nominal rise time to anticipate for the bus (depends on capacitance).
+                This field is sized to have a range of at least Standard Mode's 1000 ns max with a core clock at 1 GHz.
+                '''
+        }
+        { bits: "24:16"
+          name: "T_F"
+          desc: '''
+                The nominal fall time to anticipate for the bus (influences SDA hold times).
+                This field is sized to have a range of at least Standard Mode's 300 ns max with a core clock at 1 GHz.
+                '''
+        }
+      ]
+    }
+    { name: "TIMING2"
+      desc: '''
+            Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+            All values are expressed in units of the input clock period.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "12:0"
+          name: "TSU_STA"
+          desc: '''
+                Actual setup time for repeated start signals.
+                This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz.
+                '''
+        }
+        { bits: "28:16"
+          name: "THD_STA"
+          desc: '''
+                Actual hold time for start signals.
+                This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.
+                '''
+        }
+      ]
+    }
+    { name: "TIMING3"
+      desc: '''
+            Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+            All values are expressed in units of the input clock period.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "8:0"
+          name: "TSU_DAT"
+          desc: '''
+                Actual setup time for data (or ack) bits.
+                This field is sized to have a range of at least Standard Mode's 250 ns max with a core clock at 1 GHz.
+                '''
+        }
+        { bits: "28:16"
+          name: "THD_DAT"
+          desc: '''
+                Actual hold time for data (or ack) bits.
+                (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
+                This field is sized to have a range that accommodates Standard Mode's 3.45 us max for TVD_DAT with a core clock at 1 GHz.
+                However, this field is generally expected to represent a time substantially shorter than that.
+                It should be long enough to cover the maximum round-trip latency from output pins, through pads and voltage transitions on the board, and back to the input pins, but it should not be substantially greater.
+                '''
+        }
+      ]
+    }
+    { name: "TIMING4"
+      desc: '''
+            Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+            All values are expressed in units of the input clock period.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "12:0"
+          name: "TSU_STO"
+          desc: '''
+                Actual setup time for stop signals.
+                This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.
+                '''
+        }
+        { bits: "28:16"
+          name: "T_BUF"
+          desc: '''
+                Actual time between each STOP signal and the following START signal.
+                This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz.
+                '''
+        }
+      ]
+    }
+    { name: "TIMEOUT_CTRL"
+      desc: '''
+            I2C clock stretching and bus timeout control.
+
+            This timeout must be enabled by setting !!TIMEOUT_CTRL.EN to 1, and the behavior of this feature depends on the value of !!TIMEOUT_CTRL.MODE.
+
+            If the mode is "STRETCH_TIMEOUT", this is used in I2C controller mode to detect whether a connected target is stretching a single low time beyond the timeout value.
+            Configured as such, this timeout is more informative and doesn't do more than assert the "stretch_timeout" interrupt.
+
+            If the mode is "BUS_TIMEOUT", it is used to detect whether the clock has been held low for too long instead, inclusive of the controller's clock low time.
+            This is useful for an SMBus context, where the VAL programmed should be tTIMEOUT:MIN.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "29:0"
+          name: "VAL"
+          desc: "Clock stretching timeout value (in units of input clock frequency)"
+        }
+        { bits: "30"
+          name: "MODE"
+          desc: '''
+                Selects the timeout mode, between a stretch timeout and a bus timeout.
+
+                Between the two modes, the primary difference is how much of the clock low period is counted.
+                For a stretch timeout, only the time that another device holds the clock low will be counted.
+                For a bus timeout, the entire clock low time is counted, consistent with the SMBus tTIMEOUT type.
+
+                !!TIMEOUT_CTRL.EN must be 1 for either of these features to be enabled.
+                '''
+          enum: [
+            { value: "0",
+              name: "STRETCH_TIMEOUT",
+              desc: '''
+                    The timeout is a target stretch timeout.
+                    The counter will track how long the clock has been stretched by another device while the controller is active.
+                    '''
+            },
+            { value: "1",
+              name: "BUS_TIMEOUT",
+              desc: '''
+                    The timeout is a clock low timeout.
+                    The counter will track how long the clock low period is, inclusive of the controller's ordinary low count.
+                    A timeout will set !!CONTROLLER_EVENTS.BUS_TIMEOUT and cause a "controller_halt" interrupt.
+                    '''
+            },
+          ],
+        }
+        { bits: "31"
+          name: "EN"
+          desc: "Enable stretch timeout or bus timeout feature"
+        }
+      ]
+    }
+    { name: "TARGET_ID"
+      desc: "I2C target address and mask pairs"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "6:0"
+          name: "ADDRESS0"
+          desc: "I2C target address number 0"
+        }
+        { bits: "13:7"
+          name: "MASK0"
+          desc: '''
+                I2C target mask number 0.
+                At least one bit in MASK0 must be set to 1 for ADDRESS0 to be used.
+                '''
+        }
+        { bits: "20:14"
+          name: "ADDRESS1"
+          desc: "I2C target address number 1"
+        }
+        { bits: "27:21"
+          name: "MASK1"
+          desc: '''
+                I2C target mask number 1.
+                At least one bit in MASK1 must be set to 1 for ADDRESS1 to be used.
+                '''
+        }
+      ]
+    }
+    { name: "ACQDATA"
+      desc: "I2C target acquired data"
+      swaccess: "ro"
+      hwaccess: "hrw"
+      hwext: "true"
+      hwre: "true"
+      fields: [
+        { bits: "7:0"
+          name: "ABYTE"
+          desc: "Address for accepted transaction or acquired byte"
+        }
+        { bits: "10:8"
+          name: "SIGNAL"
+          desc: '''
+                Indicates any control symbols associated with the ABYTE.
+
+                For the STOP symbol, a stretch timeout or other unexpected events will cause a NACK_STOP to appear in the ACQ FIFO.
+                If the ACQ FIFO doesn't have enough space to record a START and a STOP, the transaction will be dropped entirely on a stretch timeout.
+                In that case, the START byte will not appear (neither as START nor NACK_START), but a standalone NACK_STOP may, if there was space.
+                Software can discard any standalone NACK_STOP that appears.
+
+                See the associated values for more information about the contents.
+                '''
+          enum: [
+            { value: "0",
+              name: "NONE",
+              desc: "ABYTE contains an ordinary data byte that was received and ACK'd."
+            },
+            { value: "1",
+              name: "START",
+              desc: '''
+                    A START condition preceded the ABYTE to start a new transaction.
+                    ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.
+                    '''
+            },
+            { value: "2",
+              name: "STOP",
+              desc: '''
+                    A STOP condition was received for a transaction including a transfer that addressed this Target.
+                    No transfers addressing this Target in that transaction were NACK'd.
+                    ABYTE contains no data.
+                    '''
+            },
+            { value: "3",
+              name: "RESTART",
+              desc: '''
+                    A repeated START condition preceded the ABYTE, extending the current transaction with a new transfer.
+                    ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.
+                    '''
+            },
+            { value: "4",
+              name: "NACK",
+              desc: '''ABYTE contains an ordinary data byte that was received and NACK'd.'''
+            },
+            { value: "5",
+              name: "NACK_START",
+              desc: '''
+                    A START condition preceded the ABYTE (including repeated START) that was part of a NACK'd transfer.
+                    The ABYTE contains the matching I2C address and command bit.
+                    The ABYTE was ACK'd, but the rest of the transaction was NACK'ed.
+                    '''
+            },
+            { value: "6",
+              name: "NACK_STOP",
+              desc: '''
+                    A transaction including a transfer that addressed this Target was ended, but the transaction ended abnormally and/or the transfer was NACK'd.
+                    The end can be due to a STOP condition or unexpected events, such as a bus timeout (if enabled).
+                    ABYTE contains no data.
+
+                    NACKing can occur for multiple reasons, including a stretch timeout, a SW-directed NACK, or lost arbitration.
+                    This signal is a bucket for all these error-type terminations.
+                    '''
+            },
+          ]
+        }
+      ]
+      tags: [// Updated by the hw. Exclude from init and write-checks.
+             // Without actual I2C traffic, read from this FIFO returns Xs.
+             "excl:CsrAllTests:CsrExclCheck"]
+    }
+    { name: "TXDATA"
+      desc: "I2C target transmit data"
+      swaccess: "wo"
+      hwaccess: "hro"
+      hwqe: "true"
+      fields: [
+        { bits: "7:0" }
+      ]
+      tags: [// FIFO can fill up due to write check accesses, and then fail an assertion upon timeout on full.
+             "excl:CsrNonInitTests:CsrExclWriteCheck"]
+    }
+    { name: "HOST_TIMEOUT_CTRL"
+      desc: '''
+            I2C host clock generation timeout value (in units of input clock frequency).
+
+            In an active transaction in Target-Mode, if the Controller ceases to send SCL pulses
+            for this number of cycles then the "host_timeout" interrupt will be asserted.
+
+            In multi-controller monitoring mode, !!HOST_TIMEOUT_CTRL is required to be nonzero to transition out of the initial busy state.
+            Set this CSR to 0 to disable this behaviour.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "19:0" }
+      ]
+    }
+    { name: "TARGET_TIMEOUT_CTRL"
+      desc: '''
+            I2C target internal stretching timeout control.
+            When the target has stretched beyond this time it will send a NACK for incoming data bytes or release SDA for outgoing data bytes.
+            The behavior for the address byte is configurable via !!CTRL.ACK_ADDR_AFTER_TIMEOUT.
+            Note that the count accumulates stretching time over the course of a transaction.
+            In other words, this is equivalent to the SMBus cumulative target clock extension time.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "30:0"
+          name: "VAL"
+          desc: "Clock stretching timeout value (in units of input clock frequency)"
+        }
+        { bits: "31"
+          name: "EN"
+          desc: "Enable timeout feature and send NACK once the timeout has been reached"
+        }
+      ]
+    }
+    { name: "TARGET_NACK_COUNT"
+      desc: '''
+            Number of times the I2C target has NACK'ed a new transaction since the last read of this register.
+            Reading this register clears it.
+            This is useful because when the ACQ FIFO is full the software know that a NACK has occurred, but without this register would not know how many transactions it missed.
+            When it reaches its maximum value it will stay at that value.
+            '''
+      swaccess: "rc"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "7:0" }
+      ]
+    }
+    { name: "TARGET_ACK_CTRL"
+      desc: "Controls for mid-transfer (N)ACK phase handling"
+      swaccess: "rw"
+      hwaccess: "hrw"
+      hwqe: true
+      hwext: true
+      fields: [
+        { bits: "8:0"
+          name: "NBYTES"
+          desc: '''
+                Remaining number of bytes the Target module may ACK automatically.
+
+                If !!CTRL.ACK_CTRL_EN is set to 1, the Target module will stretch the clock at the (N)ACK phase of a byte if this CSR is 0, awaiting software's instructions.
+
+                At the beginning of each Write transfer, this byte count is reset to 0.
+                Writes to this CSR also are only accepted while the Target module is stretching the clock.
+                The Target module will always ACK its address if the ACQ FIFO has space.
+                For data bytes afterwards, it will stop at the (N)ACK phase and stretch the clock when this CSR is 0.
+                For each data byte that is ACK'd in a transaction, the byte count will decrease by 1.
+
+                Note that a full ACQ FIFO can still cause the Target module to halt at the beginning of a new byte.
+                The ACK Control Mode provides an additional synchronization point, during the (N)ACK phase instead of after.
+                For both cases, !!TARGET_TIMEOUT_CTRL applies, and stretching past the timeout will produce an automatic NACK.
+
+                This mode can be used to implement the mid-transfer (N)ACK responses required by various SMBus protocols.
+                '''
+          tags: [// Writes only succeed in a specific stretching state. Exclude from write-checks.
+                 "excl:CsrNonInitTests:CsrExclWriteCheck"]
+        }
+        { bits: "31"
+          name: "NACK"
+          swaccess: "wo"
+          hwaccess: "hro"
+          desc: '''
+                When the Target module stretches on the (N)ACK phase of a Write due to !!TARGET_ACK_CTRL.NBYTES being 0, writing a 1 here will cause it to send a NACK.
+
+                If software chooses to NACK, note that the NACKing behavior is the same as if a stretch timeout occurred.
+                The rest of the transaction will be NACK'd, including subsequent transfers.
+                For the address byte, the (N)ACK phase of subsequent transfers will follow the behavior specified by !!CTRL.NACK_ADDR_AFTER_TIMEOUT.
+
+                Automatically clears to 0.
+                '''
+        }
+      ]
+    }
+    { name: "ACQ_FIFO_NEXT_DATA"
+      desc: '''
+            The data byte pending to be written to the ACQ FIFO.
+
+            This CSR is only valid while the Target module is stretching in the (N)ACK phase, indicated by !!STATUS.ACK_CTRL_STRETCH .
+            It is intended to be used with ACK Control Mode, so software may check the current byte.
+            '''
+      swaccess: "ro"
+      hwaccess: "hwo"
+      hwext: true
+      fields: [
+        { bits: "7:0" }
+      ]
+      tags: [// Updated by the hw. Exclude from init and write-checks.
+             // Without actual I2C traffic, read from this CSR returns Xs.
+             "excl:CsrAllTests:CsrExclCheck"]
+    }
+    { name: "HOST_NACK_HANDLER_TIMEOUT"
+      desc: '''
+            Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.
+            (in units of input clock frequency)
+
+            If an active Controller-Transmitter transfer receives a NACK from the Target, the !!CONTROLLER_EVENTS.NACK bit is set.
+            In turn, this causes the Controller FSM to halt awaiting software intervention, and the 'controller_halt' interrupt may assert.
+            Software must clear the !!CONTROLLER_EVENTS.NACK bit to allow the state machine to continue, typically after clearing out the FMTFIFO to start a new transfer.
+            While halted, the active transaction is not ended (no STOP (P) condition is created), and the block asserts SCL and leaves SDA released.
+
+            This timeout can be used to automatically produce a STOP condition, whether as a backstop for slow software responses (longer timeout) or as a convenience (short timeout).
+            If the timeout expires, the Controller FSM will issue a STOP (P) condition on the bus to end the active transaction.
+            Additionally, the !!CONTROLLER_EVENTS.UNHANDLED_NACK_TIMEOUT bit is set to alert software, and the FSM will return to the idle state and halt until the bit is cleared.
+
+            The enable bit must be set for this feature to operate.
+            '''
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "30:0"
+          name: "VAL"
+          desc: "Unhandled NAK timeout value (in units of input clock frequency)"
+        }
+        { bits: "31"
+          name: "EN"
+          desc: "Timeout enable"
+        }
+      ]
+    }
+    { name: "CONTROLLER_EVENTS"
+      desc: '''
+            Latched events that explain why the controller halted.
+
+            Any bits that are set must be written (with a 1) to clear the CONTROLLER_HALT interrupt.
+            '''
+      swaccess: "rw1c"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0"
+          name: "NACK"
+          desc: "Received an unexpected NACK"
+        }
+        { bits: "1"
+          name: "UNHANDLED_NACK_TIMEOUT"
+          desc: "A Host-Mode active transaction has been ended by the !!HOST_NACK_HANDLER_TIMEOUT mechanism."
+        }
+        { bits: "2"
+          name: "BUS_TIMEOUT"
+          desc: "A Host-Mode active transaction has terminated due to a bus timeout activated by !!TIMEOUT_CTRL."
+        }
+        { bits: "3"
+          name: "ARBITRATION_LOST"
+          desc: "A Host-Mode active transaction has terminated due to lost arbitration."
+        }
+      ]
+      tags: ["excl:CsrAllTests:CsrExclCheck"]
+    }
+    { name: "TARGET_EVENTS"
+      desc: '''
+            Latched events that can cause the target module to stretch the clock at the beginning of a read transfer.
+
+            These events cause TX FIFO-related stretching even when the TX FIFO has data available.
+            Any bits that are set must be written (with a 1) to clear the tx_stretch interrupt.
+
+            This CSR serves as a gate to prevent the Target module from responding to a read command with unrelated, leftover data.
+            '''
+      swaccess: "rw1c"
+      hwaccess: "hrw"
+      fields: [
+        { bits: "0"
+          name: "TX_PENDING"
+          desc: '''
+                A new Target-Mode read transfer has arrived that addressed this target.
+
+                This bit is used by software to confirm the release of the contents in the TX FIFO.
+                If the contents do not apply, software should first reset the TX FIFO, then load it with the correct data, then clear this bit.
+
+                Optionally enabled by !!CTRL.TX_STRETCH_CTRL_EN.
+                '''
+        }
+        { bits: "1"
+          name: "BUS_TIMEOUT"
+          desc: "A Target-Mode read transfer has terminated due to a bus timeout activated by !!TIMEOUT_CTRL."
+        }
+        { bits: "2"
+          name: "ARBITRATION_LOST"
+          desc: "A Target-Mode read transfer has terminated due to lost arbitration."
+        }
+      ]
+      tags: ["excl:CsrAllTests:CsrExclCheck"]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/i2c/doc/registers.md b/docs/um/ip/i2c/doc/registers.md
new file mode 100644
index 00000000..84ca1915
--- /dev/null
+++ b/docs/um/ip/i2c/doc/registers.md
@@ -0,0 +1,913 @@
+## Summary
+
+| Name                                                          | Offset   |   Length | Description                                                                                               |
+|:--------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------------|
+| i2c.[`INTR_STATE`](#intr_state)                               | 0x0      |        4 | Interrupt State Register                                                                                  |
+| i2c.[`INTR_ENABLE`](#intr_enable)                             | 0x4      |        4 | Interrupt Enable Register                                                                                 |
+| i2c.[`INTR_TEST`](#intr_test)                                 | 0x8      |        4 | Interrupt Test Register                                                                                   |
+| i2c.[`ALERT_TEST`](#alert_test)                               | 0xc      |        4 | Alert Test Register                                                                                       |
+| i2c.[`CTRL`](#ctrl)                                           | 0x10     |        4 | I2C Control Register                                                                                      |
+| i2c.[`STATUS`](#status)                                       | 0x14     |        4 | I2C Live Status Register for Host and Target modes                                                        |
+| i2c.[`RDATA`](#rdata)                                         | 0x18     |        4 | I2C Read Data                                                                                             |
+| i2c.[`FDATA`](#fdata)                                         | 0x1c     |        4 | I2C Host Format Data                                                                                      |
+| i2c.[`FIFO_CTRL`](#fifo_ctrl)                                 | 0x20     |        4 | I2C FIFO control register                                                                                 |
+| i2c.[`HOST_FIFO_CONFIG`](#host_fifo_config)                   | 0x24     |        4 | Host mode FIFO configuration                                                                              |
+| i2c.[`TARGET_FIFO_CONFIG`](#target_fifo_config)               | 0x28     |        4 | Target mode FIFO configuration                                                                            |
+| i2c.[`HOST_FIFO_STATUS`](#host_fifo_status)                   | 0x2c     |        4 | Host mode FIFO status register                                                                            |
+| i2c.[`TARGET_FIFO_STATUS`](#target_fifo_status)               | 0x30     |        4 | Target mode FIFO status register                                                                          |
+| i2c.[`OVRD`](#ovrd)                                           | 0x34     |        4 | I2C Override Control Register                                                                             |
+| i2c.[`VAL`](#val)                                             | 0x38     |        4 | Oversampled RX values                                                                                     |
+| i2c.[`TIMING0`](#timing0)                                     | 0x3c     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING1`](#timing1)                                     | 0x40     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING2`](#timing2)                                     | 0x44     |        4 | Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).                       |
+| i2c.[`TIMING3`](#timing3)                                     | 0x48     |        4 | Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).                      |
+| i2c.[`TIMING4`](#timing4)                                     | 0x4c     |        4 | Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).                      |
+| i2c.[`TIMEOUT_CTRL`](#timeout_ctrl)                           | 0x50     |        4 | I2C clock stretching and bus timeout control.                                                             |
+| i2c.[`TARGET_ID`](#target_id)                                 | 0x54     |        4 | I2C target address and mask pairs                                                                         |
+| i2c.[`ACQDATA`](#acqdata)                                     | 0x58     |        4 | I2C target acquired data                                                                                  |
+| i2c.[`TXDATA`](#txdata)                                       | 0x5c     |        4 | I2C target transmit data                                                                                  |
+| i2c.[`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl)                 | 0x60     |        4 | I2C host clock generation timeout value (in units of input clock frequency).                              |
+| i2c.[`TARGET_TIMEOUT_CTRL`](#target_timeout_ctrl)             | 0x64     |        4 | I2C target internal stretching timeout control.                                                           |
+| i2c.[`TARGET_NACK_COUNT`](#target_nack_count)                 | 0x68     |        4 | Number of times the I2C target has NACK'ed a new transaction since the last read of this register.        |
+| i2c.[`TARGET_ACK_CTRL`](#target_ack_ctrl)                     | 0x6c     |        4 | Controls for mid-transfer (N)ACK phase handling                                                           |
+| i2c.[`ACQ_FIFO_NEXT_DATA`](#acq_fifo_next_data)               | 0x70     |        4 | The data byte pending to be written to the ACQ FIFO.                                                      |
+| i2c.[`HOST_NACK_HANDLER_TIMEOUT`](#host_nack_handler_timeout) | 0x74     |        4 | Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.            |
+| i2c.[`CONTROLLER_EVENTS`](#controller_events)                 | 0x78     |        4 | Latched events that explain why the controller halted.                                                    |
+| i2c.[`TARGET_EVENTS`](#target_events)                         | 0x7c     |        4 | Latched events that can cause the target module to stretch the clock at the beginning of a read transfer. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                                                                                                                                                                                                            |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                                                                                                                                                                                                                                               |
+|   14   |  rw1c  |   0x0   | host_timeout     | target mode interrupt: raised if the host stops sending the clock during an ongoing transaction.                                                                                                                                                                                       |
+|   13   |  rw1c  |   0x0   | unexp_stop       | target mode interrupt: raised if STOP is received without a preceding NACK during an external host read.                                                                                                                                                                               |
+|   12   |   ro   |   0x0   | acq_stretch      | target mode interrupt: raised if the target is stretching clocks due to full ACQ FIFO or zero count in [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) (if enabled). This is a level status interrupt.                                                                                    |
+|   11   |   ro   |   0x0   | tx_threshold     | target mode interrupt: asserted whilst the TX FIFO level is below the low threshold. This is a level status interrupt.                                                                                                                                                                 |
+|   10   |   ro   |   0x0   | tx_stretch       | target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.                                                                                                                                                                 |
+|   9    |  rw1c  |   0x0   | cmd_complete     | host and target mode interrupt. In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.                                                                   |
+|   8    |  rw1c  |   0x0   | sda_unstable     | host mode interrupt: raised if the target does not assert a constant value of SDA during transmission.                                                                                                                                                                                 |
+|   7    |  rw1c  |   0x0   | stretch_timeout  | host mode interrupt: raised if target stretches the clock beyond the allowed timeout period                                                                                                                                                                                            |
+|   6    |  rw1c  |   0x0   | sda_interference | host mode interrupt: raised if the SDA line goes low when host is trying to assert high                                                                                                                                                                                                |
+|   5    |  rw1c  |   0x0   | scl_interference | host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).                                                                                                                                                                                 |
+|   4    |   ro   |   0x0   | controller_halt  | host mode interrupt: raised if the controller FSM is halted, such as on an unexpected NACK or lost arbitration. Check [`CONTROLLER_EVENTS`](#controller_events) for the reason. The interrupt will be released when the bits in [`CONTROLLER_EVENTS`](#controller_events) are cleared. |
+|   3    |  rw1c  |   0x0   | rx_overflow      | host mode interrupt: raised if the RX FIFO has overflowed.                                                                                                                                                                                                                             |
+|   2    |   ro   |   0x0   | acq_threshold    | target mode interrupt: asserted whilst the ACQ FIFO level is above the high threshold. This is a level status interrupt.                                                                                                                                                               |
+|   1    |   ro   |   0x0   | rx_threshold     | host mode interrupt: asserted whilst the RX FIFO level is above the high threshold. This is a level status interrupt.                                                                                                                                                                  |
+|   0    |   ro   |   0x0   | fmt_threshold    | host mode interrupt: asserted whilst the FMT FIFO level is below the low threshold. This is a level status interrupt.                                                                                                                                                                  |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                                   |
+|   14   |   rw   |   0x0   | host_timeout     | Enable interrupt when [`INTR_STATE.host_timeout`](#intr_state) is set.     |
+|   13   |   rw   |   0x0   | unexp_stop       | Enable interrupt when [`INTR_STATE.unexp_stop`](#intr_state) is set.       |
+|   12   |   rw   |   0x0   | acq_stretch      | Enable interrupt when [`INTR_STATE.acq_stretch`](#intr_state) is set.      |
+|   11   |   rw   |   0x0   | tx_threshold     | Enable interrupt when [`INTR_STATE.tx_threshold`](#intr_state) is set.     |
+|   10   |   rw   |   0x0   | tx_stretch       | Enable interrupt when [`INTR_STATE.tx_stretch`](#intr_state) is set.       |
+|   9    |   rw   |   0x0   | cmd_complete     | Enable interrupt when [`INTR_STATE.cmd_complete`](#intr_state) is set.     |
+|   8    |   rw   |   0x0   | sda_unstable     | Enable interrupt when [`INTR_STATE.sda_unstable`](#intr_state) is set.     |
+|   7    |   rw   |   0x0   | stretch_timeout  | Enable interrupt when [`INTR_STATE.stretch_timeout`](#intr_state) is set.  |
+|   6    |   rw   |   0x0   | sda_interference | Enable interrupt when [`INTR_STATE.sda_interference`](#intr_state) is set. |
+|   5    |   rw   |   0x0   | scl_interference | Enable interrupt when [`INTR_STATE.scl_interference`](#intr_state) is set. |
+|   4    |   rw   |   0x0   | controller_halt  | Enable interrupt when [`INTR_STATE.controller_halt`](#intr_state) is set.  |
+|   3    |   rw   |   0x0   | rx_overflow      | Enable interrupt when [`INTR_STATE.rx_overflow`](#intr_state) is set.      |
+|   2    |   rw   |   0x0   | acq_threshold    | Enable interrupt when [`INTR_STATE.acq_threshold`](#intr_state) is set.    |
+|   1    |   rw   |   0x0   | rx_threshold     | Enable interrupt when [`INTR_STATE.rx_threshold`](#intr_state) is set.     |
+|   0    |   rw   |   0x0   | fmt_threshold    | Enable interrupt when [`INTR_STATE.fmt_threshold`](#intr_state) is set.    |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fmt_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "controller_halt", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "scl_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_interference", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "stretch_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "sda_unstable", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "cmd_complete", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_threshold", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "acq_stretch", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "unexp_stop", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "host_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                         |
+|:------:|:------:|:-------:|:-----------------|:--------------------------------------------------------------------|
+| 31:15  |        |         |                  | Reserved                                                            |
+|   14   |   wo   |   0x0   | host_timeout     | Write 1 to force [`INTR_STATE.host_timeout`](#intr_state) to 1.     |
+|   13   |   wo   |   0x0   | unexp_stop       | Write 1 to force [`INTR_STATE.unexp_stop`](#intr_state) to 1.       |
+|   12   |   wo   |   0x0   | acq_stretch      | Write 1 to force [`INTR_STATE.acq_stretch`](#intr_state) to 1.      |
+|   11   |   wo   |   0x0   | tx_threshold     | Write 1 to force [`INTR_STATE.tx_threshold`](#intr_state) to 1.     |
+|   10   |   wo   |   0x0   | tx_stretch       | Write 1 to force [`INTR_STATE.tx_stretch`](#intr_state) to 1.       |
+|   9    |   wo   |   0x0   | cmd_complete     | Write 1 to force [`INTR_STATE.cmd_complete`](#intr_state) to 1.     |
+|   8    |   wo   |   0x0   | sda_unstable     | Write 1 to force [`INTR_STATE.sda_unstable`](#intr_state) to 1.     |
+|   7    |   wo   |   0x0   | stretch_timeout  | Write 1 to force [`INTR_STATE.stretch_timeout`](#intr_state) to 1.  |
+|   6    |   wo   |   0x0   | sda_interference | Write 1 to force [`INTR_STATE.sda_interference`](#intr_state) to 1. |
+|   5    |   wo   |   0x0   | scl_interference | Write 1 to force [`INTR_STATE.scl_interference`](#intr_state) to 1. |
+|   4    |   wo   |   0x0   | controller_halt  | Write 1 to force [`INTR_STATE.controller_halt`](#intr_state) to 1.  |
+|   3    |   wo   |   0x0   | rx_overflow      | Write 1 to force [`INTR_STATE.rx_overflow`](#intr_state) to 1.      |
+|   2    |   wo   |   0x0   | acq_threshold    | Write 1 to force [`INTR_STATE.acq_threshold`](#intr_state) to 1.    |
+|   1    |   wo   |   0x0   | rx_threshold     | Write 1 to force [`INTR_STATE.rx_threshold`](#intr_state) to 1.     |
+|   0    |   wo   |   0x0   | fmt_threshold    | Write 1 to force [`INTR_STATE.fmt_threshold`](#intr_state) to 1.    |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CTRL
+I2C Control Register
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ENABLEHOST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ENABLETARGET", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NACK_ADDR_AFTER_TIMEOUT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACK_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MULTI_CONTROLLER_MONITOR_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TX_STRETCH_CTRL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                              |
+|:------:|:------:|:-------:|:------------------------------------------------------------------|
+|  31:7  |        |         | Reserved                                                          |
+|   6    |   rw   |   0x0   | [TX_STRETCH_CTRL_EN](#ctrl--tx_stretch_ctrl_en)                   |
+|   5    |   rw   |   0x0   | [MULTI_CONTROLLER_MONITOR_EN](#ctrl--multi_controller_monitor_en) |
+|   4    |   rw   |   0x0   | [ACK_CTRL_EN](#ctrl--ack_ctrl_en)                                 |
+|   3    |   rw   |   0x0   | [NACK_ADDR_AFTER_TIMEOUT](#ctrl--nack_addr_after_timeout)         |
+|   2    |   rw   |   0x0   | [LLPBK](#ctrl--llpbk)                                             |
+|   1    |   rw   |   0x0   | [ENABLETARGET](#ctrl--enabletarget)                               |
+|   0    |   rw   |   0x0   | [ENABLEHOST](#ctrl--enablehost)                                   |
+
+### CTRL . TX_STRETCH_CTRL_EN
+If set to 1, this bit causes a read transfer addressed to this target to set the corresponding bit in [`TARGET_EVENTS.`](#target_events)
+
+While [`TARGET_EVENTS.TX_PENDING`](#target_events) is 1, subsequent read transactions will stretch the clock, even if there is data in the TX FIFO.
+
+If enabled, this function allows software to confirm the data in the TX FIFO should be released for the current read.
+This may be useful for cases where the TX FIFO has data that does not apply to the current transfer.
+For example, the transaction could've targeted an alternate function via another address.
+
+### CTRL . MULTI_CONTROLLER_MONITOR_EN
+Enable the bus monitor in multi-controller mode.
+
+If a 0->1 transition happens while [`CTRL.ENABLEHOST`](#ctrl) and [`CTRL.ENABLETARGET`](#ctrl) are both 0, the bus monitor will enable and begin in the "bus busy" state.
+To transition to a bus free state, [`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl) must be nonzero, so the bus monitor may count out idle cycles to confirm the freedom to transmit.
+In addition, the bus monitor will track whether the bus is free based on the enabled timeouts and detected Stop symbols.
+For multi-controller mode, ensure [`CTRL.MULTI_CONTROLLER_MONITOR_EN`](#ctrl) becomes 1 no later than [`CTRL.ENABLEHOST`](#ctrl) or [`CTRL.ENABLETARGET.`](#ctrl)
+This bit can be set at the same time as either or both of the other two, though.
+
+Note that if [`CTRL.MULTI_CONTROLLER_MONITOR_EN`](#ctrl) is set after [`CTRL.ENABLEHOST`](#ctrl) or [`CTRL.ENABLETARGET`](#ctrl), the bus monitor will begin in the "bus free" state instead.
+This would violate the proper protocol for a controller to join a multi-controller environment.
+However, if this controller is known to be the first to join, this ordering will enable skipping the idle wait.
+
+When 0, the bus monitor will report that the bus is always free, so the controller FSM is never blocked from transmitting.
+
+### CTRL . ACK_CTRL_EN
+Enable I2C Target ACK Control Mode.
+
+ACK Control Mode works together with [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) to allow software to control upper-layer protocol (N)ACKing (e.g. as in SMBus).
+This bit enables the mode when 1, and [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) limits how many bytes may be automatically ACK'd while the ACQ FIFO has space.
+If it is 0, the decision to ACK or NACK is made only from stretching timeouts and [`CTRL.NACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+
+### CTRL . NACK_ADDR_AFTER_TIMEOUT
+Enable NACKing the address on a stretch timeout.
+
+This is a Target mode feature.
+If enabled (1), a stretch timeout will cause the device to NACK the address byte.
+If disabled (0), a stretch timeout will cause the device to ACK the address byte.
+SMBus requires that devices always ACK their address, even for read commands.
+However, non-SMBus protocols may have a different approach and can choose to NACK instead.
+
+Note that both cases handle data bytes the same way.
+For writes, the Target module will NACK all subsequent data bytes until it receives a Stop.
+For reads, the Target module will release SDA, causing 0xff to be returned for all data bytes until it receives a Stop.
+
+### CTRL . LLPBK
+Enable I2C line loopback test
+If line loopback is enabled, the internal design sees ACQ and RX data as "1"
+
+### CTRL . ENABLETARGET
+Enable Target I2C functionality
+
+### CTRL . ENABLEHOST
+Enable Host I2C functionality
+
+## STATUS
+I2C Live Status Register for Host and Target modes
+- Offset: `0x14`
+- Reset default: `0x33c`
+- Reset mask: `0x7ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FMTFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FMTEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HOSTIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TARGETIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACQEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACK_CTRL_STRETCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                              |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------|
+| 31:11  |        |         |                  | Reserved                                                                                                 |
+|   10   |   ro   |    x    | ACK_CTRL_STRETCH | Target mode stretching at (N)ACK phase due to zero count in [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) |
+|   9    |   ro   |   0x1   | ACQEMPTY         | Target mode receive FIFO is empty                                                                        |
+|   8    |   ro   |   0x1   | TXEMPTY          | Target mode TX FIFO is empty                                                                             |
+|   7    |   ro   |    x    | ACQFULL          | Target mode receive FIFO is full                                                                         |
+|   6    |   ro   |    x    | TXFULL           | Target mode TX FIFO is full                                                                              |
+|   5    |   ro   |   0x1   | RXEMPTY          | Host mode RX FIFO is empty                                                                               |
+|   4    |   ro   |   0x1   | TARGETIDLE       | Target functionality is idle. No Target transaction is in progress                                       |
+|   3    |   ro   |   0x1   | HOSTIDLE         | Host functionality is idle. No Host transaction is in progress                                           |
+|   2    |   ro   |   0x1   | FMTEMPTY         | Host mode FMT FIFO is empty                                                                              |
+|   1    |   ro   |    x    | RXFULL           | Host mode RX FIFO is full                                                                                |
+|   0    |   ro   |    x    | FMTFULL          | Host mode FMT FIFO is full                                                                               |
+
+## RDATA
+I2C Read Data
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   ro   |    x    | RDATA  |               |
+
+## FDATA
+I2C Host Format Data
+
+Writes to this register are used to define and drive Controller-Mode transactions.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FBYTE", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STOP", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "READB", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RCONT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "NAKOK", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   |
+|:------:|:------:|:-------:|:-----------------------|
+| 31:13  |        |         | Reserved               |
+|   12   |   wo   |   0x0   | [NAKOK](#fdata--nakok) |
+|   11   |   wo   |   0x0   | [RCONT](#fdata--rcont) |
+|   10   |   wo   |   0x0   | [READB](#fdata--readb) |
+|   9    |   wo   |   0x0   | [STOP](#fdata--stop)   |
+|   8    |   wo   |   0x0   | [START](#fdata--start) |
+|  7:0   |   wo   |   0x0   | [FBYTE](#fdata--fbyte) |
+
+### FDATA . NAKOK
+For the currrent controller-transmitter byte (WRITE), do not halt via CONTROLLER_EVENTS
+or assert the 'controller_halt' interrupt if the current byte is not ACK'd.
+
+### FDATA . RCONT
+Do not NACK the last byte read, let the read operation continue.
+
+### FDATA . READB
+Transfer Direction Indicator.
+
+If unset, this write to FDATA defines a controller-transmitter operation (WRITE).
+A single byte of data (FBYTE) is written to the bus.
+
+If set, this write to FDATA defines a controller-receiver operation (READ).
+The value of FBYTE defines the number of bytes read from the bus. (256 if FBYTE==0)"
+After this number of bytes are read, the final byte will be NACKed to end the transfer
+unless RCONT is also set.
+
+### FDATA . STOP
+Issue a STOP condition after transmitting FBYTE.
+
+### FDATA . START
+Issue a START condition before transmitting FBYTE.
+
+### FDATA . FBYTE
+Format Byte.
+
+If no flags are set, hardware will transmit this byte directly.
+
+If READB is set, this field becomes the number of bytes hardware will automatically
+read from the bus.
+
+## FIFO_CTRL
+I2C FIFO control register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x183`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "FMTRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 5}, {"name": "ACQRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                             |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------|
+|  31:9  |        |         |        | Reserved                                                                |
+|   8    |   wo   |   0x0   | TXRST  | TX FIFO reset. Write 1 to the register resets it. Read returns 0        |
+|   7    |   wo   |   0x0   | ACQRST | ACQ FIFO reset. Write 1 to the register resets it. Read returns 0       |
+|  6:2   |        |         |        | Reserved                                                                |
+|   1    |   wo   |   0x0   | FMTRST | FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0 |
+|   0    |   wo   |   0x0   | RXRST  | RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0   |
+
+## HOST_FIFO_CONFIG
+Host mode FIFO configuration
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "FMT_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                                |
+|:------:|:------:|:-------:|:-----------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:28  |        |         |            | Reserved                                                                                                                                                   |
+| 27:16  |   rw   |   0x0   | FMT_THRESH | Threshold level for FMT interrupts. Whilst the number of used entries in the FMT FIFO is below this setting, the fmt_threshold interrupt will be asserted. |
+| 15:12  |        |         |            | Reserved                                                                                                                                                   |
+|  11:0  |   rw   |   0x0   | RX_THRESH  | Threshold level for RX interrupts. Whilst the level of data in the RX FIFO is above this setting, the rx_threshold interrupt will be asserted.             |
+
+## TARGET_FIFO_CONFIG
+Target mode FIFO configuration
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "ACQ_THRESH", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                             |
+|:------:|:------:|:-------:|:-----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:28  |        |         |            | Reserved                                                                                                                                                |
+| 27:16  |   rw   |   0x0   | ACQ_THRESH | Threshold level for ACQ interrupts. Whilst the level of data in the ACQ FIFO is above this setting, the acq_threshold interrupt will be asserted.       |
+| 15:12  |        |         |            | Reserved                                                                                                                                                |
+|  11:0  |   rw   |   0x0   | TX_THRESH  | Threshold level for TX interrupts. Whilst the number of used entries in the TX FIFO is below this setting, the tx_threshold interrupt will be asserted. |
+
+## HOST_FIFO_STATUS
+Host mode FIFO status register
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FMTLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "RXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:28  |        |         |        | Reserved                       |
+| 27:16  |   ro   |    x    | RXLVL  | Current fill level of RX fifo  |
+| 15:12  |        |         |        | Reserved                       |
+|  11:0  |   ro   |    x    | FMTLVL | Current fill level of FMT fifo |
+
+## TARGET_FIFO_STATUS
+Target mode FIFO status register
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xfff0fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "ACQLVL", "bits": 12, "attr": ["ro"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                    |
+|:------:|:------:|:-------:|:-------|:-------------------------------|
+| 31:28  |        |         |        | Reserved                       |
+| 27:16  |   ro   |    x    | ACQLVL | Current fill level of ACQ fifo |
+| 15:12  |        |         |        | Reserved                       |
+|  11:0  |   ro   |    x    | TXLVL  | Current fill level of TX fifo  |
+
+## OVRD
+I2C Override Control Register
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXOVRDEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SCLVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SDAVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                               |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------|
+|  31:3  |        |         |          | Reserved                                                                  |
+|   2    |   rw   |   0x0   | SDAVAL   | Value for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z |
+|   1    |   rw   |   0x0   | SCLVAL   | Value for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z |
+|   0    |   rw   |   0x0   | TXOVRDEN | Override the SDA and SCL TX signals.                                      |
+
+## VAL
+Oversampled RX values
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "SCL_RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"name": "SDA_RX", "bits": 16, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------|
+| 31:16  |   ro   |    x    | SDA_RX | Last 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31. |
+|  15:0  |   ro   |    x    | SCL_RX | Last 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.  |
+
+## TIMING0
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+These must be greater than 2 in order for the change in SCL to propagate to the input of the FSM so that acknowledgements are detected correctly.
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "THIGH", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "TLOW", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                        |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |        | Reserved                                                                                                                                                           |
+| 28:16  |   rw   |   0x0   | TLOW   | The actual time to hold SCL low between any two SCL pulses. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+| 15:13  |        |         |        | Reserved                                                                                                                                                           |
+|  12:0  |   rw   |   0x0   | THIGH  | The actual time to hold SCL high in a given pulse. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.          |
+
+## TIMING1
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x1ff03ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "T_R", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "T_F", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                                                                                                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:25  |        |         |        | Reserved                                                                                                                                                                            |
+| 24:16  |   rw   |   0x0   | T_F    | The nominal fall time to anticipate for the bus (influences SDA hold times). This field is sized to have a range of at least Standard Mode's 300 ns max with a core clock at 1 GHz. |
+| 15:10  |        |         |        | Reserved                                                                                                                                                                            |
+|  9:0   |   rw   |   0x0   | T_R    | The nominal rise time to anticipate for the bus (depends on capacitance). This field is sized to have a range of at least Standard Mode's 1000 ns max with a core clock at 1 GHz.   |
+
+## TIMING2
+Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "THD_STA", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                          |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |         | Reserved                                                                                                                                             |
+| 28:16  |   rw   |   0x0   | THD_STA | Actual hold time for start signals. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.           |
+| 15:13  |        |         |         | Reserved                                                                                                                                             |
+|  12:0  |   rw   |   0x0   | TSU_STA | Actual setup time for repeated start signals. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+
+## TIMING3
+Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x1fff01ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_DAT", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "THD_DAT", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         |
+|:------:|:------:|:-------:|:-----------------------------|
+| 31:29  |        |         | Reserved                     |
+| 28:16  |   rw   |   0x0   | [THD_DAT](#timing3--thd_dat) |
+|  15:9  |        |         | Reserved                     |
+|  8:0   |   rw   |   0x0   | [TSU_DAT](#timing3--tsu_dat) |
+
+### TIMING3 . THD_DAT
+Actual hold time for data (or ack) bits.
+(Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
+This field is sized to have a range that accommodates Standard Mode's 3.45 us max for TVD_DAT with a core clock at 1 GHz.
+However, this field is generally expected to represent a time substantially shorter than that.
+It should be long enough to cover the maximum round-trip latency from output pins, through pads and voltage transitions on the board, and back to the input pins, but it should not be substantially greater.
+
+### TIMING3 . TSU_DAT
+Actual setup time for data (or ack) bits.
+This field is sized to have a range of at least Standard Mode's 250 ns max with a core clock at 1 GHz.
+
+## TIMING4
+Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
+All values are expressed in units of the input clock period.
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x1fff1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TSU_STO", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "T_BUF", "bits": 13, "attr": ["rw"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                                                                                                                                                 |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 31:29  |        |         |         | Reserved                                                                                                                                                                    |
+| 28:16  |   rw   |   0x0   | T_BUF   | Actual time between each STOP signal and the following START signal. This field is sized to have a range of at least Standard Mode's 4.7 us max with a core clock at 1 GHz. |
+| 15:13  |        |         |         | Reserved                                                                                                                                                                    |
+|  12:0  |   rw   |   0x0   | TSU_STO | Actual setup time for stop signals. This field is sized to have a range of at least Standard Mode's 4.0 us max with a core clock at 1 GHz.                                  |
+
+## TIMEOUT_CTRL
+I2C clock stretching and bus timeout control.
+
+This timeout must be enabled by setting [`TIMEOUT_CTRL.EN`](#timeout_ctrl) to 1, and the behavior of this feature depends on the value of [`TIMEOUT_CTRL.MODE.`](#timeout_ctrl)
+
+If the mode is "STRETCH_TIMEOUT", this is used in I2C controller mode to detect whether a connected target is stretching a single low time beyond the timeout value.
+Configured as such, this timeout is more informative and doesn't do more than assert the "stretch_timeout" interrupt.
+
+If the mode is "BUS_TIMEOUT", it is used to detect whether the clock has been held low for too long instead, inclusive of the controller's clock low time.
+This is useful for an SMBus context, where the VAL programmed should be tTIMEOUT:MIN.
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 30, "attr": ["rw"], "rotate": 0}, {"name": "MODE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                        |
+|:------:|:------:|:-------:|:----------------------------|
+|   31   |   rw   |   0x0   | [EN](#timeout_ctrl--en)     |
+|   30   |   rw   |   0x0   | [MODE](#timeout_ctrl--mode) |
+|  29:0  |   rw   |   0x0   | [VAL](#timeout_ctrl--val)   |
+
+### TIMEOUT_CTRL . EN
+Enable stretch timeout or bus timeout feature
+
+### TIMEOUT_CTRL . MODE
+Selects the timeout mode, between a stretch timeout and a bus timeout.
+
+Between the two modes, the primary difference is how much of the clock low period is counted.
+For a stretch timeout, only the time that another device holds the clock low will be counted.
+For a bus timeout, the entire clock low time is counted, consistent with the SMBus tTIMEOUT type.
+
+[`TIMEOUT_CTRL.EN`](#timeout_ctrl) must be 1 for either of these features to be enabled.
+
+| Value   | Name            | Description                                                                                                                                                                                                                                |
+|:--------|:----------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 0x0     | STRETCH_TIMEOUT | The timeout is a target stretch timeout. The counter will track how long the clock has been stretched by another device while the controller is active.                                                                                    |
+| 0x1     | BUS_TIMEOUT     | The timeout is a clock low timeout. The counter will track how long the clock low period is, inclusive of the controller's ordinary low count. A timeout will set !!CONTROLLER_EVENTS.BUS_TIMEOUT and cause a "controller_halt" interrupt. |
+
+
+### TIMEOUT_CTRL . VAL
+Clock stretching timeout value (in units of input clock frequency)
+
+## TARGET_ID
+I2C target address and mask pairs
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0xfffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ADDRESS0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "ADDRESS1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"name": "MASK1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                   |
+|:------:|:------:|:-------:|:---------|:----------------------------------------------------------------------------------------------|
+| 31:28  |        |         |          | Reserved                                                                                      |
+| 27:21  |   rw   |   0x0   | MASK1    | I2C target mask number 1. At least one bit in MASK1 must be set to 1 for ADDRESS1 to be used. |
+| 20:14  |   rw   |   0x0   | ADDRESS1 | I2C target address number 1                                                                   |
+|  13:7  |   rw   |   0x0   | MASK0    | I2C target mask number 0. At least one bit in MASK0 must be set to 1 for ADDRESS0 to be used. |
+|  6:0   |   rw   |   0x0   | ADDRESS0 | I2C target address number 0                                                                   |
+
+## ACQDATA
+I2C target acquired data
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ABYTE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "SIGNAL", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                       |
+|:------:|:------:|:-------:|:---------------------------|
+| 31:11  |        |         | Reserved                   |
+|  10:8  |   ro   |    x    | [SIGNAL](#acqdata--signal) |
+|  7:0   |   ro   |    x    | [ABYTE](#acqdata--abyte)   |
+
+### ACQDATA . SIGNAL
+Indicates any control symbols associated with the ABYTE.
+
+For the STOP symbol, a stretch timeout or other unexpected events will cause a NACK_STOP to appear in the ACQ FIFO.
+If the ACQ FIFO doesn't have enough space to record a START and a STOP, the transaction will be dropped entirely on a stretch timeout.
+In that case, the START byte will not appear (neither as START nor NACK_START), but a standalone NACK_STOP may, if there was space.
+Software can discard any standalone NACK_STOP that appears.
+
+See the associated values for more information about the contents.
+
+| Value   | Name       | Description                                                                                                                                                                                                                                                                                                                                                                                                                                         |
+|:--------|:-----------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 0x0     | NONE       | ABYTE contains an ordinary data byte that was received and ACK'd.                                                                                                                                                                                                                                                                                                                                                                                   |
+| 0x1     | START      | A START condition preceded the ABYTE to start a new transaction. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.                                                                                                                                                                                                                                                                             |
+| 0x2     | STOP       | A STOP condition was received for a transaction including a transfer that addressed this Target. No transfers addressing this Target in that transaction were NACK'd. ABYTE contains no data.                                                                                                                                                                                                                                                       |
+| 0x3     | RESTART    | A repeated START condition preceded the ABYTE, extending the current transaction with a new transfer. ABYTE contains the 7-bit I2C address plus R/W command bit in the order received on the bus, MSB first.                                                                                                                                                                                                                                        |
+| 0x4     | NACK       | ABYTE contains an ordinary data byte that was received and NACK'd.                                                                                                                                                                                                                                                                                                                                                                                  |
+| 0x5     | NACK_START | A START condition preceded the ABYTE (including repeated START) that was part of a NACK'd transfer. The ABYTE contains the matching I2C address and command bit. The ABYTE was ACK'd, but the rest of the transaction was NACK'ed.                                                                                                                                                                                                                  |
+| 0x6     | NACK_STOP  | A transaction including a transfer that addressed this Target was ended, but the transaction ended abnormally and/or the transfer was NACK'd. The end can be due to a STOP condition or unexpected events, such as a bus timeout (if enabled). ABYTE contains no data. NACKing can occur for multiple reasons, including a stretch timeout, a SW-directed NACK, or lost arbitration. This signal is a bucket for all these error-type terminations. |
+
+Other values are reserved.
+
+### ACQDATA . ABYTE
+Address for accepted transaction or acquired byte
+
+## TXDATA
+I2C target transmit data
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   wo   |   0x0   | TXDATA |               |
+
+## HOST_TIMEOUT_CTRL
+I2C host clock generation timeout value (in units of input clock frequency).
+
+In an active transaction in Target-Mode, if the Controller ceases to send SCL pulses
+for this number of cycles then the "host_timeout" interrupt will be asserted.
+
+In multi-controller monitoring mode, [`HOST_TIMEOUT_CTRL`](#host_timeout_ctrl) is required to be nonzero to transition out of the initial busy state.
+Set this CSR to 0 to disable this behaviour.
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0xfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "HOST_TIMEOUT_CTRL", "bits": 20, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+| 31:20  |        |         |                   | Reserved      |
+|  19:0  |   rw   |   0x0   | HOST_TIMEOUT_CTRL |               |
+
+## TARGET_TIMEOUT_CTRL
+I2C target internal stretching timeout control.
+When the target has stretched beyond this time it will send a NACK for incoming data bytes or release SDA for outgoing data bytes.
+The behavior for the address byte is configurable via [`CTRL.ACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+Note that the count accumulates stretching time over the course of a transaction.
+In other words, this is equivalent to the SMBus cumulative target clock extension time.
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EN     | Enable timeout feature and send NACK once the timeout has been reached |
+|  30:0  |   rw   |   0x0   | VAL    | Clock stretching timeout value (in units of input clock frequency)     |
+
+## TARGET_NACK_COUNT
+Number of times the I2C target has NACK'ed a new transaction since the last read of this register.
+Reading this register clears it.
+This is useful because when the ACQ FIFO is full the software know that a NACK has occurred, but without this register would not know how many transactions it missed.
+When it reaches its maximum value it will stay at that value.
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TARGET_NACK_COUNT", "bits": 8, "attr": ["rc"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description   |
+|:------:|:------:|:-------:|:------------------|:--------------|
+|  31:8  |        |         |                   | Reserved      |
+|  7:0   |   rc   |   0x0   | TARGET_NACK_COUNT |               |
+
+## TARGET_ACK_CTRL
+Controls for mid-transfer (N)ACK phase handling
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x800001ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "NBYTES", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 22}, {"name": "NACK", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                               |
+|:------:|:------:|:-------:|:-----------------------------------|
+|   31   |   wo   |    x    | [NACK](#target_ack_ctrl--nack)     |
+|  30:9  |        |         | Reserved                           |
+|  8:0   |   rw   |    x    | [NBYTES](#target_ack_ctrl--nbytes) |
+
+### TARGET_ACK_CTRL . NACK
+When the Target module stretches on the (N)ACK phase of a Write due to [`TARGET_ACK_CTRL.NBYTES`](#target_ack_ctrl) being 0, writing a 1 here will cause it to send a NACK.
+
+If software chooses to NACK, note that the NACKing behavior is the same as if a stretch timeout occurred.
+The rest of the transaction will be NACK'd, including subsequent transfers.
+For the address byte, the (N)ACK phase of subsequent transfers will follow the behavior specified by [`CTRL.NACK_ADDR_AFTER_TIMEOUT.`](#ctrl)
+
+Automatically clears to 0.
+
+### TARGET_ACK_CTRL . NBYTES
+Remaining number of bytes the Target module may ACK automatically.
+
+If [`CTRL.ACK_CTRL_EN`](#ctrl) is set to 1, the Target module will stretch the clock at the (N)ACK phase of a byte if this CSR is 0, awaiting software's instructions.
+
+At the beginning of each Write transfer, this byte count is reset to 0.
+Writes to this CSR also are only accepted while the Target module is stretching the clock.
+The Target module will always ACK its address if the ACQ FIFO has space.
+For data bytes afterwards, it will stop at the (N)ACK phase and stretch the clock when this CSR is 0.
+For each data byte that is ACK'd in a transaction, the byte count will decrease by 1.
+
+Note that a full ACQ FIFO can still cause the Target module to halt at the beginning of a new byte.
+The ACK Control Mode provides an additional synchronization point, during the (N)ACK phase instead of after.
+For both cases, [`TARGET_TIMEOUT_CTRL`](#target_timeout_ctrl) applies, and stretching past the timeout will produce an automatic NACK.
+
+This mode can be used to implement the mid-transfer (N)ACK responses required by various SMBus protocols.
+
+## ACQ_FIFO_NEXT_DATA
+The data byte pending to be written to the ACQ FIFO.
+
+This CSR is only valid while the Target module is stretching in the (N)ACK phase, indicated by [`STATUS.ACK_CTRL_STRETCH`](#status) .
+It is intended to be used with ACK Control Mode, so software may check the current byte.
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "ACQ_FIFO_NEXT_DATA", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:8  |        |         |                    | Reserved      |
+|  7:0   |   ro   |    x    | ACQ_FIFO_NEXT_DATA |               |
+
+## HOST_NACK_HANDLER_TIMEOUT
+Timeout in Host-Mode for an unhandled NACK before hardware automatically ends the transaction.
+(in units of input clock frequency)
+
+If an active Controller-Transmitter transfer receives a NACK from the Target, the [`CONTROLLER_EVENTS.NACK`](#controller_events) bit is set.
+In turn, this causes the Controller FSM to halt awaiting software intervention, and the 'controller_halt' interrupt may assert.
+Software must clear the [`CONTROLLER_EVENTS.NACK`](#controller_events) bit to allow the state machine to continue, typically after clearing out the FMTFIFO to start a new transfer.
+While halted, the active transaction is not ended (no STOP (P) condition is created), and the block asserts SCL and leaves SDA released.
+
+This timeout can be used to automatically produce a STOP condition, whether as a backstop for slow software responses (longer timeout) or as a convenience (short timeout).
+If the timeout expires, the Controller FSM will issue a STOP (P) condition on the bus to end the active transaction.
+Additionally, the [`CONTROLLER_EVENTS.UNHANDLED_NACK_TIMEOUT`](#controller_events) bit is set to alert software, and the FSM will return to the idle state and halt until the bit is cleared.
+
+The enable bit must be set for this feature to operate.
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 31, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                     |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------|
+|   31   |   rw   |   0x0   | EN     | Timeout enable                                                  |
+|  30:0  |   rw   |   0x0   | VAL    | Unhandled NAK timeout value (in units of input clock frequency) |
+
+## CONTROLLER_EVENTS
+Latched events that explain why the controller halted.
+
+Any bits that are set must be written (with a 1) to clear the CONTROLLER_HALT interrupt.
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0xf`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "NACK", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNHANDLED_NACK_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                                                                                               |
+|:------:|:------:|:-------:|:-----------------------|:--------------------------------------------------------------------------------------------------------------------------|
+|  31:4  |        |         |                        | Reserved                                                                                                                  |
+|   3    |  rw1c  |   0x0   | ARBITRATION_LOST       | A Host-Mode active transaction has terminated due to lost arbitration.                                                    |
+|   2    |  rw1c  |   0x0   | BUS_TIMEOUT            | A Host-Mode active transaction has terminated due to a bus timeout activated by [`TIMEOUT_CTRL.`](#timeout_ctrl)          |
+|   1    |  rw1c  |   0x0   | UNHANDLED_NACK_TIMEOUT | A Host-Mode active transaction has been ended by the [`HOST_NACK_HANDLER_TIMEOUT`](#host_nack_handler_timeout) mechanism. |
+|   0    |  rw1c  |   0x0   | NACK                   | Received an unexpected NACK                                                                                               |
+
+## TARGET_EVENTS
+Latched events that can cause the target module to stretch the clock at the beginning of a read transfer.
+
+These events cause TX FIFO-related stretching even when the TX FIFO has data available.
+Any bits that are set must be written (with a 1) to clear the tx_stretch interrupt.
+
+This CSR serves as a gate to prevent the Target module from responding to a read command with unrelated, leftover data.
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX_PENDING", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "BUS_TIMEOUT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ARBITRATION_LOST", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                 |
+|:------:|:------:|:-------:|:-----------------------------------------------------|
+|  31:3  |        |         | Reserved                                             |
+|   2    |  rw1c  |   0x0   | [ARBITRATION_LOST](#target_events--arbitration_lost) |
+|   1    |  rw1c  |   0x0   | [BUS_TIMEOUT](#target_events--bus_timeout)           |
+|   0    |  rw1c  |   0x0   | [TX_PENDING](#target_events--tx_pending)             |
+
+### TARGET_EVENTS . ARBITRATION_LOST
+A Target-Mode read transfer has terminated due to lost arbitration.
+
+### TARGET_EVENTS . BUS_TIMEOUT
+A Target-Mode read transfer has terminated due to a bus timeout activated by [`TIMEOUT_CTRL.`](#timeout_ctrl)
+
+### TARGET_EVENTS . TX_PENDING
+A new Target-Mode read transfer has arrived that addressed this target.
+
+This bit is used by software to confirm the release of the contents in the TX FIFO.
+If the contents do not apply, software should first reset the TX FIFO, then load it with the correct data, then clear this bit.
+
+Optionally enabled by [`CTRL.TX_STRETCH_CTRL_EN.`](#ctrl)
+
diff --git a/docs/um/ip/integer_cluster/doc/pulp_cluster_peripherals_memory_map.md b/docs/um/ip/integer_cluster/doc/pulp_cluster_peripherals_memory_map.md
new file mode 100644
index 00000000..647cda18
--- /dev/null
+++ b/docs/um/ip/integer_cluster/doc/pulp_cluster_peripherals_memory_map.md
@@ -0,0 +1,40 @@
+## PULP Cluster Peripheral Memory Map
+
+This document describes the memory-mapped peripheral devices accessible from the PULP cluster through the peripheral interconnect slave port.
+
+## Base Address
+
+- **Cluster Base Address**: `0x5000_0000`
+- **Peripheral Offset**: `0x0020_0000`
+- **External Offset**: `0x0040_0000`
+
+**Cluster Peripheral Base Address**:  
+`0x5020_0000` – `0x5040_0000` (2 MiB region)
+
+---
+
+## Peripheral Layout
+
+| Peripheral           | ID   | Offset (from Peripheral Base) | Address Range                  |
+|----------------------|------|-------------------------------|--------------------------------|
+| EOC                  | 0    | `0x0000`                      | `0x5020_0000` – `0x5020_03FF`  |
+| Timer                | 1    | `0x0400`                      | `0x5020_0400` – `0x5020_07FF`  |
+| Event Unit (also 3)  | 2/3  | `0x0800`                      | `0x5020_0800` – `0x5020_0FFF`  |
+| HWPE                 | 4    | `0x1000`                      | `0x5020_1000` – `0x5020_13FF`  |
+| ICache Controller    | 5    | `0x1400`                      | `0x5020_1400` – `0x5020_17FF`  |
+| DMA (Cluster)        | 6    | `0x1800`                      | `0x5020_1800` – `0x5020_1BFF`  |
+| DMA (Fabric Ctrl)    | 7    | `0x1C00`                      | `0x5020_1C00` – `0x5020_1FFF`  |
+| HMR Unit             | 8    | `0x2000`                      | `0x5020_2000` – `0x5020_23FF`  |
+| External             | 9    | `0x2400`                      | `0x5020_2400` – `0x5020_27FF`  |
+| Error Unit           | 10   | `0x2800`                      | `0x5020_2800` – `0x5020_2BFF`  |
+
+---
+
+## Address Mapping Summary
+
+| Region           | Index | Start Address | End Address   | Notes                          |
+|------------------|--------|----------------|---------------|--------------------------------|
+| TCDM             | 0      | `0x5000_0000`   | `0x5000_0000 + TCDM_SIZE` | Tightly Coupled Data Memory    |
+| Peripherals      | 1      | `0x5020_0000`   | `0x5040_0000` | Cluster Peripheral Region      |
+| External         | 2      | `0x5040_0000`   | `0xFFFF_FFFF` | Access beyond cluster          |
+| Below Cluster    | 3      | `0x0000_0000`   | `0x5000_0000` | Not cluster-related            |
diff --git a/docs/um/ip/irq_router/data/irq_router_regs.hjson b/docs/um/ip/irq_router/data/irq_router_regs.hjson
new file mode 100644
index 00000000..941261c7
--- /dev/null
+++ b/docs/um/ip/irq_router/data/irq_router_regs.hjson
@@ -0,0 +1,32 @@
+// Copyright lowRISC contributors.
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Alessandro Ottaviano <aottaviano@iis.ee.ethz.ch.it>
+
+// Register layout for one interrupt line
+
+{
+  name: "irq_router",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device"}
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "IRQ_TARGET_MASK",
+      desc: "Target selection bitmask control register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+	{ bits: "31:0",
+	  resval: 1,
+	  name: "mask",
+	  desc: "Target selection bitmask control register for single interrupt line. Reflects interrupt line logic level."
+	}
+      ],
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/irq_router/data/irq_router_regs_doc.hjson b/docs/um/ip/irq_router/data/irq_router_regs_doc.hjson
new file mode 100644
index 00000000..c0698f23
--- /dev/null
+++ b/docs/um/ip/irq_router/data/irq_router_regs_doc.hjson
@@ -0,0 +1,36 @@
+// Copyright lowRISC contributors.
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Alessandro Ottaviano <aottaviano@iis.ee.ethz.ch.it>
+
+// Register layout for one interrupt line
+
+{
+  name: "irq_router",
+  cip_id: "36",
+  version: "0.0.1-beta.1",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device"}
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "IRQ_TARGET_MASK",
+      desc: "Target selection bitmask control register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+	{ bits: "31:0",
+	  resval: 1,
+	  name: "mask",
+	  desc: "Target selection bitmask control register for single interrupt line. Reflects interrupt line logic level."
+	}
+      ],
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/irq_router/doc/registers.md b/docs/um/ip/irq_router/doc/registers.md
new file mode 100644
index 00000000..fe02b1f6
--- /dev/null
+++ b/docs/um/ip/irq_router/doc/registers.md
@@ -0,0 +1,22 @@
+## Summary
+
+| Name                                             | Offset   |   Length | Description                               |
+|:-------------------------------------------------|:---------|---------:|:------------------------------------------|
+| irq_router.[`IRQ_TARGET_MASK`](#irq_target_mask) | 0x0      |        4 | Target selection bitmask control register |
+
+## IRQ_TARGET_MASK
+Target selection bitmask control register
+- Offset: `0x0`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "mask", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                                               |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x1   | mask   | Target selection bitmask control register for single interrupt line. Reflects interrupt line logic level. |
+
diff --git a/docs/um/ip/l2_ecc_config/data/ecc_sram_wrapper.hjson b/docs/um/ip/l2_ecc_config/data/ecc_sram_wrapper.hjson
new file mode 100644
index 00000000..412bda5d
--- /dev/null
+++ b/docs/um/ip/l2_ecc_config/data/ecc_sram_wrapper.hjson
@@ -0,0 +1,86 @@
+{
+  name: "ECC_manager",
+  clock_primary: "clk_i",
+  reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+
+  registers: [
+    { name: "mismatch_count",
+      desc: "Correctable mismatches caught by ecc on access",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on access"
+        }
+      ]
+    },
+    { name: "scrub_interval",
+      desc: "Interval between scrubs",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0"
+          name: "scrub_interval"
+          desc: "Interval between scrubs"
+        }
+      ]
+    },
+    { name: "scrub_fix_count",
+      desc: "Correctable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "scrub_uncorrectable_count",
+      desc: "Uncorrectable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "uncorrectable_mismatches",
+          desc: "Uncorrectable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "write_mask_data_n",
+      desc: "Testing: Inverted write mask for data bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "write_mask_data_n",
+          desc: "Testing: Inverted write mask for data bits"
+        }
+      ]
+    },
+    { name: "write_mask_ecc_n",
+      desc: "Testing: Inverted write mask for ECC bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "6:0",
+          name: "write_mask_ecc_n",
+          desc: "Testing: Inverted write mask for ECC bits"
+        }
+      ]
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/l2_ecc_config/data/ecc_sram_wrapper_doc.hjson b/docs/um/ip/l2_ecc_config/data/ecc_sram_wrapper_doc.hjson
new file mode 100644
index 00000000..7a2db8a3
--- /dev/null
+++ b/docs/um/ip/l2_ecc_config/data/ecc_sram_wrapper_doc.hjson
@@ -0,0 +1,94 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Author: Michael Rogenmoser <michaero@iis.ee.ethz.ch>
+
+{
+  name: "ECC_manager",
+  cip_id: "36",
+  version: "0.0.0", // null, commit 5616a36
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "mismatch_count",
+      desc: "Correctable mismatches caught by ecc on access",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on access"
+        }
+      ]
+    },
+    { name: "scrub_interval",
+      desc: "Interval between scrubs",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0"
+          name: "scrub_interval"
+          desc: "Interval between scrubs"
+        }
+      ]
+    },
+    { name: "scrub_fix_count",
+      desc: "Correctable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "correctable_mismatches",
+          desc: "Correctable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "scrub_uncorrectable_count",
+      desc: "Uncorrectable mismatches caught by ecc on scrub",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "uncorrectable_mismatches",
+          desc: "Uncorrectable mismatches caught by ecc on scrub"
+        }
+      ]
+    },
+    { name: "write_mask_data_n",
+      desc: "Testing: Inverted write mask for data bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "31:0",
+          name: "write_mask_data_n",
+          desc: "Testing: Inverted write mask for data bits"
+        }
+      ]
+    },
+    { name: "write_mask_ecc_n",
+      desc: "Testing: Inverted write mask for ECC bits",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "6:0",
+          name: "write_mask_ecc_n",
+          desc: "Testing: Inverted write mask for ECC bits"
+        }
+      ]
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/l2_ecc_config/doc/registers.md b/docs/um/ip/l2_ecc_config/doc/registers.md
new file mode 100644
index 00000000..6a6d27df
--- /dev/null
+++ b/docs/um/ip/l2_ecc_config/doc/registers.md
@@ -0,0 +1,108 @@
+## Summary
+
+| Name                                                                  | Offset   |   Length | Description                                     |
+|:----------------------------------------------------------------------|:---------|---------:|:------------------------------------------------|
+| ECC_manager.[`mismatch_count`](#mismatch_count)                       | 0x0      |        4 | Correctable mismatches caught by ecc on access  |
+| ECC_manager.[`scrub_interval`](#scrub_interval)                       | 0x4      |        4 | Interval between scrubs                         |
+| ECC_manager.[`scrub_fix_count`](#scrub_fix_count)                     | 0x8      |        4 | Correctable mismatches caught by ecc on scrub   |
+| ECC_manager.[`scrub_uncorrectable_count`](#scrub_uncorrectable_count) | 0xc      |        4 | Uncorrectable mismatches caught by ecc on scrub |
+| ECC_manager.[`write_mask_data_n`](#write_mask_data_n)                 | 0x10     |        4 | Testing: Inverted write mask for data bits      |
+| ECC_manager.[`write_mask_ecc_n`](#write_mask_ecc_n)                   | 0x14     |        4 | Testing: Inverted write mask for ECC bits       |
+
+## mismatch_count
+Correctable mismatches caught by ecc on access
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                    |
+|:------:|:------:|:-------:|:-----------------------|:-----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on access |
+
+## scrub_interval
+Interval between scrubs
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "scrub_interval", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description             |
+|:------:|:------:|:-------:|:---------------|:------------------------|
+|  31:0  |   rw   |   0x0   | scrub_interval | Interval between scrubs |
+
+## scrub_fix_count
+Correctable mismatches caught by ecc on scrub
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "correctable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description                                   |
+|:------:|:------:|:-------:|:-----------------------|:----------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | correctable_mismatches | Correctable mismatches caught by ecc on scrub |
+
+## scrub_uncorrectable_count
+Uncorrectable mismatches caught by ecc on scrub
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "uncorrectable_mismatches", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                     | Description                                     |
+|:------:|:------:|:-------:|:-------------------------|:------------------------------------------------|
+|  31:0  |  rw0c  |   0x0   | uncorrectable_mismatches | Uncorrectable mismatches caught by ecc on scrub |
+
+## write_mask_data_n
+Testing: Inverted write mask for data bits
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_data_n", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                                |
+|:------:|:------:|:-------:|:------------------|:-------------------------------------------|
+|  31:0  |   rw   |   0x0   | write_mask_data_n | Testing: Inverted write mask for data bits |
+
+## write_mask_ecc_n
+Testing: Inverted write mask for ECC bits
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "write_mask_ecc_n", "bits": 7, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                               |
+|:------:|:------:|:-------:|:-----------------|:------------------------------------------|
+|  31:7  |        |         |                  | Reserved                                  |
+|  6:0   |   rw   |   0x0   | write_mask_ecc_n | Testing: Inverted write mask for ECC bits |
+
diff --git a/docs/um/ip/mailbox/data/mailbox.hjson b/docs/um/ip/mailbox/data/mailbox.hjson
new file mode 100644
index 00000000..34c9db63
--- /dev/null
+++ b/docs/um/ip/mailbox/data/mailbox.hjson
@@ -0,0 +1,146 @@
+// Copyright lowRISC contributors.
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Maicol Ciani <maicol.ciani@unibo.it>
+// Robert Balas <balasr@iis.ee.ethz.ch>
+
+// Register layout of one mailbox
+
+{
+  name: "mailbox",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device"}
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "IRQ_SND_STAT",
+      desc: "Sender interrupt status register",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "stat",
+          desc: "Sender side interrupt status. Receiver confirms letter. Reflects interrupt line logic level."
+        }
+      ],
+    },
+    { name: "IRQ_SND_SET",
+      desc: "Sender interrupt set register",
+      swaccess: "wo",  // w1s
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "set",
+          desc: "Sender side interrupt set. Receiver confirms letter."
+        }
+      ],
+    },
+    { name: "IRQ_SND_CLR",
+      desc: "Sender interrupt clear register",
+      swaccess: "wo",  // w1c
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "clr",
+          desc: "Sender side interrupt clear. Receiver confirms letter."
+        }
+      ],
+    },
+    { name: "IRQ_SND_EN",
+      desc: "Sender interrupt enable register",
+      swaccess: "rw",  // rw
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "en",
+          desc: "Sender side interrupt enable. Receiver confirms letter."
+        }
+      ],
+    },
+    { reserved: "12" },
+    { name: "IRQ_RCV_STAT",
+      desc: "Receiver interrupt status register",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "stat",
+          desc: "Receiver side interrupt status. Sender notifies receiver of a new letter arriving. Reflects interrupt line logic level."
+        }
+      ],
+    },
+    { name: "IRQ_RCV_SET",
+      desc: "Receiver interrupt set register",
+      swaccess: "wo",  // w1s
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "set",
+          desc: "Receiver side interrupt set. Sender notifies receiver of a new letter arriving."
+        }
+      ],
+    },
+
+    { name: "IRQ_RCV_CLR",
+      desc: "Receiver interrupt clear register",
+      swaccess: "wo",  // w1c
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "clr",
+          desc: "Receiver side interrupt clear. Sender notifies receiver of a new letter arriving."
+        }
+      ],
+    },
+    { name: "IRQ_RCV_EN",
+      desc: "Receiver interrupt enable register",
+      swaccess: "rw",  // rw
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "en",
+          desc: "Receiver side interrupt enable. Sender notifies receiver of a new letter arriving."
+        }
+      ],
+    },
+    { reserved: "12" },
+    { name: "LETTER0",
+      desc: "Memory region 0 to put a message or pointer",
+      swaccess: "rw",
+      hwaccess: "none",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "LETTER1",
+      desc: "Memory region 1 to put a message or pointer",
+      swaccess: "rw",
+      hwaccess: "none",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/mailbox/data/mailbox_doc.hjson b/docs/um/ip/mailbox/data/mailbox_doc.hjson
new file mode 100644
index 00000000..0e62d20e
--- /dev/null
+++ b/docs/um/ip/mailbox/data/mailbox_doc.hjson
@@ -0,0 +1,150 @@
+// Copyright lowRISC contributors.
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Maicol Ciani <maicol.ciani@unibo.it>
+// Robert Balas <balasr@iis.ee.ethz.ch>
+
+// Register layout of one mailbox
+
+{
+  name: "mailbox",
+  cip_id: "36",
+  version: "1.1.0",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device"}
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "IRQ_SND_STAT",
+      desc: "Sender interrupt status register",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "stat",
+          desc: "Sender side interrupt status. Receiver confirms letter. Reflects interrupt line logic level."
+        }
+      ],
+    },
+    { name: "IRQ_SND_SET",
+      desc: "Sender interrupt set register",
+      swaccess: "wo",  // w1s
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "set",
+          desc: "Sender side interrupt set. Receiver confirms letter."
+        }
+      ],
+    },
+    { name: "IRQ_SND_CLR",
+      desc: "Sender interrupt clear register",
+      swaccess: "wo",  // w1c
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "clr",
+          desc: "Sender side interrupt clear. Receiver confirms letter."
+        }
+      ],
+    },
+    { name: "IRQ_SND_EN",
+      desc: "Sender interrupt enable register",
+      swaccess: "rw",  // rw
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "en",
+          desc: "Sender side interrupt enable. Receiver confirms letter."
+        }
+      ],
+    },
+    { reserved: "12" },
+    { name: "IRQ_RCV_STAT",
+      desc: "Receiver interrupt status register",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "stat",
+          desc: "Receiver side interrupt status. Sender notifies receiver of a new letter arriving. Reflects interrupt line logic level."
+        }
+      ],
+    },
+    { name: "IRQ_RCV_SET",
+      desc: "Receiver interrupt set register",
+      swaccess: "wo",  // w1s
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "set",
+          desc: "Receiver side interrupt set. Sender notifies receiver of a new letter arriving."
+        }
+      ],
+    },
+
+    { name: "IRQ_RCV_CLR",
+      desc: "Receiver interrupt clear register",
+      swaccess: "wo",  // w1c
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "clr",
+          desc: "Receiver side interrupt clear. Sender notifies receiver of a new letter arriving."
+        }
+      ],
+    },
+    { name: "IRQ_RCV_EN",
+      desc: "Receiver interrupt enable register",
+      swaccess: "rw",  // rw
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:1", name: "reserved", desc: "reserved", swaccess: "ro", hwaccess: "none"},
+        { bits: "0",
+          name: "en",
+          desc: "Receiver side interrupt enable. Sender notifies receiver of a new letter arriving."
+        }
+      ],
+    },
+    { reserved: "12" },
+    { name: "LETTER0",
+      desc: "Memory region 0 to put a message or pointer",
+      swaccess: "rw",
+      hwaccess: "none",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+    { name: "LETTER1",
+      desc: "Memory region 1 to put a message or pointer",
+      swaccess: "rw",
+      hwaccess: "none",
+      fields: [
+        { bits: "31:0" }
+      ],
+    },
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/mailbox/doc/registers.md b/docs/um/ip/mailbox/doc/registers.md
new file mode 100644
index 00000000..b253eb73
--- /dev/null
+++ b/docs/um/ip/mailbox/doc/registers.md
@@ -0,0 +1,183 @@
+## Summary
+
+| Name                                    | Offset   |   Length | Description                                 |
+|:----------------------------------------|:---------|---------:|:--------------------------------------------|
+| mailbox.[`IRQ_SND_STAT`](#irq_snd_stat) | 0x0      |        4 | Sender interrupt status register            |
+| mailbox.[`IRQ_SND_SET`](#irq_snd_set)   | 0x4      |        4 | Sender interrupt set register               |
+| mailbox.[`IRQ_SND_CLR`](#irq_snd_clr)   | 0x8      |        4 | Sender interrupt clear register             |
+| mailbox.[`IRQ_SND_EN`](#irq_snd_en)     | 0xc      |        4 | Sender interrupt enable register            |
+| mailbox.[`IRQ_RCV_STAT`](#irq_rcv_stat) | 0x40     |        4 | Receiver interrupt status register          |
+| mailbox.[`IRQ_RCV_SET`](#irq_rcv_set)   | 0x44     |        4 | Receiver interrupt set register             |
+| mailbox.[`IRQ_RCV_CLR`](#irq_rcv_clr)   | 0x48     |        4 | Receiver interrupt clear register           |
+| mailbox.[`IRQ_RCV_EN`](#irq_rcv_en)     | 0x4c     |        4 | Receiver interrupt enable register          |
+| mailbox.[`LETTER0`](#letter0)           | 0x80     |        4 | Memory region 0 to put a message or pointer |
+| mailbox.[`LETTER1`](#letter1)           | 0x84     |        4 | Memory region 1 to put a message or pointer |
+
+## IRQ_SND_STAT
+Sender interrupt status register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stat", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                  |
+|:------:|:------:|:-------:|:---------|:---------------------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                                     |
+|   0    |   ro   |    x    | stat     | Sender side interrupt status. Receiver confirms letter. Reflects interrupt line logic level. |
+
+## IRQ_SND_SET
+Sender interrupt set register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "set", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                          |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                             |
+|   0    |   wo   |    x    | set      | Sender side interrupt set. Receiver confirms letter. |
+
+## IRQ_SND_CLR
+Sender interrupt clear register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clr", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                            |
+|:------:|:------:|:-------:|:---------|:-------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                               |
+|   0    |   wo   |    x    | clr      | Sender side interrupt clear. Receiver confirms letter. |
+
+## IRQ_SND_EN
+Sender interrupt enable register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                             |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------|
+|  31:1  |   ro   |   0x0   | reserved | reserved                                                |
+|   0    |   rw   |   0x0   | en       | Sender side interrupt enable. Receiver confirms letter. |
+
+## IRQ_RCV_STAT
+Receiver interrupt status register
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "stat", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                                                             |
+|:------:|:------:|:-------:|:---------|:------------------------------------------------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                                                                |
+|   0    |   ro   |    x    | stat     | Receiver side interrupt status. Sender notifies receiver of a new letter arriving. Reflects interrupt line logic level. |
+
+## IRQ_RCV_SET
+Receiver interrupt set register
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "set", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                     |
+|:------:|:------:|:-------:|:---------|:--------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                        |
+|   0    |   wo   |    x    | set      | Receiver side interrupt set. Sender notifies receiver of a new letter arriving. |
+
+## IRQ_RCV_CLR
+Receiver interrupt clear register
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clr", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------------------------------------------------------|
+|  31:1  |   ro   |    x    | reserved | reserved                                                                          |
+|   0    |   wo   |    x    | clr      | Receiver side interrupt clear. Sender notifies receiver of a new letter arriving. |
+
+## IRQ_RCV_EN
+Receiver interrupt enable register
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reserved", "bits": 31, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                                                                        |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------------------------------------------------|
+|  31:1  |   ro   |   0x0   | reserved | reserved                                                                           |
+|   0    |   rw   |   0x0   | en       | Receiver side interrupt enable. Sender notifies receiver of a new letter arriving. |
+
+## LETTER0
+Memory region 0 to put a message or pointer
+- Offset: `0x80`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LETTER0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   rw   |   0x0   | LETTER0 |               |
+
+## LETTER1
+Memory region 1 to put a message or pointer
+- Offset: `0x84`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "LETTER1", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:0  |   rw   |   0x0   | LETTER1 |               |
+
diff --git a/docs/um/ip/plic/data/plic.hjson b/docs/um/ip/plic/data/plic.hjson
new file mode 100644
index 00000000..a9576646
--- /dev/null
+++ b/docs/um/ip/plic/data/plic.hjson
@@ -0,0 +1,412 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# RV_PLIC register template
+#
+# Parameter (given by Python tool)
+#  - src:    Number of Interrupt Sources
+#  - target: Number of Targets that handle interrupt requests
+#  - prio:   Max value of interrupt priorities
+#  - module_instance_name: Module instance name.
+{
+  name: "rv_plic",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+
+  param_list: [
+    { name: "NumSrc",
+      desc: "Number of interrupt sources",
+      type: "int",
+      default: "32",
+      local: "true"
+    },
+    { name: "NumTarget",
+      desc: "Number of Targets (Harts)",
+      type: "int",
+      default: "1",
+      local: "true",
+    },
+    { name: "PrioWidth",
+      desc: "Width of priority signals",
+      type: "int",
+      default: "3",
+      local: "true",
+    },
+  ],
+
+  // In order to not disturb the PLIC address map, we place the alert test
+  // register manually at a safe offset after the main CSRs.
+  no_auto_alert_regs: "True",
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+
+  inter_signal_list: [
+    { struct:  "logic",
+      type:    "uni",
+      name:    "irq",
+      act:     "req",
+      package: "",
+      width:   "1"
+    },
+
+    { struct:  "logic",
+      type:    "uni",
+      name:    "irq_id",
+      act:     "req",
+      package: "",
+    },
+
+    { struct:  "logic",
+      type:    "uni",
+      name:    "msip",
+      act:     "req",
+      package: "",
+      width:   "1"
+    },
+  ]
+
+  regwidth: "32",
+  registers: [
+    { name: "PRIO0",
+      desc: "Interrupt Source 0 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO1",
+      desc: "Interrupt Source 1 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO2",
+      desc: "Interrupt Source 2 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO3",
+      desc: "Interrupt Source 3 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO4",
+      desc: "Interrupt Source 4 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO5",
+      desc: "Interrupt Source 5 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO6",
+      desc: "Interrupt Source 6 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO7",
+      desc: "Interrupt Source 7 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO8",
+      desc: "Interrupt Source 8 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO9",
+      desc: "Interrupt Source 9 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO10",
+      desc: "Interrupt Source 10 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO11",
+      desc: "Interrupt Source 11 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO12",
+      desc: "Interrupt Source 12 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO13",
+      desc: "Interrupt Source 13 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO14",
+      desc: "Interrupt Source 14 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO15",
+      desc: "Interrupt Source 15 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO16",
+      desc: "Interrupt Source 16 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO17",
+      desc: "Interrupt Source 17 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO18",
+      desc: "Interrupt Source 18 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO19",
+      desc: "Interrupt Source 19 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO20",
+      desc: "Interrupt Source 20 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO21",
+      desc: "Interrupt Source 21 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO22",
+      desc: "Interrupt Source 22 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO23",
+      desc: "Interrupt Source 23 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO24",
+      desc: "Interrupt Source 24 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO25",
+      desc: "Interrupt Source 25 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO26",
+      desc: "Interrupt Source 26 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO27",
+      desc: "Interrupt Source 27 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO28",
+      desc: "Interrupt Source 28 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO29",
+      desc: "Interrupt Source 29 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO30",
+      desc: "Interrupt Source 30 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO31",
+      desc: "Interrupt Source 31 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { skipto: "0x00001000" }
+    { multireg: {
+        name: "IP",
+        desc: "Interrupt Pending",
+        count: "NumSrc",
+        cname: "RV_PLIC",
+        swaccess: "ro",
+        hwaccess: "hwo",
+        fields: [
+          { bits: "0", name: "P", desc: "Interrupt Pending of Source" }
+        ],
+        tags: [// IP is driven by intr_src, cannot auto-predict
+               "excl:CsrNonInitTests:CsrExclCheck"],
+      }
+    },
+    { skipto: "0x2000" }
+    { multireg: {
+        name: "IE0",
+        desc: "Interrupt Enable for Target 0",
+        count: "NumSrc",
+        cname: "RV_PLIC",
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "0", name: "E", desc: "Interrupt Enable of Source" }
+        ],
+      }
+    }
+    { skipto: "0x200000" }
+    { name: "THRESHOLD0",
+      desc: "Threshold of priority for Target 0",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "CC0",
+      desc: '''Claim interrupt by read, complete interrupt by write for Target 0.
+      Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      hwre: "true",
+      fields: [
+        { bits: "4:0" }
+      ],
+      tags: [// CC register value is related to IP
+             "excl:CsrNonInitTests:CsrExclCheck"],
+    }
+  { skipto: "0x4000000" }
+    { name: "MSIP0",
+      desc: '''msip for Hart 0.
+      Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          desc: "Software Interrupt Pending register",
+        }
+      ],
+    }
+  { skipto: "0x4004000" }
+  { name: "ALERT_TEST",
+      desc: '''Alert Test Register.''',
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe:     "True",
+      hwext:    "True",
+      fields: [
+        { bits: "0",
+          name: "fatal_fault",
+          desc: "'Write 1 to trigger one alert event of this kind.'",
+        }
+      ],
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/plic/data/plic_doc.hjson b/docs/um/ip/plic/data/plic_doc.hjson
new file mode 100644
index 00000000..e8a632e0
--- /dev/null
+++ b/docs/um/ip/plic/data/plic_doc.hjson
@@ -0,0 +1,416 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# RV_PLIC register template
+#
+# Parameter (given by Python tool)
+#  - src:    Number of Interrupt Sources
+#  - target: Number of Targets that handle interrupt requests
+#  - prio:   Max value of interrupt priorities
+#  - module_instance_name: Module instance name.
+{
+  name: "rv_plic",
+  cip_id: "36",
+  version: "0.0.0", //used in opentitan_peripherals from pulp platform
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+
+  param_list: [
+    { name: "NumSrc",
+      desc: "Number of interrupt sources",
+      type: "int",
+      default: "32",
+      local: "true"
+    },
+    { name: "NumTarget",
+      desc: "Number of Targets (Harts)",
+      type: "int",
+      default: "1",
+      local: "true",
+    },
+    { name: "PrioWidth",
+      desc: "Width of priority signals",
+      type: "int",
+      default: "3",
+      local: "true",
+    },
+  ],
+
+  // In order to not disturb the PLIC address map, we place the alert test
+  // register manually at a safe offset after the main CSRs.
+  no_auto_alert_regs: "True",
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+
+  inter_signal_list: [
+    { struct:  "logic",
+      type:    "uni",
+      name:    "irq",
+      act:     "req",
+      package: "",
+      width:   "1"
+    },
+
+    { struct:  "logic",
+      type:    "uni",
+      name:    "irq_id",
+      act:     "req",
+      package: "",
+    },
+
+    { struct:  "logic",
+      type:    "uni",
+      name:    "msip",
+      act:     "req",
+      package: "",
+      width:   "1"
+    },
+  ]
+
+  regwidth: "32",
+  registers: [
+    { name: "PRIO0",
+      desc: "Interrupt Source 0 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO1",
+      desc: "Interrupt Source 1 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO2",
+      desc: "Interrupt Source 2 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO3",
+      desc: "Interrupt Source 3 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO4",
+      desc: "Interrupt Source 4 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO5",
+      desc: "Interrupt Source 5 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO6",
+      desc: "Interrupt Source 6 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO7",
+      desc: "Interrupt Source 7 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO8",
+      desc: "Interrupt Source 8 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO9",
+      desc: "Interrupt Source 9 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO10",
+      desc: "Interrupt Source 10 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO11",
+      desc: "Interrupt Source 11 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO12",
+      desc: "Interrupt Source 12 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO13",
+      desc: "Interrupt Source 13 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO14",
+      desc: "Interrupt Source 14 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO15",
+      desc: "Interrupt Source 15 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO16",
+      desc: "Interrupt Source 16 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO17",
+      desc: "Interrupt Source 17 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO18",
+      desc: "Interrupt Source 18 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO19",
+      desc: "Interrupt Source 19 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO20",
+      desc: "Interrupt Source 20 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO21",
+      desc: "Interrupt Source 21 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO22",
+      desc: "Interrupt Source 22 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO23",
+      desc: "Interrupt Source 23 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO24",
+      desc: "Interrupt Source 24 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO25",
+      desc: "Interrupt Source 25 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO26",
+      desc: "Interrupt Source 26 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO27",
+      desc: "Interrupt Source 27 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO28",
+      desc: "Interrupt Source 28 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO29",
+      desc: "Interrupt Source 29 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO30",
+      desc: "Interrupt Source 30 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "PRIO31",
+      desc: "Interrupt Source 31 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { skipto: "0x00001000" }
+    { multireg: {
+        name: "IP",
+        desc: "Interrupt Pending",
+        count: "NumSrc",
+        cname: "RV_PLIC",
+        swaccess: "ro",
+        hwaccess: "hwo",
+        fields: [
+          { bits: "0", name: "P", desc: "Interrupt Pending of Source" }
+        ],
+        tags: [// IP is driven by intr_src, cannot auto-predict
+               "excl:CsrNonInitTests:CsrExclCheck"],
+      }
+    },
+    { skipto: "0x2000" }
+    { multireg: {
+        name: "IE0",
+        desc: "Interrupt Enable for Target 0",
+        count: "NumSrc",
+        cname: "RV_PLIC",
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "0", name: "E", desc: "Interrupt Enable of Source" }
+        ],
+      }
+    }
+    { skipto: "0x200000" }
+    { name: "THRESHOLD0",
+      desc: "Threshold of priority for Target 0",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "2:0" }
+      ],
+    }
+    { name: "CC0",
+      desc: '''Claim interrupt by read, complete interrupt by write for Target 0.
+      Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      hwre: "true",
+      fields: [
+        { bits: "4:0" }
+      ],
+      tags: [// CC register value is related to IP
+             "excl:CsrNonInitTests:CsrExclCheck"],
+    }
+  { skipto: "0x4000000" }
+    { name: "MSIP0",
+      desc: '''msip for Hart 0.
+      Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          desc: "Software Interrupt Pending register",
+        }
+      ],
+    }
+  { skipto: "0x4004000" }
+  { name: "ALERT_TEST",
+      desc: '''Alert Test Register.''',
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe:     "True",
+      hwext:    "True",
+      fields: [
+        { bits: "0",
+          name: "fatal_fault",
+          desc: "'Write 1 to trigger one alert event of this kind.'",
+        }
+      ],
+    }
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/plic/doc/registers.md b/docs/um/ip/plic/doc/registers.md
new file mode 100644
index 00000000..3717573a
--- /dev/null
+++ b/docs/um/ip/plic/doc/registers.md
@@ -0,0 +1,751 @@
+## Summary
+
+| Name                                | Offset    |   Length | Description                                                        |
+|:------------------------------------|:----------|---------:|:-------------------------------------------------------------------|
+| rv_plic.[`PRIO0`](#prio0)           | 0x0       |        4 | Interrupt Source 0 Priority                                        |
+| rv_plic.[`PRIO1`](#prio1)           | 0x4       |        4 | Interrupt Source 1 Priority                                        |
+| rv_plic.[`PRIO2`](#prio2)           | 0x8       |        4 | Interrupt Source 2 Priority                                        |
+| rv_plic.[`PRIO3`](#prio3)           | 0xc       |        4 | Interrupt Source 3 Priority                                        |
+| rv_plic.[`PRIO4`](#prio4)           | 0x10      |        4 | Interrupt Source 4 Priority                                        |
+| rv_plic.[`PRIO5`](#prio5)           | 0x14      |        4 | Interrupt Source 5 Priority                                        |
+| rv_plic.[`PRIO6`](#prio6)           | 0x18      |        4 | Interrupt Source 6 Priority                                        |
+| rv_plic.[`PRIO7`](#prio7)           | 0x1c      |        4 | Interrupt Source 7 Priority                                        |
+| rv_plic.[`PRIO8`](#prio8)           | 0x20      |        4 | Interrupt Source 8 Priority                                        |
+| rv_plic.[`PRIO9`](#prio9)           | 0x24      |        4 | Interrupt Source 9 Priority                                        |
+| rv_plic.[`PRIO10`](#prio10)         | 0x28      |        4 | Interrupt Source 10 Priority                                       |
+| rv_plic.[`PRIO11`](#prio11)         | 0x2c      |        4 | Interrupt Source 11 Priority                                       |
+| rv_plic.[`PRIO12`](#prio12)         | 0x30      |        4 | Interrupt Source 12 Priority                                       |
+| rv_plic.[`PRIO13`](#prio13)         | 0x34      |        4 | Interrupt Source 13 Priority                                       |
+| rv_plic.[`PRIO14`](#prio14)         | 0x38      |        4 | Interrupt Source 14 Priority                                       |
+| rv_plic.[`PRIO15`](#prio15)         | 0x3c      |        4 | Interrupt Source 15 Priority                                       |
+| rv_plic.[`PRIO16`](#prio16)         | 0x40      |        4 | Interrupt Source 16 Priority                                       |
+| rv_plic.[`PRIO17`](#prio17)         | 0x44      |        4 | Interrupt Source 17 Priority                                       |
+| rv_plic.[`PRIO18`](#prio18)         | 0x48      |        4 | Interrupt Source 18 Priority                                       |
+| rv_plic.[`PRIO19`](#prio19)         | 0x4c      |        4 | Interrupt Source 19 Priority                                       |
+| rv_plic.[`PRIO20`](#prio20)         | 0x50      |        4 | Interrupt Source 20 Priority                                       |
+| rv_plic.[`PRIO21`](#prio21)         | 0x54      |        4 | Interrupt Source 21 Priority                                       |
+| rv_plic.[`PRIO22`](#prio22)         | 0x58      |        4 | Interrupt Source 22 Priority                                       |
+| rv_plic.[`PRIO23`](#prio23)         | 0x5c      |        4 | Interrupt Source 23 Priority                                       |
+| rv_plic.[`PRIO24`](#prio24)         | 0x60      |        4 | Interrupt Source 24 Priority                                       |
+| rv_plic.[`PRIO25`](#prio25)         | 0x64      |        4 | Interrupt Source 25 Priority                                       |
+| rv_plic.[`PRIO26`](#prio26)         | 0x68      |        4 | Interrupt Source 26 Priority                                       |
+| rv_plic.[`PRIO27`](#prio27)         | 0x6c      |        4 | Interrupt Source 27 Priority                                       |
+| rv_plic.[`PRIO28`](#prio28)         | 0x70      |        4 | Interrupt Source 28 Priority                                       |
+| rv_plic.[`PRIO29`](#prio29)         | 0x74      |        4 | Interrupt Source 29 Priority                                       |
+| rv_plic.[`PRIO30`](#prio30)         | 0x78      |        4 | Interrupt Source 30 Priority                                       |
+| rv_plic.[`PRIO31`](#prio31)         | 0x7c      |        4 | Interrupt Source 31 Priority                                       |
+| rv_plic.[`IP`](#IP)                 | 0x1000    |        4 | Interrupt Pending                                                  |
+| rv_plic.[`IE0`](#IE0)               | 0x2000    |        4 | Interrupt Enable for Target 0                                      |
+| rv_plic.[`THRESHOLD0`](#threshold0) | 0x200000  |        4 | Threshold of priority for Target 0                                 |
+| rv_plic.[`CC0`](#cc0)               | 0x200004  |        4 | Claim interrupt by read, complete interrupt by write for Target 0. |
+| rv_plic.[`MSIP0`](#msip0)           | 0x4000000 |        4 | msip for Hart 0.                                                   |
+| rv_plic.[`ALERT_TEST`](#alert_test) | 0x4004000 |        4 | Alert Test Register.                                               |
+
+## PRIO0
+Interrupt Source 0 Priority
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO0  |               |
+
+## PRIO1
+Interrupt Source 1 Priority
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO1  |               |
+
+## PRIO2
+Interrupt Source 2 Priority
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO2  |               |
+
+## PRIO3
+Interrupt Source 3 Priority
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO3  |               |
+
+## PRIO4
+Interrupt Source 4 Priority
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO4", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO4  |               |
+
+## PRIO5
+Interrupt Source 5 Priority
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO5", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO5  |               |
+
+## PRIO6
+Interrupt Source 6 Priority
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO6", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO6  |               |
+
+## PRIO7
+Interrupt Source 7 Priority
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO7", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO7  |               |
+
+## PRIO8
+Interrupt Source 8 Priority
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO8", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO8  |               |
+
+## PRIO9
+Interrupt Source 9 Priority
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO9", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO9  |               |
+
+## PRIO10
+Interrupt Source 10 Priority
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO10", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO10 |               |
+
+## PRIO11
+Interrupt Source 11 Priority
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO11", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO11 |               |
+
+## PRIO12
+Interrupt Source 12 Priority
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO12", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO12 |               |
+
+## PRIO13
+Interrupt Source 13 Priority
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO13", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO13 |               |
+
+## PRIO14
+Interrupt Source 14 Priority
+- Offset: `0x38`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO14", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO14 |               |
+
+## PRIO15
+Interrupt Source 15 Priority
+- Offset: `0x3c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO15", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO15 |               |
+
+## PRIO16
+Interrupt Source 16 Priority
+- Offset: `0x40`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO16", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO16 |               |
+
+## PRIO17
+Interrupt Source 17 Priority
+- Offset: `0x44`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO17", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO17 |               |
+
+## PRIO18
+Interrupt Source 18 Priority
+- Offset: `0x48`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO18", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO18 |               |
+
+## PRIO19
+Interrupt Source 19 Priority
+- Offset: `0x4c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO19", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO19 |               |
+
+## PRIO20
+Interrupt Source 20 Priority
+- Offset: `0x50`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO20", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO20 |               |
+
+## PRIO21
+Interrupt Source 21 Priority
+- Offset: `0x54`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO21", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO21 |               |
+
+## PRIO22
+Interrupt Source 22 Priority
+- Offset: `0x58`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO22", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO22 |               |
+
+## PRIO23
+Interrupt Source 23 Priority
+- Offset: `0x5c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO23", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO23 |               |
+
+## PRIO24
+Interrupt Source 24 Priority
+- Offset: `0x60`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO24", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO24 |               |
+
+## PRIO25
+Interrupt Source 25 Priority
+- Offset: `0x64`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO25", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO25 |               |
+
+## PRIO26
+Interrupt Source 26 Priority
+- Offset: `0x68`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO26", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO26 |               |
+
+## PRIO27
+Interrupt Source 27 Priority
+- Offset: `0x6c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO27", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO27 |               |
+
+## PRIO28
+Interrupt Source 28 Priority
+- Offset: `0x70`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO28", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO28 |               |
+
+## PRIO29
+Interrupt Source 29 Priority
+- Offset: `0x74`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO29", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO29 |               |
+
+## PRIO30
+Interrupt Source 30 Priority
+- Offset: `0x78`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO30", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO30 |               |
+
+## PRIO31
+Interrupt Source 31 Priority
+- Offset: `0x7c`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PRIO31", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:3  |        |         |        | Reserved      |
+|  2:0   |   rw   |   0x0   | PRIO31 |               |
+
+## IP
+Interrupt Pending
+- Offset: `0x1000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "P_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_9", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_10", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_11", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_12", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_13", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_14", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_15", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_16", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_17", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_18", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_19", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_20", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_21", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_22", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_23", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_24", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_25", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_26", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_27", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_28", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_29", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_30", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "P_31", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                 |
+|:------:|:------:|:-------:|:-------|:----------------------------|
+|   31   |   ro   |   0x0   | P_31   | Interrupt Pending of Source |
+|   30   |   ro   |   0x0   | P_30   | Interrupt Pending of Source |
+|   29   |   ro   |   0x0   | P_29   | Interrupt Pending of Source |
+|   28   |   ro   |   0x0   | P_28   | Interrupt Pending of Source |
+|   27   |   ro   |   0x0   | P_27   | Interrupt Pending of Source |
+|   26   |   ro   |   0x0   | P_26   | Interrupt Pending of Source |
+|   25   |   ro   |   0x0   | P_25   | Interrupt Pending of Source |
+|   24   |   ro   |   0x0   | P_24   | Interrupt Pending of Source |
+|   23   |   ro   |   0x0   | P_23   | Interrupt Pending of Source |
+|   22   |   ro   |   0x0   | P_22   | Interrupt Pending of Source |
+|   21   |   ro   |   0x0   | P_21   | Interrupt Pending of Source |
+|   20   |   ro   |   0x0   | P_20   | Interrupt Pending of Source |
+|   19   |   ro   |   0x0   | P_19   | Interrupt Pending of Source |
+|   18   |   ro   |   0x0   | P_18   | Interrupt Pending of Source |
+|   17   |   ro   |   0x0   | P_17   | Interrupt Pending of Source |
+|   16   |   ro   |   0x0   | P_16   | Interrupt Pending of Source |
+|   15   |   ro   |   0x0   | P_15   | Interrupt Pending of Source |
+|   14   |   ro   |   0x0   | P_14   | Interrupt Pending of Source |
+|   13   |   ro   |   0x0   | P_13   | Interrupt Pending of Source |
+|   12   |   ro   |   0x0   | P_12   | Interrupt Pending of Source |
+|   11   |   ro   |   0x0   | P_11   | Interrupt Pending of Source |
+|   10   |   ro   |   0x0   | P_10   | Interrupt Pending of Source |
+|   9    |   ro   |   0x0   | P_9    | Interrupt Pending of Source |
+|   8    |   ro   |   0x0   | P_8    | Interrupt Pending of Source |
+|   7    |   ro   |   0x0   | P_7    | Interrupt Pending of Source |
+|   6    |   ro   |   0x0   | P_6    | Interrupt Pending of Source |
+|   5    |   ro   |   0x0   | P_5    | Interrupt Pending of Source |
+|   4    |   ro   |   0x0   | P_4    | Interrupt Pending of Source |
+|   3    |   ro   |   0x0   | P_3    | Interrupt Pending of Source |
+|   2    |   ro   |   0x0   | P_2    | Interrupt Pending of Source |
+|   1    |   ro   |   0x0   | P_1    | Interrupt Pending of Source |
+|   0    |   ro   |   0x0   | P_0    | Interrupt Pending of Source |
+
+## IE0
+Interrupt Enable for Target 0
+- Offset: `0x2000`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "E_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "E_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                |
+|:------:|:------:|:-------:|:-------|:---------------------------|
+|   31   |   rw   |   0x0   | E_31   | Interrupt Enable of Source |
+|   30   |   rw   |   0x0   | E_30   | Interrupt Enable of Source |
+|   29   |   rw   |   0x0   | E_29   | Interrupt Enable of Source |
+|   28   |   rw   |   0x0   | E_28   | Interrupt Enable of Source |
+|   27   |   rw   |   0x0   | E_27   | Interrupt Enable of Source |
+|   26   |   rw   |   0x0   | E_26   | Interrupt Enable of Source |
+|   25   |   rw   |   0x0   | E_25   | Interrupt Enable of Source |
+|   24   |   rw   |   0x0   | E_24   | Interrupt Enable of Source |
+|   23   |   rw   |   0x0   | E_23   | Interrupt Enable of Source |
+|   22   |   rw   |   0x0   | E_22   | Interrupt Enable of Source |
+|   21   |   rw   |   0x0   | E_21   | Interrupt Enable of Source |
+|   20   |   rw   |   0x0   | E_20   | Interrupt Enable of Source |
+|   19   |   rw   |   0x0   | E_19   | Interrupt Enable of Source |
+|   18   |   rw   |   0x0   | E_18   | Interrupt Enable of Source |
+|   17   |   rw   |   0x0   | E_17   | Interrupt Enable of Source |
+|   16   |   rw   |   0x0   | E_16   | Interrupt Enable of Source |
+|   15   |   rw   |   0x0   | E_15   | Interrupt Enable of Source |
+|   14   |   rw   |   0x0   | E_14   | Interrupt Enable of Source |
+|   13   |   rw   |   0x0   | E_13   | Interrupt Enable of Source |
+|   12   |   rw   |   0x0   | E_12   | Interrupt Enable of Source |
+|   11   |   rw   |   0x0   | E_11   | Interrupt Enable of Source |
+|   10   |   rw   |   0x0   | E_10   | Interrupt Enable of Source |
+|   9    |   rw   |   0x0   | E_9    | Interrupt Enable of Source |
+|   8    |   rw   |   0x0   | E_8    | Interrupt Enable of Source |
+|   7    |   rw   |   0x0   | E_7    | Interrupt Enable of Source |
+|   6    |   rw   |   0x0   | E_6    | Interrupt Enable of Source |
+|   5    |   rw   |   0x0   | E_5    | Interrupt Enable of Source |
+|   4    |   rw   |   0x0   | E_4    | Interrupt Enable of Source |
+|   3    |   rw   |   0x0   | E_3    | Interrupt Enable of Source |
+|   2    |   rw   |   0x0   | E_2    | Interrupt Enable of Source |
+|   1    |   rw   |   0x0   | E_1    | Interrupt Enable of Source |
+|   0    |   rw   |   0x0   | E_0    | Interrupt Enable of Source |
+
+## THRESHOLD0
+Threshold of priority for Target 0
+- Offset: `0x200000`
+- Reset default: `0x0`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "THRESHOLD0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description   |
+|:------:|:------:|:-------:|:-----------|:--------------|
+|  31:3  |        |         |            | Reserved      |
+|  2:0   |   rw   |   0x0   | THRESHOLD0 |               |
+
+## CC0
+Claim interrupt by read, complete interrupt by write for Target 0.
+Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.
+- Offset: `0x200004`
+- Reset default: `0x0`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CC0", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:5  |        |         |        | Reserved      |
+|  4:0   |   rw   |    x    | CC0    |               |
+
+## MSIP0
+msip for Hart 0.
+Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.
+- Offset: `0x4000000`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "MSIP0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                         |
+|:------:|:------:|:-------:|:-------|:------------------------------------|
+|  31:1  |        |         |        | Reserved                            |
+|   0    |   rw   |   0x0   | MSIP0  | Software Interrupt Pending register |
+
+## ALERT_TEST
+Alert Test Register.
+- Offset: `0x4004000`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                        |
+|:------:|:------:|:-------:|:------------|:---------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                           |
+|   0    |   wo   |    x    | fatal_fault | 'Write 1 to trigger one alert event of this kind.' |
+
diff --git a/docs/um/ip/safety_island/data/safety_soc_ctrl_regs.hjson b/docs/um/ip/safety_island/data/safety_soc_ctrl_regs.hjson
new file mode 100644
index 00000000..b99f65cb
--- /dev/null
+++ b/docs/um/ip/safety_island/data/safety_soc_ctrl_regs.hjson
@@ -0,0 +1,68 @@
+# Copyright 2023 ETH Zurich and University of Bologna
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+{
+  name: "safety_soc_ctrl",
+  clock_primary: "clk_i",
+  reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+  registers: [
+    { name: "bootaddr",
+      desc: "Core Boot Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "bootaddr",
+          desc: "Boot Address",
+          resval: 0x1A00_0000
+        }
+      ]
+
+    },
+    { name: "fetchen",
+      desc: "Core Fetch Enable",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0",
+          name: "fetchen",
+          desc: "Fetch Enable",
+          resval: 0
+        }
+      ]
+    },
+    { name: "corestatus",
+      desc: "Core Return Status (return value, EOC)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "core_status",
+          desc: "Core Return Status (EOC(bit[31]) and status(bit[30:0]))",
+          resval: 0
+        }
+      ]
+    }
+    { name: "bootmode",
+      desc: "Core Boot Mode",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "1:0",
+          name: "bootmode",
+          desc: "Boot Mode",
+          resval: 0x0
+        }
+      ]
+
+    },
+  ],
+}
\ No newline at end of file
diff --git a/docs/um/ip/safety_island/data/safety_soc_ctrl_regs_doc.hjson b/docs/um/ip/safety_island/data/safety_soc_ctrl_regs_doc.hjson
new file mode 100644
index 00000000..b54b483d
--- /dev/null
+++ b/docs/um/ip/safety_island/data/safety_soc_ctrl_regs_doc.hjson
@@ -0,0 +1,71 @@
+# Copyright 2023 ETH Zurich and University of Bologna
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+# Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+
+{
+  name: "safety_soc_ctrl",
+  cip_id: "36",
+  version: "0.0.0", //null, commit aaef55c
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul",
+      direction: "device"
+    }
+  ],
+  regwidth: "32",
+  registers: [
+    { name: "bootaddr",
+      desc: "Core Boot Address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "bootaddr",
+          desc: "Boot Address",
+          resval: 0x1A00_0000
+        }
+      ]
+
+    },
+    { name: "fetchen",
+      desc: "Core Fetch Enable",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0",
+          name: "fetchen",
+          desc: "Fetch Enable",
+          resval: 0
+        }
+      ]
+    },
+    { name: "corestatus",
+      desc: "Core Return Status (return value, EOC)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "core_status",
+          desc: "Core Return Status (EOC(bit[31]) and status(bit[30:0]))",
+          resval: 0
+        }
+      ]
+    }
+    { name: "bootmode",
+      desc: "Core Boot Mode",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "1:0",
+          name: "bootmode",
+          desc: "Boot Mode",
+          resval: 0x0
+        }
+      ]
+
+    },
+  ],
+}
diff --git a/docs/um/ip/safety_island/doc/registers.md b/docs/um/ip/safety_island/doc/registers.md
new file mode 100644
index 00000000..e95798e2
--- /dev/null
+++ b/docs/um/ip/safety_island/doc/registers.md
@@ -0,0 +1,75 @@
+## Summary
+
+| Name                                        | Offset   |   Length | Description                            |
+|:--------------------------------------------|:---------|---------:|:---------------------------------------|
+| safety_soc_ctrl.[`bootaddr`](#bootaddr)     | 0x0      |        4 | Core Boot Address                      |
+| safety_soc_ctrl.[`fetchen`](#fetchen)       | 0x4      |        4 | Core Fetch Enable                      |
+| safety_soc_ctrl.[`corestatus`](#corestatus) | 0x8      |        4 | Core Return Status (return value, EOC) |
+| safety_soc_ctrl.[`bootmode`](#bootmode)     | 0xc      |        4 | Core Boot Mode                         |
+
+## bootaddr
+Core Boot Address
+- Offset: `0x0`
+- Reset default: `0x1a000000`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |   Reset    | Name     | Description   |
+|:------:|:------:|:----------:|:---------|:--------------|
+|  31:0  |   rw   | 0x1a000000 | bootaddr | Boot Address  |
+
+## fetchen
+Core Fetch Enable
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description   |
+|:------:|:------:|:-------:|:--------|:--------------|
+|  31:1  |        |         |         | Reserved      |
+|   0    |   rw   |   0x0   | fetchen | Fetch Enable  |
+
+## corestatus
+Core Return Status (return value, EOC)
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                             |
+|:------:|:------:|:-------:|:------------|:--------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) |
+
+## bootmode
+Core Boot Mode
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description   |
+|:------:|:------:|:-------:|:---------|:--------------|
+|  31:2  |        |         |          | Reserved      |
+|  1:0   |   rw   |   0x0   | bootmode | Boot Mode     |
+
diff --git a/docs/um/ip/serial_link/data/serial_link_regs.hjson b/docs/um/ip/serial_link/data/serial_link_regs.hjson
new file mode 100644
index 00000000..4c1592fb
--- /dev/null
+++ b/docs/um/ip/serial_link/data/serial_link_regs.hjson
@@ -0,0 +1,421 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Author: Tim Fischer <fischeti@iis.ee.ethz.ch>
+
+{
+  name: "serial_link",
+  clock_primary: "clk_i"
+  reset_primary: "rst_ni"
+  bus_interfaces: [
+      { protocol: "reg_iface", direction: "device"}
+  ]
+  regwidth: "32",
+  param_list: [
+    { name: "NumChannels",
+      desc: "Number of channels",
+      type: "int",
+      default: "38",
+      local: "true"
+    },
+    { name: "Log2NumChannels",
+      desc: "Number of channels",
+      type: "int",
+      default: "6",
+      local: "true"
+    },
+    { name: "NumBits",
+      desc: "Number of bits transfered in one clock cycle (2 * NumLanes)",
+      type: "int",
+      default: "16",
+      local: "true"
+    },
+    { name: "Log2MaxClkDiv",
+      desc: "Number of bits for clock divider counter",
+      type: "int",
+      default: "10",
+      local: "true"
+    },
+    { name: "FlushCounterWidth",
+      desc: "The number of bits used for the auto-flush counters in the channel allocator"
+      type: "int",
+      default: "8",
+      local: "true"
+    },
+    { name: "Log2RawModeTXFifoDepth",
+      desc: "The depth of the TX FIFO for raw mode operation."
+      type: "int",
+      default: "3",
+      local: "true"
+    }
+  ],
+
+  registers: [
+    {
+      name: "CTRL",
+      desc: "Global clock, isolation and reset control configuration"
+      swaccess: "rw",
+      hwaccess: "hro",
+      // Clock disabled (i.e. gated) by default
+      fields: [
+        {
+          bits: "0",
+          name: "clk_ena",
+          desc: "Clock gate enable for network, link, physical layer. (active-high)",
+          resval: 0,
+        },
+        {
+          bits: "1",
+          name: "reset_n",
+          resval: 1,
+          // *Not* held in reset (i.e. signal high) by default.
+          // Since clock is gated on reset, inner serial link state should *not* change until ungate.
+          desc: "SW controlled synchronous reset. (active-low)"
+        },
+        // All channels isolated by default
+        {
+          bits: "8",
+          name: "axi_in_isolate",
+          resval: 1,
+          desc: "Isolate AXI slave in port. (active-high)"
+        },
+        {
+          bits: "9",
+          name: "axi_out_isolate",
+          resval: 1,
+          desc: "Isolate AXI master out port. (active-high)"
+        }
+      ]
+    },
+    {
+      name: "ISOLATED",
+      desc: "Isolation status of AXI ports",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwqe: "true",
+      hwext: "true",
+      // All channels isolated by default
+      fields: [
+        {bits: "0:0", name: "axi_in",  resval: 1, desc: "slave in isolation status"},
+        {bits: "1:1", name: "axi_out", resval: 1, desc: "master out isolation status"},
+      ]
+    },
+    { multireg:
+      {
+        name: "TX_PHY_CLK_DIV",
+        desc: "Holds clock divider factor for forwarded clock of the TX Phys",
+        count: "NumChannels",
+        cname: "TX_PHY_CLK_DIV",
+        swaccess: "rw",
+        hwaccess: "hro",
+        compact: false,
+        fields: [
+          { bits: "Log2MaxClkDiv:0",
+            desc: "Clock division factor of TX clock",
+            name: "clk_divs",
+            resval: 8
+          }
+        ]
+      }
+    },
+    { multireg:
+      {
+        name: "TX_PHY_CLK_START",
+        desc: "Controls duty cycle and phase of rising edge in TX Phys",
+        count: "NumChannels",
+        cname: "TX_PHY_CLK_START",
+        compact: false,
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "Log2MaxClkDiv:0",
+            name: "clk_shift_start",
+            desc: "Positive Edge of divided, shifted clock",
+            resval: 2
+          }
+        ]
+      }
+    },
+    { multireg:
+      {
+        name: "TX_PHY_CLK_END",
+        desc: "Controls duty cycle and phase of falling edge in TX Phys",
+        count: "NumChannels",
+        cname: "TX_PHY_CLK_END",
+        compact: false,
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "Log2MaxClkDiv:0",
+            name: "clk_shift_end",
+            desc: "Negative Edge of divided, shifted clock",
+            resval: 6
+          }
+        ]
+      }
+    },
+    {
+      name: "RAW_MODE_EN",
+      desc: "Enables Raw mode",
+      swaccess: "wo",
+      hwaccess: "hro",
+      fields: [
+        {bits: "0", resval: 0}
+      ]
+    },
+    {
+      name: "RAW_MODE_IN_CH_SEL",
+      desc: "Receive channel select in RAW mode",
+      swaccess: "wo",
+      hwaccess: "hro",
+      fields: [
+        { bits: "Log2NumChannels-1:0",
+          resval: 0
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "RAW_MODE_IN_DATA_VALID"
+        cname: "RAW_MODE_IN_DATA_VALID"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Mask for valid data in RX FIFOs during RAW mode."
+        swaccess: "ro",
+        hwaccess: "hwo",
+        hwext: "true",
+        fields: [
+          {
+            bits: "0"
+          },
+        ]
+      }
+    },
+    {
+      name: "RAW_MODE_IN_DATA",
+      desc: "Data received by the selected channel in RAW mode",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "NumBits-1:0",
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "RAW_MODE_OUT_CH_MASK"
+        cname: "RAW_MODE_OUT_CH_MASK"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Selects channels to send out data in RAW mode, '1 corresponds to broadcasting"
+        swaccess: "wo",
+        hwaccess: "hro",
+        fields: [
+          {
+            bits: "0",
+            resval: 0
+          },
+        ]
+      }
+    },
+    {
+      name: "RAW_MODE_OUT_DATA_FIFO",
+      desc: "Data that will be pushed to the RAW mode output FIFO",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe: "true",
+      fields: [
+        { bits: "NumBits-1:0",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "RAW_MODE_OUT_DATA_FIFO_CTRL",
+      desc: "Status and control register for the RAW mode data out FIFO",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        {
+          bits: "0",
+          name: "clear",
+          swaccess: "wo",
+          hwaccess: "hro",
+          desc: "Clears the raw mode TX FIFO.",
+        },
+        {
+          bits: "8+Log2RawModeTXFifoDepth-1:8",
+          name: "fill_state",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          desc: "The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.",
+          resval: 0
+        },
+        {
+          bits: "31",
+          name: "is_full",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          desc: "If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again.",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "RAW_MODE_OUT_EN",
+      desc: "Enable transmission of data currently hold in the output FIFO",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "FLOW_CONTROL_FIFO_CLEAR",
+      desc: "Clears the flow control Fifo",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "0",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "CHANNEL_ALLOC_TX_CFG"
+      desc: "Configuration settings for the TX side in the channel allocator"
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "0",
+          name: "bypass_en",
+          desc: "Enable bypassing the TX channel allocator"
+          resval: 1
+        },
+        {
+          bits: "1",
+          name: "auto_flush_en",
+          desc: "Enable the auto-flush feature of the TX side in the channel allocator"
+          resval: 1
+        },
+        {
+          bits: "15:8",
+          name: "auto_flush_count",
+          desc: "The number of cycles to wait before auto flushing (sending) packets in the channel allocator",
+          resval: 2
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "CHANNEL_ALLOC_TX_CH_EN"
+        cname: "CHANNEL_ALLOC_TX_CH_EN"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Channel enable mask for the TX side."
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          {
+            bits: "0",
+            resval: 1
+          },
+        ]
+      }
+    },
+    {
+      name: "CHANNEL_ALLOC_TX_CTRL",
+      desc: "Soft clear or force flush the TX side of the channel allocator",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        {
+          bits: "0",
+          name: "clear",
+          desc: "Software clear the TX side of the channel allocator",
+        },
+        {
+          bits: "1",
+          name: "flush",
+          desc: "Flush (transmit remaining data) in the TX side of the channel allocator.",
+        }
+      ]
+    },
+    {
+      name: "CHANNEL_ALLOC_RX_CFG"
+      desc: "Configuration settings for the RX side in the channel allocator"
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "0",
+          name: "bypass_en",
+          desc: "Enable bypassing the RX channel allocator"
+          resval: 1
+        },
+        {
+          bits: "1",
+          name: "auto_flush_en",
+          desc: "Enable the auto-flush feature of the RX side in the channel allocator"
+          resval: 1
+        },
+        {
+          bits: "15:8",
+          name: "auto_flush_count",
+          desc: "The number of cycles to wait before synchronizing on partial packets on the RX side",
+          resval: 2
+        },
+        {
+          bits: "16",
+          name: "sync_en",
+          desc: "Enable (1) or disable (0) the synchronization barrier between the channels (needs to be disabled in raw mode).",
+          resval: 1
+        }
+      ]
+    },
+    {
+      name: "CHANNEL_ALLOC_RX_CTRL",
+      desc: "Soft clear the RX side of the channel allocator",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        {
+          bits: "0",
+          name: "clear",
+          desc: "Software clear the TX side of the channel allocator",
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "CHANNEL_ALLOC_RX_CH_EN"
+        cname: "CHANNEL_ALLOC_RX_CH_EN"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Channel enable mask for the RX side."
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          {
+            bits: "0",
+            resval: 1
+          },
+        ]
+      }
+    },
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/serial_link/data/serial_link_regs_doc.hjson b/docs/um/ip/serial_link/data/serial_link_regs_doc.hjson
new file mode 100644
index 00000000..d009fdb1
--- /dev/null
+++ b/docs/um/ip/serial_link/data/serial_link_regs_doc.hjson
@@ -0,0 +1,424 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Author: Tim Fischer <fischeti@iis.ee.ethz.ch>
+
+{
+  name: "serial_link",
+  cip_id: "36",
+  version: "1.1.0",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+      { protocol: "tlul", direction: "device"}
+  ]
+  regwidth: "32",
+  param_list: [
+    { name: "NumChannels",
+      desc: "Number of channels",
+      type: "int",
+      default: "38",
+      local: "true"
+    },
+    { name: "Log2NumChannels",
+      desc: "Number of channels",
+      type: "int",
+      default: "6",
+      local: "true"
+    },
+    { name: "NumBits",
+      desc: "Number of bits transfered in one clock cycle (2 * NumLanes)",
+      type: "int",
+      default: "16",
+      local: "true"
+    },
+    { name: "Log2MaxClkDiv",
+      desc: "Number of bits for clock divider counter",
+      type: "int",
+      default: "10",
+      local: "true"
+    },
+    { name: "FlushCounterWidth",
+      desc: "The number of bits used for the auto-flush counters in the channel allocator"
+      type: "int",
+      default: "8",
+      local: "true"
+    },
+    { name: "Log2RawModeTXFifoDepth",
+      desc: "The depth of the TX FIFO for raw mode operation."
+      type: "int",
+      default: "3",
+      local: "true"
+    }
+  ],
+
+  registers: [
+    {
+      name: "CTRL",
+      desc: "Global clock, isolation and reset control configuration"
+      swaccess: "rw",
+      hwaccess: "hro",
+      // Clock disabled (i.e. gated) by default
+      fields: [
+        {
+          bits: "0",
+          name: "clk_ena",
+          desc: "Clock gate enable for network, link, physical layer. (active-high)",
+          resval: 0,
+        },
+        {
+          bits: "1",
+          name: "reset_n",
+          resval: 1,
+          // *Not* held in reset (i.e. signal high) by default.
+          // Since clock is gated on reset, inner serial link state should *not* change until ungate.
+          desc: "SW controlled synchronous reset. (active-low)"
+        },
+        // All channels isolated by default
+        {
+          bits: "8",
+          name: "axi_in_isolate",
+          resval: 1,
+          desc: "Isolate AXI slave in port. (active-high)"
+        },
+        {
+          bits: "9",
+          name: "axi_out_isolate",
+          resval: 1,
+          desc: "Isolate AXI master out port. (active-high)"
+        }
+      ]
+    },
+    {
+      name: "ISOLATED",
+      desc: "Isolation status of AXI ports",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwqe: "true",
+      hwext: "true",
+      // All channels isolated by default
+      fields: [
+        {bits: "0:0", name: "axi_in",  resval: 1, desc: "slave in isolation status"},
+        {bits: "1:1", name: "axi_out", resval: 1, desc: "master out isolation status"},
+      ]
+    },
+    { multireg:
+      {
+        name: "TX_PHY_CLK_DIV",
+        desc: "Holds clock divider factor for forwarded clock of the TX Phys",
+        count: "NumChannels",
+        cname: "TX_PHY_CLK_DIV",
+        swaccess: "rw",
+        hwaccess: "hro",
+        compact: false,
+        fields: [
+          { bits: "Log2MaxClkDiv:0",
+            desc: "Clock division factor of TX clock",
+            name: "clk_divs",
+            resval: 8
+          }
+        ]
+      }
+    },
+    { multireg:
+      {
+        name: "TX_PHY_CLK_START",
+        desc: "Controls duty cycle and phase of rising edge in TX Phys",
+        count: "NumChannels",
+        cname: "TX_PHY_CLK_START",
+        compact: false,
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "Log2MaxClkDiv:0",
+            name: "clk_shift_start",
+            desc: "Positive Edge of divided, shifted clock",
+            resval: 2
+          }
+        ]
+      }
+    },
+    { multireg:
+      {
+        name: "TX_PHY_CLK_END",
+        desc: "Controls duty cycle and phase of falling edge in TX Phys",
+        count: "NumChannels",
+        cname: "TX_PHY_CLK_END",
+        compact: false,
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          { bits: "Log2MaxClkDiv:0",
+            name: "clk_shift_end",
+            desc: "Negative Edge of divided, shifted clock",
+            resval: 6
+          }
+        ]
+      }
+    },
+    {
+      name: "RAW_MODE_EN",
+      desc: "Enables Raw mode",
+      swaccess: "wo",
+      hwaccess: "hro",
+      fields: [
+        {bits: "0", resval: 0}
+      ]
+    },
+    {
+      name: "RAW_MODE_IN_CH_SEL",
+      desc: "Receive channel select in RAW mode",
+      swaccess: "wo",
+      hwaccess: "hro",
+      fields: [
+        { bits: "Log2NumChannels-1:0",
+          resval: 0
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "RAW_MODE_IN_DATA_VALID"
+        cname: "RAW_MODE_IN_DATA_VALID"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Mask for valid data in RX FIFOs during RAW mode."
+        swaccess: "ro",
+        hwaccess: "hwo",
+        hwext: "true",
+        fields: [
+          {
+            bits: "0"
+          },
+        ]
+      }
+    },
+    {
+      name: "RAW_MODE_IN_DATA",
+      desc: "Data received by the selected channel in RAW mode",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "NumBits-1:0",
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "RAW_MODE_OUT_CH_MASK"
+        cname: "RAW_MODE_OUT_CH_MASK"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Selects channels to send out data in RAW mode, '1 corresponds to broadcasting"
+        swaccess: "wo",
+        hwaccess: "hro",
+        fields: [
+          {
+            bits: "0",
+            resval: 0
+          },
+        ]
+      }
+    },
+    {
+      name: "RAW_MODE_OUT_DATA_FIFO",
+      desc: "Data that will be pushed to the RAW mode output FIFO",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe: "true",
+      fields: [
+        { bits: "NumBits-1:0",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "RAW_MODE_OUT_DATA_FIFO_CTRL",
+      desc: "Status and control register for the RAW mode data out FIFO",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        {
+          bits: "0",
+          name: "clear",
+          swaccess: "wo",
+          hwaccess: "hro",
+          desc: "Clears the raw mode TX FIFO.",
+        },
+        {
+          bits: "8+Log2RawModeTXFifoDepth-1:8",
+          name: "fill_state",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          desc: "The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.",
+          resval: 0
+        },
+        {
+          bits: "31",
+          name: "is_full",
+          swaccess: "ro",
+          hwaccess: "hwo",
+          desc: "If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again.",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "RAW_MODE_OUT_EN",
+      desc: "Enable transmission of data currently hold in the output FIFO",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "FLOW_CONTROL_FIFO_CLEAR",
+      desc: "Clears the flow control Fifo",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "0",
+          resval: 0
+        }
+      ]
+    },
+    {
+      name: "CHANNEL_ALLOC_TX_CFG"
+      desc: "Configuration settings for the TX side in the channel allocator"
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "0",
+          name: "bypass_en",
+          desc: "Enable bypassing the TX channel allocator"
+          resval: 1
+        },
+        {
+          bits: "1",
+          name: "auto_flush_en",
+          desc: "Enable the auto-flush feature of the TX side in the channel allocator"
+          resval: 1
+        },
+        {
+          bits: "15:8",
+          name: "auto_flush_count",
+          desc: "The number of cycles to wait before auto flushing (sending) packets in the channel allocator",
+          resval: 2
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "CHANNEL_ALLOC_TX_CH_EN"
+        cname: "CHANNEL_ALLOC_TX_CH_EN"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Channel enable mask for the TX side."
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          {
+            bits: "0",
+            resval: 1
+          },
+        ]
+      }
+    },
+    {
+      name: "CHANNEL_ALLOC_TX_CTRL",
+      desc: "Soft clear or force flush the TX side of the channel allocator",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        {
+          bits: "0",
+          name: "clear",
+          desc: "Software clear the TX side of the channel allocator",
+        },
+        {
+          bits: "1",
+          name: "flush",
+          desc: "Flush (transmit remaining data) in the TX side of the channel allocator.",
+        }
+      ]
+    },
+    {
+      name: "CHANNEL_ALLOC_RX_CFG"
+      desc: "Configuration settings for the RX side in the channel allocator"
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "0",
+          name: "bypass_en",
+          desc: "Enable bypassing the RX channel allocator"
+          resval: 1
+        },
+        {
+          bits: "1",
+          name: "auto_flush_en",
+          desc: "Enable the auto-flush feature of the RX side in the channel allocator"
+          resval: 1
+        },
+        {
+          bits: "15:8",
+          name: "auto_flush_count",
+          desc: "The number of cycles to wait before synchronizing on partial packets on the RX side",
+          resval: 2
+        },
+        {
+          bits: "16",
+          name: "sync_en",
+          desc: "Enable (1) or disable (0) the synchronization barrier between the channels (needs to be disabled in raw mode).",
+          resval: 1
+        }
+      ]
+    },
+    {
+      name: "CHANNEL_ALLOC_RX_CTRL",
+      desc: "Soft clear the RX side of the channel allocator",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        {
+          bits: "0",
+          name: "clear",
+          desc: "Software clear the TX side of the channel allocator",
+        }
+      ]
+    },
+    {multireg:
+      {
+        name: "CHANNEL_ALLOC_RX_CH_EN"
+        cname: "CHANNEL_ALLOC_RX_CH_EN"
+        count: "NumChannels",
+        compact: "true",
+        desc: "Channel enable mask for the RX side."
+        swaccess: "rw",
+        hwaccess: "hro",
+        fields: [
+          {
+            bits: "0",
+            resval: 1
+          },
+        ]
+      }
+    },
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/serial_link/doc/registers.md b/docs/um/ip/serial_link/doc/registers.md
new file mode 100644
index 00000000..24eac5c9
--- /dev/null
+++ b/docs/um/ip/serial_link/doc/registers.md
@@ -0,0 +1,833 @@
+## Summary
+
+| Name                                                                      | Offset   |   Length | Description                                                                   |
+|:--------------------------------------------------------------------------|:---------|---------:|:------------------------------------------------------------------------------|
+| serial_link.[`CTRL`](#ctrl)                                               | 0x0      |        4 | Global clock, isolation and reset control configuration                       |
+| serial_link.[`ISOLATED`](#isolated)                                       | 0x4      |        4 | Isolation status of AXI ports                                                 |
+| serial_link.[`TX_PHY_CLK_DIV_0`](#tx_phy_clk_div)                         | 0x8      |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_1`](#tx_phy_clk_div)                         | 0xc      |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_2`](#tx_phy_clk_div)                         | 0x10     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_3`](#tx_phy_clk_div)                         | 0x14     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_4`](#tx_phy_clk_div)                         | 0x18     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_5`](#tx_phy_clk_div)                         | 0x1c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_6`](#tx_phy_clk_div)                         | 0x20     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_7`](#tx_phy_clk_div)                         | 0x24     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_8`](#tx_phy_clk_div)                         | 0x28     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_9`](#tx_phy_clk_div)                         | 0x2c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_10`](#tx_phy_clk_div)                        | 0x30     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_11`](#tx_phy_clk_div)                        | 0x34     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_12`](#tx_phy_clk_div)                        | 0x38     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_13`](#tx_phy_clk_div)                        | 0x3c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_14`](#tx_phy_clk_div)                        | 0x40     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_15`](#tx_phy_clk_div)                        | 0x44     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_16`](#tx_phy_clk_div)                        | 0x48     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_17`](#tx_phy_clk_div)                        | 0x4c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_18`](#tx_phy_clk_div)                        | 0x50     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_19`](#tx_phy_clk_div)                        | 0x54     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_20`](#tx_phy_clk_div)                        | 0x58     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_21`](#tx_phy_clk_div)                        | 0x5c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_22`](#tx_phy_clk_div)                        | 0x60     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_23`](#tx_phy_clk_div)                        | 0x64     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_24`](#tx_phy_clk_div)                        | 0x68     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_25`](#tx_phy_clk_div)                        | 0x6c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_26`](#tx_phy_clk_div)                        | 0x70     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_27`](#tx_phy_clk_div)                        | 0x74     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_28`](#tx_phy_clk_div)                        | 0x78     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_29`](#tx_phy_clk_div)                        | 0x7c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_30`](#tx_phy_clk_div)                        | 0x80     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_31`](#tx_phy_clk_div)                        | 0x84     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_32`](#tx_phy_clk_div)                        | 0x88     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_33`](#tx_phy_clk_div)                        | 0x8c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_34`](#tx_phy_clk_div)                        | 0x90     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_35`](#tx_phy_clk_div)                        | 0x94     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_36`](#tx_phy_clk_div)                        | 0x98     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_DIV_37`](#tx_phy_clk_div)                        | 0x9c     |        4 | Holds clock divider factor for forwarded clock of the TX Phys                 |
+| serial_link.[`TX_PHY_CLK_START_0`](#tx_phy_clk_start)                     | 0xa0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_1`](#tx_phy_clk_start)                     | 0xa4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_2`](#tx_phy_clk_start)                     | 0xa8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_3`](#tx_phy_clk_start)                     | 0xac     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_4`](#tx_phy_clk_start)                     | 0xb0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_5`](#tx_phy_clk_start)                     | 0xb4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_6`](#tx_phy_clk_start)                     | 0xb8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_7`](#tx_phy_clk_start)                     | 0xbc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_8`](#tx_phy_clk_start)                     | 0xc0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_9`](#tx_phy_clk_start)                     | 0xc4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_10`](#tx_phy_clk_start)                    | 0xc8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_11`](#tx_phy_clk_start)                    | 0xcc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_12`](#tx_phy_clk_start)                    | 0xd0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_13`](#tx_phy_clk_start)                    | 0xd4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_14`](#tx_phy_clk_start)                    | 0xd8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_15`](#tx_phy_clk_start)                    | 0xdc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_16`](#tx_phy_clk_start)                    | 0xe0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_17`](#tx_phy_clk_start)                    | 0xe4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_18`](#tx_phy_clk_start)                    | 0xe8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_19`](#tx_phy_clk_start)                    | 0xec     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_20`](#tx_phy_clk_start)                    | 0xf0     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_21`](#tx_phy_clk_start)                    | 0xf4     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_22`](#tx_phy_clk_start)                    | 0xf8     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_23`](#tx_phy_clk_start)                    | 0xfc     |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_24`](#tx_phy_clk_start)                    | 0x100    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_25`](#tx_phy_clk_start)                    | 0x104    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_26`](#tx_phy_clk_start)                    | 0x108    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_27`](#tx_phy_clk_start)                    | 0x10c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_28`](#tx_phy_clk_start)                    | 0x110    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_29`](#tx_phy_clk_start)                    | 0x114    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_30`](#tx_phy_clk_start)                    | 0x118    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_31`](#tx_phy_clk_start)                    | 0x11c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_32`](#tx_phy_clk_start)                    | 0x120    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_33`](#tx_phy_clk_start)                    | 0x124    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_34`](#tx_phy_clk_start)                    | 0x128    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_35`](#tx_phy_clk_start)                    | 0x12c    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_36`](#tx_phy_clk_start)                    | 0x130    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_START_37`](#tx_phy_clk_start)                    | 0x134    |        4 | Controls duty cycle and phase of rising edge in TX Phys                       |
+| serial_link.[`TX_PHY_CLK_END_0`](#tx_phy_clk_end)                         | 0x138    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_1`](#tx_phy_clk_end)                         | 0x13c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_2`](#tx_phy_clk_end)                         | 0x140    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_3`](#tx_phy_clk_end)                         | 0x144    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_4`](#tx_phy_clk_end)                         | 0x148    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_5`](#tx_phy_clk_end)                         | 0x14c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_6`](#tx_phy_clk_end)                         | 0x150    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_7`](#tx_phy_clk_end)                         | 0x154    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_8`](#tx_phy_clk_end)                         | 0x158    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_9`](#tx_phy_clk_end)                         | 0x15c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_10`](#tx_phy_clk_end)                        | 0x160    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_11`](#tx_phy_clk_end)                        | 0x164    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_12`](#tx_phy_clk_end)                        | 0x168    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_13`](#tx_phy_clk_end)                        | 0x16c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_14`](#tx_phy_clk_end)                        | 0x170    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_15`](#tx_phy_clk_end)                        | 0x174    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_16`](#tx_phy_clk_end)                        | 0x178    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_17`](#tx_phy_clk_end)                        | 0x17c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_18`](#tx_phy_clk_end)                        | 0x180    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_19`](#tx_phy_clk_end)                        | 0x184    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_20`](#tx_phy_clk_end)                        | 0x188    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_21`](#tx_phy_clk_end)                        | 0x18c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_22`](#tx_phy_clk_end)                        | 0x190    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_23`](#tx_phy_clk_end)                        | 0x194    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_24`](#tx_phy_clk_end)                        | 0x198    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_25`](#tx_phy_clk_end)                        | 0x19c    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_26`](#tx_phy_clk_end)                        | 0x1a0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_27`](#tx_phy_clk_end)                        | 0x1a4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_28`](#tx_phy_clk_end)                        | 0x1a8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_29`](#tx_phy_clk_end)                        | 0x1ac    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_30`](#tx_phy_clk_end)                        | 0x1b0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_31`](#tx_phy_clk_end)                        | 0x1b4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_32`](#tx_phy_clk_end)                        | 0x1b8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_33`](#tx_phy_clk_end)                        | 0x1bc    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_34`](#tx_phy_clk_end)                        | 0x1c0    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_35`](#tx_phy_clk_end)                        | 0x1c4    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_36`](#tx_phy_clk_end)                        | 0x1c8    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`TX_PHY_CLK_END_37`](#tx_phy_clk_end)                        | 0x1cc    |        4 | Controls duty cycle and phase of falling edge in TX Phys                      |
+| serial_link.[`RAW_MODE_EN`](#raw_mode_en)                                 | 0x1d0    |        4 | Enables Raw mode                                                              |
+| serial_link.[`RAW_MODE_IN_CH_SEL`](#raw_mode_in_ch_sel)                   | 0x1d4    |        4 | Receive channel select in RAW mode                                            |
+| serial_link.[`RAW_MODE_IN_DATA_VALID_0`](#RAW_MODE_IN_DATA_VALID_0)       | 0x1d8    |        4 | Mask for valid data in RX FIFOs during RAW mode.                              |
+| serial_link.[`RAW_MODE_IN_DATA_VALID_1`](#RAW_MODE_IN_DATA_VALID_1)       | 0x1dc    |        4 | Mask for valid data in RX FIFOs during RAW mode.                              |
+| serial_link.[`RAW_MODE_IN_DATA`](#raw_mode_in_data)                       | 0x1e0    |        4 | Data received by the selected channel in RAW mode                             |
+| serial_link.[`RAW_MODE_OUT_CH_MASK_0`](#RAW_MODE_OUT_CH_MASK_0)           | 0x1e4    |        4 | Selects channels to send out data in RAW mode, '1 corresponds to broadcasting |
+| serial_link.[`RAW_MODE_OUT_CH_MASK_1`](#RAW_MODE_OUT_CH_MASK_1)           | 0x1e8    |        4 | Selects channels to send out data in RAW mode, '1 corresponds to broadcasting |
+| serial_link.[`RAW_MODE_OUT_DATA_FIFO`](#raw_mode_out_data_fifo)           | 0x1ec    |        4 | Data that will be pushed to the RAW mode output FIFO                          |
+| serial_link.[`RAW_MODE_OUT_DATA_FIFO_CTRL`](#raw_mode_out_data_fifo_ctrl) | 0x1f0    |        4 | Status and control register for the RAW mode data out FIFO                    |
+| serial_link.[`RAW_MODE_OUT_EN`](#raw_mode_out_en)                         | 0x1f4    |        4 | Enable transmission of data currently hold in the output FIFO                 |
+| serial_link.[`FLOW_CONTROL_FIFO_CLEAR`](#flow_control_fifo_clear)         | 0x1f8    |        4 | Clears the flow control Fifo                                                  |
+| serial_link.[`CHANNEL_ALLOC_TX_CFG`](#channel_alloc_tx_cfg)               | 0x1fc    |        4 | Configuration settings for the TX side in the channel allocator               |
+| serial_link.[`CHANNEL_ALLOC_TX_CH_EN_0`](#CHANNEL_ALLOC_TX_CH_EN_0)       | 0x200    |        4 | Channel enable mask for the TX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_TX_CH_EN_1`](#CHANNEL_ALLOC_TX_CH_EN_1)       | 0x204    |        4 | Channel enable mask for the TX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_TX_CTRL`](#channel_alloc_tx_ctrl)             | 0x208    |        4 | Soft clear or force flush the TX side of the channel allocator                |
+| serial_link.[`CHANNEL_ALLOC_RX_CFG`](#channel_alloc_rx_cfg)               | 0x20c    |        4 | Configuration settings for the RX side in the channel allocator               |
+| serial_link.[`CHANNEL_ALLOC_RX_CTRL`](#channel_alloc_rx_ctrl)             | 0x210    |        4 | Soft clear the RX side of the channel allocator                               |
+| serial_link.[`CHANNEL_ALLOC_RX_CH_EN_0`](#CHANNEL_ALLOC_RX_CH_EN_0)       | 0x214    |        4 | Channel enable mask for the RX side.                                          |
+| serial_link.[`CHANNEL_ALLOC_RX_CH_EN_1`](#CHANNEL_ALLOC_RX_CH_EN_1)       | 0x218    |        4 | Channel enable mask for the RX side.                                          |
+
+## CTRL
+Global clock, isolation and reset control configuration
+- Offset: `0x0`
+- Reset default: `0x302`
+- Reset mask: `0x303`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_ena", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "reset_n", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "axi_in_isolate", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "axi_out_isolate", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                                                        |
+|:------:|:------:|:-------:|:----------------|:-------------------------------------------------------------------|
+| 31:10  |        |         |                 | Reserved                                                           |
+|   9    |   rw   |   0x1   | axi_out_isolate | Isolate AXI master out port. (active-high)                         |
+|   8    |   rw   |   0x1   | axi_in_isolate  | Isolate AXI slave in port. (active-high)                           |
+|  7:2   |        |         |                 | Reserved                                                           |
+|   1    |   rw   |   0x1   | reset_n         | SW controlled synchronous reset. (active-low)                      |
+|   0    |   rw   |   0x0   | clk_ena         | Clock gate enable for network, link, physical layer. (active-high) |
+
+## ISOLATED
+Isolation status of AXI ports
+- Offset: `0x4`
+- Reset default: `0x3`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "axi_in", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "axi_out", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                 |
+|:------:|:------:|:-------:|:--------|:----------------------------|
+|  31:2  |        |         |         | Reserved                    |
+|   1    |   ro   |   0x1   | axi_out | master out isolation status |
+|   0    |   ro   |   0x1   | axi_in  | slave in isolation status   |
+
+## TX_PHY_CLK_DIV
+Holds clock divider factor for forwarded clock of the TX Phys
+- Reset default: `0x8`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name              | Offset   |
+|:------------------|:---------|
+| TX_PHY_CLK_DIV_0  | 0x8      |
+| TX_PHY_CLK_DIV_1  | 0xc      |
+| TX_PHY_CLK_DIV_2  | 0x10     |
+| TX_PHY_CLK_DIV_3  | 0x14     |
+| TX_PHY_CLK_DIV_4  | 0x18     |
+| TX_PHY_CLK_DIV_5  | 0x1c     |
+| TX_PHY_CLK_DIV_6  | 0x20     |
+| TX_PHY_CLK_DIV_7  | 0x24     |
+| TX_PHY_CLK_DIV_8  | 0x28     |
+| TX_PHY_CLK_DIV_9  | 0x2c     |
+| TX_PHY_CLK_DIV_10 | 0x30     |
+| TX_PHY_CLK_DIV_11 | 0x34     |
+| TX_PHY_CLK_DIV_12 | 0x38     |
+| TX_PHY_CLK_DIV_13 | 0x3c     |
+| TX_PHY_CLK_DIV_14 | 0x40     |
+| TX_PHY_CLK_DIV_15 | 0x44     |
+| TX_PHY_CLK_DIV_16 | 0x48     |
+| TX_PHY_CLK_DIV_17 | 0x4c     |
+| TX_PHY_CLK_DIV_18 | 0x50     |
+| TX_PHY_CLK_DIV_19 | 0x54     |
+| TX_PHY_CLK_DIV_20 | 0x58     |
+| TX_PHY_CLK_DIV_21 | 0x5c     |
+| TX_PHY_CLK_DIV_22 | 0x60     |
+| TX_PHY_CLK_DIV_23 | 0x64     |
+| TX_PHY_CLK_DIV_24 | 0x68     |
+| TX_PHY_CLK_DIV_25 | 0x6c     |
+| TX_PHY_CLK_DIV_26 | 0x70     |
+| TX_PHY_CLK_DIV_27 | 0x74     |
+| TX_PHY_CLK_DIV_28 | 0x78     |
+| TX_PHY_CLK_DIV_29 | 0x7c     |
+| TX_PHY_CLK_DIV_30 | 0x80     |
+| TX_PHY_CLK_DIV_31 | 0x84     |
+| TX_PHY_CLK_DIV_32 | 0x88     |
+| TX_PHY_CLK_DIV_33 | 0x8c     |
+| TX_PHY_CLK_DIV_34 | 0x90     |
+| TX_PHY_CLK_DIV_35 | 0x94     |
+| TX_PHY_CLK_DIV_36 | 0x98     |
+| TX_PHY_CLK_DIV_37 | 0x9c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_divs", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                       |
+|:------:|:------:|:-------:|:---------|:----------------------------------|
+| 31:11  |        |         |          | Reserved                          |
+|  10:0  |   rw   |   0x8   | clk_divs | Clock division factor of TX clock |
+
+## TX_PHY_CLK_START
+Controls duty cycle and phase of rising edge in TX Phys
+- Reset default: `0x2`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name                | Offset   |
+|:--------------------|:---------|
+| TX_PHY_CLK_START_0  | 0xa0     |
+| TX_PHY_CLK_START_1  | 0xa4     |
+| TX_PHY_CLK_START_2  | 0xa8     |
+| TX_PHY_CLK_START_3  | 0xac     |
+| TX_PHY_CLK_START_4  | 0xb0     |
+| TX_PHY_CLK_START_5  | 0xb4     |
+| TX_PHY_CLK_START_6  | 0xb8     |
+| TX_PHY_CLK_START_7  | 0xbc     |
+| TX_PHY_CLK_START_8  | 0xc0     |
+| TX_PHY_CLK_START_9  | 0xc4     |
+| TX_PHY_CLK_START_10 | 0xc8     |
+| TX_PHY_CLK_START_11 | 0xcc     |
+| TX_PHY_CLK_START_12 | 0xd0     |
+| TX_PHY_CLK_START_13 | 0xd4     |
+| TX_PHY_CLK_START_14 | 0xd8     |
+| TX_PHY_CLK_START_15 | 0xdc     |
+| TX_PHY_CLK_START_16 | 0xe0     |
+| TX_PHY_CLK_START_17 | 0xe4     |
+| TX_PHY_CLK_START_18 | 0xe8     |
+| TX_PHY_CLK_START_19 | 0xec     |
+| TX_PHY_CLK_START_20 | 0xf0     |
+| TX_PHY_CLK_START_21 | 0xf4     |
+| TX_PHY_CLK_START_22 | 0xf8     |
+| TX_PHY_CLK_START_23 | 0xfc     |
+| TX_PHY_CLK_START_24 | 0x100    |
+| TX_PHY_CLK_START_25 | 0x104    |
+| TX_PHY_CLK_START_26 | 0x108    |
+| TX_PHY_CLK_START_27 | 0x10c    |
+| TX_PHY_CLK_START_28 | 0x110    |
+| TX_PHY_CLK_START_29 | 0x114    |
+| TX_PHY_CLK_START_30 | 0x118    |
+| TX_PHY_CLK_START_31 | 0x11c    |
+| TX_PHY_CLK_START_32 | 0x120    |
+| TX_PHY_CLK_START_33 | 0x124    |
+| TX_PHY_CLK_START_34 | 0x128    |
+| TX_PHY_CLK_START_35 | 0x12c    |
+| TX_PHY_CLK_START_36 | 0x130    |
+| TX_PHY_CLK_START_37 | 0x134    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_shift_start", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                             |
+|:------:|:------:|:-------:|:----------------|:----------------------------------------|
+| 31:11  |        |         |                 | Reserved                                |
+|  10:0  |   rw   |   0x2   | clk_shift_start | Positive Edge of divided, shifted clock |
+
+## TX_PHY_CLK_END
+Controls duty cycle and phase of falling edge in TX Phys
+- Reset default: `0x6`
+- Reset mask: `0x7ff`
+
+### Instances
+
+| Name              | Offset   |
+|:------------------|:---------|
+| TX_PHY_CLK_END_0  | 0x138    |
+| TX_PHY_CLK_END_1  | 0x13c    |
+| TX_PHY_CLK_END_2  | 0x140    |
+| TX_PHY_CLK_END_3  | 0x144    |
+| TX_PHY_CLK_END_4  | 0x148    |
+| TX_PHY_CLK_END_5  | 0x14c    |
+| TX_PHY_CLK_END_6  | 0x150    |
+| TX_PHY_CLK_END_7  | 0x154    |
+| TX_PHY_CLK_END_8  | 0x158    |
+| TX_PHY_CLK_END_9  | 0x15c    |
+| TX_PHY_CLK_END_10 | 0x160    |
+| TX_PHY_CLK_END_11 | 0x164    |
+| TX_PHY_CLK_END_12 | 0x168    |
+| TX_PHY_CLK_END_13 | 0x16c    |
+| TX_PHY_CLK_END_14 | 0x170    |
+| TX_PHY_CLK_END_15 | 0x174    |
+| TX_PHY_CLK_END_16 | 0x178    |
+| TX_PHY_CLK_END_17 | 0x17c    |
+| TX_PHY_CLK_END_18 | 0x180    |
+| TX_PHY_CLK_END_19 | 0x184    |
+| TX_PHY_CLK_END_20 | 0x188    |
+| TX_PHY_CLK_END_21 | 0x18c    |
+| TX_PHY_CLK_END_22 | 0x190    |
+| TX_PHY_CLK_END_23 | 0x194    |
+| TX_PHY_CLK_END_24 | 0x198    |
+| TX_PHY_CLK_END_25 | 0x19c    |
+| TX_PHY_CLK_END_26 | 0x1a0    |
+| TX_PHY_CLK_END_27 | 0x1a4    |
+| TX_PHY_CLK_END_28 | 0x1a8    |
+| TX_PHY_CLK_END_29 | 0x1ac    |
+| TX_PHY_CLK_END_30 | 0x1b0    |
+| TX_PHY_CLK_END_31 | 0x1b4    |
+| TX_PHY_CLK_END_32 | 0x1b8    |
+| TX_PHY_CLK_END_33 | 0x1bc    |
+| TX_PHY_CLK_END_34 | 0x1c0    |
+| TX_PHY_CLK_END_35 | 0x1c4    |
+| TX_PHY_CLK_END_36 | 0x1c8    |
+| TX_PHY_CLK_END_37 | 0x1cc    |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_shift_end", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                             |
+|:------:|:------:|:-------:|:--------------|:----------------------------------------|
+| 31:11  |        |         |               | Reserved                                |
+|  10:0  |   rw   |   0x6   | clk_shift_end | Negative Edge of divided, shifted clock |
+
+## RAW_MODE_EN
+Enables Raw mode
+- Offset: `0x1d0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_EN", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description   |
+|:------:|:------:|:-------:|:------------|:--------------|
+|  31:1  |        |         |             | Reserved      |
+|   0    |   wo   |   0x0   | RAW_MODE_EN |               |
+
+## RAW_MODE_IN_CH_SEL
+Receive channel select in RAW mode
+- Offset: `0x1d4`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_CH_SEL", "bits": 6, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description   |
+|:------:|:------:|:-------:|:-------------------|:--------------|
+|  31:6  |        |         |                    | Reserved      |
+|  5:0   |   wo   |   0x0   | RAW_MODE_IN_CH_SEL |               |
+
+## RAW_MODE_IN_DATA_VALID_0
+Mask for valid data in RX FIFOs during RAW mode.
+- Offset: `0x1d8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA_VALID_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_6", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_7", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_8", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_9", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_10", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_11", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_12", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_13", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_14", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_15", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_16", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_17", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_18", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_19", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_20", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_21", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_22", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_23", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_24", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_25", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_26", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_27", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_28", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_29", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_30", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_31", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_31 |               |
+|   30   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_30 |               |
+|   29   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_29 |               |
+|   28   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_28 |               |
+|   27   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_27 |               |
+|   26   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_26 |               |
+|   25   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_25 |               |
+|   24   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_24 |               |
+|   23   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_23 |               |
+|   22   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_22 |               |
+|   21   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_21 |               |
+|   20   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_20 |               |
+|   19   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_19 |               |
+|   18   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_18 |               |
+|   17   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_17 |               |
+|   16   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_16 |               |
+|   15   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_15 |               |
+|   14   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_14 |               |
+|   13   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_13 |               |
+|   12   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_12 |               |
+|   11   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_11 |               |
+|   10   |   ro   |    x    | RAW_MODE_IN_DATA_VALID_10 |               |
+|   9    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_9  |               |
+|   8    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_8  |               |
+|   7    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_7  |               |
+|   6    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_6  |               |
+|   5    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_5  |               |
+|   4    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_4  |               |
+|   3    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_3  |               |
+|   2    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_2  |               |
+|   1    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_1  |               |
+|   0    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_0  |               |
+
+## RAW_MODE_IN_DATA_VALID_1
+Mask for valid data in RX FIFOs during RAW mode.
+- Offset: `0x1dc`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA_VALID_32", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_33", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_34", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_35", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_36", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RAW_MODE_IN_DATA_VALID_37", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_37 | For RAW_MODE_IN_DATA_VALID1 |
+|   4    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_36 | For RAW_MODE_IN_DATA_VALID1 |
+|   3    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_35 | For RAW_MODE_IN_DATA_VALID1 |
+|   2    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_34 | For RAW_MODE_IN_DATA_VALID1 |
+|   1    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_33 | For RAW_MODE_IN_DATA_VALID1 |
+|   0    |   ro   |    x    | RAW_MODE_IN_DATA_VALID_32 | For RAW_MODE_IN_DATA_VALID1 |
+
+## RAW_MODE_IN_DATA
+Data received by the selected channel in RAW mode
+- Offset: `0x1e0`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_IN_DATA", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description   |
+|:------:|:------:|:-------:|:-----------------|:--------------|
+| 31:16  |        |         |                  | Reserved      |
+|  15:0  |   ro   |    x    | RAW_MODE_IN_DATA |               |
+
+## RAW_MODE_OUT_CH_MASK_0
+Selects channels to send out data in RAW mode, '1 corresponds to broadcasting
+- Offset: `0x1e4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_CH_MASK_0", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_1", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_2", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_3", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_4", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_5", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_6", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_7", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_8", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_9", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_10", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_11", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_12", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_13", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_14", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_15", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_16", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_17", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_18", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_19", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_20", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_21", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_22", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_23", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_24", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_25", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_26", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_27", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_28", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_29", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_30", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_31", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|   31   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_31 |               |
+|   30   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_30 |               |
+|   29   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_29 |               |
+|   28   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_28 |               |
+|   27   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_27 |               |
+|   26   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_26 |               |
+|   25   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_25 |               |
+|   24   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_24 |               |
+|   23   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_23 |               |
+|   22   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_22 |               |
+|   21   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_21 |               |
+|   20   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_20 |               |
+|   19   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_19 |               |
+|   18   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_18 |               |
+|   17   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_17 |               |
+|   16   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_16 |               |
+|   15   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_15 |               |
+|   14   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_14 |               |
+|   13   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_13 |               |
+|   12   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_12 |               |
+|   11   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_11 |               |
+|   10   |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_10 |               |
+|   9    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_9  |               |
+|   8    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_8  |               |
+|   7    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_7  |               |
+|   6    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_6  |               |
+|   5    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_5  |               |
+|   4    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_4  |               |
+|   3    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_3  |               |
+|   2    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_2  |               |
+|   1    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_1  |               |
+|   0    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_0  |               |
+
+## RAW_MODE_OUT_CH_MASK_1
+Selects channels to send out data in RAW mode, '1 corresponds to broadcasting
+- Offset: `0x1e8`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_CH_MASK_32", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_33", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_34", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_35", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_36", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RAW_MODE_OUT_CH_MASK_37", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description               |
+|:------:|:------:|:-------:|:------------------------|:--------------------------|
+|  31:6  |        |         |                         | Reserved                  |
+|   5    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_37 | For RAW_MODE_OUT_CH_MASK1 |
+|   4    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_36 | For RAW_MODE_OUT_CH_MASK1 |
+|   3    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_35 | For RAW_MODE_OUT_CH_MASK1 |
+|   2    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_34 | For RAW_MODE_OUT_CH_MASK1 |
+|   1    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_33 | For RAW_MODE_OUT_CH_MASK1 |
+|   0    |   wo   |   0x0   | RAW_MODE_OUT_CH_MASK_32 | For RAW_MODE_OUT_CH_MASK1 |
+
+## RAW_MODE_OUT_DATA_FIFO
+Data that will be pushed to the RAW mode output FIFO
+- Offset: `0x1ec`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_DATA_FIFO", "bits": 16, "attr": ["wo"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                   | Description   |
+|:------:|:------:|:-------:|:-----------------------|:--------------|
+| 31:16  |        |         |                        | Reserved      |
+|  15:0  |   wo   |   0x0   | RAW_MODE_OUT_DATA_FIFO |               |
+
+## RAW_MODE_OUT_DATA_FIFO_CTRL
+Status and control register for the RAW mode data out FIFO
+- Offset: `0x1f0`
+- Reset default: `0x0`
+- Reset mask: `0x80000701`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 7}, {"name": "fill_state", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 20}, {"name": "is_full", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description                                                                                                                                                       |
+|:------:|:------:|:-------:|:-----------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   ro   |   0x0   | is_full    | If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again. |
+| 30:11  |        |         |            | Reserved                                                                                                                                                          |
+|  10:8  |   ro   |   0x0   | fill_state | The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.                                                                        |
+|  7:1   |        |         |            | Reserved                                                                                                                                                          |
+|   0    |   wo   |    x    | clear      | Clears the raw mode TX FIFO.                                                                                                                                      |
+
+## RAW_MODE_OUT_EN
+Enable transmission of data currently hold in the output FIFO
+- Offset: `0x1f4`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RAW_MODE_OUT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description   |
+|:------:|:------:|:-------:|:----------------|:--------------|
+|  31:1  |        |         |                 | Reserved      |
+|   0    |   rw   |   0x0   | RAW_MODE_OUT_EN |               |
+
+## FLOW_CONTROL_FIFO_CLEAR
+Clears the flow control Fifo
+- Offset: `0x1f8`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "FLOW_CONTROL_FIFO_CLEAR", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                    | Description   |
+|:------:|:------:|:-------:|:------------------------|:--------------|
+|  31:1  |        |         |                         | Reserved      |
+|   0    |   wo   |   0x0   | FLOW_CONTROL_FIFO_CLEAR |               |
+
+## CHANNEL_ALLOC_TX_CFG
+Configuration settings for the TX side in the channel allocator
+- Offset: `0x1fc`
+- Reset default: `0x203`
+- Reset mask: `0xff03`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypass_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auto_flush_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "auto_flush_count", "bits": 8, "attr": ["rw"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                  |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------|
+| 31:16  |        |         |                  | Reserved                                                                                     |
+|  15:8  |   rw   |   0x2   | auto_flush_count | The number of cycles to wait before auto flushing (sending) packets in the channel allocator |
+|  7:2   |        |         |                  | Reserved                                                                                     |
+|   1    |   rw   |   0x1   | auto_flush_en    | Enable the auto-flush feature of the TX side in the channel allocator                        |
+|   0    |   rw   |   0x1   | bypass_en        | Enable bypassing the TX channel allocator                                                    |
+
+## CHANNEL_ALLOC_TX_CH_EN_0
+Channel enable mask for the TX side.
+- Offset: `0x200`
+- Reset default: `0xffffffff`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_TX_CH_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_31 |               |
+|   30   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_30 |               |
+|   29   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_29 |               |
+|   28   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_28 |               |
+|   27   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_27 |               |
+|   26   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_26 |               |
+|   25   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_25 |               |
+|   24   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_24 |               |
+|   23   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_23 |               |
+|   22   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_22 |               |
+|   21   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_21 |               |
+|   20   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_20 |               |
+|   19   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_19 |               |
+|   18   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_18 |               |
+|   17   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_17 |               |
+|   16   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_16 |               |
+|   15   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_15 |               |
+|   14   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_14 |               |
+|   13   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_13 |               |
+|   12   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_12 |               |
+|   11   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_11 |               |
+|   10   |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_10 |               |
+|   9    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_9  |               |
+|   8    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_8  |               |
+|   7    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_7  |               |
+|   6    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_6  |               |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_5  |               |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_4  |               |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_3  |               |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_2  |               |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_1  |               |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_0  |               |
+
+## CHANNEL_ALLOC_TX_CH_EN_1
+Channel enable mask for the TX side.
+- Offset: `0x204`
+- Reset default: `0x3f`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_TX_CH_EN_32", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_33", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_34", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_35", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_36", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_TX_CH_EN_37", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_37 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_36 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_35 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_34 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_33 | For CHANNEL_ALLOC_TX_CH_EN1 |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_TX_CH_EN_32 | For CHANNEL_ALLOC_TX_CH_EN1 |
+
+## CHANNEL_ALLOC_TX_CTRL
+Soft clear or force flush the TX side of the channel allocator
+- Offset: `0x208`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "flush", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                              |
+|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------|
+|  31:2  |        |         |        | Reserved                                                                 |
+|   1    |   wo   |    x    | flush  | Flush (transmit remaining data) in the TX side of the channel allocator. |
+|   0    |   wo   |    x    | clear  | Software clear the TX side of the channel allocator                      |
+
+## CHANNEL_ALLOC_RX_CFG
+Configuration settings for the RX side in the channel allocator
+- Offset: `0x20c`
+- Reset default: `0x10203`
+- Reset mask: `0x1ff03`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "bypass_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auto_flush_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "auto_flush_count", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "sync_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}}
+```
+
+|  Bits  |  Type  |  Reset  | Name             | Description                                                                                                    |
+|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------------------------------------------|
+| 31:17  |        |         |                  | Reserved                                                                                                       |
+|   16   |   rw   |   0x1   | sync_en          | Enable (1) or disable (0) the synchronization barrier between the channels (needs to be disabled in raw mode). |
+|  15:8  |   rw   |   0x2   | auto_flush_count | The number of cycles to wait before synchronizing on partial packets on the RX side                            |
+|  7:2   |        |         |                  | Reserved                                                                                                       |
+|   1    |   rw   |   0x1   | auto_flush_en    | Enable the auto-flush feature of the RX side in the channel allocator                                          |
+|   0    |   rw   |   0x1   | bypass_en        | Enable bypassing the RX channel allocator                                                                      |
+
+## CHANNEL_ALLOC_RX_CTRL
+Soft clear the RX side of the channel allocator
+- Offset: `0x210`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clear", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                         |
+|:------:|:------:|:-------:|:-------|:----------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                            |
+|   0    |   wo   |    x    | clear  | Software clear the TX side of the channel allocator |
+
+## CHANNEL_ALLOC_RX_CH_EN_0
+Channel enable mask for the RX side.
+- Offset: `0x214`
+- Reset default: `0xffffffff`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_RX_CH_EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_12", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_13", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_14", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_15", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_16", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_17", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_18", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_19", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_20", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_21", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_22", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_23", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_24", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_25", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_26", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_27", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_28", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_29", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_30", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_31", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description   |
+|:------:|:------:|:-------:|:--------------------------|:--------------|
+|   31   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_31 |               |
+|   30   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_30 |               |
+|   29   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_29 |               |
+|   28   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_28 |               |
+|   27   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_27 |               |
+|   26   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_26 |               |
+|   25   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_25 |               |
+|   24   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_24 |               |
+|   23   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_23 |               |
+|   22   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_22 |               |
+|   21   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_21 |               |
+|   20   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_20 |               |
+|   19   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_19 |               |
+|   18   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_18 |               |
+|   17   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_17 |               |
+|   16   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_16 |               |
+|   15   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_15 |               |
+|   14   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_14 |               |
+|   13   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_13 |               |
+|   12   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_12 |               |
+|   11   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_11 |               |
+|   10   |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_10 |               |
+|   9    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_9  |               |
+|   8    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_8  |               |
+|   7    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_7  |               |
+|   6    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_6  |               |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_5  |               |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_4  |               |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_3  |               |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_2  |               |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_1  |               |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_0  |               |
+
+## CHANNEL_ALLOC_RX_CH_EN_1
+Channel enable mask for the RX side.
+- Offset: `0x218`
+- Reset default: `0x3f`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CHANNEL_ALLOC_RX_CH_EN_32", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_33", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_34", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_35", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_36", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CHANNEL_ALLOC_RX_CH_EN_37", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                      | Description                 |
+|:------:|:------:|:-------:|:--------------------------|:----------------------------|
+|  31:6  |        |         |                           | Reserved                    |
+|   5    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_37 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   4    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_36 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   3    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_35 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   2    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_34 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   1    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_33 | For CHANNEL_ALLOC_RX_CH_EN1 |
+|   0    |   rw   |   0x1   | CHANNEL_ALLOC_RX_CH_EN_32 | For CHANNEL_ALLOC_RX_CH_EN1 |
+
diff --git a/docs/um/ip/spim/data/spi_host_ot.hjson b/docs/um/ip/spim/data/spi_host_ot.hjson
new file mode 100644
index 00000000..08b9823f
--- /dev/null
+++ b/docs/um/ip/spim/data/spi_host_ot.hjson
@@ -0,0 +1,673 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name:               "spi_host",
+  human_name:         "SPI Host",
+  one_line_desc:      "Serial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices",
+  one_paragraph_desc: '''
+  SPI Host bridges communications from the TileLink Uncached Light (TL-UL) bus and off-chip devices by acting as a SPI interface bus master, primarily intended for communication with serial NOR flash devices and other low-speed devices.
+  While SPI is not a formal standard, this implementation aims to be general enough to support a variety of devices by providing a plethora of run-time configurable options.
+  Communication with each device on the bus uses an independent chip select (CS), and each transaction may be individually configured regarding endianness, polarity and phase (CPOL/ CPHA), and full-duplex/half-duplex commands in standard mode.
+  32-bit TL-UL registers interface with receive and transmit data FIFOs as well as a command FIFO for encoding multiple sequential 'segments' making up a larger SPI transaction.
+  This allows each segment to have an arbitrary byte-count, Std/Dual/Quad width, and direction, and it allows the CS to be managed automatically across multiple sequential segments.
+  '''
+  // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
+  cip_id:             "27",
+  design_spec:        "../doc",
+  dv_doc:             "../doc/dv",
+  hw_checklist:       "../doc/checklist",
+  sw_checklist:       "/sw/device/lib/dif/dif_spi_host",
+  revisions: [
+    {
+      version:            "3.0.0",
+      life_stage:         "L1",
+      design_stage:       "D0",
+      verification_stage: "V0",
+      dif_stage:          "S1",
+    }
+  ]
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true},
+  ]
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device", racl_support: true }
+  ],
+  inter_signal_list: [
+    { struct:  "passthrough",
+      package: "spi_device_pkg",
+      type:    "req_rsp",
+      name:    "passthrough",
+      act:     "rsp",
+      width:   "1"
+    }
+    { struct: "logic",
+      type:   "uni",
+      name:   "lsio_trigger",
+      desc: '''
+            Self-clearing status trigger for the DMA.
+            Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour.
+            '''
+      act:    "req",
+    }
+    { struct:  "racl_policy_vec",
+      type:    "uni",
+      name:    "racl_policies",
+      act:     "rcv",
+      package: "top_racl_pkg",
+      desc:    '''
+        Incoming RACL policy vector from a racl_ctrl instance.
+        The policy selection vector (parameter) selects the policy for each register.
+      '''
+    }
+    { struct:  "racl_error_log",
+      type:    "uni",
+      name:    "racl_error",
+      act:     "req",
+      width:   "1"
+      package: "top_racl_pkg",
+      desc:    '''
+        RACL error log information of this module.
+      '''
+    }
+  ]
+  regwidth: "32",
+  param_list: [
+    { name: "ByteOrder",
+      desc: '''Byte order to use when transmitting or receiving data.  If ByteOrder = 0,
+               the IP uses a Big-Endian ordering for the bytes in DATA.
+               The most significant byte (MSB) of DATA is transmitted first, and
+               received data is placed in the MSB location of DATA.  If ByteOrder = 1,
+               a Little-Endian ordering is used for these registers, and the LSB of each
+               gets priority for receiving and transmitting data.'''
+      type: "logic",
+      default: "1"
+    },
+    { name: "NumCS",
+      desc: "The number of active-low chip select (cs_n) lines to create.",
+      type: "int",
+      default: "1"
+      local: "true",
+      expose: "true",
+    },
+    { name: "TxDepth",
+      desc: "The size of the Tx FIFO (in words)",
+      type: "int",
+      default: "72"
+    },
+    { name: "RxDepth",
+      desc: "The size of the Rx FIFO (in words)",
+      type: "int",
+      default: "64"
+    },
+    { name: "CmdDepth",
+      desc: "The size of the Cmd FIFO (one segment descriptor per entry)",
+      type: "int",
+      default: "4"
+    }
+  ],
+  available_output_list: [
+    { name:  "sck"
+      desc:  "SPI Clock"
+    },
+    { name:  "csb"
+      desc:  '''Chip Select# (One hot, active low).  The size of this port should match NumCS.'''
+      width: "1"
+    }
+  ],
+  available_inout_list: [
+    { name:  "sd",
+      desc:  "SPI data bus",
+      width: "4"
+    },
+  ],
+  interrupt_list: [
+    { name: "error",
+      desc: '''Error-related interrupts, see !!ERROR_ENABLE register for more
+               information.'''
+    },
+    { name: "spi_event",
+      type: "status",
+      desc: '''Event-related interrupts, see !!EVENT_ENABLE register for more
+               information.'''
+    }
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  features: [
+    { name: "SPIHOST.USECASE.SERIALNORFLASH",
+      desc: '''
+        The SPI host block can talk to serial NOR flash devices.
+      '''
+    },
+    { name: "SPIHOST.USECASE.PASSTHROUGH",
+      desc: '''
+        The SPI host block can work together with a device to create a pass through.
+      '''
+    },
+    { name: "SPIHOST.RATE.STANDARD",
+      desc: '''
+        Host can operate in standard SPI data rate.
+      '''
+    },
+    { name: "SPIHOST.RATE.DUAL",
+      desc: '''
+        Host can operate in dual SPI data rate.
+      '''
+    },
+    { name: "SPIHOST.RATE.QUAD",
+      desc: '''
+        Host can operate in quad SPI data rate.
+      '''
+    },
+    { name: "SPIHOST.CONFIG.CPOL",
+      desc: '''
+        The polarity of the SPI can be configured.
+      '''
+    },
+    { name: "SPIHOST.CONFIG.CLOCKDIV",
+      desc: '''
+        The clock divider in the SPI host can be configured.
+      '''
+    },
+    { name: "SPIHOST.EVENT.WATERMARK",
+      desc: '''
+        The block can be configured to raise an event on watermarks for transmit and receive queues.
+      '''
+    },
+    { name: "SPIHOST.EVENT.FULL",
+      desc: '''
+        The block can be configured to raise an event when the receive queue is full.
+      '''
+    },
+    { name: "SPIHOST.EVENT.EMPTY",
+      desc: '''
+        The block can be configured to raise an event when the transmit queue is empty.
+      '''
+    }
+  ],
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+  ]
+  registers: [
+    { name: "CONTROL",
+      desc: "Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31",
+          name: "SPIEN",
+          desc: '''Enables the SPI host.  On reset, this field is 0, meaning
+                   that no transactions can proceed.'''
+          resval: "0x0"
+        },
+        { bits: "30",
+          name: "SW_RST",
+          desc: '''Clears the internal state (not registers) to the reset state when set to 1,
+                   including the FIFOs, the CDC's, the core state machine and the shift register.
+                   In the current implementation, the CDC FIFOs are drained not reset.
+                   Therefore software must confirm that both FIFO's empty before releasing
+                   the IP from reset.''',
+          resval: "0x0"
+        },
+        { bits: "29",
+          name: "OUTPUT_EN",
+          desc: '''Enable the SPI host output buffers for the sck, csb, and sd lines.  This allows
+                   the SPI_HOST IP to connect to the same bus as other SPI controllers without
+                   interference.''',
+          resval: "0x0"
+        },
+        { bits: "15:8",
+          name: "TX_WATERMARK"
+          desc: '''If !!EVENT_ENABLE.TXWM is set, the IP will send
+                   an interrupt when the depth of the TX FIFO drops below
+                   TX_WATERMARK words (32b each).'''
+          resval: "0"
+        },
+        { bits: "7:0",
+          name: "RX_WATERMARK"
+          desc: '''If !!EVENT_ENABLE.RXWM is set, the IP will send
+                   an interrupt when the depth of the RX FIFO reaches
+                   RX_WATERMARK words (32b each).'''
+          resval: "127"
+        },
+      ]
+    },
+    { name: "STATUS",
+      desc: "Status register",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      fields: [
+        { bits: "31",
+          name: "READY",
+          desc: '''When high, indicates the SPI host is ready to receive
+                   commands. Writing to COMMAND when READY is low is
+                   an error, and will trigger an interrupt.''',
+          resval: "0x0"
+        },
+        { bits: "30",
+          name: "ACTIVE",
+          desc: '''When high, indicates the SPI host is processing a previously
+                   issued command.'''
+          resval: "0x0"
+        },
+        { bits: "29",
+          name: "TXFULL",
+          desc: '''When high, indicates that the transmit data fifo is full.
+                   Any further writes to !!TXDATA will create an error interrupt.
+                '''
+          resval: "0x0"
+        },
+        { bits: "28",
+          name: "TXEMPTY",
+          desc: '''When high, indicates that the transmit data fifo is empty.
+                '''
+          resval: "0x0"
+        },
+        { bits: "27"
+          name: "TXSTALL",
+          desc: '''If high, signifies that an ongoing transaction has stalled
+                   due to lack of data in the TX FIFO''',
+          resval: "0x0"
+        },
+        { bits: "26",
+          name: "TXWM",
+          desc: '''If high, the amount of data in the TX FIFO has fallen below the
+                   level of !!CONTROL.TX_WATERMARK words (32b each).'''
+          resval: "0x0"
+        },
+        { bits: "25",
+          name: "RXFULL",
+          desc: '''When high, indicates that the receive fifo is full.  Any
+                   ongoing transactions will stall until firmware reads some
+                   data from !!RXDATA.'''
+          resval: "0x0"
+        },
+        { bits: "24",
+          name: "RXEMPTY",
+          desc: '''When high, indicates that the receive fifo is empty.
+                   Any reads from RX FIFO will cause an error interrupt.'''
+          resval: "0x0"
+        },
+        { bits: "23",
+          name: "RXSTALL",
+          desc: '''If high, signifies that an ongoing transaction has stalled
+                   due to lack of available space in the RX FIFO''',
+          resval: "0x0"
+        },
+        { bits: "22",
+          name: "BYTEORDER",
+          desc: '''The value of the ByteOrder parameter, provided so that firmware
+                   can confirm proper IP configuration.'''
+        }
+        { bits: "20",
+          name: "RXWM",
+          desc: '''If high, the number of 32-bits in the RX FIFO now exceeds the
+                   !!CONTROL.RX_WATERMARK entries (32b each).'''
+          resval: "0x0"
+        },
+        { bits: "19:16",
+          name: "CMDQD",
+          desc: '''Command queue depth. Indicates how many unread 32-bit words are
+                   currently in the command segment queue.''',
+          resval: "0x0"
+        },
+        { bits: "15:8",
+          name: "RXQD",
+          desc: '''Receive queue depth. Indicates how many unread 32-bit words are
+                   currently in the RX FIFO.  When active, this result may an
+                   underestimate due to synchronization delays.''',
+          resval: "0x0"
+        },
+        { bits: "7:0",
+          name: "TXQD",
+          desc: '''Transmit queue depth.
+                   Indicates how many unsent 32-bit words are currently in the TX FIFO.
+                   When active, this result may be an overestimate due to synchronization delays.
+                ''',
+          resval: "0x0"
+        }
+      ]
+      tags: [// Updated by the hw. Exclude from init and write-checks.
+             "excl:CsrAllTests:CsrExclCheck"]
+
+    },
+    { name: "CONFIGOPTS",
+      desc: '''Configuration options register.
+
+               Contains options for controlling the current peripheral.
+               Firmware needs to configure the options before the transfer.
+            '''
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31",
+          name: "CPOL",
+          desc: '''The polarity of the sck clock signal.  When CPOL is 0,
+                    sck is low when idle, and emits high pulses.   When CPOL
+                    is 1, sck is high when idle, and emits a series of low
+                    pulses.'''
+          resval: "0x0"
+        },
+        { bits: "30",
+          name: "CPHA",
+          desc: '''The phase of the sck clock signal relative to the data. When
+                    CPHA = 0, the data changes on the trailing edge of sck
+                    and is typically sampled on the leading edge.  Conversely
+                    if CPHA = 1 high, data lines change on the leading edge of
+                    sck and are typically sampled on the trailing edge.
+                    CPHA should be chosen to match the phase of the selected
+                    device.  The sampling behavior is modified by the
+                    !!CONFIGOPTS.FULLCYC bit.''',
+          resval: "0x0"
+        },
+        { bits: "29",
+          name: "FULLCYC",
+          desc: '''Full cycle.  Modifies the CPHA sampling behaviour to allow
+                    for longer device logic setup times.  Rather than sampling the SD
+                    bus a half cycle after shifting out data, the data is sampled
+                    a full cycle after shifting data out.  This means that if
+                    CPHA = 0, data is shifted out on the trailing edge, and
+                    sampled a full cycle later.  If CPHA = 1, data is shifted and
+                    sampled with the trailing edge, also separated by a
+                    full cycle.''',
+          resval: 0
+        },
+        { bits: "27:24",
+          name: "CSNLEAD",
+          desc: '''CS_N Leading Time.  Indicates the number of half sck cycles,
+                    CSNLEAD+1, to leave between the falling edge of cs_n and
+                    the first edge of sck.  Setting this register to zero
+                    corresponds to the minimum delay of one-half sck cycle'''
+          resval: 0
+        },
+        { bits: "23:20",
+          name: "CSNTRAIL"
+          desc: '''CS_N Trailing Time.  Indicates the number of half sck cycles,
+                    CSNTRAIL+1, to leave between last edge of sck and the rising
+                    edge of cs_n. Setting this register to zero corresponds
+                    to the minimum delay of one-half sck cycle.'''
+          resval: 0
+        },
+        { bits: "19:16",
+          name: "CSNIDLE"
+          desc: '''Minimum idle time between commands. Indicates the minimum
+                    number of sck half-cycles to hold cs_n high between commands.
+                    Setting this register to zero creates a minimally-wide CS_N-high
+                    pulse of one-half sck cycle.'''
+          resval: 0
+        },
+        { bits: "15:0",
+          name: "CLKDIV",
+          desc: '''Core clock divider.  Slows down subsequent SPI transactions by a
+                    factor of (CLKDIV+1) relative to the core clock frequency.  The
+                    period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`'''
+          resval: 0
+        },
+      ]
+    },
+    { name: "CSID",
+      desc: '''Chip-Select ID
+
+               Controls which device to target with the next command.  This register
+               is passed to the core whenever !!COMMAND is written.  The core then
+               asserts cio_csb_o[!!CSID] during the execution of the command.''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "CSID",
+          desc: "Chip Select ID",
+          resval: "0x0"
+        }
+      ]
+    },
+    { name: "COMMAND",
+      desc: '''Command Register
+
+               Parameters specific to each command segment.  Unlike the !!CONFIGOPTS multi-register,
+               there is only one command register for controlling all attached SPI devices''',
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "24:5",
+          name: "LEN",
+          desc: '''Segment Length.
+
+                   For read or write segments, this field controls the
+                   number of 1-byte bursts to transmit and or receive in
+                   this command segment.  The number of cyles required
+                   to send or received a byte will depend on !!COMMAND.SPEED.
+                   For dummy segments, (!!COMMAND.DIRECTION == 0), this register
+                   controls the number of dummy cycles to issue.
+                   The number of bytes (or dummy cycles) in the segment will be
+                   equal to !!COMMAND.LEN + 1.''',
+          resval: "0x0"
+        },
+        { bits: "4:3",
+          name: "DIRECTION",
+          desc: '''The direction for the following command: "0" = Dummy cycles
+                   (no TX/RX). "1" = Rx only, "2" = Tx only, "3" = Bidirectional
+                   Tx/Rx (Standard SPI mode only).'''
+          resval: "0x0"
+        }
+        { bits: "2:1",
+          name: "SPEED",
+          desc: '''The speed for this command segment: "0" = Standard SPI. "1" = Dual SPI.
+                   "2"=Quad SPI,  "3": RESERVED.''',
+          resval: "0x0"
+        },
+        { bits: "0",
+          name: "CSAAT",
+          desc: '''**C**hip **S**elect **A**ctive **A**fter **T**ransaction.
+                   If !!COMMAND.CSAAT = 0, the chip select line is raised immediately
+                   at the end of the command segment.
+                   If !!COMMAND.CSAAT = 1, the chip select line is left low at the
+                   end of the current transaction segment.
+                   This allows the creation of longer, more complete SPI transactions,
+                   consisting of several separate segments for issuing instructions,
+                   pausing for dummy cycles, and transmitting or receiving data from
+                   the device.''',
+          resval: "0x0"
+        },
+      ],
+      tags: [// Triggers exceptions if registers are improperly configured
+             // Exclude from RW tests
+             "excl:CsrAllTests:CsrExclWrite"]
+    },
+    { window: {
+        name: "RXDATA",
+        items: "1",
+        validbits: "32",
+        desc: '''SPI Receive Data.
+
+                 Reads from this window pull data from the RXFIFO.
+
+                 The serial order of bit transmission
+                 is chosen to match SPI flash devices. Individual bytes
+                 are always transmitted with the most significant bit first.
+                 Only four-byte reads are supported. If ByteOrder = 0,
+                 the first byte received is packed in the MSB of !!RXDATA.
+                 For some processor architectures, this could lead to shuffling
+                 of flash data as compared to how it is written in memory.
+                 In which case, choosing ByteOrder = 1 can reverse the
+                 byte-order of each data read, causing the first byte
+                 received to be packed into the LSB of !!RXDATA. (Though within
+                 each byte the most significant bit is always pulled
+                 from the bus first.)'''
+        swaccess: "ro",
+      }
+    },
+    { window: {
+        name: "TXDATA",
+        items: "1",
+        validbits: "32",
+        byte-write: "true",
+        desc: '''SPI Transmit Data.
+
+                 Data written to this window is placed into the TXFIFO.
+                 Byte-enables are supported for writes.
+
+                 The serial order of bit transmission
+                 is chosen to match SPI flash devices. Individual bytes
+                 are always transmitted with the most significant bit first.
+                 Multi-byte writes are also supported, and if ByteOrder = 0,
+                 the bits of !!TXDATA are transmitted strictly in order of
+                 decreasing signficance (i.e. most signicant bit first).
+                 For some processor architectures, this could lead to shuffling
+                 of flash data as compared to how it is written in memory.
+                 In which case, choosing ByteOrder = 1 can reverse the
+                 byte-order of multi-byte data writes.  (Though within
+                 each byte the most significant bit is always sent first.)'''
+        swaccess: "wo",
+        unusual: "false"
+      }
+    },
+    { name: "ERROR_ENABLE",
+      desc: "Controls which classes of errors raise an interrupt."
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        # Bit 5 (Access Invalid) always triggers an error, so bit 5 is reserved.
+        { bits: "4",
+          name: "CSIDINVAL",
+          desc: '''Invalid CSID: If this bit is set, the block sends an error interrupt whenever
+                   a command is submitted, but CSID exceeds NumCS.''',
+          resval: "0x1"
+        }
+        { bits: "3",
+          name: "CMDINVAL",
+          desc: '''Invalid Command Errors: If this bit is set, the block sends an
+                   error interrupt whenever a command is sent with invalid values for
+                   !!COMMAND.SPEED or !!COMMAND.DIRECTION.''',
+          resval: "0x1"
+        },
+        { bits: "2",
+          name: "UNDERFLOW",
+          desc: '''Underflow Errors: If this bit is set, the block sends an
+                   error interrupt whenever there is a read from !!RXDATA
+                   but the RX FIFO is empty.'''
+          resval: "0x1"
+        },
+        { bits: "1",
+          name: "OVERFLOW",
+          desc: '''Overflow Errors: If this bit is set, the block sends an
+                   error interrupt whenever the TX FIFO overflows.'''
+          resval: "0x1"
+        },
+        { bits: "0",
+          name: "CMDBUSY",
+          desc: '''Command Error: If this bit is set, the block sends an error
+                   interrupt whenever a command is issued while busy (i.e. a 1 is
+                   when !!STATUS.READY is not asserted.)''',
+          resval: "0x1"
+        },
+      ]
+    },
+    { name: "ERROR_STATUS",
+      desc: '''Indicates that any errors that have occurred.
+               When an error
+               occurs, the corresponding bit must be cleared here before
+               issuing any further commands.'''
+      swaccess: "rw1c",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "5",
+          name: "ACCESSINVAL",
+          desc: '''Indicates that TLUL attempted to write to TXDATA with no bytes enabled. Such
+                   'zero byte' writes are not supported.''',
+          resval: "0x0"
+          tags: [// Updated by the hw. Exclude from init and write-checks.
+                 "excl:CsrAllTests:CsrExclCheck"]
+        },
+        { bits: "4",
+          name: "CSIDINVAL",
+          desc: '''Indicates a command was attempted with an invalid value for !!CSID.''',
+          resval: "0x0"
+        },
+        { bits: "3",
+          name: "CMDINVAL",
+          desc: '''Indicates an invalid command segment, meaning either an invalid value of
+                   !!COMMAND.SPEED or a request for bidirectional data transfer at dual or quad
+                   speed''',
+             resval: "0x0"
+        },
+        { bits: "2",
+          name: "UNDERFLOW",
+          desc: '''Indicates that firmware has attempted to read from
+                   !!RXDATA when the RX FIFO is empty.''',
+          resval: "0x0"
+        },
+        { bits: "1",
+          name: "OVERFLOW",
+          desc: '''Indicates that firmware has overflowed the TX FIFO'''
+          resval: "0x0"
+          tags: [// Updated by the hw. Exclude from init and write-checks.
+                 "excl:CsrAllTests:CsrExclCheck"]
+        },
+        { bits: "0",
+          name: "CMDBUSY",
+          desc: '''Indicates a write to !!COMMAND when !!STATUS.READY = 0.
+                   '''
+          resval: "0x0"
+        },
+      ]
+    },
+    { name: "EVENT_ENABLE",
+      desc: "Controls which classes of SPI events raise an interrupt.",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "5",
+          name: "IDLE",
+          desc: '''Assert to send a spi_event interrupt whenever !!STATUS.ACTIVE
+                   goes low''',
+          resval: "0x0"
+        }
+        { bits: "4",
+          name: "READY",
+          desc: '''Assert to send a spi_event interrupt whenever !!STATUS.READY
+                   goes high''',
+          resval: "0x0"
+        },
+        { bits: "3",
+          name: "TXWM",
+          desc: '''Assert to send a spi_event interrupt whenever the number of 32-bit words in
+                   the TX FIFO is less than !!CONTROL.TX_WATERMARK.  To prevent the
+                   reassertion of this interrupt add more data to the TX FIFO, or
+                   reduce !!CONTROL.TX_WATERMARK.''',
+          resval: "0x0"
+        },
+        { bits: "2",
+          name: "RXWM",
+          desc: '''Assert to send a spi_event interrupt whenever the number of 32-bit words in
+                   the RX FIFO is greater than !!CONTROL.RX_WATERMARK. To prevent the
+                   reassertion of this interrupt, read more data from the RX FIFO, or
+                   increase !!CONTROL.RX_WATERMARK.''',
+          resval: "0x0"
+        },
+        { bits: "1",
+          name: "TXEMPTY",
+          desc: '''Assert to send a spi_event interrupt whenever !!STATUS.TXEMPTY
+                   goes high''',
+          resval: "0x0"
+        },
+        { bits: "0",
+          name: "RXFULL",
+          desc: '''Assert to send a spi_event interrupt whenever !!STATUS.RXFULL
+                   goes high''',
+          resval: "0x0"
+        },
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/spim/doc/registers.md b/docs/um/ip/spim/doc/registers.md
new file mode 100644
index 00000000..867a0e15
--- /dev/null
+++ b/docs/um/ip/spim/doc/registers.md
@@ -0,0 +1,459 @@
+## Summary
+
+| Name                                     | Offset   |   Length | Description                                              |
+|:-----------------------------------------|:---------|---------:|:---------------------------------------------------------|
+| spi_host.[`INTR_STATE`](#intr_state)     | 0x0      |        4 | Interrupt State Register                                 |
+| spi_host.[`INTR_ENABLE`](#intr_enable)   | 0x4      |        4 | Interrupt Enable Register                                |
+| spi_host.[`INTR_TEST`](#intr_test)       | 0x8      |        4 | Interrupt Test Register                                  |
+| spi_host.[`ALERT_TEST`](#alert_test)     | 0xc      |        4 | Alert Test Register                                      |
+| spi_host.[`CONTROL`](#control)           | 0x10     |        4 | Control register                                         |
+| spi_host.[`STATUS`](#status)             | 0x14     |        4 | Status register                                          |
+| spi_host.[`CONFIGOPTS`](#configopts)     | 0x18     |        4 | Configuration options register.                          |
+| spi_host.[`CSID`](#csid)                 | 0x1c     |        4 | Chip-Select ID                                           |
+| spi_host.[`COMMAND`](#command)           | 0x20     |        4 | Command Register                                         |
+| spi_host.[`RXDATA`](#rxdata)             | 0x24     |        4 | SPI Receive Data.                                        |
+| spi_host.[`TXDATA`](#txdata)             | 0x28     |        4 | SPI Transmit Data.                                       |
+| spi_host.[`ERROR_ENABLE`](#error_enable) | 0x2c     |        4 | Controls which classes of errors raise an interrupt.     |
+| spi_host.[`ERROR_STATUS`](#error_status) | 0x30     |        4 | Indicates that any errors that have occurred.            |
+| spi_host.[`EVENT_ENABLE`](#event_enable) | 0x34     |        4 | Controls which classes of SPI events raise an interrupt. |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                  |
+|:------:|:------:|:-------:|:----------|:---------------------------------------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                                                     |
+|   1    |   ro   |   0x0   | spi_event | Event-related interrupts, see [`EVENT_ENABLE`](#event_enable) register for more information. |
+|   0    |  rw1c  |   0x0   | error     | Error-related interrupts, see [`ERROR_ENABLE`](#error_enable) register for more information. |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                         |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                            |
+|   1    |   rw   |   0x0   | spi_event | Enable interrupt when [`INTR_STATE.spi_event`](#intr_state) is set. |
+|   0    |   rw   |   0x0   | error     | Enable interrupt when [`INTR_STATE.error`](#intr_state) is set.     |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "spi_event", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------|
+|  31:2  |        |         |           | Reserved                                                     |
+|   1    |   wo   |   0x0   | spi_event | Write 1 to force [`INTR_STATE.spi_event`](#intr_state) to 1. |
+|   0    |   wo   |   0x0   | error     | Write 1 to force [`INTR_STATE.error`](#intr_state) to 1.     |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CONTROL
+Control register
+- Offset: `0x10`
+- Reset default: `0x7f`
+- Reset mask: `0xe000ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX_WATERMARK", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TX_WATERMARK", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 13}, {"name": "OUTPUT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SW_RST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SPIEN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                   |
+|:------:|:------:|:-------:|:---------------------------------------|
+|   31   |   rw   |   0x0   | [SPIEN](#control--spien)               |
+|   30   |   rw   |   0x0   | [SW_RST](#control--sw_rst)             |
+|   29   |   rw   |   0x0   | [OUTPUT_EN](#control--output_en)       |
+| 28:16  |        |         | Reserved                               |
+|  15:8  |   rw   |   0x0   | [TX_WATERMARK](#control--tx_watermark) |
+|  7:0   |   rw   |  0x7f   | [RX_WATERMARK](#control--rx_watermark) |
+
+### CONTROL . SPIEN
+Enables the SPI host.  On reset, this field is 0, meaning
+   that no transactions can proceed.
+
+### CONTROL . SW_RST
+Clears the internal state (not registers) to the reset state when set to 1,
+   including the FIFOs, the CDC's, the core state machine and the shift register.
+   In the current implementation, the CDC FIFOs are drained not reset.
+   Therefore software must confirm that both FIFO's empty before releasing
+   the IP from reset.
+
+### CONTROL . OUTPUT_EN
+Enable the SPI host output buffers for the sck, csb, and sd lines.  This allows
+   the SPI_HOST IP to connect to the same bus as other SPI controllers without
+   interference.
+
+### CONTROL . TX_WATERMARK
+If [`EVENT_ENABLE.TXWM`](#event_enable) is set, the IP will send
+   an interrupt when the depth of the TX FIFO drops below
+   TX_WATERMARK words (32b each).
+
+### CONTROL . RX_WATERMARK
+If [`EVENT_ENABLE.RXWM`](#event_enable) is set, the IP will send
+   an interrupt when the depth of the RX FIFO reaches
+   RX_WATERMARK words (32b each).
+
+## STATUS
+Status register
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffdfffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXQD", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "RXQD", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CMDQD", "bits": 4, "attr": ["ro"], "rotate": 0}, {"name": "RXWM", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "BYTEORDER", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXSTALL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXWM", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXSTALL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ACTIVE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "READY", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                               |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|   31   |   ro   |   0x0   | READY     | When high, indicates the SPI host is ready to receive commands. Writing to COMMAND when READY is low is an error, and will trigger an interrupt.                          |
+|   30   |   ro   |   0x0   | ACTIVE    | When high, indicates the SPI host is processing a previously issued command.                                                                                              |
+|   29   |   ro   |   0x0   | TXFULL    | When high, indicates that the transmit data fifo is full. Any further writes to [`TXDATA`](#txdata) will create an error interrupt.                                       |
+|   28   |   ro   |   0x0   | TXEMPTY   | When high, indicates that the transmit data fifo is empty.                                                                                                                |
+|   27   |   ro   |   0x0   | TXSTALL   | If high, signifies that an ongoing transaction has stalled due to lack of data in the TX FIFO                                                                             |
+|   26   |   ro   |   0x0   | TXWM      | If high, the amount of data in the TX FIFO has fallen below the level of [`CONTROL.TX_WATERMARK`](#control) words (32b each).                                             |
+|   25   |   ro   |   0x0   | RXFULL    | When high, indicates that the receive fifo is full.  Any ongoing transactions will stall until firmware reads some data from [`RXDATA.`](#rxdata)                         |
+|   24   |   ro   |   0x0   | RXEMPTY   | When high, indicates that the receive fifo is empty. Any reads from RX FIFO will cause an error interrupt.                                                                |
+|   23   |   ro   |   0x0   | RXSTALL   | If high, signifies that an ongoing transaction has stalled due to lack of available space in the RX FIFO                                                                  |
+|   22   |   ro   |   0x0   | BYTEORDER | The value of the ByteOrder parameter, provided so that firmware can confirm proper IP configuration.                                                                      |
+|   21   |        |         |           | Reserved                                                                                                                                                                  |
+|   20   |   ro   |   0x0   | RXWM      | If high, the number of 32-bits in the RX FIFO now exceeds the [`CONTROL.RX_WATERMARK`](#control) entries (32b each).                                                      |
+| 19:16  |   ro   |   0x0   | CMDQD     | Command queue depth. Indicates how many unread 32-bit words are currently in the command segment queue.                                                                   |
+|  15:8  |   ro   |   0x0   | RXQD      | Receive queue depth. Indicates how many unread 32-bit words are currently in the RX FIFO.  When active, this result may an underestimate due to synchronization delays.   |
+|  7:0   |   ro   |   0x0   | TXQD      | Transmit queue depth. Indicates how many unsent 32-bit words are currently in the TX FIFO. When active, this result may be an overestimate due to synchronization delays. |
+
+## CONFIGOPTS
+Configuration options register.
+
+   Contains options for controlling the current peripheral.
+   Firmware needs to configure the options before the transfer.
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xefffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CLKDIV", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "CSNIDLE", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "CSNTRAIL", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "CSNLEAD", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "FULLCYC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CPHA", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CPOL", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                              |
+|:------:|:------:|:-------:|:----------------------------------|
+|   31   |   rw   |   0x0   | [CPOL](#configopts--cpol)         |
+|   30   |   rw   |   0x0   | [CPHA](#configopts--cpha)         |
+|   29   |   rw   |   0x0   | [FULLCYC](#configopts--fullcyc)   |
+|   28   |        |         | Reserved                          |
+| 27:24  |   rw   |   0x0   | [CSNLEAD](#configopts--csnlead)   |
+| 23:20  |   rw   |   0x0   | [CSNTRAIL](#configopts--csntrail) |
+| 19:16  |   rw   |   0x0   | [CSNIDLE](#configopts--csnidle)   |
+|  15:0  |   rw   |   0x0   | [CLKDIV](#configopts--clkdiv)     |
+
+### CONFIGOPTS . CPOL
+The polarity of the sck clock signal.  When CPOL is 0,
+    sck is low when idle, and emits high pulses.   When CPOL
+    is 1, sck is high when idle, and emits a series of low
+    pulses.
+
+### CONFIGOPTS . CPHA
+The phase of the sck clock signal relative to the data. When
+    CPHA = 0, the data changes on the trailing edge of sck
+    and is typically sampled on the leading edge.  Conversely
+    if CPHA = 1 high, data lines change on the leading edge of
+    sck and are typically sampled on the trailing edge.
+    CPHA should be chosen to match the phase of the selected
+    device.  The sampling behavior is modified by the
+    [`CONFIGOPTS.FULLCYC`](#configopts) bit.
+
+### CONFIGOPTS . FULLCYC
+Full cycle.  Modifies the CPHA sampling behaviour to allow
+    for longer device logic setup times.  Rather than sampling the SD
+    bus a half cycle after shifting out data, the data is sampled
+    a full cycle after shifting data out.  This means that if
+    CPHA = 0, data is shifted out on the trailing edge, and
+    sampled a full cycle later.  If CPHA = 1, data is shifted and
+    sampled with the trailing edge, also separated by a
+    full cycle.
+
+### CONFIGOPTS . CSNLEAD
+CS_N Leading Time.  Indicates the number of half sck cycles,
+    CSNLEAD+1, to leave between the falling edge of cs_n and
+    the first edge of sck.  Setting this register to zero
+    corresponds to the minimum delay of one-half sck cycle
+
+### CONFIGOPTS . CSNTRAIL
+CS_N Trailing Time.  Indicates the number of half sck cycles,
+    CSNTRAIL+1, to leave between last edge of sck and the rising
+    edge of cs_n. Setting this register to zero corresponds
+    to the minimum delay of one-half sck cycle.
+
+### CONFIGOPTS . CSNIDLE
+Minimum idle time between commands. Indicates the minimum
+    number of sck half-cycles to hold cs_n high between commands.
+    Setting this register to zero creates a minimally-wide CS_N-high
+    pulse of one-half sck cycle.
+
+### CONFIGOPTS . CLKDIV
+Core clock divider.  Slows down subsequent SPI transactions by a
+    factor of (CLKDIV+1) relative to the core clock frequency.  The
+    period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`
+
+## CSID
+Chip-Select ID
+
+   Controls which device to target with the next command.  This register
+   is passed to the core whenever [`COMMAND`](#command) is written.  The core then
+   asserts cio_csb_o[[`CSID`](#csid)] during the execution of the command.
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CSID", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description    |
+|:------:|:------:|:-------:|:-------|:---------------|
+|  31:0  |   rw   |   0x0   | CSID   | Chip Select ID |
+
+## COMMAND
+Command Register
+
+   Parameters specific to each command segment.  Unlike the [`CONFIGOPTS`](#configopts) multi-register,
+   there is only one command register for controlling all attached SPI devices
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0x1ffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CSAAT", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "SPEED", "bits": 2, "attr": ["wo"], "rotate": -90}, {"name": "DIRECTION", "bits": 2, "attr": ["wo"], "rotate": -90}, {"name": "LEN", "bits": 20, "attr": ["wo"], "rotate": 0}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                             |
+|:------:|:------:|:-------:|:---------------------------------|
+| 31:25  |        |         | Reserved                         |
+|  24:5  |   wo   |   0x0   | [LEN](#command--len)             |
+|  4:3   |   wo   |   0x0   | [DIRECTION](#command--direction) |
+|  2:1   |   wo   |   0x0   | [SPEED](#command--speed)         |
+|   0    |   wo   |   0x0   | [CSAAT](#command--csaat)         |
+
+### COMMAND . LEN
+Segment Length.
+
+   For read or write segments, this field controls the
+   number of 1-byte bursts to transmit and or receive in
+   this command segment.  The number of cyles required
+   to send or received a byte will depend on [`COMMAND.SPEED.`](#command)
+   For dummy segments, ([`COMMAND.DIRECTION`](#command) == 0), this register
+   controls the number of dummy cycles to issue.
+   The number of bytes (or dummy cycles) in the segment will be
+   equal to [`COMMAND.LEN`](#command) + 1.
+
+### COMMAND . DIRECTION
+The direction for the following command: "0" = Dummy cycles
+   (no TX/RX). "1" = Rx only, "2" = Tx only, "3" = Bidirectional
+   Tx/Rx (Standard SPI mode only).
+
+### COMMAND . SPEED
+The speed for this command segment: "0" = Standard SPI. "1" = Dual SPI.
+   "2"=Quad SPI,  "3": RESERVED.
+
+### COMMAND . CSAAT
+**C**hip **S**elect **A**ctive **A**fter **T**ransaction.
+   If [`COMMAND.CSAAT`](#command) = 0, the chip select line is raised immediately
+   at the end of the command segment.
+   If [`COMMAND.CSAAT`](#command) = 1, the chip select line is left low at the
+   end of the current transaction segment.
+   This allows the creation of longer, more complete SPI transactions,
+   consisting of several separate segments for issuing instructions,
+   pausing for dummy cycles, and transmitting or receiving data from
+   the device.
+
+## RXDATA
+SPI Receive Data.
+
+   Reads from this window pull data from the RXFIFO.
+
+   The serial order of bit transmission
+   is chosen to match SPI flash devices. Individual bytes
+   are always transmitted with the most significant bit first.
+   Only four-byte reads are supported. If ByteOrder = 0,
+   the first byte received is packed in the MSB of !!RXDATA.
+   For some processor architectures, this could lead to shuffling
+   of flash data as compared to how it is written in memory.
+   In which case, choosing ByteOrder = 1 can reverse the
+   byte-order of each data read, causing the first byte
+   received to be packed into the LSB of !!RXDATA. (Though within
+   each byte the most significant bit is always pulled
+   from the bus first.)
+
+- Word Aligned Offset Range: `0x24`to`0x24`
+- Size (words): `1`
+- Access: `ro`
+- Byte writes are *not* supported.
+
+## TXDATA
+SPI Transmit Data.
+
+   Data written to this window is placed into the TXFIFO.
+   Byte-enables are supported for writes.
+
+   The serial order of bit transmission
+   is chosen to match SPI flash devices. Individual bytes
+   are always transmitted with the most significant bit first.
+   Multi-byte writes are also supported, and if ByteOrder = 0,
+   the bits of !!TXDATA are transmitted strictly in order of
+   decreasing signficance (i.e. most signicant bit first).
+   For some processor architectures, this could lead to shuffling
+   of flash data as compared to how it is written in memory.
+   In which case, choosing ByteOrder = 1 can reverse the
+   byte-order of multi-byte data writes.  (Though within
+   each byte the most significant bit is always sent first.)
+
+- Word Aligned Offset Range: `0x28`to`0x28`
+- Size (words): `1`
+- Access: `wo`
+- Byte writes are  supported.
+
+## ERROR_ENABLE
+Controls which classes of errors raise an interrupt.
+- Offset: `0x2c`
+- Reset default: `0x1f`
+- Reset mask: `0x1f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CMDBUSY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "OVERFLOW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "UNDERFLOW", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CMDINVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CSIDINVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                                                                                                                                       |
+|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:5  |        |         |           | Reserved                                                                                                                                                                                          |
+|   4    |   rw   |   0x1   | CSIDINVAL | Invalid CSID: If this bit is set, the block sends an error interrupt whenever a command is submitted, but CSID exceeds NumCS.                                                                     |
+|   3    |   rw   |   0x1   | CMDINVAL  | Invalid Command Errors: If this bit is set, the block sends an error interrupt whenever a command is sent with invalid values for [`COMMAND.SPEED`](#command) or [`COMMAND.DIRECTION.`](#command) |
+|   2    |   rw   |   0x1   | UNDERFLOW | Underflow Errors: If this bit is set, the block sends an error interrupt whenever there is a read from [`RXDATA`](#rxdata) but the RX FIFO is empty.                                              |
+|   1    |   rw   |   0x1   | OVERFLOW  | Overflow Errors: If this bit is set, the block sends an error interrupt whenever the TX FIFO overflows.                                                                                           |
+|   0    |   rw   |   0x1   | CMDBUSY   | Command Error: If this bit is set, the block sends an error interrupt whenever a command is issued while busy (i.e. a 1 is when [`STATUS.READY`](#status) is not asserted.)                       |
+
+## ERROR_STATUS
+Indicates that any errors that have occurred.
+   When an error
+   occurs, the corresponding bit must be cleared here before
+   issuing any further commands.
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "CMDBUSY", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "OVERFLOW", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "UNDERFLOW", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CMDINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CSIDINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ACCESSINVAL", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                                                                                                                                             |
+|:------:|:------:|:-------:|:------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:6  |        |         |             | Reserved                                                                                                                                                                |
+|   5    |  rw1c  |   0x0   | ACCESSINVAL | Indicates that TLUL attempted to write to TXDATA with no bytes enabled. Such 'zero byte' writes are not supported.                                                      |
+|   4    |  rw1c  |   0x0   | CSIDINVAL   | Indicates a command was attempted with an invalid value for [`CSID.`](#csid)                                                                                            |
+|   3    |  rw1c  |   0x0   | CMDINVAL    | Indicates an invalid command segment, meaning either an invalid value of [`COMMAND.SPEED`](#command) or a request for bidirectional data transfer at dual or quad speed |
+|   2    |  rw1c  |   0x0   | UNDERFLOW   | Indicates that firmware has attempted to read from [`RXDATA`](#rxdata) when the RX FIFO is empty.                                                                       |
+|   1    |  rw1c  |   0x0   | OVERFLOW    | Indicates that firmware has overflowed the TX FIFO                                                                                                                      |
+|   0    |  rw1c  |   0x0   | CMDBUSY     | Indicates a write to [`COMMAND`](#command) when [`STATUS.READY`](#status) = 0.                                                                                          |
+
+## EVENT_ENABLE
+Controls which classes of SPI events raise an interrupt.
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXFULL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RXWM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXWM", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "READY", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IDLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                              |
+|:------:|:------:|:-------:|:----------------------------------|
+|  31:6  |        |         | Reserved                          |
+|   5    |   rw   |   0x0   | [IDLE](#event_enable--idle)       |
+|   4    |   rw   |   0x0   | [READY](#event_enable--ready)     |
+|   3    |   rw   |   0x0   | [TXWM](#event_enable--txwm)       |
+|   2    |   rw   |   0x0   | [RXWM](#event_enable--rxwm)       |
+|   1    |   rw   |   0x0   | [TXEMPTY](#event_enable--txempty) |
+|   0    |   rw   |   0x0   | [RXFULL](#event_enable--rxfull)   |
+
+### EVENT_ENABLE . IDLE
+Assert to send a spi_event interrupt whenever [`STATUS.ACTIVE`](#status)
+   goes low
+
+### EVENT_ENABLE . READY
+Assert to send a spi_event interrupt whenever [`STATUS.READY`](#status)
+   goes high
+
+### EVENT_ENABLE . TXWM
+Assert to send a spi_event interrupt whenever the number of 32-bit words in
+   the TX FIFO is less than [`CONTROL.TX_WATERMARK.`](#control)  To prevent the
+   reassertion of this interrupt add more data to the TX FIFO, or
+   reduce [`CONTROL.TX_WATERMARK.`](#control)
+
+### EVENT_ENABLE . RXWM
+Assert to send a spi_event interrupt whenever the number of 32-bit words in
+   the RX FIFO is greater than [`CONTROL.RX_WATERMARK.`](#control) To prevent the
+   reassertion of this interrupt, read more data from the RX FIFO, or
+   increase [`CONTROL.RX_WATERMARK.`](#control)
+
+### EVENT_ENABLE . TXEMPTY
+Assert to send a spi_event interrupt whenever [`STATUS.TXEMPTY`](#status)
+   goes high
+
+### EVENT_ENABLE . RXFULL
+Assert to send a spi_event interrupt whenever [`STATUS.RXFULL`](#status)
+   goes high
+
diff --git a/docs/um/ip/tagger/data/tagger_regs.hjson b/docs/um/ip/tagger/data/tagger_regs.hjson
new file mode 100644
index 00000000..4a86051e
--- /dev/null
+++ b/docs/um/ip/tagger/data/tagger_regs.hjson
@@ -0,0 +1,80 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Authors: 
+// Diyou Shen <dishen@student.ethz.ch>
+
+
+
+{
+    name: "tagger_reg",
+    clock_primary: "clk_i",
+    reset_primary: "rst_ni",
+    bus_interfaces: [{
+        protocol: "reg_iface",
+        direction: "device"
+    }],
+    regwidth: "32",
+    registers: [{
+        multireg: {
+            name: "PAT_COMMIT",
+            desc: "Partition configuration commit register",
+            count: "1",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "0",
+                name: "commit",
+                desc: "commit changes of partition configuration",
+                resval: "0"
+            }]
+        }},
+        
+        {
+        multireg: {
+            name: "PAT_ADDR",
+            desc: "Partition address",
+            count: "16",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "31:0",
+                name: "PAT_ADDR",
+                desc: "Single partition configurations: address",
+                resval: "0"
+            }]
+        }},
+        {
+        multireg: {
+            name: "PATID",
+            desc: "Partition ID",
+            count: "3",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "31:0",
+                name: "PATID",
+                desc: "Partition ID (PatID) for each partition, length determined by params",
+                resval: "0"
+            }]
+        }},
+        {
+        multireg: {
+            name: "ADDR_CONF",
+            desc: "Address encoding mode switch register",
+            count: "1",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "31:0",
+                name: "addr_conf",
+                desc: "2 bits configuration for each partition. 2'b00: OFF, 2'b01: TOR, 2'b10: NA4",
+                resval: "0"
+            }]
+        }}  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/tagger/data/tagger_regs_doc.hjson b/docs/um/ip/tagger/data/tagger_regs_doc.hjson
new file mode 100644
index 00000000..2ca3b2a5
--- /dev/null
+++ b/docs/um/ip/tagger/data/tagger_regs_doc.hjson
@@ -0,0 +1,83 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Authors: 
+// Diyou Shen <dishen@student.ethz.ch>
+
+
+
+{
+    name: "tagger_reg",
+    cip_id: "36",
+    version: "0.0.0", //null, commit  b288376
+    clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+    ],
+    bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+    ],
+    regwidth: "32",
+    registers: [{
+	multireg: {
+	    name: "PAT_COMMIT",
+	    desc: "Partition configuration commit register",
+	    count: "1",
+	    cname: "TAGGER",
+	    swaccess: "rw",
+	    hwaccess: "hrw",
+	    fields: [{
+		bits: "0",
+		name: "commit",
+		desc: "commit changes of partition configuration",
+		resval: "0"
+	    }]
+	}},
+
+	{
+	multireg: {
+	    name: "PAT_ADDR",
+	    desc: "Partition address",
+	    count: "16",
+	    cname: "TAGGER",
+	    swaccess: "rw",
+	    hwaccess: "hrw",
+	    fields: [{
+		bits: "31:0",
+		name: "PAT_ADDR",
+		desc: "Single partition configurations: address",
+		resval: "0"
+	    }]
+	}},
+	{
+	multireg: {
+	    name: "PATID",
+	    desc: "Partition ID",
+	    count: "3",
+	    cname: "TAGGER",
+	    swaccess: "rw",
+	    hwaccess: "hrw",
+	    fields: [{
+		bits: "31:0",
+		name: "PATID",
+		desc: "Partition ID (PatID) for each partition, length determined by params",
+		resval: "0"
+	    }]
+	}},
+	{
+	multireg: {
+	    name: "ADDR_CONF",
+	    desc: "Address encoding mode switch register",
+	    count: "1",
+	    cname: "TAGGER",
+	    swaccess: "rw",
+	    hwaccess: "hrw",
+	    fields: [{
+		bits: "31:0",
+		name: "addr_conf",
+		desc: "2 bits configuration for each partition. 2'b00: OFF, 2'b01: TOR, 2'b10: NA4",
+		resval: "0"
+	    }]
+	}}  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/tagger/data/tagger_regs_doc.hjson~ b/docs/um/ip/tagger/data/tagger_regs_doc.hjson~
new file mode 100644
index 00000000..c2356966
--- /dev/null
+++ b/docs/um/ip/tagger/data/tagger_regs_doc.hjson~
@@ -0,0 +1,83 @@
+// Copyright 2018-2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Authors: 
+// Diyou Shen <dishen@student.ethz.ch>
+
+
+
+{
+    name: "tagger_reg",
+    cip_id: "36",
+    version: "0.0.0", // Carfiled_chip-V4.1 2023-11-16
+    clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+    ],
+    bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+    ],
+    regwidth: "32",
+    registers: [{
+        multireg: {
+            name: "PAT_COMMIT",
+            desc: "Partition configuration commit register",
+            count: "1",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "0",
+                name: "commit",
+                desc: "commit changes of partition configuration",
+                resval: "0"
+            }]
+        }},
+        
+        {
+        multireg: {
+            name: "PAT_ADDR",
+            desc: "Partition address",
+            count: "16",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "31:0",
+                name: "PAT_ADDR",
+                desc: "Single partition configurations: address",
+                resval: "0"
+            }]
+        }},
+        {
+        multireg: {
+            name: "PATID",
+            desc: "Partition ID",
+            count: "3",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "31:0",
+                name: "PATID",
+                desc: "Partition ID (PatID) for each partition, length determined by params",
+                resval: "0"
+            }]
+        }},
+        {
+        multireg: {
+            name: "ADDR_CONF",
+            desc: "Address encoding mode switch register",
+            count: "1",
+            cname: "TAGGER",
+            swaccess: "rw",
+            hwaccess: "hrw",
+            fields: [{
+                bits: "31:0",
+                name: "addr_conf",
+                desc: "2 bits configuration for each partition. 2'b00: OFF, 2'b01: TOR, 2'b10: NA4",
+                resval: "0"
+            }]
+        }}  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/tagger/doc/registers.md b/docs/um/ip/tagger/doc/registers.md
new file mode 100644
index 00000000..9277edab
--- /dev/null
+++ b/docs/um/ip/tagger/doc/registers.md
@@ -0,0 +1,126 @@
+## Summary
+
+| Name                                   | Offset   |   Length | Description                             |
+|:---------------------------------------|:---------|---------:|:----------------------------------------|
+| tagger_reg.[`PAT_COMMIT`](#PAT_COMMIT) | 0x0      |        4 | Partition configuration commit register |
+| tagger_reg.[`PAT_ADDR_0`](#pat_addr)   | 0x4      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_1`](#pat_addr)   | 0x8      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_2`](#pat_addr)   | 0xc      |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_3`](#pat_addr)   | 0x10     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_4`](#pat_addr)   | 0x14     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_5`](#pat_addr)   | 0x18     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_6`](#pat_addr)   | 0x1c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_7`](#pat_addr)   | 0x20     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_8`](#pat_addr)   | 0x24     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_9`](#pat_addr)   | 0x28     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_10`](#pat_addr)  | 0x2c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_11`](#pat_addr)  | 0x30     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_12`](#pat_addr)  | 0x34     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_13`](#pat_addr)  | 0x38     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_14`](#pat_addr)  | 0x3c     |        4 | Partition address                       |
+| tagger_reg.[`PAT_ADDR_15`](#pat_addr)  | 0x40     |        4 | Partition address                       |
+| tagger_reg.[`PATID_0`](#patid)         | 0x44     |        4 | Partition ID                            |
+| tagger_reg.[`PATID_1`](#patid)         | 0x48     |        4 | Partition ID                            |
+| tagger_reg.[`PATID_2`](#patid)         | 0x4c     |        4 | Partition ID                            |
+| tagger_reg.[`ADDR_CONF`](#addr_conf)   | 0x50     |        4 | Address encoding mode switch register   |
+
+## PAT_COMMIT
+Partition configuration commit register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "commit_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                               |
+|:------:|:------:|:-------:|:---------|:------------------------------------------|
+|  31:1  |        |         |          | Reserved                                  |
+|   0    |   rw   |   0x0   | commit_0 | commit changes of partition configuration |
+
+## PAT_ADDR
+Partition address
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name        | Offset   |
+|:------------|:---------|
+| PAT_ADDR_0  | 0x4      |
+| PAT_ADDR_1  | 0x8      |
+| PAT_ADDR_2  | 0xc      |
+| PAT_ADDR_3  | 0x10     |
+| PAT_ADDR_4  | 0x14     |
+| PAT_ADDR_5  | 0x18     |
+| PAT_ADDR_6  | 0x1c     |
+| PAT_ADDR_7  | 0x20     |
+| PAT_ADDR_8  | 0x24     |
+| PAT_ADDR_9  | 0x28     |
+| PAT_ADDR_10 | 0x2c     |
+| PAT_ADDR_11 | 0x30     |
+| PAT_ADDR_12 | 0x34     |
+| PAT_ADDR_13 | 0x38     |
+| PAT_ADDR_14 | 0x3c     |
+| PAT_ADDR_15 | 0x40     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PAT_ADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                              |
+|:------:|:------:|:-------:|:---------|:-----------------------------------------|
+|  31:0  |   rw   |   0x0   | PAT_ADDR | Single partition configurations: address |
+
+## PATID
+Partition ID
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name    | Offset   |
+|:--------|:---------|
+| PATID_0 | 0x44     |
+| PATID_1 | 0x48     |
+| PATID_2 | 0x4c     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "PATID", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                          |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | PATID  | Partition ID (PatID) for each partition, length determined by params |
+
+## ADDR_CONF
+Address encoding mode switch register
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Instances
+
+| Name      | Offset   |
+|:----------|:---------|
+| ADDR_CONF | 0x50     |
+
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "addr_conf", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                                 |
+|:------:|:------:|:-------:|:----------|:----------------------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | addr_conf | 2 bits configuration for each partition. 2'b00: OFF, 2'b01: TOR, 2'b10: NA4 |
+
diff --git a/docs/um/ip/uart/data/uart_ot.hjson b/docs/um/ip/uart/data/uart_ot.hjson
new file mode 100644
index 00000000..3b88b5a9
--- /dev/null
+++ b/docs/um/ip/uart/data/uart_ot.hjson
@@ -0,0 +1,476 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name:               "uart",
+  human_name:         "UART",
+  one_line_desc:      "Full duplex serial communication interface, supports bit rates of up to 1 Mbit/s",
+  one_paragraph_desc: '''
+  Universal Asynchronous Receiver/Transmitter (UART) provides industry standard serial communication with external devices via two wires at a programmable baud rate.
+  Its full duplex design supports simultaneous transmission and reception, and flow control may be achieved using software handshaking if required.
+  To reduce software load, UART includes hardware FIFOs and supports interrupt generation when the FIFO level reaches software-programmable thresholds.
+  For compatibility with a variety of different targets and applications, the baud rate is software programmable and bit rates of up to 1 Mbit/s are supported.
+  The data format is restricted to 8 bits, reducing the complexity and cost, with optional parity for robustness against transmission errors.
+  '''
+  // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
+  cip_id:             "30",
+  design_spec:        "../doc",
+  dv_doc:             "../doc/dv",
+  hw_checklist:       "../doc/checklist",
+  sw_checklist:       "/sw/device/lib/dif/dif_uart",
+  revisions: [
+  {
+    version:            "1.0.0",
+    life_stage:         "L2",
+    design_stage:       "D3",
+    verification_stage: "V3",
+    commit_id:          "4166794b902cc72b4cfdfacca0869ffc56e6b42a",
+    notes:              ""
+  }
+  {
+    version:            "1.1.0",
+    life_stage:         "L1",
+    design_stage:       "D3",
+    verification_stage: "V2S",
+    commit_id:          "486ba480c12f8e71cfb0d41cdf8df1e51a1f26ab"
+    dif_stage:          "S2",
+    notes:              ""
+  }
+  {
+    version:            "2.1.0",
+    life_stage:         "L1",
+    design_stage:       "D2S",
+    verification_stage: "V2S",
+    commit_id:          "ffab8da7381c66b3d2e2b78a382a9f6937e5482e",
+    dif_stage:          "S2",
+    notes:              ""
+  }
+  ]
+  clocking: [{clock: "clk_i", reset: "rst_ni"}],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device", racl_support: true }
+  ],
+  available_input_list: [
+    { name: "rx", desc: "Serial receive bit" }
+  ],
+  available_output_list: [
+    { name: "tx", desc: "Serial transmit bit" }
+  ],
+  interrupt_list: [
+    { name:    "tx_watermark",
+      type:    "status",
+      default: "1",
+      desc:    "raised if the transmit FIFO is past the high-water mark."}
+    { name: "rx_watermark",
+      type: "status",
+      desc: "raised if the receive FIFO is past the high-water mark."}
+    { name: "tx_done",
+      desc: "raised if the transmit FIFO has emptied and no transmit is ongoing."}
+    { name: "rx_overflow",
+      desc: "raised if the receive FIFO has overflowed."}
+    { name: "rx_frame_err",
+      desc: "raised if a framing error has been detected on receive."}
+    { name: "rx_break_err",
+      desc: "raised if break condition has been detected on receive."}
+    { name: "rx_timeout"
+      desc: '''
+          raised if RX FIFO has characters remaining in the FIFO without being
+          retrieved for the programmed time period.
+          '''
+    }
+    { name: "rx_parity_err"
+      desc: "raised if the receiver has detected a parity error."}
+    { name:   "tx_empty",
+      type:   "status",
+      default: "1",
+      desc:    "raised if the transmit FIFO is empty."}
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  features: [
+    { name: "UART.PARITY",
+      desc: '''
+        The UART can be configured to so that it sends (or expects) a parity bit after each 8 data bits.
+        In receive mode, the UART sends the rx_parity_err interrupt if it receives a parity bit of the wrong polarity.
+        The parity mode is configurable (ensuring words are even or odd).
+      '''
+    },
+    { name: "UART.LINE_LOOPBACK",
+      desc: '''
+        The UART can be configured so that incoming bits are sent on the TX side.
+      '''
+    },
+    { name: "UART.SYSTEM_LOOPBACK",
+      desc: '''
+        The UART can be configured so that outgoing bits are registered as having been received on the RX side.
+      '''
+    },
+    { name: "UART.BAUD_RATE_CONTROL",
+      desc: '''
+        The UART baud rate can be configured.
+      '''
+    },
+    { name: "UART.LINE_BREAK",
+      desc: '''
+        The UART can detect line breaks (defined as the RX pin being continuously low for several bit-times).
+        The threshold for number of low bits to signal a line break is configurable.
+      '''
+    },
+    { name: "UART.FIFO_INTERRUPTS",
+      desc: '''
+        The UART can be configured to send an "watermark" interrupt when RX or TX FIFO is nearly full/empty, respectively.
+        It sends an rx_overflow interrupt if it sees an extra character when the RX FIFO is full.
+      '''
+    },
+  ]
+  inter_signal_list: [
+    { struct: "logic"
+      type:   "uni"
+      name:   "lsio_trigger"
+      desc: '''
+            Self-clearing status trigger for the DMA.
+            Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour.
+      '''
+      act:    "req"
+    }
+    { struct:  "racl_policy_vec",
+      type:    "uni",
+      name:    "racl_policies",
+      act:     "rcv",
+      package: "top_racl_pkg",
+      desc:    '''
+        Incoming RACL policy vector from a racl_ctrl instance.
+        The policy selection vector (parameter) selects the policy for each register.
+      '''
+    }
+    { struct:  "racl_error_log",
+      type:    "uni",
+      name:    "racl_error",
+      act:     "req",
+      width:   "1"
+      package: "top_racl_pkg",
+      desc:    '''
+        RACL error log information of this module.
+      '''
+    }
+  ]
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+  ]
+  param_list: [
+    // Note that the watermark CSRs further below need to be adjusted when
+    // making changes to these FIFO depths. The RTL and DV are written in
+    // a parametric way and will adjust automatically.
+    { name:    "RxFifoDepth",
+      desc:    "Number of bytes in the RX FIFO.",
+      type:    "int",
+      default: "64",
+      local:   "true",
+    }
+    { name:    "TxFifoDepth",
+      desc:    "Number of bytes in the TX FIFO.",
+      type:    "int",
+      default: "32",
+      local:   "true",
+    }
+  ]
+  regwidth: "32",
+  registers: [
+    { name: "CTRL",
+      desc: "UART control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "TX",
+          desc: "TX enable"
+        }
+        { bits: "1",
+          name: "RX",
+          desc: "RX enable"
+          tags: [// enable RX in other tests only. In top-level, RX pin is driven by 0 when it's
+                 // not selected at pinmux, which causes RX related status updated to non-default
+                 // value
+            "excl:CsrAllTests:CsrExclWrite"]
+        }
+        { bits: "2",
+          name: "NF",
+          desc: '''RX noise filter enable.
+                If the noise filter is enabled, RX line goes through the 3-tap
+                repetition code. It ignores single IP clock period noise.
+          '''
+        }
+        { bits: "4",
+          name: "SLPBK",
+          desc: '''System loopback enable.
+
+                If this bit is turned on, any outgoing bits to TX are received through RX.
+                See Block Diagram. Note that the TX line goes 1 if System loopback is enabled.
+                '''
+        }
+        { bits: "5",
+          name: "LLPBK",
+          desc: '''Line loopback enable.
+
+                If this bit is turned on, incoming bits are forwarded to TX for testing purpose.
+                See Block Diagram. Note that the internal design sees RX value as 1 always if line
+                loopback is enabled.
+                '''
+        }
+        { bits: "6",
+          name: "PARITY_EN",
+          desc: "If true, parity is enabled in both RX and TX directions."
+        }
+        { bits: "7",
+          name: "PARITY_ODD",
+          desc: "If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even."
+        }
+        { bits: "9:8",
+          name: "RXBLVL",
+          desc: '''
+                Trigger level for RX break detection. Sets the number of character
+                times the line must be low to detect a break.
+                ''',
+          enum: [
+            { value: "0",
+              name: "break2",
+              desc: "2 characters"
+            },
+            { value: "1",
+              name: "break4",
+              desc: "4 characters"
+            },
+            { value: "2",
+              name: "break8",
+              desc: "8 characters"
+            },
+            { value: "3",
+              name: "break16",
+              desc: "16 characters"
+            }
+          ]
+        }
+        { bits: "31:16",
+          name: "NCO",
+          desc: "BAUD clock rate control."
+        }
+      ]
+    },
+    { name:     "STATUS"
+      desc:     "UART live status register"
+      swaccess: "ro"
+      hwaccess: "hrw"
+      hwext:    "true"
+      hwre:     "true"
+      fields: [
+        { bits: "0"
+          name: "TXFULL"
+          desc: "TX buffer is full"
+        }
+        { bits: "1"
+          name: "RXFULL"
+          desc: "RX buffer is full"
+        }
+        { bits: "2"
+          name: "TXEMPTY"
+          desc: "TX FIFO is empty"
+          resval: "1"
+        }
+        { bits: "3"
+          name: "TXIDLE"
+          desc: "TX FIFO is empty and all bits have been transmitted"
+          resval: "1"
+        }
+        { bits: "4"
+          name: "RXIDLE"
+          desc: "RX is idle"
+          resval: "1",
+        }
+        { bits: "5"
+          name: "RXEMPTY"
+          desc: "RX FIFO is empty"
+          resval: "1"
+        }
+      ]
+    }
+    { name: "RDATA",
+      desc: "UART read data",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "7:0" }
+      ]
+      tags: [// read wdata when fifo is empty, dut may return unknown data
+             "excl:CsrAllTests:CsrExclCheck"]
+    }
+    { name: "WDATA",
+      desc: "UART write data",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwqe: "true",
+      fields: [
+        { bits: "7:0" }
+      ]
+      tags: [// don't write to wdata - it affects several other csrs
+             "excl:CsrNonInitTests:CsrExclWrite"]
+    }
+    { name: "FIFO_CTRL",
+      desc: "UART FIFO control register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      hwqe:     "true",
+      fields: [
+        { bits: "0",
+          swaccess: "wo",
+          hwaccess: "hro",
+          name: "RXRST",
+          desc: "RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0"
+        }
+        { bits: "1",
+          swaccess: "wo",
+          hwaccess: "hro",
+          name: "TXRST",
+          desc: "TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0"
+        }
+        { bits: "4:2",
+          name: "RXILVL",
+          desc: '''Trigger level for RX interrupts. If the FIFO depth is greater than or equal to
+                the setting, it raises rx_watermark interrupt.
+                ''',
+          enum: [
+            { value: "0",
+              name: "rxlvl1",
+              desc: "1 character"
+            },
+            { value: "1",
+              name: "rxlvl2",
+              desc: "2 characters"
+            },
+            { value: "2",
+              name: "rxlvl4",
+              desc: "4 characters"
+            },
+            { value: "3",
+              name: "rxlvl8",
+              desc: "8 characters"
+            },
+            { value: "4",
+              name: "rxlvl16",
+              desc: "16 characters"
+            },
+            { value: "5",
+              name: "rxlvl32",
+              desc: "32 characters"
+            },
+            { value: "6",
+              name: "rxlvl62",
+              desc: "62 characters"
+            },
+          ]
+        }
+        { bits: "7:5",
+          name: "TXILVL",
+          desc: '''Trigger level for TX interrupts. If the FIFO depth is less than the setting, it
+                raises tx_watermark interrupt.
+                ''',
+          enum: [
+            { value: "0",
+              name: "txlvl1",
+              desc: "1 character"
+            },
+            { value: "1",
+              name: "txlvl2",
+              desc: "2 characters"
+            },
+            { value: "2",
+              name: "txlvl4",
+              desc: "4 characters"
+            },
+            { value: "3",
+              name: "txlvl8",
+              desc: "8 characters"
+            },
+            { value: "4",
+              name: "txlvl16",
+              desc: "16 characters"
+            },
+          ]
+        }
+      ]
+    }
+    { name: "FIFO_STATUS",
+      desc: "UART FIFO status register",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "7:0",
+          name: "TXLVL",
+          desc: "Current fill level of TX fifo"
+        }
+        { bits: "23:16",
+          name: "RXLVL",
+          desc: "Current fill level of RX fifo"
+        }
+      ]
+    }
+    { name: "OVRD",
+      desc: "TX pin override control. Gives direct SW control over TX pin state",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0",
+          name: "TXEN",
+          desc: "Enable TX pin override control",
+          tags: [// writes to ovrd.txen causes tx output to be forced to ovrd.txval
+                 // causing protocol violation
+                 "excl:CsrAllTests:CsrExclWrite"]
+        }
+        { bits: "1",
+          name: "TXVAL",
+          desc: "Write to set the value of the TX pin"
+        }
+      ]
+    }
+    { name: "VAL",
+      desc: "UART oversampled values",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext:    "true",
+      fields: [
+        { bits: "15:0",
+          name: "RX",
+          desc: '''
+                Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15.
+                '''
+          tags: [// UART oversampled values are updated by design according to setting and pin RX
+                 "excl:CsrNonInitTests:CsrExclCheck"]
+        }
+      ]
+    }
+    { name: "TIMEOUT_CTRL",
+      desc: "UART RX timeout control",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "23:0",
+          name: "VAL",
+          desc: "RX timeout value in UART bit times"
+        }
+        { bits: "31",
+          name: "EN",
+          desc: "Enable RX timeout feature"
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/uart/doc/registers.md b/docs/um/ip/uart/doc/registers.md
new file mode 100644
index 00000000..2c3d8307
--- /dev/null
+++ b/docs/um/ip/uart/doc/registers.md
@@ -0,0 +1,365 @@
+## Summary
+
+| Name                                 | Offset   |   Length | Description                                                        |
+|:-------------------------------------|:---------|---------:|:-------------------------------------------------------------------|
+| uart.[`INTR_STATE`](#intr_state)     | 0x0      |        4 | Interrupt State Register                                           |
+| uart.[`INTR_ENABLE`](#intr_enable)   | 0x4      |        4 | Interrupt Enable Register                                          |
+| uart.[`INTR_TEST`](#intr_test)       | 0x8      |        4 | Interrupt Test Register                                            |
+| uart.[`ALERT_TEST`](#alert_test)     | 0xc      |        4 | Alert Test Register                                                |
+| uart.[`CTRL`](#ctrl)                 | 0x10     |        4 | UART control register                                              |
+| uart.[`STATUS`](#status)             | 0x14     |        4 | UART live status register                                          |
+| uart.[`RDATA`](#rdata)               | 0x18     |        4 | UART read data                                                     |
+| uart.[`WDATA`](#wdata)               | 0x1c     |        4 | UART write data                                                    |
+| uart.[`FIFO_CTRL`](#fifo_ctrl)       | 0x20     |        4 | UART FIFO control register                                         |
+| uart.[`FIFO_STATUS`](#fifo_status)   | 0x24     |        4 | UART FIFO status register                                          |
+| uart.[`OVRD`](#ovrd)                 | 0x28     |        4 | TX pin override control. Gives direct SW control over TX pin state |
+| uart.[`VAL`](#val)                   | 0x2c     |        4 | UART oversampled values                                            |
+| uart.[`TIMEOUT_CTRL`](#timeout_ctrl) | 0x30     |        4 | UART RX timeout control                                            |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x0`
+- Reset default: `0x101`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                                                                    |
+|:------:|:------:|:-------:|:--------------|:---------------------------------------------------------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                                                                       |
+|   8    |   ro   |   0x1   | tx_empty      | raised if the transmit FIFO is empty.                                                                          |
+|   7    |  rw1c  |   0x0   | rx_parity_err | raised if the receiver has detected a parity error.                                                            |
+|   6    |  rw1c  |   0x0   | rx_timeout    | raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period. |
+|   5    |  rw1c  |   0x0   | rx_break_err  | raised if break condition has been detected on receive.                                                        |
+|   4    |  rw1c  |   0x0   | rx_frame_err  | raised if a framing error has been detected on receive.                                                        |
+|   3    |  rw1c  |   0x0   | rx_overflow   | raised if the receive FIFO has overflowed.                                                                     |
+|   2    |  rw1c  |   0x0   | tx_done       | raised if the transmit FIFO has emptied and no transmit is ongoing.                                            |
+|   1    |   ro   |   0x0   | rx_watermark  | raised if the receive FIFO is past the high-water mark.                                                        |
+|   0    |   ro   |   0x1   | tx_watermark  | raised if the transmit FIFO is past the high-water mark.                                                       |
+
+## INTR_ENABLE
+Interrupt Enable Register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                             |
+|:------:|:------:|:-------:|:--------------|:------------------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                                |
+|   8    |   rw   |   0x0   | tx_empty      | Enable interrupt when [`INTR_STATE.tx_empty`](#intr_state) is set.      |
+|   7    |   rw   |   0x0   | rx_parity_err | Enable interrupt when [`INTR_STATE.rx_parity_err`](#intr_state) is set. |
+|   6    |   rw   |   0x0   | rx_timeout    | Enable interrupt when [`INTR_STATE.rx_timeout`](#intr_state) is set.    |
+|   5    |   rw   |   0x0   | rx_break_err  | Enable interrupt when [`INTR_STATE.rx_break_err`](#intr_state) is set.  |
+|   4    |   rw   |   0x0   | rx_frame_err  | Enable interrupt when [`INTR_STATE.rx_frame_err`](#intr_state) is set.  |
+|   3    |   rw   |   0x0   | rx_overflow   | Enable interrupt when [`INTR_STATE.rx_overflow`](#intr_state) is set.   |
+|   2    |   rw   |   0x0   | tx_done       | Enable interrupt when [`INTR_STATE.tx_done`](#intr_state) is set.       |
+|   1    |   rw   |   0x0   | rx_watermark  | Enable interrupt when [`INTR_STATE.rx_watermark`](#intr_state) is set.  |
+|   0    |   rw   |   0x0   | tx_watermark  | Enable interrupt when [`INTR_STATE.tx_watermark`](#intr_state) is set.  |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0x1ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "tx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_watermark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_overflow", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_frame_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_break_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_timeout", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rx_parity_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "tx_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description                                                      |
+|:------:|:------:|:-------:|:--------------|:-----------------------------------------------------------------|
+|  31:9  |        |         |               | Reserved                                                         |
+|   8    |   wo   |   0x0   | tx_empty      | Write 1 to force [`INTR_STATE.tx_empty`](#intr_state) to 1.      |
+|   7    |   wo   |   0x0   | rx_parity_err | Write 1 to force [`INTR_STATE.rx_parity_err`](#intr_state) to 1. |
+|   6    |   wo   |   0x0   | rx_timeout    | Write 1 to force [`INTR_STATE.rx_timeout`](#intr_state) to 1.    |
+|   5    |   wo   |   0x0   | rx_break_err  | Write 1 to force [`INTR_STATE.rx_break_err`](#intr_state) to 1.  |
+|   4    |   wo   |   0x0   | rx_frame_err  | Write 1 to force [`INTR_STATE.rx_frame_err`](#intr_state) to 1.  |
+|   3    |   wo   |   0x0   | rx_overflow   | Write 1 to force [`INTR_STATE.rx_overflow`](#intr_state) to 1.   |
+|   2    |   wo   |   0x0   | tx_done       | Write 1 to force [`INTR_STATE.tx_done`](#intr_state) to 1.       |
+|   1    |   wo   |   0x0   | rx_watermark  | Write 1 to force [`INTR_STATE.rx_watermark`](#intr_state) to 1.  |
+|   0    |   wo   |   0x0   | tx_watermark  | Write 1 to force [`INTR_STATE.tx_watermark`](#intr_state) to 1.  |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## CTRL
+UART control register
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0xffff03f7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RX", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NF", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "SLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "LLPBK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PARITY_ODD", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RXBLVL", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "NCO", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                            |
+|:------:|:------:|:-------:|:--------------------------------|
+| 31:16  |   rw   |   0x0   | [NCO](#ctrl--nco)               |
+| 15:10  |        |         | Reserved                        |
+|  9:8   |   rw   |   0x0   | [RXBLVL](#ctrl--rxblvl)         |
+|   7    |   rw   |   0x0   | [PARITY_ODD](#ctrl--parity_odd) |
+|   6    |   rw   |   0x0   | [PARITY_EN](#ctrl--parity_en)   |
+|   5    |   rw   |   0x0   | [LLPBK](#ctrl--llpbk)           |
+|   4    |   rw   |   0x0   | [SLPBK](#ctrl--slpbk)           |
+|   3    |        |         | Reserved                        |
+|   2    |   rw   |   0x0   | [NF](#ctrl--nf)                 |
+|   1    |   rw   |   0x0   | [RX](#ctrl--rx)                 |
+|   0    |   rw   |   0x0   | [TX](#ctrl--tx)                 |
+
+### CTRL . NCO
+BAUD clock rate control.
+
+### CTRL . RXBLVL
+Trigger level for RX break detection. Sets the number of character
+times the line must be low to detect a break.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | break2  | 2 characters  |
+| 0x1     | break4  | 4 characters  |
+| 0x2     | break8  | 8 characters  |
+| 0x3     | break16 | 16 characters |
+
+
+### CTRL . PARITY_ODD
+If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even.
+
+### CTRL . PARITY_EN
+If true, parity is enabled in both RX and TX directions.
+
+### CTRL . LLPBK
+Line loopback enable.
+
+If this bit is turned on, incoming bits are forwarded to TX for testing purpose.
+See Block Diagram. Note that the internal design sees RX value as 1 always if line
+loopback is enabled.
+
+### CTRL . SLPBK
+System loopback enable.
+
+If this bit is turned on, any outgoing bits to TX are received through RX.
+See Block Diagram. Note that the TX line goes 1 if System loopback is enabled.
+
+### CTRL . NF
+RX noise filter enable.
+If the noise filter is enabled, RX line goes through the 3-tap
+repetition code. It ignores single IP clock period noise.
+
+### CTRL . RX
+RX enable
+
+### CTRL . TX
+TX enable
+
+## STATUS
+UART live status register
+- Offset: `0x14`
+- Reset default: `0x3c`
+- Reset mask: `0x3f`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXFULL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXIDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RXEMPTY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description                                         |
+|:------:|:------:|:-------:|:--------|:----------------------------------------------------|
+|  31:6  |        |         |         | Reserved                                            |
+|   5    |   ro   |   0x1   | RXEMPTY | RX FIFO is empty                                    |
+|   4    |   ro   |   0x1   | RXIDLE  | RX is idle                                          |
+|   3    |   ro   |   0x1   | TXIDLE  | TX FIFO is empty and all bits have been transmitted |
+|   2    |   ro   |   0x1   | TXEMPTY | TX FIFO is empty                                    |
+|   1    |   ro   |    x    | RXFULL  | RX buffer is full                                   |
+|   0    |   ro   |    x    | TXFULL  | TX buffer is full                                   |
+
+## RDATA
+UART read data
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RDATA", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   ro   |    x    | RDATA  |               |
+
+## WDATA
+UART write data
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "WDATA", "bits": 8, "attr": ["wo"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description   |
+|:------:|:------:|:-------:|:-------|:--------------|
+|  31:8  |        |         |        | Reserved      |
+|  7:0   |   wo   |   0x0   | WDATA  |               |
+
+## FIFO_CTRL
+UART FIFO control register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TXRST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "TXILVL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                         |
+|:------:|:------:|:-------:|:-----------------------------|
+|  31:8  |        |         | Reserved                     |
+|  7:5   |   rw   |   0x0   | [TXILVL](#fifo_ctrl--txilvl) |
+|  4:2   |   rw   |   0x0   | [RXILVL](#fifo_ctrl--rxilvl) |
+|   1    |   wo   |   0x0   | [TXRST](#fifo_ctrl--txrst)   |
+|   0    |   wo   |   0x0   | [RXRST](#fifo_ctrl--rxrst)   |
+
+### FIFO_CTRL . TXILVL
+Trigger level for TX interrupts. If the FIFO depth is less than the setting, it
+raises tx_watermark interrupt.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | txlvl1  | 1 character   |
+| 0x1     | txlvl2  | 2 characters  |
+| 0x2     | txlvl4  | 4 characters  |
+| 0x3     | txlvl8  | 8 characters  |
+| 0x4     | txlvl16 | 16 characters |
+
+Other values are reserved.
+
+### FIFO_CTRL . RXILVL
+Trigger level for RX interrupts. If the FIFO depth is greater than or equal to
+the setting, it raises rx_watermark interrupt.
+
+| Value   | Name    | Description   |
+|:--------|:--------|:--------------|
+| 0x0     | rxlvl1  | 1 character   |
+| 0x1     | rxlvl2  | 2 characters  |
+| 0x2     | rxlvl4  | 4 characters  |
+| 0x3     | rxlvl8  | 8 characters  |
+| 0x4     | rxlvl16 | 16 characters |
+| 0x5     | rxlvl32 | 32 characters |
+| 0x6     | rxlvl62 | 62 characters |
+
+Other values are reserved.
+
+### FIFO_CTRL . TXRST
+TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0
+
+### FIFO_CTRL . RXRST
+RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0
+
+## FIFO_STATUS
+UART FIFO status register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0xff00ff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}, {"name": "RXLVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                   |
+|:------:|:------:|:-------:|:-------|:------------------------------|
+| 31:24  |        |         |        | Reserved                      |
+| 23:16  |   ro   |    x    | RXLVL  | Current fill level of RX fifo |
+|  15:8  |        |         |        | Reserved                      |
+|  7:0   |   ro   |    x    | TXLVL  | Current fill level of TX fifo |
+
+## OVRD
+TX pin override control. Gives direct SW control over TX pin state
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "TXEN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TXVAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                          |
+|:------:|:------:|:-------:|:-------|:-------------------------------------|
+|  31:2  |        |         |        | Reserved                             |
+|   1    |   rw   |   0x0   | TXVAL  | Write to set the value of the TX pin |
+|   0    |   rw   |   0x0   | TXEN   | Enable TX pin override control       |
+
+## VAL
+UART oversampled values
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "RX", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                            |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------|
+| 31:16  |        |         |        | Reserved                                                               |
+|  15:0  |   ro   |    x    | RX     | Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15. |
+
+## TIMEOUT_CTRL
+UART RX timeout control
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0x80ffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "VAL", "bits": 24, "attr": ["rw"], "rotate": 0}, {"bits": 7}, {"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|   31   |   rw   |   0x0   | EN     | Enable RX timeout feature          |
+| 30:24  |        |         |        | Reserved                           |
+|  23:0  |   rw   |   0x0   | VAL    | RX timeout value in UART bit times |
+
diff --git a/docs/um/ip/unbent/data/err_unit_regs.hjson b/docs/um/ip/unbent/data/err_unit_regs.hjson
new file mode 100644
index 00000000..22c7ec86
--- /dev/null
+++ b/docs/um/ip/unbent/data/err_unit_regs.hjson
@@ -0,0 +1,70 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Michael Rogenmoser <michaero@iis.ee.ethz.ch>
+
+{
+  name: "bus_err_unit",
+  clock_primary: "clk_i",
+  reset_primary: "rst_ni",
+  bus_interfaces: [
+    { protocol: "reg_iface",
+      direction: "device"
+    }
+  ],
+
+  regwidth: "32",
+
+  registers: [
+    { name: "err_addr",
+      desc: "Address of the bus error",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "31:0",
+          name: "err_addr",
+          desc: "Address of the bus error"
+        }
+      ]
+    },
+    { name: "err_addr_top",
+      desc: "Top of the address of the bus error",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "31:0",
+          name: "err_addr",
+          desc: "Address of the bus error"
+        }
+      ]
+    },
+    { name: "err_code",
+      desc: "Error code of the bus error",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "31:0",
+          name: "err_code",
+          desc: "Error code of the bus error"
+        }
+      ]
+    },
+    { name: "meta",
+      desc: "Meta information of the bus error",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "31:0",
+          name: "meta",
+          desc: "Meta information of the bus error"
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/unbent/data/err_unit_regs_doc.hjson b/docs/um/ip/unbent/data/err_unit_regs_doc.hjson
new file mode 100644
index 00000000..2997e602
--- /dev/null
+++ b/docs/um/ip/unbent/data/err_unit_regs_doc.hjson
@@ -0,0 +1,70 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Author: Michael Rogenmoser <michaero@iis.ee.ethz.ch>
+
+{
+  name: "bus_err_unit",
+  cip_id: "36",
+  version: "0.1.6",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32",
+  registers: [
+    { name: "err_addr",
+      desc: "Address of the bus error",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "31:0",
+          name: "err_addr",
+          desc: "Address of the bus error"
+        }
+      ]
+    },
+    { name: "err_addr_top",
+      desc: "Top of the address of the bus error",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "31:0",
+          name: "err_addr",
+          desc: "Address of the bus error"
+        }
+      ]
+    },
+    { name: "err_code",
+      desc: "Error code of the bus error",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre: "true",
+      fields: [
+        { bits: "31:0",
+          name: "err_code",
+          desc: "Error code of the bus error"
+        }
+      ]
+    },
+    { name: "meta",
+      desc: "Meta information of the bus error",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      hwext: "true",
+      fields: [
+        { bits: "31:0",
+          name: "meta",
+          desc: "Meta information of the bus error"
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/unbent/doc/registers.md b/docs/um/ip/unbent/doc/registers.md
new file mode 100644
index 00000000..46160c72
--- /dev/null
+++ b/docs/um/ip/unbent/doc/registers.md
@@ -0,0 +1,73 @@
+## Summary
+
+| Name                                         | Offset   |   Length | Description                         |
+|:---------------------------------------------|:---------|---------:|:------------------------------------|
+| bus_err_unit.[`err_addr`](#err_addr)         | 0x0      |        4 | Address of the bus error            |
+| bus_err_unit.[`err_addr_top`](#err_addr_top) | 0x4      |        4 | Top of the address of the bus error |
+| bus_err_unit.[`err_code`](#err_code)         | 0x8      |        4 | Error code of the bus error         |
+| bus_err_unit.[`meta`](#meta)                 | 0xc      |        4 | Meta information of the bus error   |
+
+## err_addr
+Address of the bus error
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description              |
+|:------:|:------:|:-------:|:---------|:-------------------------|
+|  31:0  |   ro   |    x    | err_addr | Address of the bus error |
+
+## err_addr_top
+Top of the address of the bus error
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_addr", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description              |
+|:------:|:------:|:-------:|:---------|:-------------------------|
+|  31:0  |   ro   |    x    | err_addr | Address of the bus error |
+
+## err_code
+Error code of the bus error
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "err_code", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name     | Description                 |
+|:------:|:------:|:-------:|:---------|:----------------------------|
+|  31:0  |   ro   |    x    | err_code | Error code of the bus error |
+
+## meta
+Meta information of the bus error
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "meta", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                       |
+|:------:|:------:|:-------:|:-------|:----------------------------------|
+|  31:0  |   ro   |    x    | meta   | Meta information of the bus error |
+
diff --git a/docs/um/ip/vga/data/axi_vga_regs.hjson b/docs/um/ip/vga/data/axi_vga_regs.hjson
new file mode 100644
index 00000000..6c9debd0
--- /dev/null
+++ b/docs/um/ip/vga/data/axi_vga_regs.hjson
@@ -0,0 +1,246 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Nicole Narr <narrn@student.ethz.ch>
+// Christopher Reinwardt <creinwar@student.ethz.ch>
+{
+  name: "axi_vga"
+  clock_primary: "clk_i"
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: 32
+  registers: [
+    { name: "CONTROL",
+      desc: "Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "0"
+          resval: "0"
+          name: "enable"
+          desc: '''
+                Enables FSM.
+                '''
+        }
+        {
+          bits: "1"
+          resval: "1"
+          name: "hsync_pol"
+          desc: '''
+                Sets polarity for HSYNC
+                0 - Active Low
+                1 - Active High
+                '''
+        }
+        {
+          bits: "2"
+          resval: "1"
+          name: "vsync_pol"
+          desc: '''
+                Sets polarity for VSYNC
+                0 - Active Low
+                1 - Active High
+                '''
+        }
+      ]
+    }
+    { name: "CLK_DIV"
+      desc: "Clock divider"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        {
+          bits: "7:0"
+          resval: "1"
+          name: "clk_div"
+          desc: '''
+                Clock divider.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_VISIBLE_SIZE",
+      desc: "Size of horizontal visible area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_visible_size"
+          desc: '''
+                Size of horizontal visible area.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_FRONT_PORCH_SIZE",
+      desc: "Size of horizontal front porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_front_porch_size"
+          desc: '''
+                Size of horizontal front porch.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_SYNC_SIZE",
+      desc: "Size of horizontal sync area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_sync_size"
+          desc: '''
+                Size of horizontal sync area.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_BACK_PORCH_SIZE",
+      desc: "Size of horizontal back porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_back_porch_size"
+          desc: '''
+                Size of horizontal back porch.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_VISIBLE_SIZE",
+      desc: "Size of vertical visible area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_visible_size"
+          desc: '''
+                Size of vertical visible area.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_FRONT_PORCH_SIZE",
+      desc: "Size of vertical front porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_front_porch_size"
+          desc: '''
+                Size of vertical front porch.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_SYNC_SIZE",
+      desc: "Size of vertical sync area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_sync_size"
+          desc: '''
+                Size of vertical sync area.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_BACK_PORCH_SIZE",
+      desc: "Size of vertical back porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_back_porch_size"
+          desc: '''
+                Size of vertical back porch.
+                '''
+        }
+      ]
+    }
+    { name: "START_ADDR_LOW",
+      desc: "Low end of start address of frame buffer",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "0x00000000"
+          name: "start_addr_low"
+          desc: '''
+                Low end of start address of frame buffer.
+                '''
+        }
+      ]
+    }
+    { name: "START_ADDR_HIGH",
+      desc: "High end of start address of frame buffer",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "0"
+          name: "start_addr_high"
+          desc: '''
+                High end of start address of frame buffer.
+                '''
+        }
+      ]
+    }
+    { name: "FRAME_SIZE",
+      desc: "Size of whole frame",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "0"
+          name: "frame_size"
+          desc: '''
+                Size of whole frame.
+                '''
+        }
+      ]
+    }
+    { name: "BURST_LEN",
+      desc: "Number of beats in a burst",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "7:0"
+          resval: "0"
+          name: "burst_len"
+          desc: '''
+                Number of beats in a burst.
+                '''
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/vga/data/axi_vga_regs_doc.hjson b/docs/um/ip/vga/data/axi_vga_regs_doc.hjson
new file mode 100644
index 00000000..2b2428ec
--- /dev/null
+++ b/docs/um/ip/vga/data/axi_vga_regs_doc.hjson
@@ -0,0 +1,251 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+//
+// Nicole Narr <narrn@student.ethz.ch>
+// Christopher Reinwardt <creinwar@student.ethz.ch>
+{
+  name: "axi_vga"
+  cip_id: "36",
+  version: "0.1.1",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: 32
+  registers: [
+    { name: "CONTROL",
+      desc: "Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "0"
+          resval: "0"
+          name: "enable"
+          desc: '''
+                Enables FSM.
+                '''
+        }
+        {
+          bits: "1"
+          resval: "1"
+          name: "hsync_pol"
+          desc: '''
+                Sets polarity for HSYNC
+                0 - Active Low
+                1 - Active High
+                '''
+        }
+        {
+          bits: "2"
+          resval: "1"
+          name: "vsync_pol"
+          desc: '''
+                Sets polarity for VSYNC
+                0 - Active Low
+                1 - Active High
+                '''
+        }
+      ]
+    }
+    { name: "CLK_DIV"
+      desc: "Clock divider"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        {
+          bits: "7:0"
+          resval: "1"
+          name: "clk_div"
+          desc: '''
+                Clock divider.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_VISIBLE_SIZE",
+      desc: "Size of horizontal visible area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_visible_size"
+          desc: '''
+                Size of horizontal visible area.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_FRONT_PORCH_SIZE",
+      desc: "Size of horizontal front porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_front_porch_size"
+          desc: '''
+                Size of horizontal front porch.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_SYNC_SIZE",
+      desc: "Size of horizontal sync area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_sync_size"
+          desc: '''
+                Size of horizontal sync area.
+                '''
+        }
+      ]
+    }
+    { name: "HORI_BACK_PORCH_SIZE",
+      desc: "Size of horizontal back porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "hori_back_porch_size"
+          desc: '''
+                Size of horizontal back porch.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_VISIBLE_SIZE",
+      desc: "Size of vertical visible area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_visible_size"
+          desc: '''
+                Size of vertical visible area.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_FRONT_PORCH_SIZE",
+      desc: "Size of vertical front porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_front_porch_size"
+          desc: '''
+                Size of vertical front porch.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_SYNC_SIZE",
+      desc: "Size of vertical sync area",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_sync_size"
+          desc: '''
+                Size of vertical sync area.
+                '''
+        }
+      ]
+    }
+    { name: "VERT_BACK_PORCH_SIZE",
+      desc: "Size of vertical back porch",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "1"
+          name: "vert_back_porch_size"
+          desc: '''
+                Size of vertical back porch.
+                '''
+        }
+      ]
+    }
+    { name: "START_ADDR_LOW",
+      desc: "Low end of start address of frame buffer",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "0x00000000"
+          name: "start_addr_low"
+          desc: '''
+                Low end of start address of frame buffer.
+                '''
+        }
+      ]
+    }
+    { name: "START_ADDR_HIGH",
+      desc: "High end of start address of frame buffer",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "0"
+          name: "start_addr_high"
+          desc: '''
+                High end of start address of frame buffer.
+                '''
+        }
+      ]
+    }
+    { name: "FRAME_SIZE",
+      desc: "Size of whole frame",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "31:0"
+          resval: "0"
+          name: "frame_size"
+          desc: '''
+                Size of whole frame.
+                '''
+        }
+      ]
+    }
+    { name: "BURST_LEN",
+      desc: "Number of beats in a burst",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        {
+          bits: "7:0"
+          resval: "0"
+          name: "burst_len"
+          desc: '''
+                Number of beats in a burst.
+                '''
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/docs/um/ip/vga/doc/registers.md b/docs/um/ip/vga/doc/registers.md
new file mode 100644
index 00000000..5e67279c
--- /dev/null
+++ b/docs/um/ip/vga/doc/registers.md
@@ -0,0 +1,248 @@
+## Summary
+
+| Name                                                      | Offset   |   Length | Description                               |
+|:----------------------------------------------------------|:---------|---------:|:------------------------------------------|
+| axi_vga.[`CONTROL`](#control)                             | 0x0      |        4 | Control register                          |
+| axi_vga.[`CLK_DIV`](#clk_div)                             | 0x4      |        4 | Clock divider                             |
+| axi_vga.[`HORI_VISIBLE_SIZE`](#hori_visible_size)         | 0x8      |        4 | Size of horizontal visible area           |
+| axi_vga.[`HORI_FRONT_PORCH_SIZE`](#hori_front_porch_size) | 0xc      |        4 | Size of horizontal front porch            |
+| axi_vga.[`HORI_SYNC_SIZE`](#hori_sync_size)               | 0x10     |        4 | Size of horizontal sync area              |
+| axi_vga.[`HORI_BACK_PORCH_SIZE`](#hori_back_porch_size)   | 0x14     |        4 | Size of horizontal back porch             |
+| axi_vga.[`VERT_VISIBLE_SIZE`](#vert_visible_size)         | 0x18     |        4 | Size of vertical visible area             |
+| axi_vga.[`VERT_FRONT_PORCH_SIZE`](#vert_front_porch_size) | 0x1c     |        4 | Size of vertical front porch              |
+| axi_vga.[`VERT_SYNC_SIZE`](#vert_sync_size)               | 0x20     |        4 | Size of vertical sync area                |
+| axi_vga.[`VERT_BACK_PORCH_SIZE`](#vert_back_porch_size)   | 0x24     |        4 | Size of vertical back porch               |
+| axi_vga.[`START_ADDR_LOW`](#start_addr_low)               | 0x28     |        4 | Low end of start address of frame buffer  |
+| axi_vga.[`START_ADDR_HIGH`](#start_addr_high)             | 0x2c     |        4 | High end of start address of frame buffer |
+| axi_vga.[`FRAME_SIZE`](#frame_size)                       | 0x30     |        4 | Size of whole frame                       |
+| axi_vga.[`BURST_LEN`](#burst_len)                         | 0x34     |        4 | Number of beats in a burst                |
+
+## CONTROL
+Control register
+- Offset: `0x0`
+- Reset default: `0x6`
+- Reset mask: `0x7`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "hsync_pol", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "vsync_pol", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                            |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------|
+|  31:3  |        |         |           | Reserved                                               |
+|   2    |   rw   |   0x1   | vsync_pol | Sets polarity for VSYNC 0 - Active Low 1 - Active High |
+|   1    |   rw   |   0x1   | hsync_pol | Sets polarity for HSYNC 0 - Active Low 1 - Active High |
+|   0    |   rw   |   0x0   | enable    | Enables FSM.                                           |
+
+## CLK_DIV
+Clock divider
+- Offset: `0x4`
+- Reset default: `0x1`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "clk_div", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name    | Description    |
+|:------:|:------:|:-------:|:--------|:---------------|
+|  31:8  |        |         |         | Reserved       |
+|  7:0   |   rw   |   0x1   | clk_div | Clock divider. |
+
+## HORI_VISIBLE_SIZE
+Size of horizontal visible area
+- Offset: `0x8`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_visible_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                      |
+|:------:|:------:|:-------:|:------------------|:---------------------------------|
+|  31:0  |   rw   |   0x1   | hori_visible_size | Size of horizontal visible area. |
+
+## HORI_FRONT_PORCH_SIZE
+Size of horizontal front porch
+- Offset: `0xc`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_front_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                     |
+|:------:|:------:|:-------:|:----------------------|:--------------------------------|
+|  31:0  |   rw   |   0x1   | hori_front_porch_size | Size of horizontal front porch. |
+
+## HORI_SYNC_SIZE
+Size of horizontal sync area
+- Offset: `0x10`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_sync_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                   |
+|:------:|:------:|:-------:|:---------------|:------------------------------|
+|  31:0  |   rw   |   0x1   | hori_sync_size | Size of horizontal sync area. |
+
+## HORI_BACK_PORCH_SIZE
+Size of horizontal back porch
+- Offset: `0x14`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "hori_back_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description                    |
+|:------:|:------:|:-------:|:---------------------|:-------------------------------|
+|  31:0  |   rw   |   0x1   | hori_back_porch_size | Size of horizontal back porch. |
+
+## VERT_VISIBLE_SIZE
+Size of vertical visible area
+- Offset: `0x18`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_visible_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name              | Description                    |
+|:------:|:------:|:-------:|:------------------|:-------------------------------|
+|  31:0  |   rw   |   0x1   | vert_visible_size | Size of vertical visible area. |
+
+## VERT_FRONT_PORCH_SIZE
+Size of vertical front porch
+- Offset: `0x1c`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_front_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                   |
+|:------:|:------:|:-------:|:----------------------|:------------------------------|
+|  31:0  |   rw   |   0x1   | vert_front_porch_size | Size of vertical front porch. |
+
+## VERT_SYNC_SIZE
+Size of vertical sync area
+- Offset: `0x20`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_sync_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                 |
+|:------:|:------:|:-------:|:---------------|:----------------------------|
+|  31:0  |   rw   |   0x1   | vert_sync_size | Size of vertical sync area. |
+
+## VERT_BACK_PORCH_SIZE
+Size of vertical back porch
+- Offset: `0x24`
+- Reset default: `0x1`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "vert_back_porch_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                 | Description                  |
+|:------:|:------:|:-------:|:---------------------|:-----------------------------|
+|  31:0  |   rw   |   0x1   | vert_back_porch_size | Size of vertical back porch. |
+
+## START_ADDR_LOW
+Low end of start address of frame buffer
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "start_addr_low", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                               |
+|:------:|:------:|:-------:|:---------------|:------------------------------------------|
+|  31:0  |   rw   |   0x0   | start_addr_low | Low end of start address of frame buffer. |
+
+## START_ADDR_HIGH
+High end of start address of frame buffer
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "start_addr_high", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name            | Description                                |
+|:------:|:------:|:-------:|:----------------|:-------------------------------------------|
+|  31:0  |   rw   |   0x0   | start_addr_high | High end of start address of frame buffer. |
+
+## FRAME_SIZE
+Size of whole frame
+- Offset: `0x30`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "frame_size", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name       | Description          |
+|:------:|:------:|:-------:|:-----------|:---------------------|
+|  31:0  |   rw   |   0x0   | frame_size | Size of whole frame. |
+
+## BURST_LEN
+Number of beats in a burst
+- Offset: `0x34`
+- Reset default: `0x0`
+- Reset mask: `0xff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "burst_len", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                 |
+|:------:|:------:|:-------:|:----------|:----------------------------|
+|  31:8  |        |         |           | Reserved                    |
+|  7:0   |   rw   |   0x0   | burst_len | Number of beats in a burst. |
+
diff --git a/docs/um/ip/watchdog_timer/data/aon_timer.hjson b/docs/um/ip/watchdog_timer/data/aon_timer.hjson
new file mode 100644
index 00000000..b0660b09
--- /dev/null
+++ b/docs/um/ip/watchdog_timer/data/aon_timer.hjson
@@ -0,0 +1,265 @@
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+{
+  name:               "aon_timer",
+  human_name:         "Always-On Timer",
+  one_line_desc:      "Wakeup and watchdog timers running on a low-power, always-on clock",
+  one_paragraph_desc: '''
+  Always-On (AON) Timer is the main timer hardware block of OpenTitan.
+  It includes two 32-bit up-counting timers, one of which functions as a wakeup timer and the other as a watchdog timer.
+  The watchdog timer has two thresholds: a 'bark' threshold that generates an interrupt and a 'bite' threshold that resets the system.
+  The wakeup timer has a 12-bit pre-scaler to enable very long timeouts and also generates an interrupt to the core.
+  The timers run on a ~200 kHz AON clock and have a maximum timeout window of roughly ~6 hours for the watchdog timer and ~1000 days with the use of the pre-scaler for the wakeup timer.
+  '''
+  design_spec:        "../doc",
+  dv_doc:             "../doc/dv",
+  hw_checklist:       "../doc/checklist",
+  sw_checklist:       "/sw/device/lib/dif/dif_aon_timer",
+  version:            "1.0",
+  life_stage:         "L1",
+  design_stage:       "D3",
+  verification_stage: "V2",
+  dif_stage:          "S2",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true},
+    {clock: "clk_aon_i", reset: "rst_aon_ni"}
+  ]
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device"}
+  ],
+  interrupt_list: [
+    { name: "wkup_timer_expired",
+      desc: "Raised if the wakeup timer has hit the specified threshold"
+    },
+    { name: "wdog_timer_bark",
+      desc: "Raised if the watchdog timer has hit the bark threshold"
+    },
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  wakeup_list: [
+    { name: "wkup_req",
+      desc: "Raised if the wakeup or watchdog timer has hit the specified threshold"
+    },
+  ],
+  reset_request_list: [
+    { name: "aon_timer_rst_req",
+      desc: "watchdog reset requestt"
+    },
+  ],
+  inter_signal_list: [
+    // wakeup and reset request signals
+    { struct:  "logic",
+      type:    "uni",
+      name:    "nmi_wdog_timer_bark",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    { struct:  "logic",
+      type:    "uni",
+      name:    "wkup_req",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    { struct:  "logic",
+      type:    "uni",
+      name:    "aon_timer_rst_req",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    // Broadcast from LC
+    { struct:  "lc_tx"
+      type:    "uni"
+      name:    "lc_escalate_en"
+      act:     "rcv"
+      default: "lc_ctrl_pkg::Off"
+      package: "lc_ctrl_pkg"
+    },
+    { name:    "sleep_mode",
+      type:    "uni",
+      act:     "rcv",
+      package: "",
+      struct:  "logic",
+      width:   "1"
+    }
+  ],
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+  ]
+  no_auto_intr_regs: "true",
+  regwidth: "32",
+  registers: [
+    { name: "WKUP_CTRL",
+      desc: "Wakeup Timer Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "When set to 1, the wakeup timer will count",
+        }
+        { bits: "12:1",
+          name: "prescaler",
+          desc: "Pre-scaler value for wakeup timer count",
+        }
+      ],
+    },
+    { name: "WKUP_THOLD",
+      desc: "Wakeup Timer Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a wakeup interrupt should be generated",
+        }
+      ],
+    },
+    { name: "WKUP_COUNT",
+      desc: "Wakeup Timer Count Register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "count",
+          desc: "The current wakeup counter value",
+        }
+      ],
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "WDOG_REGWEN",
+      desc: "Watchdog Timer Write Enable Register",
+      swaccess: "rw0c",
+      hwaccess: "none",
+      fields: [
+        { bits: "0",
+          name: "regwen",
+          desc: "Once cleared, the watchdog configuration will be locked until the next reset",
+          resval: 1
+        }
+      ]
+    },
+    { name: "WDOG_CTRL",
+      desc: "Watchdog Timer Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "When set to 1, the watchdog timer will count",
+        },
+        { bits: "1",
+          name: "pause_in_sleep",
+          desc: "When set to 1, the watchdog timer will not count during sleep",
+        }
+      ],
+    },
+    { name: "WDOG_BARK_THOLD",
+      desc: "Watchdog Timer Bark Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a watchdog bark interrupt should be generated",
+        }
+      ],
+    },
+    { name: "WDOG_BITE_THOLD",
+      desc: "Watchdog Timer Bite Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a watchdog bite reset should be generated",
+        }
+      ],
+    },
+    { name: "WDOG_COUNT",
+      desc: "Watchdog Timer Count Register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "count",
+          desc: "The current watchdog counter value",
+        }
+      ],
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "INTR_STATE",
+      desc: "Interrupt State Register",
+      swaccess: "rw1c",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0",
+          name: "wkup_timer_expired",
+          desc: "Raised if the wakeup timer has hit the specified threshold",
+        }
+        { bits: "1",
+          name: "wdog_timer_bark",
+          desc: "Raised if the watchdog timer has hit the bark threshold",
+        }
+      ]
+      tags: [// interrupt could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "INTR_TEST",
+      desc: "Interrupt Test Register",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "0",
+          name: "wkup_timer_expired",
+          desc: "Write 1 to force wkup_timer_expired interrupt",
+        }
+        { bits: "1",
+          name: "wdog_timer_bark",
+          desc: "Write 1 to force wdog_timer_bark interrupt",
+        }
+      ]
+    },
+    { name: "WKUP_CAUSE",
+      desc: "Wakeup request status",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "0",
+          name: "cause",
+          desc: "AON timer requested wakeup, write 0 to clear",
+        }
+      ]
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+  ],
+}
diff --git a/docs/um/ip/watchdog_timer/data/aon_timer.hjson~ b/docs/um/ip/watchdog_timer/data/aon_timer.hjson~
new file mode 100644
index 00000000..e69de29b
diff --git a/docs/um/ip/watchdog_timer/data/aon_timer_doc.hjson b/docs/um/ip/watchdog_timer/data/aon_timer_doc.hjson
new file mode 100644
index 00000000..bb551070
--- /dev/null
+++ b/docs/um/ip/watchdog_timer/data/aon_timer_doc.hjson
@@ -0,0 +1,266 @@
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+{
+  name:               "aon_timer",
+  human_name:         "Always-On Timer",
+  one_line_desc:      "Wakeup and watchdog timers running on a low-power, always-on clock",
+  one_paragraph_desc: '''
+  Always-On (AON) Timer is the main timer hardware block of OpenTitan.
+  It includes two 32-bit up-counting timers, one of which functions as a wakeup timer and the other as a watchdog timer.
+  The watchdog timer has two thresholds: a 'bark' threshold that generates an interrupt and a 'bite' threshold that resets the system.
+  The wakeup timer has a 12-bit pre-scaler to enable very long timeouts and also generates an interrupt to the core.
+  The timers run on a ~200 kHz AON clock and have a maximum timeout window of roughly ~6 hours for the watchdog timer and ~1000 days with the use of the pre-scaler for the wakeup timer.
+  '''
+  design_spec:        "../doc",
+  dv_doc:             "../doc/dv",
+  hw_checklist:       "../doc/checklist",
+  sw_checklist:       "/sw/device/lib/dif/dif_aon_timer",
+  version:            "1.0.0",
+  life_stage:         "L1",
+  design_stage:       "D3",
+  verification_stage: "V2",
+  dif_stage:"S2",
+  cip_id: "3",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true},
+    {clock: "clk_aon_i", reset: "rst_aon_ni"}
+  ]
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device"}
+  ],
+  interrupt_list: [
+    { name: "wkup_timer_expired",
+      desc: "Raised if the wakeup timer has hit the specified threshold"
+    },
+    { name: "wdog_timer_bark",
+      desc: "Raised if the watchdog timer has hit the bark threshold"
+    },
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  wakeup_list: [
+    { name: "wkup_req",
+      desc: "Raised if the wakeup or watchdog timer has hit the specified threshold"
+    },
+  ],
+  reset_request_list: [
+    { name: "aon_timer_rst_req",
+      desc: "watchdog reset requestt"
+    },
+  ],
+  inter_signal_list: [
+    // wakeup and reset request signals
+    { struct:  "logic",
+      type:    "uni",
+      name:    "nmi_wdog_timer_bark",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    { struct:  "logic",
+      type:    "uni",
+      name:    "wkup_req",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    { struct:  "logic",
+      type:    "uni",
+      name:    "aon_timer_rst_req",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    // Broadcast from LC
+    { struct:  "lc_tx"
+      type:    "uni"
+      name:    "lc_escalate_en"
+      act:     "rcv"
+      default: "lc_ctrl_pkg::Off"
+      package: "lc_ctrl_pkg"
+    },
+    { name:    "sleep_mode",
+      type:    "uni",
+      act:     "rcv",
+      package: "",
+      struct:  "logic",
+      width:   "1"
+    }
+  ],
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+  ]
+  no_auto_intr_regs: "true",
+  regwidth: "32",
+  registers: [
+    { name: "WKUP_CTRL",
+      desc: "Wakeup Timer Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "When set to 1, the wakeup timer will count",
+        }
+        { bits: "12:1",
+          name: "prescaler",
+          desc: "Pre-scaler value for wakeup timer count",
+        }
+      ],
+    },
+    { name: "WKUP_THOLD",
+      desc: "Wakeup Timer Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a wakeup interrupt should be generated",
+        }
+      ],
+    },
+    { name: "WKUP_COUNT",
+      desc: "Wakeup Timer Count Register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "count",
+          desc: "The current wakeup counter value",
+        }
+      ],
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "WDOG_REGWEN",
+      desc: "Watchdog Timer Write Enable Register",
+      swaccess: "rw0c",
+      hwaccess: "none",
+      fields: [
+        { bits: "0",
+          name: "regwen",
+          desc: "Once cleared, the watchdog configuration will be locked until the next reset",
+          resval: 1
+        }
+      ]
+    },
+    { name: "WDOG_CTRL",
+      desc: "Watchdog Timer Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "When set to 1, the watchdog timer will count",
+        },
+        { bits: "1",
+          name: "pause_in_sleep",
+          desc: "When set to 1, the watchdog timer will not count during sleep",
+        }
+      ],
+    },
+    { name: "WDOG_BARK_THOLD",
+      desc: "Watchdog Timer Bark Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a watchdog bark interrupt should be generated",
+        }
+      ],
+    },
+    { name: "WDOG_BITE_THOLD",
+      desc: "Watchdog Timer Bite Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a watchdog bite reset should be generated",
+        }
+      ],
+    },
+    { name: "WDOG_COUNT",
+      desc: "Watchdog Timer Count Register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "count",
+          desc: "The current watchdog counter value",
+        }
+      ],
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "INTR_STATE",
+      desc: "Interrupt State Register",
+      swaccess: "rw1c",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0",
+          name: "wkup_timer_expired",
+          desc: "Raised if the wakeup timer has hit the specified threshold",
+        }
+        { bits: "1",
+          name: "wdog_timer_bark",
+          desc: "Raised if the watchdog timer has hit the bark threshold",
+        }
+      ]
+      tags: [// interrupt could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "INTR_TEST",
+      desc: "Interrupt Test Register",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "0",
+          name: "wkup_timer_expired",
+          desc: "Write 1 to force wkup_timer_expired interrupt",
+        }
+        { bits: "1",
+          name: "wdog_timer_bark",
+          desc: "Write 1 to force wdog_timer_bark interrupt",
+        }
+      ]
+    },
+    { name: "WKUP_CAUSE",
+      desc: "Wakeup request status",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "0",
+          name: "cause",
+          desc: "AON timer requested wakeup, write 0 to clear",
+        }
+      ]
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+  ],
+}
diff --git a/docs/um/ip/watchdog_timer/data/aon_timer_doc.hjson~ b/docs/um/ip/watchdog_timer/data/aon_timer_doc.hjson~
new file mode 100644
index 00000000..c8b49daf
--- /dev/null
+++ b/docs/um/ip/watchdog_timer/data/aon_timer_doc.hjson~
@@ -0,0 +1,266 @@
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+{
+  name:               "aon_timer",
+  human_name:         "Always-On Timer",
+  one_line_desc:      "Wakeup and watchdog timers running on a low-power, always-on clock",
+  one_paragraph_desc: '''
+  Always-On (AON) Timer is the main timer hardware block of OpenTitan.
+  It includes two 32-bit up-counting timers, one of which functions as a wakeup timer and the other as a watchdog timer.
+  The watchdog timer has two thresholds: a 'bark' threshold that generates an interrupt and a 'bite' threshold that resets the system.
+  The wakeup timer has a 12-bit pre-scaler to enable very long timeouts and also generates an interrupt to the core.
+  The timers run on a ~200 kHz AON clock and have a maximum timeout window of roughly ~6 hours for the watchdog timer and ~1000 days with the use of the pre-scaler for the wakeup timer.
+  '''
+  design_spec:        "../doc",
+  dv_doc:             "../doc/dv",
+  hw_checklist:       "../doc/checklist",
+  sw_checklist:       "/sw/device/lib/dif/dif_aon_timer",
+  version:            "1.0",
+  life_stage:         "L1",
+  design_stage:       "D3",
+  verification_stage: "V2",
+  dif_stage:"S2",
+  cip_id: "3",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true},
+    {clock: "clk_aon_i", reset: "rst_aon_ni"}
+  ]
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device"}
+  ],
+  interrupt_list: [
+    { name: "wkup_timer_expired",
+      desc: "Raised if the wakeup timer has hit the specified threshold"
+    },
+    { name: "wdog_timer_bark",
+      desc: "Raised if the watchdog timer has hit the bark threshold"
+    },
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+      '''
+    }
+  ],
+  wakeup_list: [
+    { name: "wkup_req",
+      desc: "Raised if the wakeup or watchdog timer has hit the specified threshold"
+    },
+  ],
+  reset_request_list: [
+    { name: "aon_timer_rst_req",
+      desc: "watchdog reset requestt"
+    },
+  ],
+  inter_signal_list: [
+    // wakeup and reset request signals
+    { struct:  "logic",
+      type:    "uni",
+      name:    "nmi_wdog_timer_bark",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    { struct:  "logic",
+      type:    "uni",
+      name:    "wkup_req",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    { struct:  "logic",
+      type:    "uni",
+      name:    "aon_timer_rst_req",
+      act:     "req",
+      package: "",
+      default: "1'b0"
+    },
+    // Broadcast from LC
+    { struct:  "lc_tx"
+      type:    "uni"
+      name:    "lc_escalate_en"
+      act:     "rcv"
+      default: "lc_ctrl_pkg::Off"
+      package: "lc_ctrl_pkg"
+    },
+    { name:    "sleep_mode",
+      type:    "uni",
+      act:     "rcv",
+      package: "",
+      struct:  "logic",
+      width:   "1"
+    }
+  ],
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+  ]
+  no_auto_intr_regs: "true",
+  regwidth: "32",
+  registers: [
+    { name: "WKUP_CTRL",
+      desc: "Wakeup Timer Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "When set to 1, the wakeup timer will count",
+        }
+        { bits: "12:1",
+          name: "prescaler",
+          desc: "Pre-scaler value for wakeup timer count",
+        }
+      ],
+    },
+    { name: "WKUP_THOLD",
+      desc: "Wakeup Timer Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a wakeup interrupt should be generated",
+        }
+      ],
+    },
+    { name: "WKUP_COUNT",
+      desc: "Wakeup Timer Count Register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "count",
+          desc: "The current wakeup counter value",
+        }
+      ],
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "WDOG_REGWEN",
+      desc: "Watchdog Timer Write Enable Register",
+      swaccess: "rw0c",
+      hwaccess: "none",
+      fields: [
+        { bits: "0",
+          name: "regwen",
+          desc: "Once cleared, the watchdog configuration will be locked until the next reset",
+          resval: 1
+        }
+      ]
+    },
+    { name: "WDOG_CTRL",
+      desc: "Watchdog Timer Control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "0",
+          name: "enable",
+          desc: "When set to 1, the watchdog timer will count",
+        },
+        { bits: "1",
+          name: "pause_in_sleep",
+          desc: "When set to 1, the watchdog timer will not count during sleep",
+        }
+      ],
+    },
+    { name: "WDOG_BARK_THOLD",
+      desc: "Watchdog Timer Bark Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a watchdog bark interrupt should be generated",
+        }
+      ],
+    },
+    { name: "WDOG_BITE_THOLD",
+      desc: "Watchdog Timer Bite Threshold Register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      async: "clk_aon_i",
+      regwen: "WDOG_REGWEN",
+      fields: [
+        { bits: "31:0",
+          name: "threshold",
+          desc: "The count at which a watchdog bite reset should be generated",
+        }
+      ],
+    },
+    { name: "WDOG_COUNT",
+      desc: "Watchdog Timer Count Register",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "31:0",
+          name: "count",
+          desc: "The current watchdog counter value",
+        }
+      ],
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "INTR_STATE",
+      desc: "Interrupt State Register",
+      swaccess: "rw1c",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0",
+          name: "wkup_timer_expired",
+          desc: "Raised if the wakeup timer has hit the specified threshold",
+        }
+        { bits: "1",
+          name: "wdog_timer_bark",
+          desc: "Raised if the watchdog timer has hit the bark threshold",
+        }
+      ]
+      tags: [// interrupt could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+    { name: "INTR_TEST",
+      desc: "Interrupt Test Register",
+      swaccess: "wo",
+      hwaccess: "hro",
+      hwext: "true",
+      hwqe: "true",
+      fields: [
+        { bits: "0",
+          name: "wkup_timer_expired",
+          desc: "Write 1 to force wkup_timer_expired interrupt",
+        }
+        { bits: "1",
+          name: "wdog_timer_bark",
+          desc: "Write 1 to force wdog_timer_bark interrupt",
+        }
+      ]
+    },
+    { name: "WKUP_CAUSE",
+      desc: "Wakeup request status",
+      swaccess: "rw0c",
+      hwaccess: "hrw",
+      async: "clk_aon_i",
+      fields: [
+        { bits: "0",
+          name: "cause",
+          desc: "AON timer requested wakeup, write 0 to clear",
+        }
+      ]
+      tags: [// this could be updated by HW
+        "excl:CsrNonInitTests:CsrExclWriteCheck"],
+    },
+  ],
+}
diff --git a/docs/um/ip/watchdog_timer/doc/registers.md b/docs/um/ip/watchdog_timer/doc/registers.md
new file mode 100644
index 00000000..05eedaab
--- /dev/null
+++ b/docs/um/ip/watchdog_timer/doc/registers.md
@@ -0,0 +1,223 @@
+## Summary
+
+| Name                                            | Offset   |   Length | Description                            |
+|:------------------------------------------------|:---------|---------:|:---------------------------------------|
+| aon_timer.[`ALERT_TEST`](#alert_test)           | 0x0      |        4 | Alert Test Register                    |
+| aon_timer.[`WKUP_CTRL`](#wkup_ctrl)             | 0x4      |        4 | Wakeup Timer Control register          |
+| aon_timer.[`WKUP_THOLD`](#wkup_thold)           | 0x8      |        4 | Wakeup Timer Threshold Register        |
+| aon_timer.[`WKUP_COUNT`](#wkup_count)           | 0xc      |        4 | Wakeup Timer Count Register            |
+| aon_timer.[`WDOG_REGWEN`](#wdog_regwen)         | 0x10     |        4 | Watchdog Timer Write Enable Register   |
+| aon_timer.[`WDOG_CTRL`](#wdog_ctrl)             | 0x14     |        4 | Watchdog Timer Control register        |
+| aon_timer.[`WDOG_BARK_THOLD`](#wdog_bark_thold) | 0x18     |        4 | Watchdog Timer Bark Threshold Register |
+| aon_timer.[`WDOG_BITE_THOLD`](#wdog_bite_thold) | 0x1c     |        4 | Watchdog Timer Bite Threshold Register |
+| aon_timer.[`WDOG_COUNT`](#wdog_count)           | 0x20     |        4 | Watchdog Timer Count Register          |
+| aon_timer.[`INTR_STATE`](#intr_state)           | 0x24     |        4 | Interrupt State Register               |
+| aon_timer.[`INTR_TEST`](#intr_test)             | 0x28     |        4 | Interrupt Test Register                |
+| aon_timer.[`WKUP_CAUSE`](#wkup_cause)           | 0x2c     |        4 | Wakeup request status                  |
+
+## ALERT_TEST
+Alert Test Register
+- Offset: `0x0`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
+```
+
+|  Bits  |  Type  |  Reset  | Name        | Description                                      |
+|:------:|:------:|:-------:|:------------|:-------------------------------------------------|
+|  31:1  |        |         |             | Reserved                                         |
+|   0    |   wo   |   0x0   | fatal_fault | Write 1 to trigger one alert event of this kind. |
+
+## WKUP_CTRL
+Wakeup Timer Control register
+- Offset: `0x4`
+- Reset default: `0x0`
+- Reset mask: `0x1fff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "prescaler", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------|
+| 31:13  |        |         |           | Reserved                                   |
+|  12:1  |   rw   |   0x0   | prescaler | Pre-scaler value for wakeup timer count    |
+|   0    |   rw   |   0x0   | enable    | When set to 1, the wakeup timer will count |
+
+## WKUP_THOLD
+Wakeup Timer Threshold Register
+- Offset: `0x8`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                               |
+|:------:|:------:|:-------:|:----------|:----------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a wakeup interrupt should be generated |
+
+## WKUP_COUNT
+Wakeup Timer Count Register
+- Offset: `0xc`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "count", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                      |
+|:------:|:------:|:-------:|:-------|:---------------------------------|
+|  31:0  |   rw   |   0x0   | count  | The current wakeup counter value |
+
+## WDOG_REGWEN
+Watchdog Timer Write Enable Register
+- Offset: `0x10`
+- Reset default: `0x1`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "regwen", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                                                  |
+|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------|
+|  31:1  |        |         |        | Reserved                                                                     |
+|   0    |  rw0c  |   0x1   | regwen | Once cleared, the watchdog configuration will be locked until the next reset |
+
+## WDOG_CTRL
+Watchdog Timer Control register
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pause_in_sleep", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
+```
+
+|  Bits  |  Type  |  Reset  | Name           | Description                                                   |
+|:------:|:------:|:-------:|:---------------|:--------------------------------------------------------------|
+|  31:2  |        |         |                | Reserved                                                      |
+|   1    |   rw   |   0x0   | pause_in_sleep | When set to 1, the watchdog timer will not count during sleep |
+|   0    |   rw   |   0x0   | enable         | When set to 1, the watchdog timer will count                  |
+
+## WDOG_BARK_THOLD
+Watchdog Timer Bark Threshold Register
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                      |
+|:------:|:------:|:-------:|:----------|:-----------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a watchdog bark interrupt should be generated |
+
+## WDOG_BITE_THOLD
+Watchdog Timer Bite Threshold Register
+- Offset: `0x1c`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+- Register enable: [`WDOG_REGWEN`](#wdog_regwen)
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "threshold", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name      | Description                                                  |
+|:------:|:------:|:-------:|:----------|:-------------------------------------------------------------|
+|  31:0  |   rw   |   0x0   | threshold | The count at which a watchdog bite reset should be generated |
+
+## WDOG_COUNT
+Watchdog Timer Count Register
+- Offset: `0x20`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "count", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                        |
+|:------:|:------:|:-------:|:-------|:-----------------------------------|
+|  31:0  |   rw   |   0x0   | count  | The current watchdog counter value |
+
+## INTR_STATE
+Interrupt State Register
+- Offset: `0x24`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "wkup_timer_expired", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "wdog_timer_bark", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description                                                |
+|:------:|:------:|:-------:|:-------------------|:-----------------------------------------------------------|
+|  31:2  |        |         |                    | Reserved                                                   |
+|   1    |  rw1c  |   0x0   | wdog_timer_bark    | Raised if the watchdog timer has hit the bark threshold    |
+|   0    |  rw1c  |   0x0   | wkup_timer_expired | Raised if the wakeup timer has hit the specified threshold |
+
+## INTR_TEST
+Interrupt Test Register
+- Offset: `0x28`
+- Reset default: `0x0`
+- Reset mask: `0x3`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "wkup_timer_expired", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "wdog_timer_bark", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+```
+
+|  Bits  |  Type  |  Reset  | Name               | Description                                   |
+|:------:|:------:|:-------:|:-------------------|:----------------------------------------------|
+|  31:2  |        |         |                    | Reserved                                      |
+|   1    |   wo   |    x    | wdog_timer_bark    | Write 1 to force wdog_timer_bark interrupt    |
+|   0    |   wo   |    x    | wkup_timer_expired | Write 1 to force wkup_timer_expired interrupt |
+
+## WKUP_CAUSE
+Wakeup request status
+- Offset: `0x2c`
+- Reset default: `0x0`
+- Reset mask: `0x1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "cause", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name   | Description                                  |
+|:------:|:------:|:-------:|:-------|:---------------------------------------------|
+|  31:1  |        |         |        | Reserved                                     |
+|   0    |  rw0c  |   0x0   | cause  | AON timer requested wakeup, write 0 to clear |
+
diff --git a/hw/regs/CL_DMA/CL_DMA.hjson b/hw/regs/CL_DMA/CL_DMA.hjson
new file mode 100644
index 00000000..4777ef75
--- /dev/null
+++ b/hw/regs/CL_DMA/CL_DMA.hjson
@@ -0,0 +1,327 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# DMA register template
+{
+  name:               "dma"
+  human_name:         "DMA Controller"
+  one_line_desc:      "DMA Controller for the integrated OpenTitan."
+  one_paragraph_desc: '''
+  Cluster DMA component manages the following features:
+  - parametric number of RX/TX full-duplex channels
+  - Up to 16 outstanding transfers between L1 and L2 memories
+  - Linear or 2D transfers modes on both TCDM or EXT (L2) sides
+  '''
+  cip_id:             "36",
+  design_spec:        "../doc"
+  dv_doc:             "../doc/dv"
+  version:            "1.0.0"
+
+  clocking: [{clock: "clk_i", reset: "rst_ni", primary: true}]
+  scan: "true"        // Enable `scanmode_i` port
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device", hier_path: "u_dma_reg" }
+    { protocol: "tlul", direction: "host", name: "host" }
+  ]
+  param_list: [
+    { name: "NumIntClearSources",
+      desc: "Number of interrupt clearing sources to process",
+      type: "int",
+      default: "11",
+      local: "true"
+    },
+    { name: "EnableDataIntgGen",
+      desc: "Compute integrity bits for A channel data on all TL-UL host ports",
+      type: "bit",
+      default: "1'b1",
+      local: "false",
+      expose: "true",
+    },
+    { name: "EnableRspDataIntgCheck",
+      desc: "Enable integrity checks on the response TL-UL D channel",
+      type: "bit",
+      default: "1'b1",
+      local: "false",
+      expose: "true",
+    },
+    { name: "TlUserRsvd",
+      desc: "Value of `rsvd` field in A channel of all TL-UL host ports",
+      type: "logic [tlul_pkg::RsvdWidth-1:0]"
+      default: "'0",
+      local: "false",
+      expose: "true",
+    },
+    { name: "SysRacl",
+      desc: "Value of `racl_vec` field in `sys` output",
+      type: "logic [dma_pkg::SYS_RACL_WIDTH-1:0]"
+      default: "'0",
+      local: "false",
+      expose: "true",
+    },
+    { name: "OtAgentId",
+      desc: "OT Agent ID"
+      type: "int unsigned"
+      default: "0",
+      local: "false",
+      expose: "true",
+    },
+  ],
+  inter_signal_list: [
+    { name: "lsio_trigger"
+      type: "uni",
+      act: "rcv",
+      package: "dma_pkg",
+      struct: "lsio_trigger",
+      width: "1"
+    }
+    { name: "sys"
+      type: "req_rsp"
+      struct: "sys"
+      package: "dma_pkg"
+      act: "req"
+      width: "1"
+    }
+    { struct:  "tl_h2d"
+      package: "tlul_pkg"
+      type:    "uni"
+      name:    "ctn_tl_h2d"
+      act:     "req"
+      desc:    "TL-UL host port for egress into CTN (request part), synchronous"
+    }
+    { struct:  "tl_d2h"
+      package: "tlul_pkg"
+      type:    "uni"
+      name:    "ctn_tl_d2h"
+      act:     "rcv"
+      desc:    "TL-UL host port for egress into CTN (response part), synchronous"
+    }
+  ]
+  interrupt_list: [
+    { name: "dma_done"
+      desc: "DMA operation has been completed."
+      type: "status"
+    }
+    { name: "dma_chunk_done"
+      desc: "Indicates the transfer of a single chunk has been completed."
+      type: "status"
+    }
+    { name: "dma_error"
+      desc: "DMA error has occurred. DMA_STATUS.error_code register shows the details."
+      type: "status"
+    }
+  ]
+  alert_list: [
+    { name: "fatal_fault"
+      desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected."
+    }
+  ]
+  countermeasures: [
+    { name: "BUS.INTEGRITY",
+      desc: "End-to-end bus integrity scheme."
+    }
+    { name: "ASID.INTERSIG.MUBI",
+      desc: "Destination and source ASID signals are multibit encoded."
+    }
+    { name: "RANGE.CONFIG.REGWEN_MUBI",
+      desc: "DMA enabled memory range is software multibit lockable."
+    }
+  ]
+  regwidth: "32"
+  registers: [
+    { name: "CMD"
+      desc: '''
+            ?
+            ?
+            ?
+            '''
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "16:0"
+          name: "LEN"
+          resval: 0x0
+          desc: "Transfer length in bytes configuration bitfield."
+        }
+        { bits: "17"
+          name: "TYPE"
+          resval: 0x0
+          desc: '''Transfer direction configuration bitfield:
+                -1'b0: L1 to L2
+                -1'b1: L2 to L1
+                '''
+        }
+        { bits: "18"
+          name: "INC"
+          resval: 0x0
+          desc: '''Transfer incremental configuration bitfield:
+                -1'b0: non incremental.
+                -1'b1: incremental.
+                '''
+        }
+        { bits: "19"
+          name: "EXT_2D"
+          resval: 0x0
+          desc: '''Transfer type configuration bitfield:
+                -1'b0: linear transfer in EXT interface.
+                -1'b1: 2D transfer in EXT interface.
+                '''
+        }
+        { bits: "20"
+          name: "ELE"
+          resval: 0x0
+          desc: '''Transfer event generation configuration bitfield:
+                -1'b0: disabled.
+                -1'b1: enabled.
+                '''
+        }
+        { bits: "21"
+          name: "ILE"
+          resval: 0x0
+          desc: '''Transfer interrupt generation configuration bitfield:
+                -1'b0: disabled.
+                -1'b1: enabled.
+                '''
+        }
+        { bits: "22"
+          name: "BLE"
+          resval: 0x0
+          desc: '''Transfer event or interrupt broadcast configuration bitfield:
+                1'b0: event or interrupt is routed to the cluster core who initiated the transfer.
+                1'b1: event or interrupt are broadcasted to all cluster cores.
+                '''
+        }
+        { bits: "23"
+          name: "TCDM_2D"
+          resval: 0x0
+          desc: '''Transfer type configuration bitfield:
+                -1'b0: linear transfer in TCDM interface
+                -1'b1: 2D transfer in TCDM interface
+                '''
+        }
+      ]
+    }
+    { name: "TID"
+      desc: "Transfer identifier value bitfield."
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "3:0"
+          name: "get_tid"
+          resval: 0x0
+          desc: "Transfer identifier value bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_ADDR"
+      desc: "Transfer L1 base address configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "tcdm_addr"
+          resval: 0x0
+          desc: "Transfer L1 base address configuration bitfield."
+        }
+      ]
+    }
+    { name: "EXT_ADDR"
+      desc: "Transfer L2 base address configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ext_addr"
+          resval: 0x0
+          desc: "Transfer L2 base address configuration bitfield."
+        }
+      ]
+    }
+    { name: "EXT_COUNT_2D"
+      desc: "EXT 2D transfer conut value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ext_count_2D"
+          resval: 0x0
+          desc: "EXT 2D transfer conut value configuration bitfield."
+        }
+      ]
+    }
+    { name: "EXT_STRIDE_2D"
+      desc: "EXT 2D transfer stride value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "ext_stride_2D"
+          resval: 0x0
+          desc: "EXT 2D transfer stride value configuration bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_COUNT_2D"
+      desc: "TCDM 2D transfer conut value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "tcdm_count_2D"
+          resval: 0x0
+          desc: "TCDM 2D transfer conut value configuration bitfield."
+        }
+      ]
+    }
+    { name: "TCDM_STRIDE_2D"
+      desc: "TCDM 2D transfer stride value configuration bitfield."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0"
+          name: "tcdm_stride_2D"
+          resval: 0x0
+          desc: "TCDM 2D transfer stride value configuration bitfield."
+        }
+      ]
+    }
+    { name: "STATUS"
+      desc: '''
+            ?
+            ?
+            ?
+            '''
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "15:0"
+          name: "TID_TR"
+          resval: 0x0
+          desc: '''Transfer status bitfield:
+                TID_TR[i]=1'b1 means that transfer with TID i is active.
+		'''
+        }
+        { bits: "31:16"
+          name: "TID_ALLOC"
+          resval: 0x0
+          desc: '''Transfer status bitfield:
+                - TID_TR[i]=1'b0 means that transfer allocator with TID i-16 is free.
+                - TID_TR[i]=1'b1 means that transfer allocator with TID i-16 is reserved.
+                '''
+        }
+      ]
+    }
+    { name: "TID_FREE"
+      desc: "Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i."
+      swaccess: "wo"
+      hwaccess: "hro"
+      fields: [
+        { bits: "15:0"
+          name: "tid_free"
+          resval: 0x0
+          desc: "Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i."
+        }
+      ]
+    }
+  ]
+}
diff --git a/hw/regs/carfield_regs_Doc.hjson b/hw/regs/carfield_regs_Doc.hjson
new file mode 100644
index 00000000..dad20d5d
--- /dev/null
+++ b/hw/regs/carfield_regs_Doc.hjson
@@ -0,0 +1,713 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Robert Balas <balasr@iis.ee.ethz.ch>
+// Luca Valente <luca.valente@unibo.it>
+{
+  name: "carfield",
+  cip_id: "2",
+  version: "1.0.1",
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", idle: "idle_o", primary: true}
+  ],
+  bus_interfaces: [
+    { protocol: "tlul", direction: "device" }
+  ],
+  regwidth: "32",
+  registers :[
+
+    { name: "VERSION0",
+      desc: "Cheshire sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION1",
+      desc: "Safety Island sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION2",
+      desc: "Security Island sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION3",
+      desc: "PULP Cluster sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "VERSION4",
+      desc: "Spatz CLuster sha256 commit",
+      swaccess: "ro",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "JEDEC_IDCODE",
+      desc: "JEDEC ID CODE -TODO assign-",
+      swaccess: "rw",
+      hwaccess: "none",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "GENERIC_SCRATCH0",
+      desc: "Scratch",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "GENERIC_SCRATCH1",
+      desc: "Scratch",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "HOST_RST",
+      desc: "Host Domain reset -active high, inverted in HW-",
+      swaccess: "ro",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_RST",
+      desc: "Periph Domain reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_RST",
+      desc: "Safety Island reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_RST",
+      desc: "Security Island reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_RST",
+      desc: "PULP Cluster reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_RST",
+      desc: "Spatz Cluster reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_RST",
+      desc: "L2 reset -active high, inverted in HW-",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_ISOLATE",
+      desc: "Periph Domain  AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_ISOLATE",
+      desc: "Safety Island AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_ISOLATE",
+      desc: "Security Island AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_ISOLATE",
+      desc: "PULP Cluster AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_ISOLATE",
+      desc: "Spatz Cluster AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_ISOLATE",
+      desc: "L2 AXI isolate",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_ISOLATE_STATUS",
+      desc: "Periph Domain AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_ISOLATE_STATUS",
+      desc: "Safety Island AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_ISOLATE_STATUS",
+      desc: "Security Island AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_ISOLATE_STATUS",
+      desc: "PULP Cluster AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_ISOLATE_STATUS",
+      desc: "Spatz Cluster AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_ISOLATE_STATUS",
+      desc: "L2 AXI isolate status",
+      swaccess: "rw",
+      hwaccess: "hwo",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_CLK_EN",
+      desc: "Periph Domain clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_CLK_EN",
+      desc: "Safety Island clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_CLK_EN",
+      desc: "Security Island clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_CLK_EN",
+      desc: "PULP Cluster clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_CLK_EN",
+      desc: "Spatz Cluster clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "L2_CLK_EN",
+      desc: "Shared L2 memory clk gate enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PERIPH_CLK_SEL",
+      desc: "Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "2",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_CLK_SEL",
+      desc: "Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_CLK_SEL",
+      desc: "Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_CLK_SEL",
+      desc: "PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_CLK_SEL",
+      desc: "Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "L2_CLK_SEL",
+      desc: "L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "PERIPH_CLK_DIV_VALUE",
+      desc: "Periph Domain clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_CLK_DIV_VALUE",
+      desc: "Safety Island clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_CLK_DIV_VALUE",
+      desc: "Security Island clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_CLK_DIV_VALUE",
+      desc: "PULP Cluster clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_CLK_DIV_VALUE",
+      desc: "Spatz Cluster clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "L2_CLK_DIV_VALUE",
+      desc: "L2 Memory clk divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "23:0" }
+      ],
+    }
+
+    { name: "HOST_FETCH_ENABLE",
+      desc: "Host Domain fetch enable",
+      swaccess: "ro",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_FETCH_ENABLE",
+      desc: "Safety Island fetch enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_FETCH_ENABLE",
+      desc: "Security Island fetch enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_FETCH_ENABLE",
+      desc: "PULP Cluster fetch enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_DEBUG_REQ",
+      desc: "Spatz Cluster debug req",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+
+    { name: "HOST_BOOT_ADDR",
+      desc: "Host boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x1000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "SAFETY_ISLAND_BOOT_ADDR",
+      desc: "Safety Island boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "SECURITY_ISLAND_BOOT_ADDR",
+      desc: "Security Island boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_BOOT_ADDR",
+      desc: "PULP Cluster boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_BOOT_ADDR",
+      desc: "Spatz Cluster boot address",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0x70000000",
+      hwqe: "0",
+      fields: [
+        { bits: "31:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_BOOT_ENABLE",
+      desc: "PULP Cluster boot enable",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "SPATZ_CLUSTER_BUSY",
+      desc: "Spatz Cluster busy",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_BUSY",
+      desc: "PULP Cluster busy",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "PULP_CLUSTER_EOC",
+      desc: "PULP Cluster end of computation",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      resval: "0",
+      hwqe: "0",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "ETH_RGMII_PHY_CLK_DIV_EN",
+      desc: "Ethernet RGMII PHY clock divider enable bit",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "ETH_RGMII_PHY_CLK_DIV_VALUE",
+      desc: "Ethernet RGMII PHY clock divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "100",
+      hwqe: "1",
+      fields: [
+        { bits: "19:0" }
+      ],
+    }
+
+    { name: "ETH_MDIO_CLK_DIV_EN",
+      desc: "Ethernet MDIO clock divider enable bit",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "1",
+      hwqe: "1",
+      fields: [
+        { bits: "0:0" }
+      ],
+    }
+
+    { name: "ETH_MDIO_CLK_DIV_VALUE",
+      desc: "Ethernet MDIO clock divider value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "100",
+      hwqe: "1",
+      fields: [
+        { bits: "19:0" }
+      ],
+    }
+  ],
+}