From 677cb8bbb6b75bb3f4ec6852ae7f3cfb184c8a3b Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sun, 18 May 2025 16:44:43 +0200 Subject: [PATCH] treewide: Bump PULP cluster to `v3.0.3` * This adds support to new accelerators, namely Neureka and Softex. These, and Redmule, use a fault-tolerant HCI interconnect * Reparametrize the number of pulp cluster cores to 8 (adapt pulp-runtime and regression_tests accordingly) * Cleanup some parameterization in top-level carfield * Rename Cheshire Cfg from `Cfg` to `CheshireCfg` --- Bender.local | 6 +- Bender.lock | 119 +++--- Bender.yml | 2 +- bender-common.mk | 1 + carfield.mk | 10 +- hw/carfield.sv | 318 +++++++-------- hw/carfield_pkg.sv | 374 ++++++++++-------- hw/cheshire_wrap.sv | 101 ++--- hw/l2_wrap.sv | 2 +- sw/tests/bare-metal/pulpd/sw.mk | 6 +- target/sim/src/carfield_fix.sv | 24 +- target/sim/src/vip_carfield_soc.sv | 2 +- target/synth/src/carfield_synth_wrap.sv | 2 +- .../flavor_vanilla/src/carfield_top_xilinx.sv | 4 +- .../carfield_ip/src/carfield_xilinx.sv | 4 +- 15 files changed, 506 insertions(+), 469 deletions(-) diff --git a/Bender.local b/Bender.local index c0f64453..e89e2063 100644 --- a/Bender.local +++ b/Bender.local @@ -7,15 +7,15 @@ overrides: axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics.git , version: 0.8.2 } apb: { git: "https://github.com/pulp-platform/apb.git" , version: 0.2.3 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git" , version: 0.4.1 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git" , rev: "5616a36f5e51d6f07f1c8bca15194077657e197d" } # branch: yt/rapidrecovery + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git" , rev: astral-v0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git" , version: =0.2.13 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git" , version: =0.8.0 } idma: { git: "https://github.com/pulp-platform/idma.git" , version: 0.5.1 } - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git" , rev: a971e364bf8090cf77fafad995b480c1ac7ea4e0 } scm: { git: "https://github.com/pulp-platform/scm.git" , rev: 74426dee36f28ae1c02f7635cf844a0156145320 } - cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix clic: { git: "https://github.com/pulp-platform/clic.git" , rev: 0ff9f07e0a492bff046dfe24399b1e1e82d557b7 } # branch: balasr/dev-2 fpnew: { git: "https://github.com/pulp-platform/cvfpu.git" , rev: pulp-v0.1.3 } cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git" , version: =0.0.0-alpha.4 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git" , rev: 4024f01b1d67cdf1cf9486467d0f2e2f407aa372 } + neureka: { git: "https://github.com/pulp-platform/neureka.git" , rev: f6b9a014c7ff4c536865c8ad376b383d4026f286 } + softex: { git: "https://github.com/belanoa/softex.git" , rev: a93ddff106ca3596660584ce6c7f77fb2a8475e3 } diff --git a/Bender.lock b/Bender.lock index d2e45dc9..5be2b7b8 100644 --- a/Bender.lock +++ b/Bender.lock @@ -33,16 +33,16 @@ packages: - common_verification - tech_cells_generic axi2mem: - revision: 6973e0434d26ba578cdb4aa69c26c1facd1a3f15 - version: null + revision: be0c696709acaee579787ba2432d26ad27640594 + version: 1.0.2 source: Git: https://github.com/pulp-platform/axi2mem.git dependencies: - axi_slice - common_cells axi2per: - revision: a99ef2fac9f3b087671109a27c766f25e8e0f115 - version: 1.0.1 + revision: e8ca052a745e184ca960933b2fe416b725e9ca81 + version: 1.0.2 source: Git: https://github.com/pulp-platform/axi2per.git dependencies: @@ -58,14 +58,6 @@ packages: - common_verification - register_interface - tech_cells_generic - axi_node: - revision: e2d038004c5b8cec9dd3bb9d23ad0bee72f9d908 - version: 1.1.4 - source: - Git: git@github.com:pulp-platform/axi_node.git - dependencies: - - axi - - common_cells axi_obi: revision: null version: null @@ -101,8 +93,8 @@ packages: dependencies: - common_cells axi_vga: - revision: 07be187d1e954d8090031b32d236ad76dc62ce45 - version: 0.1.1 + revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e + version: 0.1.4 source: Git: https://github.com/pulp-platform/axi_vga.git dependencies: @@ -167,15 +159,15 @@ packages: - scm - tech_cells_generic cluster_interconnect: - revision: 89e1019d64a86425211be6200770576cbdf3e8b3 - version: null + revision: 2967d8d17be0a6139229ca8d3d4956e182aec3de + version: 1.3.0 source: Git: https://github.com/pulp-platform/cluster_interconnect.git dependencies: - common_cells cluster_peripherals: - revision: c015839816938a790c8da5fd5829cfc536f1ca9c - version: null + revision: e464eb9ddcc39e5a50009819601c4f213b1d4ba3 + version: 2.2.0 source: Git: https://github.com/pulp-platform/cluster_peripherals.git dependencies: @@ -189,8 +181,8 @@ packages: - common_verification - tech_cells_generic common_verification: - revision: 9c07fa860593b2caabd9b5681740c25fac04b878 - version: 0.2.3 + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] @@ -233,6 +225,14 @@ packages: Git: https://github.com/pulp-platform/event_unit_flex.git dependencies: - common_cells + flex-v: + revision: e9355c2f6ec4c105abdff39489e5d1be93bc4374 + version: null + source: + Git: https://github.com/pulp-platform/flex-v.git + dependencies: + - fpnew + - tech_cells_generic fpnew: revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null @@ -249,36 +249,39 @@ packages: dependencies: - common_cells hci: - revision: b2e6f391aa6c10c03f45b693d80a0aaddecf169b + revision: aed9005c761827c6cbff2ea9a15f9cc37acd1169 version: null source: Git: https://github.com/pulp-platform/hci.git dependencies: - cluster_interconnect + - common_cells - hwpe-stream - l2_tcdm_hybrid_interco + - redundancy_cells + - register_interface hier-icache: - revision: a971e364bf8090cf77fafad995b480c1ac7ea4e0 - version: null + revision: 7243834d2407ca23cff583d57641c84b982bd9bc + version: 1.3.0 source: Git: https://github.com/pulp-platform/hier-icache.git dependencies: - - axi_node + - axi - axi_slice - common_cells - icache-intc - scm - tech_cells_generic hwpe-ctrl: - revision: b7857919ea14b586901ff4282ad7749a3d50501e + revision: a5966201aeeb988d607accdc55da933a53c6a56e version: null source: Git: https://github.com/pulp-platform/hwpe-ctrl.git dependencies: - tech_cells_generic hwpe-stream: - revision: ddc154424187dff42a8fcec946c768ceb13f13de - version: 1.6.4 + revision: 3bc9694705b72a5b9bddc7fcde5091b9e45ba0c8 + version: null source: Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: @@ -304,7 +307,7 @@ packages: revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985 version: 1.0.1 source: - Git: git@github.com:pulp-platform/icache-intc.git + Git: https://github.com/pulp-platform/icache-intc.git dependencies: [] idma: revision: ca1b28816a3706be0bf9ce01378246d5346384f0 @@ -341,12 +344,23 @@ packages: - common_cells - register_interface mchan: - revision: 7f064f205a3e0203e959b14773c4afecf56681ab - version: null + revision: 3f2ae92f78e2ddbd0e079cbb4f81fcc248171c12 + version: 1.2.4 source: Git: https://github.com/pulp-platform/mchan.git dependencies: - common_cells + neureka: + revision: f6b9a014c7ff4c536865c8ad376b383d4026f286 + version: null + source: + Git: https://github.com/pulp-platform/neureka.git + dependencies: + - hci + - hwpe-ctrl + - hwpe-stream + - register_interface + - zeroriscy obi: revision: 0155fc34e900c7c884e081c0a1114a247937ff69 version: 0.1.7 @@ -380,8 +394,8 @@ packages: - register_interface - tech_cells_generic per2axi: - revision: 892fcad60b6374fe558cbde76f4a529d473ba5ca - version: 1.0.4 + revision: 18cf4f2ad51b73de0448843ce0def54ab5fb274b + version: 1.0.5 source: Git: https://github.com/pulp-platform/per2axi.git dependencies: @@ -395,35 +409,37 @@ packages: - axi - common_verification pulp_cluster: - revision: 135d0883d82d58ac803725ef69b027c666df7115 - version: null + revision: 579905eacb7c4b94be91a4e0cb76697acb62b1c3 + version: 3.0.3 source: Git: https://github.com/pulp-platform/pulp_cluster.git dependencies: - axi - axi2mem - axi2per - - axi_slice + - cluster_icache - cluster_interconnect - cluster_peripherals - common_cells - cv32e40p - event_unit_flex + - flex-v - hci - hier-icache - ibex - idma - mchan + - neureka - per2axi - redmule - redundancy_cells - register_interface - - riscv - scm + - softex - tech_cells_generic - timer_unit redmule: - revision: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea + revision: 9223ccc932e21d0667e9c2d30831db41eec9299e version: null source: Git: https://github.com/pulp-platform/redmule.git @@ -434,9 +450,10 @@ packages: - hci - hwpe-ctrl - hwpe-stream + - register_interface - tech_cells_generic redundancy_cells: - revision: 5616a36f5e51d6f07f1c8bca15194077657e197d + revision: 9e31f7c6c24877eaf58279903e7a162b16c9a721 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git @@ -455,14 +472,6 @@ packages: - axi - common_cells - common_verification - riscv: - revision: a1dcae35edae6092ddbf92c424690cb903b678d5 - version: null - source: - Git: git@github.com:AlSaqr-platform/riscv_nn.git - dependencies: - - fpnew - - tech_cells_generic riscv-dbg: revision: 138d74bcaa90c70180c12215db3776813d2a95f2 version: 0.8.0 @@ -508,6 +517,18 @@ packages: - axi - common_cells - register_interface + softex: + revision: a93ddff106ca3596660584ce6c7f77fb2a8475e3 + version: null + source: + Git: https://github.com/belanoa/softex.git + dependencies: + - common_cells + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - ibex spatz: revision: b8fea8f2386f837a0854ad4e84f25b70a3a430e0 version: null @@ -556,3 +577,9 @@ packages: - axi - common_cells - register_interface + zeroriscy: + revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 + version: null + source: + Git: https://github.com/yvantor/ibex.git + dependencies: [] diff --git a/Bender.yml b/Bender.yml index 91ad9843..92762aa6 100644 --- a/Bender.yml +++ b/Bender.yml @@ -17,7 +17,7 @@ dependencies: hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, version: 0.0.9 } dyn_mem: { git: https://github.com/pulp-platform/dyn_spm.git, rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main safety_island: { git: https://github.com/pulp-platform/safety_island.git, rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield - pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 135d0883d82d58ac803725ef69b027c666df7115 } # branch: yt/rapidrecovery + pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, version: 3.0.3 } opentitan: { git: https://github.com/pulp-platform/opentitan.git, rev: 48595339c9bea8eddf7cc799bb74e6af5ec5d846 } # branch: carfield-soc mailbox_unit: { git: git@github.com:pulp-platform/mailbox_unit.git, version: 1.1.0 } apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.3 } diff --git a/bender-common.mk b/bender-common.mk index 4e5ba36f..3a688e48 100644 --- a/bender-common.mk +++ b/bender-common.mk @@ -17,6 +17,7 @@ common_targs += -t cv32e40p_use_ff_regfile common_targs += -t scm_use_fpga_scm common_targs += -t cv64a6_imafdcsclic_sv39 common_targs += -t rtl +common_targs += -t deprecated # Carfield config target. common_targs += -t $(CARFIELD_CONFIG) diff --git a/carfield.mk b/carfield.mk index 2d4ba693..dddfab0b 100644 --- a/carfield.mk +++ b/carfield.mk @@ -57,7 +57,7 @@ include $(CAR_ROOT)/bender-safed.mk ###################### CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git -CAR_NONFREE_COMMIT ?= f21a428 +CAR_NONFREE_COMMIT ?= e7cfa03 ## @section Carfield platform nonfree components ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC @@ -191,12 +191,8 @@ $(SAFED_SW_DIR)/pulp-freertos: $(SAFED_ROOT) $(MAKE) -C $(SAFED_ROOT) pulp-freertos BENDER="$(BENDER)" ## Clone integer PMCA domain's SW stack in the dedicated repository. -pulpd-sw-init: $(PULPD_ROOT) $(PULPD_ROOT)/pulp-runtime $(PULPD_ROOT)/regression-tests - -$(PULPD_ROOT)/pulp-runtime: $(PULPD_ROOT) - $(MAKE) -C $(PULPD_ROOT) pulp-runtime -$(PULPD_ROOT)/regression-tests: $(PULPD_ROOT) - $(MAKE) -C $(PULPD_ROOT) regression-tests +pulpd-sw-init: + $(MAKE) -C $(PULPD_ROOT) sw-init ## Build safe domain SW .PHONY: safed-sw-build diff --git a/hw/carfield.sv b/hw/carfield.sv index c87093e4..5729d043 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -21,7 +21,7 @@ module carfield import tlul_ot_pkg::*; import spatz_cluster_pkg::*; #( - parameter cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault, + parameter cheshire_cfg_t Cfg = carfield_pkg::CheshireCfg, parameter int unsigned HypNumPhys = 2, parameter int unsigned HypNumChips = 2, `ifdef GEN_NO_HYPERBUS // bender-xilinx.mk @@ -173,10 +173,15 @@ module carfield output carfield_debug_sigs_t debug_signals_o ); +`CHESHIRE_TYPEDEF_ALL(carfield_, CheshireCfg) +// Generate indices and get maps for all ports +localparam axi_in_t AxiIn = gen_axi_in(CheshireCfg); +localparam axi_out_t AxiOut = gen_axi_out(CheshireCfg); +localparam int unsigned AxiSlvIdWidth = CheshireCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); + /********************************* * General parameters and defines * **********************************/ -`CHESHIRE_TYPEDEF_ALL(carfield_, Cfg) // Clocking and reset strategy logic periph_rst_n; @@ -203,8 +208,8 @@ logic l2_clk; // verilog_lint: waive-start line-length // Peripheral interrupts -logic [Cfg.NumExtOutIntrs-1:0] chs_intrs_distributed; -logic [Cfg.NumExtIrqHarts-1:0] chs_mti; +logic [CheshireCfg.NumExtOutIntrs-1:0] chs_intrs_distributed; +logic [CheshireCfg.NumExtIrqHarts-1:0] chs_mti; logic [CarfieldNumPeriphsIntrs-1:0] car_periph_intrs; logic car_sys_timer_lo_intr, car_sys_timer_hi_intr, car_sys_timer_lo_intr_sync, car_sys_timer_hi_intr_sync; @@ -271,7 +276,7 @@ assign car_periph_intrs = { // Mailbox unit interrupts -localparam int unsigned CheshireNumIntHarts = Cfg.NumCores; +localparam int unsigned CheshireNumIntHarts = CheshireCfg.NumCores; localparam int unsigned SafedNumIntHarts = 1; localparam int unsigned SecdNumIntHarts = 1; @@ -324,89 +329,83 @@ logic [IntClusterNumCores-1:0] pulpcl_dbg_reqs; logic [MaxHartId:0] safed_dbg_reqs; assign pulpcl_dbg_reqs = safed_dbg_reqs[PulpHartIdOffs+:IntClusterNumCores]; -// Generate indices and get maps for all ports -localparam axi_in_t AxiIn = gen_axi_in(Cfg); -localparam axi_out_t AxiOut = gen_axi_out(Cfg); - /////////////////////////////// // Wide Parameters: A48, D32 // /////////////////////////////// -localparam int unsigned AxiSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(AxiIn.num_in); - // Wide AXI types -typedef logic [ Cfg.AddrWidth-1:0] car_addrw_t; -typedef logic [ Cfg.AxiDataWidth-1:0] car_dataw_t; -typedef logic [(Cfg.AxiDataWidth)/8-1:0] car_strb_t; -typedef logic [ Cfg.AxiUserWidth-1:0] car_usr_t; +typedef logic [ CheshireCfg.AddrWidth-1:0] car_addrw_t; +typedef logic [ CheshireCfg.AxiDataWidth-1:0] car_dataw_t; +typedef logic [(CheshireCfg.AxiDataWidth)/8-1:0] car_strb_t; +typedef logic [ CheshireCfg.AxiUserWidth-1:0] car_usr_t; typedef logic [ AxiSlvIdWidth-1:0] car_slv_id_t; // Slave CDC parameters localparam int unsigned CarfieldAxiSlvAwWidth = - (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth , + (2**LogDepth)*axi_pkg::aw_width(CheshireCfg.AddrWidth , AxiSlvIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); localparam int unsigned CarfieldAxiSlvWWidth = - (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth); + (2**LogDepth)*axi_pkg::w_width(CheshireCfg.AxiDataWidth, + CheshireCfg.AxiUserWidth); localparam int unsigned CarfieldAxiSlvBWidth = (2**LogDepth)*axi_pkg::b_width(AxiSlvIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); localparam int unsigned CarfieldAxiSlvArWidth = - (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth , + (2**LogDepth)*axi_pkg::ar_width(CheshireCfg.AddrWidth , AxiSlvIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); localparam int unsigned CarfieldAxiSlvRWidth = - (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth, + (2**LogDepth)*axi_pkg::r_width(CheshireCfg.AxiDataWidth, AxiSlvIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); // Master CDC parameters localparam int unsigned CarfieldAxiMstAwWidth = - (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth , - Cfg.AxiMstIdWidth, - Cfg.AxiUserWidth ); + (2**LogDepth)*axi_pkg::aw_width(CheshireCfg.AddrWidth , + CheshireCfg.AxiMstIdWidth, + CheshireCfg.AxiUserWidth ); localparam int unsigned CarfieldAxiMstWWidth = - (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth); + (2**LogDepth)*axi_pkg::w_width(CheshireCfg.AxiDataWidth, + CheshireCfg.AxiUserWidth); localparam int unsigned CarfieldAxiMstBWidth = - (2**LogDepth)*axi_pkg::b_width(Cfg.AxiMstIdWidth, - Cfg.AxiUserWidth ); + (2**LogDepth)*axi_pkg::b_width(CheshireCfg.AxiMstIdWidth, + CheshireCfg.AxiUserWidth ); localparam int unsigned CarfieldAxiMstArWidth = - (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth , - Cfg.AxiMstIdWidth, - Cfg.AxiUserWidth ); + (2**LogDepth)*axi_pkg::ar_width(CheshireCfg.AddrWidth , + CheshireCfg.AxiMstIdWidth, + CheshireCfg.AxiUserWidth ); localparam int unsigned CarfieldAxiMstRWidth = - (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth , - Cfg.AxiMstIdWidth, - Cfg.AxiUserWidth ); + (2**LogDepth)*axi_pkg::r_width(CheshireCfg.AxiDataWidth , + CheshireCfg.AxiMstIdWidth, + CheshireCfg.AxiUserWidth ); // External register interface synchronous with Cheshire's clock domain carfield_reg_req_t [iomsb(NumSyncRegSlv):0] ext_reg_req, ext_reg_req_cut; carfield_reg_rsp_t [iomsb(NumSyncRegSlv):0] ext_reg_rsp, ext_reg_rsp_cut; `ifndef GEN_NO_HYPERBUS // bender-xilinx.mk -localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth + +localparam int unsigned LlcIdWidth = CheshireCfg.AxiMstIdWidth + $clog2(AxiIn.num_in)+ - Cfg.LlcNotBypass ; + CheshireCfg.LlcNotBypass ; localparam int unsigned LlcArWidth = (2**LogDepth)* - axi_pkg::ar_width(Cfg.AddrWidth , + axi_pkg::ar_width(CheshireCfg.AddrWidth , LlcIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); localparam int unsigned LlcAwWidth = (2**LogDepth)* - axi_pkg::aw_width(Cfg.AddrWidth , + axi_pkg::aw_width(CheshireCfg.AddrWidth , LlcIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); localparam int unsigned LlcBWidth = (2**LogDepth)* axi_pkg::b_width(LlcIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); localparam int unsigned LlcRWidth = (2**LogDepth)* - axi_pkg::r_width(Cfg.AxiDataWidth, + axi_pkg::r_width(CheshireCfg.AxiDataWidth, LlcIdWidth , - Cfg.AxiUserWidth); + CheshireCfg.AxiUserWidth); localparam int unsigned LlcWWidth = (2**LogDepth)* - axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth ); + axi_pkg::w_width(CheshireCfg.AxiDataWidth, + CheshireCfg.AxiUserWidth ); logic [LlcArWidth-1:0] llc_ar_data; logic [ LogDepth:0] llc_ar_wptr; @@ -429,8 +428,8 @@ logic [ LogDepth:0] llc_w_rptr; logic hyper_isolate_req, hyper_isolated_rsp; logic security_island_isolate_req; -logic [iomsb(Cfg.AxiExtNumSlv):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; -logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp; +logic [iomsb(CheshireCfg.AxiExtNumSlv):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; +logic [iomsb(CheshireCfg.AxiExtNumMst):0] master_isolated_rsp; // All AXI Slaves (the Mailbox) logic [iomsb(NumSlaveCDCs):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data; @@ -450,21 +449,21 @@ logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_wptr ; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_rptr ; // All AXI Masters -logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_wptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_rptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_wptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_rptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_wptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_rptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_wptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_rptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_wptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_rptr ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_wptr; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_rptr; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_wptr ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_rptr ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_wptr ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_rptr ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_wptr; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_rptr; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_wptr ; +logic [iomsb(CheshireCfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_rptr ; // soc reg signals carfield_reg2hw_t car_regs_reg2hw; @@ -739,7 +738,7 @@ assign chs_ext_intrs = { `ifndef CHS_NETLIST cheshire_wrap #( - .Cfg ( Cfg ), + .Cfg ( CheshireCfg ), .ExtHartinfo ( '0 ), .NumExtIntrs ( CarfieldNumExtIntrs ), .cheshire_axi_ext_llc_ar_chan_t ( carfield_axi_llc_ar_chan_t ), @@ -912,10 +911,10 @@ hyperbus_wrap #( .NumChips ( HypNumChips ), .NumPhys ( HypNumPhys ), .IsClockODelayed ( 1'b0 ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), .AxiIdWidth ( LlcIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), .axi_req_t ( carfield_axi_llc_req_t ), .axi_rsp_t ( carfield_axi_llc_rsp_t ), .axi_w_chan_t ( carfield_axi_llc_w_chan_t ), @@ -929,7 +928,7 @@ hyperbus_wrap #( .reg_rsp_t ( carfield_a32_d32_reg_rsp_t ), .RxFifoLogDepth ( 32'd2 ), .TxFifoLogDepth ( 32'd2 ), - .RstChipBase ( Cfg.LlcOutRegionStart ), + .RstChipBase ( CheshireCfg.LlcOutRegionStart ), .RstChipSpace ( HypNumPhys * HypNumChips * 'h800_0000 ), .PhyStartupCycles ( 300 * 200 ), .AxiLogDepth ( LogDepth ), @@ -938,7 +937,7 @@ hyperbus_wrap #( .AxiSlaveBWidth ( LlcBWidth ), .AxiSlaveRWidth ( LlcRWidth ), .AxiSlaveWWidth ( LlcWWidth ), - .AxiMaxTrans ( Cfg.AxiMaxSlvTrans ), + .AxiMaxTrans ( CheshireCfg.AxiMaxSlvTrans ), .CdcSyncStages ( SyncStages ) ) i_hyperbus_wrap ( .clk_i ( periph_clk ), @@ -1026,25 +1025,25 @@ if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2 `ifndef L2_WRAP_NETLIST l2_wrap #( - .Cfg ( Cfg ), + .Cfg ( CheshireCfg ), .NumPort ( NumL2Ports ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxTrans ( Cfg.AxiMaxSlvTrans ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), + .AxiMaxTrans ( CheshireCfg.AxiMaxSlvTrans ), .LogDepth ( LogDepth ), .CdcSyncStages( SyncStages ), .NumRules ( L2NumRules ), .L2MemSize ( L2MemSize ), // Atomics - .L2MaxReadTxns ( Cfg.LlcMaxReadTxns ), // TODO: AMO parameters are default + .L2MaxReadTxns ( CheshireCfg.LlcMaxReadTxns ), // TODO: AMO parameters are default // from the LLC (Cheshire), at the // moment - .L2MaxWriteTxns ( Cfg.LlcMaxWriteTxns ), - .AxiUserAmoMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserAmoLsb ( Cfg.AxiUserAmoLsb ), - .L2AmoNumCuts ( Cfg.LlcAmoNumCuts ), + .L2MaxWriteTxns ( CheshireCfg.LlcMaxWriteTxns ), + .AxiUserAmoMsb ( CheshireCfg.AxiUserAmoMsb ), + .AxiUserAmoLsb ( CheshireCfg.AxiUserAmoLsb ), + .L2AmoNumCuts ( CheshireCfg.LlcAmoNumCuts ), .l2_ecc_reg_req_t ( carfield_reg_req_t ), .l2_ecc_reg_rsp_t ( carfield_reg_rsp_t ) ) i_reconfigurable_l2 ( @@ -1168,17 +1167,17 @@ if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island safety_island_synth_wrapper #( .SafetyIslandCfg ( SafetyIslandCfg ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), .AxiInIdWidth ( AxiSlvIdWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + .AxiOutIdWidth ( CheshireCfg.AxiMstIdWidth ), .AxiUserAtop ( 1'b1 ), - .AxiUserAtopMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserAtopLsb ( Cfg.AxiUserAmoLsb ), - .AxiUserEccErr ( Cfg.AxiUserErrBits ), - .AxiUserEccErrBit ( Cfg.AxiUserErrLsb ), + .AxiUserAtopMsb ( CheshireCfg.AxiUserAmoMsb ), + .AxiUserAtopLsb ( CheshireCfg.AxiUserAmoLsb ), + .AxiUserEccErr ( CheshireCfg.AxiUserErrBits ), + .AxiUserEccErrBit ( CheshireCfg.AxiUserErrLsb ), .DefaultUser ( 10'b00000_0_0101 ), .LogDepth ( LogDepth ), @@ -1320,52 +1319,15 @@ if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster assign slave_isolated[IntClusterSlvIdx] = slave_isolated_rsp[IntClusterSlvIdx] & master_isolated_rsp[IntClusterMstIdx]; + localparam pulp_cluster_package::pulp_cluster_cfg_t IntegerClusterCfg + = gen_int_cluster_cfg(CheshireCfg); + `ifndef INT_CLUSTER_NETLIST pulp_cluster #( - .NB_CORES ( IntClusterNumCores ), - .NB_HWPE_PORTS ( IntClusterNumHwpePorts ), - .NB_DMAS ( IntClusterNumDmas ), - .NB_MPERIPHS ( IntClusterNumMstPer ), - .NB_SPERIPHS ( IntClusterNumSlvPer ), - .SynchStages ( SyncStages ), - .TCDM_SIZE ( IntClusterTcdmSize ), - .NB_TCDM_BANKS ( IntClusterTcdmBanks ), - .HWPE_PRESENT ( IntClusterHwpePresent ), - .USE_HETEROGENEOUS_INTERCONNECT ( IntClusterUseHci ), - .SET_ASSOCIATIVE ( IntClusterSetAssociative ), - .NB_CACHE_BANKS ( IntClusterNumCacheBanks ), - .CACHE_LINE ( IntClusterNumCacheLines ), - .CACHE_SIZE ( IntClusterCacheSize ), - .L0_BUFFER_FEATURE ( "DISABLED" ), - .MULTICAST_FEATURE ( "DISABLED" ), - .SHARED_ICACHE ( "ENABLED" ), - .DIRECT_MAPPED_FEATURE ( "DISABLED" ), - .L2_SIZE ( L2MemSize ), - .USE_REDUCED_TAG ( "TRUE" ), - .DEBUG_START_ADDR ( IntClusterDbgStart ), - .ROM_BOOT_ADDR ( IntClusterBootAddr ), - .BOOT_ADDR ( IntClusterBootAddr ), - .INSTR_RDATA_WIDTH ( IntClusterInstrRdataWidth ), - .CLUST_FPU ( IntClusterFpu ), - .CLUST_FP_DIVSQRT ( IntClusterFpuDivSqrt ), - .CLUST_SHARED_FP ( IntClusterFpu ), - .CLUST_SHARED_FP_DIVSQRT ( IntClusterFpuDivSqrt ), - .NumAxiMst ( IntClusterNumAxiMst ), - .NumAxiSlv ( IntClusterNumAxiSlv ), - .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), - .AXI_DATA_C2S_WIDTH ( Cfg.AxiDataWidth ), - .AXI_DATA_S2C_WIDTH ( Cfg.AxiDataWidth ), - .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), - .AXI_ID_IN_WIDTH ( AxiSlvIdWidth ), - .AXI_ID_OUT_WIDTH ( Cfg.AxiMstIdWidth ), - .AXI_MAX_IN_TRANS ( Cfg.AxiMaxSlvTrans ), - .AXI_MAX_OUT_TRANS ( Cfg.AxiMaxSlvTrans ), - .LOG_DEPTH ( LogDepth ), - .BaseAddr ( CarfieldIslandsCfg.pulp.base ), - .CdcSynchStages ( SyncStages ) - ) i_integer_cluster ( + .Cfg ( IntegerClusterCfg ) + ) i_integer_cluster ( `else - int_cluster i_integer_cluster ( + int_cluster i_integer_cluster ( `endif .clk_i ( pulp_clk ), .rst_ni ( pulp_rst_n ), @@ -1374,7 +1336,7 @@ if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster .pmu_mem_pwdn_i ( '0 ), .base_addr_i ( CarfieldIslandsCfg.pulp.base[31:28] ), .test_mode_i ( test_mode_i ), - .cluster_id_i ( IntClusterIndex ), + .cluster_id_i ( carfield_pkg::IntClusterIndex ), .en_sa_boot_i ( car_regs_reg2hw.pulp_cluster_boot_enable ), .fetch_en_i ( car_regs_reg2hw.pulp_cluster_fetch_enable ), .eoc_o ( car_regs_hw2reg.pulp_cluster_eoc.d ), @@ -1495,11 +1457,11 @@ if (CarfieldIslandsCfg.spatz.enable) begin : gen_spatz_cluster `ifndef FP_CLUSTER_NETLIST spatz_cluster_wrapper #( - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiInIdWidth ( AxiSlvIdWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), + .AxiInIdWidth ( AxiSlvIdWidth ), + .AxiOutIdWidth ( CheshireCfg.AxiMstIdWidth ), .IwcAxiIdOutWidth ( FpClustIwcAxiIdOutWidth ), .LogDepth ( LogDepth ), .CdcSyncStages ( SyncStages ), @@ -1664,14 +1626,14 @@ if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem `ifndef SECD_NETLIST secure_subsystem_synth_wrap #( .HartIdOffs ( OpnTitHartIdOffs ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), - .AxiOtAddrWidth ( Cfg.AddrWidth ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), + .AxiOutIdWidth ( CheshireCfg.AxiMstIdWidth ), + .AxiOtAddrWidth ( CheshireCfg.AddrWidth ), .AxiOtDataWidth ( AxiNarrowDataWidth ), // TODO: why is this exposed? - .AxiOtUserWidth ( Cfg.AxiUserWidth ), - .AxiOtOutIdWidth ( Cfg.AxiMstIdWidth ), + .AxiOtUserWidth ( CheshireCfg.AxiUserWidth ), + .AxiOtOutIdWidth ( CheshireCfg.AxiMstIdWidth ), .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), @@ -1783,15 +1745,15 @@ axi_cut #( // Shim atomics, which are not supported in reg // TODO: should we use a filter instead here? axi_riscv_atomics_structs #( - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxReadTxns ( Cfg.RegMaxReadTxns ), - .AxiMaxWriteTxns ( Cfg.RegMaxWriteTxns ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), + .AxiIdWidth ( AxiSlvIdWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), + .AxiMaxReadTxns ( CheshireCfg.RegMaxReadTxns ), + .AxiMaxWriteTxns ( CheshireCfg.RegMaxWriteTxns ), .AxiUserAsId ( 1 ), - .AxiUserIdMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), + .AxiUserIdMsb ( CheshireCfg.AxiUserAmoMsb ), + .AxiUserIdLsb ( CheshireCfg.AxiUserAmoLsb ), .RiscvWordWidth ( 64 ), .NAxiCuts ( 0 ), .axi_req_t ( carfield_axi_slv_req_t ), @@ -1799,15 +1761,15 @@ axi_riscv_atomics_structs #( ) i_atomics_mbox ( .clk_i ( host_clk_i ), .rst_ni ( host_pwr_on_rst_n ), - .axi_slv_req_i ( axi_pre_amo_cut_mbox_req ), - .axi_slv_rsp_o ( axi_pre_amo_cut_mbox_rsp ), + .axi_slv_req_i ( axi_pre_amo_cut_mbox_req ), + .axi_slv_rsp_o ( axi_pre_amo_cut_mbox_rsp ), .axi_mst_req_o ( axi_amo_mbox_req ), .axi_mst_rsp_i ( axi_amo_mbox_rsp ) ); // AXI cut axi_cut #( - .Bypass ( ~Cfg.RegAmoPostCut ), + .Bypass ( ~CheshireCfg.RegAmoPostCut ), .aw_chan_t ( carfield_axi_slv_aw_chan_t ), .w_chan_t ( carfield_axi_slv_w_chan_t ), .b_chan_t ( carfield_axi_slv_b_chan_t ), @@ -1829,10 +1791,10 @@ carfield_reg_req_t reg_mbox_req; carfield_reg_rsp_t reg_mbox_rsp; axi_to_reg_v2 #( - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), .RegDataWidth ( AxiNarrowDataWidth ), // 32-bit .axi_req_t ( carfield_axi_slv_req_t ), .axi_rsp_t ( carfield_axi_slv_rsp_t ), @@ -1906,10 +1868,10 @@ if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet ); AXI_BUS #( - .AXI_ADDR_WIDTH( Cfg.AddrWidth ), - .AXI_DATA_WIDTH( Cfg.AxiDataWidth ), + .AXI_ADDR_WIDTH( CheshireCfg.AddrWidth ), + .AXI_DATA_WIDTH( CheshireCfg.AxiDataWidth ), .AXI_ID_WIDTH ( AxiSlvIdWidth ), - .AXI_USER_WIDTH( Cfg.AxiUserWidth ) + .AXI_USER_WIDTH( CheshireCfg.AxiUserWidth ) ) axi_ethernet (); `AXI_ASSIGN_FROM_REQ(axi_ethernet, axi_ethernet_req); @@ -2009,10 +1971,10 @@ if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet // Ethernet IP eth_rgmii #( - .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), - .AXI_DATA_WIDTH ( Cfg.AxiDataWidth ), + .AXI_ADDR_WIDTH ( CheshireCfg.AddrWidth ), + .AXI_DATA_WIDTH ( CheshireCfg.AxiDataWidth ), .AXI_ID_WIDTH ( AxiSlvIdWidth ), - .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) + .AXI_USER_WIDTH ( CheshireCfg.AxiUserWidth ) ) i_eth_rgmii ( .clk_i ( eth_mdio_clk ), /* Clock 200MHz */ @@ -2119,17 +2081,17 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... // Shim atomics, which are not supported in reg // TODO: should we use a filter instead here? axi_riscv_atomics_structs #( - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxReadTxns ( Cfg.RegMaxReadTxns ), - .AxiMaxWriteTxns ( Cfg.RegMaxWriteTxns ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), + .AxiDataWidth ( CheshireCfg.AxiDataWidth ), + .AxiIdWidth ( AxiSlvIdWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), + .AxiMaxReadTxns ( CheshireCfg.RegMaxReadTxns ), + .AxiMaxWriteTxns ( CheshireCfg.RegMaxWriteTxns ), .AxiUserAsId ( 1 ), - .AxiUserIdMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), + .AxiUserIdMsb ( CheshireCfg.AxiUserAmoMsb ), + .AxiUserIdLsb ( CheshireCfg.AxiUserAmoLsb ), .RiscvWordWidth ( 64 ), - .NAxiCuts ( Cfg.RegAmoNumCuts ), + .NAxiCuts ( CheshireCfg.RegAmoNumCuts ), .axi_req_t ( carfield_axi_slv_req_t ), .axi_rsp_t ( carfield_axi_slv_rsp_t ) ) i_atomics_peripherals ( @@ -2145,7 +2107,7 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... carfield_axi_slv_rsp_t axi_d64_a48_amo_cut_peripherals_rsp; axi_cut #( - .Bypass ( ~Cfg.RegAmoPostCut ), + .Bypass ( ~CheshireCfg.RegAmoPostCut ), .aw_chan_t ( carfield_axi_slv_aw_chan_t ), .w_chan_t ( carfield_axi_slv_w_chan_t ), .b_chan_t ( carfield_axi_slv_b_chan_t ), @@ -2171,9 +2133,9 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... carfield_axi_d32_a48_slv_rsp_t axi_d32_a48_peripherals_rsp; axi_dw_converter #( - .AxiSlvPortDataWidth ( Cfg.AxiDataWidth ), + .AxiSlvPortDataWidth ( CheshireCfg.AxiDataWidth ), .AxiMstPortDataWidth ( AxiNarrowDataWidth ), - .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiAddrWidth ( CheshireCfg.AddrWidth ), .AxiIdWidth ( AxiSlvIdWidth ), .aw_chan_t ( carfield_axi_slv_aw_chan_t ), .mst_w_chan_t ( carfield_axi_d32_a48_slv_w_chan_t ), @@ -2229,7 +2191,7 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... .AxiAddrWidth ( AxiNarrowAddrWidth ), .AxiDataWidth ( AxiNarrowDataWidth ), .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiUserWidth ( CheshireCfg.AxiUserWidth ), .AxiMaxWriteTxns( 1 ), .AxiMaxReadTxns ( 1 ), .FallThrough ( 1 ), diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index d3701bdd..9fd14db2 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -451,9 +451,10 @@ typedef enum hartid_t { localparam int unsigned MaxHartId = 63; -localparam int unsigned IntClusterNumCores = 12; +localparam int unsigned IntClusterNumCores = 8; localparam bit [MaxHartId:0] SafetyIslandExtHarts = {MaxHartId+1{1'b0}} | (((1<> 6); localparam dm::hartinfo_t PulpHartInfo = '{ zero1: '0, @@ -476,40 +477,119 @@ endfunction localparam dm::hartinfo_t [MaxHartId:0] SafetyIslandExtHartinfo = pulp_hart_info(SafetyIslandExtHarts); -// Safety island configuration -localparam safety_island_pkg::safety_island_cfg_t SafetyIslandCfg = '{ - HartId: SafetyIslHartIdOffs, - BankNumBytes: 32'h0001_0000, - NumBanks: 2, - // JTAG ID code: - // LSB [0]: 1'h1 - // PULP Platform Manufacturer [11:1]: 11'h6d9 - // Part Number [27:12]: 16'hca71 - // Version [31:28]: 4'h1 - PulpJtagIdCode: 32'h1_ca71_db3, - NumTimers: 1, - UseClic: 1, - ClicIntCtlBits: 8, - UseSSClic: 0, - UseUSClic: 0, - UseVSClic: 0, - UseVSPrio: 0, - NVsCtxts: 0, - UseFastIrq: 1, - UseFpu: 1, - UseIntegerCluster: 1, - UseXPulp: 1, - UseZfinx: 1, - UseTCLS: 1, - NumInterrupts: 128, - NumMhpmCounters: 1, - // All non-set values should be zero - default: '0 +// CDC FIFO parameters (FIFO depth). +localparam int unsigned LogDepth = 3; + +/*****************/ +/* L2 Parameters */ +/*****************/ +localparam int unsigned NumL2Ports = (CarfieldIslandsCfg.l2_port1.enable) ? 2 : 1; +localparam int unsigned L2MemSize = CarfieldIslandsCfg.l2_port0.size/2; +localparam int unsigned L2NumRules = 4; // 2 rules per each access mode + // (interleaved, non-interleaved) +localparam doub_bt L2Port0InterlBase = CarfieldIslandsCfg.l2_port0.base; +localparam doub_bt L2Port1InterlBase = CarfieldIslandsCfg.l2_port1.base; +localparam doub_bt L2Port0NonInterlBase = CarfieldIslandsCfg.l2_port0.base + L2MemSize; +localparam doub_bt L2Port1NonInterlBase = CarfieldIslandsCfg.l2_port1.base + L2MemSize; + +/****************************/ +/* Safety Island Parameters */ +/****************************/ +localparam int unsigned SafetyIslandMemOffset = 'h0000_0000; +localparam int unsigned SafetyIslandPerOffset = 'h0020_0000; + +/******************************/ +/* Integer Cluster Parameters */ +/******************************/ +localparam int unsigned IntClusterDbgStart = CarfieldIslandsCfg.safed.base+ + SafetyIslandPerOffset+ + safety_island_pkg::DebugAddrOffset; +localparam int unsigned IntClusterBootAddrDefaultOffs = 'h8080; +localparam int unsigned IntClusterBootAddr = CarfieldIslandsCfg.l2_port0.base + + IntClusterBootAddrDefaultOffs; +localparam int unsigned IntClusterNumEoc = 1; + +/*************************************/ +/* Floating Point Cluster Parameters */ +/*************************************/ +localparam int unsigned FpClustAxiMaxOutTrans = 4; +localparam int unsigned FpClustIwcAxiIdOutWidth = 3; + +/*******************************/ +/* Narrow Parameters: A32, D32 */ +/*******************************/ +localparam int unsigned AxiNarrowAddrWidth = 32; +localparam int unsigned AxiNarrowDataWidth = 32; +localparam int unsigned AxiNarrowStrobe = AxiNarrowDataWidth/8; + +// Narrow AXI types +typedef logic [ AxiNarrowAddrWidth-1:0] car_nar_addrw_t; +typedef logic [ AxiNarrowDataWidth-1:0] car_nar_dataw_t; +typedef logic [ AxiNarrowStrobe-1:0] car_nar_strb_t; + +// APB Mapping +localparam int unsigned NumApbMst = 5; + +typedef enum int { + SystemTimerIdx = 'd0, + AdvancedTimerIdx = 'd1, + SystemWdtIdx = 'd2, + CanIdx = 'd3, + HyperBusIdx = 'd4 +} carfield_peripherals_e; + +// Address map of peripheral system +typedef struct packed { + logic [31:0] idx; + car_nar_addrw_t start_addr; + car_nar_addrw_t end_addr; +} carfield_addr_map_rule_t; + +localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ + // 0: System Timer + '{ idx: SystemTimerIdx, start_addr: SystemTimerBase, + end_addr: SystemTimerBase + SystemTimerSize }, + // 1: Advanced Timer + '{ idx: AdvancedTimerIdx, start_addr: SystemAdvancedTimerBase, + end_addr: SystemAdvancedTimerBase + SystemAdvancedTimerSize }, + // 2: WDT + '{ idx: SystemWdtIdx, start_addr: SystemWatchdogBase, + end_addr: SystemWatchdogBase + SystemWatchdogSize }, + // 3: Can + '{ idx: CanIdx, start_addr: CanBase, + end_addr: CanBase + CanSize }, + // 4: Hyperbus + '{ idx: HyperBusIdx, start_addr: HyperBusBase, + end_addr: HyperBusBase + HyperBusSize } }; +// Narrow reg types +`REG_BUS_TYPEDEF_ALL(carfield_a32_d32_reg, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) + + +////////////////////////////// +// Debug Signal Port Struct // +////////////////////////////// + + +// 6 clock gateable Subdomains in Carfield: periph_domain, safety_island, security_isalnd, spatz & +// pulp_cluster, L2 shared memory +localparam int unsigned NumDomains = CarfieldNumDomains; + +typedef struct packed { + logic [NumDomains-1:0] domain_clk; + logic [NumDomains-1:0] domain_rsts_n; + logic host_pwr_on_rst_n; +} carfield_debug_sigs_t; + +/////////////////////////// +// Islands configuration // +/////////////////////////// + // verilog_lint: waive-start line-length + // Cheshire configuration -localparam cheshire_cfg_t CarfieldCfgDefault = '{ +localparam cheshire_cfg_t CheshireCfg = '{ // CVA6 parameters Cva6RASDepth : ariane_pkg::ArianeDefaultConfig.RASDepth, Cva6BTBEntries : ariane_pkg::ArianeDefaultConfig.BTBEntries, @@ -645,139 +725,109 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ // All non-set values should be zero default: '0 }; -// verilog_lint: waive-stop line-length -// CDC FIFO parameters (FIFO depth). -localparam int unsigned LogDepth = 3; - -/*****************/ -/* L2 Parameters */ -/*****************/ -localparam int unsigned NumL2Ports = (CarfieldIslandsCfg.l2_port1.enable) ? 2 : 1; -localparam int unsigned L2MemSize = CarfieldIslandsCfg.l2_port0.size/2; -localparam int unsigned L2NumRules = 4; // 2 rules per each access mode - // (interleaved, non-interleaved) -localparam doub_bt L2Port0InterlBase = CarfieldIslandsCfg.l2_port0.base; -localparam doub_bt L2Port1InterlBase = CarfieldIslandsCfg.l2_port1.base; -localparam doub_bt L2Port0NonInterlBase = CarfieldIslandsCfg.l2_port0.base + L2MemSize; -localparam doub_bt L2Port1NonInterlBase = CarfieldIslandsCfg.l2_port1.base + L2MemSize; - -/****************************/ -/* Safety Island Parameters */ -/****************************/ -localparam int unsigned SafetyIslandMemOffset = 'h0000_0000; -localparam int unsigned SafetyIslandPerOffset = 'h0020_0000; - -/******************************/ -/* Integer Cluster Parameters */ -/******************************/ -localparam int unsigned IntClusterNumHwpePorts = 9; -localparam int unsigned IntClusterNumDmas = 4; -localparam int unsigned IntClusterNumMstPer = 1; -localparam int unsigned IntClusterNumSlvPer = 10; -localparam int unsigned IntClusterTcdmSize = 256*1024; -localparam int unsigned IntClusterTcdmBanks = 16; -localparam int unsigned IntClusterHwpePresent = 1; -localparam int unsigned IntClusterUseHci = 1; -localparam int unsigned IntClusterSetAssociative = 4; -localparam int unsigned IntClusterNumCacheBanks = 2; -localparam int unsigned IntClusterNumCacheLines = 1; -localparam int unsigned IntClusterCacheSize = 4*1024; -localparam int unsigned IntClusterDbgStart = CarfieldIslandsCfg.safed.base+ - SafetyIslandPerOffset+ - safety_island_pkg::DebugAddrOffset; -localparam int unsigned IntClusterBootAddrDefaultOffs = 'h8080; -localparam int unsigned IntClusterBootAddr = CarfieldIslandsCfg.l2_port0.base + - IntClusterBootAddrDefaultOffs; -localparam int unsigned IntClusterInstrRdataWidth = 32; -localparam int unsigned IntClusterFpu = 0; -localparam int unsigned IntClusterFpuDivSqrt = 0; -localparam int unsigned IntClusterSharedFpu = 0; -localparam int unsigned IntClusterSharedFpuDivSqrt = 0; -localparam int unsigned IntClusterNumAxiMst = 3; -localparam int unsigned IntClusterNumAxiSlv = 4; -// IntClusterAxiIdInWidth is fixed from PULP Cluster -localparam int unsigned IntClusterAxiIdInWidth = $clog2(IntClusterNumCacheBanks) + 3; -localparam int unsigned IntClusterAxiIdOutWidth = IntClusterAxiIdInWidth + - $clog2(IntClusterNumAxiSlv); -localparam int unsigned IntClusterMaxUniqId = 1; -localparam int unsigned IntClusterNumEoc = 1; -localparam logic [ 5:0] IntClusterIndex = (PulpHartIdOffs >> 5); -localparam logic [CarfieldCfgDefault.AddrWidth-1:0] IntClusterInternalSize = 'h0040_0000; - -/*************************************/ -/* Floating Point Cluster Parameters */ -/*************************************/ -localparam int unsigned FpClustAxiMaxOutTrans = 4; -localparam int unsigned FpClustIwcAxiIdOutWidth = 3; - -/*******************************/ -/* Narrow Parameters: A32, D32 */ -/*******************************/ -localparam int unsigned AxiNarrowAddrWidth = 32; -localparam int unsigned AxiNarrowDataWidth = 32; -localparam int unsigned AxiNarrowStrobe = AxiNarrowDataWidth/8; - -// Narrow AXI types -typedef logic [ AxiNarrowAddrWidth-1:0] car_nar_addrw_t; -typedef logic [ AxiNarrowDataWidth-1:0] car_nar_dataw_t; -typedef logic [ AxiNarrowStrobe-1:0] car_nar_strb_t; -typedef logic [ IntClusterAxiIdInWidth-1:0] intclust_idin_t; -typedef logic [IntClusterAxiIdOutWidth-1:0] intclust_idout_t; - -// APB Mapping -localparam int unsigned NumApbMst = 5; - -typedef enum int { - SystemTimerIdx = 'd0, - AdvancedTimerIdx = 'd1, - SystemWdtIdx = 'd2, - CanIdx = 'd3, - HyperBusIdx = 'd4 -} carfield_peripherals_e; - -// Address map of peripheral system -typedef struct packed { - logic [31:0] idx; - car_nar_addrw_t start_addr; - car_nar_addrw_t end_addr; -} carfield_addr_map_rule_t; - -localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ - // 0: System Timer - '{ idx: SystemTimerIdx, start_addr: SystemTimerBase, - end_addr: SystemTimerBase + SystemTimerSize }, - // 1: Advanced Timer - '{ idx: AdvancedTimerIdx, start_addr: SystemAdvancedTimerBase, - end_addr: SystemAdvancedTimerBase + SystemAdvancedTimerSize }, - // 2: WDT - '{ idx: SystemWdtIdx, start_addr: SystemWatchdogBase, - end_addr: SystemWatchdogBase + SystemWatchdogSize }, - // 3: Can - '{ idx: CanIdx, start_addr: CanBase, - end_addr: CanBase + CanSize }, - // 4: Hyperbus - '{ idx: HyperBusIdx, start_addr: HyperBusBase, - end_addr: HyperBusBase + HyperBusSize } +// Safety island configuration +localparam safety_island_pkg::safety_island_cfg_t SafetyIslandCfg = '{ + HartId: SafetyIslHartIdOffs, + BankNumBytes: 32'h0001_0000, + NumBanks: 2, + // JTAG ID code: + // LSB [0]: 1'h1 + // PULP Platform Manufacturer [11:1]: 11'h6d9 + // Part Number [27:12]: 16'hca71 + // Version [31:28]: 4'h1 + PulpJtagIdCode: 32'h1_ca71_db3, + NumTimers: 1, + UseClic: 1, + ClicIntCtlBits: 8, + UseSSClic: 0, + UseUSClic: 0, + UseVSClic: 0, + UseVSPrio: 0, + NVsCtxts: 0, + UseFastIrq: 1, + UseFpu: 1, + UseIntegerCluster: 1, + UseXPulp: 1, + UseZfinx: 1, + UseTCLS: 1, + NumInterrupts: 128, + NumMhpmCounters: 1, + // All non-set values should be zero + default: '0 }; -// Narrow reg types -`REG_BUS_TYPEDEF_ALL(carfield_a32_d32_reg, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) - - -////////////////////////////// -// Debug Signal Port Struct // -////////////////////////////// - - -// 6 clock gateable Subdomains in Carfield: periph_domain, safety_island, security_isalnd, spatz & -// pulp_cluster, L2 shared memory -localparam int unsigned NumDomains = CarfieldNumDomains; - -typedef struct packed { - logic [NumDomains-1:0] domain_clk; - logic [NumDomains-1:0] domain_rsts_n; - logic host_pwr_on_rst_n; -} carfield_debug_sigs_t; +function automatic pulp_cluster_package::pulp_cluster_cfg_t gen_int_cluster_cfg(cheshire_pkg::cheshire_cfg_t cfg); + axi_in_t AxiIn = gen_axi_in(cfg); + // Base our config on the upstream default + pulp_cluster_package::pulp_cluster_cfg_t ret = pulp_cluster_package::PulpClusterDefaultCfg; + // Modify what we need to + ret.CoreType = pulp_cluster_package::RI5CY; + ret.NumCores = IntClusterNumCores; + ret.DmaNumPlugs = 4; + ret.DmaNumOutstandingBursts = 8; + ret.DmaBurstLength = 256; + ret.NumMstPeriphs = 1; + ret.NumSlvPeriphs = 12; + ret.ClusterAlias = 1; + ret.ClusterAliasBase = 'h0; + ret.NumSyncStages = SyncStages; + ret.UseHci = 1; + ret.TcdmSize = 256*1024; + ret.TcdmNumBank = 16; + ret.HwpePresent = 1; + ret.HwpeCfg = '{NumHwpes: 3, + HwpeList: {pulp_cluster_package::SOFTEX, + pulp_cluster_package::NEUREKA, + pulp_cluster_package::REDMULE} + }; + ret.HwpeNumPorts = 9; + ret.HMRPresent = 1; + ret.HMRDmrEnabled = 1; + ret.HMRTmrEnabled = 1; + ret.HMRDmrFIxed = 0; + ret.HMRTmrFIxed = 0; + ret.HMRInterleaveGrps = 1; + ret.HMREnableRapidRecovery = 1; + ret.HMRSeparateDataVoters = 1; + ret.HMRSeparateAxiBus = 0; + ret.HMRNumBusVoters = 1; + ret.EnableECC = 1; + ret.ECCInterco = 1; + ret.iCacheNumBanks = 2; + ret.iCacheNumLines = 1; + ret.iCacheNumWays = 4; + ret.iCacheSharedSize = 4*1024; + ret.iCachePrivateSize = 512; + ret.iCachePrivateDataWidth = 32; + ret.EnableReducedTag = 1; + ret.L2Size = L2MemSize; + ret.DmBaseAddr = IntClusterDbgStart; + ret.BootRomBaseAddr = CarfieldIslandsCfg.l2_port0.base + 'h8080; + ret.BootAddr = CarfieldIslandsCfg.l2_port0.base + 'h8080; + ret.EnablePrivateFpu = 1; + ret.EnablePrivateFpDivSqrt = 0; + ret.NumAxiIn = 4; + ret.NumAxiOut = 3; + ret.AxiIdInWidth = cfg.AxiMstIdWidth + $clog2(AxiIn.num_in); + ret.AxiIdOutWidth = cfg.AxiMstIdWidth; + ret.AxiAddrWidth = cfg.AddrWidth; + ret.AxiDataInWidth = cfg.AxiDataWidth; + ret.AxiDataOutWidth = cfg.AxiDataWidth; + ret.AxiUserWidth = cfg.AxiUserWidth; + ret.AxiMaxInTrans = cfg.AxiMaxSlvTrans; + ret.AxiMaxOutTrans = cfg.AxiMaxSlvTrans; + ret.AxiCdcLogDepth = LogDepth; + ret.AxiCdcSyncStages = SyncStages; + ret.SyncStages = SyncStages; + ret.ClusterBaseAddr = CarfieldAxiMap.AxiStart[CarfieldAxiSlvIdx.pulp]; + ret.ClusterPeriphOffs = 'h00200000; + ret.ClusterExternalOffs = 'h00400000; + ret.EnableRemapAddress = 0; + ret.SnitchICache = 0; + // Return modified config + return ret; +endfunction +// verilog_lint: waive-stop line-length endpackage diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv index 4b185e93..01ddca33 100644 --- a/hw/cheshire_wrap.sv +++ b/hw/cheshire_wrap.sv @@ -16,7 +16,7 @@ module cheshire_wrap import cheshire_pkg::*; #( parameter cheshire_cfg_t Cfg = '0, - parameter dm::hartinfo_t [iomsb(Cfg.NumExtDbgHarts)-1:0] ExtHartinfo = '0, + parameter dm::hartinfo_t [cheshire_pkg::iomsb(Cfg.NumExtDbgHarts)-1:0] ExtHartinfo = '0, parameter int unsigned NumExtIntrs = 32, parameter type cheshire_axi_ext_llc_ar_chan_t = logic, parameter type cheshire_axi_ext_llc_aw_chan_t = logic, @@ -134,46 +134,46 @@ module cheshire_wrap output logic [ LogDepth:0] llc_mst_w_wptr_o , input logic [ LogDepth:0] llc_mst_w_rptr_i , // External AXI isolate slave Ports (except the Mailbox) - input logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolate_i, - output logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolated_o, + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolate_i, + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolated_o, // External async AXI slave Ports (except the Mailbox) - output logic [iomsb(NumSlaveCDCs):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o, - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_wptr_o, - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_rptr_i, - output logic [iomsb(NumSlaveCDCs):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o, - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_wptr_o, - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_rptr_i, - input logic [iomsb(NumSlaveCDCs):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i , - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_wptr_i , - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_rptr_o , - input logic [iomsb(NumSlaveCDCs):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i , - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_wptr_i , - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_rptr_o , - output logic [iomsb(NumSlaveCDCs):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o , - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_wptr_o , - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_rptr_i , + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o, + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_wptr_o, + input logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_rptr_i, + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o, + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_wptr_o, + input logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_rptr_i, + input logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i , + input logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_wptr_i , + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_rptr_o , + input logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i , + input logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_wptr_i , + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_rptr_o , + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o , + output logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_wptr_o , + input logic [cheshire_pkg::iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_rptr_i , // External async AXI master Ports - input logic [iomsb(Cfg.AxiExtNumMst):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, - input logic [iomsb(Cfg.AxiExtNumMst):0][ExtMstAwWidth-1:0] axi_ext_mst_aw_data_i, - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_wptr_i, - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_rptr_o, - output logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstBWidth-1:0] axi_ext_mst_b_data_o , - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_wptr_o , - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_rptr_i , - output logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstRWidth-1:0] axi_ext_mst_r_data_o , - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_wptr_o , - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_rptr_i , - input logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i , - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_wptr_i , - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_rptr_o , + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ExtMstAwWidth-1:0] axi_ext_mst_aw_data_i, + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_wptr_i, + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_rptr_o, + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ ExtMstBWidth-1:0] axi_ext_mst_b_data_o , + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_wptr_o , + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_rptr_i , + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ ExtMstRWidth-1:0] axi_ext_mst_r_data_o , + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_wptr_o , + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_rptr_i , + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i , + input logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_wptr_i , + output logic [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_rptr_o , // Mailboxes output cheshire_axi_ext_slv_req_t axi_mbox_slv_req_o, input cheshire_axi_ext_slv_rsp_t axi_mbox_slv_rsp_i, // External reg demux slaves Cheshire's clock domain (sync) - output cheshire_reg_ext_req_t [iomsb(NumSyncRegSlv):0] reg_ext_slv_req_o, - input cheshire_reg_ext_rsp_t [iomsb(NumSyncRegSlv):0] reg_ext_slv_rsp_i, + output cheshire_reg_ext_req_t [cheshire_pkg::iomsb(NumSyncRegSlv):0] reg_ext_slv_req_o, + input cheshire_reg_ext_rsp_t [cheshire_pkg::iomsb(NumSyncRegSlv):0] reg_ext_slv_rsp_i, // External reg demux slaves other clock domains (async) // Padframe and PLL output logic [NumAsyncRegSlv-1:0] ext_reg_async_slv_req_o, @@ -183,16 +183,17 @@ module cheshire_wrap output logic [NumAsyncRegSlv-1:0] ext_reg_async_slv_ack_o, input cheshire_reg_ext_rsp_t [NumAsyncRegSlv-1:0] ext_reg_async_slv_data_i, // Interrupts from external devices - input logic [iomsb(Cfg.NumExtInIntrs):0] intr_ext_i, - output logic [iomsb(Cfg.NumExtOutIntrTgts):0][iomsb(Cfg.NumExtOutIntrs):0] intr_ext_o, + input logic [cheshire_pkg::iomsb(Cfg.NumExtInIntrs):0] intr_ext_i, + output logic [cheshire_pkg::iomsb(Cfg.NumExtOutIntrTgts):0] + [cheshire_pkg::iomsb(Cfg.NumExtOutIntrs):0] intr_ext_o, // Interrupts to external harts - output logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_ext_o, - output logic [iomsb(Cfg.NumExtIrqHarts):0] mtip_ext_o, - output logic [iomsb(Cfg.NumExtIrqHarts):0] msip_ext_o, + output logic [cheshire_pkg::iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_ext_o, + output logic [cheshire_pkg::iomsb(Cfg.NumExtIrqHarts):0] mtip_ext_o, + output logic [cheshire_pkg::iomsb(Cfg.NumExtIrqHarts):0] msip_ext_o, // Debug interface to external harts output logic dbg_active_o, - output logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_req_o, - input logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_unavail_i, + output logic [cheshire_pkg::iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_req_o, + input logic [cheshire_pkg::iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_unavail_i, // JTAG interface input logic jtag_tck_i, input logic jtag_trst_ni, @@ -243,15 +244,15 @@ module cheshire_wrap ); // All AXI slave buses -cheshire_axi_ext_slv_req_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_req; -cheshire_axi_ext_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_rsp; +cheshire_axi_ext_slv_req_t [cheshire_pkg::iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_req; +cheshire_axi_ext_slv_rsp_t [cheshire_pkg::iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_rsp; -cheshire_axi_ext_slv_req_t [iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_req; -cheshire_axi_ext_slv_rsp_t [iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_rsp; +cheshire_axi_ext_slv_req_t [cheshire_pkg::iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_req; +cheshire_axi_ext_slv_rsp_t [cheshire_pkg::iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_rsp; // All AXI master buses -cheshire_axi_ext_mst_req_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_req; -cheshire_axi_ext_mst_rsp_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_rsp; +cheshire_axi_ext_mst_req_t [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_req; +cheshire_axi_ext_mst_rsp_t [cheshire_pkg::iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_rsp; // External LLC (DRAM) bus cheshire_axi_ext_llc_req_t axi_llc_mst_req, axi_llc_mst_isolated_req; @@ -261,8 +262,8 @@ cheshire_axi_ext_llc_rsp_t axi_llc_mst_rsp, axi_llc_mst_isolated_rsp; `AXI_ASSIGN_REQ_STRUCT(axi_mbox_slv_req_o, axi_ext_slv_req[MailboxSlvIdx]) `AXI_ASSIGN_RESP_STRUCT(axi_ext_slv_rsp[MailboxSlvIdx], axi_mbox_slv_rsp_i) -cheshire_reg_ext_req_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_req; -cheshire_reg_ext_rsp_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_rsp; +cheshire_reg_ext_req_t [cheshire_pkg::iomsb(Cfg.RegExtNumSlv):0] ext_reg_req; +cheshire_reg_ext_rsp_t [cheshire_pkg::iomsb(Cfg.RegExtNumSlv):0] ext_reg_rsp; // Generate synchronous external register interface from Cheshire for (genvar i = 0; i < NumSyncRegSlv; i++) begin: gen_ext_reg_sync diff --git a/hw/l2_wrap.sv b/hw/l2_wrap.sv index 85179770..1207a89d 100644 --- a/hw/l2_wrap.sv +++ b/hw/l2_wrap.sv @@ -11,7 +11,7 @@ module l2_wrap import axi_pkg::*; import dyn_mem_pkg::*; #( - parameter cheshire_pkg::cheshire_cfg_t Cfg = CarfieldCfgDefault, + parameter cheshire_pkg::cheshire_cfg_t Cfg = carfield_pkg::CheshireCfg, /// AXI Ports settings parameter int unsigned NumPort = 2, parameter int unsigned AxiAddrWidth = 48, diff --git a/sw/tests/bare-metal/pulpd/sw.mk b/sw/tests/bare-metal/pulpd/sw.mk index bfe5e53d..6adf9b18 100644 --- a/sw/tests/bare-metal/pulpd/sw.mk +++ b/sw/tests/bare-metal/pulpd/sw.mk @@ -5,14 +5,14 @@ # Alessandro Ottaviano # Yvan Tortorella -.PHONY: all clean +.PHONY: pulpd-sw-all pulpd-sw-clean # Make fragment for integer cluster bare-metal tests compiled with pulp-runtime. # List all the directories in the 'tests' folder CAR_PULPD_SW := $(CAR_SW_DIR)/tests/bare-metal/pulpd -PULPD_SW_DIR := $(PULPD_ROOT)/regression-tests/carfield -PULPD_TEST_DIRS := $(wildcard $(PULPD_ROOT)/regression-tests/carfield/*) +PULPD_SW_DIR := $(PULPD_ROOT)/regression_tests/carfield +PULPD_TEST_DIRS := $(wildcard $(PULPD_ROOT)/regression_tests/carfield/*) # We remove unneded TCDM sections directly from the binary we want to generate. This speeds up the standalone # simulation when preloading the L2 memory using JTAG and Serial Link. diff --git a/target/sim/src/carfield_fix.sv b/target/sim/src/carfield_fix.sv index 10b7f543..6ca3705b 100644 --- a/target/sim/src/carfield_fix.sv +++ b/target/sim/src/carfield_fix.sv @@ -31,13 +31,13 @@ module carfield_soc_fixture; // DUT // ///////// - localparam cheshire_cfg_t DutCfg = carfield_pkg::CarfieldCfgDefault; - `CHESHIRE_TYPEDEF_ALL(, DutCfg) + localparam cheshire_cfg_t DutCheshireCfg = carfield_pkg::CheshireCfg; + `CHESHIRE_TYPEDEF_ALL(, DutCheshireCfg) localparam time ClkPeriodSys = 10ns; localparam time ClkPeriodJtag = 40ns; localparam time ClkPeriodRtc = 1000ns; // 1MHz RTC clock. Note: needs to equal - // `DutCfg.RTCFreq` for successful autonomous boot + // `DutCheshireCfg.RTCFreq` for successful autonomous boot // (e.g., SPI) localparam int unsigned RstCycles = 5; localparam real TAppl = 0.1; @@ -130,7 +130,7 @@ module carfield_soc_fixture; wire [NumPhys-1:0][7:0] pad_hyper_dq; carfield #( - .Cfg ( DutCfg ), + .Cfg ( DutCheshireCfg ), .HypNumPhys ( NumPhys ), .HypNumChips ( NumChips ), .reg_req_t ( reg_req_t ), @@ -243,7 +243,7 @@ module carfield_soc_fixture; // Verification IPs for carfield vip_carfield_soc #( - .DutCfg ( DutCfg ), + .DutCfg ( DutCheshireCfg ), // Determine whether we preload the hyperram model or not User preload. If 0, the memory model // is not preloaded at time 0. .HypUserPreload ( `HYP_USER_PRELOAD ), @@ -292,7 +292,7 @@ module carfield_soc_fixture; // VIP vip_cheshire_soc #( - .DutCfg ( DutCfg ), + .DutCfg ( DutCheshireCfg ), .axi_ext_llc_req_t ( axi_llc_req_t ), .axi_ext_llc_rsp_t ( axi_llc_rsp_t ), .axi_ext_mst_req_t ( axi_mst_req_t ), @@ -330,8 +330,8 @@ module carfield_soc_fixture; if (CarfieldIslandsCfg.safed.enable) begin : gen_safed_vip localparam time ClkPeriodSafedJtag = 20ns; - localparam axi_in_t AxiIn = gen_axi_in(DutCfg); - localparam int unsigned AxiSlvIdWidth = DutCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); + localparam axi_in_t AxiIn = gen_axi_in(DutCheshireCfg); + localparam int unsigned AxiSlvIdWidth = DutCheshireCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); vip_safety_island_soc #( .DutCfg ( SafetyIslandCfg ), @@ -348,11 +348,11 @@ module carfield_soc_fixture; .ClkPeriodJtag ( ClkPeriodSafedJtag ), .ClkPeriodRtc ( ClkPeriodRtc ), .RstCycles ( RstCycles ), - .AxiDataWidth ( DutCfg.AxiDataWidth ), - .AxiAddrWidth ( DutCfg.AddrWidth ), + .AxiDataWidth ( DutCheshireCfg.AxiDataWidth ), + .AxiAddrWidth ( DutCheshireCfg.AddrWidth ), .AxiInputIdWidth ( AxiSlvIdWidth ), - .AxiOutputIdWidth ( DutCfg.AxiMstIdWidth ), - .AxiUserWidth ( DutCfg.AxiUserWidth ), + .AxiOutputIdWidth ( DutCheshireCfg.AxiMstIdWidth ), + .AxiUserWidth ( DutCheshireCfg.AxiUserWidth ), .AxiDebug ( 0 ), .ApplFrac ( TAppl ), .TestFrac ( TTest ) diff --git a/target/sim/src/vip_carfield_soc.sv b/target/sim/src/vip_carfield_soc.sv index 78196d88..3c6d2380 100644 --- a/target/sim/src/vip_carfield_soc.sv +++ b/target/sim/src/vip_carfield_soc.sv @@ -11,7 +11,7 @@ module vip_carfield_soc import cheshire_pkg::*; #( // DUT - parameter cheshire_cfg_t DutCfg = carfield_pkg::CarfieldCfgDefault, + parameter cheshire_cfg_t DutCfg = carfield_pkg::CheshireCfg, parameter type axi_slv_ext_req_t = logic, parameter type axi_slv_ext_rsp_t = logic, parameter int unsigned HypNumPhys = 2, diff --git a/target/synth/src/carfield_synth_wrap.sv b/target/synth/src/carfield_synth_wrap.sv index c30e1afe..a04a58d0 100644 --- a/target/synth/src/carfield_synth_wrap.sv +++ b/target/synth/src/carfield_synth_wrap.sv @@ -132,7 +132,7 @@ module carfield_synth_wrap output carfield_debug_sigs_t debug_signals_o ); - localparam cheshire_cfg_t DutCfg = carfield_pkg::CarfieldCfgDefault; + localparam cheshire_cfg_t DutCfg = carfield_pkg::CheshireCfg; `CHESHIRE_TYPEDEF_ALL(, DutCfg) carfield #( diff --git a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv index 5a679991..701ccaba 100644 --- a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv @@ -409,7 +409,7 @@ module carfield_top_xilinx // Carfield Cfg // ////////////////// - localparam cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault; + localparam cheshire_cfg_t Cfg = carfield_pkg::CheshireCfg; `CHESHIRE_TYPEDEF_ALL(carfield_, Cfg) /////////////////// @@ -561,7 +561,7 @@ end // gen_hyper_phy logic jtag_host_to_safety, jtag_safety_to_ot; carfield #( - .Cfg (carfield_pkg::CarfieldCfgDefault), + .Cfg (carfield_pkg::CheshireCfg), .reg_req_t(carfield_reg_req_t), .reg_rsp_t(carfield_reg_rsp_t), `ifdef GEN_NO_HYPERBUS diff --git a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv index f5b310cc..69134391 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv +++ b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv @@ -278,7 +278,7 @@ module carfield_xilinx // Carfield Cfg // ////////////////// - localparam cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault; + localparam cheshire_cfg_t Cfg = carfield_pkg::CheshireCfg; `CHESHIRE_TYPEDEF_ALL(carfield_, Cfg) /////////////////// @@ -691,7 +691,7 @@ module carfield_xilinx logic jtag_host_to_safety, jtag_safety_to_ot; carfield #( - .Cfg (carfield_pkg::CarfieldCfgDefault), + .Cfg (carfield_pkg::CheshireCfg), .reg_req_t(carfield_reg_req_t), .reg_rsp_t(carfield_reg_rsp_t), `ifdef GEN_NO_HYPERBUS // bender-xilinx.mk