From f9b2c40b742cb9b26875407628bbe87cf5d5afc9 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:08 +0800 Subject: [PATCH 01/37] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Add bindings doc for Bouffalolab UART Driver Signed-off-by: Jisheng Zhang --- .../bindings/serial/bouffalolab,uart.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml new file mode 100644 index 00000000000000..6cef956d33d25e --- /dev/null +++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Jisheng Zhang +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Bouffalolab UART Controller + +maintainers: + - Jisheng Zhang + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: bouffalolab,uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + aliases { + serial0 = &uart0; + }; + + uart0: serial@30002000 { + compatible = "bouffalolab,uart"; + reg = <0x30002000 0x1000>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + }; +... From 2c19a5bf97717be85036e886250502c2e35364ec Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:11 +0800 Subject: [PATCH 02/37] riscv: add the Bouffalolab SoC family Kconfig option The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 4b6deb2715f1c4..a68ab2172230e5 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config SOC_BOUFFALOLAB + bool "Bouffalolab SoCs" + select SIFIVE_PLIC + help + This enables support for Bouffalolab SoC platforms. + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" select MCHP_CLK_MPFS From 77c6c7a056e0e02ccd5b182bf263ea27a71cc959 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:12 +0800 Subject: [PATCH 03/37] riscv: dts: bouffalolab: add the bl808 SoC base device tree Add a baisc dtsi for the bouffalolab bl808 SoC. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index b0ff5fbabb0c9a..2d4376810bcc75 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += bouffalolab subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi new file mode 100644 index 00000000000000..c98ebb14ee10a6 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang + */ + +#include + +/ { + compatible = "bouffalolab,bl808"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@30002000 { + compatible = "bouffalolab,uart"; + reg = <0x30002000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "thead,c900-plic"; + reg = <0xe0000000 0x4000000>; + interrupts-extended = <&cpu0_intc 0xffffffff>, + <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <64>; + }; + }; +}; From cddacea7c8a17fdefacde5abd9974678e6f51058 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:13 +0800 Subject: [PATCH 04/37] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Sipeed manufactures a M1S system-on-module and dock board, add basic support for them. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/bouffalolab/Makefile | 2 ++ .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile new file mode 100644 index 00000000000000..42e17e1a97bd17 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts new file mode 100644 index 00000000000000..64421fb2ad67d9 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang + */ + +/dts-v1/; + +#include "bl808.dtsi" + +/ { + model = "Sipeed M1S"; + compatible = "sipeed,m1s", "bouffalolab,bl808"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:2000000n8"; + }; + + memory@50000000 { + device_type = "memory"; + reg = <0x50000000 0x04000000>; + }; +}; + +&uart0 { + status = "okay"; +}; From 69f07729f4f5bd7aa4a9095976a45e5dd8c9b335 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 20 Nov 2022 16:21:14 +0800 Subject: [PATCH 05/37] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer I want to maintain this Bouffalolab riscv SoC entry from now on. Signed-off-by: Jisheng Zhang --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 135d93368d36ed..a8ee2a529ecb54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17975,6 +17975,12 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V BOUFFALOLAB SOC SUPPORT +M: Jisheng Zhang +L: linux-riscv at lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/bouffalolab/ + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley M: Daire McNamara From 398fa5f8dd0b26e2ef59c38db908ce4bae033017 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 8 Jan 2023 01:35:45 -0800 Subject: [PATCH 06/37] riscv: bl808: Add defconfig --- arch/riscv/configs/bl808_defconfig | 143 +++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 arch/riscv/configs/bl808_defconfig diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig new file mode 100644 index 00000000000000..8a441a64be1a85 --- /dev/null +++ b/arch/riscv/configs/bl808_defconfig @@ -0,0 +1,143 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_PERF_EVENTS=y +CONFIG_SOC_BOUFFALOLAB=y +CONFIG_SOC_VIRT=y +CONFIG_ERRATA_THEAD=y +CONFIG_SMP=y +CONFIG_NR_CPUS=8 +CONFIG_RISCV_SBI_V01=y +# CONFIG_COMPAT is not set +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_PAGE_REPORTING=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_DNS_RESOLVER=y +CONFIG_NETLINK_DIAG=y +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK_RO=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_ROM=y +CONFIG_MTD_ABSENT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PHYSMAP_VERSATILE=y +CONFIG_MTD_PHYSMAP_GEMINI=y +CONFIG_MTD_PLATRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_VIRTIO_BLK=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_VIRTIO=y +CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y +# CONFIG_ETHERNET is not set +CONFIG_MDIO_DEVICE=y +# CONFIG_WLAN is not set +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=y +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_BFLB=y +CONFIG_SERIAL_BFLB_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_XILINX=y +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=y +CONFIG_I2C_DEBUG_CORE=y +CONFIG_I2C_DEBUG_ALGO=y +CONFIG_I2C_DEBUG_BUS=y +CONFIG_FB=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_VIRTIO=y +CONFIG_GENERIC_PHY=y +CONFIG_AUTOFS4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +# CONFIG_EFIVAR_FS is not set +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_KEYS=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_XZ_DEC=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_TIMEKEEPING=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y From 87c20a57492ca7eeff77278c74385a9ba6d39f2a Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 8 Jan 2023 02:25:29 -0800 Subject: [PATCH 07/37] riscv: dts: bouffalolab: add bootargs/initrd --- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 64421fb2ad67d9..84e5aac6cbf851 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -17,6 +17,9 @@ chosen { stdout-path = "serial0:2000000n8"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + linux,initrd-start = <0x0 0x52000000>; + linux,initrd-end = <0x0 0x52941784>; }; memory@50000000 { From c463c23723ed8823f03a7d0417136b800154af9b Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 8 Jan 2023 02:26:04 -0800 Subject: [PATCH 08/37] riscv: dts: bouffalolab: add xip_flash --- .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 84e5aac6cbf851..bdb502ea5a5489 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -26,6 +26,20 @@ device_type = "memory"; reg = <0x50000000 0x04000000>; }; + + xip_flash@58500000 { + compatible = "mtd-rom"; + reg = <0x58500000 0x400000>; + linux,mtd-name = "xip-flash.0"; + erase-size = <0x10000>; + bank-width = <4>; + + rootfs@0 { + label = "rootfs"; + reg = <0x00000 0x280000>; + read-only; + }; + }; }; &uart0 { From 950fd2ac1cd7529abee5852773db654e617173d1 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 18:14:53 -0800 Subject: [PATCH 09/37] WIP: add BFLB MBOX interrupt controller driver --- .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index bdb502ea5a5489..70259bad7dfd31 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -45,3 +45,7 @@ &uart0 { status = "okay"; }; + +&ipclic { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index c98ebb14ee10a6..c5cda8d74ccd9d 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { compatible = "bouffalolab,bl808"; @@ -60,6 +61,19 @@ status = "disabled"; }; + ipclic: mailbox@30005000 { + compatible = "bouffalolab,bflb-ipc"; + reg = <0x30005000 0x20>, + <0x30005020 0x20>, + <0x2000a800 0x20>, + <0x2000a820 0x20>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + status = "disabled"; + }; + plic: interrupt-controller@e0000000 { compatible = "thead,c900-plic"; reg = <0xe0000000 0x4000000>; From 661769605519fdb71bd4600663f8e0d5c810af7b Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 18:16:51 -0800 Subject: [PATCH 10/37] WIP: sdhci: add BFLB sdhci driver --- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 70259bad7dfd31..effaeda67c3fb7 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -46,6 +46,10 @@ status = "okay"; }; +&sdhci0 { + status = "okay"; +}; + &ipclic { status = "okay"; }; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index c5cda8d74ccd9d..6f859194f82c36 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -61,6 +61,17 @@ status = "disabled"; }; + sdhci0: sdhci@20060000 { + compatible = "bouffalolab,bflb-sdhci"; + reg = <0x20060000 0x100>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_SDHCI + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_SDHCI>; + clocks = <&xtal>; + status = "disabled"; + }; + ipclic: mailbox@30005000 { compatible = "bouffalolab,bflb-ipc"; reg = <0x30005000 0x20>, From 4b74d104b878abe090836f86e42475a0b80235c9 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 15:22:09 -0800 Subject: [PATCH 11/37] bl808_defconfig: enable sdhci driver --- arch/riscv/configs/bl808_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 8a441a64be1a85..049fe1c25d74ec 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -103,6 +103,10 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_BFLB=y CONFIG_RTC_CLASS=y CONFIG_SYNC_FILE=y # CONFIG_VIRTIO_MENU is not set From 69e4d28bdf14e9a6c764f14ec7466c603d976094 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 15:22:29 -0800 Subject: [PATCH 12/37] bl808_defconfig: enable mailbox irqchip driver --- arch/riscv/configs/bl808_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 049fe1c25d74ec..d2786235830294 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -111,6 +111,8 @@ CONFIG_RTC_CLASS=y CONFIG_SYNC_FILE=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set +CONFIG_MAILBOX=y +CONFIG_BFLB_IPC=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_VIRTIO=y From 3b946f78adcf9cd06ab60e444ce696aa3bab66d8 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 15:23:03 -0800 Subject: [PATCH 13/37] bl808_defconfig: enable irq debugfs --- arch/riscv/configs/bl808_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index d2786235830294..0cc8c786a522b2 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -1,5 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BPF_SYSCALL=y From e4017e32952a79b01a829092298e558bee92681e Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Wed, 11 Jan 2023 18:14:53 -0800 Subject: [PATCH 14/37] WIP: add BFLB MBOX interrupt controller driver --- include/dt-bindings/mailbox/bflb-ipc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/mailbox/bflb-ipc.h diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h new file mode 100644 index 00000000000000..1d4c4be6292e97 --- /dev/null +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Allen Martin + */ + +#ifndef __DT_BINDINGS_MAILBOX_BFLB_IPC_H +#define __DT_BINDINGS_MAILBOX_BFLB_IPC_H + +/* Source processor */ +#define BFLB_IPC_SOURCE_M0 0 +#define BFLB_IPC_SOURCE_LP 1 + +/* Peripheral device ID */ +#define BFLB_IPC_DEVICE_SDHCI 0 + +#endif From 885fc70c6a228c9285c23ec4d7f07a98964f643f Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Sat, 14 Jan 2023 00:05:40 +0000 Subject: [PATCH 15/37] UART2 working under Linux! --- arch/riscv/boot/dts/bouffalolab/Makefile | 1 + .../dts/bouffalolab/bl808-pine64-ox64.dts | 60 +++++++++++++++++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 13 +++- include/dt-bindings/mailbox/bflb-ipc.h | 1 + 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile index 42e17e1a97bd17..bc7aad3d560406 100644 --- a/arch/riscv/boot/dts/bouffalolab/Makefile +++ b/arch/riscv/boot/dts/bouffalolab/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-pine64-ox64.dtb diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts new file mode 100644 index 00000000000000..a3b1ae9f04780d --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang + */ + +/dts-v1/; + +#include "bl808.dtsi" + +/ { + model = "Pine64 Ox64"; + compatible = "sipeed,m1s", "bouffalolab,bl808"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:2000000n8"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + linux,initrd-start = <0x0 0x52000000>; + linux,initrd-end = <0x0 0x52941784>; + }; + + memory@50000000 { + device_type = "memory"; + reg = <0x50000000 0x04000000>; + }; + + xip_flash@58500000 { + compatible = "mtd-rom"; + reg = <0x58500000 0x400000>; + linux,mtd-name = "xip-flash.0"; + erase-size = <0x10000>; + bank-width = <4>; + + rootfs@0 { + label = "rootfs"; + reg = <0x00000 0x280000>; + read-only; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; +}; + +&ipclic { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 6f859194f82c36..755071f80b5904 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -60,7 +60,18 @@ clocks = <&xtal>; status = "disabled"; }; - + + uart1: serial@0x2000AA00 { + compatible = "bouffalolab,uart"; + reg = <0x2000AA00 0x0100>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_UART2 + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_UART2>; + clocks = <&xtal>; + status = "disabled"; + }; + sdhci0: sdhci@20060000 { compatible = "bouffalolab,bflb-sdhci"; reg = <0x20060000 0x100>; diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h index 1d4c4be6292e97..e96fe62cbeb9a2 100644 --- a/include/dt-bindings/mailbox/bflb-ipc.h +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -12,5 +12,6 @@ /* Peripheral device ID */ #define BFLB_IPC_DEVICE_SDHCI 0 +#define BFLB_IPC_DEVICE_UART2 1 #endif From 9a54e5b68abb12792cda5342b581a46356e57825 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sat, 14 Jan 2023 17:59:13 -0800 Subject: [PATCH 16/37] dts: bl808: add fake sdh clock at 96MHz --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 755071f80b5904..ecb285cd7763ed 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -45,6 +45,13 @@ #clock-cells = <0>; }; + sdh: sdh-clk { + compatible = "fixed-clock"; + clock-frequency = <96000000>; + clock-output-names = "sdh"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges; @@ -79,7 +86,7 @@ BFLB_IPC_DEVICE_SDHCI IRQ_TYPE_EDGE_RISING>; mboxes = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_SDHCI>; - clocks = <&xtal>; + clocks = <&sdh>; status = "disabled"; }; From ad398a49333c425e52f8f46840d4276bdcbdc457 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Sun, 15 Jan 2023 13:38:26 +0000 Subject: [PATCH 17/37] Disable flash rootfs for now, edit bootargs to use SDHCI ext4 partition 1 rootfs --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index a3b1ae9f04780d..d3d228c3d8c0ea 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -18,7 +18,7 @@ chosen { stdout-path = "serial0:2000000n8"; - bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p1 rootwait rootfstype=ext4"; linux,initrd-start = <0x0 0x52000000>; linux,initrd-end = <0x0 0x52941784>; }; @@ -35,11 +35,11 @@ erase-size = <0x10000>; bank-width = <4>; - rootfs@0 { + /*rootfs@0 { label = "rootfs"; - reg = <0x00000 0x280000>; + reg = <0x00000 0x400000>; read-only; - }; + };*/ }; }; From b2fe2832f829538921d9c8ac3bbcbd053b776c6b Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Sun, 15 Jan 2023 14:24:55 +0000 Subject: [PATCH 18/37] Update defconfig with EXT4 support for SD rootfs --- arch/riscv/configs/bl808_defconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 0cc8c786a522b2..2acab58e801b67 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -118,6 +118,7 @@ CONFIG_BFLB_IPC=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_VIRTIO=y CONFIG_GENERIC_PHY=y +CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -133,11 +134,8 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y CONFIG_KEYS=y CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" -CONFIG_CRYPTO=y -CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_DEV_VIRTIO=y -CONFIG_CRC16=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_XZ_DEC=y From 4c45c424d0d3e02b1d47b275d37d477f944d6914 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 13 Jan 2023 02:38:06 -0800 Subject: [PATCH 19/37] usb: add bflb ehci controller --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 10 ++++++++++ include/dt-bindings/mailbox/bflb-ipc.h | 1 + 4 files changed, 19 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index d3d228c3d8c0ea..66a892f880c71a 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -58,3 +58,7 @@ &ipclic { status = "okay"; }; + +&ehci0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index effaeda67c3fb7..19155bcc269373 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -53,3 +53,7 @@ &ipclic { status = "okay"; }; + +&ehci0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index ecb285cd7763ed..f3e4f17e69c033 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -90,6 +90,16 @@ status = "disabled"; }; + ehci0: usb@20072000 { + compatible = "generic-ehci"; + reg = <0x20072010 0x1000>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_USB + IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + ipclic: mailbox@30005000 { compatible = "bouffalolab,bflb-ipc"; reg = <0x30005000 0x20>, diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h index e96fe62cbeb9a2..327e150384b95f 100644 --- a/include/dt-bindings/mailbox/bflb-ipc.h +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -13,5 +13,6 @@ /* Peripheral device ID */ #define BFLB_IPC_DEVICE_SDHCI 0 #define BFLB_IPC_DEVICE_UART2 1 +#define BFLB_IPC_DEVICE_USB 2 #endif From 0a7184765d42e951d892e1c7b70c6eb08eb67ec9 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 13 Jan 2023 02:38:58 -0800 Subject: [PATCH 20/37] bl808_defconfig: enable USB and EHCI --- arch/riscv/configs/bl808_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 2acab58e801b67..c43e21711750c7 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -103,7 +103,9 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_HID_REDRAGON is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y From aa9ca42882bd51620df7d5b591bb0c368ea830e4 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 15 Jan 2023 21:06:40 -0800 Subject: [PATCH 21/37] dts: bl808: fix offset of ehci controller ehci controller registers are at address 0x20072000 not 0x20072010 --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index f3e4f17e69c033..5e90f3ee04d716 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -92,7 +92,7 @@ ehci0: usb@20072000 { compatible = "generic-ehci"; - reg = <0x20072010 0x1000>; + reg = <0x20072000 0x1000>; interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_USB IRQ_TYPE_EDGE_RISING>; From 3258905a37d4e65b045453a0955a87a03469a6d2 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 15 Jan 2023 21:11:40 -0800 Subject: [PATCH 22/37] bl808_defconfig: enable USB serial and network devices --- arch/riscv/configs/bl808_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index c43e21711750c7..39ad1cb2b4bc55 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -106,6 +106,8 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y From dcecd699e76f054916fde5f661fecc410938c5f9 Mon Sep 17 00:00:00 2001 From: Justin Hammond Date: Fri, 20 Jan 2023 13:45:52 +0800 Subject: [PATCH 23/37] Rename DTS Files --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 8 +------- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 2 +- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 10 +++++----- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 66a892f880c71a..eede26e4f043c0 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -9,7 +9,7 @@ / { model = "Pine64 Ox64"; - compatible = "sipeed,m1s", "bouffalolab,bl808"; + compatible = "sipeed,m1s", "bflb,bl808"; aliases { serial0 = &uart0; @@ -34,12 +34,6 @@ linux,mtd-name = "xip-flash.0"; erase-size = <0x10000>; bank-width = <4>; - - /*rootfs@0 { - label = "rootfs"; - reg = <0x00000 0x400000>; - read-only; - };*/ }; }; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 19155bcc269373..ed2d18482920c6 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -9,7 +9,7 @@ / { model = "Sipeed M1S"; - compatible = "sipeed,m1s", "bouffalolab,bl808"; + compatible = "sipeed,m1s", "bflb,bl808"; aliases { serial0 = &uart0; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 5e90f3ee04d716..bdfed1bde043ff 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -7,7 +7,7 @@ #include / { - compatible = "bouffalolab,bl808"; + compatible = "bflb,bl808"; #address-cells = <1>; #size-cells = <1>; @@ -61,7 +61,7 @@ #size-cells = <1>; uart0: serial@30002000 { - compatible = "bouffalolab,uart"; + compatible = "bflb,bl808-uart"; reg = <0x30002000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&xtal>; @@ -69,7 +69,7 @@ }; uart1: serial@0x2000AA00 { - compatible = "bouffalolab,uart"; + compatible = "bflb,bl808-uart"; reg = <0x2000AA00 0x0100>; interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_UART2 @@ -80,7 +80,7 @@ }; sdhci0: sdhci@20060000 { - compatible = "bouffalolab,bflb-sdhci"; + compatible = "bflb,bl808-sdhci"; reg = <0x20060000 0x100>; interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 BFLB_IPC_DEVICE_SDHCI @@ -101,7 +101,7 @@ }; ipclic: mailbox@30005000 { - compatible = "bouffalolab,bflb-ipc"; + compatible = "bflb,bl808-ipc"; reg = <0x30005000 0x20>, <0x30005020 0x20>, <0x2000a800 0x20>, From 5de10314906445dd50565284c6fb822e86e3490c Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 20 Jan 2023 19:01:49 -0800 Subject: [PATCH 24/37] dts: bl808-pine64-ox64: change rootfs to /dev/mmcblk0p2 --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index eede26e4f043c0..4e183098f171ec 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -18,7 +18,7 @@ chosen { stdout-path = "serial0:2000000n8"; - bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p1 rootwait rootfstype=ext4"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p2 rootwait rootfstype=ext4"; linux,initrd-start = <0x0 0x52000000>; linux,initrd-end = <0x0 0x52941784>; }; From 37884166bce69b4289af44e9e1422b7b1078c463 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:00:32 -0800 Subject: [PATCH 25/37] dts: bl808-pine64-ox64: disable secondary UART Pinmux for this device conflicts with EMAC, so disable it until pinmux is changed to some other pins. --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 4e183098f171ec..96cc039133cc04 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -41,10 +41,6 @@ status = "okay"; }; -&uart1 { - status = "okay"; -}; - &sdhci0 { status = "okay"; }; From 92d66e03a0a0f921142c67472eec01cbbfde13b9 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:02:40 -0800 Subject: [PATCH 26/37] dts: bl808: add entry for EMAC device Add device-tree node for EMAC ethernet device and fake clock node to represent 50MHz clock to the device. Add a virtualized interrupt bit for forwareded EMAC interrupts. --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 17 +++++++++++++++++ include/dt-bindings/mailbox/bflb-ipc.h | 1 + 2 files changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index bdfed1bde043ff..dd795667dea68f 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -52,6 +52,13 @@ #clock-cells = <0>; }; + enet: enet-clk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "enet"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges; @@ -100,6 +107,16 @@ status = "disabled"; }; + enet0: emac@20070000 { + compatible = "opencores,ethoc"; + reg = <0x20070000 0x1000>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_EMAC + IRQ_TYPE_EDGE_RISING>; + clocks = <&enet>; + status = "disabled"; + }; + ipclic: mailbox@30005000 { compatible = "bflb,bl808-ipc"; reg = <0x30005000 0x20>, diff --git a/include/dt-bindings/mailbox/bflb-ipc.h b/include/dt-bindings/mailbox/bflb-ipc.h index 327e150384b95f..0a3c6745a673c1 100644 --- a/include/dt-bindings/mailbox/bflb-ipc.h +++ b/include/dt-bindings/mailbox/bflb-ipc.h @@ -14,5 +14,6 @@ #define BFLB_IPC_DEVICE_SDHCI 0 #define BFLB_IPC_DEVICE_UART2 1 #define BFLB_IPC_DEVICE_USB 2 +#define BFLB_IPC_DEVICE_EMAC 3 #endif From 2ad217b4095e489b76e3d8f1d9c42a668c5e013b Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:13:31 -0800 Subject: [PATCH 27/37] riscv: bl808_defconfig: enable ETHOC driver --- arch/riscv/configs/bl808_defconfig | 45 ++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index 39ad1cb2b4bc55..d51f2d78c139d6 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -63,8 +63,48 @@ CONFIG_BLK_DEV_SD=y CONFIG_SCSI_VIRTIO=y CONFIG_NETDEVICES=y CONFIG_VIRTIO_NET=y -# CONFIG_ETHERNET is not set -CONFIG_MDIO_DEVICE=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set +# CONFIG_NET_VENDOR_LITEX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +CONFIG_ETHOC=y +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set # CONFIG_WLAN is not set CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_EVDEV=y @@ -88,6 +128,7 @@ CONFIG_I2C_SLAVE_EEPROM=y CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y +# CONFIG_PTP_1588_CLOCK is not set CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set From a7bbe72dd574b66708c0cc060898551f3917b74a Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Tue, 24 Jan 2023 17:14:05 -0800 Subject: [PATCH 28/37] dts: bl808: enable enet nodes --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 4 ++++ arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 96cc039133cc04..f9ed636291f614 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -52,3 +52,7 @@ &ehci0 { status = "okay"; }; + +&enet0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index ed2d18482920c6..031c824f2061ae 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -57,3 +57,7 @@ &ehci0 { status = "okay"; }; + +&enet0 { + status = "okay"; +}; From ee0931def8e7ff676e11ebe147c1128862e2c8f6 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 5 Feb 2023 16:13:42 -0600 Subject: [PATCH 29/37] riscv: dts: bflb: m1s: Fix address/size-cells The number of address cells needed here (one) does not match the implicitly-defined default number of cells. Signed-off-by: Samuel Holland --- arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 031c824f2061ae..5307508e7a9462 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -33,6 +33,8 @@ linux,mtd-name = "xip-flash.0"; erase-size = <0x10000>; bank-width = <4>; + #address-cells = <1>; + #size-cells = <1>; rootfs@0 { label = "rootfs"; From be296b48621098e41309ac433fc3ebdd3d64c4bd Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Sun, 5 Feb 2023 20:18:50 -0800 Subject: [PATCH 30/37] riscv: dts: bflb: ox64: Fix address/size-cells The number of address cells needed here (one) does not match the implicitly-defined default number of cells. Signed-off-by: Allen Martin --- arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index f9ed636291f614..f1db126d88e76f 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -34,6 +34,8 @@ linux,mtd-name = "xip-flash.0"; erase-size = <0x10000>; bank-width = <4>; + #address-cells = <1>; + #size-cells = <1>; }; }; From d48d4b1210f8a99578a429fecc282e83d7f8bc92 Mon Sep 17 00:00:00 2001 From: Justin Hammond Date: Mon, 6 Feb 2023 13:38:55 +0800 Subject: [PATCH 31/37] Add timer node for OpenSBI 1.2 compatibility --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index dd795667dea68f..34652e17aece8f 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -140,5 +140,12 @@ #interrupt-cells = <2>; riscv,ndev = <64>; }; + + clint: timer@e4000000 { + compatible = "thead,c900-clint"; + reg = <0xe4000000 0xc000>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu0_intc 7>; + }; }; }; From b79eef5b82707b2fe5823dc6e5e30f3fd94561ff Mon Sep 17 00:00:00 2001 From: Justin Hammond Date: Mon, 6 Feb 2023 13:41:53 +0800 Subject: [PATCH 32/37] Tabstops are 8 chars, not 4 --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 34652e17aece8f..7cd033b6a1cf36 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -145,7 +145,7 @@ compatible = "thead,c900-clint"; reg = <0xe4000000 0xc000>; interrupts-extended = <&cpu0_intc 3>, - <&cpu0_intc 7>; + <&cpu0_intc 7>; }; }; }; From 4fb02196485265eeb2c13868932219d3de09a809 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Thu, 16 Feb 2023 19:42:01 +0000 Subject: [PATCH 33/37] Update device trees for new GPIO and HWRNG drivers --- .../dts/bouffalolab/bl808-pine64-ox64.dts | 8 +++++ arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 30 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index f1db126d88e76f..5050c80b6f1150 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -39,6 +39,14 @@ }; }; +&pinctrl { + status = "okay"; +}; + +&seceng { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi index 7cd033b6a1cf36..73a4e055c7a9e6 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -67,6 +67,36 @@ #address-cells = <1>; #size-cells = <1>; + pinctrl: pinctrl@0x200008C4 { + compatible = "bflb,pinctrl"; + //Last register is for gpio_cfg141 at 0x20000af8 + reg = <0x200008C4 0x1000>; + //clocks = <&gpio_clk>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 46>; + bflb,npins = <46>; + + status = "disabled"; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&ipclic BFLB_IPC_SOURCE_M0 + BFLB_IPC_DEVICE_GPIO IRQ_TYPE_EDGE_RISING>; + + sdh_pins: sdh-pins { + pins = "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5"; + function = "sdh"; + }; + }; + + seceng: seceng@0x20004000 { + compatible = "bflb,seceng"; + reg = <0x20004000 0x1000>; + status = "disabled"; + }; + uart0: serial@30002000 { compatible = "bflb,bl808-uart"; reg = <0x30002000 0x1000>; From 56820fe33133f4d37dc277a344c5a54bfeb502c3 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Tue, 14 Feb 2023 23:12:03 +0000 Subject: [PATCH 34/37] Update bl808_defconfig for new drivers --- arch/riscv/configs/bl808_defconfig | 40 ++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/riscv/configs/bl808_defconfig b/arch/riscv/configs/bl808_defconfig index d51f2d78c139d6..9e234dcb5ec0d7 100644 --- a/arch/riscv/configs/bl808_defconfig +++ b/arch/riscv/configs/bl808_defconfig @@ -11,8 +11,10 @@ CONFIG_CGROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y +CONFIG_EXPERT=y CONFIG_PERF_EVENTS=y CONFIG_SOC_BOUFFALOLAB=y CONFIG_SOC_VIRT=y @@ -129,21 +131,15 @@ CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y # CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_BFLB_GPIO=y +CONFIG_GPIO_SYSFS=y CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_REDRAGON is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set +CONFIG_HID_CHICONY=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y @@ -153,6 +149,27 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_BFLB=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_USER=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=y +CONFIG_LEDS_TRIGGER_PATTERN=y +CONFIG_LEDS_TRIGGER_AUDIO=y +CONFIG_LEDS_TRIGGER_TTY=y CONFIG_RTC_CLASS=y CONFIG_SYNC_FILE=y # CONFIG_VIRTIO_MENU is not set @@ -180,6 +197,7 @@ CONFIG_NLS_UTF8=y CONFIG_KEYS=y CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_DEV_BFLB_SECENG=y CONFIG_CRYPTO_DEV_VIRTIO=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y @@ -187,7 +205,9 @@ CONFIG_XZ_DEC=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_MEMORY_INIT=y CONFIG_DEBUG_TIMEKEEPING=y +# CONFIG_FTRACE is not set CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y From 5bc30359db03519fe18fafbbf0b1f4c38dbebdf7 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Thu, 16 Feb 2023 19:43:15 +0000 Subject: [PATCH 35/37] Bring M1s device tree up to date with Ox64's changes, fix compatible string on the Ox64 device tree --- .../dts/bouffalolab/bl808-pine64-ox64.dts | 2 +- .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 31 ++++++++++++++----- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts index 5050c80b6f1150..c5b1e86310d983 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-pine64-ox64.dts @@ -9,7 +9,7 @@ / { model = "Pine64 Ox64"; - compatible = "sipeed,m1s", "bflb,bl808"; + compatible = "pine64,ox64", "bflb,bl808"; aliases { serial0 = &uart0; diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts index 5307508e7a9462..ecdce792132336 100644 --- a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -6,9 +6,11 @@ /dts-v1/; #include "bl808.dtsi" +#include +#include / { - model = "Sipeed M1S"; + model = "Sipeed M1s"; compatible = "sipeed,m1s", "bflb,bl808"; aliases { @@ -17,7 +19,7 @@ chosen { stdout-path = "serial0:2000000n8"; - bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mtdblock0 ro rootfstype=squashfs"; + bootargs = "console=ttyS0,2000000 loglevel=8 earlycon=sbi root=/dev/mmcblk0p2 rootwait rootfstype=ext4"; linux,initrd-start = <0x0 0x52000000>; linux,initrd-end = <0x0 0x52941784>; }; @@ -35,15 +37,30 @@ bank-width = <4>; #address-cells = <1>; #size-cells = <1>; + }; + + leds { + compatible = "gpio-leds"; + + led { + gpios = <&pinctrl 8 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + status = "okay"; - rootfs@0 { - label = "rootfs"; - reg = <0x00000 0x280000>; - read-only; - }; + led { + pins = "GPIO8"; + function = "gpio"; }; }; +&seceng { + status = "okay"; +}; + &uart0 { status = "okay"; }; From ab66f49c1c7b0f4e86abb94a855717a800c947d8 Mon Sep 17 00:00:00 2001 From: Alexander Horner <33007665+alexhorner@users.noreply.github.com> Date: Tue, 14 Feb 2023 22:44:18 +0000 Subject: [PATCH 36/37] Add GPIO/PINCTRL and HWRNG/Crypto drivers --- drivers/crypto/Kconfig | 11 + drivers/crypto/Makefile | 1 + drivers/crypto/bflb-seceng.c | 670 ++++++++++++++++++++++++++++++ drivers/pinctrl/Kconfig | 16 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-bflb.c | 719 +++++++++++++++++++++++++++++++++ 6 files changed, 1418 insertions(+) create mode 100644 drivers/crypto/bflb-seceng.c create mode 100644 drivers/pinctrl/pinctrl-bflb.c diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index dfb103f81a64b3..e8de3d60ffd863 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -13,6 +13,17 @@ if CRYPTO_HW source "drivers/crypto/allwinner/Kconfig" +config CRYPTO_DEV_BFLB_SECENG + tristate "Bouffalo Lab Secure Engine Driver" + depends on SOC_BOUFFALOLAB + select CRYPTO_RNG + help + This driver provides support for the Random Number + Generator hardware found on Bouffalo Lab BL808 SoCs. + + To compile this driver as a module, choose M here. The + module will be called bflb-seceng. If unsure, say N. + config CRYPTO_DEV_PADLOCK tristate "Support for VIA PadLock ACE" depends on X86 && !UML diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index fa8bf1be1a8cde..1b5c60587c436f 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o obj-$(CONFIG_CRYPTO_DEV_ATMEL_I2C) += atmel-i2c.o obj-$(CONFIG_CRYPTO_DEV_ATMEL_ECC) += atmel-ecc.o obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA204A) += atmel-sha204a.o +obj-$(CONFIG_CRYPTO_DEV_BFLB_SECENG) += bflb-seceng.o obj-$(CONFIG_CRYPTO_DEV_CAVIUM_ZIP) += cavium/ obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/ obj-$(CONFIG_CRYPTO_DEV_CCREE) += ccree/ diff --git a/drivers/crypto/bflb-seceng.c b/drivers/crypto/bflb-seceng.c new file mode 100644 index 00000000000000..3e450f06ddeaea --- /dev/null +++ b/drivers/crypto/bflb-seceng.c @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Bouffalo Lab SoC Secure Engine driver +// +// Based on qcom-rng.c +// Copyright (c) 2017-18 Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//Register map +//se_sha_0_ctrl +#define REG_SECENG_SHA_0_CTRL 0 //Offset from base address +#define REG_SECENG_SHA_0_CTRL_MSG_LEN GENMASK(31, 16) +#define REG_SECENG_SHA_0_CTRL_LINK_MODE BIT(15) +#define REG_SECENG_SHA_0_CTRL_MODE_EXT GENMASK(13, 12) +#define REG_SECENG_SHA_0_CTRL_INT_MASK BIT(11) +#define REG_SECENG_SHA_0_CTRL_INT_SET_1T BIT(10) +#define REG_SECENG_SHA_0_CTRL_INT_CLR_1T BIT(9) +#define REG_SECENG_SHA_0_CTRL_INT BIT(8) +#define REG_SECENG_SHA_0_CTRL_HASH_SEL BIT(6) +#define REG_SECENG_SHA_0_CTRL_EN BIT(5) +#define REG_SECENG_SHA_0_CTRL_MODE GENMASK(4, 2) +#define REG_SECENG_SHA_0_CTRL_INT_TRIG_1T BIT(1) +#define REG_SECENG_SHA_0_CTRL_BUSY BIT(0) + +//se_sha_0_msa +#define REG_SECENG_SHA_0_MSA 4 + +//se_sha_0_status +#define REG_SECENG_SHA_0_STATUS 8 + +//se_sha_0_endian +#define REG_SECENG_SHA_0_ENDIAN 12 +#define REG_SECENG_SHA_0_ENDIAN_VAL BIT(0) + +//se_sha_0_hash_l_0 +#define REG_SECENG_SHA_0_HASH_L_0 16 + +//se_sha_0_hash_l_1 +#define REG_SECENG_SHA_0_HASH_L_1 20 + +//se_sha_0_hash_l_2 +#define REG_SECENG_SHA_0_HASH_L_2 24 + +//se_sha_0_hash_l_3 +#define REG_SECENG_SHA_0_HASH_L_3 28 + +//se_sha_0_hash_l_4 +#define REG_SECENG_SHA_0_HASH_L_4 32 + +//se_sha_0_hash_l_5 +#define REG_SECENG_SHA_0_HASH_L_5 36 + +//se_sha_0_hash_l_6 +#define REG_SECENG_SHA_0_HASH_L_6 40 + +//se_sha_0_hash_l_7 +#define REG_SECENG_SHA_0_HASH_L_7 44 + +//se_sha_0_hash_h_0 +#define REG_SECENG_SHA_0_HASH_H_0 48 + +//se_sha_0_hash_h_1 +#define REG_SECENG_SHA_0_HASH_H_1 52 + +//se_sha_0_hash_h_2 +#define REG_SECENG_SHA_0_HASH_H_2 56 + +//se_sha_0_hash_h_3 +#define REG_SECENG_SHA_0_HASH_H_3 60 + +//se_sha_0_hash_h_4 +#define REG_SECENG_SHA_0_HASH_H_4 64 + +//se_sha_0_hash_h_5 +#define REG_SECENG_SHA_0_HASH_H_5 68 + +//se_sha_0_hash_h_6 +#define REG_SECENG_SHA_0_HASH_H_6 72 + +//se_sha_0_hash_h_7 +#define REG_SECENG_SHA_0_HASH_H_7 76 + +//se_sha_0_link +#define REG_SECENG_SHA_0_LINK 80 + +//se_sha_0_ctrl_prot +#define REG_SECENG_SHA_0_CTRL_PROT 252 +#define REG_SECENG_SHA_0_CTRL_PROT_ID1_EN BIT(2) +#define REG_SECENG_SHA_0_CTRL_PROT_ID0_EN BIT(1) + +//se_aes_0_ctrl +#define REG_SECENG_AES_0_CTRL 256 +#define REG_SECENG_AES_0_CTRL_MSG_LEN GENMASK(31, 16) +#define REG_SECENG_AES_0_CTRL_LINK_MODE BIT(15) +#define REG_SECENG_AES_0_CTRL_IV_SEL BIT(14) +#define REG_SECENG_AES_0_CTRL_BLOCK_MODE GENMASK(13, 12) +#define REG_SECENG_AES_0_CTRL_INT_MASK BIT(11) +#define REG_SECENG_AES_0_CTRL_INT_SET_1T BIT(10) +#define REG_SECENG_AES_0_CTRL_INT_CLR_1T BIT(9) +#define REG_SECENG_AES_0_CTRL_INT BIT(8) +#define REG_SECENG_AES_0_CTRL_HW_KEY_EN BIT(7) +#define REG_SECENG_AES_0_CTRL_DEC_KEY_SEL BIT(6) +#define REG_SECENG_AES_0_CTRL_DEC_EN BIT(5) +#define REG_SECENG_AES_0_CTRL_MODE GENMASK(4, 3) +#define REG_SECENG_AES_0_CTRL_EN BIT(2) +#define REG_SECENG_AES_0_CTRL_TRIG_1T BIT(1) +#define REG_SECENG_AES_0_CTRL_BUSY BIT(0) + +//se_aes_0_msa +#define REG_SECENG_AES_0_MSA 260 + +//se_aes_0_mda +#define REG_SECENG_AES_0_MDA 264 + +//se_aes_0_status +#define REG_SECENG_AES_0_STATUS 268 + +//se_aes_0_iv_0 +#define REG_SECENG_AES_0_IV_0 272 + +//se_aes_0_iv_1 +#define REG_SECENG_AES_0_IV_1 276 + +//se_aes_0_iv_2 +#define REG_SECENG_AES_0_IV_2 280 + +//se_aes_0_iv_3 +#define REG_SECENG_AES_0_IV_3 284 + +//se_aes_0_key_0 +#define REG_SECENG_AES_0_KEY_0 288 + +//se_aes_0_key_1 +#define REG_SECENG_AES_0_KEY_1 292 + +//se_aes_0_key_2 +#define REG_SECENG_AES_0_KEY_2 296 + +//se_aes_0_key_3 +#define REG_SECENG_AES_0_KEY_3 300 + +//se_aes_0_key_4 +#define REG_SECENG_AES_0_KEY_4 304 + +//se_aes_0_key_5 +#define REG_SECENG_AES_0_KEY_5 308 + +//se_aes_0_key_6 +#define REG_SECENG_AES_0_KEY_6 312 + +//se_aes_0_key_7 +#define REG_SECENG_AES_0_KEY_7 316 + +//se_aes_0_key_sel +#define REG_SECENG_AES_0_KEY_SEL 320 +#define REG_SECENG_AES_0_KEY_SEL_VAL GENMASK(1, 0) + +//se_aes_1_key_sel +#define REG_SECENG_AES_1_KEY_SEL 324 +#define REG_SECENG_AES_01KEY_SEL_VAL GENMASK(1, 0) + +//se_aes_0_endian +#define REG_SECENG_AES_0_ENDIAN 328 +#define REG_SECENG_AES_0_ENDIAN_CTR_LEN GENMASK(31, 30) +#define REG_SECENG_AES_0_ENDIAN_TWK BIT(4) +#define REG_SECENG_AES_0_ENDIAN_IV BIT(3) +#define REG_SECENG_AES_0_ENDIAN_KEY BIT(2) +#define REG_SECENG_AES_0_ENDIAN_DIN BIT(1) +#define REG_SECENG_AES_0_ENDIAN_DOUT BIT(0) + +//se_aes_sboot +#define REG_SECENG_AES_SBOOT 332 +#define REG_SECENG_AES_SBOOT_UNI_LEN GENMASK(31, 16) +#define REG_SECENG_AES_SBOOT_XTS_MODE BIT(15) +#define REG_SECENG_AES_SBOOT_KEY_SEL BIT(0) + +//se_aes_0_link +#define REG_SECENG_AES_0_LINK 336 + +//se_aes_0_ctrl_prot +#define REG_SECENG_AES_0_CTRL_PROT 508 +#define REG_SECENG_AES_0_CTRL_PROT_ID1_EN BIT(2) +#define REG_SECENG_AES_0_CTRL_PROT_ID0_EN BIT(1) + +//se_trng_0_ctrl_0 +#define REG_SECENG_TRNG_0_CTRL_0 512 +#define REG_SECENG_TRNG_0_CTRL_0_MANUAL_EN BIT(15) +#define REG_SECENG_TRNG_0_CTRL_0_MANUAL_RESEED BIT(14) +#define REG_SECENG_TRNG_0_CTRL_0_MANUAL_FUN_SEL BIT(13) +#define REG_SECENG_TRNG_0_CTRL_0_INT_MASK BIT(11) +#define REG_SECENG_TRNG_0_CTRL_0_INT_SET_1T BIT(10) +#define REG_SECENG_TRNG_0_CTRL_0_INT_CLR_1T BIT(9) +#define REG_SECENG_TRNG_0_CTRL_0_INT BIT(8) +#define REG_SECENG_TRNG_0_CTRL_0_HT_ERROR BIT(4) +#define REG_SECENG_TRNG_0_CTRL_0_DOUT_CLR_1T BIT(3) +#define REG_SECENG_TRNG_0_CTRL_0_EN BIT(2) +#define REG_SECENG_TRNG_0_CTRL_0_TRIG_1T BIT(1) +#define REG_SECENG_TRNG_0_CTRL_0_BUSY BIT(0) + +//se_trng_0_status +#define REG_SECENG_TRNG_0_STATUS 516 + +//se_trng_0_dout_0 +#define REG_SECENG_TRNG_0_DOUT_0 520 + +//se_trng_0_dout_1 +#define REG_SECENG_TRNG_0_DOUT_1 524 + +//se_trng_0_dout_2 +#define REG_SECENG_TRNG_0_DOUT_2 528 + +//se_trng_0_dout_3 +#define REG_SECENG_TRNG_0_DOUT_3 532 + +//se_trng_0_dout_4 +#define REG_SECENG_TRNG_0_DOUT_4 536 + +//se_trng_0_dout_5 +#define REG_SECENG_TRNG_0_DOUT_5 540 + +//se_trng_0_dout_6 +#define REG_SECENG_TRNG_0_DOUT_6 544 + +//se_trng_0_dout_7 +#define REG_SECENG_TRNG_0_DOUT_7 548 + +//se_trng_0_test +#define REG_SECENG_TRNG_0_TEST 552 +#define REG_SECENG_TRNG_0_TEST_HT_ALARM_N GENMASK(11, 4) +#define REG_SECENG_TRNG_0_TEST_HT_DIS BIT(3) +#define REG_SECENG_TRNG_0_TEST_CP_BYPASS BIT(2) +#define REG_SECENG_TRNG_0_TEST_CP_TEST_EN BIT(1) +#define REG_SECENG_TRNG_0_TEST_TEST_EN BIT(0) + +//se_trng_0_ctrl_1 +#define REG_SECENG_TRNG_0_CTRL_1_RESEED_N_LSB 556 + +//se_trng_0_ctrl_2 +#define REG_SECENG_TRNG_0_CTRL_2_RESEED_N_MSB 560 +#define REG_SECENG_TRNG_0_CTRL_1_RESEED_N_MSB_VALUE GENMASK(15, 0) + +//se_trng_0_ctrl_3 +#define REG_SECENG_TRNG_0_CTRL_3 564 +#define REG_SECENG_TRNG_0_CTRL_3_ROSC_EN BIT(31) +#define REG_SECENG_TRNG_0_CTRL_3_HT_OD_EN BIT(26) +#define REG_SECENG_TRNG_0_CTRL_3_HT_APT_C GENMASK(25, 16) +#define REG_SECENG_TRNG_0_CTRL_3_HT_RCT_C GENMASK(15, 8) +#define REG_SECENG_TRNG_0_CTRL_3_CP_RATIO GENMASK(7, 0) + +//se_trng_0_test_out_0 +#define REG_SECENG_TRNG_0_TEST_OUT_0 576 + +//se_trng_0_test_out_1 +#define REG_SECENG_TRNG_0_TEST_OUT_1 580 + +//se_trng_0_test_out_2 +#define REG_SECENG_TRNG_0_TEST_OUT_2 584 + +//se_trng_0_test_out_3 +#define REG_SECENG_TRNG_0_TEST_OUT_3 588 + +//se_trng_0_ctrl_prot +#define REG_SECENG_TRNG_0_CTRL_PROT 764 +#define REG_SECENG_TRNG_0_CTRL_PROT_ID1_EN BIT(2) +#define REG_SECENG_TRNG_0_CTRL_PROT_ID0_EN BIT(1) + +//se_pka_0_ctrl_0 +#define REG_SECENG_PKA_0_CTRL_0 768 +#define REG_SECENG_PKA_0_CTRL_0_STATUS GENMASK(31, 16) +#define REG_SECENG_PKA_0_CTRL_0_STATUS_CLR_1T BIT(15) +#define REG_SECENG_PKA_0_CTRL_0_RAM_CLR_MD BIT(13) +#define REG_SECENG_PKA_0_CTRL_0_ENDIAN BIT(12) +#define REG_SECENG_PKA_0_CTRL_0_INT_MASK BIT(11) +#define REG_SECENG_PKA_0_CTRL_0_INT_SET BIT(10) +#define REG_SECENG_PKA_0_CTRL_0_INT_CLR_1T BIT(9) +#define REG_SECENG_PKA_0_CTRL_0_INT BIT(8) +#define REG_SECENG_PKA_0_CTRL_0_PROT_MD GENMASK(7, 4) +#define REG_SECENG_PKA_0_CTRL_0_EN BIT(3) +#define REG_SECENG_PKA_0_CTRL_0_BUSY BIT(2) +#define REG_SECENG_PKA_0_CTRL_0_DONE_CLR_1T BIT(1) +#define REG_SECENG_PKA_0_CTRL_0_DONE BIT(0) + +//se_pka_0_seed +#define REG_SECENG_PKA_0_SEED 780 + +//se_pka_0_ctrl_1 +#define REG_SECENG_PKA_0_CTRL_1 784 +#define REG_SECENG_PKA_0_CTRL_1_HBYPASS BIT(3) +#define REG_SECENG_PKA_0_CTRL_1_HBURST GENMASK(2, 0) + +//se_pka_0_rw +#define REG_SECENG_PKA_0_RW 832 +//This is a confusing register which I have not mapped because +//"BL808 Reference Manual 1.2 EN" seems wrong + +//se_pka_0_rw_burst +#define REG_SECENG_PKA_0_RW_BURST 864 +//This is a confusing register which I have not mapped because +//"BL808 Reference Manual 1.2 EN" seems wrong + +//se_pka_0_ctrl_prot +#define REG_SECENG_PKA_0_CTRL_PROT 1020 +#define REG_SECENG_PKA_0_CTRL_PROT_ID1_EN BIT(2) +#define REG_SECENG_PKA_0_CTRL_PROT_ID0_EN BIT(1) + +//se_cdet_0_ctrl_0 +#define REG_SECENG_CDET_0_CTRL_0 1024 +#define REG_SECENG_CDET_0_CTRL_0_G_LOOP_MIN GENMASK(31, 24) +#define REG_SECENG_CDET_0_CTRL_0_G_LOOP_MAX GENMASK(23, 16) +#define REG_SECENG_CDET_0_CTRL_0_STATUS GENMASK(15, 2) +#define REG_SECENG_CDET_0_CTRL_0_ERROR BIT(1) +#define REG_SECENG_CDET_0_CTRL_0_EN BIT(0) + +//se_cdet_0_ctrl_1 +#define REG_SECENG_CDET_0_CTRL_1 1028 +#define REG_SECENG_CDET_0_CTRL_1_G_SLP_N GENMASK(23, 16) +#define REG_SECENG_CDET_0_CTRL_1_T_DLY_N GENMASK(15, 8) +#define REG_SECENG_CDET_0_CTRL_1_T_LOOP_N GENMASK(7, 0) + +//se_cdet_0_ctrl_prot +#define REG_SECENG_CDET_0_CTRL_PROT 1276 +#define REG_SECENG_CDET_0_CTRL_PROT_ID1_EN BIT(2) +#define REG_SECENG_CDET_0_CTRL_PROT_ID0_EN BIT(1) +#define REG_SECENG_CDET_0_CTRL_PROT_PROT_EN BIT(0) + +//se_gmac_0_ctrl_0 +#define REG_SECENG_GMAC_0_CTRL_0 1280 +#define REG_SECENG_GMAC_0_CTRL_0_X_ENDIAN BIT(14) +#define REG_SECENG_GMAC_0_CTRL_0_H_ENDIAN BIT(13) +#define REG_SECENG_GMAC_0_CTRL_0_T_ENDIAN BIT(12) +#define REG_SECENG_GMAC_0_CTRL_0_INT_MASK BIT(11) +#define REG_SECENG_GMAC_0_CTRL_0_INT_SET_1T BIT(10) +#define REG_SECENG_GMAC_0_CTRL_0_INT_CLR_1T BIT(9) +#define REG_SECENG_GMAC_0_CTRL_0_INT BIT(8) +#define REG_SECENG_GMAC_0_CTRL_0_EN BIT(2) +#define REG_SECENG_GMAC_0_CTRL_0_TRIG_1T BIT(1) +#define REG_SECENG_GMAC_0_CTRL_0_BUSY BIT(0) + +//se_gmac_0_lca +#define REG_SECENG_GMAC_0_LCA 1284 + +//se_gmac_0_status +#define REG_SECENG_GMAC_0_STATUS 1288 + +//se_gmac_0_ctrl_prot +#define REG_SECENG_GMAC_0_CTRL_PROT 1532 +#define REG_SECENG_GMAC_0_CTRL_PROT_ID1_EN BIT(2) +#define REG_SECENG_GMAC_0_CTRL_PROT_ID0_EN BIT(1) + +//se_ctrl_prot_rd +#define REG_SECENG_CTRL_PROT_RD 3840 +#define REG_SECENG_CTRL_PROT_RD_DBG_DIS BIT(31) +#define REG_SECENG_CTRL_PROT_RD_GMAC_ID1_EN_RD BIT(11) +#define REG_SECENG_CTRL_PROT_RD_GMAC_ID0_EN_RD BIT(10) +#define REG_SECENG_CTRL_PROT_RD_CDET_ID1_EN_RD BIT(9) +#define REG_SECENG_CTRL_PROT_RD_CDET_ID0_EN_RD BIT(8) +#define REG_SECENG_CTRL_PROT_RD_PKA_ID1_EN_RD BIT(7) +#define REG_SECENG_CTRL_PROT_RD_PKA_ID0_EN_RD BIT(6) +#define REG_SECENG_CTRL_PROT_RD_TRNG_ID1_EN_RD BIT(5) +#define REG_SECENG_CTRL_PROT_RD_TRNG_ID0_EN_RD BIT(4) +#define REG_SECENG_CTRL_PROT_RD_AES_ID1_EN_RD BIT(3) +#define REG_SECENG_CTRL_PROT_RD_AES_ID0_EN_RD BIT(2) +#define REG_SECENG_CTRL_PROT_RD_SHA_ID1_EN_RD BIT(1) +#define REG_SECENG_CTRL_PROT_RD_SHA_ID0_EN_RD BIT(0) + +struct bflb_seceng { + struct mutex lock; + struct device *dev; + void __iomem *base; + struct regmap *map; + unsigned int initialised; + + struct hwrng hwrng; +}; + +struct bflb_seceng_ctx { + struct bflb_seceng *seceng; +}; + +struct regmap_config bflb_seceng_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .cache_type = REGCACHE_FLAT, + .max_register = 512 * sizeof(u32), + .num_reg_defaults_raw = 512, + .use_relaxed_mmio = true, + .use_raw_spinlock = true, +}; + +static struct bflb_seceng *bflb_seceng_dev; + +static void bflb_seceng_trng_wait_ready(void) +{ + while (readl_relaxed(bflb_seceng_dev->base + REG_SECENG_TRNG_0_CTRL_0) & + REG_SECENG_TRNG_0_CTRL_0_BUSY) { + dev_dbg(bflb_seceng_dev->dev, "Waiting for TRNG ready"); + schedule(); + } +} + +static void bflb_seceng_trng_init(void) +{ + regmap_update_bits(bflb_seceng_dev->map, REG_SECENG_TRNG_0_CTRL_0, + REG_SECENG_TRNG_0_CTRL_0_EN | REG_SECENG_TRNG_0_CTRL_0_INT_CLR_1T, + FIELD_PREP(REG_SECENG_TRNG_0_CTRL_0_EN, 1) | + FIELD_PREP(REG_SECENG_TRNG_0_CTRL_0_INT_CLR_1T, 1)); + + bflb_seceng_trng_wait_ready(); +} + +static void bflb_seceng_trng_refresh(void) +{ + regmap_update_bits(bflb_seceng_dev->map, REG_SECENG_TRNG_0_CTRL_0, + REG_SECENG_TRNG_0_CTRL_0_DOUT_CLR_1T, + FIELD_PREP(REG_SECENG_TRNG_0_CTRL_0_DOUT_CLR_1T, 1)); //Clear DOUT + + bflb_seceng_trng_wait_ready(); + + regmap_update_bits(bflb_seceng_dev->map, REG_SECENG_TRNG_0_CTRL_0, + REG_SECENG_TRNG_0_CTRL_0_DOUT_CLR_1T, + FIELD_PREP(REG_SECENG_TRNG_0_CTRL_0_DOUT_CLR_1T, 0)); //Reset clear DOUT + + regmap_update_bits(bflb_seceng_dev->map, + REG_SECENG_TRNG_0_CTRL_0, REG_SECENG_TRNG_0_CTRL_0_TRIG_1T, + FIELD_PREP(REG_SECENG_TRNG_0_CTRL_0_TRIG_1T, 1)); //Force TRNG refresh + + bflb_seceng_trng_wait_ready(); + + regmap_update_bits(bflb_seceng_dev->map, REG_SECENG_TRNG_0_CTRL_0, + REG_SECENG_TRNG_0_CTRL_0_INT_CLR_1T, + FIELD_PREP(REG_SECENG_TRNG_0_CTRL_0_INT_CLR_1T, 1)); //Clear INT + + dev_dbg(bflb_seceng_dev->dev, "Refreshed TRNG"); +} + +static unsigned int bflb_seceng_trng_read_dout(struct bflb_seceng *seceng, + unsigned int doutreg) +{ + return readl_relaxed(seceng->base + REG_SECENG_TRNG_0_DOUT_0 + + (doutreg * 4)); +} + +static inline unsigned int bflb_seceng_trng_read32(void) +{ + static u8 doutreg = 8; + u32 val; + + if (doutreg >= 8) { + //If we have read all available registers (of starting anew), + //refresh them and start again + doutreg = 0; + + bflb_seceng_trng_refresh(); + } + + dev_dbg(bflb_seceng_dev->dev, "Selected TRNG DOUT register %u", doutreg); + + //Read selected register + val = bflb_seceng_trng_read_dout(bflb_seceng_dev, doutreg); + doutreg++; //Move on to next register + + dev_dbg(bflb_seceng_dev->dev, "TRNG DOUT register produced %u", val); + + return val; +} + +static inline u8 bflb_seceng_trng_read8(void) +{ + static unsigned int lastread; + static u8 shift = 4; + + if (shift == 4) { + shift = 0; + + lastread = bflb_seceng_trng_read32(); + } + + return (lastread >> (shift++ * 8)) & 0xFF; +} + +static void bflb_seceng_trng_fill_buffer(u8 *buff, unsigned long bufflen) +{ + unsigned long i; + + for (i = 0; i < bufflen; i++) + buff[i] = bflb_seceng_trng_read8(); +} + +static int bflb_seceng_trng_hwrng_read(struct hwrng *rng, void *data, + size_t max, bool wait) +{ + //Currently ignoring wait + + mutex_lock(&bflb_seceng_dev->lock); + + dev_dbg(bflb_seceng_dev->dev, "Starting TRNG hwrng read for %lu bytes...", + max); + + bflb_seceng_trng_fill_buffer(data, max); + + mutex_unlock(&bflb_seceng_dev->lock); + + //We're always going to fill the buffer, so just return what was asked for + return max; +} + +static int bflb_seceng_trng_crypto_generate(struct crypto_rng *tfm, + const u8 *src, unsigned int slen, u8 *dstn, unsigned int dlen) +{ + struct bflb_seceng_ctx *ctx = crypto_rng_ctx(tfm); + struct bflb_seceng *seceng = ctx->seceng; + + mutex_lock(&seceng->lock); + + dev_dbg(seceng->dev, + "Starting TRNG crypto buffer filling read for %u bytes...", dlen); + + bflb_seceng_trng_fill_buffer(dstn, dlen); + + mutex_unlock(&seceng->lock); + + return 0; +} + +static int bflb_seceng_trng_crypto_seed(struct crypto_rng *tfm, const u8 *seed, + unsigned int slen) +{ + return 0; +} + +static int bflb_seceng_trng_crypto_init(struct crypto_tfm *tfm) +{ + struct bflb_seceng_ctx *ctx = crypto_tfm_ctx(tfm); + + ctx->seceng = bflb_seceng_dev; + + //Skip actual initialisation of the hardware if we have already done so + if (bflb_seceng_dev->initialised) + return 0; + + bflb_seceng_trng_init(); + + dev_dbg(bflb_seceng_dev->dev, "Initialised TRNG via crypto"); + + bflb_seceng_dev->initialised = 1; + return 0; +} + +static int bflb_seceng_trng_hwrng_init(struct hwrng *rng) +{ + if (bflb_seceng_dev->initialised) + return 0; + + bflb_seceng_trng_init(); + + dev_dbg(bflb_seceng_dev->dev, "Initialised TRNG via hwrng"); + + bflb_seceng_dev->initialised = 1; + return 0; +} + +static struct rng_alg bflb_seceng_trng_alg = { + .generate = bflb_seceng_trng_crypto_generate, + .seed = bflb_seceng_trng_crypto_seed, + .seedsize = 0, + .base = { + .cra_name = "stdrng", + .cra_driver_name = "bflb-seceng", + .cra_flags = CRYPTO_ALG_TYPE_RNG, + .cra_priority = 300, + .cra_ctxsize = sizeof(struct bflb_seceng_ctx), + .cra_module = THIS_MODULE, + .cra_init = bflb_seceng_trng_crypto_init, + } +}; + +static struct hwrng bflb_hwrng = { + .name = "bflb-seceng", + .init = bflb_seceng_trng_hwrng_init, + .read = bflb_seceng_trng_hwrng_read, +}; + +static int bflb_seceng_probe(struct platform_device *pdev) +{ + struct bflb_seceng *seceng; + int ret; + + seceng = devm_kzalloc(&pdev->dev, sizeof(*seceng), GFP_KERNEL); + + if (!seceng) + return -ENOMEM; + + seceng->dev = &pdev->dev; + + platform_set_drvdata(pdev, seceng); + mutex_init(&seceng->lock); + + seceng->base = devm_platform_ioremap_resource(pdev, 0); + + if (IS_ERR(seceng->base)) + return PTR_ERR(seceng->base); + + seceng->map = devm_regmap_init_mmio(&pdev->dev, seceng->base, + &bflb_seceng_regmap_config); + + if (IS_ERR(seceng->map)) + return dev_err_probe(&pdev->dev, PTR_ERR(seceng->map), + "Failed to create regmap\n"); + + bflb_seceng_dev = seceng; //Assign driver static + + ret = crypto_register_rng(&bflb_seceng_trng_alg); + + if (ret) + dev_err_probe(&pdev->dev, ret, + "Failed to register as a crypto random number generator\n"); + + seceng->hwrng = bflb_hwrng; + + ret = hwrng_register(&seceng->hwrng); + + if (ret) + dev_err_probe(&pdev->dev, ret, + "Failed to register as a hardware random number generator\n"); + + dev_info(&pdev->dev, "Bouffalo Lab Secure Engine"); + + return ret; +} + +static int bflb_seceng_remove(struct platform_device *pdev) +{ + hwrng_unregister(&bflb_seceng_dev->hwrng); + crypto_unregister_rng(&bflb_seceng_trng_alg); + + bflb_seceng_dev = NULL; + + return 0; +} + +static const struct of_device_id __maybe_unused bflb_seceng_of_match[] = { + { .compatible = "bflb,seceng", .data = (const void *)0, }, + {} +}; +MODULE_DEVICE_TABLE(of, bflb_seceng_of_match); + +static struct platform_driver bflb_seceng_driver = { + .probe = bflb_seceng_probe, + .remove = bflb_seceng_remove, + .driver = { + .name = "bflb-seceng", + .of_match_table = bflb_seceng_of_match, + .suppress_bind_attrs = true, + } +}; +module_platform_driver(bflb_seceng_driver); + +MODULE_DESCRIPTION("Bouffalo BL808 Secure Engine driver"); +MODULE_AUTHOR("Alexander Horner "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7d5f5458c72ed2..9120cd4b761f6a 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -127,6 +127,22 @@ config PINCTRL_AXP209 selected. Say Y to enable pinctrl and GPIO support for the AXP209 PMIC. +config PINCTRL_BFLB_GPIO + tristate "Bouffalo Lab SoC GPIO pin controller driver" + depends on SOC_BOUFFALOLAB + select PINMUX + select GPIOLIB + select GPIOLIB_IRQCHIP + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select OF_GPIO + help + This is the driver for the GPIO controller found on Bouffalo Lab RISC-V SoCs. + + This driver can also be built as a module. If so, the module + will be called pinctrl-bflb-gpio. + config PINCTRL_BM1880 bool "Bitmain BM1880 Pinctrl driver" depends on OF && (ARCH_BITMAIN || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2ad5..9f7c89ed4bb40f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o +obj-$(CONFIG_PINCTRL_BFLB_GPIO) += pinctrl-bflb.o obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o diff --git a/drivers/pinctrl/pinctrl-bflb.c b/drivers/pinctrl/pinctrl-bflb.c new file mode 100644 index 00000000000000..4223fcc18ed591 --- /dev/null +++ b/drivers/pinctrl/pinctrl-bflb.c @@ -0,0 +1,719 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Bouffalo Lab SoC pinctrl+GPIO+external IRQ driver + * + * Based on: pinctrl-apple-gpio.c + * Copyright (C) The Asahi Linux Contributors + * Copyright (C) 2020 Corellium LLC + * + * Based on: pinctrl-pistachio.c + * Copyright (C) 2014 Imagination Technologies Ltd. + * Copyright (C) 2014 Google, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "pinctrl-utils.h" +#include "core.h" +#include "pinmux.h" + +struct bflb_gpio_pinctrl { + struct device *dev; + struct pinctrl_dev *pctldev; + + void __iomem *base; + struct regmap *map; + + struct pinctrl_desc pinctrl_desc; + struct gpio_chip gpio_chip; + + void *irqsunmasked; + u8 irqgrps[]; +}; + +//Register indexing +#define REG_GPIO(x) (4 * (x)) + +//Register map +#define REG_GPIOx_MODE GENMASK(31, 30) +#define REG_GPIOx_I BIT(28) +#define REG_GPIOx_CLR BIT(26) +#define REG_GPIOx_SET BIT(25) +#define REG_GPIOx_O BIT(24) +#define REG_GPIOx_INT_MASK BIT(22) +#define REG_GPIOx_INT_STAT BIT(21) +#define REG_GPIOx_INT_CLR BIT(20) +#define REG_GPIOx_INT_MODE_SET GENMASK(29, 16) +#define REG_GPIOx_FUNC_SEL GENMASK(12, 8) +#define REG_GPIOx_OE BIT(6) +#define REG_GPIOx_PD BIT(5) +#define REG_GPIOx_PU BIT(4) +#define REG_GPIOx_DRV GENMASK(3, 2) +#define REG_GPIOx_SMT BIT(1) +#define REG_GPIOx_IE BIT(0) + +//Interrupt trigger modes +#define BFLB_IRQ_MODE_SYNC_EDGE_FALLING 0 +#define BFLB_IRQ_MODE_SYNC_EDGE_RISING 1 +#define BFLB_IRQ_MODE_SYNC_LEVEL_LOW 2 +#define BFLB_IRQ_MODE_SYNC_LEVEL_HIGH 3 +#define BFLB_IRQ_MODE_SYNC_EDGE_BOTH 4 + +#define BFLB_IRQ_MODE_ASYNC_EDGE_FALLING 8 +#define BFLB_IRQ_MODE_ASYNC_EDGE_RISING 9 +#define BFLB_IRQ_MODE_ASYNC_LEVEL_LOW 10 +#define BFLB_IRQ_MODE_ASYNC_LEVEL_HIGH 11 + +static const char * const pinmux_functions[] = { + //AH: As taken from smaeul's pinctrl-bflb.c for U-Boot + [0] = "sdh", + [1] = "spi0", + [2] = "flash", + [3] = "i2s", + [4] = "pdm", + [5] = "i2c0", + [6] = "i2c1", + [7] = "uart", + [8] = "emac", + [9] = "cam", + [10] = "analog", + [11] = "gpio", + [16] = "pwm0", + [17] = "pwm1", + [18] = "spi1", // mm_spi + [19] = "i2c2", // mm_i2c0 + [20] = "i2c3", // mm_i2c1 + [21] = "mm_uart", + [22] = "dbi_b", + [23] = "dbi_c", + [24] = "dpi", + [25] = "jtag_lp", + [26] = "jtag_m0", + [27] = "jtag_d0", + [31] = "clock", +}; + +struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .cache_type = REGCACHE_FLAT, + .max_register = 512 * sizeof(u32), + .num_reg_defaults_raw = 512, + .use_relaxed_mmio = true, + .use_raw_spinlock = true, +}; + +//AH: Set raw gpio config register bits based on mask +static void bflb_gpio_set_reg(struct bflb_gpio_pinctrl *pctl, unsigned int pin, + u32 mask, u32 value) +{ + regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); +} + +//AH: Get raw gpio config register bits +static u32 bflb_gpio_get_reg(struct bflb_gpio_pinctrl *pctl, unsigned int pin) +{ + int ret; + u32 val; + + ret = regmap_read(pctl->map, REG_GPIO(pin), &val); + + if (ret) + return 0; + + return val; +} + +/* Pin controller functions */ + +static const struct pinctrl_ops bflb_gpio_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +/* Pin multiplexer functions */ + +//AH: Configure gpio modes and features +static int bflb_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned int func, + unsigned int group) +{ + struct bflb_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + bflb_gpio_set_reg(pctl, group, REG_GPIOx_FUNC_SEL, + FIELD_PREP(REG_GPIOx_FUNC_SEL, func)); + + dev_dbg(pctl->dev, "Pin %u set to function %u", group, func); + + return 0; +} + +static const struct pinmux_ops bflb_gpio_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = bflb_gpio_pinmux_set, + .strict = true, +}; + +/* GPIO chip functions */ + +//AH: Get the current gpio direction +static int bflb_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + unsigned int reg = bflb_gpio_get_reg(pctl, offset); + + if (FIELD_GET(REG_GPIOx_OE, reg) == 1 && + FIELD_GET(REG_GPIOx_IE, reg) == 0) { + return GPIO_LINE_DIRECTION_OUT; + } else if (FIELD_GET(REG_GPIOx_IE, reg) == 1 && + FIELD_GET(REG_GPIOx_OE, reg) == 0) { + return GPIO_LINE_DIRECTION_IN; + } + + return -EIO; +} + +//AH: Get the incoming input or outgoing output value for the specified GPIO +static int bflb_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + unsigned int reg = bflb_gpio_get_reg(pctl, offset); + + if (FIELD_GET(REG_GPIOx_OE, reg) == 1 && + FIELD_GET(REG_GPIOx_IE, reg) == 0) { + reg = readl_relaxed(pctl->base + REG_GPIO(offset)); + return !!(reg & REG_GPIOx_O); + } else if (FIELD_GET(REG_GPIOx_IE, reg) == 1 && + FIELD_GET(REG_GPIOx_OE, reg) == 0) { + reg = readl_relaxed(pctl->base + REG_GPIO(offset)); + return !!(reg & REG_GPIOx_I); + } + + return -EIO; +} + +//AH: Set the specified GPIO's output state +static void bflb_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_O, value ? + FIELD_PREP(REG_GPIOx_O, 1) : 0); + + dev_dbg(pctl->dev, "Pin %u set to value %u", offset, value); +} + +//AH: Set the specified gpio direction to input +static int bflb_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_OE | REG_GPIOx_IE | REG_GPIOx_SMT, + FIELD_PREP(REG_GPIOx_OE, 0) | FIELD_PREP(REG_GPIOx_IE, 1) | + FIELD_PREP(REG_GPIOx_SMT, 1)); + + dev_dbg(pctl->dev, "Pin %u set to direction input", offset); + + return 0; +} + +//AH: Set the specified gpio direction to output +static int bflb_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_PD | REG_GPIOx_PU | REG_GPIOx_OE | + REG_GPIOx_IE | REG_GPIOx_SMT | REG_GPIOx_MODE, + FIELD_PREP(REG_GPIOx_PD, 0) | FIELD_PREP(REG_GPIOx_PU, 0) | + FIELD_PREP(REG_GPIOx_OE, 1) | FIELD_PREP(REG_GPIOx_IE, 0) | + FIELD_PREP(REG_GPIOx_SMT, 1) | FIELD_PREP(REG_GPIOx_MODE, 0)); + + dev_dbg(pctl->dev, "Pin %u set to direction output", offset); + + bflb_gpio_set(chip, offset, value); //Set the initially passed value + + return 0; +} + +//AH: Configure pin electrical characteristics +static int bflb_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + enum pin_config_param param = pinconf_to_config_param(config); + unsigned int arg = pinconf_to_config_argument(config); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_PD | REG_GPIOx_PU, + FIELD_PREP(REG_GPIOx_PD, 0) | FIELD_PREP(REG_GPIOx_PU, 0)); + break; + + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (arg) { + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_PD | REG_GPIOx_PU, + FIELD_PREP(REG_GPIOx_PD, 0) | FIELD_PREP(REG_GPIOx_PU, 0)); + } + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg) { + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_PD | REG_GPIOx_PU, + FIELD_PREP(REG_GPIOx_PD, 1) | FIELD_PREP(REG_GPIOx_PU, 0)); + } + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (arg) { + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_PD | REG_GPIOx_PU, + FIELD_PREP(REG_GPIOx_PD, 0) | FIELD_PREP(REG_GPIOx_PU, 1)); + } + break; + + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_PD | REG_GPIOx_PU | + REG_GPIOx_IE | REG_GPIOx_OE, FIELD_PREP(REG_GPIOx_PD, 0) | + FIELD_PREP(REG_GPIOx_PU, 0) | FIELD_PREP(REG_GPIOx_IE, 0) | + FIELD_PREP(REG_GPIOx_OE, 0)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_IE, + FIELD_PREP(REG_GPIOx_IE, !!arg)); + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_SMT, + FIELD_PREP(REG_GPIOx_SMT, !!arg)); + break; + + case PIN_CONFIG_OUTPUT: + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_OE | REG_GPIOx_O, + FIELD_PREP(REG_GPIOx_OE, 1) | FIELD_PREP(REG_GPIOx_O, !!arg)); + break; + + case PIN_CONFIG_OUTPUT_ENABLE: + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_OE, + FIELD_PREP(REG_GPIOx_OE, 1)); + break; + + default: return -ENOTSUPP; + } + + dev_dbg(pctl->dev, "Pin %u config set to %lu (param %u, arg %u)", offset, + config, param, arg); + + return 0; +} + +/* IRQ chip functions */ + +//AH: Clear the interrupt for the specified GPIO +static void bflb_gpio_irq_ack(struct irq_data *data) +{ + struct bflb_gpio_pinctrl *pctl = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); + + bflb_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_INT_CLR, + FIELD_PREP(REG_GPIOx_INT_CLR, 1)); + + bflb_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_INT_CLR, + FIELD_PREP(REG_GPIOx_INT_CLR, 0)); + + dev_dbg(pctl->dev, "Pin %lu IRQ ACK", data->hwirq); +} + +//AH: Find the correct value for the type of interrupts we want to receive +//for a GPIO +static unsigned int bflb_gpio_irq_type(unsigned int type) +{ + unsigned int selected; + + switch (type & IRQ_TYPE_SENSE_MASK) { + + case IRQ_TYPE_EDGE_RISING: + selected = BFLB_IRQ_MODE_SYNC_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_FALLING: + selected = BFLB_IRQ_MODE_SYNC_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_BOTH: + selected = BFLB_IRQ_MODE_SYNC_EDGE_BOTH; + break; + + case IRQ_TYPE_LEVEL_HIGH: + selected = BFLB_IRQ_MODE_SYNC_LEVEL_HIGH; + break; + + case IRQ_TYPE_LEVEL_LOW: + selected = BFLB_IRQ_MODE_SYNC_LEVEL_LOW; + break; + + //No "off" available on BL808, set to default IRQ_TYPE_EDGE_FALLING and + //then we'll need to mask + default: + selected = BFLB_IRQ_MODE_SYNC_EDGE_FALLING; + break; + } + + return selected; +} + +//AH: Disable the specified GPIO's interrupt +static void bflb_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(gc); + + bflb_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_INT_MASK, + FIELD_PREP(REG_GPIOx_INT_MASK, 1)); + + clear_bit(data->hwirq, pctl->irqsunmasked); + gpiochip_disable_irq(gc, data->hwirq); + + dev_dbg(pctl->dev, "Pin %lu IRQ Mask", data->hwirq); +} + +//AH: Enable the specified GPIO's interrupt +static void bflb_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(gc); + unsigned int irqtype = bflb_gpio_irq_type(irqd_get_trigger_type(data)); + + gpiochip_enable_irq(gc, data->hwirq); + set_bit(data->hwirq, pctl->irqsunmasked); + + bflb_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_INT_MASK | + REG_GPIOx_INT_MODE_SET, FIELD_PREP(REG_GPIOx_INT_MASK, 0) | + FIELD_PREP(REG_GPIOx_INT_MODE_SET, irqtype)); + + dev_dbg(pctl->dev, "Pin %lu IRQ Unmask", data->hwirq); +} + +//AH: Initialise the specified GPIO's interrupt +static unsigned int bflb_gpio_irq_startup(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + + bflb_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_INT_CLR, + FIELD_PREP(REG_GPIOx_INT_CLR, 1)); + + bflb_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_INT_CLR, + FIELD_PREP(REG_GPIOx_INT_CLR, 0)); + + bflb_gpio_irq_unmask(data); + + dev_dbg(pctl->dev, "Pin %lu IRQ Started", data->hwirq); + + return 0; +} + +//AH: Set the specified GPIO's interrupt mode +static int bflb_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct bflb_gpio_pinctrl *pctl = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); + + unsigned int irqtype = bflb_gpio_irq_type(type); + + if (irqtype == 0) + return -EINVAL; + + bflb_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_INT_MODE_SET, + FIELD_PREP(REG_GPIOx_INT_MODE_SET, irqtype)); + + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(data, handle_level_irq); + else + irq_set_handler_locked(data, handle_edge_irq); + + dev_dbg(pctl->dev, "Pin %lu IRQ type set to %u", data->hwirq, irqtype); + + return 0; +} + +//AH: Handle GPIO interrupts on this controller +static void bflb_gpio_irq_handler(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + u8 *grpp = irq_desc_get_handler_data(desc); + struct bflb_gpio_pinctrl *pctl; + unsigned int pinh; + unsigned long reg; + struct gpio_chip *gc; + + pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]); + gc = &pctl->gpio_chip; + + chained_irq_enter(chip, desc); + + //We must go through each individual GPIO register to read its interrupt + //status. There is no gpio_cfg128+ helper register for interrupts + //(looking at BL808 RM) + for (pinh = 0; pinh < gc->ngpio; pinh += 1) { + if (test_bit(pinh, pctl->irqsunmasked)) { + dev_dbg(pctl->dev, "Reading IRQ status of pin %u", pinh); + + reg = readl_relaxed(pctl->base + REG_GPIO(pinh)); + + if (reg & REG_GPIOx_INT_STAT) { + generic_handle_domain_irq(gc->irq.domain, pinh); + dev_dbg(pctl->dev, "Pin %u IRQ Fire", pinh); + } + } else { + dev_dbg(pctl->dev, "Ignoring IRQ status of masked pin %u", pinh); + } + } + + chained_irq_exit(chip, desc); +} + +static const struct irq_chip bflb_gpio_irqchip = { + .name = "bflb-gpio", + .irq_startup = bflb_gpio_irq_startup, + .irq_ack = bflb_gpio_irq_ack, + .irq_mask = bflb_gpio_irq_mask, + .irq_unmask = bflb_gpio_irq_unmask, + .irq_set_type = bflb_gpio_irq_set_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int bflb_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + int ret; + struct bflb_gpio_pinctrl *pctl = gpiochip_get_data(chip); + + ret = pinctrl_gpio_request(chip->base + offset); + + if (ret) + return ret; + + bflb_gpio_set_reg(pctl, offset, REG_GPIOx_FUNC_SEL, + FIELD_PREP(REG_GPIOx_FUNC_SEL, 11/*SWGPIO*/)); + + dev_dbg(pctl->dev, "Pin %u set to function GPIO as part of request", + offset); + + return 0; +} + +/* Probe & register */ + +static int bflb_gpio_register(struct bflb_gpio_pinctrl *pctl) +{ + struct gpio_irq_chip *girq = &pctl->gpio_chip.irq; + void **irq_data = NULL; + int ret; + + pctl->gpio_chip.label = dev_name(pctl->dev); + pctl->gpio_chip.request = bflb_gpio_request; + pctl->gpio_chip.free = gpiochip_generic_free; + pctl->gpio_chip.get_direction = bflb_gpio_get_direction; + pctl->gpio_chip.direction_input = bflb_gpio_direction_input; + pctl->gpio_chip.direction_output = bflb_gpio_direction_output; + pctl->gpio_chip.get = bflb_gpio_get; + pctl->gpio_chip.set = bflb_gpio_set; + pctl->gpio_chip.set_config = bflb_gpio_set_config; + pctl->gpio_chip.base = -1; + pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins; + pctl->gpio_chip.parent = pctl->dev; + + if (girq->num_parents) { + int i; + + gpio_irq_chip_set_chip(girq, &bflb_gpio_irqchip); + + girq->parent_handler = bflb_gpio_irq_handler; + + girq->parents = kmalloc_array(girq->num_parents, sizeof(*girq->parents), + GFP_KERNEL); + irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data), + GFP_KERNEL); + + if (!girq->parents || !irq_data) { + ret = -ENOMEM; + goto out_free_irq_data; + } + + for (i = 0; i < girq->num_parents; i++) { + ret = platform_get_irq(to_platform_device(pctl->dev), i); + + if (ret < 0) + goto out_free_irq_data; + + girq->parents[i] = ret; + pctl->irqgrps[i] = i; + irq_data[i] = &pctl->irqgrps[i]; + } + + girq->parent_handler_data_array = irq_data; + girq->per_parent_data = true; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + } + + ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); + +out_free_irq_data: + kfree(girq->parents); + kfree(irq_data); + + return ret; +} + +static int bflb_gpio_pinctrl_probe(struct platform_device *pdev) +{ + struct bflb_gpio_pinctrl *pctl; + struct pinctrl_pin_desc *pins; + + unsigned int npins; + const char **pin_names; + unsigned int *pin_nums; + unsigned int i, nirqs = 0; + int res; + + if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) { + res = platform_irq_count(pdev); + if (res > 0) + nirqs = res; + } + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + + if (!pctl) + return -ENOMEM; + + pctl->dev = &pdev->dev; + pctl->gpio_chip.irq.num_parents = nirqs; + + dev_set_drvdata(&pdev->dev, pctl); + + if (of_property_read_u32(pdev->dev.of_node, "bflb,npins", &npins)) + return dev_err_probe(&pdev->dev, -EINVAL, + "bflb,npins property not found\n"); + + pctl->irqsunmasked = devm_bitmap_zalloc(&pdev->dev, npins, GFP_KERNEL); + + pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]), GFP_KERNEL); + pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]), + GFP_KERNEL); + pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]), + GFP_KERNEL); + + if (!pins || !pin_names || !pin_nums) + return -ENOMEM; + + pctl->base = devm_platform_ioremap_resource(pdev, 0); + + if (IS_ERR(pctl->base)) + return PTR_ERR(pctl->base); + + pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config); + + if (IS_ERR(pctl->map)) + return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map), + "Failed to create regmap\n"); + + for (i = 0; i < npins; i++) { + pins[i].number = i; + pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "GPIO%u", i); + pins[i].drv_data = pctl; + pin_names[i] = pins[i].name; + pin_nums[i] = i; + } + + pctl->pinctrl_desc.name = dev_name(pctl->dev); + pctl->pinctrl_desc.pins = pins; + pctl->pinctrl_desc.npins = npins; + pctl->pinctrl_desc.pctlops = &bflb_gpio_pinctrl_ops; + pctl->pinctrl_desc.pmxops = &bflb_gpio_pinmux_ops; + + pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, + pctl); + + if (IS_ERR(pctl->pctldev)) + return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev), + "Failed to register pinctrl device.\n"); + + for (i = 0; i < npins; i++) { + res = pinctrl_generic_add_group(pctl->pctldev, + pins[i].name, pin_nums + i, 1, pctl); + + dev_dbg(&pdev->dev, "Registered pin %s with numeric %u", + pins[i].name, i); + + if (res < 0) + return dev_err_probe(pctl->dev, res, "Failed to register group"); + } + + for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) { + if (pinmux_functions[i]) { + res = pinmux_generic_add_function(pctl->pctldev, + pinmux_functions[i], pin_names, npins, pctl); + + dev_dbg(&pdev->dev, "Registered function %s with numeric %u", + pinmux_functions[i], i); + + if (res < 0) + return dev_err_probe(pctl->dev, res, + "Failed to register function."); + } + } + + dev_info(&pdev->dev, "Bouffalo Lab pinctrl+GPIO(+interrupt) controller - " + "Registered %lu function(s) for %u pin(s)", + + ARRAY_SIZE(pinmux_functions), npins); + + return bflb_gpio_register(pctl); +} + +static const struct of_device_id bflb_gpio_pinctrl_of_match[] = { + { .compatible = "bflb,pinctrl", }, + { } +}; + +MODULE_DEVICE_TABLE(of, bflb_gpio_pinctrl_of_match); + +static struct platform_driver bflb_gpio_pinctrl_driver = { + .driver = { + .name = "bflb-gpio-pinctrl", + .of_match_table = bflb_gpio_pinctrl_of_match, + .suppress_bind_attrs = true, + }, + .probe = bflb_gpio_pinctrl_probe, +}; + +module_platform_driver(bflb_gpio_pinctrl_driver); + +MODULE_DESCRIPTION("Bouffalo BL808 pinctrl/GPIO driver"); +MODULE_AUTHOR("Alexander Horner "); +MODULE_LICENSE("GPL v2"); From f2387201c7c1d00453f22eb297c9c3a6dda88a4b Mon Sep 17 00:00:00 2001 From: Krzysztof Adamski Date: Wed, 12 Apr 2023 12:08:34 +0200 Subject: [PATCH 37/37] pinctrl: bflb: fix the numeric function values The function values to be written to the register are not consecutive (like there are no functions for values 12-15). The pinctrl subsystem assigns the indexes (selectors) for each function as they are added so the selector for pwm0 was 12, not 16. Since bflb_gpio_pinmux_set was using those selectors as a register value, all of the functions 12+ were not set correctly. For example for i2c2, the value of 15 was written to the register instead of 19. This patch fixes this problem by passing the index of the function from the table as a data parameter to the pinmux_generic_add_function() so that it can be retrieved in the bflb_gpio_pinmux_set() and used to set correct register value. Signed-off-by: Krzysztof Adamski --- drivers/pinctrl/pinctrl-bflb.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-bflb.c b/drivers/pinctrl/pinctrl-bflb.c index 4223fcc18ed591..c1296cc5d474c5 100644 --- a/drivers/pinctrl/pinctrl-bflb.c +++ b/drivers/pinctrl/pinctrl-bflb.c @@ -152,15 +152,17 @@ static const struct pinctrl_ops bflb_gpio_pinctrl_ops = { /* Pin multiplexer functions */ //AH: Configure gpio modes and features -static int bflb_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned int func, +static int bflb_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { struct bflb_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct function_desc *desc = pinmux_generic_get_function(pctldev, selector); + int *func = desc->data; bflb_gpio_set_reg(pctl, group, REG_GPIOx_FUNC_SEL, - FIELD_PREP(REG_GPIOx_FUNC_SEL, func)); + FIELD_PREP(REG_GPIOx_FUNC_SEL, *func)); - dev_dbg(pctl->dev, "Pin %u set to function %u", group, func); + dev_dbg(pctl->dev, "Pin %u set to function %u", group, *func); return 0; } @@ -593,11 +595,12 @@ static int bflb_gpio_pinctrl_probe(struct platform_device *pdev) { struct bflb_gpio_pinctrl *pctl; struct pinctrl_pin_desc *pins; + int *funcs; unsigned int npins; const char **pin_names; unsigned int *pin_nums; - unsigned int i, nirqs = 0; + unsigned int i, j, nirqs = 0; int res; if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) { @@ -627,6 +630,8 @@ static int bflb_gpio_pinctrl_probe(struct platform_device *pdev) GFP_KERNEL); pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]), GFP_KERNEL); + funcs = devm_kmalloc_array(&pdev->dev, ARRAY_SIZE(pinmux_functions), sizeof(funcs[0]), + GFP_KERNEL); if (!pins || !pin_names || !pin_nums) return -ENOMEM; @@ -674,10 +679,11 @@ static int bflb_gpio_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(pctl->dev, res, "Failed to register group"); } - for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) { + for (i = 0, j = 0; i < ARRAY_SIZE(pinmux_functions); ++i) { if (pinmux_functions[i]) { + funcs[j] = i; res = pinmux_generic_add_function(pctl->pctldev, - pinmux_functions[i], pin_names, npins, pctl); + pinmux_functions[i], pin_names, npins, &funcs[j]); dev_dbg(&pdev->dev, "Registered function %s with numeric %u", pinmux_functions[i], i); @@ -685,6 +691,7 @@ static int bflb_gpio_pinctrl_probe(struct platform_device *pdev) if (res < 0) return dev_err_probe(pctl->dev, res, "Failed to register function."); + j++; } }