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[aqilc]

Hey, just came across this and I would love to know more about how it works, what design decisions you made, and especially how to compile/simulate it. Which simulation/synthesis toolchains did you use?

This looks like a super cool project and an immense feat, awesome job on it! This is honestly super cool stuff.

[maxcai314]

Hi, sorry for the late response, I'm pretty bad at checking github notifications

This project was written in SystemVerilog and runs using the Vivado Design Suite. I used the RISC-V specification and followed the appendix chapters of Hennessy and Patterson's Computer Architecture: A Quantitative Approach for the hardware design. I first implemented a single-cycle CPU which implements all the features, then designed a simple pipeline.

I wasn't actually able to synthesize it due to some mysterious bug in Vivado and the specific FPGA I wanted to implement on, and I'm not really sure how to do that :/ I kinda stopped working on the project since then

[aqilc]

Wow, that's really cool. My school doesn't use Vivado so I don't have access to the synthesizer so I can't look at it myself :(. This is absolutely insane to do by yourself though.

Also, God Damn getting these mysterious Vivado bugs that are basically unsolvable is so relatable. Had to start over a couple times in my classes too, these softwares are less stable than Uranium 235. I wish I could help.