From 1a25b051b85be11b2c52b62b7799f9d7bc347713 Mon Sep 17 00:00:00 2001 From: lfdevs <109842948+lfdevs@users.noreply.github.com> Date: Fri, 9 Jan 2026 18:21:07 +0800 Subject: [PATCH 1/6] fix(main/mesa): Fix build errors caused by Adreno 710/720 Try to fix unofficial support for Adreno 710 and Adreno 720 to prevent build errors. The added values `tile_max_w` and `tile_max_h` were derived by analogy with the Adreno 730 and have not been empirically validated. --- ...016-unofficial_support_adreno_710_720.patch | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/packages/mesa/0016-unofficial_support_adreno_710_720.patch b/packages/mesa/0016-unofficial_support_adreno_710_720.patch index 650d62a1463..ef35a1bc4dd 100644 --- a/packages/mesa/0016-unofficial_support_adreno_710_720.patch +++ b/packages/mesa/0016-unofficial_support_adreno_710_720.patch @@ -7,7 +7,7 @@ https://gitlab.freedesktop.org/mesa/mesa/-/issues/13036 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py -@@ -1065,6 +1065,42 @@ add_gpus([ +@@ -1171,6 +1171,46 @@ add_gpus([ raw_magic_regs = a730_raw_magic_regs, )) @@ -20,6 +20,8 @@ https://gitlab.freedesktop.org/mesa/mesa/-/issues/13036 + num_ccu = 4, + tile_align_w = 64, + tile_align_h = 32, ++ tile_max_w = 1024, ++ tile_max_h = 1024, + num_vsc_pipes = 32, + cs_shared_mem_size = 32 * 1024, + wave_granularity = 2, @@ -38,6 +40,8 @@ https://gitlab.freedesktop.org/mesa/mesa/-/issues/13036 + num_ccu = 4, + tile_align_w = 64, + tile_align_h = 32, ++ tile_max_w = 1024, ++ tile_max_h = 1024, + num_vsc_pipes = 32, + cs_shared_mem_size = 32 * 1024, + wave_granularity = 2, @@ -50,11 +54,13 @@ https://gitlab.freedesktop.org/mesa/mesa/-/issues/13036 add_gpus([ GPUId(chip_id=0x07030001, name="FD730"), # KGSL, no speedbin data GPUId(chip_id=0xffff07030001, name="FD730"), # Default no-speedbin fallback +diff --git a/src/freedreno/drm-shim/freedreno_noop.c b/src/freedreno/drm-shim/freedreno_noop.c +index 4c3e817fce7..bdfba0f5613 100644 --- a/src/freedreno/drm-shim/freedreno_noop.c +++ b/src/freedreno/drm-shim/freedreno_noop.c -@@ -237,6 +237,16 @@ static const struct msm_device_info device_infos[] = { - .chip_id = CHIPID(6, 6, 0, 0xff), - .gmem_size = 1024 * 1024 + 512 * 1024, +@@ -236,6 +236,16 @@ static const struct msm_device_info device_infos[] = { + .chip_id = CHIPID(5, 1, 0, 0xff), + .gmem_size = 256 * 1024, }, + { + .gpu_id = 710 @@ -67,5 +73,5 @@ https://gitlab.freedesktop.org/mesa/mesa/-/issues/13036 + .gmem_size = 2 * 1024 * 1024, + }, { - .gpu_id = 730, - .chip_id = 0x07030001, + .gpu_id = 530, + .chip_id = CHIPID(5, 3, 0, 2), From d97c3610c8bf1f95837f109bc4778a59ce54e1a7 Mon Sep 17 00:00:00 2001 From: lfdevs <109842948+lfdevs@users.noreply.github.com> Date: Sun, 11 Jan 2026 22:30:19 +0800 Subject: [PATCH 2/6] bump(main/mesa): 26.0.0 Sync with upstream code: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39167 --- packages/mesa/build.sh | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/packages/mesa/build.sh b/packages/mesa/build.sh index 190a7591320..94ee2bcea22 100644 --- a/packages/mesa/build.sh +++ b/packages/mesa/build.sh @@ -3,9 +3,10 @@ TERMUX_PKG_DESCRIPTION="An open-source implementation of the OpenGL specificatio TERMUX_PKG_LICENSE="MIT" TERMUX_PKG_LICENSE_FILE="docs/license.rst" TERMUX_PKG_MAINTAINER="@termux" -TERMUX_PKG_VERSION="25.3.4" -TERMUX_PKG_SRCURL=https://archive.mesa3d.org/mesa-${TERMUX_PKG_VERSION}.tar.xz -TERMUX_PKG_SHA256=3a0fc6ec070b45ae25dc2ccb5e52fae1d89141f7c39c4a91fe4eaa80dfff9deb +TERMUX_PKG_VERSION="26.0.0" +TERMUX_PKG_SRCURL=git+https://gitlab.freedesktop.org/robclark/mesa.git +TERMUX_PKG_GIT_BRANCH=tu/gen8 +_COMMIT=81075945d6c2dda77c6609180f3fcb6fd80372ab TERMUX_PKG_AUTO_UPDATE=true TERMUX_PKG_DEPENDS="libandroid-shmem, libc++, libdrm, libglvnd, libllvm (<< $TERMUX_LLVM_NEXT_MAJOR_VERSION), libwayland, libx11, libxext, libxfixes, libxshmfence, libxxf86vm, ncurses, vulkan-loader, zlib, zstd" TERMUX_PKG_SUGGESTS="mesa-dev" From 4dc29b450c1025b1754aa0979e8419db14038590 Mon Sep 17 00:00:00 2001 From: lfdevs <109842948+lfdevs@users.noreply.github.com> Date: Fri, 16 Jan 2026 21:32:11 +0800 Subject: [PATCH 3/6] enhance(main/mesa): Add unofficial support for Adreno 830 --- .../0019-unofficial-support-adreno-830.patch | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 packages/mesa/0019-unofficial-support-adreno-830.patch diff --git a/packages/mesa/0019-unofficial-support-adreno-830.patch b/packages/mesa/0019-unofficial-support-adreno-830.patch new file mode 100644 index 00000000000..33ae38135cb --- /dev/null +++ b/packages/mesa/0019-unofficial-support-adreno-830.patch @@ -0,0 +1,85 @@ +Modified based on Adreno 840, most features should work. + +--- a/src/freedreno/common/freedreno_devices.py ++++ b/src/freedreno/common/freedreno_devices.py +@@ -1499,28 +1499,6 @@ a8xx_gen2 = GPUProps( + has_fs_tex_prefetch = False, + ) + +-# Totally fake, just to get cffdump to work: +-add_gpus([ +- GPUId(chip_id=0x44050000, name="FD830"), +- ], A6xxGPUInfo( +- CHIP.A8XX, +- [a7xx_base, a7xx_gen3, a8xx_base], +- num_ccu = 6, +- num_slices = 3, +- tile_align_w = 64, +- tile_align_h = 32, +- tile_max_w = 16384, +- tile_max_h = 16384, +- num_vsc_pipes = 32, +- cs_shared_mem_size = 32 * 1024, +- wave_granularity = 2, +- fibers_per_sp = 128 * 2 * 16, +- magic_regs = dict( +- ), +- raw_magic_regs = [ +- ], +- )) +- + # For a8xx, the chicken bit and most other non-ctx reg + # programming moves into the kernel, and what remains + # should be easier to share between devices +@@ -1555,6 +1533,29 @@ a8xx_gen2_raw_magic_regs = [ + [A6XXRegs.REG_A8XX_PC_MODE_CNTL, 0x00003f00], + ] + ++# Modified based on Adreno 840, most features should work ++add_gpus([ ++ GPUId(chip_id=0x44050000, name="FD830"), ++ GPUId(chip_id=0xffff44050001, name="Adreno (TM) 830"), ++ ], A6xxGPUInfo( ++ CHIP.A8XX, ++ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_gen2, ++ GPUProps(shading_rate_matches_vk = True)], ++ num_ccu = 6, ++ num_slices = 3, ++ tile_align_w = 96, ++ tile_align_h = 32, ++ tile_max_w = 16416, ++ tile_max_h = 16384, ++ num_vsc_pipes = 32, ++ cs_shared_mem_size = 32 * 1024, ++ wave_granularity = 2, ++ fibers_per_sp = 128 * 2 * 16, ++ magic_regs = dict( ++ ), ++ raw_magic_regs = a8xx_gen2_raw_magic_regs, ++ )) ++ + add_gpus([ + GPUId(chip_id=0xffff44050A31, name="Adreno (TM) 840"), + ], A6xxGPUInfo( +--- a/src/freedreno/drm-shim/freedreno_noop.c ++++ b/src/freedreno/drm-shim/freedreno_noop.c +@@ -288,7 +288,7 @@ static const struct msm_device_info device_infos[] = { + }, + { + .gpu_id = 830, +- .chip_id = 0x44050000, ++ .chip_id = 0x44050001, + .gmem_size = 12 * 1024 * 1024, + }, + }; +--- a/src/freedreno/ir3/tests/disasm.c ++++ b/src/freedreno/ir3/tests/disasm.c +@@ -33,7 +33,7 @@ + #define INSTR_6XX_RAW(i, d, ...) { .gpu_id = 630, .instr = NULL, .instr_raw = i, .expected = d, __VA_ARGS__ } + #define INSTR_7XX(i, d, ...) { .chip_id = 0x07030001, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ } + #define INSTR_7XX_RAW(i, d, ...) { .chip_id = 0x07030001, .instr = NULL, .instr_raw = i, .expected = d, __VA_ARGS__ } +-#define INSTR_8XX(i, d, ...) { .chip_id = 0x44050000, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ } ++#define INSTR_8XX(i, d, ...) { .chip_id = 0x44050001, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ } + /* clang-format on */ + + static const struct test { From d0af9841f6f8221932923359a894675be0299eb1 Mon Sep 17 00:00:00 2001 From: lfdevs <109842948+lfdevs@users.noreply.github.com> Date: Tue, 3 Feb 2026 17:00:41 +0800 Subject: [PATCH 4/6] bump(main/mesa): 26.1.0 Sync with upstream code: https://gitlab.freedesktop.org/mesa/mesa/-/commit/6ea4fe9806b93ee9c4f0dd1b571e4a4a52c666ca --- packages/mesa/0004-do-not-check-xlocale.patch | 7 ++++--- packages/mesa/build.sh | 8 ++++---- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/packages/mesa/0004-do-not-check-xlocale.patch b/packages/mesa/0004-do-not-check-xlocale.patch index 1419dfcd9d5..55f437a3d45 100644 --- a/packages/mesa/0004-do-not-check-xlocale.patch +++ b/packages/mesa/0004-do-not-check-xlocale.patch @@ -1,12 +1,13 @@ +++ ./meson.build -@@ -1403,8 +1403,8 @@ +@@ -1462,9 +1462,8 @@ if not ['linux'].contains(host_machine.system()) endif endif -foreach h : ['xlocale.h', 'linux/futex.h', 'endian.h', 'dlfcn.h', 'sys/shm.h', -- 'cet.h', 'pthread_np.h', 'sys/inotify.h', 'linux/udmabuf.h'] +- 'cet.h', 'pthread_np.h', 'poll.h', 'sys/inotify.h', +- 'linux/udmabuf.h'] +foreach h : ['linux/futex.h', 'endian.h', 'dlfcn.h', 'sys/shm.h', -+ 'cet.h', 'pthread_np.h', 'sys/inotify.h'] ++ 'cet.h', 'pthread_np.h', 'poll.h', 'sys/inotify.h'] if cc.check_header(h) pre_args += '-DHAVE_@0@'.format(h.to_upper().underscorify()) endif diff --git a/packages/mesa/build.sh b/packages/mesa/build.sh index 94ee2bcea22..cc76d1dddf5 100644 --- a/packages/mesa/build.sh +++ b/packages/mesa/build.sh @@ -3,10 +3,10 @@ TERMUX_PKG_DESCRIPTION="An open-source implementation of the OpenGL specificatio TERMUX_PKG_LICENSE="MIT" TERMUX_PKG_LICENSE_FILE="docs/license.rst" TERMUX_PKG_MAINTAINER="@termux" -TERMUX_PKG_VERSION="26.0.0" -TERMUX_PKG_SRCURL=git+https://gitlab.freedesktop.org/robclark/mesa.git -TERMUX_PKG_GIT_BRANCH=tu/gen8 -_COMMIT=81075945d6c2dda77c6609180f3fcb6fd80372ab +TERMUX_PKG_VERSION="26.1.0" +TERMUX_PKG_SRCURL=git+https://gitlab.freedesktop.org/mesa/mesa.git +TERMUX_PKG_GIT_BRANCH=main +_COMMIT=6ea4fe9806b93ee9c4f0dd1b571e4a4a52c666ca TERMUX_PKG_AUTO_UPDATE=true TERMUX_PKG_DEPENDS="libandroid-shmem, libc++, libdrm, libglvnd, libllvm (<< $TERMUX_LLVM_NEXT_MAJOR_VERSION), libwayland, libx11, libxext, libxfixes, libxshmfence, libxxf86vm, ncurses, vulkan-loader, zlib, zstd" TERMUX_PKG_SUGGESTS="mesa-dev" From 95ed155c5f38a52ce719c69e62ac99d9ed6c897b Mon Sep 17 00:00:00 2001 From: lfdevs <109842948+lfdevs@users.noreply.github.com> Date: Tue, 3 Feb 2026 18:06:11 +0800 Subject: [PATCH 5/6] enhance(main/mesa): tu/kgsl: Add UBWC_5 and UBWC_6 support This patch is from Rob Clark: https://gitlab.freedesktop.org/mesa/mesa/-/commit/2da45c609845854491c09bd26d9d8245834ea4af?merge_request_iid=39358 Co-authored-by: Rob Clark --- .../mesa/0020-UBWC_5-and-UBWC_6-support.patch | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 packages/mesa/0020-UBWC_5-and-UBWC_6-support.patch diff --git a/packages/mesa/0020-UBWC_5-and-UBWC_6-support.patch b/packages/mesa/0020-UBWC_5-and-UBWC_6-support.patch new file mode 100644 index 00000000000..487f6bf0219 --- /dev/null +++ b/packages/mesa/0020-UBWC_5-and-UBWC_6-support.patch @@ -0,0 +1,24 @@ +From 2da45c609845854491c09bd26d9d8245834ea4af Mon Sep 17 00:00:00 2001 +From: Rob Clark +Date: Tue, 13 Jan 2026 10:58:51 -0800 +Subject: [PATCH] WIP: tu/kgsl: Add UBWC_5 and UBWC_6 support + +The #defines seem to map 1:1, so we can add support even without an +updated kgsl uabi header. +--- + src/freedreno/vulkan/tu_knl_kgsl.cc | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/freedreno/vulkan/tu_knl_kgsl.cc b/src/freedreno/vulkan/tu_knl_kgsl.cc +index e3a49692e941..48a0f8802e1a 100644 +--- a/src/freedreno/vulkan/tu_knl_kgsl.cc ++++ b/src/freedreno/vulkan/tu_knl_kgsl.cc +@@ -1842,6 +1842,8 @@ tu_knl_kgsl_load(struct tu_instance *instance, int fd) + device->ubwc_config.macrotile_mode = FDL_MACROTILE_4_CHANNEL; + break; + case KGSL_UBWC_4_0: ++ case 5: ++ case 6: + device->ubwc_config.bank_swizzle_levels = 0x6; + device->ubwc_config.macrotile_mode = FDL_MACROTILE_8_CHANNEL; + break; From 4f6d6f652c3db086e23370e092552f22a9dd5647 Mon Sep 17 00:00:00 2001 From: lfdevs <109842948+lfdevs@users.noreply.github.com> Date: Wed, 11 Feb 2026 21:22:44 +0800 Subject: [PATCH 6/6] enhance(main/mesa): Add unofficial support for Adreno 810/825/829 The source code is from whitebelyash: https://github.com/whitebelyash/mesa-tu8/commit/67514c8b1d938168f199494b8f6852f07d74c039 https://github.com/whitebelyash/mesa-tu8/commit/5295a445d06ad616b614dda3f8a129e1a56605f8 https://github.com/whitebelyash/mesa-tu8/commit/c9e8f035d2ccddad7bfdfc9c165954fbcad0b5dd --- ...nofficial-support-adreno-810-825-829.patch | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 packages/mesa/0021-unofficial-support-adreno-810-825-829.patch diff --git a/packages/mesa/0021-unofficial-support-adreno-810-825-829.patch b/packages/mesa/0021-unofficial-support-adreno-810-825-829.patch new file mode 100644 index 00000000000..e64cc4a0ab7 --- /dev/null +++ b/packages/mesa/0021-unofficial-support-adreno-810-825-829.patch @@ -0,0 +1,147 @@ +freedreno: enable Adreno 810/825/829 + +The source code is from whitebelyash: +https://github.com/whitebelyash/mesa-tu8/commit/67514c8b1d938168f199494b8f6852f07d74c039 +https://github.com/whitebelyash/mesa-tu8/commit/5295a445d06ad616b614dda3f8a129e1a56605f8 +https://github.com/whitebelyash/mesa-tu8/commit/c9e8f035d2ccddad7bfdfc9c165954fbcad0b5dd + +diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py +index 5cbd5d11504..ebeaab440a4 100644 +--- a/src/freedreno/common/freedreno_devices.py ++++ b/src/freedreno/common/freedreno_devices.py +@@ -1505,6 +1505,62 @@ a8xx_gen2 = GPUProps( + has_salu_int_narrowing_quirk = True + ) + ++a8xx_825 = GPUProps( ++ sysmem_vpc_attr_buf_size = 131072, ++ sysmem_vpc_pos_buf_size = 65536, ++ sysmem_vpc_bv_pos_buf_size = 32768, ++ sysmem_ccu_color_cache_fraction = CCUColorCacheFraction.FULL.value, ++ sysmem_per_ccu_color_cache_size = 128 * 1024, ++ sysmem_ccu_depth_cache_fraction = CCUColorCacheFraction.THREE_QUARTER.value, ++ sysmem_per_ccu_depth_cache_size = 96 * 1024, # TODO: check if 128 works too ++ gmem_vpc_attr_buf_size = 49152, ++ gmem_vpc_pos_buf_size = 24576, ++ gmem_vpc_bv_pos_buf_size = 32768, ++ gmem_ccu_color_cache_fraction = CCUColorCacheFraction.EIGHTH.value, ++ gmem_per_ccu_color_cache_size = 16 * 1024, ++ gmem_ccu_depth_cache_fraction = CCUColorCacheFraction.FULL.value, ++ gmem_per_ccu_depth_cache_size = 127 * 1024, ++) ++ ++a8xx_810 = GPUProps( ++ sysmem_vpc_attr_buf_size = 131072, ++ sysmem_vpc_pos_buf_size = 65536, ++ sysmem_vpc_bv_pos_buf_size = 32768, ++ # These values are maximum size of depth/color cache for current A8XX Gen2 sysmem configuration ++ # Bigger values cause an integer underflow in freedreno gmem calculations ++ sysmem_ccu_color_cache_fraction = CCUColorCacheFraction.FULL.value, ++ sysmem_per_ccu_color_cache_size = 32 * 1024, ++ sysmem_ccu_depth_cache_fraction = CCUColorCacheFraction.THREE_QUARTER.value, ++ sysmem_per_ccu_depth_cache_size = 32 * 1024, ++ gmem_vpc_attr_buf_size = 49152, ++ gmem_vpc_pos_buf_size = 24576, ++ gmem_vpc_bv_pos_buf_size = 32768, ++ gmem_ccu_color_cache_fraction = CCUColorCacheFraction.EIGHTH.value, ++ gmem_per_ccu_color_cache_size = 16 * 1024, ++ gmem_ccu_depth_cache_fraction = CCUColorCacheFraction.FULL.value, ++ gmem_per_ccu_depth_cache_size = 64 * 1024, ++ # FD810 does not support ray tracing ++ has_ray_intersection = False, ++ has_sw_fuse = False, ++) ++ ++a8xx_829 = GPUProps( ++ sysmem_vpc_attr_buf_size = 131072, ++ sysmem_vpc_pos_buf_size = 65536, ++ sysmem_vpc_bv_pos_buf_size = 32768, ++ sysmem_ccu_color_cache_fraction = CCUColorCacheFraction.FULL.value, ++ sysmem_per_ccu_color_cache_size = 128 * 1024, ++ sysmem_ccu_depth_cache_fraction = CCUColorCacheFraction.THREE_QUARTER.value, ++ sysmem_per_ccu_depth_cache_size = 96 * 1024, ++ gmem_vpc_attr_buf_size = 49152, ++ gmem_vpc_pos_buf_size = 24576, ++ gmem_vpc_bv_pos_buf_size = 32768, ++ gmem_ccu_color_cache_fraction = CCUColorCacheFraction.EIGHTH.value, ++ gmem_per_ccu_color_cache_size = 16 * 1024, ++ gmem_ccu_depth_cache_fraction = CCUColorCacheFraction.FULL.value, ++ gmem_per_ccu_depth_cache_size = 127 * 1024, ++) ++ + # For a8xx, the chicken bit and most other non-ctx reg + # programming moves into the kernel, and what remains + # should be easier to share between devices +@@ -1563,6 +1619,72 @@ add_gpus([ + raw_magic_regs = a8xx_gen2_raw_magic_regs, + )) + ++# gen8_6_0 ++add_gpus([ ++ GPUId(chip_id=0x44030000, name="FD825"), ++ ], A6xxGPUInfo( ++ CHIP.A8XX, ++ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_825], ++ num_ccu = 4, ++ num_slices = 2, ++ tile_align_w = 64, ++ tile_align_h = 32, ++ tile_max_w = 16384, ++ tile_max_h = 16384, ++ num_vsc_pipes = 32, ++ cs_shared_mem_size = 32 * 1024, ++ wave_granularity = 2, ++ fibers_per_sp = 128 * 2 * 16, ++ magic_regs = dict( ++ ), ++ raw_magic_regs = a8xx_gen2_raw_magic_regs, ++ )) ++ ++# gen8_3_0 ++add_gpus([ ++ GPUId(chip_id=0x44010000, name="FD810"), ++ ], A6xxGPUInfo( ++ CHIP.A8XX, ++ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_810], ++ num_ccu = 2, ++ num_slices = 1, ++ tile_align_w = 64, ++ tile_align_h = 32, ++ tile_max_w = 16384, ++ tile_max_h = 16384, ++ num_vsc_pipes = 32, ++ cs_shared_mem_size = 32 * 1024, ++ wave_granularity = 2, ++ fibers_per_sp = 128 * 2 * 16, ++ magic_regs = dict( ++ ), ++ raw_magic_regs = a8xx_gen2_raw_magic_regs, ++ )) ++ ++# TODO: Properly fill all values for this GPU ++# Very weird GPU, ugh.. ++add_gpus([ ++ GPUId(chip_id=0x44030A00, name="FD829"), # kgsl id??? ++ GPUId(chip_id=0x44030A20, name="FD829"), # found by testing ++ GPUId(chip_id=0xffff44030A00, name="FD829"), ++ ], A6xxGPUInfo( ++ CHIP.A8XX, ++ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_829,], ++ num_ccu = 4, ++ num_slices = 2, ++ tile_align_w = 64, ++ tile_align_h = 32, ++ tile_max_w = 16384, ++ tile_max_h = 16384, ++ num_vsc_pipes = 32, ++ cs_shared_mem_size = 32 * 1024, ++ wave_granularity = 2, ++ fibers_per_sp = 128 * 2 * 16, ++ magic_regs = dict( ++ ), ++ raw_magic_regs = a8xx_gen2_raw_magic_regs, ++ )) ++ + add_gpus([ + GPUId(chip_id=0xffff44050A31, name="Adreno (TM) 840"), + ], A6xxGPUInfo(