diff --git a/board/edu-unt/inc/board.h b/board/edu-unt/inc/board.h new file mode 100644 index 0000000..372c565 --- /dev/null +++ b/board/edu-unt/inc/board.h @@ -0,0 +1,86 @@ +/************************************************************************************************ +Copyright (c) 2022-2024, Laboratorio de Microprocesadores +Facultad de Ciencias Exactas y Tecnología, Universidad Nacional de Tucumán +https://www.microprocesadores.unt.edu.ar/ + +Copyright (c) 2022-2024, Esteban Volentini + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and +associated documentation files (the "Software"), to deal in the Software without restriction, +including without limitation the rights to use, copy, modify, merge, publish, distribute, +sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES +OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +*************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/** \brief Longan NANO board declarations + ** + ** \addtogroup board Board support + ** \brief Board agnostic configuration module + ** @{ */ + +/* === Headers files inclusions ================================================================ */ + +#if defined(USE_HAL) +#include "hal.h" +#endif +#if defined(USE_DRIVERS) +#include "gd32vf103.h" +#endif + +/* === Cabecera C++ ============================================================================ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* === Public macros definitions =============================================================== */ + +#if defined(USE_HAL) + +#elif defined(USE_DRIVERS) + +// #define LED_R_GPIO GPIOA +// #define LED_R_PIN GPIO_PIN_0 + +// #define LED_G_GPIO GPIOA +// #define LED_G_PIN GPIO_PIN_1 + +// #define LED_B_GPIO GPIOA +// #define LED_B_PIN GPIO_PIN_2 + +#endif + +/* === Public data type declarations =========================================================== */ + +/* === Public variable declarations ============================================================ */ + +/* === Public function declarations ============================================================ */ + +/** + * @brief Function to initilize board configuration + */ +void BoardSetup(void); + +/* === End of documentation ==================================================================== */ + +#ifdef __cplusplus +} +#endif + +/** @} End of module definition for doxygen */ + +#endif /* BOARD_H */ diff --git a/board/edu-unt/makefile b/board/edu-unt/makefile new file mode 100644 index 0000000..0ac472d --- /dev/null +++ b/board/edu-unt/makefile @@ -0,0 +1,28 @@ +################################################################################################## +# Copyright (c) 2022-2024, Laboratorio de Microprocesadores +# Facultad de Ciencias Exactas y Tecnología, Universidad Nacional de Tucumán +# https://www.microprocesadores.unt.edu.ar/ +# +# Copyright (c) 2022-2024, Esteban Volentini +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and +# associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or substantial +# portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES +# OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +################################################################################################## + +MCU ?= gd32vf103cbt6 + +USE_DRIVERS ?= y diff --git a/board/edu-unt/src/board.c b/board/edu-unt/src/board.c new file mode 100644 index 0000000..daf18e2 --- /dev/null +++ b/board/edu-unt/src/board.c @@ -0,0 +1,63 @@ +/************************************************************************************************ +Copyright (c) 2022-2024, Laboratorio de Microprocesadores +Facultad de Ciencias Exactas y Tecnología, Universidad Nacional de Tucumán +https://www.microprocesadores.unt.edu.ar/ + +Copyright (c) 2022-2024, Esteban Volentini + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and +associated documentation files (the "Software"), to deal in the Software without restriction, +including without limitation the rights to use, copy, modify, merge, publish, distribute, +sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES +OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +*************************************************************************************************/ + +/** \brief Longan NANO board configuration implementation + ** + ** \addtogroup board Board support + ** \brief Board agnostic configuration module + ** @{ */ + +/* === Headers files inclusions =============================================================== */ + +#include "board.h" +#include "gd32vf103.h" + +/* === Macros definitions ====================================================================== */ + +/* === Private data type declarations ========================================================== */ + +/* === Private variable declarations =========================================================== */ + +/* === Private function declarations =========================================================== */ + +/* === Public variable definitions ============================================================= */ + +/* === Private variable definitions ============================================================ */ + +/* === Private function implementation ========================================================= */ + +/* === Public function implementation ========================================================== */ + +void BoardSetup(void) { +#ifdef USE_DRIVERS + SystemInit(); + SystemCoreClockUpdate(); +#endif +} + +/* === End of documentation ==================================================================== + */ + +/** @} End of module definition for doxygen */ diff --git a/external/base/arch/rv32/core/src/write.c b/external/base/arch/rv32/core/src/write.c index 79dfe53..f2539b1 100644 --- a/external/base/arch/rv32/core/src/write.c +++ b/external/base/arch/rv32/core/src/write.c @@ -20,26 +20,22 @@ extern int _put_char(int ch) __attribute__((weak)); size_t __write(int handle, const unsigned char *buf, size_t bufSize) { size_t nChars = 0; - if (handle == -1) { return 0; } - for (; bufSize > 0; --bufSize) { _put_char((uint8_t) *buf); ++buf; ++nChars; } - return nChars; } int puts(const char* string) { return __write(0, (const void *) string, strlen(string)); } - #elif defined ( __GNUC__ ) ssize_t _write(int fd, const void* ptr, size_t len) { const uint8_t * current = (const uint8_t *) ptr; diff --git a/external/base/mcu/gd32f103c8/linker/release.ld b/external/base/mcu/gd32f103c8/linker/release.ld index 6997702..b65db90 100644 --- a/external/base/mcu/gd32f103c8/linker/release.ld +++ b/external/base/mcu/gd32f103c8/linker/release.ld @@ -10,7 +10,11 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Specify the memory areas */ MEMORY { +<<<<<<< HEAD RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +======= + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +>>>>>>> origin/main FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K } @@ -83,7 +87,11 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ +<<<<<<< HEAD + .data : +======= .data : +>>>>>>> origin/main { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -94,7 +102,11 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* Uninitialized data section */ . = ALIGN(4); .bss : @@ -122,7 +134,11 @@ SECTIONS . = ALIGN(8); } >RAM +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/external/base/mcu/gd32f103c8/startup/startup_gd32f10x_md.s b/external/base/mcu/gd32f103c8/startup/startup_gd32f10x_md.s index 5f1f662..2c8ebea 100644 --- a/external/base/mcu/gd32f103c8/startup/startup_gd32f10x_md.s +++ b/external/base/mcu/gd32f103c8/startup/startup_gd32f10x_md.s @@ -2,7 +2,6 @@ .cpu cortex-m3 .fpu softvfp .thumb - .global g_pfnVectors .global Default_Handler @@ -32,7 +31,6 @@ CopyDataInit: ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 - LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata @@ -46,7 +44,6 @@ FillZerobss: movs r3, #0 str r3, [r2] adds r2, r2, #4 - LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 @@ -316,3 +313,7 @@ g_pfnVectors: .weak EXMC_IRQHandler .thumb_set EXMC_IRQHandler,Default_Handler +<<<<<<< HEAD + +======= +>>>>>>> origin/main diff --git a/external/base/soc/gd32f10x/device/inc/gd32f10x.h b/external/base/soc/gd32f10x/device/inc/gd32f10x.h index 4e64c8a..b79f29e 100644 --- a/external/base/soc/gd32f10x/device/inc/gd32f10x.h +++ b/external/base/soc/gd32f10x/device/inc/gd32f10x.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -40,25 +64,44 @@ OF SUCH DAMAGE. #ifdef cplusplus extern "C" { +<<<<<<< HEAD +#endif +======= #endif +>>>>>>> origin/main /* define GD32F10x */ #if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) /* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */ +<<<<<<< HEAD /* #define GD32F10X_HD */ /*!< GD32F10X_HD: GD32 High density Value Line devices */ /* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */ /* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */ #endif /* define GD32F10x */ +======= + /* #define GD32F10X_HD */ /*!< GD32F10X_HD: GD32 High density Value Line devices */ + /* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */ + /* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */ +#endif /* define GD32F10x */ + +>>>>>>> origin/main #if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) #error "Please select the target GD32F10x device in gd32f10x.h file" #endif /* undefine GD32F10x tip */ /* define value of high speed crystal oscillator (HXTAL) in Hz */ +<<<<<<< HEAD +#if !defined HXTAL_VALUE +#ifdef GD32F10X_CL +#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ +#else +======= #if !defined HXTAL_VALUE #ifdef GD32F10X_CL #define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ #else +>>>>>>> origin/main #define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ #endif /* HXTAL_VALUE */ #endif /* high speed crystal oscillator value */ @@ -69,7 +112,11 @@ OF SUCH DAMAGE. #endif /* high speed crystal oscillator startup timeout */ /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +<<<<<<< HEAD #if !defined (IRC8M_VALUE) +======= +#if !defined (IRC8M_VALUE) +>>>>>>> origin/main #define IRC8M_VALUE ((uint32_t)8000000) #endif /* internal 8MHz RC oscillator value */ @@ -79,12 +126,20 @@ OF SUCH DAMAGE. #endif /* internal 8MHz RC oscillator startup timeout */ /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +<<<<<<< HEAD +#if !defined (IRC40K_VALUE) +======= #if !defined (IRC40K_VALUE) +>>>>>>> origin/main #define IRC40K_VALUE ((uint32_t)40000) #endif /* internal 40KHz RC oscillator value */ /* define value of low speed crystal oscillator (LXTAL)in Hz */ +<<<<<<< HEAD #if !defined (LXTAL_VALUE) +======= +#if !defined (LXTAL_VALUE) +>>>>>>> origin/main #define LXTAL_VALUE ((uint32_t)32768) #endif /* low speed crystal oscillator value */ @@ -92,7 +147,11 @@ OF SUCH DAMAGE. #define __GD32F10x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __GD32F10x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __GD32F10x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +<<<<<<< HEAD +#define __GD32F10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +======= #define __GD32F10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +>>>>>>> origin/main #define __GD32F10x_STDPERIPH_VERSION ((__GD32F10x_STDPERIPH_VERSION_MAIN << 24)\ |(__GD32F10x_STDPERIPH_VERSION_SUB1 << 16)\ |(__GD32F10x_STDPERIPH_VERSION_SUB2 << 8)\ @@ -320,7 +379,11 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +<<<<<<< HEAD #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +======= +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +>>>>>>> origin/main #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) /* main flash and SRAM memory map */ @@ -394,4 +457,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #ifdef cplusplus } #endif +<<<<<<< HEAD +#endif +======= #endif +>>>>>>> origin/main diff --git a/external/base/soc/gd32f10x/device/inc/system_gd32f10x.h b/external/base/soc/gd32f10x/device/inc/system_gd32f10x.h index 5bd6b79..f86405f 100644 --- a/external/base/soc/gd32f10x/device/inc/system_gd32f10x.h +++ b/external/base/soc/gd32f10x/device/inc/system_gd32f10x.h @@ -9,6 +9,7 @@ All rights reserved. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -30,6 +31,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/device/src/system_gd32f10x.c b/external/base/soc/gd32f10x/device/src/system_gd32f10x.c index 22529a8..f42ee8e 100644 --- a/external/base/soc/gd32f10x/device/src/system_gd32f10x.c +++ b/external/base/soc/gd32f10x/device/src/system_gd32f10x.c @@ -9,6 +9,7 @@ All rights reserved. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -30,6 +31,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -179,7 +203,11 @@ void SystemInit(void) RCU_CTL &= ~(RCU_CTL_HXTALBPS); /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ +<<<<<<< HEAD + +======= +>>>>>>> origin/main #ifdef GD32F10X_CL RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); @@ -204,7 +232,11 @@ void SystemInit(void) /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ system_clock_config(); +<<<<<<< HEAD +======= + +>>>>>>> origin/main #ifdef VECT_TAB_SRAM nvic_vector_table_set(NVIC_VECTTAB_RAM, VECT_TAB_OFFSET); #else @@ -223,33 +255,56 @@ static void system_clock_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; +<<<<<<< HEAD + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + +======= /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; +>>>>>>> origin/main /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ while(1){ } } +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB/1 */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; +<<<<<<< HEAD /* select HXTAL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; +======= + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + +>>>>>>> origin/main /* wait until HXTAL is selected as system clock */ while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)){ } @@ -604,11 +659,19 @@ static void system_clock_72m_hxtal(void) RCU_CFG0 |= RCU_PLL_MUL18; #elif defined(GD32F10X_CL) +<<<<<<< HEAD /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ +======= + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ +>>>>>>> origin/main RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); @@ -756,11 +819,19 @@ static void system_clock_108m_hxtal(void) RCU_CFG0 |= RCU_PLL_MUL27; #elif defined(GD32F10X_CL) +<<<<<<< HEAD + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ +======= /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ +>>>>>>> origin/main RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); @@ -798,7 +869,11 @@ static void system_clock_48m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; @@ -854,7 +929,11 @@ static void system_clock_72m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; @@ -910,7 +989,11 @@ static void system_clock_108m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; @@ -980,12 +1063,20 @@ void SystemCoreClockUpdate(void) case SEL_IRC8M: SystemCoreClock = IRC8M_VALUE; break; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* HXTAL is selected as CK_SYS */ case SEL_HXTAL: SystemCoreClock = HXTAL_VALUE; break; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* PLL is selected as CK_SYS */ case SEL_PLL: /* PLL clock source selection, HXTAL or IRC8M/2 */ @@ -997,7 +1088,11 @@ void SystemCoreClockUpdate(void) }else{ /* PLL clock source is HXTAL */ ck_src = HXTAL_VALUE; +<<<<<<< HEAD + +======= +>>>>>>> origin/main #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_adc.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_adc.h index bbc5630..4d26965 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_adc.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_adc.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_bkp.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_bkp.h index 555930b..0c04b5c 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_bkp.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_bkp.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -113,7 +137,11 @@ OF SUCH DAMAGE. /* constants definitions */ /* BKP data register number */ +<<<<<<< HEAD +typedef enum +======= typedef enum +>>>>>>> origin/main { BKP_DATA_0 = 1, /*!< BKP data register 0 */ BKP_DATA_1, /*!< BKP data register 1 */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_can.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_can.h index e4a9a27..4d9894a 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_can.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_can.h @@ -1,7 +1,11 @@ /*! \file gd32f10x_can.h \brief definitions for the CAN +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -13,6 +17,29 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -34,6 +61,7 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -333,6 +361,46 @@ OF SUCH DAMAGE. typedef enum { /* flags in STAT register */ +<<<<<<< HEAD + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ + /* flags in TSTAT register */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +======= CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ @@ -371,15 +439,22 @@ typedef enum CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +>>>>>>> origin/main }can_flag_enum; /* CAN interrupt flags */ typedef enum { /* interrupt flags in STAT register */ +<<<<<<< HEAD CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ +======= + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ +>>>>>>> origin/main /* interrupt flags in TSTAT register */ CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ @@ -393,16 +468,27 @@ typedef enum CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ /* interrupt flags in ERR register */ +<<<<<<< HEAD + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ +======= CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ +>>>>>>> origin/main }can_interrupt_flag_enum; /* CAN initiliaze parameters structure */ typedef struct { +<<<<<<< HEAD + uint8_t working_mode; /*!< CAN working mode */ +======= uint8_t working_mode; /*!< CAN working mode */ +>>>>>>> origin/main uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ uint8_t time_segment_1; /*!< time segment 1 */ uint8_t time_segment_2; /*!< time segment 2 */ @@ -521,6 +607,21 @@ typedef enum /* transmit data byte 2 */ #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) +<<<<<<< HEAD +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +======= /* transmit data byte 3 */ #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) @@ -534,6 +635,7 @@ typedef enum #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /* transmit data byte 7 */ +>>>>>>> origin/main #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) /* receive mailbox extended identifier*/ @@ -572,6 +674,15 @@ typedef enum /* receive data byte 7 */ #define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) +<<<<<<< HEAD +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive error count */ +======= /* error number */ #define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) @@ -579,6 +690,7 @@ typedef enum #define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) /* receive error count */ +>>>>>>> origin/main #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* CAN errors */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_crc.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_crc.h index 7dc5527..2b63ecb 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_crc.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_crc.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dac.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dac.h index fe059f1..b2d246a 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dac.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dac.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -69,7 +93,11 @@ OF SUCH DAMAGE. #define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ #define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +<<<<<<< HEAD #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +======= +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +>>>>>>> origin/main #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ #define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ @@ -198,7 +226,11 @@ void dac_disable(uint32_t dac_periph); /* enable DAC DMA */ void dac_dma_enable(uint32_t dac_periph); /* disable DAC DMA */ +<<<<<<< HEAD +void dac_dma_disable(uint32_t dac_periph); +======= void dac_dma_disable(uint32_t dac_periph); +>>>>>>> origin/main /* enable DAC output buffer */ void dac_output_buffer_enable(uint32_t dac_periph); /* disable DAC output buffer */ @@ -244,6 +276,10 @@ void dac_concurrent_output_buffer_enable(void); /* disable DAC concurrent buffer function */ void dac_concurrent_output_buffer_disable(void); /* set DAC concurrent mode data holding register value */ +<<<<<<< HEAD +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +======= void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +>>>>>>> origin/main #endif /* GD32F10X_DAC_H */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dbg.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dbg.h index e1f9715..d558a0b 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dbg.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dbg.h @@ -12,6 +12,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,6 +34,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dma.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dma.h index 6b73c16..bf4361c 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dma.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_dma.h @@ -12,6 +12,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,6 +34,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -122,6 +146,16 @@ OF SUCH DAMAGE. /* constants definitions */ /* DMA channel select */ +<<<<<<< HEAD +typedef enum +{ + DMA_CH0 = 0, /*!< DMA channel 0 */ + DMA_CH1, /*!< DMA channel 1 */ + DMA_CH2, /*!< DMA channel 2 */ + DMA_CH3, /*!< DMA channel 3 */ + DMA_CH4, /*!< DMA channel 4 */ + DMA_CH5, /*!< DMA channel 5 */ +======= typedef enum { DMA_CH0 = 0, /*!< DMA channel 0 */ @@ -130,6 +164,7 @@ typedef enum DMA_CH3, /*!< DMA channel 3 */ DMA_CH4, /*!< DMA channel 4 */ DMA_CH5, /*!< DMA channel 5 */ +>>>>>>> origin/main DMA_CH6 /*!< DMA channel 6 */ } dma_channel_enum; diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_exmc.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_exmc.h index 4177f70..c03ba1c 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_exmc.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_exmc.h @@ -1,7 +1,11 @@ /*! \file gd32f10x_exmc.h \brief definitions for the EXMC +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +37,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -185,7 +213,11 @@ typedef struct uint32_t databus_width; /*!< specifies the databus width of external memory */ uint32_t memory_type; /*!< specifies the type of external memory */ uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ +<<<<<<< HEAD exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing +======= + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing +>>>>>>> origin/main parameters for read if the extended mode is used */ exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ }exmc_norsram_parameter_struct; @@ -202,7 +234,11 @@ typedef struct /* EXMC NAND initialize struct */ typedef struct { +<<<<<<< HEAD + uint32_t nand_bank; /*!< select the bank of NAND */ +======= uint32_t nand_bank; /*!< select the bank of NAND */ +>>>>>>> origin/main uint32_t ecc_size; /*!< the page size for the ECC calculation */ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ @@ -220,7 +256,11 @@ typedef struct uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ uint32_t wait_feature; /*!< enables or disables the Wait feature */ exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ +<<<<<<< HEAD + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +======= exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +>>>>>>> origin/main exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ }exmc_pccard_parameter_struct;; diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fmc.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fmc.h index 20d4109..5371db0 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fmc.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fmc.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -206,7 +230,11 @@ typedef enum #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ +<<<<<<< HEAD +/* option bytes software/hardware free watch dog timer */ +======= /* option bytes software/hardware free watch dog timer */ +>>>>>>> origin/main #define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ #define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fwdgt.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fwdgt.h index 4e44da6..dae8a19 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fwdgt.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_fwdgt.h @@ -1,7 +1,11 @@ /*! \file gd32f10x_fwdgt.h \brief definitions for the FWDGT +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,29 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +59,7 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_gpio.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_gpio.h index 43a0c3b..84de192 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_gpio.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_gpio.h @@ -1,7 +1,11 @@ /*! \file gd32f10x_gpio.h \brief definitions for the GPIO +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +37,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -74,7 +102,11 @@ OF SUCH DAMAGE. /* bits definitions */ /* GPIO_CTL0 */ +<<<<<<< HEAD #define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +======= +#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +>>>>>>> origin/main #define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ #define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ #define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ @@ -92,7 +124,11 @@ OF SUCH DAMAGE. #define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ /* GPIO_CTL1 */ +<<<<<<< HEAD +#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +======= #define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +>>>>>>> origin/main #define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ #define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ #define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ @@ -244,7 +280,11 @@ OF SUCH DAMAGE. #define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ #define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ +<<<<<<< HEAD +#else +======= #else +>>>>>>> origin/main /* memory map and bit definitions for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices */ #define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_i2c.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_i2c.h index e9d3c8b..a7e0314 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_i2c.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_i2c.h @@ -1,7 +1,11 @@ /*! \file gd32f10x_i2c.h \brief definitions for the I2C +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -12,6 +16,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,6 +38,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -181,7 +209,11 @@ typedef enum I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ +<<<<<<< HEAD + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ +======= I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ +>>>>>>> origin/main I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_pmu.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_pmu.h index 12802ee..3f3ed7f 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_pmu.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_pmu.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rcu.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rcu.h index 86fdcd9..e43a8fb 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rcu.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rcu.h @@ -1,7 +1,11 @@ /*! \file gd32f10x_rcu.h \brief definitions for the RCU +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,29 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +59,7 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -390,7 +418,11 @@ typedef enum RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* APB1 peripherals */ RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ @@ -423,7 +455,11 @@ typedef enum RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* APB2 peripherals */ RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ @@ -465,7 +501,11 @@ typedef enum RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ #endif /* GD32F10X_CL */ +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* APB1 peripherals */ RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ @@ -497,7 +537,11 @@ typedef enum RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* APB2 peripherals */ RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rtc.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rtc.h index 6751748..01a9439 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rtc.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_rtc.h @@ -1,7 +1,11 @@ /*! \file gd32f10x_rtc.h \brief definitions for the RTC +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,29 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +59,7 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_sdio.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_sdio.h index 57b7a3c..348fefe 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_sdio.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_sdio.h @@ -1,6 +1,10 @@ /*! \file gd32f10x_sdio.h +<<<<<<< HEAD \brief definitions for the SDIO +======= + \brief definitions for the SDIO +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x @@ -11,6 +15,29 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +59,7 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_timer.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_timer.h index 9d85405..8d3b4f0 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_timer.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_timer.h @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -111,7 +135,11 @@ OF SUCH DAMAGE. #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* TIMER_DMAINTEN */ #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ #define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ @@ -249,7 +277,11 @@ OF SUCH DAMAGE. /* constants definitions */ /* TIMER init parameter struct definitions */ typedef struct +<<<<<<< HEAD { +======= +{ +>>>>>>> origin/main uint16_t prescaler; /*!< prescaler value */ uint16_t alignedmode; /*!< aligned mode */ uint16_t counterdirection; /*!< counter direction */ @@ -260,7 +292,11 @@ typedef struct /* break parameter struct definitions*/ typedef struct +<<<<<<< HEAD +{ +======= { +>>>>>>> origin/main uint16_t runoffstate; /*!< run mode off-state */ uint16_t ideloffstate; /*!< idle mode off-state */ uint16_t deadtime; /*!< dead time */ @@ -272,7 +308,11 @@ typedef struct /* channel output parameter struct definitions */ typedef struct +<<<<<<< HEAD { +======= +{ +>>>>>>> origin/main uint16_t outputstate; /*!< channel output state */ uint16_t outputnstate; /*!< channel complementary output state */ uint16_t ocpolarity; /*!< channel output polarity */ @@ -283,7 +323,11 @@ typedef struct /* channel input parameter struct definitions */ typedef struct +<<<<<<< HEAD +{ +======= { +>>>>>>> origin/main uint16_t icpolarity; /*!< channel input polarity */ uint16_t icselection; /*!< channel input mode selection */ uint16_t icprescaler; /*!< channel input capture prescaler */ @@ -308,7 +352,11 @@ typedef struct #define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ #define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ #define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ +<<<<<<< HEAD +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK +======= #define TIMER_INT_FLAG_BRK TIMER_INT_BRK +>>>>>>> origin/main /* TIMER flag */ #define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ @@ -332,7 +380,11 @@ typedef struct #define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ #define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ +<<<<<<< HEAD /* channel DMA request source selection */ +======= +/* channel DMA request source selection */ +>>>>>>> origin/main #define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ @@ -422,7 +474,11 @@ typedef struct #define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ +<<<<<<< HEAD +/* idle mode off-state configure */ +======= /* idle mode off-state configure */ +>>>>>>> origin/main #define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ @@ -467,11 +523,19 @@ typedef struct #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ +<<<<<<< HEAD /* idle state of channel output */ #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ /* idle state of channel complementary output */ +======= +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +>>>>>>> origin/main #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ @@ -497,7 +561,11 @@ typedef struct #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ +<<<<<<< HEAD /* channel control shadow register update control */ +======= +/* channel control shadow register update control */ +>>>>>>> origin/main #define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ #define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ @@ -539,7 +607,11 @@ typedef struct #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ /* slave mode control */ +<<<<<<< HEAD +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +======= #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +>>>>>>> origin/main #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ #define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */ #define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */ @@ -549,7 +621,11 @@ typedef struct #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ +<<<<<<< HEAD /* master slave mode selection */ +======= +/* master slave mode selection */ +>>>>>>> origin/main #define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ @@ -564,7 +640,11 @@ typedef struct #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ +<<<<<<< HEAD +/* channel 0 trigger input selection */ +======= /* channel 0 trigger input selection */ +>>>>>>> origin/main #define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ #define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ diff --git a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_usart.h b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_usart.h index 17d420e..cefce01 100644 --- a/external/base/soc/gd32f10x/drivers/inc/gd32f10x_usart.h +++ b/external/base/soc/gd32f10x/drivers/inc/gd32f10x_usart.h @@ -1,6 +1,10 @@ /*! \file gd32f10x_usart.h +<<<<<<< HEAD \brief definitions for the USART +======= + \brief definitions for the USART +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.1, firmware for GD32F10x @@ -11,6 +15,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +37,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -373,4 +401,8 @@ void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt); FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); /* clear interrupt flag in STAT register */ void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag); +<<<<<<< HEAD +#endif /* GD32F10X_USART_H */ +======= #endif /* GD32F10X_USART_H */ +>>>>>>> origin/main diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_adc.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_adc.c index 9754bc0..8d95f67 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_adc.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_adc.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -60,7 +84,11 @@ OF SUCH DAMAGE. #define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! +<<<<<<< HEAD \brief reset ADC +======= + \brief reset ADC +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[out] none \retval none @@ -134,11 +162,19 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ /* enable inserted channel group convert automatically */ ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; +<<<<<<< HEAD } if(0U != (function & ADC_CONTINUOUS_MODE)){ /* enable continuous mode */ ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; } +======= + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } +>>>>>>> origin/main }else{ if(0U != (function & ADC_SCAN_MODE)){ /* disable scan mode */ @@ -147,16 +183,28 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ /* disable inserted channel group convert automatically */ ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; +<<<<<<< HEAD } if(0U != (function & ADC_CONTINUOUS_MODE)){ /* disable continuous mode */ ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; } +======= + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } +>>>>>>> origin/main } } /*! +<<<<<<< HEAD \brief configure ADC data alignment +======= + \brief configure ADC data alignment +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] data_alignment: data alignment select only one parameter can be selected which is shown as below: @@ -187,7 +235,11 @@ void adc_enable(uint32_t adc_periph) if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ /* enable ADC */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; +<<<<<<< HEAD + } +======= } +>>>>>>> origin/main } /*! @@ -247,7 +299,11 @@ void adc_tempsensor_vrefint_disable(void) } /*! +<<<<<<< HEAD \brief enable DMA request +======= + \brief enable DMA request +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[out] none \retval none @@ -259,7 +315,11 @@ void adc_dma_mode_enable(uint32_t adc_periph) } /*! +<<<<<<< HEAD + \brief disable DMA request +======= \brief disable DMA request +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[out] none \retval none @@ -271,7 +331,11 @@ void adc_dma_mode_disable(uint32_t adc_periph) } /*! +<<<<<<< HEAD \brief configure ADC discontinuous mode +======= + \brief configure ADC discontinuous mode +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_channel_group: select the channel group only one parameter can be selected which is shown as below: @@ -338,12 +402,20 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u } /*! +<<<<<<< HEAD + \brief configure ADC regular channel +======= \brief configure ADC regular channel +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: +<<<<<<< HEAD \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx +======= + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx +>>>>>>> origin/main \param[in] sample_time: the sample time value only one parameter can be selected which is shown as below: \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles @@ -360,7 +432,11 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { uint32_t rsq,sampt; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* ADC regular sequence config */ if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ /* the regular group sequence rank is smaller than six */ @@ -385,7 +461,11 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c ADC_RSQ0(adc_periph) = rsq; }else{ } +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* ADC sampling time config */ if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ /* the regular group sequence rank is smaller than ten */ @@ -406,7 +486,11 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c } /*! +<<<<<<< HEAD + \brief configure ADC inserted channel +======= \brief configure ADC inserted channel +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 \param[in] adc_channel: the selected ADC channel @@ -437,7 +521,11 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_ isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); ADC_ISQ(adc_periph) = isq; +<<<<<<< HEAD /* ADC sampling time config */ +======= + /* ADC sampling time config */ +>>>>>>> origin/main if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ /* the inserted group sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); @@ -457,7 +545,11 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_ } /*! +<<<<<<< HEAD + \brief configure ADC inserted channel offset +======= \brief configure ADC inserted channel offset +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] inserted_channel: insert channel select only one parameter can be selected @@ -476,17 +568,29 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(num <= ADC_OFFSET_LENGTH){ /* calculate the offset of the register */ num = num * ADC_OFFSET_SHIFT_LENGTH; /* config the offset of the selected channels */ REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); +<<<<<<< HEAD } } /*! \brief configure ADC external trigger source +======= + } +} + +/*! + \brief configure ADC external trigger source +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_channel_group: select the channel group only one parameter can be selected which is shown as below: @@ -495,6 +599,7 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch \param[in] external_trigger_source: regular or inserted group trigger source only one parameter can be selected for regular channel: +<<<<<<< HEAD \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select @@ -528,11 +633,50 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select \arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger +======= + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select + \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 + \arg ADC2_EXTTRIG_REGULAR_T2_CH0: TIMER2 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select + \arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select + \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select + \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T3_CH2: TIMER3 CH2 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH1: TIMER7 CH1 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select + \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select + \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger +>>>>>>> origin/main \param[out] none \retval none */ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +<<<<<<< HEAD { +======= +{ +>>>>>>> origin/main switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: /* configure ADC regular group external trigger source */ @@ -550,7 +694,11 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel } /*! +<<<<<<< HEAD + \brief configure ADC external trigger +======= \brief configure ADC external trigger +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_channel_group: select the channel group one or more parameters can be selected which are shown as below: @@ -570,7 +718,11 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ /* enable ADC inserted channel group external trigger */ ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; +<<<<<<< HEAD } +======= + } +>>>>>>> origin/main }else{ if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ /* disable ADC regular channel group external trigger */ @@ -579,12 +731,20 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ /* disable ADC regular channel group external trigger */ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; +<<<<<<< HEAD + } +======= } +>>>>>>> origin/main } } /*! +<<<<<<< HEAD + \brief enable ADC software trigger +======= \brief enable ADC software trigger +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_channel_group: select the channel group one or more parameters can be selected which are shown as below: @@ -606,7 +766,11 @@ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) } /*! +<<<<<<< HEAD \brief read ADC regular group data register +======= + \brief read ADC regular group data register +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] none \param[out] none @@ -618,7 +782,11 @@ uint16_t adc_regular_data_read(uint32_t adc_periph) } /*! +<<<<<<< HEAD + \brief read ADC inserted group data register +======= \brief read ADC inserted group data register +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] inserted_channel: insert channel select only one parameter can be selected @@ -671,7 +839,11 @@ uint32_t adc_sync_mode_convert_value_read(void) /*! +<<<<<<< HEAD \brief configure ADC analog watchdog single channel +======= + \brief configure ADC analog watchdog single channel +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: @@ -688,10 +860,17 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel } /*! +<<<<<<< HEAD + \brief configure ADC analog watchdog group channel + \param[in] adc_periph: ADCx, x=0,1,2 + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: +======= \brief configure ADC analog watchdog group channel \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_channel_group: the channel group use analog watchdog only one parameter can be selected which is shown as below: +>>>>>>> origin/main \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group @@ -721,7 +900,11 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_ } /*! +<<<<<<< HEAD + \brief disable ADC analog watchdog +======= \brief disable ADC analog watchdog +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[out] none \retval none @@ -732,7 +915,11 @@ void adc_watchdog_disable(uint32_t adc_periph) } /*! +<<<<<<< HEAD \brief configure ADC analog watchdog threshold +======= + \brief configure ADC analog watchdog threshold +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] low_threshold: analog watchdog low threshold, 0..4095 \param[in] high_threshold: analog watchdog high threshold, 0..4095 @@ -878,7 +1065,11 @@ void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) } /*! +<<<<<<< HEAD + \brief enable ADC interrupt +======= \brief enable ADC interrupt +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_interrupt: the adc interrupt one or more parameters can be selected which are shown as below: @@ -893,6 +1084,7 @@ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) /* enable ADC analog watchdog interrupt */ if(0U != (adc_interrupt & ADC_INT_WDE)){ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; +<<<<<<< HEAD } /* enable ADC end of group conversion interrupt */ if(0U != (adc_interrupt & ADC_INT_EOC)){ @@ -900,12 +1092,25 @@ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) } /* enable ADC end of inserted group conversion interrupt */ if(0U != (adc_interrupt & ADC_INT_EOIC)){ +======= + } + /* enable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + } + /* enable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ +>>>>>>> origin/main ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; } } /*! +<<<<<<< HEAD \brief disable ADC interrupt +======= + \brief disable ADC interrupt +>>>>>>> origin/main \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_interrupt: the adc interrupt flag one or more parameters can be selected which are shown as below: @@ -916,6 +1121,19 @@ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) \retval none */ void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +<<<<<<< HEAD +{ + /* disable ADC analog watchdog interrupt */ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; + } + /* disable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; + } + /* disable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ +======= { /* disable ADC analog watchdog interrupt */ if(0U != (adc_interrupt & ADC_INT_WDE)){ @@ -927,6 +1145,7 @@ void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) } /* disable ADC end of inserted group conversion interrupt */ if(0U != (adc_interrupt & ADC_INT_EOIC)){ +>>>>>>> origin/main ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; } } diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_bkp.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_bkp.c index c681f0f..96a8b65 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_bkp.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_bkp.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -84,7 +108,11 @@ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) uint16_t bkp_data_read(bkp_data_register_enum register_number) { uint16_t data = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* get the data from the BKP data register */ if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ data = BKP_DATA10_41(register_number - 1U); @@ -152,7 +180,11 @@ void bkp_rtc_signal_output_disable(void) void bkp_rtc_output_select(uint16_t outputsel) { uint16_t ctl = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* configure BKP_OCTL_ROSEL with outputsel */ ctl = BKP_OCTL; ctl &= (uint16_t)~BKP_OCTL_ROSEL; @@ -161,7 +193,11 @@ void bkp_rtc_output_select(uint16_t outputsel) } /*! +<<<<<<< HEAD \brief set RTC clock calibration value +======= + \brief set RTC clock calibration value +>>>>>>> origin/main \param[in] value: RTC clock calibration value \arg 0x00 - 0x7F \param[out] none @@ -170,7 +206,11 @@ void bkp_rtc_output_select(uint16_t outputsel) void bkp_rtc_calibration_value_set(uint8_t value) { uint16_t ctl; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* configure BKP_OCTL_RCCV with value */ ctl = BKP_OCTL; ctl &= (uint16_t)~BKP_OCTL_RCCV; @@ -212,7 +252,11 @@ void bkp_tamper_detection_disable(void) void bkp_tamper_active_level_set(uint16_t level) { uint16_t ctl = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* configure BKP_TPCTL_TPAL with level */ ctl = BKP_TPCTL; ctl &= (uint16_t)~BKP_TPCTL_TPAL; diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_can.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_can.c index 1325f1b..c2180d2 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_can.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_can.c @@ -14,6 +14,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -35,12 +36,36 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ #include "gd32f10x_can.h" #define CAN_ERROR_HANDLE(s) do{}while(1) +<<<<<<< HEAD #define RFO1_CLEAR_VAL ((uint32_t)0x00000000U) /*!< RFO1 clear value */ #define RFF1_CLEAR_VAL ((uint32_t)0x00000018U) /*!< RFF1 clear value */ @@ -49,6 +74,16 @@ OF SUCH DAMAGE. \brief deinitialize CAN \param[in] can_periph \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + +#define RFO1_CLEAR_VAL ((uint32_t)0x00000000U) /*!< RFO1 clear value */ +#define RFF1_CLEAR_VAL ((uint32_t)0x00000018U) /*!< RFF1 clear value */ + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval none */ @@ -72,20 +107,32 @@ void can_deinit(uint32_t can_periph) /*! \brief initialize CAN parameter struct with a default value +<<<<<<< HEAD + \param[in] type: the type of CAN parameter struct +======= \param[in] type: the type of CAN parameter struct +>>>>>>> origin/main only one parameter can be selected which is shown as below: \arg CAN_INIT_STRUCT: the CAN initial struct \arg CAN_FILTER_STRUCT: the CAN filter struct \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct +<<<<<<< HEAD \param[in] p_struct: the pointer of the specific struct +======= + \param[in] p_struct: the pointer of the specific struct +>>>>>>> origin/main \param[out] none \retval none */ void can_struct_para_init(can_struct_type_enum type, void* p_struct) { uint8_t i; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* get type of the struct */ switch(type){ /* used for can_init() */ @@ -93,15 +140,24 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct) ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE; ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; +<<<<<<< HEAD + ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; +======= ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; +>>>>>>> origin/main ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; +<<<<<<< HEAD +======= + +>>>>>>> origin/main break; /* used for can_filter_init() */ case CAN_FILTER_STRUCT: @@ -121,27 +177,43 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct) for(i = 0U; i < 8U; i++){ ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; } +<<<<<<< HEAD + +======= +>>>>>>> origin/main ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; +<<<<<<< HEAD +======= + +>>>>>>> origin/main break; /* used for can_message_receive() */ case CAN_RX_MESSAGE_STRUCT: for(i = 0U; i < 8U; i++){ ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; } +<<<<<<< HEAD + +======= +>>>>>>> origin/main ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; ((can_receive_message_struct*)p_struct)->rx_efid = 0U; ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; ((can_receive_message_struct*)p_struct)->rx_fi = 0U; ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; +<<<<<<< HEAD +======= + +>>>>>>> origin/main break; default: @@ -152,7 +224,11 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct) /*! \brief initialize CAN \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] can_parameter_init: parameters for CAN initializtion \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) @@ -172,7 +248,11 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init { uint32_t timeout = CAN_TIMEOUT; ErrStatus flag = ERROR; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* disable sleep mode */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; /* enable initialize mode */ @@ -227,7 +307,11 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init CAN_CTL(can_periph) |= CAN_CTL_TFO; }else{ CAN_CTL(can_periph) &= ~CAN_CTL_TFO; +<<<<<<< HEAD + } +======= } +>>>>>>> origin/main /* disable initialize mode */ CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; timeout = CAN_TIMEOUT; @@ -239,21 +323,36 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init if(0U != timeout){ flag = SUCCESS; } +<<<<<<< HEAD } +======= + } +>>>>>>> origin/main return flag; } /*! +<<<<<<< HEAD + \brief initialize CAN filter +======= \brief initialize CAN filter +>>>>>>> origin/main \param[in] can_filter_parameter_init: struct for CAN filter initialization \arg filter_list_high: 0x0000 - 0xFFFF \arg filter_list_low: 0x0000 - 0xFFFF \arg filter_mask_high: 0x0000 - 0xFFFF \arg filter_mask_low: 0x0000 - 0xFFFF +<<<<<<< HEAD \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 \arg filter_number: 0 - 27 \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT +======= + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT +>>>>>>> origin/main \arg filter_enable: ENABLE or DISABLE \param[out] none \retval none @@ -261,13 +360,21 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) { uint32_t val = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); /* filter lock disable */ CAN_FCTL(CAN0) |= CAN_FCTL_FLD; /* disable filter */ CAN_FW(CAN0) &= ~(uint32_t)val; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* filter 16 bits */ if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ /* set filter 16 bits */ @@ -294,7 +401,11 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); } +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* filter mode */ if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ /* mask mode */ @@ -303,7 +414,11 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) /* list mode */ CAN_FMCFG(CAN0) |= (uint32_t)val; } +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* filter FIFO */ if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ /* FIFO0 */ @@ -312,6 +427,15 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) /* FIFO1 */ CAN_FAFIFO(CAN0) |= (uint32_t)val; } +<<<<<<< HEAD + + /* filter working */ + if(ENABLE == can_filter_parameter_init->filter_enable){ + + CAN_FW(CAN0) |= (uint32_t)val; + } + +======= /* filter working */ if(ENABLE == can_filter_parameter_init->filter_enable){ @@ -319,6 +443,7 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) CAN_FW(CAN0) |= (uint32_t)val; } +>>>>>>> origin/main /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } @@ -345,7 +470,11 @@ void can1_filter_start_bank(uint8_t start_bank) /*! \brief enable CAN debug freeze \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval none */ @@ -369,7 +498,11 @@ void can_debug_freeze_enable(uint32_t can_periph) /*! \brief disable CAN debug freeze \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval none */ @@ -393,14 +526,22 @@ void can_debug_freeze_disable(uint32_t can_periph) /*! \brief enable CAN time trigger mode \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval none */ void can_time_trigger_mode_enable(uint32_t can_periph) { uint8_t mailbox_number; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* enable the tcc mode */ CAN_CTL(can_periph) |= CAN_CTL_TTC; /* enable time stamp */ @@ -412,14 +553,23 @@ void can_time_trigger_mode_enable(uint32_t can_periph) /*! \brief disable CAN time trigger mode \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval none */ void can_time_trigger_mode_disable(uint32_t can_periph) { +<<<<<<< HEAD + uint8_t mailbox_number; + +======= uint8_t mailbox_number; +>>>>>>> origin/main /* disable the TCC mode */ CAN_CTL(can_periph) &= ~CAN_CTL_TTC; /* reset TSEN bits */ @@ -431,7 +581,11 @@ void can_time_trigger_mode_disable(uint32_t can_periph) /*! \brief transmit CAN message \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] transmit_message: struct for CAN transmit message \arg tx_sfid: 0x00000000 - 0x000007FF \arg tx_efid: 0x00000000 - 0x1FFFFFFF @@ -460,7 +614,11 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t if(CAN_NOMAILBOX == mailbox_number){ return CAN_NOMAILBOX; } +<<<<<<< HEAD +======= + +>>>>>>> origin/main CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; if(CAN_FF_STANDARD == transmit_message->tx_ff){ /* set transmit mailbox standard identifier */ @@ -491,9 +649,15 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t } /*! +<<<<<<< HEAD + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \brief get CAN transmit state \param[in] can_periph \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] mailbox_number only one parameter can be selected which is shown as below: \arg CAN_MAILBOX(x=0,1,2) @@ -504,8 +668,13 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox { can_transmit_state_enum state = CAN_TRANSMIT_FAILED; uint32_t val = 0U; +<<<<<<< HEAD /* check selected mailbox state */ +======= + + /* check selected mailbox state */ +>>>>>>> origin/main switch(mailbox_number){ /* mailbox0 */ case CAN_MAILBOX0: @@ -523,10 +692,17 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox val = CAN_TRANSMIT_FAILED; break; } +<<<<<<< HEAD + + switch(val){ + /* transmit pending */ + case (CAN_STATE_PENDING): +======= switch(val){ /* transmit pending */ case (CAN_STATE_PENDING): +>>>>>>> origin/main state = CAN_TRANSMIT_PENDING; break; /* mailbox0 transmit succeeded */ @@ -542,7 +718,11 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox state = CAN_TRANSMIT_OK; break; /* transmit failed */ +<<<<<<< HEAD + default: +======= default: +>>>>>>> origin/main state = CAN_TRANSMIT_FAILED; break; } @@ -552,7 +732,11 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox /*! \brief stop CAN transmission \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] mailbox_number only one parameter can be selected which is shown as below: \arg CAN_MAILBOXx(x=0,1,2) @@ -581,7 +765,11 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) /*! \brief CAN receive message \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] fifo_number \arg CAN_FIFOx(x=0,1) \param[out] receive_message: struct for CAN receive message @@ -605,14 +793,24 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m /* get extended identifier */ receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); } +<<<<<<< HEAD /* get frame type */ receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); +======= + + /* get frame type */ + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); +>>>>>>> origin/main /* filtering index */ receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); /* get recevie data length */ receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* receive data */ receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); @@ -622,7 +820,11 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* release FIFO */ if(CAN_FIFO0 == fifo_number){ CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; @@ -634,7 +836,11 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m /*! \brief release FIFO0 \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] fifo_number only one parameter can be selected which is shown as below: \arg CAN_FIFOx(x=0,1) @@ -656,17 +862,28 @@ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) /*! \brief CAN receive message length \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL \param[in] fifo_number only one parameter can be selected which is shown as below: \arg CAN_FIFOx(x=0,1) +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) +>>>>>>> origin/main \param[out] none \retval message length */ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) { uint8_t val = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(CAN_FIFO0 == fifo_number){ /* FIFO0 */ val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); @@ -682,7 +899,11 @@ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) /*! \brief set CAN working mode \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] can_working_mode only one parameter can be selected which is shown as below: \arg CAN_MODE_INITIALIZE @@ -695,8 +916,13 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) { ErrStatus flag = ERROR; /* timeout for IWS or also for SLPWS bits */ +<<<<<<< HEAD + uint32_t timeout = CAN_TIMEOUT; + +======= uint32_t timeout = CAN_TIMEOUT; +>>>>>>> origin/main if(CAN_MODE_INITIALIZE == working_mode){ /* disable sleep mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); @@ -746,7 +972,11 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) /*! \brief wake up CAN \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -754,10 +984,17 @@ ErrStatus can_wakeup(uint32_t can_periph) { ErrStatus flag = ERROR; uint32_t timeout = CAN_TIMEOUT; +<<<<<<< HEAD /* wakeup */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; +======= + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + +>>>>>>> origin/main while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ timeout--; } @@ -773,7 +1010,11 @@ ErrStatus can_wakeup(uint32_t can_periph) /*! \brief get CAN error type \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval can_error_enum \arg CAN_ERROR_NONE: no error @@ -789,7 +1030,11 @@ can_error_enum can_error_get(uint32_t can_periph) { can_error_enum error; error = CAN_ERROR_NONE; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* get error type */ error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); return error; @@ -798,14 +1043,22 @@ can_error_enum can_error_get(uint32_t can_periph) /*! \brief get CAN receive error number \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval error number */ uint8_t can_receive_error_number_get(uint32_t can_periph) { uint8_t val; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* get error count */ val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); return val; @@ -814,23 +1067,38 @@ uint8_t can_receive_error_number_get(uint32_t can_periph) /*! \brief get CAN transmit error number \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[out] none \retval error number */ uint8_t can_transmit_error_number_get(uint32_t can_periph) { uint8_t val; +<<<<<<< HEAD +======= + +>>>>>>> origin/main val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); return val; } /*! +<<<<<<< HEAD \brief enable CAN interrupt \param[in] can_periph \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL \param[in] interrupt +======= + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL + \param[in] interrupt +>>>>>>> origin/main one or more parameters can be selected which are shown as below: \arg CAN_INT_TME: transmit mailbox empty interrupt enable \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable @@ -855,9 +1123,15 @@ void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) } /*! +<<<<<<< HEAD + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \brief disable CAN interrupt \param[in] can_periph \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] interrupt one or more parameters can be selected which are shown as below: \arg CAN_INT_TME: transmit mailbox empty interrupt enable @@ -885,7 +1159,11 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) /*! \brief get CAN flag state \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] flag: CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below: \arg CAN_FLAG_RXL: RX level @@ -926,7 +1204,11 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \retval FlagStatus: SET or RESET */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +<<<<<<< HEAD { +======= +{ +>>>>>>> origin/main /* get flag and interrupt enable state */ if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ return SET; @@ -938,7 +1220,11 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) /*! \brief clear CAN flag state \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] flag: CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below: \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode @@ -977,7 +1263,11 @@ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) /*! \brief get CAN interrupt flag state \param[in] can_periph +<<<<<<< HEAD \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering @@ -1003,7 +1293,11 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f { uint32_t ret1 = RESET; uint32_t ret2 = RESET; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* get the staus of interrupt flag */ if (flag == CAN_INT_FLAG_RFL0) { ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); @@ -1026,7 +1320,11 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f /*! \brief clear CAN interrupt flag state \param[in] can_periph +<<<<<<< HEAD + \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +======= \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL +>>>>>>> origin/main \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_crc.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_crc.c index efe301c..0d375c8 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_crc.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_crc.c @@ -1,7 +1,11 @@ /*! \file gd32f10x_crc.c \brief CRC driver +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +37,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -65,7 +93,11 @@ void crc_data_register_reset(void) } /*! +<<<<<<< HEAD + \brief read the value of the data register +======= \brief read the value of the data register +>>>>>>> origin/main \param[in] none \param[out] none \retval 32-bit value of the data register diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_dac.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_dac.c index 744b931..2fce42f 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_dac.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_dac.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -68,7 +92,11 @@ void dac_enable(uint32_t dac_periph) }else{ DAC_CTL |= DAC_CTL_DEN1; } +<<<<<<< HEAD } +======= +} +>>>>>>> origin/main /*! \brief disable DAC @@ -479,7 +507,11 @@ void dac_concurrent_software_trigger_enable(void) { uint32_t swt = 0U; swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; +<<<<<<< HEAD + DAC_SWT |= (swt); +======= DAC_SWT |= (swt); +>>>>>>> origin/main } /*! diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_dbg.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_dbg.c index 749fc48..875aba5 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_dbg.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_dbg.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -135,10 +159,17 @@ void dbg_trace_pin_disable(void) } /*! +<<<<<<< HEAD + \brief trace pin mode selection + \param[in] trace_mode: + only one parameter can be selected which is shown as below: + \arg TRACE_MODE_ASYNC: trace pin used for async mode +======= \brief trace pin mode selection \param[in] trace_mode: only one parameter can be selected which is shown as below: \arg TRACE_MODE_ASYNC: trace pin used for async mode +>>>>>>> origin/main \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_dma.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_dma.c index 1df495b..39136f8 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_dma.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_dma.c @@ -12,6 +12,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,6 +34,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -44,7 +68,11 @@ OF SUCH DAMAGE. static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); /*! +<<<<<<< HEAD + \brief deinitialize DMA a channel registers +======= \brief deinitialize DMA a channel registers +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is deinitialized @@ -58,7 +86,11 @@ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* disable DMA a channel */ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; /* reset DMA channel registers */ @@ -79,7 +111,11 @@ void dma_struct_para_init(dma_parameter_struct* init_struct) { /* set the DMA struct with the default values */ init_struct->periph_addr = 0U; +<<<<<<< HEAD + init_struct->periph_width = 0U; +======= init_struct->periph_width = 0U; +>>>>>>> origin/main init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; init_struct->memory_addr = 0U; init_struct->memory_width = 0U; @@ -99,7 +135,11 @@ void dma_struct_para_init(dma_parameter_struct* init_struct) \param[in] init_struct: the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT +<<<<<<< HEAD periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE +======= + periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE +>>>>>>> origin/main memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE @@ -112,6 +152,7 @@ void dma_struct_para_init(dma_parameter_struct* init_struct) void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) { uint32_t ctl; +<<<<<<< HEAD if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE @@ -126,6 +167,22 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru /* configure the number of remaining data to be transferred */ DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); +======= + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + +>>>>>>> origin/main /* configure peripheral transfer width,memory transfer width, */ ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); @@ -145,24 +202,40 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru }else{ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* configure the direction of data transfer */ if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; }else{ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; +<<<<<<< HEAD } } /*! \brief enable DMA circulation mode +======= + } +} + +/*! + \brief enable DMA circulation mode +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none +<<<<<<< HEAD + \retval none +======= \retval none +>>>>>>> origin/main */ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) { @@ -174,6 +247,7 @@ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) } /*! +<<<<<<< HEAD \brief disable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) @@ -182,13 +256,27 @@ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none +======= + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +>>>>>>> origin/main */ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD +======= + +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } @@ -196,7 +284,11 @@ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) \brief enable memory to memory mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) +<<<<<<< HEAD + \param[in] channelx: specify which DMA channel +======= \param[in] channelx: specify which DMA channel +>>>>>>> origin/main only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none @@ -207,7 +299,11 @@ void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD +======= + +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; } @@ -226,50 +322,82 @@ void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; } /*! +<<<<<<< HEAD \brief enable DMA channel +======= + \brief enable DMA channel +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none +<<<<<<< HEAD + \retval none +======= \retval none +>>>>>>> origin/main */ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; } /*! +<<<<<<< HEAD \brief disable DMA channel +======= + \brief disable DMA channel +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none +<<<<<<< HEAD + \retval none +======= \retval none +>>>>>>> origin/main */ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD +======= + +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; } /*! +<<<<<<< HEAD + \brief set DMA peripheral base address +======= \brief set DMA peripheral base address +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set peripheral base address @@ -277,19 +405,31 @@ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] address: peripheral base address \param[out] none +<<<<<<< HEAD \retval none +======= + \retval none +>>>>>>> origin/main */ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHPADDR(dma_periph, channelx) = address; } /*! +<<<<<<< HEAD \brief set DMA memory base address +======= + \brief set DMA memory base address +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set memory base address @@ -297,19 +437,31 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] address: memory base address \param[out] none +<<<<<<< HEAD + \retval none +======= \retval none +>>>>>>> origin/main */ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD +======= + +>>>>>>> origin/main DMA_CHMADDR(dma_periph, channelx) = address; } /*! +<<<<<<< HEAD + \brief set the number of remaining data to be transferred by the DMA +======= \brief set the number of remaining data to be transferred by the DMA +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set number @@ -318,18 +470,36 @@ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, u \param[in] number: the number of remaining data to be transferred by the DMA \arg 0x0000-0xFFFF \param[out] none +<<<<<<< HEAD \retval none +======= + \retval none +>>>>>>> origin/main */ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); } /*! +<<<<<<< HEAD + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +======= \brief get the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) @@ -338,18 +508,27 @@ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval uint32_t: the number of remaining data to be transferred by the DMA +>>>>>>> origin/main */ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main return (uint32_t)DMA_CHCNT(dma_periph, channelx); } /*! +<<<<<<< HEAD \brief configure priority level of DMA channel +======= + \brief configure priority level of DMA channel +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -362,16 +541,28 @@ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) \arg DMA_PRIORITY_HIGH: high priority \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority \param[out] none +<<<<<<< HEAD + \retval none +======= \retval none +>>>>>>> origin/main */ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) { uint32_t ctl; +<<<<<<< HEAD if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +======= + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + +>>>>>>> origin/main /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ @@ -381,7 +572,11 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_ } /*! +<<<<<<< HEAD + \brief configure transfer data size of memory +======= \brief configure transfer data size of memory +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -398,11 +593,19 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) { uint32_t ctl; +<<<<<<< HEAD + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + +======= if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +>>>>>>> origin/main /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ @@ -412,7 +615,11 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin } /*! +<<<<<<< HEAD \brief configure transfer data size of peripheral +======= + \brief configure transfer data size of peripheral +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -429,11 +636,19 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) { uint32_t ctl; +<<<<<<< HEAD if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +======= + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + +>>>>>>> origin/main /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ @@ -443,7 +658,11 @@ void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin } /*! +<<<<<<< HEAD \brief enable next address increasement algorithm of memory +======= + \brief enable next address increasement algorithm of memory +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -457,12 +676,20 @@ void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; } /*! +<<<<<<< HEAD \brief disable next address increasement algorithm of memory +======= + \brief disable next address increasement algorithm of memory +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -476,7 +703,11 @@ void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } @@ -495,12 +726,20 @@ void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; } /*! +<<<<<<< HEAD \brief disable next address increasement algorithm of peripheral +======= + \brief disable next address increasement algorithm of peripheral +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -514,12 +753,20 @@ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; } /*! +<<<<<<< HEAD \brief configure the direction of data transfer on the channel +======= + \brief configure the direction of data transfer on the channel +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -537,7 +784,11 @@ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channel if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(DMA_PERIPHERAL_TO_MEMORY == direction){ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; } else { @@ -546,7 +797,11 @@ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channel } /*! +<<<<<<< HEAD \brief check DMA flag is set or not +======= + \brief check DMA flag is set or not +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag @@ -571,7 +826,11 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t }else{ reval = RESET; } +<<<<<<< HEAD + +======= +>>>>>>> origin/main return reval; } @@ -597,7 +856,11 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla } /*! +<<<<<<< HEAD \brief check DMA flag and interrupt enable bit is set or not +======= + \brief check DMA flag and interrupt enable bit is set or not +>>>>>>> origin/main \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag @@ -614,7 +877,11 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { uint32_t interrupt_enable = 0U, interrupt_flag = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main switch(flag){ case DMA_INT_FLAG_FTF: /* check whether the full transfer finish interrupt flag is set and enabled */ @@ -634,8 +901,13 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx default: DMA_WRONG_HANDLE } +<<<<<<< HEAD /* when the interrupt flag is set and enabled, return SET */ +======= + + /* when the interrupt flag is set and enabled, return SET */ +>>>>>>> origin/main if(interrupt_flag && interrupt_enable){ return SET; }else{ @@ -668,7 +940,11 @@ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, ui \brief enable DMA interrupt \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) +<<<<<<< HEAD \param[in] channelx: specify which DMA channel +======= + \param[in] channelx: specify which DMA channel +>>>>>>> origin/main only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] source: specify which interrupt to enbale @@ -684,7 +960,11 @@ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD + +======= +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) |= source; } @@ -708,7 +988,11 @@ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint3 if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } +<<<<<<< HEAD +======= + +>>>>>>> origin/main DMA_CHCTL(dma_periph, channelx) &= ~source; } @@ -725,13 +1009,21 @@ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint3 static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) { ErrStatus val = SUCCESS; +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(DMA1 == dma_periph){ /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ if(channelx > DMA_CH4){ val = ERROR; } } +<<<<<<< HEAD + +======= +>>>>>>> origin/main return val; } diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_exmc.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_exmc.c index 095fd43..cef6e81 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_exmc.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_exmc.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -115,7 +139,11 @@ void exmc_norsram_deinit(uint32_t norsram_region) \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE +<<<<<<< HEAD extended_mode: ENABLE or DISABLE +======= + extended_mode: ENABLE or DISABLE +>>>>>>> origin/main asyn_wait: ENABLE or DISABLE nwait_signal: ENABLE or DISABLE memory_write: ENABLE or DISABLE @@ -139,9 +167,15 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); /* clear relative bits */ +<<<<<<< HEAD + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | +======= snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | +>>>>>>> origin/main EXMC_SNCTL_NRMUX )); snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | @@ -284,7 +318,11 @@ void exmc_nand_deinit(uint32_t nand_bank) void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) { uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; +<<<<<<< HEAD +======= + +>>>>>>> origin/main npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| EXMC_NPCTL_NDTP | exmc_nand_init_struct->databus_width | @@ -422,7 +460,11 @@ void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) { /* configure the EXMC bank3 PC card control register */ EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | +<<<<<<< HEAD + EXMC_NAND_DATABUS_WIDTH_16B | +======= EXMC_NAND_DATABUS_WIDTH_16B | +>>>>>>> origin/main exmc_pccard_init_struct->ctr_latency | exmc_pccard_init_struct->atr_latency ; @@ -557,7 +599,11 @@ FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag) /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(bank); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if ((status & flag) != (uint32_t)flag ){ /* flag is reset */ return RESET; diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_fmc.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_fmc.c index 64c89b8..2b93186 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_fmc.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_fmc.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -49,7 +73,11 @@ OF SUCH DAMAGE. void fmc_wscnt_set(uint32_t wscnt) { uint32_t reg; +<<<<<<< HEAD + +======= +>>>>>>> origin/main reg = FMC_WS; /* set the wait state counter value */ reg &= ~FMC_WS_WSCNT; @@ -80,7 +108,11 @@ void fmc_unlock(void) } /*! +<<<<<<< HEAD \brief unlock the FMC bank0 operation +======= + \brief unlock the FMC bank0 operation +>>>>>>> origin/main this function can be used for all GD32F10x devices. for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. @@ -98,7 +130,11 @@ void fmc_bank0_unlock(void) } /*! +<<<<<<< HEAD + \brief unlock the FMC bank1 operation +======= \brief unlock the FMC bank1 operation +>>>>>>> origin/main this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. \param[in] none \param[out] none @@ -123,7 +159,11 @@ void fmc_lock(void) { /* set the LK bit */ FMC_CTL0 |= FMC_CTL0_LK; +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(FMC_BANK0_SIZE < FMC_SIZE){ /* set the LK bit */ FMC_CTL1 |= FMC_CTL1_LK; @@ -167,7 +207,11 @@ void fmc_bank1_lock(void) fmc_state_enum fmc_page_erase(uint32_t page_address) { fmc_state_enum fmc_state; +<<<<<<< HEAD +======= + +>>>>>>> origin/main if(FMC_BANK0_SIZE < FMC_SIZE){ if(FMC_BANK0_END_ADDRESS > page_address){ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); @@ -248,11 +292,19 @@ fmc_state_enum fmc_mass_erase(void) } }else{ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +<<<<<<< HEAD + + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; +======= if(FMC_READY == fmc_state){ /* start whole chip erase */ FMC_CTL0 |= FMC_CTL0_MER; FMC_CTL0 |= FMC_CTL0_START; +>>>>>>> origin/main /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the MER bit */ @@ -299,7 +351,11 @@ fmc_state_enum fmc_bank1_erase(void) fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); +<<<<<<< HEAD +======= + +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* start FMC bank1 erase */ FMC_CTL1 |= FMC_CTL1_MER; @@ -325,8 +381,13 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) fmc_state_enum fmc_state = FMC_READY; if(FMC_BANK0_SIZE < FMC_SIZE){ if(FMC_BANK0_END_ADDRESS > address){ +<<<<<<< HEAD + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + +======= fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; @@ -337,8 +398,13 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) FMC_CTL0 &= ~FMC_CTL0_PG; } }else{ +<<<<<<< HEAD fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); +======= + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL1 |= FMC_CTL1_PG; @@ -351,7 +417,11 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) } }else{ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; @@ -360,7 +430,11 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL0 &= ~FMC_CTL0_PG; +<<<<<<< HEAD } +======= + } +>>>>>>> origin/main } /* return the FMC state */ return fmc_state; @@ -378,8 +452,13 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) fmc_state_enum fmc_state = FMC_READY; if(FMC_BANK0_SIZE < FMC_SIZE){ if(FMC_BANK0_END_ADDRESS > address){ +<<<<<<< HEAD + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + +======= fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; @@ -390,8 +469,13 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) FMC_CTL0 &= ~FMC_CTL0_PG; } }else{ +<<<<<<< HEAD fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); +======= + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL1 |= FMC_CTL1_PG; @@ -404,7 +488,11 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) } }else{ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; @@ -413,7 +501,11 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL0 &= ~FMC_CTL0_PG; +<<<<<<< HEAD } +======= + } +>>>>>>> origin/main } /* return the FMC state */ return fmc_state; @@ -465,7 +557,11 @@ fmc_state_enum ob_erase(void) /* check the option byte security protection value */ if(RESET != ob_spc_get()){ +<<<<<<< HEAD + temp_spc = FMC_USPC; +======= temp_spc = FMC_USPC; +>>>>>>> origin/main } if(FMC_READY == fmc_state){ @@ -476,16 +572,26 @@ fmc_state_enum ob_erase(void) /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(FMC_READY == fmc_state){ /* reset the OBER bit */ FMC_CTL0 &= ~FMC_CTL0_OBER; /* set the OBPG bit */ FMC_CTL0 |= FMC_CTL0_OBPG; /* no security protection */ +<<<<<<< HEAD + OB_SPC = (uint16_t)temp_spc; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +======= OB_SPC = (uint16_t)temp_spc; /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +>>>>>>> origin/main if(FMC_TOERR != fmc_state){ /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; @@ -503,9 +609,15 @@ fmc_state_enum ob_erase(void) /*! \brief enable write protection +<<<<<<< HEAD \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if you want to protect the corresponding pages. meanwhile, sector macro could used to set specific sector write protected. +======= + \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if + you want to protect the corresponding pages. meanwhile, sector + macro could used to set specific sector write protected. +>>>>>>> origin/main one or more parameters can be selected which are shown as below: \arg OB_WPx(x = 0..31): write protect specify sector \arg OB_WP_ALL: write protect all sector @@ -525,31 +637,51 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); if(FMC_READY == fmc_state){ +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* set the OBPG bit*/ FMC_CTL0 |= FMC_CTL0_OBPG; if(0xFFU != temp_wp0){ OB_WP0 = temp_wp0; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ OB_WP1 = temp_wp1; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ OB_WP2 = temp_wp2; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ OB_WP3 = temp_wp3; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } @@ -557,7 +689,11 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; } +<<<<<<< HEAD + } +======= } +>>>>>>> origin/main /* return the FMC state */ return fmc_state; } @@ -578,6 +714,24 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc) if(FMC_READY == fmc_state){ FMC_CTL0 |= FMC_CTL0_OBER; FMC_CTL0 |= FMC_CTL0_START; +<<<<<<< HEAD + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + + /* start the option byte program */ + FMC_CTL0 |= FMC_CTL0_OBPG; + + OB_SPC = (uint16_t)ob_spc; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + +======= /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); @@ -594,6 +748,7 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc) /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +>>>>>>> origin/main if(FMC_TOERR != fmc_state){ /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; @@ -610,13 +765,21 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc) } /*! +<<<<<<< HEAD \brief program the FMC user option byte +======= + \brief program the FMC user option byte +>>>>>>> origin/main \param[in] ob_fwdgt: option byte watchdog value \arg OB_FWDGT_SW: software free watchdog \arg OB_FWDGT_HW: hardware free watchdog \param[in] ob_deepsleep: option byte deepsleep reset value \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode +<<<<<<< HEAD + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode +======= \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode +>>>>>>> origin/main \param[in] ob_stdby:option byte standby reset value \arg OB_STDBY_NRST: no reset when entering standby mode \arg OB_STDBY_RST: generate a reset instead of entering standby mode @@ -633,6 +796,16 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_ /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +<<<<<<< HEAD + + if(FMC_READY == fmc_state){ + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); + OB_USER = (uint16_t)temp; + +======= if(FMC_READY == fmc_state){ /* set the OBPG bit*/ @@ -641,6 +814,7 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_ temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); OB_USER = (uint16_t)temp; +>>>>>>> origin/main /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); @@ -666,12 +840,21 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) if(FMC_READY == fmc_state){ /* set the OBPG bit */ +<<<<<<< HEAD + FMC_CTL0 |= FMC_CTL0_OBPG; + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + +======= FMC_CTL0 |= FMC_CTL0_OBPG; REG16(address) = data; /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); +>>>>>>> origin/main if(FMC_TOERR != fmc_state){ /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; @@ -826,7 +1009,11 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) { uint32_t ret1 = RESET; uint32_t ret2 = RESET; +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ /* get the staus of interrupt flag */ ret1 = (uint32_t)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); @@ -873,7 +1060,11 @@ void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) fmc_state_enum fmc_bank0_state_get(void) { fmc_state_enum fmc_state = FMC_READY; +<<<<<<< HEAD + +======= +>>>>>>> origin/main if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ fmc_state = FMC_BUSY; }else{ @@ -881,7 +1072,11 @@ fmc_state_enum fmc_bank0_state_get(void) fmc_state = FMC_WPERR; }else{ if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ +<<<<<<< HEAD fmc_state = FMC_PGERR; +======= + fmc_state = FMC_PGERR; +>>>>>>> origin/main } } } @@ -906,7 +1101,11 @@ fmc_state_enum fmc_bank1_state_get(void) fmc_state = FMC_WPERR; }else{ if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ +<<<<<<< HEAD + fmc_state = FMC_PGERR; +======= fmc_state = FMC_PGERR; +>>>>>>> origin/main } } } @@ -924,14 +1123,22 @@ fmc_state_enum fmc_bank1_state_get(void) fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) { fmc_state_enum fmc_state = FMC_BUSY; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* wait for FMC ready */ do{ /* get FMC state */ fmc_state = fmc_bank0_state_get(); timeout--; }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); +<<<<<<< HEAD +======= + +>>>>>>> origin/main if(FMC_BUSY == fmc_state){ fmc_state = FMC_TOERR; } @@ -948,14 +1155,22 @@ fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) { fmc_state_enum fmc_state = FMC_BUSY; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* wait for FMC ready */ do{ /* get FMC state */ fmc_state = fmc_bank1_state_get(); timeout--; }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(FMC_BUSY == fmc_state){ fmc_state = FMC_TOERR; } diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_fwdgt.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_fwdgt.c index 9f1240b..d85b323 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_fwdgt.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_fwdgt.c @@ -1,7 +1,11 @@ /*! \file gd32f10x_fwdgt.c \brief FWDGT driver +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,29 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +59,7 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -88,14 +116,30 @@ ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) { uint32_t timeout = FWDGT_PSC_TIMEOUT; uint32_t flag_status = RESET; +<<<<<<< HEAD /* enable write access to FWDGT_PSC */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +======= + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + +>>>>>>> origin/main /* wait until the PUD flag to be reset */ do{ flag_status = FWDGT_STAT & FWDGT_STAT_PUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); +<<<<<<< HEAD + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; +======= if ((uint32_t)RESET != flag_status){ return ERROR; @@ -103,6 +147,7 @@ ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) /* configure FWDGT */ FWDGT_PSC = (uint32_t)prescaler_value; +>>>>>>> origin/main return SUCCESS; } @@ -117,19 +162,34 @@ ErrStatus fwdgt_reload_value_config(uint16_t reload_value) { uint32_t timeout = FWDGT_RLD_TIMEOUT; uint32_t flag_status = RESET; +<<<<<<< HEAD /* enable write access to FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +======= + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + +>>>>>>> origin/main /* wait until the RUD flag to be reset */ do{ flag_status = FWDGT_STAT & FWDGT_STAT_RUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); +<<<<<<< HEAD + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + +======= if ((uint32_t)RESET != flag_status){ return ERROR; } +>>>>>>> origin/main FWDGT_RLD = RLD_RLD(reload_value); return SUCCESS; @@ -165,14 +225,22 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) { uint32_t timeout = FWDGT_PSC_TIMEOUT; uint32_t flag_status = RESET; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* enable write access to FWDGT_PSC,and FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; /* wait until the PUD flag to be reset */ do{ flag_status = FWDGT_STAT & FWDGT_STAT_PUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if((uint32_t)RESET != flag_status){ return ERROR; } @@ -184,7 +252,11 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) do{ flag_status = FWDGT_STAT & FWDGT_STAT_RUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); +<<<<<<< HEAD + +======= +>>>>>>> origin/main if((uint32_t)RESET != flag_status){ return ERROR; } @@ -197,7 +269,11 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) /*! \brief get flag state of FWDGT +<<<<<<< HEAD \param[in] flag: flag to get +======= + \param[in] flag: flag to get +>>>>>>> origin/main only one parameter can be selected which is shown as below: \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going @@ -209,6 +285,10 @@ FlagStatus fwdgt_flag_get(uint16_t flag) if(FWDGT_STAT & flag){ return SET; } +<<<<<<< HEAD + +======= +>>>>>>> origin/main return RESET; } diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_gpio.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_gpio.c index 60147cc..f472c64 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_gpio.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_gpio.c @@ -1,7 +1,11 @@ /*! \file gd32f10x_gpio.c \brief GPIO driver +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,12 +37,39 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ #include "gd32f10x_gpio.h" +<<<<<<< HEAD +#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ +======= #define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ +>>>>>>> origin/main #define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ #define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ #define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ @@ -110,7 +142,11 @@ void gpio_afio_deinit(void) /*! \brief GPIO parameter initialization +<<<<<<< HEAD + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] mode: gpio pin mode only one parameter can be selected which is shown as below: \arg GPIO_MODE_AIN: analog input mode @@ -141,7 +177,11 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin /* GPIO mode configuration */ temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* GPIO speed configuration */ if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ /* output mode max speed:10MHz,2MHz,50MHz */ @@ -152,12 +192,20 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin for(i = 0U;i < 8U;i++){ if((1U << i) & pin){ reg = GPIO_CTL0(gpio_periph); +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* clear the specified pin mode bits */ reg &= ~GPIO_MODE_MASK(i); /* set the specified pin mode bits */ reg |= GPIO_MODE_SET(i, temp_mode); +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* set IPD or IPU */ if(GPIO_MODE_IPD == mode){ /* reset the corresponding OCTL bit */ @@ -176,12 +224,20 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin for(i = 8U;i < 16U;i++){ if((1U << i) & pin){ reg = GPIO_CTL1(gpio_periph); +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* clear the specified pin mode bits */ reg &= ~GPIO_MODE_MASK(i - 8U); /* set the specified pin mode bits */ reg |= GPIO_MODE_SET(i - 8U, temp_mode); +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* set IPD or IPU */ if(GPIO_MODE_IPD == mode){ /* reset the corresponding OCTL bit */ @@ -200,7 +256,11 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin /*! \brief set GPIO pin +<<<<<<< HEAD \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -214,7 +274,11 @@ void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) /*! \brief reset GPIO pin +<<<<<<< HEAD + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -228,7 +292,11 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) /*! \brief write data to the specified GPIO pin +<<<<<<< HEAD \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -249,7 +317,11 @@ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) /*! \brief write data to the specified GPIO port +<<<<<<< HEAD + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] data: specify the value to be written to the port output data register \param[out] none \retval none @@ -261,7 +333,11 @@ void gpio_port_write(uint32_t gpio_periph,uint16_t data) /*! \brief get GPIO pin input status +<<<<<<< HEAD + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -271,7 +347,11 @@ void gpio_port_write(uint32_t gpio_periph,uint16_t data) FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) { if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ +<<<<<<< HEAD return SET; +======= + return SET; +>>>>>>> origin/main }else{ return RESET; } @@ -279,7 +359,11 @@ FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) /*! \brief get GPIO port input status +<<<<<<< HEAD + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[out] none \retval input status of gpio all pins */ @@ -290,7 +374,11 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph) /*! \brief get GPIO pin output status +<<<<<<< HEAD \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -308,7 +396,11 @@ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) /*! \brief get GPIO port output status +<<<<<<< HEAD + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[out] none \retval output status of gpio all pins */ @@ -326,7 +418,11 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) \arg GPIO_USART1_REMAP: USART1 remapping \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping \arg GPIO_USART2_FULL_REMAP: USART2 full remapping +<<<<<<< HEAD \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping +======= + \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping +>>>>>>> origin/main \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping @@ -342,14 +438,24 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) \arg GPIO_ADC0_ETRGRT_REMAP: ADC0 external trigger routine conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) \arg GPIO_ADC1_ETRGRT_REMAP: ADC1 external trigger routine conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) +<<<<<<< HEAD + \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices) +======= \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices) +>>>>>>> origin/main \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices) \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled +<<<<<<< HEAD \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL, GD32F10X_HD and GD32F10X_XD devices) \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices) +======= + \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL, GD32F10X_HD and GD32F10X_XD devices) + \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) + \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices) +>>>>>>> origin/main \arg GPIO_TIMER8_REMAP: TIMER8 remapping \arg GPIO_TIMER9_REMAP: TIMER9 remapping \arg GPIO_TIMER10_REMAP: TIMER10 remapping @@ -387,12 +493,20 @@ void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) temp_reg &= ~(remap1 << ((remap >> 0x15U)*0x10U)); temp_reg |= ~PCF_SWJCFG_MASK; } +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* set pin remap value */ if(DISABLE != newvalue){ temp_reg |= (remap1 << ((remap >> 0x15U)*0x10U)); } +<<<<<<< HEAD + +======= +>>>>>>> origin/main if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ /* set AFIO_PCF1 regiter value */ AFIO_PCF1 = temp_reg; @@ -409,7 +523,11 @@ void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) \arg GPIO_PORT_SOURCE_GPIOB: output port source B \arg GPIO_PORT_SOURCE_GPIOC: output port source C \arg GPIO_PORT_SOURCE_GPIOD: output port source D +<<<<<<< HEAD \arg GPIO_PORT_SOURCE_GPIOE: output port source E +======= + \arg GPIO_PORT_SOURCE_GPIOE: output port source E +>>>>>>> origin/main \arg GPIO_PORT_SOURCE_GPIOF: output port source F \arg GPIO_PORT_SOURCE_GPIOG: output port source G \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) @@ -462,6 +580,7 @@ void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) { uint32_t reg = 0U; reg = AFIO_EC; +<<<<<<< HEAD /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); @@ -469,6 +588,15 @@ void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); reg |= (uint32_t)output_pin; +======= + + /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ + reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); + + reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); + reg |= (uint32_t)output_pin; + +>>>>>>> origin/main AFIO_EC = reg; } @@ -496,7 +624,11 @@ void gpio_event_output_disable(void) /*! \brief lock GPIO pin +<<<<<<< HEAD + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +======= \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) +>>>>>>> origin/main \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_i2c.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_i2c.c index 9721ae8..b92d3b5 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_i2c.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_i2c.c @@ -1,7 +1,11 @@ /*! \file gd32f10x_i2c.c \brief I2C driver +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -12,6 +16,29 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,6 +60,7 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -78,7 +106,11 @@ void i2c_deinit(uint32_t i2c_periph) \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) \param[in] dutycyc: duty cycle in fast mode only one parameter can be selected which is shown as below: +<<<<<<< HEAD + \arg I2C_DTCY_2: T_low/T_high=2 +======= \arg I2C_DTCY_2: T_low/T_high=2 +>>>>>>> origin/main \arg I2C_DTCY_16_9: T_low/T_high=16/9 \param[out] none \retval none @@ -87,7 +119,11 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) { uint32_t pclk1, clkc, freq, risetime; uint32_t temp; +<<<<<<< HEAD +======= + +>>>>>>> origin/main pclk1 = rcu_clock_freq_get(CK_APB1); /* I2C peripheral clock frequency */ freq = (uint32_t)(pclk1/1000000U); @@ -97,9 +133,15 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) temp = I2C_CTL1(i2c_periph); temp &= ~I2C_CTL1_I2CCLK; temp |= freq; +<<<<<<< HEAD + + I2C_CTL1(i2c_periph) = temp; + +======= I2C_CTL1(i2c_periph) = temp; +>>>>>>> origin/main if(100000U >= clkspeed){ /* the maximum SCL rise time is 1000ns in standard mode */ risetime = (uint32_t)((pclk1/1000000U)+1U); @@ -110,7 +152,11 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) }else{ I2C_RT(i2c_periph) = risetime; } +<<<<<<< HEAD + clkc = (uint32_t)(pclk1/(clkspeed*2U)); +======= clkc = (uint32_t)(pclk1/(clkspeed*2U)); +>>>>>>> origin/main if(clkc < 0x04U){ /* the CLKC in standard mode minmum value is 4 */ clkc = 0x04U; @@ -131,7 +177,11 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) } if(0U == (clkc & I2C_CKCFG_CLKC)){ /* the CLKC in fast mode minmum value is 1 */ +<<<<<<< HEAD clkc |= 0x0001U; +======= + clkc |= 0x0001U; +>>>>>>> origin/main } I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; @@ -140,7 +190,11 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) } /*! +<<<<<<< HEAD + \brief configure I2C address +======= \brief configure I2C address +>>>>>>> origin/main \param[in] i2c_periph: I2Cx(x=0,1) \param[in] mode: only one parameter can be selected which is shown as below: @@ -158,9 +212,15 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat { /* SMBus/I2C mode selected */ uint32_t ctl = 0U; +<<<<<<< HEAD ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SMBEN); +======= + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); +>>>>>>> origin/main ctl |= mode; I2C_CTL0(i2c_periph) = ctl; /* configure address */ @@ -230,11 +290,19 @@ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) /*! \brief master sends slave address \param[in] i2c_periph: I2Cx(x=0,1) +<<<<<<< HEAD + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver +======= \param[in] addr: slave address \param[in] trandirection: transmitter or receiver only one parameter can be selected which is shown as below: \arg I2C_TRANSMITTER: transmitter \arg I2C_RECEIVER: receiver +>>>>>>> origin/main \param[out] none \retval none */ @@ -266,7 +334,11 @@ void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) /*! \brief disable dual-address mode +<<<<<<< HEAD \param[in] i2c_periph: I2Cx(x=0,1) +======= + \param[in] i2c_periph: I2Cx(x=0,1) +>>>>>>> origin/main \param[out] none \retval none */ @@ -277,7 +349,11 @@ void i2c_dualaddr_disable(uint32_t i2c_periph) /*! \brief enable I2C +<<<<<<< HEAD + \param[in] i2c_periph: I2Cx(x=0,1) +======= \param[in] i2c_periph: I2Cx(x=0,1) +>>>>>>> origin/main \param[out] none \retval none */ @@ -288,7 +364,11 @@ void i2c_enable(uint32_t i2c_periph) /*! \brief disable I2C +<<<<<<< HEAD \param[in] i2c_periph: I2Cx(x=0,1) +======= + \param[in] i2c_periph: I2Cx(x=0,1) +>>>>>>> origin/main \param[out] none \retval none */ @@ -322,7 +402,11 @@ void i2c_stop_on_bus(uint32_t i2c_periph) /*! \brief I2C transmit data function \param[in] i2c_periph: I2Cx(x=0,1) +<<<<<<< HEAD + \param[in] data: data of transmission +======= \param[in] data: data of transmission +>>>>>>> origin/main \param[out] none \retval none */ @@ -356,9 +440,15 @@ void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) { /* configure I2C DMA function */ uint32_t ctl = 0U; +<<<<<<< HEAD + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); +======= ctl = I2C_CTL1(i2c_periph); ctl &= ~(I2C_CTL1_DMAON); +>>>>>>> origin/main ctl |= dmastate; I2C_CTL1(i2c_periph) = ctl; } @@ -377,9 +467,15 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) { /* configure DMA last transfer */ uint32_t ctl = 0U; +<<<<<<< HEAD ctl = I2C_CTL1(i2c_periph); ctl &= ~(I2C_CTL1_DMALST); +======= + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); +>>>>>>> origin/main ctl |= dmalast; I2C_CTL1(i2c_periph) = ctl; } @@ -398,9 +494,15 @@ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) { /* configure I2C SCL strerching */ uint32_t ctl = 0U; +<<<<<<< HEAD + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SS); +======= ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SS); +>>>>>>> origin/main ctl |= stretchpara; I2C_CTL0(i2c_periph) = ctl; } @@ -419,9 +521,15 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) { /* configure slave response to a general call enable or disable */ uint32_t ctl = 0U; +<<<<<<< HEAD ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_GCEN); +======= + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); +>>>>>>> origin/main ctl |= gcallpara; I2C_CTL0(i2c_periph) = ctl; } @@ -440,9 +548,15 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) { /* modify CTL0 and configure software reset I2C state */ uint32_t ctl = 0U; +<<<<<<< HEAD + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); +======= ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SRESET); +>>>>>>> origin/main ctl |= sreset; I2C_CTL0(i2c_periph) = ctl; } @@ -452,8 +566,13 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) \param[in] i2c_periph: I2Cx(x=0,1) \param[in] pecstate: only one parameter can be selected which is shown as below: +<<<<<<< HEAD \arg I2C_PEC_ENABLE: PEC calculation on \arg I2C_PEC_DISABLE: PEC calculation off +======= + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off +>>>>>>> origin/main \param[out] none \retval none */ @@ -461,7 +580,11 @@ void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) { /* on/off PEC calculation */ uint32_t ctl = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_PECEN); ctl |= pecstate; @@ -473,8 +596,13 @@ void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) \param[in] i2c_periph: I2Cx(x=0,1) \param[in] pecpara: only one parameter can be selected which is shown as below: +<<<<<<< HEAD \arg I2C_PECTRANS_ENABLE: transfer PEC \arg I2C_PECTRANS_DISABLE: not transfer PEC +======= + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC +>>>>>>> origin/main \param[out] none \retval none */ @@ -482,7 +610,11 @@ void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) { /* whether to transfer PEC */ uint32_t ctl = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_PECTRANS); ctl |= pecpara; @@ -505,8 +637,13 @@ uint8_t i2c_pec_value_get(uint32_t i2c_periph) \param[in] i2c_periph: I2Cx(x=0,1) \param[in] smbuspara: only one parameter can be selected which is shown as below: +<<<<<<< HEAD + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin +======= \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin +>>>>>>> origin/main \param[out] none \retval none */ @@ -514,7 +651,11 @@ void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) { /* issue alert through SMBA pin configure*/ uint32_t ctl = 0U; +<<<<<<< HEAD +======= + +>>>>>>> origin/main ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SALT); ctl |= smbuspara; @@ -535,7 +676,11 @@ void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) { /* enable or disable I2C ARP protocol*/ uint32_t ctl = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_ARPEN); ctl |= arpstate; @@ -588,9 +733,15 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_PECERR: PEC error when receiving data +<<<<<<< HEAD + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode +======= \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_AERR: acknowledge error \arg I2C_FLAG_LOSTARB: arbitration lost in master mode +>>>>>>> origin/main \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \param[out] none @@ -613,7 +764,11 @@ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: \arg I2C_INT_ERR: error interrupt +<<<<<<< HEAD \arg I2C_INT_EV: event interrupt +======= + \arg I2C_INT_EV: event interrupt +>>>>>>> origin/main \arg I2C_INT_BUF: buffer interrupt \param[out] none \retval none @@ -628,8 +783,13 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) \param[in] i2c_periph: I2Cx(x=0,1) \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum only one parameter can be selected which is shown as below: +<<<<<<< HEAD + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable +======= \arg I2C_INT_ERR: error interrupt enable \arg I2C_INT_EV: event interrupt enable +>>>>>>> origin/main \arg I2C_INT_BUF: buffer interrupt enable \param[out] none \retval none @@ -664,10 +824,17 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { uint32_t intenable = 0U, flagstatus = 0U, bufie; +<<<<<<< HEAD /* check BUFIE */ bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; +======= + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + +>>>>>>> origin/main /* get the interrupt enable bit status */ intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); /* get the corresponding flag bit status */ @@ -675,7 +842,11 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ if(intenable && bufie){ +<<<<<<< HEAD intenable = 1U; +======= + intenable = 1U; +>>>>>>> origin/main }else{ intenable = 0U; } @@ -683,7 +854,11 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i if((0U != flagstatus) && (0U != intenable)){ return SET; }else{ +<<<<<<< HEAD + return RESET; +======= return RESET; +>>>>>>> origin/main } } diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_pmu.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_pmu.c index cb11509..8583cc6 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_pmu.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_pmu.c @@ -12,6 +12,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -33,6 +34,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -103,7 +127,11 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) { /* clear sleepdeep bit of Cortex-M3 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* select WFI or WFE command to enter sleep mode */ if(WFI_CMD == sleepmodecmd){ __WFI(); @@ -119,7 +147,11 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) \arg PMU_LDO_NORMAL: LDO work in normal power mode when pmu enter deepsleep mode \arg PMU_LDO_LOWPOWER: LDO work in low power mode when pmu enter deepsleep mode \param[in] deepsleepmodecmd: +<<<<<<< HEAD + only one parameter can be selected which is shown as below: +======= only one parameter can be selected which is shown as below: +>>>>>>> origin/main \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none @@ -127,6 +159,15 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) */ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) { +<<<<<<< HEAD + static uint32_t reg_snap[ 4 ]; + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + +======= static uint32_t reg_snap[ 4 ]; /* clear stbmod and ldolp bits */ PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); @@ -134,6 +175,7 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) /* set ldolp bit according to pmu_ldo */ PMU_CTL |= ldo; +>>>>>>> origin/main /* set sleepdeep bit of Cortex-M3 system control register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; @@ -141,12 +183,20 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) reg_snap[1] = REG32(0xE000E100U); reg_snap[2] = REG32(0xE000E104U); reg_snap[3] = REG32(0xE000E108U); +<<<<<<< HEAD +======= + +>>>>>>> origin/main REG32(0xE000E010U) &= 0x00010004U; REG32(0xE000E180U) = 0XFF7FF83DU; REG32(0xE000E184U) = 0XBFFFF8FFU; REG32(0xE000E188U) = 0xFFFFFFFFU; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* select WFI or WFE command to enter deepsleep mode */ if(WFI_CMD == deepsleepmodecmd){ __WFI(); @@ -156,10 +206,17 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) __WFE(); } +<<<<<<< HEAD + REG32(0xE000E010U) = reg_snap[0] ; + REG32(0xE000E100U) = reg_snap[1] ; + REG32(0xE000E104U) = reg_snap[2] ; + REG32(0xE000E108U) = reg_snap[3] ; +======= REG32(0xE000E010U) = reg_snap[0] ; REG32(0xE000E100U) = reg_snap[1] ; REG32(0xE000E104U) = reg_snap[2] ; REG32(0xE000E108U) = reg_snap[3] ; +>>>>>>> origin/main /* reset sleepdeep bit of Cortex-M3 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_rcu.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_rcu.c index a29c616..8df0f19 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_rcu.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_rcu.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -277,7 +301,11 @@ void rcu_bkp_reset_disable(void) void rcu_system_clock_source_config(uint32_t ck_sys) { uint32_t reg; +<<<<<<< HEAD +======= + +>>>>>>> origin/main reg = RCU_CFG0; /* reset the SCS bits and set according to ck_sys */ reg &= ~RCU_CFG0_SCS; @@ -309,7 +337,11 @@ uint32_t rcu_system_clock_source_get(void) void rcu_ahb_clock_config(uint32_t ck_ahb) { uint32_t reg; +<<<<<<< HEAD + +======= +>>>>>>> origin/main reg = RCU_CFG0; /* reset the AHBPSC bits and set according to ck_ahb */ @@ -332,7 +364,11 @@ void rcu_ahb_clock_config(uint32_t ck_ahb) void rcu_apb1_clock_config(uint32_t ck_apb1) { uint32_t reg; +<<<<<<< HEAD +======= + +>>>>>>> origin/main reg = RCU_CFG0; /* reset the APB1PSC and set according to ck_apb1 */ @@ -355,7 +391,11 @@ void rcu_apb1_clock_config(uint32_t ck_apb1) void rcu_apb2_clock_config(uint32_t ck_apb2) { uint32_t reg; +<<<<<<< HEAD + +======= +>>>>>>> origin/main reg = RCU_CFG0; /* reset the APB2PSC and set according to ck_apb2 */ @@ -382,7 +422,11 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) void rcu_ckout0_config(uint32_t ckout0_src) { uint32_t reg; +<<<<<<< HEAD + +======= +>>>>>>> origin/main reg = RCU_CFG0; /* reset the CKOUT0SRC, set according to ckout0_src */ @@ -391,7 +435,11 @@ void rcu_ckout0_config(uint32_t ckout0_src) } /*! +<<<<<<< HEAD \brief configure the main PLL clock +======= + \brief configure the main PLL clock +>>>>>>> origin/main \param[in] pll_src: PLL clock source selection only one parameter can be selected which is shown as below: \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL @@ -454,7 +502,11 @@ void rcu_predv0_config(uint32_t predv0_div) void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) { uint32_t reg = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main reg = RCU_CFG1; /* reset PREDV0SEL and PREDV0 bits */ reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); @@ -475,7 +527,11 @@ void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) void rcu_predv1_config(uint32_t predv1_div) { uint32_t reg = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main reg = RCU_CFG1; /* reset the PREDV1 bits */ reg &= ~RCU_CFG1_PREDV1; @@ -486,7 +542,11 @@ void rcu_predv1_config(uint32_t predv1_div) } /*! +<<<<<<< HEAD \brief configure the PLL1 clock +======= + \brief configure the PLL1 clock +>>>>>>> origin/main \param[in] pll_mul: PLL clock multiplication factor only one parameter can be selected which is shown as below: \arg RCU_PLL1_MULx (x = 8..16, 20) @@ -500,7 +560,11 @@ void rcu_pll1_config(uint32_t pll_mul) } /*! +<<<<<<< HEAD + \brief configure the PLL2 clock +======= \brief configure the PLL2 clock +>>>>>>> origin/main \param[in] pll_mul: PLL clock multiplication factor only one parameter can be selected which is shown as below: \arg RCU_PLL2_MULx (x = 8..16, 20) @@ -510,7 +574,11 @@ void rcu_pll1_config(uint32_t pll_mul) void rcu_pll2_config(uint32_t pll_mul) { RCU_CFG1 &= ~RCU_CFG1_PLL2MF; +<<<<<<< HEAD + RCU_CFG1 |= pll_mul; +======= RCU_CFG1 |= pll_mul; +>>>>>>> origin/main } #endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ @@ -572,7 +640,11 @@ void rcu_adc_clock_config(uint32_t adc_psc) void rcu_usb_clock_config(uint32_t usb_psc) { uint32_t reg; +<<<<<<< HEAD +======= + +>>>>>>> origin/main reg = RCU_CFG0; /* configure the USBD/USBFS prescaler factor */ @@ -599,8 +671,13 @@ void rcu_usb_clock_config(uint32_t usb_psc) void rcu_rtc_clock_config(uint32_t rtc_clock_source) { uint32_t reg; +<<<<<<< HEAD + + reg = RCU_BDCTL; +======= reg = RCU_BDCTL; +>>>>>>> origin/main /* reset the RTCSRC bits and set according to rtc_clock_source */ reg &= ~RCU_BDCTL_RTCSRC; RCU_BDCTL = (reg | rtc_clock_source); @@ -619,8 +696,13 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source) void rcu_i2s1_clock_config(uint32_t i2s_clock_source) { uint32_t reg; +<<<<<<< HEAD reg = RCU_CFG1; +======= + + reg = RCU_CFG1; +>>>>>>> origin/main /* reset the I2S1SEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG1_I2S1SEL; RCU_CFG1 = (reg | i2s_clock_source); @@ -638,8 +720,13 @@ void rcu_i2s1_clock_config(uint32_t i2s_clock_source) void rcu_i2s2_clock_config(uint32_t i2s_clock_source) { uint32_t reg; +<<<<<<< HEAD + + reg = RCU_CFG1; +======= reg = RCU_CFG1; +>>>>>>> origin/main /* reset the I2S2SEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG1_I2S2SEL; RCU_CFG1 = (reg | i2s_clock_source); @@ -789,7 +876,11 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) uint32_t stb_cnt = 0U; ErrStatus reval = ERROR; FlagStatus osci_stat = RESET; +<<<<<<< HEAD + +======= +>>>>>>> origin/main switch(osci){ /* wait HXTAL stable */ case RCU_HXTAL: @@ -980,7 +1071,11 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) { uint32_t reg; +<<<<<<< HEAD + +======= +>>>>>>> origin/main switch(osci){ /* disable HXTAL to bypass mode */ case RCU_HXTAL: @@ -1039,7 +1134,11 @@ void rcu_hxtal_clock_monitor_disable(void) void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) { uint32_t reg; +<<<<<<< HEAD +======= + +>>>>>>> origin/main reg = RCU_CTL; /* reset the IRC8MADJ bits and set according to irc8m_adjval */ reg &= ~RCU_CTL_IRC8MADJ; @@ -1058,7 +1157,11 @@ void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) \retval none */ void rcu_deepsleep_voltage_set(uint32_t dsvol) +<<<<<<< HEAD +{ +======= { +>>>>>>> origin/main dsvol &= RCU_DSV_DSLPVS; RCU_DSV = dsvol; } @@ -1163,17 +1266,29 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) idx = GET_BITS(RCU_CFG0, 4, 7); clk_exp = ahb_exp[idx]; ahb_freq = cksys_freq >> clk_exp; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* calculate APB1 clock frequency */ idx = GET_BITS(RCU_CFG0, 8, 10); clk_exp = apb1_exp[idx]; apb1_freq = ahb_freq >> clk_exp; +<<<<<<< HEAD +======= + +>>>>>>> origin/main /* calculate APB2 clock frequency */ idx = GET_BITS(RCU_CFG0, 11, 13); clk_exp = apb2_exp[idx]; apb2_freq = ahb_freq >> clk_exp; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* return the clocks frequency */ switch(clock){ case CK_SYS: diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_rtc.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_rtc.c index d984d44..dd73d6a 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_rtc.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_rtc.c @@ -1,7 +1,11 @@ /*! \file gd32f10x_rtc.c \brief RTC driver +<<<<<<< HEAD +======= + +>>>>>>> origin/main \version 2014-12-26, V1.0.0, firmware for GD32F10x \version 2017-06-20, V2.0.0, firmware for GD32F10x \version 2018-07-31, V2.1.0, firmware for GD32F10x @@ -11,6 +15,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +37,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -56,7 +84,11 @@ void rtc_configuration_mode_enter(void) } /*! +<<<<<<< HEAD + \brief exit RTC configuration mode +======= \brief exit RTC configuration mode +>>>>>>> origin/main \param[in] none \param[out] none \retval none @@ -151,7 +183,11 @@ void rtc_alarm_config(uint32_t alarm) uint32_t rtc_counter_get(void) { uint32_t temp = 0x0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main temp = RTC_CNTL; temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); return temp; @@ -166,14 +202,22 @@ uint32_t rtc_counter_get(void) uint32_t rtc_divider_get(void) { uint32_t temp = 0x00U; +<<<<<<< HEAD +======= + +>>>>>>> origin/main temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); temp |= RTC_DIVL; return temp; } /*! +<<<<<<< HEAD + \brief get RTC flag status +======= \brief get RTC flag status +>>>>>>> origin/main \param[in] flag: specify which flag status to get only one parameter can be selected which is shown as below: \arg RTC_FLAG_SECOND: second interrupt flag @@ -211,7 +255,11 @@ void rtc_flag_clear(uint32_t flag) } /*! +<<<<<<< HEAD + \brief get RTC interrupt flag status +======= \brief get RTC interrupt flag status +>>>>>>> origin/main \param[in] flag: specify which flag status to get only one parameter can be selected which is shown as below: \arg RTC_INT_FLAG_SECOND: second interrupt flag diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_sdio.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_sdio.c index 7a12ac2..92baab7 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_sdio.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_sdio.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_spi.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_spi.c index fb776d4..96c3847 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_spi.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_spi.c @@ -506,7 +506,11 @@ uint16_t spi_crc_polynomial_get(uint32_t spi_periph) } /*! +<<<<<<< HEAD \brief turn on SPI CRC function +======= + \brief turn on SPI CRC function +>>>>>>> origin/main \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_timer.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_timer.c index 83eb072..61a026e 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_timer.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_timer.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -311,7 +335,11 @@ void timer_counter_down_direction(uint32_t timer_periph) void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) { TIMER_PSC(timer_periph) = (uint32_t)prescaler; +<<<<<<< HEAD +======= + +>>>>>>> origin/main if(TIMER_PSC_RELOAD_NOW == pscreload){ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } @@ -327,15 +355,24 @@ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t void timer_repetition_value_config(uint32_t timer_periph, uint8_t repetition) { TIMER_CREP(timer_periph) = (uint32_t)repetition; +<<<<<<< HEAD +} + +======= } +>>>>>>> origin/main /*! \brief configure TIMER autoreload register value \param[in] timer_periph: TIMERx(x=0..13) \param[in] autoreload: the counter auto-reload value \param[out] none \retval none +<<<<<<< HEAD */ +======= +*/ +>>>>>>> origin/main void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) { TIMER_CAR(timer_periph) = (uint32_t)autoreload; @@ -347,7 +384,11 @@ void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) \param[in] counter: the counter value \param[out] none \retval none +<<<<<<< HEAD +*/ +======= */ +>>>>>>> origin/main void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) { TIMER_CNT(timer_periph) = (uint32_t)counter; @@ -358,7 +399,11 @@ void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval counter value +<<<<<<< HEAD +*/ +======= */ +>>>>>>> origin/main uint32_t timer_counter_read(uint32_t timer_periph) { uint32_t count_value = 0U; @@ -371,7 +416,11 @@ uint32_t timer_counter_read(uint32_t timer_periph) \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval prescaler register value +<<<<<<< HEAD */ +======= +*/ +>>>>>>> origin/main uint16_t timer_prescaler_read(uint32_t timer_periph) { uint16_t prescaler_value = 0U; @@ -396,12 +445,20 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) }else if(TIMER_SP_MODE_REPETITIVE == spmode){ TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); }else{ +<<<<<<< HEAD + /* illegal parameters */ +======= /* illegal parameters */ +>>>>>>> origin/main } } /*! +<<<<<<< HEAD + \brief configure TIMER update source +======= \brief configure TIMER update source +>>>>>>> origin/main \param[in] timer_periph: TIMERx(x=0..13) \param[in] update: only one parameter can be selected which is shown as below: @@ -439,7 +496,11 @@ void timer_update_source_config(uint32_t timer_periph, uint32_t update) */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma) { +<<<<<<< HEAD TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +======= + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +>>>>>>> origin/main } /*! @@ -459,7 +520,11 @@ void timer_dma_enable(uint32_t timer_periph, uint16_t dma) */ void timer_dma_disable(uint32_t timer_periph, uint16_t dma) { +<<<<<<< HEAD + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +======= TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +>>>>>>> origin/main } /*! @@ -468,7 +533,11 @@ void timer_dma_disable(uint32_t timer_periph, uint16_t dma) \param[in] dma_request: channel DMA request source selection only one parameter can be selected which is shown as below: \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs +<<<<<<< HEAD \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs +======= + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs +>>>>>>> origin/main \param[out] none \retval none */ @@ -479,7 +548,11 @@ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; }else{ +<<<<<<< HEAD + /* illegal parameters */ +======= /* illegal parameters */ +>>>>>>> origin/main } } @@ -520,16 +593,28 @@ void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uin } /*! +<<<<<<< HEAD + \brief software generate events +======= \brief software generate events +>>>>>>> origin/main \param[in] timer_periph: please refer to the following parameters \param[in] event: the timer software event generation sources one or more parameters can be selected which are shown as below: \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13) +<<<<<<< HEAD + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) +======= \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) +>>>>>>> origin/main \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11) \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7) \param[out] none @@ -559,7 +644,11 @@ void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) } /*! +<<<<<<< HEAD \brief configure TIMER break function +======= + \brief configure TIMER break function +>>>>>>> origin/main \param[in] timer_periph: TIMERx(x=0,7) \param[in] breakpara: TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE @@ -644,9 +733,15 @@ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) } /*! +<<<<<<< HEAD + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE +======= \brief enable or disable channel capture/compare control shadow register \param[in] timer_periph: TIMERx(x=0,7) \param[in] newvalue: ENABLE or DISABLE +>>>>>>> origin/main \param[out] none \retval none */ @@ -665,10 +760,17 @@ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus ne \param[in] ccuctl: channel control shadow register update control only one parameter can be selected which is shown as below: \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set +<<<<<<< HEAD + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +======= \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs \param[out] none \retval none */ +>>>>>>> origin/main void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) { if(TIMER_UPDATECTL_CCU == ccuctl){ @@ -676,7 +778,11 @@ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; }else{ +<<<<<<< HEAD /* illegal parameters */ +======= + /* illegal parameters */ +>>>>>>> origin/main } } @@ -1056,7 +1162,11 @@ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, } /*! +<<<<<<< HEAD + \brief configure TIMER channel output polarity +======= \brief configure TIMER channel output polarity +>>>>>>> origin/main \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: @@ -1100,14 +1210,22 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe } /*! +<<<<<<< HEAD + \brief configure TIMER channel complementary output polarity +======= \brief configure TIMER channel complementary output polarity +>>>>>>> origin/main \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) +<<<<<<< HEAD \param[in] ocnpolarity: channel complementary output polarity +======= + \param[in] ocnpolarity: channel complementary output polarity +>>>>>>> origin/main only one parameter can be selected which is shown as below: \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low @@ -1148,8 +1266,13 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, u \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) \param[in] state: TIMER channel enable state only one parameter can be selected which is shown as below: +<<<<<<< HEAD \arg TIMER_CCX_ENABLE: channel enable \arg TIMER_CCX_DISABLE: channel disable +======= + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable +>>>>>>> origin/main \param[out] none \retval none */ @@ -1191,8 +1314,13 @@ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, \arg TIMER_CH_2: TIMER channel2 \param[in] ocnstate: TIMER channel complementary output enable state only one parameter can be selected which is shown as below: +<<<<<<< HEAD + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable +======= \arg TIMER_CCXN_ENABLE: channel complementary enable \arg TIMER_CCXN_DISABLE: channel complementary disable +>>>>>>> origin/main \param[out] none \retval none */ @@ -1235,10 +1363,17 @@ void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) } /*! +<<<<<<< HEAD + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: +======= \brief configure TIMER input capture parameter \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: +>>>>>>> origin/main \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) @@ -1274,7 +1409,11 @@ void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_i /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; break; +<<<<<<< HEAD + +======= +>>>>>>> origin/main /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ @@ -1426,7 +1565,11 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16 } /*! +<<<<<<< HEAD \brief configure TIMER input pwm capture function +======= + \brief configure TIMER input pwm capture function +>>>>>>> origin/main \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] channel: only one parameter can be selected which is shown as below: @@ -1547,19 +1690,31 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim \param[out] none \retval none */ +<<<<<<< HEAD +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +======= void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +>>>>>>> origin/main { if(TIMER_HALLINTERFACE_ENABLE == hallmode){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; }else{ +<<<<<<< HEAD /* illegal parameters */ +======= + /* illegal parameters */ +>>>>>>> origin/main } } /*! +<<<<<<< HEAD + \brief select TIMER input trigger source +======= \brief select TIMER input trigger source +>>>>>>> origin/main \param[in] timer_periph: please refer to the following parameters \param[in] intrigger: only one parameter can be selected which is shown as below: @@ -1581,10 +1736,17 @@ void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger } /*! +<<<<<<< HEAD + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] outrigger: + only one parameter can be selected which is shown as below: +======= \brief select TIMER master mode output trigger source \param[in] timer_periph: TIMERx(x=0..7) \param[in] outrigger: only one parameter can be selected which is shown as below: +>>>>>>> origin/main \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7)) \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7)) \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7)) @@ -1603,7 +1765,11 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o } /*! +<<<<<<< HEAD \brief select TIMER slave mode +======= + \brief select TIMER slave mode +>>>>>>> origin/main \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] slavemode: only one parameter can be selected which is shown as below: @@ -1627,7 +1793,11 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) } /*! +<<<<<<< HEAD + \brief configure TIMER master slave mode +======= \brief configure TIMER master slave mode +>>>>>>> origin/main \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] masterslave: only one parameter can be selected which is shown as below: @@ -1635,7 +1805,11 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable \param[out] none \retval none +<<<<<<< HEAD +*/ +======= */ +>>>>>>> origin/main void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) { if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ @@ -1643,7 +1817,11 @@ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; }else{ +<<<<<<< HEAD /* illegal parameters */ +======= + /* illegal parameters */ +>>>>>>> origin/main } } @@ -1718,7 +1896,11 @@ void timer_internal_clock_config(uint32_t timer_periph) /*! \brief configure TIMER the internal trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) +<<<<<<< HEAD + \param[in] intrigger: +======= \param[in] intrigger: +>>>>>>> origin/main only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 @@ -1832,7 +2014,11 @@ void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extpresca \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 \param[in] extpolarity: +<<<<<<< HEAD only one parameter can be selected which is shown as below: +======= + only one parameter can be selected which is shown as below: +>>>>>>> origin/main \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active \param[in] extfilter: a value between 0 and 15 @@ -1859,7 +2045,11 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) /*! \brief enable the TIMER interrupt +<<<<<<< HEAD + \param[in] timer_periph: please refer to the following parameters +======= \param[in] timer_periph: please refer to the following parameters +>>>>>>> origin/main \param[in] interrupt: timer interrupt enable source only one parameter can be selected which is shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) @@ -1875,7 +2065,11 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) */ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) { +<<<<<<< HEAD + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +======= TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +>>>>>>> origin/main } /*! @@ -1896,7 +2090,11 @@ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) */ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) { +<<<<<<< HEAD TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +======= + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +>>>>>>> origin/main } /*! @@ -1909,7 +2107,11 @@ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) +<<<<<<< HEAD + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) +======= \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) +>>>>>>> origin/main \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none @@ -1936,7 +2138,11 @@ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) +<<<<<<< HEAD \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) +======= + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) +>>>>>>> origin/main \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none @@ -1957,8 +2163,13 @@ void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) +<<<<<<< HEAD + \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) +======= \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) +>>>>>>> origin/main \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) @@ -1986,8 +2197,13 @@ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) +<<<<<<< HEAD + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) +======= \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) +>>>>>>> origin/main \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) diff --git a/external/base/soc/gd32f10x/drivers/src/gd32f10x_usart.c b/external/base/soc/gd32f10x/drivers/src/gd32f10x_usart.c index c8fd700..c063bfc 100644 --- a/external/base/soc/gd32f10x/drivers/src/gd32f10x_usart.c +++ b/external/base/soc/gd32f10x/drivers/src/gd32f10x_usart.c @@ -11,6 +11,7 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. +<<<<<<< HEAD Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -32,6 +33,29 @@ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +======= + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +>>>>>>> origin/main OF SUCH DAMAGE. */ @@ -41,7 +65,11 @@ OF SUCH DAMAGE. #define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ /*! +<<<<<<< HEAD + \brief reset USART/UART +======= \brief reset USART/UART +>>>>>>> origin/main \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none @@ -85,7 +113,11 @@ void usart_deinit(uint32_t usart_periph) \param[in] baudval: baud rate value \param[out] none \retval none +<<<<<<< HEAD +*/ +======= */ +>>>>>>> origin/main void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) { uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; @@ -110,7 +142,11 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) case UART4: /* get UART4 clock */ uclk=rcu_clock_freq_get(CK_APB1); +<<<<<<< HEAD break; +======= + break; +>>>>>>> origin/main default: break; } @@ -128,7 +164,11 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) only one parameter can be selected which is shown as below: \arg USART_PM_NONE: no parity \arg USART_PM_ODD: odd parity +<<<<<<< HEAD + \arg USART_PM_EVEN: even parity +======= \arg USART_PM_EVEN: even parity +>>>>>>> origin/main \param[out] none \retval none */ @@ -173,7 +213,11 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) { /* clear USART_CTL1 STB bits */ +<<<<<<< HEAD + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; +======= USART_CTL1(usart_periph) &= ~USART_CTL1_STB; +>>>>>>> origin/main /* configure USART stop bits */ USART_CTL1(usart_periph) |= stblen; } @@ -212,7 +256,11 @@ void usart_disable(uint32_t usart_periph) void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) { uint32_t ctl = 0U; +<<<<<<< HEAD +======= + +>>>>>>> origin/main ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_TEN; ctl |= txconfig; @@ -233,7 +281,11 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) { uint32_t ctl = 0U; +<<<<<<< HEAD + +======= +>>>>>>> origin/main ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_REN; ctl |= rxconfig; @@ -244,7 +296,11 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) /*! \brief USART transmit data function \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) +<<<<<<< HEAD \param[in] data: data of transmission +======= + \param[in] data: data of transmission +>>>>>>> origin/main \param[out] none \retval none */ @@ -322,7 +378,11 @@ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) \retval none */ void usart_lin_mode_enable(uint32_t usart_periph) +<<<<<<< HEAD +{ +======= { +>>>>>>> origin/main USART_CTL1(usart_periph) |= USART_CTL1_LMEN; } @@ -333,7 +393,11 @@ void usart_lin_mode_enable(uint32_t usart_periph) \retval none */ void usart_lin_mode_disable(uint32_t usart_periph) +<<<<<<< HEAD { +======= +{ +>>>>>>> origin/main USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); } @@ -371,7 +435,11 @@ void usart_send_break(uint32_t usart_periph) \retval none */ void usart_halfduplex_enable(uint32_t usart_periph) +<<<<<<< HEAD +{ +======= { +>>>>>>> origin/main USART_CTL2(usart_periph) |= USART_CTL2_HDEN; } @@ -382,7 +450,11 @@ void usart_halfduplex_enable(uint32_t usart_periph) \retval none */ void usart_halfduplex_disable(uint32_t usart_periph) +<<<<<<< HEAD +{ +======= { +>>>>>>> origin/main USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); } @@ -413,6 +485,17 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) \param[in] usart_periph: USARTx(x=0,1,2) \param[in] clen: CK length only one parameter can be selected which is shown as below: +<<<<<<< HEAD + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin +======= \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame \param[in] cph: clock phase @@ -422,6 +505,7 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) \param[in] cpl: clock polarity only one parameter can be selected which is shown as below: \arg USART_CPL_LOW: steady low value on CK pin +>>>>>>> origin/main \arg USART_CPL_HIGH: steady high value on CK pin \param[out] none \retval none @@ -610,6 +694,7 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig) \param[in] flag: USART flags, refer to usart_flag_enum only one parameter can be selected which is shown as below: \arg USART_FLAG_CTSF: CTS change flag +<<<<<<< HEAD \arg USART_FLAG_LBDF: LIN break detected flag \arg USART_FLAG_TBE: transmit data buffer empty \arg USART_FLAG_TC: transmission complete @@ -619,6 +704,17 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig) \arg USART_FLAG_NERR: noise error flag \arg USART_FLAG_FERR: frame error flag \arg USART_FLAG_PERR: parity error flag +======= + \arg USART_FLAG_LBDF: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLEF: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag +>>>>>>> origin/main \param[out] none \retval FlagStatus: SET or RESET */ @@ -720,7 +816,11 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) if(flagstatus && intenable){ return SET; }else{ +<<<<<<< HEAD + return RESET; +======= return RESET; +>>>>>>> origin/main } } diff --git a/external/base/soc/gd32vf103/openocd/gd32vf103.cfg b/external/base/soc/gd32vf103/openocd/gd32vf103.cfg new file mode 100644 index 0000000..d41f7c9 --- /dev/null +++ b/external/base/soc/gd32vf103/openocd/gd32vf103.cfg @@ -0,0 +1,99 @@ +adapter speed 1000 +transport select jtag + +reset_config srst_nogate + +set _CHIPNAME gd32vf103 +# The vendor's configuration expects an ID of 0x1e200a6d, but this one is what +# I have on my board (Sipeed Longan Nano, GD32VF103CBT6). +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME riscv set_enable_virt2phys off + +proc default_mem_access {} { + riscv set_mem_access progbuf +} + +default_mem_access + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x1000 -work-area-backup 1 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + +# Address 0 is only aliased to main flash when the chip is not running its +# built-in bootloader. When it is, it's instead aliased to a read only section +# of flash at 0x1fffb000. However, we can't detect or dynamically switch this, +# so just pretend it's always aliased to main flash. We need to tell OpenOCD +# about this alias because otherwise we'll try to use software breakpoints on +# code in flash, which don't work because flash mappings are read-only. +flash bank $_CHIPNAME.flashalias virtual 0x0 0 0 0 $_TARGETNAME $_FLASHNAME + +# On this chip, ndmreset (the debug module bit that triggers a software reset) +# doesn't work. So for JTAG connections without an SRST, we need to trigger a +# reset manually. This is an undocumented reset sequence that's used by the +# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin: +# +# https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2 +# +$_TARGETNAME configure -event reset-assert { + set dmcontrol 0x10 + set dmcontrol_dmactive [expr {1 << 0}] + set dmcontrol_haltreq [expr {1 << 31}] + + global _RESETMODE + global _TARGETNAME + + # Halt the core so that we can write to memory. We do this first so + # that it doesn't clobber our dmcontrol configuration. + halt + + # Set haltreq appropriately for the type of reset we're doing. This + # replicates what the generic RISC-V reset_assert() function would + # do if we weren't overriding it. The $_RESETMODE hack sucks, but + # it's the least invasive way to determine whether we need to halt, + # and psoc6.cfg already uses the same trick. (reset_deassert(), which + # does run, also does this, but at that point it may be too late: the + # reset has already been triggered, so there's a race between it and + # the haltreq write.) + # + # If we didn't override the generic handler, we'd actually still have + # to do this: the default handler sets ndmreset, which prevents memory + # access even though it doesn't actually trigger a reset on this chip. + # So we'd need to unset it here, which involves a write to dmcontrol, + # Since haltreq is write-only and there's no way to leave it unchanged, + # we'd have to figure out its proper value anyway. + set val $dmcontrol_dmactive + if {$_RESETMODE ne "run"} { + set val [expr {$val | $dmcontrol_haltreq}] + } + $_TARGETNAME riscv dmi_write $dmcontrol $val + + # Unlock 0xe0042008 so that the next write triggers a reset + $_TARGETNAME mww 0xe004200c 0x4b5a6978 + + # We need to trigger the reset using abstract memory access, since + # progbuf access tries to read a status code out of a core register + # after the write happens, which fails when the core is in reset. + riscv set_mem_access abstract + + # Go! + $_TARGETNAME mww 0xe0042008 0x1 + + # Put the memory access mode back to what it was. + default_mem_access +} + +# Capture the mode of a given reset so that we can use it later in the +# reset-assert handler. +proc init_reset { mode } { + global _RESETMODE + set _RESETMODE $mode + + if {[using_jtag]} { + jtag arp_init-reset + } +} diff --git a/module/base/makefile b/module/base/makefile index a9050d1..9f6bd7d 100644 --- a/module/base/makefile +++ b/module/base/makefile @@ -269,6 +269,8 @@ DEFINES += $(call convert_defines, $(BOARD) $(SOC) $(MCU) $(CPU) $(ARCH) $(RTOS) TARGET_NAME ?= $(BIN_DIR)/$(PROJECT_NAME) TARGET_ELF = $(TARGET_NAME).$(LD_EXTENSION) +-include $(patsubst %.o,%.d,$(PROJECT_OBJ)) + ################################################################################################## # PROJECT_OBJ += $(call objects_list,$(PROJECT_SRC),c) diff --git a/module/base/mcu/gd32vf103cbt6/makefile b/module/base/mcu/gd32vf103cbt6/makefile index 8f95c10..5d93c34 100644 --- a/module/base/mcu/gd32vf103cbt6/makefile +++ b/module/base/mcu/gd32vf103cbt6/makefile @@ -31,6 +31,4 @@ DEFINES += HXTAL_VALUE=8000000U LINKSCRIPT = external/base/mcu/$(MCU)/linker/release.ld # Flash commandfor OpenOCD download target -FLASH_WRITER_COMMANDS = -c "init" -c "reset halt" -c "flash protect 0 0 last off" -FLASH_WRITER_COMMANDS += -c "program $(TARGET_ELF) verify;" -FLASH_WRITER_COMMANDS += -c "reset run; exit 0;" +FLASH_WRITER_COMMANDS = -c "program $(TARGET_ELF) verify reset exit" diff --git a/module/base/soc/gd32vf103/makefile b/module/base/soc/gd32vf103/makefile index 75dd788..5b9557a 100644 --- a/module/base/soc/gd32vf103/makefile +++ b/module/base/soc/gd32vf103/makefile @@ -59,8 +59,8 @@ DAP ?= ftdi/um232h # Command flags for gdb server GDB_SERVER_FLAGS += $(if $(USB_LOCATION), -c "adapter usb location $(USB_LOCATION)") -GDB_SERVER_FLAGS += -f interface/$(DAP).cfg -f target/gd32vf103.cfg +GDB_SERVER_FLAGS += -f interface/$(DAP).cfg -f $(MUJU)/$(SOC_FOLDER)/openocd/gd32vf103.cfg # Command flags for download target FLASH_WRITER_FLAGS += $(if $(USB_LOCATION), -c "adapter usb location $(USB_LOCATION)") -FLASH_WRITER_FLAGS += -f interface/$(DAP).cfg -f target/gd32vf103.cfg +FLASH_WRITER_FLAGS += -f interface/$(DAP).cfg -f $(MUJU)/$(SOC_FOLDER)/openocd/gd32vf103.cfg