From 95aec9f0d63406272ae3b6b2b8e22250be4c7ec2 Mon Sep 17 00:00:00 2001
From: John Archie <jarchie@jarchie.com>
Date: Sun, 7 Sep 2014 11:23:06 -0700
Subject: [PATCH 1/2] Replaced deprecated interrupt names

All deprecated interrupt names have been replaced by their
current equivalents:

    SIG_OVERFLOW0   -> TIMER0_OVF_vect
    SIG_PIN_CHANGE2 -> PCINT2_vect
    SIG_PIN_CHANGE0 -> PCINT0_vect
    SIG_INTERRUPT0  -> INT0_vect
    SIG_COMPARATOR  -> ANALOG_COMP_vect

The code no longer generates compile errors on recent versions of GCC.
(Tested on avr-gcc 4.8.2.)
---
 iv.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/iv.c b/iv.c
index 34774ea..fe8b53c 100644
--- a/iv.c
+++ b/iv.c
@@ -573,7 +573,7 @@ static void flip_display(transition_t* trans)
 }
 
 // called @ (F_CPU/256) = ~30khz (31.25 khz)
-SIGNAL (SIG_OVERFLOW0) {
+SIGNAL (TIMER0_OVF_vect) {
   // allow other interrupts to go off while we're doing display updates
   sei();
 
@@ -628,13 +628,13 @@ SIGNAL (SIG_OVERFLOW0) {
 // We use the pin change interrupts to detect when buttons are pressed
 
 // This interrupt detects switches 1 and 3
-SIGNAL(SIG_PIN_CHANGE2) {
+SIGNAL(PCINT2_vect) {
   button_change_intr(0, !(PIND & _BV(BUTTON1)));
   button_change_intr(2, !(PIND & _BV(BUTTON3)));
 }
 
 // Just button #2
-SIGNAL(SIG_PIN_CHANGE0) {
+SIGNAL(PCINT0_vect) {
   button_change_intr(1, !(PINB & _BV(BUTTON2)));
 }
 
@@ -813,7 +813,7 @@ SIGNAL (TIMER2_COMPA_vect) {
 }
 
 //Alarm Switch
-SIGNAL(SIG_INTERRUPT0) {  
+SIGNAL(INT0_vect) {  
   uint8_t state;
 
   state = (ALARM_PIN & _BV(ALARM));
@@ -825,7 +825,7 @@ SIGNAL(SIG_INTERRUPT0) {
 }
 
 
-SIGNAL(SIG_COMPARATOR) {
+SIGNAL(ANALOG_COMP_vect) {
   //DEBUGP("COMP");
   if (ACSR & _BV(ACO)) {
     //DEBUGP("HIGH");

From 2d841a42c88fd985c20437fa9f617d514d589a60 Mon Sep 17 00:00:00 2001
From: John Archie <jarchie@jarchie.com>
Date: Sun, 7 Sep 2014 14:23:05 -0700
Subject: [PATCH 2/2] Multiple sleep-related bugfixes

This commit includes four sleep-related bugfixes.  Together, these
changes should ensure more reliable sleep behavior.

The code now uses a 2 MHz clock speed during sleep--fast enough for
reliable asynchronous timer (timer2) operation, but slow enough for
oscillator stability at 1.7 volts, the lowest possible voltage ensured
by the BOD settings.

Timer2 is now initialized only if not already initialized.  This
prevents time loss due to the unnecessary reinitializations after
calls to app_start().

The sleep code now ensures that all asynchronous timer settings are
latched before sleeping to ensure reliable waking via the once-per-
second time keeping interrupt.

The once-per-second interrupt must not exit before a full crystal
oscillation, so OCR2B--an unused timer2 register--is written at the
beginning of the interrupt routine.  The value of OCR2B is latched
after two positive edges from the crystal oscillator, and since the
system will not sleep until all asynchronous timer (timer2) registers
are latched, the system will not sleep until the necessary time has
passed.
---
 iv.c | 42 +++++++++++++++++++++++++++++++-----------
 1 file changed, 31 insertions(+), 11 deletions(-)

diff --git a/iv.c b/iv.c
index fe8b53c..86930c1 100644
--- a/iv.c
+++ b/iv.c
@@ -126,6 +126,10 @@ static uint16_t snoozetimer = 0;
  */
 static inline void sleep(void)
 {
+  // ensure all timer2 registers are written before sleeping
+  while(ASSR & (_BV(TCN2UB) | _BV(OCR2AUB) | _BV(OCR2BUB) |
+	        _BV(TCR2AUB) | _BV(TCR2BUB) ));
+
   asm volatile("sei $ sleep" : : : "memory");
 }
 
@@ -768,8 +772,20 @@ static void set_brite(void)
  */
 SIGNAL (TIMER2_COMPA_vect) {
   struct timedate td;
-  CLKPR = _BV(CLKPCE);  //MEME
-  CLKPR = 0;
+
+  // write to unused timer2 register:  the sleep code will ensure this value
+  // gets written before going to sleep--something that requires one full
+  // quartz crystal clock cycle.  This is important because this interrupt
+  // must take at least one full quartz crystal cycle for reliable sleep.
+  OCR2B = 0;
+
+  // for reliable low-voltage operation during sleep (1.7-3.0v), clock
+  // must not be set above 2 MHz; so only increase clock speed if powered
+  // by external adapter
+  if (!(ACSR & _BV(ACO))) {
+    CLKPR = _BV(CLKPCE);  // MEME
+    CLKPR = 0;
+  }
 
   td = timedate;
 
@@ -1644,15 +1660,17 @@ static void clock_init(void)
    * correction.
    */
   // Turn on the RTC by selecting the external 32khz crystal
-  ASSR = _BV(AS2); // use crystal
+  if(! TCCR2A) {  // only configure crystal if not already configured
+    ASSR = _BV(AS2); // use crystal
 
-  TCNT2 = 0;
-  OCR2A = DRIFT_BASELINE;		/* +/- drift correction */
-  TCCR2A = _BV(WGM21);
-  TCCR2B = _BV(CS22) | _BV(CS21);
+    TCNT2 = 0;
+    OCR2A = DRIFT_BASELINE;		/* +/- drift correction */
+    TCCR2A = _BV(WGM21);
+    TCCR2B = _BV(CS22) | _BV(CS21);
 
-  // enable interrupt
-  TIMSK2 = _BV(OCIE1A);
+    // enable interrupt
+    TIMSK2 = _BV(OCIE1A);
+  }
 
   // enable all interrupts!
   sei();
@@ -1689,9 +1707,11 @@ void gotosleep(void) {
   ALARM_DDR &= ~_BV(ALARM);
   
 
-  // reduce the clock speed
+  // reduce the clock speed; division by four
+  // the original firmware divides by 256, but the resultant system clock
+  // speed is too slow for reliable asynchronous timer (timer2) operation
   CLKPR = _BV(CLKPCE);
-  CLKPR = _BV(CLKPS3);
+  CLKPR = _BV(CLKPS1);
 
   SMCR = _BV(SM1) | _BV(SM0) | _BV(SE); // power-save mode