diff --git a/xml/PTL/0/ptl_aggregator.xml b/xml/PTL/0/ptl_aggregator.xml new file mode 100644 index 0000000..d3fe9f5 --- /dev/null +++ b/xml/PTL/0/ptl_aggregator.xml @@ -0,0 +1,6933 @@ + +]> + + + &otherfile; + ptl + PTL normal telemetry in Punit + 0x03086000 + ptl + 0 + + + Groupname 0x82e8 + 64 + + Local Revision ID for this product (revision of the xml) + GLOBAL_ID + Snapshot + 8 + 0 + 7 + + + '1' for fixed block telemetry ID, '0' for rest. Default is '0' + GLOBAL_ID + Snapshot + 1 + 8 + 8 + + + reserved + GLOBAL_ID + Snapshot + 3 + 9 + 11 + + + Product ID= 22 | TGLUY= 23 | TGLH= 24 | TGLS= 79 | ADL-P= 80 | ADL-S= 90 | RPL= 91 | RPL-P= 92 | RPL-S= 103 | MTL-M= 104 | MTL-P= 105 | MTL-S= 106 | ARL= 114 | LNL-M= 134 | PTL-P= 135 | PTL-H= 141 | WCL-U + GLOBAL_ID + Snapshot + 12 + 12 + 23 + + + source id for data provider + GLOBAL_ID + Snapshot + 6 + 24 + 29 + + + reserved + GLOBAL_ID + Snapshot + 2 + 30 + 31 + + + Represents the clock rate of the XTAL on this silicon.= 0 | 24MHz= 1 | 19.2MHz= 2 | 38.4MHz= 3 | 25MHz + STRAPS + Snapshot + 2 + 32 + 33 + + + reserved + STRAPS + Snapshot + 30 + 34 + 63 + + + + Groupname 0x82f0 + 64 + + reserved + SMPL_RESERVED0 + Snapshot + 8 + 0 + 7 + + + reserved + SMPL_RESERVED0 + Snapshot + 8 + 8 + 15 + + + reserved + SMPL_RESERVED0 + Snapshot + 8 + 16 + 23 + + + reserved + SMPL_RESERVED0 + Snapshot + 8 + 24 + 31 + + + reserved + SMPL_RESERVED0 + Snapshot + 8 + 32 + 39 + + + reserved + SMPL_RESERVED0 + Snapshot + 8 + 40 + 47 + + + reserved + SMPL_RESERVED0 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x82f8 + 64 + + reserved + SMPL_RESERVED_1 + Snapshot + 8 + 0 + 7 + + + reserved + SMPL_RESERVED_1 + Snapshot + 8 + 8 + 15 + + + reserved + SMPL_RESERVED_1 + Snapshot + 10 + 16 + 25 + + + reserved + SMPL_RESERVED_1 + Snapshot + 8 + 26 + 33 + + + reserved + SMPL_RESERVED_1 + Snapshot + 8 + 34 + 41 + + + reserved + SMPL_RESERVED_1 + Snapshot + 8 + 42 + 49 + + + reserved + SMPL_RESERVED_1 + Snapshot + 8 + 50 + 57 + + + reserved + SMPL_RESERVED_1 + Snapshot + 6 + 58 + 63 + + + + Groupname 0x8300 + 64 + + reserved + SMPL_RESERVED_2 + Snapshot + 8 + 0 + 7 + + + reserved + SMPL_RESERVED_2 + Snapshot + 8 + 8 + 15 + + + reserved + SMPL_RESERVED_2 + Snapshot + 8 + 16 + 23 + + + reserved + SMPL_RESERVED_2 + Snapshot + 8 + 24 + 31 + + + reserved + SMPL_RESERVED_3 + Snapshot + 8 + 32 + 39 + + + reserved + SMPL_RESERVED_3 + Snapshot + 8 + 40 + 47 + + + reserved + SMPL_RESERVED_3 + Snapshot + 8 + 48 + 55 + + + reserved + SMPL_RESERVED_3 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8308 + 64 + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8308 + Snapshot + 11 + 0 + 10 + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8308 + Snapshot + 10 + 11 + 20 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8308 + Snapshot + 3 + 21 + 23 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8308 + Snapshot + 8 + 24 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8308_1 + Snapshot + 11 + 32 + 42 + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + HW_SAMPLE_MMIO_OFFSET_8308_1 + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8308_1 + Snapshot + 3 + 53 + 55 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8308_1 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8310 + 64 + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8310 + Snapshot + 11 + 0 + 10 + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + HW_SAMPLE_MMIO_OFFSET_8310 + Snapshot + 10 + 11 + 20 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8310 + Snapshot + 3 + 21 + 23 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8310 + Snapshot + 8 + 24 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8310_1 + Snapshot + 11 + 32 + 42 + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + HW_SAMPLE_MMIO_OFFSET_8310_1 + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8310_1 + Snapshot + 3 + 53 + 55 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8310_1 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8318 + 64 + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8318 + Snapshot + 11 + 0 + 10 + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + HW_SAMPLE_MMIO_OFFSET_8318 + Snapshot + 10 + 11 + 20 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8318 + Snapshot + 3 + 21 + 23 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8318 + Snapshot + 8 + 24 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8318_1 + Snapshot + 11 + 32 + 42 + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + HW_SAMPLE_MMIO_OFFSET_8318_1 + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8318_1 + Snapshot + 3 + 53 + 55 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8318_1 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8320 + 64 + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8320 + Snapshot + 11 + 0 + 10 + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + HW_SAMPLE_MMIO_OFFSET_8320 + Snapshot + 10 + 11 + 20 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8320 + Snapshot + 3 + 21 + 23 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8320 + Snapshot + 8 + 24 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8320_1 + Snapshot + 11 + 32 + 42 + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + HW_SAMPLE_MMIO_OFFSET_8320_1 + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + HW_SAMPLE_MMIO_OFFSET_8320_1 + Snapshot + 3 + 53 + 55 + + + IA Module clock ratio, in units of 100MHz. + HW_SAMPLE_MMIO_OFFSET_8320_1 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8328 + 64 + + reserved + RSVD_8328 + Snapshot + 32 + 0 + 31 + + + reserved + SMPL_RESERVED15 + Snapshot + 11 + 32 + 42 + + + reserved + SMPL_RESERVED15 + Snapshot + 10 + 43 + 52 + + + reserved + SMPL_RESERVED15 + Snapshot + 3 + 53 + 55 + + + reserved + SMPL_RESERVED15 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8330 + 64 + + reserved + SMPL_RESERVED16 + Snapshot + 1 + 0 + 0 + + + reserved + SMPL_RESERVED16 + Snapshot + 1 + 1 + 1 + + + reserved + SMPL_RESERVED16 + Snapshot + 8 + 2 + 9 + + + reserved + SMPL_RESERVED16 + Snapshot + 3 + 10 + 12 + + + reserved + SMPL_RESERVED16 + Snapshot + 5 + 13 + 17 + + + reserved + SMPL_RESERVED16 + Snapshot + 4 + 18 + 21 + + + reserved + SMPL_RESERVED16 + Snapshot + 10 + 22 + 31 + + + reserved + SMPL_RESERVED17 + Snapshot + 1 + 32 + 32 + + + reserved + SMPL_RESERVED17 + Snapshot + 3 + 33 + 35 + + + reserved + SMPL_RESERVED17 + Snapshot + 28 + 36 + 63 + + + + Groupname 0x8338 + 64 + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_0_1 + Snapshot + 8 + 0 + 7 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_0_1 + Snapshot + 3 + 8 + 10 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 11 + 11 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 12 + 12 + + + reserved + SVID_WORKPOINT_0_1 + Snapshot + 3 + 13 + 15 + + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_0_1 + Snapshot + 8 + 16 + 23 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_0_1 + Snapshot + 3 + 24 + 26 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 27 + 27 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 28 + 28 + + + reserved + SVID_WORKPOINT_0_1 + Snapshot + 3 + 29 + 31 + + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_2_3 + Snapshot + 8 + 32 + 39 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_2_3 + Snapshot + 3 + 40 + 42 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 43 + 43 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 44 + 44 + + + reserved + SVID_WORKPOINT_2_3 + Snapshot + 3 + 45 + 47 + + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_2_3 + Snapshot + 8 + 48 + 55 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_2_3 + Snapshot + 3 + 56 + 58 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 59 + 59 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 60 + 60 + + + reserved + SVID_WORKPOINT_2_3 + Snapshot + 3 + 61 + 63 + + + + Groupname 0x8340 + 64 + + reserved + RSVD_8340 + Snapshot + 32 + 0 + 31 + + + last SVID0 VR current reading - translated IMON version for VCCIA, in amps. U16.8.8 + SVID_ICC_0_1 + Snapshot + 16 + 32 + 47 + + + last SVID1 VR current reading - translated IMON version for VCCGT, in amps. U16.8.8 + SVID_ICC_0_1 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8348 + 64 + + last SVID2 VR current reading - translated IMON version for VCCSA, in amps. U16.8.8 + SVID_ICC_2_3 + Snapshot + 16 + 0 + 15 + + + last SVID3 VR current reading - translated IMON version for VCCATOM, in amps. U16.8.8 + SVID_ICC_2_3 + Snapshot + 16 + 16 + 31 + + + reserved + RSVD_834C + Snapshot + 32 + 32 + 63 + + + + Groupname 0x8350 + 64 + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 0 + 2 + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 3 + 5 + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 6 + 8 + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 9 + 11 + + + IA Core C-state of Atom core 00: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 12 + 14 + + + IA Core C-state of Atom core 10: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 15 + 17 + + + IA Core C-state of Atom core 20: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 18 + 20 + + + LLC/Ring C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + IA_CLUSTER_CSTATES + Snapshot + 3 + 24 + 26 + + + Iceland cluster C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + IA_CLUSTER_CSTATES + Snapshot + 3 + 27 + 29 + + + GT RC-state0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 30 + 32 + + + reserved + IA_CLUSTER_CSTATES + Snapshot + 31 + 33 + 63 + + + + Groupname 0x8358 + 64 + + CDYN level granted that CORE0 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 0 + 3 + + + CDYN level granted that CORE1 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 4 + 7 + + + CDYN level granted that CORE2 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 8 + 11 + + + CDYN level granted that CORE3 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 12 + 15 + + + CDYN level granted that Atom module0 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 16 + 19 + + + CDYN level granted that Atom module1 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 20 + 23 + + + CDYN level granted that Atom module2 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 24 + 27 + + + reserved + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 4 + 28 + 31 + + + reserved + HW_SAMPLE_MMIO_OFFSET_8358 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x8360 + 64 + + Current PCH temperature + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 0 + 7 + + + Current reading from System Agent "always on" temperature sensor + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 8 + 15 + + + Current reading from IPU subsystem temperature sensor + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 16 + 23 + + + Current reading from Display subsystem temperature sensor + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 24 + 31 + + + Current reading from VPU subsystem temperature sensor + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 32 + 39 + + + Current reading from Media subsystem temperature sensor + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 40 + 47 + + + Graphics Min temp + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 48 + 55 + + + Graphics Max temp + HW_SAMPLE_MMIO_OFFSET_8360 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8368 + 64 + + Min temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 0 + 7 + + + Max temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 8 + 15 + + + Min temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 16 + 23 + + + Max temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 24 + 31 + + + Min temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 32 + 39 + + + Max temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 40 + 47 + + + Min temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 48 + 55 + + + Max temp across the core + HW_SAMPLE_MMIO_OFFSET_8368 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8370 + 64 + + Min temp across the atom module + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 0 + 7 + + + Max temp across the atom module + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 8 + 15 + + + Min temp across the atom module + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 16 + 23 + + + Max temp across the atom module + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 24 + 31 + + + Min temp across the atom module + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 32 + 39 + + + Max temp across the atom module + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 40 + 47 + + + LLC Min temp + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 48 + 55 + + + LLC Max temp + HW_SAMPLE_MMIO_OFFSET_8370 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8378 + 64 + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8378 + Snapshot + 16 + 0 + 15 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8378 + Snapshot + 16 + 16 + 31 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8378 + Snapshot + 16 + 32 + 47 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8378 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8380 + 64 + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8380 + Snapshot + 16 + 0 + 15 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8380 + Snapshot + 16 + 16 + 31 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8380 + Snapshot + 16 + 32 + 47 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8380 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8388 + 64 + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8388 + Snapshot + 16 + 0 + 15 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8388 + Snapshot + 16 + 16 + 31 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8388 + Snapshot + 16 + 32 + 47 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8388 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8390 + 64 + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8390 + Snapshot + 16 + 0 + 15 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8390 + Snapshot + 16 + 16 + 31 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8390 + Snapshot + 16 + 32 + 47 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + HW_SAMPLE_MMIO_OFFSET_8390 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8398 + 64 + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 0 + 7 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 8 + 15 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 16 + 23 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 24 + 31 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 32 + 39 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 40 + 47 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 48 + 55 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x83a0 + 64 + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE8_11 + Snapshot + 8 + 0 + 7 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE8_11 + Snapshot + 8 + 8 + 15 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE8_11 + Snapshot + 8 + 16 + 23 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE8_11 + Snapshot + 8 + 24 + 31 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE12_15 + Snapshot + 8 + 32 + 39 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE12_15 + Snapshot + 8 + 40 + 47 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE12_15 + Snapshot + 8 + 48 + 55 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE12_15 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x83a8 + 64 + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8 + Snapshot + 8 + 0 + 7 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8 + Snapshot + 8 + 8 + 15 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8 + Snapshot + 8 + 16 + 23 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8 + Snapshot + 8 + 24 + 31 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8_1 + Snapshot + 8 + 32 + 39 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8_1 + Snapshot + 8 + 40 + 47 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8_1 + Snapshot + 8 + 48 + 55 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83A8_1 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x83b0 + 64 + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0 + Snapshot + 8 + 0 + 7 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0 + Snapshot + 8 + 8 + 15 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0 + Snapshot + 8 + 16 + 23 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0 + Snapshot + 8 + 24 + 31 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0_1 + Snapshot + 8 + 32 + 39 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0_1 + Snapshot + 8 + 40 + 47 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0_1 + Snapshot + 8 + 48 + 55 + + + Current autonomous frequency target for that IA Core + HW_SAMPLE_MMIO_OFFSET_83B0_1 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x83b8 + 64 + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 0 + 7 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 8 + 15 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 16 + 23 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 24 + 31 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 32 + 39 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 40 + 47 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 48 + 55 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x83c0 + 64 + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE8_11 + Snapshot + 8 + 0 + 7 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE8_11 + Snapshot + 8 + 8 + 15 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE8_11 + Snapshot + 8 + 16 + 23 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE8_11 + Snapshot + 8 + 24 + 31 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE12_15 + Snapshot + 8 + 32 + 39 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE12_15 + Snapshot + 8 + 40 + 47 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE12_15 + Snapshot + 8 + 48 + 55 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE12_15 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x83c8 + 64 + + Current GT Efficient P-state (used as the floor for autonomous control) + GT_EFFICIENT_FREQUENCY + Snapshot + 8 + 0 + 7 + + + reserved + GT_EFFICIENT_FREQUENCY + Snapshot + 56 + 8 + 63 + + + + Groupname 0x83d0 + 64 + + Temperature of PECI sensor in 1/32 DegC + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 0 + 15 + + + Temperature of PECI sensor in 1/32 DegC + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 16 + 31 + + + Temperature of PECI sensor in 1/32 DegC + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 32 + 47 + + + reserved + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 48 + 63 + + + + Groupname 0x83d8 + 64 + + Contains EC settings for sensor 0. + PLATFORM_TEMPERATURE_EC_SETTINGS_0 + Snapshot + 32 + 0 + 31 + + + Contains EC settings for sensor 1. + PLATFORM_TEMPERATURE_EC_SETTINGS_0 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83e0 + 64 + + Contains EC settings for sensor 2. + PLATFORM_TEMPERATURE_EC_SETTINGS_1 + Snapshot + 32 + 0 + 31 + + + reserved + PLATFORM_TEMPERATURE_EC_SETTINGS_1 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83e8 + 64 + + Contains MMIO settings for sensor 0. + PLATFORM_TEMPERATURE_MMIO_SETTINGS_0 + Snapshot + 32 + 0 + 31 + + + Contains MMIO settings for sensor 1. + PLATFORM_TEMPERATURE_MMIO_SETTINGS_0 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83f0 + 64 + + Contains MMIO settings for sensor 2. + PLATFORM_TEMPERATURE_MMIO_SETTINGS_1 + Snapshot + 32 + 0 + 31 + + + reserved + PLATFORM_TEMPERATURE_MMIO_SETTINGS_1 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83f8 + 64 + + reserved + SMPL_RESERVED_0_83F8 + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8400 + 64 + + reserved + SMPL_RESERVED_1_to_64[0] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8408 + 64 + + reserved + SMPL_RESERVED_1_to_64[1] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8410 + 64 + + reserved + SMPL_RESERVED_1_to_64[2] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8418 + 64 + + reserved + SMPL_RESERVED_1_to_64[3] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8420 + 64 + + reserved + SMPL_RESERVED_1_to_64[4] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8428 + 64 + + reserved + SMPL_RESERVED_1_to_64[5] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8430 + 64 + + reserved + SMPL_RESERVED_1_to_64[6] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8438 + 64 + + reserved + SMPL_RESERVED_1_to_64[7] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8440 + 64 + + reserved + SMPL_RESERVED_1_to_64[8] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8448 + 64 + + reserved + SMPL_RESERVED_1_to_64[9] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8450 + 64 + + reserved + SMPL_RESERVED_1_to_64[10] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8458 + 64 + + reserved + SMPL_RESERVED_1_to_64[11] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8460 + 64 + + reserved + SMPL_RESERVED_1_to_64[12] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8468 + 64 + + reserved + SMPL_RESERVED_1_to_64[13] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8470 + 64 + + reserved + SMPL_RESERVED_1_to_64[14] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8478 + 64 + + reserved + SMPL_RESERVED_1_to_64[15] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8480 + 64 + + reserved + SMPL_RESERVED_1_to_64[16] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8488 + 64 + + reserved + SMPL_RESERVED_1_to_64[17] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8490 + 64 + + reserved + SMPL_RESERVED_1_to_64[18] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8498 + 64 + + reserved + SMPL_RESERVED_1_to_64[19] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84a0 + 64 + + reserved + SMPL_RESERVED_1_to_64[20] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84a8 + 64 + + reserved + SMPL_RESERVED_1_to_64[21] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84b0 + 64 + + reserved + SMPL_RESERVED_1_to_64[22] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84b8 + 64 + + reserved + SMPL_RESERVED_1_to_64[23] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84c0 + 64 + + reserved + SMPL_RESERVED_1_to_64[24] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84c8 + 64 + + reserved + SMPL_RESERVED_1_to_64[25] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84d0 + 64 + + reserved + SMPL_RESERVED_1_to_64[26] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84d8 + 64 + + reserved + SMPL_RESERVED_1_to_64[27] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84e0 + 64 + + reserved + SMPL_RESERVED_1_to_64[28] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84e8 + 64 + + reserved + SMPL_RESERVED_1_to_64[29] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84f0 + 64 + + reserved + SMPL_RESERVED_1_to_64[30] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84f8 + 64 + + reserved + SMPL_RESERVED_1_to_64[31] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8500 + 64 + + reserved + SMPL_RESERVED_1_to_64[32] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8508 + 64 + + reserved + SMPL_RESERVED_1_to_64[33] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8510 + 64 + + reserved + SMPL_RESERVED_1_to_64[34] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8518 + 64 + + reserved + SMPL_RESERVED_1_to_64[35] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8520 + 64 + + reserved + SMPL_RESERVED_1_to_64[36] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8528 + 64 + + reserved + SMPL_RESERVED_1_to_64[37] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8530 + 64 + + reserved + SMPL_RESERVED_1_to_64[38] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8538 + 64 + + reserved + SMPL_RESERVED_1_to_64[39] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8540 + 64 + + reserved + SMPL_RESERVED_1_to_64[40] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8548 + 64 + + reserved + SMPL_RESERVED_1_to_64[41] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8550 + 64 + + reserved + SMPL_RESERVED_1_to_64[42] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8558 + 64 + + reserved + SMPL_RESERVED_1_to_64[43] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8560 + 64 + + reserved + SMPL_RESERVED_1_to_64[44] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8568 + 64 + + reserved + SMPL_RESERVED_1_to_64[45] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8570 + 64 + + reserved + SMPL_RESERVED_1_to_64[46] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8578 + 64 + + reserved + SMPL_RESERVED_1_to_64[47] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8580 + 64 + + reserved + SMPL_RESERVED_1_to_64[48] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8588 + 64 + + reserved + SMPL_RESERVED_1_to_64[49] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8590 + 64 + + reserved + SMPL_RESERVED_1_to_64[50] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8598 + 64 + + reserved + SMPL_RESERVED_1_to_64[51] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85a0 + 64 + + reserved + SMPL_RESERVED_1_to_64[52] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85a8 + 64 + + reserved + SMPL_RESERVED_1_to_64[53] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85b0 + 64 + + reserved + SMPL_RESERVED_1_to_64[54] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85b8 + 64 + + reserved + SMPL_RESERVED_1_to_64[55] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85c0 + 64 + + reserved + SMPL_RESERVED_1_to_64[56] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85c8 + 64 + + reserved + SMPL_RESERVED_1_to_64[57] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85d0 + 64 + + reserved + SMPL_RESERVED_1_to_64[58] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85d8 + 64 + + reserved + SMPL_RESERVED_1_to_64[59] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85e0 + 64 + + reserved + SMPL_RESERVED_1_to_64[60] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85e8 + 64 + + reserved + SMPL_RESERVED_1_to_64[61] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85f0 + 64 + + reserved + SMPL_RESERVED_1_to_64[62] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85f8 + 64 + + reserved + SMPL_RESERVED_1_to_64[63] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8600 + 64 + + slow limit THERM has limited performance for CCP0 + PERF_LIMIT_THERM_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8608 + 64 + + slow limit THERM has limited performance for CCP1 + PERF_LIMIT_THERM_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8610 + 64 + + slow limit THERM has limited performance for CCP2 + PERF_LIMIT_THERM_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x8618 + 64 + + slow limit THERM has limited performance for CCP3 + PERF_LIMIT_THERM_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8620 + 64 + + slow limit THERM has limited performance for CCP4 + PERF_LIMIT_THERM_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8628 + 64 + + slow limit THERM has limited performance for CCP5 + PERF_LIMIT_THERM_CCP_RESIDENCY_5 + Counter + 64 + 0 + 63 + + + + Groupname 0x8630 + 64 + + slow limit THERM has limited performance for CCP6 + PERF_LIMIT_THERM_CCP_RESIDENCY_6 + Counter + 64 + 0 + 63 + + + + Groupname 0x8638 + 64 + + slow limit THERM has limited performance for CLR + PERF_LIMIT_THERM_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8640 + 64 + + slow limit THERM has limited performance for GT. + PERF_LIMIT_THERM_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8648 + 64 + + slow limit THERM has limited performance for IPU. + PERF_LIMIT_THERM_IPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8650 + 64 + + slow limit THERM has limited performance for VPU. + PERF_LIMIT_THERM_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8658 + 64 + + slow limit THERM has limited performance for Media. + PERF_LIMIT_THERM_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8660 + 64 + + slow limit POWER has limited performance for CCP0 + PERF_LIMIT_POWER_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8668 + 64 + + slow limit POWER has limited performance for CCP1 + PERF_LIMIT_POWER_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8670 + 64 + + slow limit POWER has limited performance for CCP2 + PERF_LIMIT_POWER_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x8678 + 64 + + slow limit POWER has limited performance for CCP3 + PERF_LIMIT_POWER_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8680 + 64 + + slow limit POWER has limited performance for CCP4 + PERF_LIMIT_POWER_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8688 + 64 + + slow limit POWER has limited performance for CCP5 + PERF_LIMIT_POWER_CCP_RESIDENCY_5 + Counter + 64 + 0 + 63 + + + + Groupname 0x8690 + 64 + + slow limit POWER has limited performance for CCP6 + PERF_LIMIT_POWER_CCP_RESIDENCY_6 + Counter + 64 + 0 + 63 + + + + Groupname 0x8698 + 64 + + slow limit POWER has limited performance for CLR + PERF_LIMIT_POWER_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86a0 + 64 + + slow limit POWER has limited performance for GT + PERF_LIMIT_POWER_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86a8 + 64 + + slow limit POWER has limited performance for Media + PERF_LIMIT_POWER_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86b0 + 64 + + slow limit POWER has limited performance for VPU + PERF_LIMIT_POWER_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86b8 + 64 + + slow limit EDP has limited performance for CCP0 + PERF_LIMIT_EDP_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x86c0 + 64 + + slow limit EDP has limited performance for CCP1 + PERF_LIMIT_EDP_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x86c8 + 64 + + slow limit EDP has limited performance for CCP2 + PERF_LIMIT_EDP_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x86d0 + 64 + + slow limit EDP has limited performance for CCP3 + PERF_LIMIT_EDP_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x86d8 + 64 + + slow limit EDP has limited performance for CCP4 + PERF_LIMIT_EDP_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x86e0 + 64 + + slow limit EDP has limited performance for CCP5 + PERF_LIMIT_EDP_CCP_RESIDENCY_5 + Counter + 64 + 0 + 63 + + + + Groupname 0x86e8 + 64 + + slow limit EDP has limited performance for CCP6 + PERF_LIMIT_EDP_CCP_RESIDENCY_6 + Counter + 64 + 0 + 63 + + + + Groupname 0x86f0 + 64 + + slow limit EDP has limited performance for CLR + PERF_LIMIT_EDP_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86f8 + 64 + + slow limit EDP has limited performance for GT + PERF_LIMIT_EDP_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8700 + 64 + + slow limit EDP has limited performance for Media + PERF_LIMIT_EDP_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8708 + 64 + + slow limit EDP has limited performance for VPU + PERF_LIMIT_EDP_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8710 + 64 + + slow limit OTHER has limited performance for CCP0 + PERF_LIMIT_OTHER_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8718 + 64 + + slow limit OTHER has limited performance for CCP1 + PERF_LIMIT_OTHER_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8720 + 64 + + slow limit OTHER has limited performance for CCP2 + PERF_LIMIT_OTHER_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x8728 + 64 + + slow limit OTHER has limited performance for CCP3 + PERF_LIMIT_OTHER_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8730 + 64 + + slow limit OTHER has limited performance for CCP4 + PERF_LIMIT_OTHER_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8738 + 64 + + slow limit OTHER has limited performance for CCP5 + PERF_LIMIT_OTHER_CCP_RESIDENCY_5 + Counter + 64 + 0 + 63 + + + + Groupname 0x8740 + 64 + + slow limit OTHER has limited performance for CCP6 + PERF_LIMIT_OTHER_CCP_RESIDENCY_6 + Counter + 64 + 0 + 63 + + + + Groupname 0x8748 + 64 + + slow limit OTHER has limited performance for CLR + PERF_LIMIT_OTHER_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8750 + 64 + + slow limit OTHER has limited performance for GT + PERF_LIMIT_OTHER_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8758 + 64 + + slow limit OTHER has limited performance for Media + PERF_LIMIT_OTHER_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8760 + 64 + + slow limit OTHER has limited performance for VPU + PERF_LIMIT_OTHER_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8768 + 64 + + prochot assertions. + PROCHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8770 + 64 + + VCCGT VR asserted VRHOT. + VCCIA_VRHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8778 + 64 + + VCCGT VR asserted VRHOT. + VCCGT_VRHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8780 + 64 + + VCCAUX VR asserted VRHOT. + VCCSA_VRHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8788 + 64 + + SOC was PL3 limited + PL3_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8790 + 64 + + SOC was PL2 limited + PL2_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8798 + 64 + + SOC was PL1 limited + PL1_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87a0 + 64 + + SOC was Psys PL3 limited + PSYS_PL3_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87a8 + 64 + + SOC was Psys PL2 limited + PSYS_PL2_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87b0 + 64 + + SOC was Psys PL1 limited + PSYS_PL1_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87b8 + 64 + + GT RC6 + GT_RC6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87c0 + 64 + + Media C6 residency + MEDIA_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87c8 + 64 + + IPU IS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + IPU_IS_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87d0 + 64 + + IPU PS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + IPU_PS_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x87d8 + 64 + + reserved + CNTR_RESERVED_87D8 + Counter + 64 + 0 + 63 + + + + Groupname 0x87e0 + 64 + + reserved + CNTR_RESERVED_87E0 + Counter + 64 + 0 + 63 + + + + Groupname 0x87e8 + 64 + + reserved + CNTR_RESERVED_87E8 + Counter + 64 + 0 + 63 + + + + Groupname 0x87f0 + 64 + + reserved + CNTR_RESERVED_87F0 + Counter + 64 + 0 + 63 + + + + Groupname 0x87f8 + 64 + + reserved + CNTR_RESERVED_87F8 + Counter + 64 + 0 + 63 + + + + Groupname 0x8800 + 64 + + reserved + CNTR_RESERVED_8800 + Counter + 64 + 0 + 63 + + + + Groupname 0x8808 + 64 + + C0 residency counter for Core0 + C0_RESIDENCY_CORE0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8810 + 64 + + C0 residency counter for Core1 + C0_RESIDENCY_CORE1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8818 + 64 + + C0 residency counter for Core2 + C0_RESIDENCY_CORE2 + Counter + 64 + 0 + 63 + + + + Groupname 0x8820 + 64 + + C0 residency counter for Core3 + C0_RESIDENCY_CORE3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8828 + 64 + + C0 residency counter for Core4 + C0_RESIDENCY_CORE4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8830 + 64 + + C0 residency counter for Core5 + C0_RESIDENCY_CORE5 + Counter + 64 + 0 + 63 + + + + Groupname 0x8838 + 64 + + C0 residency counter for Core6 + C0_RESIDENCY_CORE6 + Counter + 64 + 0 + 63 + + + + Groupname 0x8840 + 64 + + C0 residency counter for Core7 + C0_RESIDENCY_CORE7 + Counter + 64 + 0 + 63 + + + + Groupname 0x8848 + 64 + + C0 residency counter for Core8 + C0_RESIDENCY_CORE8 + Counter + 64 + 0 + 63 + + + + Groupname 0x8850 + 64 + + C0 residency counter for Core9 + C0_RESIDENCY_CORE9 + Counter + 64 + 0 + 63 + + + + Groupname 0x8858 + 64 + + C0 residency counter for Core10 + C0_RESIDENCY_CORE10 + Counter + 64 + 0 + 63 + + + + Groupname 0x8860 + 64 + + C0 residency counter for Core11 + C0_RESIDENCY_CORE11 + Counter + 64 + 0 + 63 + + + + Groupname 0x8868 + 64 + + C0 residency counter for Core12 + C0_RESIDENCY_CORE12 + Counter + 64 + 0 + 63 + + + + Groupname 0x8870 + 64 + + C0 residency counter for Core13 + C0_RESIDENCY_CORE13 + Counter + 64 + 0 + 63 + + + + Groupname 0x8878 + 64 + + C0 residency counter for Core14 + C0_RESIDENCY_CORE14 + Counter + 64 + 0 + 63 + + + + Groupname 0x8880 + 64 + + C0 residency counter for Core15 + C0_RESIDENCY_CORE15 + Counter + 64 + 0 + 63 + + + + Groupname 0x8888 + 64 + + Transition counter for when slow limit THERM has limited performance for CCP0 + PERF_LIMIT_THERM_CCP_COUNTER_0 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for CCP1 + PERF_LIMIT_THERM_CCP_COUNTER_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8890 + 64 + + Transition counter for when slow limit THERM has limited performance for CCP2 + PERF_LIMIT_THERM_CCP_COUNTER_2 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for CCP3 + PERF_LIMIT_THERM_CCP_COUNTER_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8898 + 64 + + Transition counter for when slow limit THERM has limited performance for CCP4 + PERF_LIMIT_THERM_CCP_COUNTER_4 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for CCP5 + PERF_LIMIT_THERM_CCP_COUNTER_5 + Counter + 32 + 32 + 63 + + + + Groupname 0x88a0 + 64 + + Transition counter for when slow limit THERM has limited performance for CCP6 + PERF_LIMIT_THERM_CCP_COUNTER_6 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for CLR + PERF_LIMIT_THERM_CLR_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x88a8 + 64 + + Transition counter for when slow limit THERM has limited performance for GT + PERF_LIMIT_THERM_GT_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for VPU + PERF_LIMIT_THERM_VPU_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x88b0 + 64 + + Transition counter for when slow limit THERM has limited performance for Media + PERF_LIMIT_THERM_MEDIA_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for CCP0 + PERF_LIMIT_POWER_CCP_COUNTER_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x88b8 + 64 + + Transition counter for when slow limit POWER has limited performance for CCP1 + PERF_LIMIT_POWER_CCP_COUNTER_1 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for CCP2 + PERF_LIMIT_POWER_CCP_COUNTER_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x88c0 + 64 + + Transition counter for when slow limit POWER has limited performance for CCP3 + PERF_LIMIT_POWER_CCP_COUNTER_3 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for CCP4 + PERF_LIMIT_POWER_CCP_COUNTER_4 + Counter + 32 + 32 + 63 + + + + Groupname 0x88c8 + 64 + + Transition counter for when slow limit POWER has limited performance for CCP5 + PERF_LIMIT_POWER_CCP_COUNTER_5 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for CCP6 + PERF_LIMIT_POWER_CCP_COUNTER_6 + Counter + 32 + 32 + 63 + + + + Groupname 0x88d0 + 64 + + Transition counter for when slow limit POWER has limited performance for CLR + PERF_LIMIT_POWER_CLR_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for GT + PERF_LIMIT_POWER_GT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x88d8 + 64 + + Transition counter for when slow limit POWER has limited performance for Media + PERF_LIMIT_POWER_MEDIA_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for VPU + PERF_LIMIT_POWER_VPU_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x88e0 + 64 + + Transition counter for when slow limit EDP has limited performance for CCP0 + PERF_LIMIT_EDP_CCP_COUNTER_0 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for CCP1 + PERF_LIMIT_EDP_CCP_COUNTER_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x88e8 + 64 + + Transition counter for when slow limit EDP has limited performance for CCP2 + PERF_LIMIT_EDP_CCP_COUNTER_2 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for CCP3 + PERF_LIMIT_EDP_CCP_COUNTER_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x88f0 + 64 + + Transition counter for when slow limit EDP has limited performance for CCP4 + PERF_LIMIT_EDP_CCP_COUNTER_4 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for CCP5 + PERF_LIMIT_EDP_CCP_COUNTER_5 + Counter + 32 + 32 + 63 + + + + Groupname 0x88f8 + 64 + + Transition counter for when slow limit EDP has limited performance for CCP6 + PERF_LIMIT_EDP_CCP_COUNTER_6 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for CLR + PERF_LIMIT_EDP_CLR_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8900 + 64 + + Transition counter for when slow limit EDP has limited performance for GT. + PERF_LIMIT_EDP_GT_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for Media + PERF_LIMIT_EDP_MEDIA_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8908 + 64 + + Transition counter for when slow limit EDP has limited performance for VPU + PERF_LIMIT_EDP_VPU_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for CCP0 + PERF_LIMIT_OTHER_CCP_COUNTER_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8910 + 64 + + Transition counter for when slow limit OTHER has limited performance for CCP1 + PERF_LIMIT_OTHER_CCP_COUNTER_1 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for CCP2 + PERF_LIMIT_OTHER_CCP_COUNTER_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8918 + 64 + + Transition counter for when slow limit OTHER has limited performance for CCP3 + PERF_LIMIT_OTHER_CCP_COUNTER_3 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for CCP4 + PERF_LIMIT_OTHER_CCP_COUNTER_4 + Counter + 32 + 32 + 63 + + + + Groupname 0x8920 + 64 + + Transition counter for when slow limit OTHER has limited performance for CCP5 + PERF_LIMIT_OTHER_CCP_COUNTER_5 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for CCP6 + PERF_LIMIT_OTHER_CCP_COUNTER_6 + Counter + 32 + 32 + 63 + + + + Groupname 0x8928 + 64 + + Transition counter for when slow limit OTHER has limited performance for CLR. + PERF_LIMIT_OTHER_CLR_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for GT. + PERF_LIMIT_OTHER_GT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8930 + 64 + + Transition counter for when slow limit OTHER has limited performance for Media. + PERF_LIMIT_OTHER_MEDIA_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for VPU. + PERF_LIMIT_OTHER_VPU_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8938 + 64 + + Energy reported by the Psys VR + PSYS_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x8940 + 64 + + Total package energy including Compute+GT+PCH, (should be the same as MSR package_energy_status) + PACKAGE_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x8948 + 64 + + IA VR energy (should be same as PRIMARY_PLANE_ENERGY_STATUS MSR) + VCCIA_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x8950 + 64 + + GT VR energy (should be same as SECONDARY_PLANE_ENERGY_STATUS) + VCCGT_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x8958 + 64 + + Energy estimated by Pcode using utilization factor from the VPU. Format is U18.14. + VPU_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x8960 + 64 + + reserved + SMPL_RESERVED0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8968 + 64 + + reserved + SMPL_RESERVED1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8970 + 64 + + reserved + SMPL_RESERVED2 + Counter + 64 + 0 + 63 + + + + Groupname 0x8978 + 64 + + reserved + SMPL_RESERVED3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8980 + 64 + + reserved + SMPL_RESERVED4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8988 + 64 + + HW_COUNTER_MMIO_OFFSET_8988 + HW_COUNTER_MMIO_OFFSET_8988 + Counter + 64 + 0 + 63 + + + + Groupname 0x8990 + 64 + + HW_COUNTER_MMIO_OFFSET_8990 + HW_COUNTER_MMIO_OFFSET_8990 + Counter + 64 + 0 + 63 + + + + Groupname 0x8998 + 64 + + HW_COUNTER_MMIO_OFFSET_8998 + HW_COUNTER_MMIO_OFFSET_8998 + Counter + 64 + 0 + 63 + + + + Groupname 0x89a0 + 64 + + HW_COUNTER_MMIO_OFFSET_89A0 + HW_COUNTER_MMIO_OFFSET_89A0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89a8 + 64 + + HW_COUNTER_MMIO_OFFSET_89A8 + HW_COUNTER_MMIO_OFFSET_89A8 + Counter + 64 + 0 + 63 + + + + Groupname 0x89b0 + 64 + + HW_COUNTER_MMIO_OFFSET_89B0 + HW_COUNTER_MMIO_OFFSET_89B0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89b8 + 64 + + HW_COUNTER_MMIO_OFFSET_89B8 + HW_COUNTER_MMIO_OFFSET_89B8 + Counter + 64 + 0 + 63 + + + + Groupname 0x89c0 + 64 + + HW_COUNTER_MMIO_OFFSET_89C0 + HW_COUNTER_MMIO_OFFSET_89C0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89c8 + 64 + + HW_COUNTER_MMIO_OFFSET_89C8 + HW_COUNTER_MMIO_OFFSET_89C8 + Counter + 64 + 0 + 63 + + + + Groupname 0x89d0 + 64 + + HW_COUNTER_MMIO_OFFSET_89D0 + HW_COUNTER_MMIO_OFFSET_89D0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89d8 + 64 + + HW_COUNTER_MMIO_OFFSET_89D8 + HW_COUNTER_MMIO_OFFSET_89D8 + Counter + 64 + 0 + 63 + + + + Groupname 0x89e0 + 64 + + HW_COUNTER_MMIO_OFFSET_89E0 + HW_COUNTER_MMIO_OFFSET_89E0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89e8 + 64 + + HW_COUNTER_MMIO_OFFSET_89E8 + HW_COUNTER_MMIO_OFFSET_89E8 + Counter + 64 + 0 + 63 + + + + Groupname 0x89f0 + 64 + + HW_COUNTER_MMIO_OFFSET_89F0 + HW_COUNTER_MMIO_OFFSET_89F0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89f8 + 64 + + reserved + SMPL_RESERVED5 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a00 + 64 + + reserved + SMPL_RESERVED6 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a08 + 64 + + reserved + SMPL_RESERVED7 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a10 + 64 + + reserved + SMPL_RESERVED8 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a18 + 64 + + reserved + SMPL_RESERVED9 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a20 + 64 + + reserved + SMPL_RESERVED10 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a28 + 64 + + reserved + SMPL_RESERVED11 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a30 + 64 + + reserved + SMPL_RESERVED12 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a38 + 64 + + reserved + SMPL_RESERVED13 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a40 + 64 + + reserved + SMPL_RESERVED14 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a48 + 64 + + reserved + CNTR_RESERVED_8A48 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a50 + 64 + + reserved + CNTR_RESERVED_8A50 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a58 + 64 + + reserved + CNTR_RESERVED_8A58 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a60 + 64 + + reserved + CNTR_RESERVED_8A60 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a68 + 64 + + prochot assertions. + PROCHOT_COUNTER + Counter + 32 + 0 + 31 + + + counts VCCIA VR asserted VRHOT. + VCCIA_VRHOT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8a70 + 64 + + counts VCCGT VR asserted VRHOT. + VCCGT_VRHOT_COUNTER + Counter + 32 + 0 + 31 + + + counts VCCSA VR asserted VRHOT. + VCCSA_VRHOT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8a78 + 64 + + SOC was PL3 limited + PL3_LIMITED_COUNTER + Counter + 32 + 0 + 31 + + + SOC was PL2 limited + PL2_LIMITED_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8a80 + 64 + + SOC was PL1 limited + PL1_LIMITED_COUNTER + Counter + 32 + 0 + 31 + + + SOC was Psys PL3 limited + PSYS_PL3_LIMITED_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8a88 + 64 + + SOC was Psys PL2 limited + PSYS_PL2_LIMITED_COUNTER + Counter + 32 + 0 + 31 + + + SOC was Psys PL1 limited + PSYS_PL1_LIMITED_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8a90 + 64 + + GT RC6 state transition counter + GT_RC6_COUNTER + Counter + 32 + 0 + 31 + + + Media C6 state transition counter + MEDIA_C6_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8a98 + 64 + + IPU IS C6 state transition counter + IPU_IS_C6_COUNTER + Counter + 32 + 0 + 31 + + + IPU PS C6 state transition counter + IPU_PS_C6_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8aa0 + 64 + + reserved + CNTR_RESERVED_8AA0 + Counter + 32 + 0 + 31 + + + reserved + CNTR_RESERVED_8AA4 + Counter + 32 + 32 + 63 + + + + Groupname 0x8aa8 + 64 + + reserved + CNTR_RESERVED_8AA8 + Counter + 32 + 0 + 31 + + + reserved + CNTR_RESERVED_8AAC + Counter + 32 + 32 + 63 + + + + Groupname 0x8ab0 + 64 + + reserved + CNTR_RESERVED_8AB0 + Counter + 32 + 0 + 31 + + + reserved + CNTR_RESERVED_8AB4 + Counter + 32 + 32 + 63 + + + + Groupname 0x8ab8 + 64 + + HW_COUNTER_MMIO_OFFSET_8AB8 + HW_COUNTER_MMIO_OFFSET_8AB8 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ac0 + 64 + + HW_COUNTER_MMIO_OFFSET_8AC0 + HW_COUNTER_MMIO_OFFSET_8AC0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ac8 + 64 + + HW_COUNTER_MMIO_OFFSET_8AC8 + HW_COUNTER_MMIO_OFFSET_8AC8 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ad0 + 64 + + HW_COUNTER_MMIO_OFFSET_8AD0 + HW_COUNTER_MMIO_OFFSET_8AD0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ad8 + 64 + + reserved + CNTR_RESERVED_8AD8 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ae0 + 64 + + reserved + CNTR_RESERVED_8AE0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ae8 + 64 + + HW_COUNTER_MMIO_OFFSET_8AE8 + HW_COUNTER_MMIO_OFFSET_8AE8 + Counter + 64 + 0 + 63 + + + + Groupname 0x8af0 + 64 + + HW_COUNTER_MMIO_OFFSET_8AF0 + HW_COUNTER_MMIO_OFFSET_8AF0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8af8 + 64 + + Counts total MC writes. Virtual bandwidth counter based on PWM_WRDATA bulkcr sample.i.e TOTAL_WRITE_BANDWIDTH = total PWM_WRDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + TOTAL_WRITE_BANDWIDTH + Counter + 64 + 0 + 63 + + + + Groupname 0x8b00 + 64 + + Counts total MC reads. Virtual bandwidth counter based on PWM_RDDATA bulkcr sample.i.e TOTAL_READ_BANDWIDTH = total PWM_RDDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + TOTAL_READ_BANDWIDTH + Counter + 64 + 0 + 63 + + + + Groupname 0x8b08 + 64 + + The counter value is incremented as a function of the number of cores that reside in C0 and active. If N cores are simultaneously in C0, then the number of "clock ticks" that are incremented is N. Counts in XTAL units. Should be same as MSR ANY_CORE_C0 0x659. + IO_PKG_IA_C0_ANY_SUM + Counter + 64 + 0 + 63 + + + + Groupname 0x8b10 + 64 + + This counter increments whenever GT slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. Should be same as MSR ANY_GFXE_C0 0x65a + IO_PKG_GT_C0_ANY + Counter + 64 + 0 + 63 + + + + Groupname 0x8b18 + 64 + + This counter increments whenever GT slices or unslices are active and in C0 state and in overlap with one of the IA cores that is active and in C0. Counts in XTAL units. Should be same as MSR CORE_GFXE_OVERLAP_C0 0x65b + IO_PKG_GT_AND_IA_OVERLAP + Counter + 64 + 0 + 63 + + + + Groupname 0x8b20 + 64 + + Follow exactly the IO_PKG_GT_C0_ANY_SLICE. The only change is that they do +N (GT ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock.PKG_GT_C0_ANY_SLICE Counts clocks that any GT slice is active. Reference clock is XTAL. + IO_PKG_GT_C0_ANY_RATIO + Counter + 64 + 0 + 63 + + + + Groupname 0x8b28 + 64 + + This counter increments whenever MEDIA slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. + IO_PKG_MEDIA_C0_ANY + Counter + 64 + 0 + 63 + + + + Groupname 0x8b30 + 64 + + Follow exactly the PKG_MEDIA_C0_ANY_SLICE. The only change is that they do +N (media ratio) instead of +1 on the relevant clock edge.PKG_MEDIA_C0_ANY_SLICE Counts clocks that any Media slice is active.Counter rate is in Xtal Clock. + IO_PKG_MEDIA_C0_ANY_RATIO + Counter + 64 + 0 + 63 + + + + Groupname 0x8b38 + 64 + + follow exactly the PKG_IA_C0_ANYThe only change is that they do +N (Max IA ratio) instead of +1 on the relevant clock edge and conditions (while any LP_AT_C0[i]=1):PCU_CR_PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU += PKG_IA_C0_CURRENT_RATIO.RATIOPKG_IA_C0_CURRENT_RATIO.RATIO = MAX(IO_WP_CV_P_STATE[IA_RATIO]).Reference clock is XTAL. + IO_PKG_IA_C0_ANY_RATIO + Counter + 64 + 0 + 63 + + + + Groupname 0x8b40 + 64 + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 0. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0 + Counter + 32 + 0 + 31 + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 1. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8b48 + 64 + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 2. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2 + Counter + 32 + 0 + 31 + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 0. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0_MMIO + Counter + 32 + 32 + 63 + + + + Groupname 0x8b50 + 64 + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 1. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1_MMIO + Counter + 32 + 0 + 31 + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 2. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2_MMIO + Counter + 32 + 32 + 63 + + + + Groupname 0x8b58 + 64 + + HW_COUNTER_MMIO_OFFSET_8B58 + HW_COUNTER_MMIO_OFFSET_8B58 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b60 + 64 + + HW_COUNTER_MMIO_OFFSET_8B60 + HW_COUNTER_MMIO_OFFSET_8B60 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b68 + 64 + + HW_COUNTER_MMIO_OFFSET_8B68 + HW_COUNTER_MMIO_OFFSET_8B68 + Counter + 32 + 0 + 31 + + + HW_COUNTER_MMIO_OFFSET_8B68 + HW_COUNTER_MMIO_OFFSET_8B68_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8b70 + 64 + + HW_COUNTER_MMIO_OFFSET_8B70 + HW_COUNTER_MMIO_OFFSET_8B70 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b78 + 64 + + HW_COUNTER_MMIO_OFFSET_8B78 + HW_COUNTER_MMIO_OFFSET_8B78 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b80 + 64 + + HW_COUNTER_MMIO_OFFSET_8B80 + HW_COUNTER_MMIO_OFFSET_8B80 + Counter + 32 + 0 + 31 + + + HW_COUNTER_MMIO_OFFSET_8B80 + HW_COUNTER_MMIO_OFFSET_8B80_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8b88 + 64 + + reserved + CNTR_RESERVED_0_8B88 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b90 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b98 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ba0 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ba8 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bb0 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bb8 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bc0 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bc8 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bd0 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bd8 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8be0 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8be8 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bf0 + 64 + + reserved + CNTR_RESERVED_1_to_110 + Counter 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b/xml/PTL/0/ptl_aggregator_interface.xml @@ -0,0 +1,7480 @@ + + + + + + + + + float + + parameter_0 + + $parameter_0 / ( 38.4 * 1e6 ) + + + float + + parameter_0 + + $parameter_0 * 0.0025 + + + float + + parameter_0 + + $parameter_0 * 64 / 1e6 + + + float + + parameter_0 + + $parameter_0 / 1e6 + + + float + + parameter_0 + + $parameter_0 * 32 / 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + ( 49 + $parameter_0 ) * 0.005 + + + integer + + parameter_0 + + ( ( ( 1 - ( ( $parameter_0 >> 7 ) & 0x1 ) ) * ( $parameter_0 & 0xff ) ) - ( ( ( $parameter_0 >> 7 ) & 0x1 ) * ( ( ( $parameter_0 & 0x7f ) ^ 0x7f ) + 1 ) ) ) + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + ( $parameter_0 & 0xff ) / ( 2**7 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x3ff ) / ( 2**3 ) + + + float + + parameter_0 + + $parameter_0 * 0.1 + + + float + + parameter_0 + + $parameter_0 * 0.01667 + + + float + + parameter_0 + + $parameter_0 * 0.025 + + + float + + parameter_0 + + $parameter_0 * 0.033 + + + float + + parameter_0 + + $parameter_0 * 0.05 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**8 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x1ff ) / ( 2**8 ) + + + float + + parameter_0 + + $parameter_0 * 100 / 128 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**15 ) + + + float + + parameter_0 + + $parameter_0 * 0.002 + + + float + + parameter_0 + + ( $parameter_0 & 0x7ff ) / ( 2**2 ) + + + float + + parameter_0 + + ( $parameter_0 & 0xffffffff ) / ( 2**14 ) + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + $parameter_0 * 64 + + + float + + parameter_0 + + $parameter_0 * 0.025 * 33.33 + + + float + + parameter_0 + + $parameter_0 / 400 * 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 * 1000 + + + float + + parameter_0 + + $parameter_0 / 10 + + + float + + parameter_0 + + $parameter_0 / 200 * 1e6 + + + float + + parameter_0 + + $parameter_0 * 1024 / 1e6 + + + float + + parameter_0 + + $parameter_0 / ( 19.2 * 1e6 ) + + + integer + + parameter_0 + + $parameter_0 + + + + ptl + PTL normal telemetry in Punit + 0x03086000 + Public + 10 + 2026-02-27 + + + Local Revision ID for this product (revision of the xml) + Snapshot + + + Container_0 + LOCAL_REVISION_ID + + + passthru + + + '1' for fixed block telemetry ID, '0' for rest. Default is '0' + Snapshot + + + Container_0 + FIXED_TELEMETRY_IDENTIFIER + + + passthru + + + reserved + Snapshot + + + Container_0 + reserved_0 + + + passthru + + + Product ID= 22 | TGLUY= 23 | TGLH= 24 | TGLS= 79 | ADL-P= 80 | ADL-S= 90 | RPL= 91 | RPL-P= 92 | RPL-S= 103 | MTL-M= 104 | MTL-P= 105 | MTL-S= 106 | ARL= 114 | LNL-M= 134 | PTL-P= 135 | PTL-H= 141 | WCL-U + Snapshot + + + Container_0 + PRODUCT_ID + + + passthru + + + source id for data provider + Snapshot + + + Container_0 + RECORD_TYPE + + + passthru + + + reserved + Snapshot + + + Container_0 + reserved_1 + + + passthru + + + Represents the clock rate of the XTAL on this silicon.= 0 | 24MHz= 1 | 19.2MHz= 2 | 38.4MHz= 3 | 25MHz + Snapshot + + + Container_0 + XTAL_FREQ + + + passthru + + + reserved + Snapshot + + + Container_0 + reserved_2 + + + passthru + + + reserved + Snapshot + + + Container_1 + smpl_reserved_0_0 + + + passthru + + + reserved + Snapshot + + + Container_1 + smpl_reserved_0_1 + + + passthru + + + reserved + Snapshot + + + Container_1 + smpl_reserved_0_2 + + + passthru + + + reserved + Snapshot + + + Container_1 + smpl_reserved_0_3 + + + passthru + + + reserved + Snapshot + + + Container_1 + smpl_reserved_0_4 + + + passthru + + + reserved + Snapshot + + + Container_1 + smpl_reserved_0_5 + + + passthru + + + reserved + Snapshot + + + Container_1 + smpl_reserved_0_6 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_0 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_1 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_2 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_3 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_4 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_5 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_6 + + + passthru + + + reserved + Snapshot + + + Container_2 + smpl_reserved_1_7 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_2_0 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_2_1 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_2_2 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_2_3 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_3_0 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_3_1 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_3_2 + + + passthru + + + reserved + Snapshot + + + Container_3 + smpl_reserved_3_3 + + + passthru + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + VOLTAGE + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + CURRENT + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + PS_OVERRIDE + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_4 + FREQ + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + VOLTAGE_1 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + Snapshot + + + Container_4 + CURRENT_1 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + PS_OVERRIDE_1 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_4 + FREQ_1 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + VOLTAGE_2 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + Snapshot + + + Container_5 + CURRENT_2 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + PS_OVERRIDE_2 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_5 + FREQ_2 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + VOLTAGE_3 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + Snapshot + + + Container_5 + CURRENT_3 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + PS_OVERRIDE_3 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_5 + FREQ_3 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + VOLTAGE_4 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + Snapshot + + + Container_6 + CURRENT_4 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + PS_OVERRIDE_4 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_6 + FREQ_4 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + VOLTAGE_5 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + Snapshot + + + Container_6 + CURRENT_5 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + PS_OVERRIDE_5 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_6 + FREQ_5 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_7 + VOLTAGE_6 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + Snapshot + + + Container_7 + CURRENT_6 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_7 + PS_OVERRIDE_6 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_7 + FREQ_6 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_7 + VOLTAGE_7 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. Not Valid. Expected value is '0' + Snapshot + + + Container_7 + CURRENT_7 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_7 + PS_OVERRIDE_7 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_7 + FREQ_7 + + + ratio_100 + + + reserved + Snapshot + + + Container_8 + rsvd + + + passthru + + + reserved + Snapshot + + + Container_8 + reserved_0_1 + + + passthru + + + reserved + Snapshot + + + Container_8 + reserved_1_1 + + + passthru + + + reserved + Snapshot + + + Container_8 + reserved_2_1 + + + passthru + + + reserved + Snapshot + + + Container_8 + reserved_3 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_0_2 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_1_2 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_2_2 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_3_1 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_4 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_5 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_6 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_0_3 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_1_3 + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_2_3 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_10 + VID_IA + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_10 + PS_IA + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_10 + FAST_IA + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_10 + DECAY_IA + + + passthru + + + reserved + Snapshot + + + Container_10 + reserved0 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_10 + VID_GT + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_10 + PS_GT + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_10 + FAST_GT + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_10 + DECAY_GT + + + passthru + + + reserved + Snapshot + + + Container_10 + reserved1 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_10 + VID_SA + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_10 + PS_SA + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_10 + FAST_SA + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_10 + DECAY_SA + + + passthru + + + reserved + Snapshot + + + Container_10 + reserved2 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_10 + VID_ATOM + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_10 + PS_ATOM + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_10 + FAST_ATOM + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_10 + DECAY_ATOM + + + passthru + + + reserved + Snapshot + + + Container_10 + reserved3 + + + passthru + + + reserved + Snapshot + + + Container_11 + reserved + + + passthru + + + last SVID0 VR current reading - translated IMON version for VCCIA, in amps. U16.8.8 + Snapshot + + + Container_11 + ICC_IA + + + U16.8.8 + + + last SVID1 VR current reading - translated IMON version for VCCGT, in amps. U16.8.8 + Snapshot + + + Container_11 + ICC_GT + + + U16.8.8 + + + last SVID2 VR current reading - translated IMON version for VCCSA, in amps. U16.8.8 + Snapshot + + + Container_12 + ICC_SA + + + U16.8.8 + + + last SVID3 VR current reading - translated IMON version for VCCATOM, in amps. U16.8.8 + Snapshot + + + Container_12 + ICC_ATOM + + + U16.8.8 + + + reserved + Snapshot + + + Container_12 + reserved_1 + + + passthru + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_13 + CORE0 + + + passthru + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_13 + CORE1 + + + passthru + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_13 + CORE2 + + + passthru + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_13 + CORE3 + + + passthru + + + IA Core C-state of Atom core 00: C01: C13: C67: CRST + Snapshot + + + Container_13 + Atom_Module0 + + + passthru + + + IA Core C-state of Atom core 10: C01: C13: C67: CRST + Snapshot + + + Container_13 + Atom_Module1 + + + passthru + + + IA Core C-state of Atom core 20: C01: C13: C67: CRST + Snapshot + + + Container_13 + Atom_Module2 + + + passthru + + + LLC/Ring C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + Snapshot + + + Container_13 + Cluster0 + + + passthru + + + Iceland cluster C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + Snapshot + + + Container_13 + Cluster1 + + + passthru + + + GT RC-state0: C01: C13: C67: CRST + Snapshot + + + Container_13 + GT + + + passthru + + + reserved + Snapshot + + + Container_13 + reserved_2 + + + passthru + + + CDYN level granted that CORE0 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_14 + CORE0_1 + + + passthru + + + CDYN level granted that CORE1 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_14 + CORE1_1 + + + passthru + + + CDYN level granted that CORE2 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_14 + CORE2_1 + + + passthru + + + CDYN level granted that CORE3 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_14 + CORE3_1 + + + passthru + + + CDYN level granted that Atom module0 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + Snapshot + + + Container_14 + ATOM_MODULE0 + + + passthru + + + CDYN level granted that Atom module1 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + Snapshot + + + Container_14 + ATOM_MODULE1 + + + passthru + + + CDYN level granted that Atom module2 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + Snapshot + + + Container_14 + ATOM_MODULE2 + + + passthru + + + reserved + Snapshot + + + Container_14 + reserved0_1 + + + passthru + + + reserved + Snapshot + + + Container_14 + reserved1_1 + + + passthru + + + Current PCH temperature + Snapshot + + + Container_15 + PCH_TEMP + + + S8.7.0 + + + Current reading from System Agent "always on" temperature sensor + Snapshot + + + Container_15 + SA_TEMP + + + S8.7.0 + + + Current reading from IPU subsystem temperature sensor + Snapshot + + + Container_15 + IPU_TEMP + + + S8.7.0 + + + Current reading from Display subsystem temperature sensor + Snapshot + + + Container_15 + DE_TEMP + + + S8.7.0 + + + Current reading from VPU subsystem temperature sensor + Snapshot + + + Container_15 + VPU_TEMP + + + S8.7.0 + + + Current reading from Media subsystem temperature sensor + Snapshot + + + Container_15 + Media_TEMP + + + S8.7.0 + + + Graphics Min temp + Snapshot + + + Container_15 + GT_MIN + + + S8.7.0 + + + Graphics Max temp + Snapshot + + + Container_15 + GT_MAX + + + S8.7.0 + + + Min temp across the core + Snapshot + + + Container_16 + CCP0_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_16 + CCP0_MAX + + + S8.7.0 + + + Min temp across the core + Snapshot + + + Container_16 + CCP1_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_16 + CCP1_MAX + + + S8.7.0 + + + Min temp across the core + Snapshot + + + Container_16 + CCP2_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_16 + CCP2_MAX + + + S8.7.0 + + + Min temp across the core + Snapshot + + + Container_16 + CCP3_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_16 + CCP3_MAX + + + S8.7.0 + + + Min temp across the atom module + Snapshot + + + Container_17 + CCP4_MIN + + + S8.7.0 + + + Max temp across the atom module + Snapshot + + + Container_17 + CCP4_MAX + + + S8.7.0 + + + Min temp across the atom module + Snapshot + + + Container_17 + CCP5_MIN + + + S8.7.0 + + + Max temp across the atom module + Snapshot + + + Container_17 + CCP5_MAX + + + S8.7.0 + + + Min temp across the atom module + Snapshot + + + Container_17 + CCP6_MIN + + + S8.7.0 + + + Max temp across the atom module + Snapshot + + + Container_17 + CCP6_MAX + + + S8.7.0 + + + LLC Min temp + Snapshot + + + Container_17 + LLC_MIN + + + S8.7.0 + + + LLC Max temp + Snapshot + + + Container_17 + LLC_MAX + + + S8.7.0 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE0_2 + + + U9.1.8 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE1_2 + + + U9.1.8 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE2_2 + + + U9.1.8 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE3_2 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_19 + CORE4 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_19 + CORE5 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_19 + CORE6 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_19 + CORE7 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_20 + CORE8 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_20 + CORE9 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_20 + CORE10 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_20 + CORE11 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_21 + CORE12 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_21 + CORE13 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_21 + CORE14 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_21 + CORE15 + + + U9.1.8 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_0 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_1 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_2 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_3 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_4 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_5 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_6 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_22 + RATIO_7 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_8 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_9 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_10 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_11 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_12 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_13 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_14 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_23 + RATIO_15 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_0_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_1_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_2_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_3_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_4_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_5_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_6_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_24 + RATIO_7_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_8_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_9_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_10_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_11_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_12_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_13_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_14_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_25 + RATIO_15_1 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_0 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_1 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_2 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_3 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_4 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_5 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_6 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_26 + IA_PE_7 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_8 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_9 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_10 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_11 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_12 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_13 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_14 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_27 + IA_PE_15 + + + ratio_100 + + + Current GT Efficient P-state (used as the floor for autonomous control) + Snapshot + + + Container_28 + GT_PE + + + ratio_100 + + + reserved + Snapshot + + + Container_28 + reserved_3 + + + passthru + + + Temperature of PECI sensor in 1/32 DegC + Snapshot + + + Container_29 + SENSOR_0 + + + platform_temperature + + + Temperature of PECI sensor in 1/32 DegC + Snapshot + + + Container_29 + SENSOR_1 + + + platform_temperature + + + Temperature of PECI sensor in 1/32 DegC + Snapshot + + + Container_29 + SENSOR_2 + + + platform_temperature + + + reserved + Snapshot + + + Container_29 + reserved_4 + + + platform_temperature + + + Contains EC settings for sensor 0. + Snapshot + + + Container_30 + EC_SETTINGS_SENSOR_0 + + + passthru + + + Contains EC settings for sensor 1. + Snapshot + + + Container_30 + EC_SETTINGS_SENSOR_1 + + + passthru + + + Contains EC settings for sensor 2. + Snapshot + + + Container_31 + EC_SETTINGS_SENSOR_2 + + + passthru + + + reserved + Snapshot + + + Container_31 + rsvd_1 + + + passthru + + + Contains MMIO settings for sensor 0. + Snapshot + + + Container_32 + EC_SETTINGS_SENSOR_0_1 + + + passthru + + + Contains MMIO settings for sensor 1. + Snapshot + + + Container_32 + EC_SETTINGS_SENSOR_1_1 + + + passthru + + + Contains MMIO settings for sensor 2. + Snapshot + + + Container_33 + EC_SETTINGS_SENSOR_2_1 + + + passthru + + + reserved + Snapshot + + + Container_33 + rsvd_2 + + + passthru + + + reserved + Snapshot + + + Container_34 + reserved_0_4 + + + passthru + + + reserved + Snapshot + + + Container_35 + reserved_0_5 + + + passthru + + + reserved + Snapshot + + + Container_36 + reserved_0_6 + + + passthru + + + reserved + Snapshot + + + Container_37 + reserved_0_7 + + + passthru + + + reserved + Snapshot + + + Container_38 + reserved_0_8 + + + passthru + + + reserved + Snapshot + + + Container_39 + reserved_0_9 + + + passthru + + + reserved + Snapshot + + + Container_40 + reserved_0_10 + + + passthru + + + reserved + Snapshot + + + Container_41 + reserved_0_11 + + + passthru + + + reserved + Snapshot + + + Container_42 + reserved_0_12 + + + passthru + + + reserved + Snapshot + + + Container_43 + reserved_0_13 + + + passthru + + + reserved + Snapshot + + + Container_44 + reserved_0_14 + + + passthru + + + reserved + Snapshot + + + Container_45 + reserved_0_15 + + + passthru + + + reserved + Snapshot + + + Container_46 + reserved_0_16 + + + passthru + + + reserved + Snapshot + + + Container_47 + reserved_0_17 + + + passthru + + + reserved + Snapshot + + + Container_48 + reserved_0_18 + + + passthru + + + reserved + Snapshot + + + Container_49 + reserved_0_19 + + + passthru + + + reserved + Snapshot + + + Container_50 + reserved_0_20 + + + passthru + + + reserved + Snapshot + + + Container_51 + reserved_0_21 + + + passthru + + + reserved + Snapshot + + + Container_52 + reserved_0_22 + + + passthru + + + reserved + Snapshot + + + Container_53 + reserved_0_23 + + + passthru + + + reserved + Snapshot + + + Container_54 + reserved_0_24 + + + passthru + + + reserved + Snapshot + + + Container_55 + reserved_0_25 + + + passthru + + + reserved + Snapshot + + + Container_56 + reserved_0_26 + + + passthru + + + reserved + Snapshot + + + Container_57 + reserved_0_27 + + + passthru + + + reserved + Snapshot + + + Container_58 + reserved_0_28 + + + passthru + + + reserved + Snapshot + + + Container_59 + reserved_0_29 + + + passthru + + + reserved + Snapshot + + + Container_60 + reserved_0_30 + + + passthru + + + reserved + Snapshot + + + Container_61 + reserved_0_31 + + + passthru + + + reserved + Snapshot + + + Container_62 + reserved_0_32 + + + passthru + + + reserved + Snapshot + + + Container_63 + reserved_0_33 + + + passthru + + + reserved + Snapshot + + + Container_64 + reserved_0_34 + + + passthru + + + reserved + Snapshot + + + Container_65 + reserved_0_35 + + + passthru + + + reserved + Snapshot + + + Container_66 + reserved_0_36 + + + passthru + + + reserved + Snapshot + + + Container_67 + reserved_0_37 + + + passthru + + + reserved + Snapshot + + + Container_68 + reserved_0_38 + + + passthru + + + reserved + Snapshot + + + Container_69 + reserved_0_39 + + + passthru + + + reserved + Snapshot + + + Container_70 + reserved_0_40 + + + passthru + + + reserved + Snapshot + + + Container_71 + reserved_0_41 + + + passthru + + + reserved + Snapshot + + + Container_72 + reserved_0_42 + + + passthru + + + reserved + Snapshot + + + Container_73 + reserved_0_43 + + + passthru + + + reserved + Snapshot + + + Container_74 + reserved_0_44 + + + passthru + + + reserved + Snapshot + + + Container_75 + reserved_0_45 + + + passthru + + + reserved + Snapshot + + + Container_76 + reserved_0_46 + + + passthru + + + reserved + Snapshot + + + Container_77 + reserved_0_47 + + + passthru + + + reserved + Snapshot + + + Container_78 + reserved_0_48 + + + passthru + + + reserved + Snapshot + + + Container_79 + reserved_0_49 + + + passthru + + + reserved + Snapshot + + + Container_80 + reserved_0_50 + + + passthru + + + reserved + Snapshot + + + Container_81 + reserved_0_51 + + + passthru + + + reserved + Snapshot + + + Container_82 + reserved_0_52 + + + passthru + + + reserved + Snapshot + + + Container_83 + reserved_0_53 + + + passthru + + + reserved + Snapshot + + + Container_84 + reserved_0_54 + + + passthru + + + reserved + Snapshot + + + Container_85 + reserved_0_55 + + + passthru + + + reserved + Snapshot + + + Container_86 + reserved_0_56 + + + passthru + + + reserved + Snapshot + + + Container_87 + reserved_0_57 + + + passthru + + + reserved + Snapshot + + + Container_88 + reserved_0_58 + + + passthru + + + reserved + Snapshot + + + Container_89 + reserved_0_59 + + + passthru + + + reserved + Snapshot + + + Container_90 + reserved_0_60 + + + passthru + + + reserved + Snapshot + + + Container_91 + reserved_0_61 + + + passthru + + + reserved + Snapshot + + + Container_92 + reserved_0_62 + + + passthru + + + reserved + Snapshot + + + Container_93 + reserved_0_63 + + + passthru + + + reserved + Snapshot + + + Container_94 + reserved_0_64 + + + passthru + + + reserved + Snapshot + + + Container_95 + reserved_0_65 + + + passthru + + + reserved + Snapshot + + + Container_96 + reserved_0_66 + + + passthru + + + reserved + Snapshot + + + Container_97 + reserved_0_67 + + + passthru + + + reserved + Snapshot + + + Container_98 + reserved_0_68 + + + passthru + + + slow limit THERM has limited performance for CCP0 + Counter + + + Container_99 + PERF_LIMIT_THERM_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit THERM has limited performance for CCP1 + Counter + + + Container_100 + PERF_LIMIT_THERM_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit THERM has limited performance for CCP2 + Counter + + + Container_101 + PERF_LIMIT_THERM_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit THERM has limited performance for CCP3 + Counter + + + Container_102 + PERF_LIMIT_THERM_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit THERM has limited performance for CCP4 + Counter + + + Container_103 + PERF_LIMIT_THERM_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit THERM has limited performance for CCP5 + Counter + + + Container_104 + PERF_LIMIT_THERM_CCP_RESIDENCY_5 + + + xtal_time + + + slow limit THERM has limited performance for CCP6 + Counter + + + Container_105 + PERF_LIMIT_THERM_CCP_RESIDENCY_6 + + + xtal_time + + + slow limit THERM has limited performance for CLR + Counter + + + Container_106 + PERF_LIMIT_THERM_CLR_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for GT. + Counter + + + Container_107 + PERF_LIMIT_THERM_GT_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for IPU. + Counter + + + Container_108 + PERF_LIMIT_THERM_IPU_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for VPU. + Counter + + + Container_109 + PERF_LIMIT_THERM_VPU_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for Media. + Counter + + + Container_110 + PERF_LIMIT_THERM_MEDIA_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for CCP0 + Counter + + + Container_111 + PERF_LIMIT_POWER_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit POWER has limited performance for CCP1 + Counter + + + Container_112 + PERF_LIMIT_POWER_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit POWER has limited performance for CCP2 + Counter + + + Container_113 + PERF_LIMIT_POWER_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit POWER has limited performance for CCP3 + Counter + + + Container_114 + PERF_LIMIT_POWER_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit POWER has limited performance for CCP4 + Counter + + + Container_115 + PERF_LIMIT_POWER_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit POWER has limited performance for CCP5 + Counter + + + Container_116 + PERF_LIMIT_POWER_CCP_RESIDENCY_5 + + + xtal_time + + + slow limit POWER has limited performance for CCP6 + Counter + + + Container_117 + PERF_LIMIT_POWER_CCP_RESIDENCY_6 + + + xtal_time + + + slow limit POWER has limited performance for CLR + Counter + + + Container_118 + PERF_LIMIT_POWER_CLR_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for GT + Counter + + + Container_119 + PERF_LIMIT_POWER_GT_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for Media + Counter + + + Container_120 + PERF_LIMIT_POWER_MEDIA_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for VPU + Counter + + + Container_121 + PERF_LIMIT_POWER_VPU_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for CCP0 + Counter + + + Container_122 + PERF_LIMIT_EDP_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit EDP has limited performance for CCP1 + Counter + + + Container_123 + PERF_LIMIT_EDP_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit EDP has limited performance for CCP2 + Counter + + + Container_124 + PERF_LIMIT_EDP_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit EDP has limited performance for CCP3 + Counter + + + Container_125 + PERF_LIMIT_EDP_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit EDP has limited performance for CCP4 + Counter + + + Container_126 + PERF_LIMIT_EDP_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit EDP has limited performance for CCP5 + Counter + + + Container_127 + PERF_LIMIT_EDP_CCP_RESIDENCY_5 + + + xtal_time + + + slow limit EDP has limited performance for CCP6 + Counter + + + Container_128 + PERF_LIMIT_EDP_CCP_RESIDENCY_6 + + + xtal_time + + + slow limit EDP has limited performance for CLR + Counter + + + Container_129 + PERF_LIMIT_EDP_CLR_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for GT + Counter + + + Container_130 + PERF_LIMIT_EDP_GT_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for Media + Counter + + + Container_131 + PERF_LIMIT_EDP_MEDIA_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for VPU + Counter + + + Container_132 + PERF_LIMIT_EDP_VPU_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for CCP0 + Counter + + + Container_133 + PERF_LIMIT_OTHER_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit OTHER has limited performance for CCP1 + Counter + + + Container_134 + PERF_LIMIT_OTHER_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit OTHER has limited performance for CCP2 + Counter + + + Container_135 + PERF_LIMIT_OTHER_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit OTHER has limited performance for CCP3 + Counter + + + Container_136 + PERF_LIMIT_OTHER_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit OTHER has limited performance for CCP4 + Counter + + + Container_137 + PERF_LIMIT_OTHER_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit OTHER has limited performance for CCP5 + Counter + + + Container_138 + PERF_LIMIT_OTHER_CCP_RESIDENCY_5 + + + xtal_time + + + slow limit OTHER has limited performance for CCP6 + Counter + + + Container_139 + PERF_LIMIT_OTHER_CCP_RESIDENCY_6 + + + xtal_time + + + slow limit OTHER has limited performance for CLR + Counter + + + Container_140 + PERF_LIMIT_OTHER_CLR_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for GT + Counter + + + Container_141 + PERF_LIMIT_OTHER_GT_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for Media + Counter + + + Container_142 + PERF_LIMIT_OTHER_MEDIA_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for VPU + Counter + + + Container_143 + PERF_LIMIT_OTHER_VPU_RESIDENCY + + + xtal_time + + + prochot assertions. + Counter + + + Container_144 + PROCHOT_RESIDENCY + + + xtal_time + + + VCCGT VR asserted VRHOT. + Counter + + + Container_145 + VCCIA_VRHOT_RESIDENCY + + + xtal_time + + + VCCGT VR asserted VRHOT. + Counter + + + Container_146 + VCCGT_VRHOT_RESIDENCY + + + xtal_time + + + VCCAUX VR asserted VRHOT. + Counter + + + Container_147 + VCCSA_VRHOT_RESIDENCY + + + xtal_time + + + SOC was PL3 limited + Counter + + + Container_148 + PL3_LIMITED_RESIDENCY + + + xtal_time + + + SOC was PL2 limited + Counter + + + Container_149 + PL2_LIMITED_RESIDENCY + + + xtal_time + + + SOC was PL1 limited + Counter + + + Container_150 + PL1_LIMITED_RESIDENCY + + + xtal_time + + + SOC was Psys PL3 limited + Counter + + + Container_151 + PSYS_PL3_LIMITED_RESIDENCY + + + xtal_time + + + SOC was Psys PL2 limited + Counter + + + Container_152 + PSYS_PL2_LIMITED_RESIDENCY + + + xtal_time + + + SOC was Psys PL1 limited + Counter + + + Container_153 + PSYS_PL1_LIMITED_RESIDENCY + + + xtal_time + + + GT RC6 + Counter + + + Container_154 + GT_RC6_RESIDENCY + + + xtal_time + + + Media C6 residency + Counter + + + Container_155 + MEDIA_C6_RESIDENCY + + + xtal_time + + + IPU IS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + Counter + + + Container_156 + IPU_IS_C6_RESIDENCY + + + xtal_time + + + IPU PS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + Counter + + + Container_157 + IPU_PS_C6_RESIDENCY + + + xtal_time + + + reserved + Counter + + + Container_158 + CNTR_RESERVED_87D8 + + + passthru + + + reserved + Counter + + + Container_159 + CNTR_RESERVED_87E0 + + + passthru + + + reserved + Counter + + + Container_160 + CNTR_RESERVED_87E8 + + + passthru + + + reserved + Counter + + + Container_161 + CNTR_RESERVED_87F0 + + + passthru + + + reserved + Counter + + + Container_162 + CNTR_RESERVED_87F8 + + + passthru + + + reserved + Counter + + + Container_163 + CNTR_RESERVED_8800 + + + passthru + + + C0 residency counter for Core0 + Counter + + + Container_164 + C0_RESIDENCY_CORE0 + + + xtal_time + + + C0 residency counter for Core1 + Counter + + + Container_165 + C0_RESIDENCY_CORE1 + + + xtal_time + + + C0 residency counter for Core2 + Counter + + + Container_166 + C0_RESIDENCY_CORE2 + + + xtal_time + + + C0 residency counter for Core3 + Counter + + + Container_167 + C0_RESIDENCY_CORE3 + + + xtal_time + + + C0 residency counter for Core4 + Counter + + + Container_168 + C0_RESIDENCY_CORE4 + + + xtal_time + + + C0 residency counter for Core5 + Counter + + + Container_169 + C0_RESIDENCY_CORE5 + + + xtal_time + + + C0 residency counter for Core6 + Counter + + + Container_170 + C0_RESIDENCY_CORE6 + + + xtal_time + + + C0 residency counter for Core7 + Counter + + + Container_171 + C0_RESIDENCY_CORE7 + + + xtal_time + + + C0 residency counter for Core8 + Counter + + + Container_172 + C0_RESIDENCY_CORE8 + + + xtal_time + + + C0 residency counter for Core9 + Counter + + + Container_173 + C0_RESIDENCY_CORE9 + + + xtal_time + + + C0 residency counter for Core10 + Counter + + + Container_174 + C0_RESIDENCY_CORE10 + + + xtal_time + + + C0 residency counter for Core11 + Counter + + + Container_175 + C0_RESIDENCY_CORE11 + + + xtal_time + + + C0 residency counter for Core12 + Counter + + + Container_176 + C0_RESIDENCY_CORE12 + + + xtal_time + + + C0 residency counter for Core13 + Counter + + + Container_177 + C0_RESIDENCY_CORE13 + + + xtal_time + + + C0 residency counter for Core14 + Counter + + + Container_178 + C0_RESIDENCY_CORE14 + + + xtal_time + + + C0 residency counter for Core15 + Counter + + + Container_179 + C0_RESIDENCY_CORE15 + + + xtal_time + + + Transition counter for when slow limit THERM has limited performance for CCP0 + Counter + + + Container_180 + PERF_LIMIT_THERM_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP1 + Counter + + + Container_180 + PERF_LIMIT_THERM_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP2 + Counter + + + Container_181 + PERF_LIMIT_THERM_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP3 + Counter + + + Container_181 + PERF_LIMIT_THERM_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP4 + Counter + + + Container_182 + PERF_LIMIT_THERM_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP5 + Counter + + + Container_182 + PERF_LIMIT_THERM_CCP_COUNTER_5 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP6 + Counter + + + Container_183 + PERF_LIMIT_THERM_CCP_COUNTER_6 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CLR + Counter + + + Container_183 + PERF_LIMIT_THERM_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for GT + Counter + + + Container_184 + PERF_LIMIT_THERM_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for VPU + Counter + + + Container_184 + PERF_LIMIT_THERM_VPU_COUNTER + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for Media + Counter + + + Container_185 + PERF_LIMIT_THERM_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP0 + Counter + + + Container_185 + PERF_LIMIT_POWER_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP1 + Counter + + + Container_186 + PERF_LIMIT_POWER_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP2 + Counter + + + Container_186 + PERF_LIMIT_POWER_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP3 + Counter + + + Container_187 + PERF_LIMIT_POWER_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP4 + Counter + + + Container_187 + PERF_LIMIT_POWER_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP5 + Counter + + + Container_188 + PERF_LIMIT_POWER_CCP_COUNTER_5 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP6 + Counter + + + Container_188 + PERF_LIMIT_POWER_CCP_COUNTER_6 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CLR + Counter + + + Container_189 + PERF_LIMIT_POWER_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for GT + Counter + + + Container_189 + PERF_LIMIT_POWER_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for Media + Counter + + + Container_190 + PERF_LIMIT_POWER_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for VPU + Counter + + + Container_190 + PERF_LIMIT_POWER_VPU_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP0 + Counter + + + Container_191 + PERF_LIMIT_EDP_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP1 + Counter + + + Container_191 + PERF_LIMIT_EDP_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP2 + Counter + + + Container_192 + PERF_LIMIT_EDP_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP3 + Counter + + + Container_192 + PERF_LIMIT_EDP_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP4 + Counter + + + Container_193 + PERF_LIMIT_EDP_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP5 + Counter + + + Container_193 + PERF_LIMIT_EDP_CCP_COUNTER_5 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP6 + Counter + + + Container_194 + PERF_LIMIT_EDP_CCP_COUNTER_6 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CLR + Counter + + + Container_194 + PERF_LIMIT_EDP_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for GT. + Counter + + + Container_195 + PERF_LIMIT_EDP_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for Media + Counter + + + Container_195 + PERF_LIMIT_EDP_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for VPU + Counter + + + Container_196 + PERF_LIMIT_EDP_VPU_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP0 + Counter + + + Container_196 + PERF_LIMIT_OTHER_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP1 + Counter + + + Container_197 + PERF_LIMIT_OTHER_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP2 + Counter + + + Container_197 + PERF_LIMIT_OTHER_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP3 + Counter + + + Container_198 + PERF_LIMIT_OTHER_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP4 + Counter + + + Container_198 + PERF_LIMIT_OTHER_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP5 + Counter + + + Container_199 + PERF_LIMIT_OTHER_CCP_COUNTER_5 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP6 + Counter + + + Container_199 + PERF_LIMIT_OTHER_CCP_COUNTER_6 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CLR. + Counter + + + Container_200 + PERF_LIMIT_OTHER_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for GT. + Counter + + + Container_200 + PERF_LIMIT_OTHER_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for Media. + Counter + + + Container_201 + PERF_LIMIT_OTHER_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for VPU. + Counter + + + Container_201 + PERF_LIMIT_OTHER_VPU_COUNTER + + + event_counter + + + Energy reported by the Psys VR + Counter + + + Container_202 + PSYS_ENERGY + + + energy_J + + + Total package energy including Compute+GT+PCH, (should be the same as MSR package_energy_status) + Counter + + + Container_203 + PACKAGE_ENERGY + + + energy_J + + + IA VR energy (should be same as PRIMARY_PLANE_ENERGY_STATUS MSR) + Counter + + + Container_204 + VCCIA_ENERGY + + + vr_energy + + + GT VR energy (should be same as SECONDARY_PLANE_ENERGY_STATUS) + Counter + + + Container_205 + VCCGT_ENERGY + + + vr_energy + + + Energy estimated by Pcode using utilization factor from the VPU. Format is U18.14. + Counter + + + Container_206 + VPU_ENERGY + + + U32.18.14 + + + reserved + Counter + + + Container_207 + SMPL_RESERVED0 + + + passthru + + + reserved + Counter + + + Container_208 + SMPL_RESERVED1 + + + passthru + + + reserved + Counter + + + Container_209 + SMPL_RESERVED2 + + + passthru + + + reserved + Counter + + + Container_210 + SMPL_RESERVED3 + + + passthru + + + reserved + Counter + + + Container_211 + SMPL_RESERVED4 + + + passthru + + + HW_COUNTER_MMIO_OFFSET_8988 + Counter + + + Container_212 + HW_COUNTER_MMIO_OFFSET_8988 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_8990 + Counter + + + Container_213 + HW_COUNTER_MMIO_OFFSET_8990 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_8998 + Counter + + + Container_214 + HW_COUNTER_MMIO_OFFSET_8998 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89A0 + Counter + + + Container_215 + HW_COUNTER_MMIO_OFFSET_89A0 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89A8 + Counter + + + Container_216 + HW_COUNTER_MMIO_OFFSET_89A8 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89B0 + Counter + + + Container_217 + HW_COUNTER_MMIO_OFFSET_89B0 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89B8 + Counter + + + Container_218 + HW_COUNTER_MMIO_OFFSET_89B8 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89C0 + Counter + + + Container_219 + HW_COUNTER_MMIO_OFFSET_89C0 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89C8 + Counter + + + Container_220 + HW_COUNTER_MMIO_OFFSET_89C8 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89D0 + Counter + + + Container_221 + HW_COUNTER_MMIO_OFFSET_89D0 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89D8 + Counter + + + Container_222 + HW_COUNTER_MMIO_OFFSET_89D8 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89E0 + Counter + + + Container_223 + HW_COUNTER_MMIO_OFFSET_89E0 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89E8 + Counter + + + Container_224 + HW_COUNTER_MMIO_OFFSET_89E8 + + + bw_32B + + + HW_COUNTER_MMIO_OFFSET_89F0 + Counter + + + Container_225 + HW_COUNTER_MMIO_OFFSET_89F0 + + + bw_32B + + + reserved + Counter + + + Container_226 + SMPL_RESERVED5 + + + passthru + + + reserved + Counter + + + Container_227 + SMPL_RESERVED6 + + + passthru + + + reserved + Counter + + + Container_228 + SMPL_RESERVED7 + + + passthru + + + reserved + Counter + + + Container_229 + SMPL_RESERVED8 + + + passthru + + + reserved + Counter + + + Container_230 + SMPL_RESERVED9 + + + passthru + + + reserved + Counter + + + Container_231 + SMPL_RESERVED10 + + + passthru + + + reserved + Counter + + + Container_232 + SMPL_RESERVED11 + + + passthru + + + reserved + Counter + + + Container_233 + SMPL_RESERVED12 + + + passthru + + + reserved + Counter + + + Container_234 + SMPL_RESERVED13 + + + passthru + + + reserved + Counter + + + Container_235 + SMPL_RESERVED14 + + + passthru + + + reserved + Counter + + + Container_236 + CNTR_RESERVED_8A48 + + + passthru + + + reserved + Counter + + + Container_237 + CNTR_RESERVED_8A50 + + + passthru + + + reserved + Counter + + + Container_238 + CNTR_RESERVED_8A58 + + + passthru + + + reserved + Counter + + + Container_239 + CNTR_RESERVED_8A60 + + + passthru + + + prochot assertions. + Counter + + + Container_240 + PROCHOT_COUNTER + + + event_counter + + + counts VCCIA VR asserted VRHOT. + Counter + + + Container_240 + VCCIA_VRHOT_COUNTER + + + event_counter + + + counts VCCGT VR asserted VRHOT. + Counter + + + Container_241 + VCCGT_VRHOT_COUNTER + + + event_counter + + + counts VCCSA VR asserted VRHOT. + Counter + + + Container_241 + VCCSA_VRHOT_COUNTER + + + event_counter + + + SOC was PL3 limited + Counter + + + Container_242 + PL3_LIMITED_COUNTER + + + event_counter + + + SOC was PL2 limited + Counter + + + Container_242 + PL2_LIMITED_COUNTER + + + event_counter + + + SOC was PL1 limited + Counter + + + Container_243 + PL1_LIMITED_COUNTER + + + event_counter + + + SOC was Psys PL3 limited + Counter + + + Container_243 + PSYS_PL3_LIMITED_COUNTER + + + event_counter + + + SOC was Psys PL2 limited + Counter + + + Container_244 + PSYS_PL2_LIMITED_COUNTER + + + event_counter + + + SOC was Psys PL1 limited + Counter + + + Container_244 + PSYS_PL1_LIMITED_COUNTER + + + event_counter + + + GT RC6 state transition counter + Counter + + + Container_245 + GT_RC6_COUNTER + + + event_counter + + + Media C6 state transition counter + Counter + + + Container_245 + MEDIA_C6_COUNTER + + + event_counter + + + IPU IS C6 state transition counter + Counter + + + Container_246 + IPU_IS_C6_COUNTER + + + event_counter + + + IPU PS C6 state transition counter + Counter + + + Container_246 + IPU_PS_C6_COUNTER + + + event_counter + + + reserved + Counter + + + Container_247 + CNTR_RESERVED_8AA0 + + + passthru + + + reserved + Counter + + + Container_247 + CNTR_RESERVED_8AA4 + + + passthru + + + reserved + Counter + + + Container_248 + CNTR_RESERVED_8AA8 + + + passthru + + + reserved + Counter + + + Container_248 + CNTR_RESERVED_8AAC + + + passthru + + + reserved + Counter + + + Container_249 + CNTR_RESERVED_8AB0 + + + passthru + + + reserved + Counter + + + Container_249 + CNTR_RESERVED_8AB4 + + + passthru + + + HW_COUNTER_MMIO_OFFSET_8AB8 + Counter + + + Container_250 + HW_COUNTER_MMIO_OFFSET_8AB8 + + + sb_time + + + HW_COUNTER_MMIO_OFFSET_8AC0 + Counter + + + Container_251 + HW_COUNTER_MMIO_OFFSET_8AC0 + + + sb_time + + + HW_COUNTER_MMIO_OFFSET_8AC8 + Counter + + + Container_252 + HW_COUNTER_MMIO_OFFSET_8AC8 + + + sb_0.5_time + + + HW_COUNTER_MMIO_OFFSET_8AD0 + Counter + + + Container_253 + HW_COUNTER_MMIO_OFFSET_8AD0 + + + sb_0.5_time + + + reserved + Counter + + + Container_254 + CNTR_RESERVED_8AD8 + + + passthru + + + reserved + Counter + + + Container_255 + CNTR_RESERVED_8AE0 + + + passthru + + + HW_COUNTER_MMIO_OFFSET_8AE8 + Counter + + + Container_256 + HW_COUNTER_MMIO_OFFSET_8AE8 + + + mc_cycles + + + HW_COUNTER_MMIO_OFFSET_8AF0 + Counter + + + Container_257 + HW_COUNTER_MMIO_OFFSET_8AF0 + + + sb_time + + + Counts total MC writes. Virtual bandwidth counter based on PWM_WRDATA bulkcr sample.i.e TOTAL_WRITE_BANDWIDTH = total PWM_WRDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + Counter + + + Container_258 + TOTAL_WRITE_BANDWIDTH + + + bw_32B + + + Counts total MC reads. Virtual bandwidth counter based on PWM_RDDATA bulkcr sample.i.e TOTAL_READ_BANDWIDTH = total PWM_RDDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + Counter + + + Container_259 + TOTAL_READ_BANDWIDTH + + + bw_32B + + + The counter value is incremented as a function of the number of cores that reside in C0 and active. If N cores are simultaneously in C0, then the number of "clock ticks" that are incremented is N. Counts in XTAL units. Should be same as MSR ANY_CORE_C0 0x659. + Counter + + + Container_260 + IO_PKG_IA_C0_ANY_SUM + + + xtal_time + + + This counter increments whenever GT slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. Should be same as MSR ANY_GFXE_C0 0x65a + Counter + + + Container_261 + IO_PKG_GT_C0_ANY + + + xtal_time + + + This counter increments whenever GT slices or unslices are active and in C0 state and in overlap with one of the IA cores that is active and in C0. Counts in XTAL units. Should be same as MSR CORE_GFXE_OVERLAP_C0 0x65b + Counter + + + Container_262 + IO_PKG_GT_AND_IA_OVERLAP + + + xtal_time + + + Follow exactly the IO_PKG_GT_C0_ANY_SLICE. The only change is that they do +N (GT ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock.PKG_GT_C0_ANY_SLICE Counts clocks that any GT slice is active. Reference clock is XTAL. + Counter + + + Container_263 + IO_PKG_GT_C0_ANY_RATIO + + + xtal_time + + + This counter increments whenever MEDIA slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. + Counter + + + Container_264 + IO_PKG_MEDIA_C0_ANY + + + xtal_time + + + Follow exactly the PKG_MEDIA_C0_ANY_SLICE. The only change is that they do +N (media ratio) instead of +1 on the relevant clock edge.PKG_MEDIA_C0_ANY_SLICE Counts clocks that any Media slice is active.Counter rate is in Xtal Clock. + Counter + + + Container_265 + IO_PKG_MEDIA_C0_ANY_RATIO + + + xtal_time + + + follow exactly the PKG_IA_C0_ANYThe only change is that they do +N (Max IA ratio) instead of +1 on the relevant clock edge and conditions (while any LP_AT_C0[i]=1):PCU_CR_PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU += PKG_IA_C0_CURRENT_RATIO.RATIOPKG_IA_C0_CURRENT_RATIO.RATIO = MAX(IO_WP_CV_P_STATE[IA_RATIO]).Reference clock is XTAL. + Counter + + + Container_266 + IO_PKG_IA_C0_ANY_RATIO + + + xtal_time + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 0. + Counter + + + Container_267 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0 + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 1. + Counter + + + Container_267 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1 + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 2. + Counter + + + Container_268 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2 + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 0. + Counter + + + Container_268 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0_MMIO + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 1. + Counter + + + Container_269 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1_MMIO + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 2. + Counter + + + Container_269 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2_MMIO + + + slowloop + + + HW_COUNTER_MMIO_OFFSET_8B58 + Counter + + + Container_270 + HW_COUNTER_MMIO_OFFSET_8B58 + + + xtal_time + + + HW_COUNTER_MMIO_OFFSET_8B60 + Counter + + + Container_271 + HW_COUNTER_MMIO_OFFSET_8B60 + + + xtal_time + + + HW_COUNTER_MMIO_OFFSET_8B68 + Counter + + + Container_272 + HW_COUNTER_MMIO_OFFSET_8B68 + + + event_counter + + + HW_COUNTER_MMIO_OFFSET_8B68 + Counter + + + Container_272 + HW_COUNTER_MMIO_OFFSET_8B68_1 + + + event_counter + + + HW_COUNTER_MMIO_OFFSET_8B70 + Counter + + + Container_273 + HW_COUNTER_MMIO_OFFSET_8B70 + + + xtal_time + + + HW_COUNTER_MMIO_OFFSET_8B78 + Counter + + + Container_274 + HW_COUNTER_MMIO_OFFSET_8B78 + + + xtal_time + + + HW_COUNTER_MMIO_OFFSET_8B80 + Counter + + + Container_275 + HW_COUNTER_MMIO_OFFSET_8B80 + + + event_counter + + + HW_COUNTER_MMIO_OFFSET_8B80 + Counter + + + Container_275 + HW_COUNTER_MMIO_OFFSET_8B80_1 + + + event_counter + + + reserved + Counter + + + Container_276 + CNTR_RESERVED_0_8B88 + + + passthru + + + reserved + Counter + + + Container_277 + CNTR_RESERVED_1_to_110 + + + passthru + + + reserved + Counter + + + Container_278 + CNTR_RESERVED_1_to_110_1 + + + passthru + + + reserved + Counter + + + Container_279 + CNTR_RESERVED_1_to_110_2 + + + passthru + + + reserved + Counter + + + Container_280 + CNTR_RESERVED_1_to_110_3 + + + passthru + + + reserved + Counter + + + Container_281 + CNTR_RESERVED_1_to_110_4 + + + passthru + + + reserved + Counter + + + Container_282 + CNTR_RESERVED_1_to_110_5 + + + passthru + + + reserved + Counter + + + Container_283 + CNTR_RESERVED_1_to_110_6 + + + passthru + + + reserved + Counter + + + Container_284 + CNTR_RESERVED_1_to_110_7 + + + passthru + + + reserved + Counter + + + Container_285 + CNTR_RESERVED_1_to_110_8 + + + passthru + + + reserved + Counter + + + Container_286 + CNTR_RESERVED_1_to_110_9 + + + passthru + + + reserved + Counter + + + Container_287 + CNTR_RESERVED_1_to_110_10 + + + passthru + + + reserved + Counter + + + Container_288 + CNTR_RESERVED_1_to_110_11 + + + passthru + + + reserved + Counter + + + Container_289 + CNTR_RESERVED_1_to_110_12 + + + passthru + + + reserved + Counter + + + Container_290 + CNTR_RESERVED_1_to_110_13 + + + passthru + + + reserved + Counter + + + Container_291 + CNTR_RESERVED_1_to_110_14 + + + passthru + + + reserved + Counter + + + Container_292 + CNTR_RESERVED_1_to_110_15 + + + passthru + + + reserved + Counter + + + Container_293 + CNTR_RESERVED_1_to_110_16 + + + passthru + + + reserved + Counter + + + Container_294 + CNTR_RESERVED_1_to_110_17 + + + passthru + + + reserved + Counter + + + Container_295 + CNTR_RESERVED_1_to_110_18 + + + passthru + + + reserved + Counter + + + Container_296 + CNTR_RESERVED_1_to_110_19 + + + passthru + + + reserved + Counter + + + Container_297 + CNTR_RESERVED_1_to_110_20 + + + passthru + + + reserved + Counter + + + Container_298 + CNTR_RESERVED_1_to_110_21 + + + passthru + + + reserved + Counter + + + Container_299 + CNTR_RESERVED_1_to_110_22 + + + passthru + + + reserved + Counter + + + Container_300 + CNTR_RESERVED_1_to_110_23 + + + passthru + + + reserved + Counter + + + Container_301 + CNTR_RESERVED_1_to_110_24 + + + passthru + + + reserved + Counter + + + Container_302 + CNTR_RESERVED_1_to_110_25 + + + passthru + + + reserved + Counter + + + Container_303 + CNTR_RESERVED_1_to_110_26 + + + passthru + + + reserved + Counter + + + Container_304 + CNTR_RESERVED_1_to_110_27 + + + passthru + + + reserved + Counter + + + Container_305 + CNTR_RESERVED_1_to_110_28 + + + passthru + + + reserved + Counter + + + Container_306 + CNTR_RESERVED_1_to_110_29 + + + passthru + + + reserved + Counter + + + Container_307 + CNTR_RESERVED_1_to_110_30 + + + passthru + + + reserved + Counter + + + Container_308 + CNTR_RESERVED_1_to_110_31 + + + passthru + + + reserved + Counter + + + Container_309 + CNTR_RESERVED_1_to_110_32 + + + passthru + + + reserved + Counter + + + Container_310 + CNTR_RESERVED_1_to_110_33 + + + passthru + + + reserved + Counter + + + Container_311 + CNTR_RESERVED_1_to_110_34 + + + passthru + + + reserved + Counter + + + Container_312 + CNTR_RESERVED_1_to_110_35 + + + passthru + + + reserved + Counter + + + Container_313 + CNTR_RESERVED_1_to_110_36 + + + passthru + + + reserved + Counter + + + Container_314 + CNTR_RESERVED_1_to_110_37 + + + passthru + + + reserved + Counter + + + Container_315 + CNTR_RESERVED_1_to_110_38 + + + passthru + + + reserved + Counter + + + Container_316 + CNTR_RESERVED_1_to_110_39 + + + passthru + + + reserved + Counter + + + Container_317 + CNTR_RESERVED_1_to_110_40 + + + passthru + + + reserved + Counter + + + Container_318 + CNTR_RESERVED_1_to_110_41 + + + passthru + + + reserved + Counter + + + Container_319 + CNTR_RESERVED_1_to_110_42 + + + passthru + + + reserved + Counter + + + Container_320 + CNTR_RESERVED_1_to_110_43 + + + passthru + + + reserved + Counter + + + Container_321 + CNTR_RESERVED_1_to_110_44 + + + passthru + + + reserved + Counter + + + Container_322 + CNTR_RESERVED_1_to_110_45 + + + passthru + + + reserved + Counter + + + Container_323 + CNTR_RESERVED_1_to_110_46 + + + passthru + + + reserved + Counter + + + Container_324 + CNTR_RESERVED_1_to_110_47 + + + passthru + + + reserved + Counter + + + Container_325 + CNTR_RESERVED_1_to_110_48 + + + passthru + + + reserved + Counter + + + Container_326 + CNTR_RESERVED_1_to_110_49 + + + passthru + + + reserved + Counter + + + Container_327 + CNTR_RESERVED_1_to_110_50 + + + passthru + + + reserved + Counter + + + Container_328 + CNTR_RESERVED_1_to_110_51 + + + passthru + + + reserved + Counter + + + Container_329 + CNTR_RESERVED_1_to_110_52 + + + passthru + + + reserved + Counter + + + Container_330 + CNTR_RESERVED_1_to_110_53 + + + passthru + + + reserved + Counter + + + Container_331 + CNTR_RESERVED_1_to_110_54 + + + passthru + + + reserved + Counter + + + Container_332 + CNTR_RESERVED_1_to_110_55 + + + passthru + + + reserved + Counter + + + Container_333 + CNTR_RESERVED_1_to_110_56 + + + passthru + + + reserved + Counter + + + Container_334 + CNTR_RESERVED_1_to_110_57 + + + passthru + + + reserved + Counter + + + Container_335 + CNTR_RESERVED_1_to_110_58 + + + passthru + + + reserved + Counter + + + Container_336 + CNTR_RESERVED_1_to_110_59 + + + passthru + + + reserved + Counter + + + Container_337 + CNTR_RESERVED_1_to_110_60 + + + passthru + + + reserved + Counter + + + Container_338 + CNTR_RESERVED_1_to_110_61 + + + passthru + + + reserved + Counter + + + Container_339 + CNTR_RESERVED_1_to_110_62 + + + passthru + + + reserved + Counter + + + Container_340 + CNTR_RESERVED_1_to_110_63 + + + passthru + + + reserved + Counter + + + Container_341 + CNTR_RESERVED_1_to_110_64 + + + passthru + + + reserved + Counter + + + Container_342 + CNTR_RESERVED_1_to_110_65 + + + passthru + + + reserved + Counter + + + Container_343 + CNTR_RESERVED_1_to_110_66 + + + passthru + + + reserved + Counter + + + Container_344 + CNTR_RESERVED_1_to_110_67 + + + passthru + + + reserved + Counter + + + Container_345 + CNTR_RESERVED_1_to_110_68 + + + passthru + + + reserved + Counter + + + Container_346 + CNTR_RESERVED_1_to_110_69 + + + passthru + + + reserved + Counter + + + Container_347 + CNTR_RESERVED_1_to_110_70 + + + passthru + + + reserved + Counter + + + Container_348 + CNTR_RESERVED_1_to_110_71 + + + passthru + + + reserved + Counter + + + Container_349 + CNTR_RESERVED_1_to_110_72 + + + passthru + + + reserved + Counter + + + Container_350 + CNTR_RESERVED_1_to_110_73 + + + passthru + + + reserved + Counter + + + Container_351 + CNTR_RESERVED_1_to_110_74 + + + passthru + + + reserved + Counter + + + Container_352 + CNTR_RESERVED_1_to_110_75 + + + passthru + + + reserved + Counter + + + Container_353 + CNTR_RESERVED_1_to_110_76 + + + passthru + + + reserved + Counter + + + Container_354 + CNTR_RESERVED_1_to_110_77 + + + passthru + + + reserved + Counter + + + Container_355 + CNTR_RESERVED_1_to_110_78 + + + passthru + + + reserved + Counter + + + Container_356 + CNTR_RESERVED_1_to_110_79 + + + passthru + + + reserved + Counter + + + Container_357 + CNTR_RESERVED_1_to_110_80 + + + passthru + + + reserved + Counter + + + Container_358 + CNTR_RESERVED_1_to_110_81 + + + passthru + + + reserved + Counter + + + Container_359 + CNTR_RESERVED_1_to_110_82 + + + passthru + + + reserved + Counter + + + Container_360 + CNTR_RESERVED_1_to_110_83 + + + passthru + + + reserved + Counter + + + Container_361 + CNTR_RESERVED_1_to_110_84 + + + passthru + + + reserved + Counter + + + Container_362 + CNTR_RESERVED_1_to_110_85 + + + passthru + + + reserved + Counter + + + Container_363 + CNTR_RESERVED_1_to_110_86 + + + passthru + + + reserved + Counter + + + Container_364 + CNTR_RESERVED_1_to_110_87 + + + passthru + + + reserved + Counter + + + Container_365 + CNTR_RESERVED_1_to_110_88 + + + passthru + + + reserved + Counter + + + Container_366 + CNTR_RESERVED_1_to_110_89 + + + passthru + + + reserved + Counter + + + Container_367 + CNTR_RESERVED_1_to_110_90 + + + passthru + + + reserved + Counter + + + Container_368 + CNTR_RESERVED_1_to_110_91 + + + passthru + + + reserved + Counter + + + Container_369 + CNTR_RESERVED_1_to_110_92 + + + passthru + + + reserved + Counter + + + Container_370 + CNTR_RESERVED_1_to_110_93 + + + passthru + + + reserved + Counter + + + Container_371 + CNTR_RESERVED_1_to_110_94 + + + passthru + + + reserved + Counter + + + Container_372 + CNTR_RESERVED_1_to_110_95 + + + passthru + + + reserved + Counter + + + Container_373 + CNTR_RESERVED_1_to_110_96 + + + passthru + + + reserved + Counter + + + Container_374 + CNTR_RESERVED_1_to_110_97 + + + passthru + + + reserved + Counter + + + Container_375 + CNTR_RESERVED_1_to_110_98 + + + passthru + + + reserved + Counter + + + Container_376 + CNTR_RESERVED_1_to_110_99 + + + passthru + + + reserved + Counter + + + Container_377 + CNTR_RESERVED_1_to_110_100 + + + passthru + + + reserved + Counter + + + Container_378 + CNTR_RESERVED_1_to_110_101 + + + passthru + + + reserved + Counter + + + Container_379 + CNTR_RESERVED_1_to_110_102 + + + passthru + + + reserved + Counter + + + Container_380 + CNTR_RESERVED_1_to_110_103 + + + passthru + + + reserved + Counter + + + Container_381 + CNTR_RESERVED_1_to_110_104 + + + passthru + + + reserved + Counter + + + Container_382 + CNTR_RESERVED_1_to_110_105 + + + passthru + + + reserved + Counter + + + Container_383 + CNTR_RESERVED_1_to_110_106 + + + passthru + + + reserved + Counter + + + Container_384 + CNTR_RESERVED_1_to_110_107 + + + passthru + + + reserved + Counter + + + Container_385 + CNTR_RESERVED_1_to_110_108 + + + passthru + + + reserved + Counter + + + Container_386 + CNTR_RESERVED_1_to_110_109 + + + passthru + + + Average DDR BW over a time interval + Counter + + + Container_387 + VPU_MEMORY_BW + + + bw_1024B + + + Cycle count of amount of times VPU is in D0 active state + Counter + + + Container_387 + VPU_D0_ACTIVE_RESIDENCY + + + xtal_time_19_2 + + + Number of times VPU enters into D0 active state + Counter + + + Container_388 + VPU_D0_ACTIVE_ENTRY_COUNT + + + event_counter + + + Cycle count of amount of time VPU is in D0I2 active state + Counter + + + Container_388 + VPU_D0i2_ACTIVE_RESIDENCY + + + xtal_time_19_2 + + + Cycle count of amount of time VPU is in D0I2 Idle state + Counter + + + Container_389 + VPU_D0i2_IDLE_RESIDENCY + + + xtal_time_19_2 + + + Number of times VPU enters into D0I2 active state + Counter + + + Container_389 + VPU_D0i2_ACTIVE_ENTRY_COUNT + + + event_counter + + + Number of times VPU enters into D0I2 Idle state + Counter + + + Container_390 + VPU_D0i2_IDLE_ENTRY_COUNT + + + event_counter + + + Overall number of cycles for a context in RealTime priority + Counter + + + Container_390 + VPU_REALTIME_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + Overall number of cycles for a context in normal priority + Counter + + + Container_391 + VPU_NORMAL_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + Overall number of cycles for a context in focus priority + Counter + + + Container_391 + VPU_FOCUS_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + Overall number of cycles for a context in background priority + Counter + + + Container_392 + VPU_IDLE_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + reserved + Counter + + + Container_392 + VPU_SMPL_RESERVED0 + + + passthru + + + reserved + Counter + + + Container_393 + VPU_SMPL_RESERVED1 + + + passthru + + + reserved + Counter + + + Container_393 + VPU_RSVD0_8F34 + + + passthru + + + reserved + Counter + + + Container_394 + VPU_RSVD_1_to_25 + + + passthru + + + reserved + Counter + + + Container_395 + VPU_RSVD_1_to_25_1 + + + passthru + + + reserved + Counter + + + Container_396 + VPU_RSVD_1_to_25_2 + + + passthru + + + reserved + Counter + + + Container_397 + VPU_RSVD_1_to_25_3 + + + passthru + + + reserved + Counter + + + Container_398 + VPU_RSVD_1_to_25_4 + + + passthru + + + reserved + Counter + + + Container_399 + VPU_RSVD_1_to_25_5 + + + passthru + + + reserved + Counter + + + Container_400 + VPU_RSVD_1_to_25_6 + + + passthru + + + reserved + Counter + + + Container_401 + VPU_RSVD_1_to_25_7 + + + passthru + + + reserved + Counter + + + Container_402 + VPU_RSVD_1_to_25_8 + + + passthru + + + reserved + Counter + + + Container_403 + VPU_RSVD_1_to_25_9 + + + passthru + + + reserved + Counter + + + Container_404 + VPU_RSVD_1_to_25_10 + + + passthru + + + reserved + Counter + + + Container_405 + VPU_RSVD_1_to_25_11 + + + passthru + + + reserved + Counter + + + Container_406 + VPU_RSVD_1_to_25_12 + + + passthru + + + reserved + Counter + + + Container_407 + VPU_RSVD_1_to_25_13 + + + passthru + + + reserved + Counter + + + Container_408 + VPU_RSVD_1_to_25_14 + + + passthru + + + reserved + Counter + + + Container_409 + VPU_RSVD_1_to_25_15 + + + passthru + + + reserved + Counter + + + Container_410 + VPU_RSVD_1_to_25_16 + + + passthru + + + reserved + Counter + + + Container_411 + VPU_RSVD_1_to_25_17 + + + passthru + + + reserved + Counter + + + Container_412 + VPU_RSVD_1_to_25_18 + + + passthru + + + reserved + Counter + + + Container_413 + VPU_RSVD_1_to_25_19 + + + passthru + + + reserved + Counter + + + Container_414 + VPU_RSVD_1_to_25_20 + + + passthru + + + reserved + Counter + + + Container_415 + VPU_RSVD_1_to_25_21 + + + passthru + + + reserved + Counter + + + Container_416 + VPU_RSVD_1_to_25_22 + + + passthru + + + reserved + Counter + + + Container_417 + VPU_RSVD_1_to_25_23 + + + passthru + + + reserved + Counter + + + Container_418 + VPU_RSVD_1_to_25_24 + + + passthru + + + \ No newline at end of file diff --git a/xml/PTL/0/ptl_common.xml b/xml/PTL/0/ptl_common.xml new file mode 100644 index 0000000..bad19c8 --- /dev/null +++ b/xml/PTL/0/ptl_common.xml @@ -0,0 +1,275 @@ + + + + + counter + + s + + ANY + + + counter + + % + + ANY + + + counter + + % + + ANY + + + status + + V + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + status + + us + + ANY + + + status + + MHz + + ANY + + + counter + + J + + ANY + + + status + + V + + ANY + + + status + + C + + S8.7.0 + + + counter + + + + ANY + + + status + + V + + U8.1.7 + + + status + + A + + U10.7.3 + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + A + + U16.8.8 + + + status + + + + U9.1.8 + + + status + + % + + ANY + + + status + + + + U16.1.15 + + + status + + V + + ANY + + + status + + A + + U11.9.2 + + + counter + + J + + U32.18.14 + + + counter + + J + + ANY + + + counter + + cycles + + ANY + + + counter + + + counter + + cycles + + ANY + + + counter + + s + + ANY + + + counter + + cycles + + ANY + + + status + + + counter + + s + + ANY + + + status + + C + + ANY + + + counter + + s + + ANY + + + counter + + MB + + ANY + + + counter + + s + + ANY + + + string + + \ No newline at end of file diff --git a/xml/PTL/1/ptl_aggregator.xml b/xml/PTL/1/ptl_aggregator.xml new file mode 100644 index 0000000..e8bc80f --- /dev/null +++ b/xml/PTL/1/ptl_aggregator.xml @@ -0,0 +1,1565 @@ + +]> + + + &otherfile; + ptl + PTL fixed telemetry in Punit + 0x03086100 + ptl + 0 + + + Groupname 0x8000 + 64 + + Crystal clock count. Used as a reference count in converting many of the counters presented in this telemetry space. + XTAL + Counter + 64 + 0 + 63 + + + + Groupname 0x8008 + 64 + + Reference count for block cause counters. Counts the number of 1ms intervals during which PkgC entry was blocked at least once by any reason. To calculate percent blocked by a specific reason, divide corresponding block reason counter by this counter value. Sums all prevent cause to PKGC + PACKAGE_CSTATE_BLOCK_REFCNT + Counter + 32 + 0 + 31 + + + Candidate for removal. Reference count for wake cause counters. To calculate percent for each wake reason, divide by this number. Sums all wake cause from PKGC + PACKAGE_CSTATE_WAKE_REFCNT + Counter + 32 + 32 + 63 + + + + Groupname 0x8010 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 0. + PREVENT_PKGC_INTERNAL_0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by VPU. + PREVENT_PKGC_VPU_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8018 + 64 + + reserved + PREVENT_PKGC_RESERVED_0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 0. + PREVENT_PKGC_CHIPSET_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8020 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 1. + PREVENT_PKGC_CHIPSET_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Media 0. + PREVENT_PKGC_MEDIA_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8028 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by Media 1. + PREVENT_PKGC_MEDIA_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by GT. + PREVENT_PKGC_GT_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8030 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 1. + PREVENT_PKGC_INTERNAL_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 2. + PREVENT_PKGC_CHIPSET_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8038 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 3. + PREVENT_PKGC_CHIPSET_3 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by IPU. + PREVENT_PKGC_IPU_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8040 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 2. + PREVENT_PKGC_INTERNAL_2 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 3. + PREVENT_PKGC_INTERNAL_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8048 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by DE. + PREVENT_PKGC_DE_0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER0. + PREVENT_PKGC_CLUSTER0_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8050 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER1. + PREVENT_PKGC_CLUSTER1_0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by D2D_GDIE_CFI. + PREVENT_PKGC_GT_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8058 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by INTERNAL_4. + PREVENT_PKGC_INTERNAL_4 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by INTERNAL_5. + PREVENT_PKGC_INTERNAL_5 + Counter + 32 + 32 + 63 + + + + Groupname 0x8060 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by INTERNAL_6. + PREVENT_PKGC_INTERNAL_6 + Counter + 32 + 0 + 31 + + + reserved + PREVENT_PKGC6_RSVD_8064 + Counter + 32 + 32 + 63 + + + + Groupname 0x8068 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by VPU. + PREVENT_PKGC_VPU_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by IPU. + PREVENT_PKGC_IPU_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8070 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by DE. + PREVENT_PKGC_DE_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by IPU. + PREVENT_PKGC_IPU_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8078 + 64 + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER0 + PREVENT_PKGC_CLUSTER0_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER1. + PREVENT_PKGC_CLUSTER1_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8080 + 64 + + reserved + PREVENT_PKGC10_RSVD_8080 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC entry was blocked by DE. + PREVENT_PKGC_DE_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8088 + 64 + + Sample, not counter.PKGC can be disabled using several methods e.g DFX, fuses, BIOS.Pcode will update this register with resolved disabled PKGC mask.Encoding: bit 0 set: disable C. bit 1 set: disable C. bit 2 is set: disable C. bit 3 is set: disable C. bit 4 is set: disable CLower 5 bits are being used, rest are reserved. + PREVENT_PKGC_DFX_OTHERS + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals where PKGCx was prevented by other reasons, incremeting in sum of prevented PKGCx per 1ms. + PREVENT_PKGC_OTHER_REASONS + Counter + 32 + 32 + 63 + + + + Groupname 0x8090 + 64 + + Measures the residency in Cluster0 C0. Units are XTAL clocks. + CLUSTER0_C0_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8098 + 64 + + Measures the residency in Cluster1 C0. Units are XTAL clocks. + CLUSTER1_C0_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80a0 + 64 + + Measures the residency in Cluster0 C2. Units are XTAL clocks. + CLUSTER0_C2_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80a8 + 64 + + Measures the residency in Cluster1 C2. Units are XTAL clocks. + CLUSTER1_C2_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80b0 + 64 + + Measures the residency in Cluster0 C3. Units are XTAL clocks. + CLUSTER0_C3_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80b8 + 64 + + Measures the residency in Cluster1 C3. Units are XTAL clocks. + CLUSTER1_C3_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80c0 + 64 + + Measures the residency in Cluster0 C6 (LLC flushed). Units are XTAL clocks. Exposed in MSR 0x0ce in TSC units + CLUSTER0_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80c8 + 64 + + Measures the residency in Cluster1 C6. Units are XTAL clocks. + CLUSTER1_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80d0 + 64 + + Measures the residency in Package C-state C2. Units are XTAL clocks. Exposed in MSR 0x60d in TSC units + PACKAGE_CSTATE_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x80d8 + 64 + + Measures the residency in Package C-state C. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x80e0 + 64 + + Measures the residency in Package C-state C. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x80e8 + 64 + + Measures the residency in Package C-state C. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x80f0 + 64 + + Measures the residency in Package C-state C. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x80f8 + 64 + + Measures the residency in Package C-state C. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_5 + Counter + 64 + 0 + 63 + + + + Groupname 0x8100 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 0 + WAKE_REASON_HW_0 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: HW 1 + WAKE_REASON_HW_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8108 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 2 + WAKE_REASON_HW_2 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: HW 3 + WAKE_REASON_HW_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8110 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 4 + WAKE_REASON_HW_4 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: PECI + WAKE_REASON_HW_PECI + Counter + 32 + 32 + 63 + + + + Groupname 0x8118 + 64 + + Count the number of times exited from PkgC state due to the reason: Display 1 + WAKE_REASON_DISPLAY_1 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: Display 2 + WAKE_REASON_DISPLAY_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8120 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 8 + WAKE_REASON_HW_8 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: JTAG + WAKE_REASON_JTAG + Counter + 32 + 32 + 63 + + + + Groupname 0x8128 + 64 + + Count the number of times exited from PkgC state due to the reason: VPU + WAKE_REASON_VPU + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: IPU + WAKE_REASON_IPU + Counter + 32 + 32 + 63 + + + + Groupname 0x8130 + 64 + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_12 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_13 + Counter + 32 + 32 + 63 + + + + Groupname 0x8138 + 64 + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_14 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_15 + Counter + 32 + 32 + 63 + + + + Groupname 0x8140 + 64 + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_16 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: According to target + WAKE_REASON_HW_17 + Counter + 32 + 32 + 63 + + + + Groupname 0x8148 + 64 + + Count the number of times exited from PkgC state due to the reason: Chipset 1 + WAKE_REASON_CHIPSET_1 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: Chipset 2 + WAKE_REASON_CHIPSET_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8150 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 20 + WAKE_REASON_HW_20 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: HW 21 + WAKE_REASON_HW_21 + Counter + 32 + 32 + 63 + + + + Groupname 0x8158 + 64 + + Count the number of times exited from PkgC state due to the reason: HW_22 + WAKE_REASON_HW_22 + Counter + 32 + 0 + 31 + + + reserved + WAKE_REASON_RSVD_815C + Counter + 32 + 32 + 63 + + + + Groupname 0x8160 + 64 + + Measures the number of transitions to Cluster0 C0 + CLUSTER0_C0_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C0 + CLUSTER1_C0_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8168 + 64 + + Measures the number of transitions to Cluster0 C2 + CLUSTER0_C2_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C2 + CLUSTER1_C2_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8170 + 64 + + Measures the number of transitions to Cluster0 C3 + CLUSTER0_C3_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C3 + CLUSTER1_C3_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8178 + 64 + + Measures the number of transitions to Cluster0 C6 + CLUSTER0_C6_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C6 + CLUSTER1_C6_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8180 + 64 + + Measures the number of transitions to Package C-state C0 + PACKAGE_CSTATE_ENTRANCE_COUNTER_0 + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Package C-state C2 + PACKAGE_CSTATE_ENTRANCE_COUNTER_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8188 + 64 + + Measures the number of transitions to Package C-state C + PACKAGE_CSTATE_ENTRANCE_COUNTER_2 + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Package C-state C + PACKAGE_CSTATE_ENTRANCE_COUNTER_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8190 + 64 + + Measures the number of transitions to Package C-state C + PACKAGE_CSTATE_ENTRANCE_COUNTER_4 + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Package C-state C + PACKAGE_CSTATE_ENTRANCE_COUNTER_5 + Counter + 32 + 32 + 63 + + + + Groupname 0x8198 + 64 + + Measures the number of transitions to Package C-state C + PACKAGE_CSTATE_ENTRANCE_COUNTER_6 + Counter + 32 + 0 + 31 + + + reserved + PACKAGE_CSTATE_RSVD_819C + Counter + 32 + 32 + 63 + + + + Groupname 0x81a0 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC6_LTR_0 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC6_NDE_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x81a8 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC6_TNTE_0 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC6_DEMOTION_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x81b0 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC6_IRT_0 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC6_LTR_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81b8 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC6_NDE_1 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC6_TNTE_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81c0 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC6_DEMOTION_1 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC6_IRT_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81c8 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC10_LTR_0 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC10_NDE_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x81d0 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC10_TNTE_0 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC10_DEMOTION_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x81d8 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC10_IRT_0 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC10_LTR_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81e0 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC10_NDE_1 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC10_TNTE_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81e8 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC10_DEMOTION_1 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC10_IRT_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81f0 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC10_LTR_2 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC10_NDE_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x81f8 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC10_TNTE_2 + Counter + 32 + 0 + 31 + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC10_DEMOTION_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8200 + 64 + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC10_IRT_2 + Counter + 32 + 0 + 31 + + + reserved + PREVENT_RSVD_8204 + Counter + 32 + 32 + 63 + + + + Groupname 0x8208 + 64 + + Current display latency tolerance + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_DISPLAY + Counter + 32 + 0 + 31 + + + Current IPU latency tolerance + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_IPU + Counter + 32 + 32 + 63 + + + + Groupname 0x8210 + 64 + + Current PCH latency tolerance + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_PCH + Counter + 32 + 0 + 31 + + + Worst-case LTR Threshold for PC + PKGC6_LTR_THRESHOLDS_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8218 + 64 + + Worst-case LTR Threshold for PC + PKGC6_LTR_THRESHOLDS_1 + Counter + 32 + 0 + 31 + + + Worst-case LTR Threshold for PC + PKGC10_LTR_THRESHOLDS_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8220 + 64 + + Worst-case LTR Threshold for PC + PKGC10_LTR_THRESHOLDS_1 + Counter + 32 + 0 + 31 + + + Worst-case LTR Threshold for PC + PKGC10_LTR_THRESHOLDS_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8228 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8230 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8238 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8240 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8248 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8250 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8258 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8260 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8268 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8270 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8278 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8280 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8288 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8290 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x8298 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82a0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82a8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82b0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82b8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82c0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82c8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82d0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82d8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + + Groupname 0x82e0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_24 + Counter + 64 + 0 + 63 + + + \ No newline at end of file diff --git a/xml/PTL/1/ptl_aggregator_interface.xml b/xml/PTL/1/ptl_aggregator_interface.xml new file mode 100644 index 0000000..bb2d9dc --- /dev/null +++ b/xml/PTL/1/ptl_aggregator_interface.xml @@ -0,0 +1,2004 @@ + + + + + + + + + float + + parameter_0 + + $parameter_0 / ( 38.4 * 1e6 ) + + + float + + parameter_0 + parameter_1 + + $parameter_0 / $parameter_1 * 100 + + + float + + parameter_0 + parameter_1 + + $parameter_0 / $parameter_1 * 100 + + + float + + parameter_0 + + $parameter_0 * 0.0025 + + + float + + parameter_0 + + $parameter_0 * 64 / 1e6 + + + float + + parameter_0 + + $parameter_0 / 1e6 + + + float + + parameter_0 + + $parameter_0 * 32 / 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + ( 49 + $parameter_0 ) * 0.005 + + + integer + + parameter_0 + + ( ( ( 1 - ( ( $parameter_0 >> 7 ) & 0x1 ) ) * ( $parameter_0 & 0xff ) ) - ( ( ( $parameter_0 >> 7 ) & 0x1 ) * ( ( ( $parameter_0 & 0x7f ) ^ 0x7f ) + 1 ) ) ) + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + ( $parameter_0 & 0xff ) / ( 2**7 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x3ff ) / ( 2**3 ) + + + float + + parameter_0 + + $parameter_0 * 0.1 + + + float + + parameter_0 + + $parameter_0 * 0.01667 + + + float + + parameter_0 + + $parameter_0 * 0.025 + + + float + + parameter_0 + + $parameter_0 * 0.033 + + + float + + parameter_0 + + $parameter_0 * 0.05 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**8 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x1ff ) / ( 2**8 ) + + + float + + parameter_0 + + $parameter_0 * 100 / 128 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**15 ) + + + float + + parameter_0 + + $parameter_0 * 0.002 + + + float + + parameter_0 + + ( $parameter_0 & 0x7ff ) / ( 2**2 ) + + + float + + parameter_0 + + ( $parameter_0 & 0xffffffff ) / ( 2**14 ) + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + $parameter_0 * 64 + + + float + + parameter_0 + + $parameter_0 * 0.025 * 33.33 + + + float + + parameter_0 + + $parameter_0 / 400 * 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 * 1000 + + + float + + parameter_0 + + $parameter_0 / 10 + + + float + + parameter_0 + + $parameter_0 / 200 * 1e6 + + + float + + parameter_0 + + $parameter_0 * 1024 / 1e6 + + + float + + parameter_0 + + $parameter_0 / ( 19.2 * 1e6 ) + + + integer + + parameter_0 + + $parameter_0 + + + + ptl + PTL fixed telemetry in Punit + 0x03086100 + Public + 10 + 2026-02-27 + + + Crystal clock count. Used as a reference count in converting many of the counters presented in this telemetry space. + Counter + + + Container_0 + XTAL + + + passthru + + + Reference count for block cause counters. Counts the number of 1ms intervals during which PkgC entry was blocked at least once by any reason. To calculate percent blocked by a specific reason, divide corresponding block reason counter by this counter value. Sums all prevent cause to PKGC + Counter + + + Container_1 + PACKAGE_CSTATE_BLOCK_REFCNT + + + event_counter + + + Candidate for removal. Reference count for wake cause counters. To calculate percent for each wake reason, divide by this number. Sums all wake cause from PKGC + Counter + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + event_counter + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 0. + Counter + + + Container_2 + PREVENT_PKGC_INTERNAL_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by VPU. + Counter + + + Container_2 + PREVENT_PKGC_VPU_0 + + + slowloop + + + reserved + Counter + + + Container_3 + PREVENT_PKGC_RESERVED_0 + + + passthru + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 0. + Counter + + + Container_3 + PREVENT_PKGC_CHIPSET_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 1. + Counter + + + Container_4 + PREVENT_PKGC_CHIPSET_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Media 0. + Counter + + + Container_4 + PREVENT_PKGC_MEDIA_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Media 1. + Counter + + + Container_5 + PREVENT_PKGC_MEDIA_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by GT. + Counter + + + Container_5 + PREVENT_PKGC_GT_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 1. + Counter + + + Container_6 + PREVENT_PKGC_INTERNAL_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 2. + Counter + + + Container_6 + PREVENT_PKGC_CHIPSET_2 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Chipset 3. + Counter + + + Container_7 + PREVENT_PKGC_CHIPSET_3 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by IPU. + Counter + + + Container_7 + PREVENT_PKGC_IPU_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 2. + Counter + + + Container_8 + PREVENT_PKGC_INTERNAL_2 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by Internal 3. + Counter + + + Container_8 + PREVENT_PKGC_INTERNAL_3 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by DE. + Counter + + + Container_9 + PREVENT_PKGC_DE_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER0. + Counter + + + Container_9 + PREVENT_PKGC_CLUSTER0_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER1. + Counter + + + Container_10 + PREVENT_PKGC_CLUSTER1_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by D2D_GDIE_CFI. + Counter + + + Container_10 + PREVENT_PKGC_GT_2 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by INTERNAL_4. + Counter + + + Container_11 + PREVENT_PKGC_INTERNAL_4 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by INTERNAL_5. + Counter + + + Container_11 + PREVENT_PKGC_INTERNAL_5 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by INTERNAL_6. + Counter + + + Container_12 + PREVENT_PKGC_INTERNAL_6 + + + slowloop + + + reserved + Counter + + + Container_12 + PREVENT_PKGC6_RSVD_8064 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by VPU. + Counter + + + Container_13 + PREVENT_PKGC_VPU_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by IPU. + Counter + + + Container_13 + PREVENT_PKGC_IPU_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by DE. + Counter + + + Container_14 + PREVENT_PKGC_DE_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by IPU. + Counter + + + Container_14 + PREVENT_PKGC_IPU_2 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER0 + Counter + + + Container_15 + PREVENT_PKGC_CLUSTER0_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by CLUSTER1. + Counter + + + Container_15 + PREVENT_PKGC_CLUSTER1_1 + + + slowloop + + + reserved + Counter + + + Container_16 + PREVENT_PKGC10_RSVD_8080 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC entry was blocked by DE. + Counter + + + Container_16 + PREVENT_PKGC_DE_2 + + + slowloop + + + Sample, not counter.PKGC can be disabled using several methods e.g DFX, fuses, BIOS.Pcode will update this register with resolved disabled PKGC mask.Encoding: bit 0 set: disable C. bit 1 set: disable C. bit 2 is set: disable C. bit 3 is set: disable C. bit 4 is set: disable CLower 5 bits are being used, rest are reserved. + Counter + + + Container_17 + PREVENT_PKGC_DFX_OTHERS + + + slowloop + + + Counts the number of 1ms intervals where PKGCx was prevented by other reasons, incremeting in sum of prevented PKGCx per 1ms. + Counter + + + Container_17 + PREVENT_PKGC_OTHER_REASONS + + + slowloop + + + Measures the residency in Cluster0 C0. Units are XTAL clocks. + Counter + + + Container_18 + CLUSTER0_C0_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C0. Units are XTAL clocks. + Counter + + + Container_19 + CLUSTER1_C0_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster0 C2. Units are XTAL clocks. + Counter + + + Container_20 + CLUSTER0_C2_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C2. Units are XTAL clocks. + Counter + + + Container_21 + CLUSTER1_C2_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster0 C3. Units are XTAL clocks. + Counter + + + Container_22 + CLUSTER0_C3_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C3. Units are XTAL clocks. + Counter + + + Container_23 + CLUSTER1_C3_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster0 C6 (LLC flushed). Units are XTAL clocks. Exposed in MSR 0x0ce in TSC units + Counter + + + Container_24 + CLUSTER0_C6_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C6. Units are XTAL clocks. + Counter + + + Container_25 + CLUSTER1_C6_RESIDENCY + + + xtal_time + + + Measures the residency in Package C-state C2. Units are XTAL clocks. Exposed in MSR 0x60d in TSC units + Counter + + + Container_26 + PACKAGE_CSTATE_RESIDENCY_0 + + + xtal_time + + + Measures the residency in Package C-state C. Units are XTAL clocks. + Counter + + + Container_27 + PACKAGE_CSTATE_RESIDENCY_1 + + + xtal_time + + + Measures the residency in Package C-state C. Units are XTAL clocks. + Counter + + + Container_28 + PACKAGE_CSTATE_RESIDENCY_2 + + + xtal_time + + + Measures the residency in Package C-state C. Units are XTAL clocks. + Counter + + + Container_29 + PACKAGE_CSTATE_RESIDENCY_3 + + + xtal_time + + + Measures the residency in Package C-state C. Units are XTAL clocks. + Counter + + + Container_30 + PACKAGE_CSTATE_RESIDENCY_4 + + + xtal_time + + + Measures the residency in Package C-state C. Units are XTAL clocks. + Counter + + + Container_31 + PACKAGE_CSTATE_RESIDENCY_5 + + + xtal_time + + + Count the number of times exited from PkgC state due to the reason: HW 0 + Counter + + + Container_32 + WAKE_REASON_HW_0 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 1 + Counter + + + Container_32 + WAKE_REASON_HW_1 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 2 + Counter + + + Container_33 + WAKE_REASON_HW_2 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 3 + Counter + + + Container_33 + WAKE_REASON_HW_3 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 4 + Counter + + + Container_34 + WAKE_REASON_HW_4 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: PECI + Counter + + + Container_34 + WAKE_REASON_HW_PECI + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Display 1 + Counter + + + Container_35 + WAKE_REASON_DISPLAY_1 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Display 2 + Counter + + + Container_35 + WAKE_REASON_DISPLAY_2 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 8 + Counter + + + Container_36 + WAKE_REASON_HW_8 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: JTAG + Counter + + + Container_36 + WAKE_REASON_JTAG + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: VPU + Counter + + + Container_37 + WAKE_REASON_VPU + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: IPU + Counter + + + Container_37 + WAKE_REASON_IPU + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_38 + WAKE_REASON_HW_12 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_38 + WAKE_REASON_HW_13 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_39 + WAKE_REASON_HW_14 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_39 + WAKE_REASON_HW_15 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_40 + WAKE_REASON_HW_16 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: According to target + Counter + + + Container_40 + WAKE_REASON_HW_17 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Chipset 1 + Counter + + + Container_41 + WAKE_REASON_CHIPSET_1 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Chipset 2 + Counter + + + Container_41 + WAKE_REASON_CHIPSET_2 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 20 + Counter + + + Container_42 + WAKE_REASON_HW_20 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 21 + Counter + + + Container_42 + WAKE_REASON_HW_21 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW_22 + Counter + + + Container_43 + WAKE_REASON_HW_22 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + reserved + Counter + + + Container_43 + WAKE_REASON_RSVD_815C + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Measures the number of transitions to Cluster0 C0 + Counter + + + Container_44 + CLUSTER0_C0_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C0 + Counter + + + Container_44 + CLUSTER1_C0_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster0 C2 + Counter + + + Container_45 + CLUSTER0_C2_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C2 + Counter + + + Container_45 + CLUSTER1_C2_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster0 C3 + Counter + + + Container_46 + CLUSTER0_C3_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C3 + Counter + + + Container_46 + CLUSTER1_C3_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster0 C6 + Counter + + + Container_47 + CLUSTER0_C6_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C6 + Counter + + + Container_47 + CLUSTER1_C6_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Package C-state C0 + Counter + + + Container_48 + PACKAGE_CSTATE_ENTRANCE_COUNTER_0 + + + event_counter + + + Measures the number of transitions to Package C-state C2 + Counter + + + Container_48 + PACKAGE_CSTATE_ENTRANCE_COUNTER_1 + + + event_counter + + + Measures the number of transitions to Package C-state C + Counter + + + Container_49 + PACKAGE_CSTATE_ENTRANCE_COUNTER_2 + + + event_counter + + + Measures the number of transitions to Package C-state C + Counter + + + Container_49 + PACKAGE_CSTATE_ENTRANCE_COUNTER_3 + + + event_counter + + + Measures the number of transitions to Package C-state C + Counter + + + Container_50 + PACKAGE_CSTATE_ENTRANCE_COUNTER_4 + + + event_counter + + + Measures the number of transitions to Package C-state C + Counter + + + Container_50 + PACKAGE_CSTATE_ENTRANCE_COUNTER_5 + + + event_counter + + + Measures the number of transitions to Package C-state C + Counter + + + Container_51 + PACKAGE_CSTATE_ENTRANCE_COUNTER_6 + + + event_counter + + + reserved + Counter + + + Container_51 + PACKAGE_CSTATE_RSVD_819C + + + passthru + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_52 + PREVENT_PKGC6_LTR_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_52 + PREVENT_PKGC6_NDE_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_53 + PREVENT_PKGC6_TNTE_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_53 + PREVENT_PKGC6_DEMOTION_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_54 + PREVENT_PKGC6_IRT_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_54 + PREVENT_PKGC6_LTR_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_55 + PREVENT_PKGC6_NDE_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_55 + PREVENT_PKGC6_TNTE_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_56 + PREVENT_PKGC6_DEMOTION_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_56 + PREVENT_PKGC6_IRT_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_57 + PREVENT_PKGC10_LTR_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_57 + PREVENT_PKGC10_NDE_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_58 + PREVENT_PKGC10_TNTE_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_58 + PREVENT_PKGC10_DEMOTION_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_59 + PREVENT_PKGC10_IRT_0 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_59 + PREVENT_PKGC10_LTR_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_60 + PREVENT_PKGC10_NDE_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_60 + PREVENT_PKGC10_TNTE_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_61 + PREVENT_PKGC10_DEMOTION_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_61 + PREVENT_PKGC10_IRT_1 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_62 + PREVENT_PKGC10_LTR_2 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_62 + PREVENT_PKGC10_NDE_2 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_63 + PREVENT_PKGC10_TNTE_2 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_63 + PREVENT_PKGC10_DEMOTION_2 + + + slowloop + + + PC WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_64 + PREVENT_PKGC10_IRT_2 + + + slowloop + + + reserved + Counter + + + Container_64 + PREVENT_RSVD_8204 + + + passthru + + + Current display latency tolerance + Counter + + + Container_65 + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_DISPLAY + + + ltr + + + Current IPU latency tolerance + Counter + + + Container_65 + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_IPU + + + ltr + + + Current PCH latency tolerance + Counter + + + Container_66 + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_PCH + + + ltr + + + Worst-case LTR Threshold for PC + Counter + + + Container_66 + PKGC6_LTR_THRESHOLDS_0 + + + ltr + + + Worst-case LTR Threshold for PC + Counter + + + Container_67 + PKGC6_LTR_THRESHOLDS_1 + + + ltr + + + Worst-case LTR Threshold for PC + Counter + + + Container_67 + PKGC10_LTR_THRESHOLDS_0 + + + ltr + + + Worst-case LTR Threshold for PC + Counter + + + Container_68 + PKGC10_LTR_THRESHOLDS_1 + + + ltr + + + Worst-case LTR Threshold for PC + Counter + + + Container_68 + PKGC10_LTR_THRESHOLDS_2 + + + ltr + + + reserved + Counter + + + Container_69 + FIXED_CNTR_RESERVED_1_to_24 + + + passthru + + + reserved + Counter + + + Container_70 + FIXED_CNTR_RESERVED_1_to_24_1 + + + passthru + + + reserved + Counter + + + Container_71 + FIXED_CNTR_RESERVED_1_to_24_2 + + + passthru + + + reserved + Counter + + + Container_72 + FIXED_CNTR_RESERVED_1_to_24_3 + + + passthru + + + reserved + Counter + + + Container_73 + FIXED_CNTR_RESERVED_1_to_24_4 + + + passthru + + + reserved + Counter + + + Container_74 + FIXED_CNTR_RESERVED_1_to_24_5 + + + passthru + + + reserved + Counter + + + Container_75 + FIXED_CNTR_RESERVED_1_to_24_6 + + + passthru + + + reserved + Counter + + + Container_76 + FIXED_CNTR_RESERVED_1_to_24_7 + + + passthru + + + reserved + Counter + + + Container_77 + FIXED_CNTR_RESERVED_1_to_24_8 + + + passthru + + + reserved + Counter + + + Container_78 + FIXED_CNTR_RESERVED_1_to_24_9 + + + passthru + + + reserved + Counter + + + Container_79 + FIXED_CNTR_RESERVED_1_to_24_10 + + + passthru + + + reserved + Counter + + + Container_80 + FIXED_CNTR_RESERVED_1_to_24_11 + + + passthru + + + reserved + Counter + + + Container_81 + FIXED_CNTR_RESERVED_1_to_24_12 + + + passthru + + + reserved + Counter + + + Container_82 + FIXED_CNTR_RESERVED_1_to_24_13 + + + passthru + + + reserved + Counter + + + Container_83 + FIXED_CNTR_RESERVED_1_to_24_14 + + + passthru + + + reserved + Counter + + + Container_84 + FIXED_CNTR_RESERVED_1_to_24_15 + + + passthru + + + reserved + Counter + + + Container_85 + FIXED_CNTR_RESERVED_1_to_24_16 + + + passthru + + + reserved + Counter + + + Container_86 + FIXED_CNTR_RESERVED_1_to_24_17 + + + passthru + + + reserved + Counter + + + Container_87 + FIXED_CNTR_RESERVED_1_to_24_18 + + + passthru + + + reserved + Counter + + + Container_88 + FIXED_CNTR_RESERVED_1_to_24_19 + + + passthru + + + reserved + Counter + + + Container_89 + FIXED_CNTR_RESERVED_1_to_24_20 + + + passthru + + + reserved + Counter + + + Container_90 + FIXED_CNTR_RESERVED_1_to_24_21 + + + passthru + + + reserved + Counter + + + Container_91 + FIXED_CNTR_RESERVED_1_to_24_22 + + + passthru + + + reserved + Counter + + + Container_92 + FIXED_CNTR_RESERVED_1_to_24_23 + + + passthru + + + \ No newline at end of file diff --git a/xml/PTL/1/ptl_common.xml b/xml/PTL/1/ptl_common.xml new file mode 100644 index 0000000..bad19c8 --- /dev/null +++ b/xml/PTL/1/ptl_common.xml @@ -0,0 +1,275 @@ + + + + + counter + + s + + ANY + + + counter + + % + + ANY + + + counter + + % + + ANY + + + status + + V + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + status + + us + + ANY + + + status + + MHz + + ANY + + + counter + + J + + ANY + + + status + + V + + ANY + + + status + + C + + S8.7.0 + + + counter + + + + ANY + + + status + + V + + U8.1.7 + + + status + + A + + U10.7.3 + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + A + + U16.8.8 + + + status + + + + U9.1.8 + + + status + + % + + ANY + + + status + + + + U16.1.15 + + + status + + V + + ANY + + + status + + A + + U11.9.2 + + + counter + + J + + U32.18.14 + + + counter + + J + + ANY + + + counter + + cycles + + ANY + + + counter + + + counter + + cycles + + ANY + + + counter + + s + + ANY + + + counter + + cycles + + ANY + + + status + + + counter + + s + + ANY + + + status + + C + + ANY + + + counter + + s + + ANY + + + counter + + MB + + ANY + + + counter + + s + + ANY + + + string + + \ No newline at end of file diff --git a/xml/pmt.xml b/xml/pmt.xml index c26b2fb..1b08ca8 100644 --- a/xml/pmt.xml +++ b/xml/pmt.xml @@ -313,5 +313,29 @@ cwf_aggregator_interface.xml + + 2026-02-27 + production + PTL normal telemetry in Punit + + PTL/0 + ptl + ptl_common.xml + ptl_aggregator.xml + ptl_aggregator_interface.xml + + + + 2026-02-27 + production + PTL fixed telemetry in Punit + + PTL/1 + ptl + ptl_common.xml + ptl_aggregator.xml + ptl_aggregator_interface.xml + +