Wrong SDC constraints

[Paebbels]

You should not set false_path constraints on clock boundaries.
You need to use set_max_delay ... -DataPathOnly.

[olofk]

You are absolutely right. My mistake.

Do you know any good source for this information btw? I tell this to people all the time but I can't remember anymore where I learned it so it would be good to point people to some explanation

[Paebbels]

I did long research to collect all the knowledge that is now merged in PoC's CDC circuits. They are shipped with constraints.

The Clifford Cumming articles about clocks, resets etc. are good. There was a new whitepaper (2018) from Aldec covering different FPGA technologies and CDC problems.

[olofk]

It would make a lot of sense to reuse those, but I would likely need to reimplement in Verilog (probably no big deal). If I get the time to do that, would you like to have verilog versions in PoC or should I host them in a separate repo?
Are these the ones you are talking about btw? https://github.com/VLSI-EDA/PoC/tree/master/src/misc/sync Haven't looked around in PoC for a while so I'm getting a bit lost in all the RTL :)

[Paebbels]

Currently PoC has not so much Verilog code, but it's not limited to VHDL only. If you like, feel free to create a MG with matching Verilog versions.

The XDCs / SDCs should apply to the same entity, right?

[olofk]

Cool. I hope to find some time to do that and also restart my experiment in creating FuseSoC packages as well. It makes a lot more sense to reuse something that has been well-tested rather than me maintaining cdc_utils which is not nearly as complete. I will reach out to you when I get down to do some work

And yes, the constraint matching should work the same.

For now, I'll just fix the wrong constraint here