I have the following simple example that fails:
typedef struct packed {
logic [31:0] v;
} value_t;
module M(input value_t foo);
initial assert (foo.v == 123);
endmodule
module main;
M my_instance( .foo('{123}) );
endmodule
With the following error:
$ ebmc --systemverilog --bound 3 port_typedef1.sv
Parsing port_typdef1.sv
Converting
Type-checking Verilog::M
file port_typdef1.sv line 5: type symbol Verilog::M.value_t not found
CONVERSION ERROR