From edb90a49fea010d1dcb0a0088ccb652e58fc7e3d Mon Sep 17 00:00:00 2001 From: Matthew McGowan Date: Thu, 27 Feb 2025 17:38:11 -0800 Subject: [PATCH] fix: USB CDC/MDC on Cygnet --- ports/stm/boards/STM32L433_boot.ld | 2 +- .../stm/common-hal/microcontroller/__init__.c | 18 ++--- ports/stm/peripherals/periph.h | 4 ++ ports/stm/peripherals/stm32l4/clocks.c | 24 ++++--- ports/stm/supervisor/internal_flash.c | 8 +-- ports/stm/supervisor/usb.c | 67 ++++++++++--------- 6 files changed, 69 insertions(+), 54 deletions(-) diff --git a/ports/stm/boards/STM32L433_boot.ld b/ports/stm/boards/STM32L433_boot.ld index 161d883160c2..686547a8ce6e 100644 --- a/ports/stm/boards/STM32L433_boot.ld +++ b/ports/stm/boards/STM32L433_boot.ld @@ -7,7 +7,7 @@ MEMORY { FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* entire flash */ FLASH_ISR (rx) : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */ - FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 192K-64K-4K /* For now, limit to 1MB so that bank switching is still possible. */ + FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 192K-64K-4K FLASH_FS (rw) : ORIGIN = 0x08030000, LENGTH = 60K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K } diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index 5a0f0ed92945..aef3b8c51f31 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -31,12 +31,14 @@ void common_hal_mcu_delay_us(uint32_t delay) { SysTick->CTRL = 0UL; } -volatile uint32_t nesting_count = 0; +static volatile uint32_t nesting_count = 0; +// 32-bit increments void common_hal_mcu_disable_interrupts(void) { - __disable_irq(); - __DMB(); - nesting_count++; + if (++nesting_count==1) { + __disable_irq(); + __DMB(); + } } void common_hal_mcu_enable_interrupts(void) { @@ -44,12 +46,10 @@ void common_hal_mcu_enable_interrupts(void) { // This is very very bad because it means there was mismatched disable/enables. reset_into_safe_mode(SAFE_MODE_INTERRUPT_ERROR); } - nesting_count--; - if (nesting_count > 0) { - return; + if (--nesting_count == 0) { + __DMB(); + __enable_irq(); } - __DMB(); - __enable_irq(); } static bool next_reset_to_bootloader = false; diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index 4960125d90f1..8a1c2ceccffa 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -137,3 +137,7 @@ typedef struct { #define HAS_BASIC_TIM 0 #include "stm32h7/stm32h743xx/periph.h" #endif + +#if !defined(HAS_DAC) +#error Unknown MCU +#endif \ No newline at end of file diff --git a/ports/stm/peripherals/stm32l4/clocks.c b/ports/stm/peripherals/stm32l4/clocks.c index d4cf3312efe1..04a2cbb7015c 100644 --- a/ports/stm/peripherals/stm32l4/clocks.c +++ b/ports/stm/peripherals/stm32l4/clocks.c @@ -9,9 +9,9 @@ #include // L4 Series -#ifdef STM32L4R5xx +#if defined(STM32L4R5xx) #include "stm32l4/stm32l4r5xx/clocks.h" -#elif STM32L433xx +#elif defined(STM32L433xx) #include "stm32l4/stm32l433xx/clocks.h" #else #error Please add other MCUs here so that they are not silently ignored due to #define typos @@ -46,18 +46,18 @@ void stm32_peripherals_clocks_init(void) { /** Configure the main internal regulator output voltage */ - #if STM32L4R5xx + #if defined(STM32L4R5xx) if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } - #elif STM32L433xx + #elif defined(STM32L433xx) if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { Error_Handler(); } #endif /* Activate PLL with MSI , stabilizied via PLL by LSE */ - #ifdef STM32L4R5xx + #if defined(STM32L4R5xx) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -70,7 +70,7 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.PLL.PLLN = 30; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - #elif STM32L433xx + #elif defined(STM32L433xx) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.MSIState = RCC_MSI_ON; @@ -84,6 +84,8 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + #else + #error Unknown MCU #endif HAL_CHECK(HAL_RCC_OscConfig(&RCC_OscInitStruct)); @@ -100,10 +102,12 @@ void stm32_peripherals_clocks_init(void) { RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - #ifdef STM32L4R5xx + #if defined(STM32L4R5xx) HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3)); - #elif STM32L433xx + #elif defined(STM32L433xx) HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4)); + #else + #error Please expand the conditional compilation to set the default flash latency #endif /* AHB prescaler divider at 1 as second step */ @@ -115,9 +119,9 @@ void stm32_peripherals_clocks_init(void) { /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ADC; - #ifdef STM32L4R5xx + #if defined(STM32L4R5xx) PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; - #elif STM32L433xx + #elif defined(STM32L433xx) PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; #endif PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index f6d687f08fd3..3d7098c6490c 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -69,13 +69,13 @@ static const flash_layout_t flash_layout[] = { }; static uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); -#elif defined(STM32L4R5XX) +#elif defined(STM32L4R5xx) static const flash_layout_t flash_layout[] = { { 0x08100000, 0x1000, 256 }, }; static uint8_t _flash_cache[0x1000] __attribute__((aligned(4))); -#elif defined(STM32L433XX) +#elif defined(STM32L433xx) static const flash_layout_t flash_layout[] = { { 0x08000000, 0x0800, 128 }, }; @@ -181,10 +181,10 @@ void port_internal_flash_flush(void) { // set up for erase FLASH_EraseInitTypeDef EraseInitStruct = {}; #if CPY_STM32L4 - #if defined(STM32L4R5XX) + #if defined(STM32L4R5xx) EraseInitStruct.TypeErase = TYPEERASE_PAGES; EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode - #elif defined(STM32L433XX) + #elif defined(STM32L433xx) EraseInitStruct.TypeErase = TYPEERASE_PAGES; EraseInitStruct.Banks = FLASH_BANK_1; #endif diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 86acdc49b34e..7ea823028971 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -14,34 +14,33 @@ #include "common-hal/microcontroller/Pin.h" static void init_usb_vbus_sense(void) { - #if (BOARD_NO_VBUS_SENSE) - // Disable VBUS sensing - #ifdef USB_OTG_GCCFG_VBDEN - // Deactivate VBUS Sensing B - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; - - #if (BOARD_NO_USB_OTG_ID_SENSE) - USB_OTG_FS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD; - USB_OTG_FS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; - #endif - - // B-peripheral session valid override enable - USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - #elif !defined(STM32L433XX) - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; - #endif + // Disable VBUS sensing + #ifdef USB_OTG_GCCFG_VBDEN + // Deactivate VBUS Sensing B + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + #if (BOARD_NO_USB_OTG_ID_SENSE) + USB_OTG_FS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD; + USB_OTG_FS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + #endif // BOARD_NO_USB_OTG_ID_SENSE + + // B-peripheral session valid override enable + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + #endif #else - // Enable VBUS hardware sensing - #ifdef USB_OTG_GCCFG_VBDEN - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; - #else - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // B Device sense - #endif + // Enable VBUS hardware sensing + #ifdef USB_OTG_GCCFG_VBDEN + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; + #else + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // B Device sense + #endif #endif } @@ -69,12 +68,15 @@ void init_usb_hardware(void) { GPIO_InitStruct.Pull = GPIO_NOPULL; #if CPY_STM32H7 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5XX) + #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5xx) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - #elif defined(STM32L433XX) + #elif defined(STM32L433xx) GPIO_InitStruct.Alternate = GPIO_AF10_USB_FS; + #else + #error Unknown MCU #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + never_reset_pin_number(0, 11); never_reset_pin_number(0, 12); claim_pin(0, 11); @@ -119,7 +121,7 @@ void init_usb_hardware(void) { #if CPY_STM32H7 HAL_PWREx_EnableUSBVoltageDetector(); __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); - #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5XX) + #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5xx) /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); #else @@ -129,6 +131,11 @@ void init_usb_hardware(void) { init_usb_vbus_sense(); } -void OTG_FS_IRQHandler(void) { +#if defined(STM32L433xx) +void USB_IRQHandler(void) +#else +void OTG_FS_IRQHandler(void) +#endif +{ usb_irq_handler(0); }