Technology Mapping #6
Description
When generating a Verilog netlist using e/Teak you should expect a popup window (if you're using the GUI, if not try --help in command line) which asks you to select a technology library. e/Teak's technology mapper automatically generates the gates within modules based on the provided library (see the generated verilog files). In your case "example.v" file which contains the timing information for every gate is the default library and is useful when you simulate the design and aim to estimate the execution time of your circuit or approximate the critical path (in synchronous designs).
If you install other technology libraries, such as UMC Faradey 130nm, e/Teak recognises the path to the library and maps the circuit based on the available gates in the package. If you don't have access to UMC Faradey 130nm then you can use NanGate 45nm library: http://www.nangate.com/?page_id=22
But why do you need Tech. mapping? By Tech mapping a design Synopsys can provide you with more accurate timing estimations. Bear in mind that e/Teak doesn't generate RTL, instead it generates gate level netlist. When you have gate-level netlist in hand you don't really need to rely on the elaboration phase of Design Compiler (DC) and you can easily skip it. The only renaming phase is Tech. mapping the design if you want to use area estimator from Synopsys. For power estimations a vcd file can be generated from the simulator and fed it into Synopsys PowerTime for power and timing estimations.
For the asynchronous designs Tech. mapper replaces C elements with Dlatches from the library. When estimating the area DC will throw some warnings saying that it has detected timing loops which could be ignored as you don't really want DC to touch/optimise your design at all!
If you need DC to optimise your design we recommend taking look at the re-synthesis paper in the Documentation folder: https://github.com/balangs/Documentation/tree/master/Peer-reviewed_Publications