diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 1f35a7e..5ae16aa 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -11,7 +11,7 @@ jobs: image: verilator/verilator:4.104 strategy: matrix: - conf_name: [general, line-ring, multicast, vc_alloc, conv_route, tiny_topos] + conf_name: [general, line-ring, multicast, vc_alloc, conv_route, tiny_topos, mesh_3d] env: ROOT: ${{ github.workspace }}/mpsoc PRONOC_WORK: ${{ github.workspace }}/mpsoc_work diff --git a/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1 b/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1 index 68179c9..279821c 100644 --- a/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1 +++ b/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1 @@ -1,6 +1,6 @@ $model = bless( { 'compile' => "verilate_mesh.sh", 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); diff --git a/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param b/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param index d95b510..35fa420 100644 --- a/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param +++ b/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param @@ -8,7 +8,7 @@ $model = bless( { "B" => "4", "LB" => "B", "Fpay" => "32", -"ROUTE_NAME" => "\"XY\"", +"ROUTE_NAME" => "\"DOR\"", "PCK_TYPE" => " \"MULTI_FLIT\"", "MIN_PCK_SIZE" => "2", "BYTE_EN" => "0", diff --git a/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy index ff79533..12a13c3 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy +++ b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { "TOPOLOGY" => "\"FMESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_3d_4x3x2x2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_3d_4x3x2x2 new file mode 100644 index 0000000..5893919 --- /dev/null +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_3d_4x3x2x2 @@ -0,0 +1,10 @@ +$model = bless( { + 'noc_param'=> { + "TOPOLOGY" => '"MESH_3D"', + "T1" => "4", + "T2" => "3", + "T3" => "2", + "T4" => "2", + "ROUTE_NAME" => '"DOR"', + } +}, 'ProNOC' ); diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy index f0c8499..ee47bc2 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy @@ -4,6 +4,6 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec index 719d562..6bb1a40 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_NONSPEC\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1 index 9d89499..1c5388c 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1 +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1 @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_SPEC1\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2 index aea90d2..ed2a7f9 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2 +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2 @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_SPEC2\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy index 4af7e61..7107201 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy @@ -1,5 +1,5 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc index 248f91c..1914e8b 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ESCAP_VC_MASK" => "4'd1", "V" => 4, } diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c index d2f38c8..26296f7 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "V" => 4, "C" => 4, "CLASS_SETTING" => "16'b1000010000100001", diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1 index 5196912..89af385 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1 +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ESCAP_VC_MASK" => "4'd1", "V" => 4, "HETERO_VC"=> "1", diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2 index 38c6d2b..bc13a6f 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2 +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "V" => 4, "ESCAP_VC_MASK" => "4'd1", "HETERO_VC"=> "2", diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2 index 8ad895e..166ee7c 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2 +++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "B"=> "2", "LB"=> 2 } diff --git a/mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy index f75ef5b..d47e3d9 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy +++ b/mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy @@ -3,6 +3,6 @@ $model = bless( { 'noc_param'=> { TOPOLOGY=>"\"RING\"", "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", } }, 'ProNOC' ); diff --git a/mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy index 5ade6a7..7d29733 100644 --- a/mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy +++ b/mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log b/mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log index d8603c4..a7862c8 100644 --- a/mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log +++ b/mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")" Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./topology_localparam.v, 143 -pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")" +pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator diff --git a/mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log b/mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log index 45a5716..2733830 100644 --- a/mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log +++ b/mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")" Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./topology_localparam.v, 143 -pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")" +pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator @@ -1347,26 +1347,26 @@ mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")" Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./mesh_torus.sv, 336 -mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")" +mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./mesh_torus.sv, 336 -mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")" +mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./mesh_torus.sv, 336 -mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")" +mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator diff --git a/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log index e9554f1..0fc7864 100644 --- a/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log +++ b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")" Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./topology_localparam.v, 143 -pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")" +pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator diff --git a/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log index 3a062f2..9dd7128 100644 --- a/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log +++ b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")" Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./topology_localparam.v, 143 -pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")" +pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator @@ -1827,26 +1827,26 @@ mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")" Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./mesh_torus.sv, 336 -mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")" +mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./mesh_torus.sv, 336 -mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")" +mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator ./../../rtl/src_noc/./mesh_torus.sv, 336 -mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")" +mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")" A left 16-bit expression is compared to a right 64-bit expression. Comparing 'ROUTE_NAME' of type string - with '"TRANC_XY"' of type string. + with '"TRANC_DOR"' of type string. Lint-[ULCO] Unequal length in comparison operator diff --git a/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3_vc_static.txt b/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3_vc_static.txt index af4ca57..d48e414 100644 --- a/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3_vc_static.txt +++ b/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3_vc_static.txt @@ -1430,9 +1430,9 @@ Module : mesh_torus_mask_non_assignable_destport_no_self_loop FileName : ./../../rtl/src_noc/./mesh_torus.sv LineNumber : 336 - Statement : if ( ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY") begin :xy + Statement : if ( ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR") begin :xy RTL_EXPRESSION : (Operators == and || used) - Node_Value : (Expr: ((ROUTE_NAME == "XY") || (ROUTE_NAME == "TRANC_XY"))) + Node_Value : (Expr: ((ROUTE_NAME == "DOR") || (ROUTE_NAME == "TRANC_DOR"))) ----------------------------------------------------------------------------- Tag : ExprParen Description : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value] @@ -1727,9 +1727,9 @@ Module : FileName : ./../../rtl/src_noc/./topology_localparam.v LineNumber : 144 - Statement : (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" )? "DETERMINISTIC" : + Statement : (ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR" )? "DETERMINISTIC" : RTL_EXPRESSION : (Operators == and || used) - Node_Value : (Expr: ((ROUTE_NAME == "XY") || (ROUTE_NAME == "TRANC_XY"))) + Node_Value : (Expr: ((ROUTE_NAME == "DOR") || (ROUTE_NAME == "TRANC_DOR"))) ----------------------------------------------------------------------------- Tag : ExprParen Description : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value] @@ -4622,7 +4622,7 @@ Module : mesh_torus_conventional_routing FileName : ./../../rtl/src_noc/./mesh_torus_routting.v LineNumber : 599 - Statement : parameter ROUTE_NAME = "XY", + Statement : parameter ROUTE_NAME = "DOR", CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -4642,7 +4642,7 @@ Module : mesh_torus_mask_non_assignable_destport FileName : ./../../rtl/src_noc/./mesh_torus.sv LineNumber : 225 - Statement : parameter ROUTE_NAME="XY", + Statement : parameter ROUTE_NAME="DOR", CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -4732,7 +4732,7 @@ Module : conventional_routing FileName : ./../../rtl/src_noc/./routing.v LineNumber : 33 - Statement : parameter ROUTE_NAME = "XY", + Statement : parameter ROUTE_NAME = "DOR", CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -4992,7 +4992,7 @@ Module : mesh_torus_deterministic_look_ahead_routing FileName : ./../../rtl/src_noc/./mesh_torus_routting.v LineNumber : 111 - Statement : parameter ROUTE_NAME="XY"// "XY", "TRANC_XY" + Statement : parameter ROUTE_NAME="DOR"// "DOR", "TRANC_DOR" CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -5212,7 +5212,7 @@ Module : mesh_torus_destp_generator FileName : ./../../rtl/src_noc/./mesh_torus.sv LineNumber : 1115 - Statement : parameter ROUTE_NAME = "XY", + Statement : parameter ROUTE_NAME = "DOR", CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -5252,7 +5252,7 @@ Module : look_ahead_routing FileName : ./../../rtl/src_noc/./routing.v LineNumber : 244 - Statement : parameter ROUTE_NAME="XY",// + Statement : parameter ROUTE_NAME="DOR",// CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -5312,7 +5312,7 @@ Module : mesh_torus_look_ahead_routing FileName : ./../../rtl/src_noc/./mesh_torus_routting.v LineNumber : 13 - Statement : parameter ROUTE_NAME = "XY",// + Statement : parameter ROUTE_NAME = "DOR",// CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -5422,7 +5422,7 @@ Module : destp_generator FileName : ./../../rtl/src_noc/./input_ports.sv LineNumber : 1091 - Statement : parameter ROUTE_NAME="XY", + Statement : parameter ROUTE_NAME="DOR", CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -5452,7 +5452,7 @@ Module : mesh_torus_mask_non_assignable_destport_no_self_loop FileName : ./../../rtl/src_noc/./mesh_torus.sv LineNumber : 282 - Statement : parameter ROUTE_NAME="XY", + Statement : parameter ROUTE_NAME="DOR", CValue : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ConstName @@ -5877,7 +5877,7 @@ Module : look_ahead_routing FileName : ./../../rtl/src_noc/./routing.v LineNumber : 244 - Statement : parameter ROUTE_NAME="XY",// + Statement : parameter ROUTE_NAME="DOR",// Param : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ParamName @@ -6067,7 +6067,7 @@ Module : destp_generator FileName : ./../../rtl/src_noc/./input_ports.sv LineNumber : 1091 - Statement : parameter ROUTE_NAME="XY", + Statement : parameter ROUTE_NAME="DOR", Param : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ParamName @@ -6377,7 +6377,7 @@ Module : mesh_torus_mask_non_assignable_destport_no_self_loop FileName : ./../../rtl/src_noc/./mesh_torus.sv LineNumber : 282 - Statement : parameter ROUTE_NAME="XY", + Statement : parameter ROUTE_NAME="DOR", Param : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ParamName @@ -6437,7 +6437,7 @@ Module : mesh_torus_mask_non_assignable_destport FileName : ./../../rtl/src_noc/./mesh_torus.sv LineNumber : 225 - Statement : parameter ROUTE_NAME="XY", + Statement : parameter ROUTE_NAME="DOR", Param : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ParamName @@ -6647,7 +6647,7 @@ Module : mesh_torus_conventional_routing FileName : ./../../rtl/src_noc/./mesh_torus_routting.v LineNumber : 599 - Statement : parameter ROUTE_NAME = "XY", + Statement : parameter ROUTE_NAME = "DOR", Param : ROUTE_NAME ----------------------------------------------------------------------------- Tag : ParamName diff --git a/mpsoc/Integration_test/default_noc_param b/mpsoc/Integration_test/default_noc_param index 0ec3ed9..b370372 100644 --- a/mpsoc/Integration_test/default_noc_param +++ b/mpsoc/Integration_test/default_noc_param @@ -5,11 +5,12 @@ $model = bless({ "T1" => "8", "T2" => "8", "T3" => "1", + "T4" => "1", "V" => "2", "B" => "4", "LB" => "B", "Fpay" => "32", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ROUTE_MODE" => "\"LOOKAHEAD\"", "PCK_TYPE" => " \"MULTI_FLIT\"", "MIN_PCK_SIZE" => "2", @@ -51,6 +52,7 @@ $model = bless({ 'T1', 'T2', 'T3', + 'T4', 'V', 'B', 'LB', diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_smart3 b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_4x4_smart3 similarity index 100% rename from mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_smart3 rename to mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_4x4_smart3 diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/ring_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/ring_8x8_2cycle_xy index 35e24e5..ae75953 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/ring_8x8_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/ring_8x8_2cycle_xy @@ -3,7 +3,7 @@ $model = bless( { 'noc_param'=> { TOPOLOGY=>"\"RING\"", "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", "ROUTE_MODE" => "\"CONVENTIONAL\"", } }, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/torus_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/torus_8x8_2cycle_xy index 58317ed..bb0e659 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/torus_8x8_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/torus_8x8_2cycle_xy @@ -1,7 +1,7 @@ $model = bless( { 'noc_param'=> { "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", "ROUTE_MODE" => "\"CONVENTIONAL\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_smart3 b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_4x4_smart3 similarity index 100% rename from mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_smart3 rename to mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_4x4_smart3 diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_2cycle_xy index ff79533..12a13c3 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_2cycle_xy @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { "TOPOLOGY" => "\"FMESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4x3_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4x3_2cycle_xy index f0c8499..ee47bc2 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4x3_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4x3_2cycle_xy @@ -4,6 +4,6 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_xy index 4af7e61..7107201 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_xy @@ -1,5 +1,5 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_4vc_4c b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_4vc_4c index d2f38c8..26296f7 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_4vc_4c +++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_4vc_4c @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "V" => 4, "C" => 4, "CLASS_SETTING" => "16'b1000010000100001", diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_b2 b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_b2 index 8ad895e..166ee7c 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_b2 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_b2 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "B"=> "2", "LB"=> 2 } diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/torus_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/torus_8x8_2cycle_xy index 5ade6a7..7d29733 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/general/torus_8x8_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/torus_8x8_2cycle_xy @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2 b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2 index af2aa51..07a06b4 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2 @@ -8,6 +8,6 @@ $model = bless( { "B" => "4", "LB" => "4", "Fpay" => "32", - "ROUTE_NAME"=>"\"XY\"" + "ROUTE_NAME"=>"\"DOR\"" } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy index 57133ba..15a1e84 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy @@ -4,6 +4,6 @@ $model = bless( { "T1" => "4", "T2" => "4", "T3" => "3", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy index caa94b2..5a31cc4 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { TOPOLOGY=>"\"LINE\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2 b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2 index cdec6fb..8a39813 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2 @@ -1,7 +1,7 @@ $model = bless( { 'noc_param'=> { TOPOLOGY=>"\"LINE\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "B"=> "2", "LB"=> 2 } diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c index 5e7b123..e204644 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c +++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c @@ -1,7 +1,7 @@ $model = bless( { 'noc_param'=> { TOPOLOGY=>"\"LINE\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "V" => 4, "C" => 4, "CLASS_SETTING" => "16'b1000010000100001", diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy index f75ef5b..d47e3d9 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy +++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy @@ -3,6 +3,6 @@ $model = bless( { 'noc_param'=> { TOPOLOGY=>"\"RING\"", "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", } }, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_2x2x2 b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_2x2x2 new file mode 100644 index 0000000..b65c45c --- /dev/null +++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_2x2x2 @@ -0,0 +1,10 @@ +$model = bless( { + 'noc_param'=> { + "TOPOLOGY" => '"MESH_3D"', + "T1" => "2", + "T2" => "2", + "T3" => "2", + "T4" => "1", + "ROUTE_NAME" => '"DOR"', + } +}, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2 b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2 new file mode 100644 index 0000000..5893919 --- /dev/null +++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2 @@ -0,0 +1,10 @@ +$model = bless( { + 'noc_param'=> { + "TOPOLOGY" => '"MESH_3D"', + "T1" => "4", + "T2" => "3", + "T3" => "2", + "T4" => "2", + "ROUTE_NAME" => '"DOR"', + } +}, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_smart b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_smart new file mode 100644 index 0000000..6c209c4 --- /dev/null +++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_smart @@ -0,0 +1,12 @@ +$model = bless( { + 'noc_param'=> { + "TOPOLOGY" => '"MESH_3D"', + "T1" => "4", + "T2" => "3", + "T3" => "2", + "T4" => "2", + "ROUTE_NAME" => '"DOR"', + "SSA_EN"=> "0", + "SMART_MAX" => "3", + } +}, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_ssa b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_ssa new file mode 100644 index 0000000..29e38cc --- /dev/null +++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_ssa @@ -0,0 +1,11 @@ +$model = bless( { + 'noc_param'=> { + "TOPOLOGY" => '"MESH_3D"', + "T1" => "4", + "T2" => "3", + "T3" => "2", + "T4" => "2", + "ROUTE_NAME" => '"DOR"', + "SSA_EN"=> "1", + } +}, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Line_3x2_v2 b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Line_3x2_v2 index 39a9863..191a894 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Line_3x2_v2 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Line_3x2_v2 @@ -8,6 +8,6 @@ $model = bless( { "B" => "4", "LB" => "4", "Fpay" => "32", - "ROUTE_NAME"=>"\"XY\"" + "ROUTE_NAME"=>"\"DOR\"" } }, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_3d_2x2x2 b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_3d_2x2x2 new file mode 100644 index 0000000..b65c45c --- /dev/null +++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_3d_2x2x2 @@ -0,0 +1,10 @@ +$model = bless( { + 'noc_param'=> { + "TOPOLOGY" => '"MESH_3D"', + "T1" => "2", + "T2" => "2", + "T3" => "2", + "T4" => "1", + "ROUTE_NAME" => '"DOR"', + } +}, 'ProNOC' ); diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/ring_3_2 b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/ring_3_2 index b1c5c90..0238d96 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/ring_3_2 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/ring_3_2 @@ -2,7 +2,7 @@ $model = bless( { 'compile' => "verilate_mesh.sh", 'noc_param'=> { "TOPOLOGY"=>"\"RING\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", "T1" => "3", "T2" => "1", "T3" => "2", diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec index 719d562..6bb1a40 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec +++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_NONSPEC\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1 index 9d89499..1c5388c 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1 @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_SPEC1\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2 index aea90d2..ed2a7f9 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2 @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_SPEC2\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc index 248f91c..1914e8b 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc +++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ESCAP_VC_MASK" => "4'd1", "V" => 4, } diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero1 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero1 index 5196912..89af385 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero1 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero1 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ESCAP_VC_MASK" => "4'd1", "V" => 4, "HETERO_VC"=> "1", diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero2 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero2 index 38c6d2b..bc13a6f 100644 --- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero2 +++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero2 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "V" => 4, "ESCAP_VC_MASK" => "4'd1", "HETERO_VC"=> "2", diff --git a/mpsoc/Integration_test/synthetic_sim/golden_ref/conv_route b/mpsoc/Integration_test/synthetic_sim/golden_ref/conv_route index 013fab1..fe86e40 100644 --- a/mpsoc/Integration_test/synthetic_sim/golden_ref/conv_route +++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/conv_route @@ -7,14 +7,14 @@ Verification Results: model is generated successfully. ****************************fmesh_2x2_openpiton : Compile *******************************: model is generated successfully. +****************************fmesh_4x4_smart3 : Compile *******************************: + model is generated successfully. ****************************mesh_3x3_v2_ssa : Compile *******************************: model is generated successfully. ****************************mesh_4x4_2cycle_mcast_f : Compile *******************************: model is generated successfully. ****************************mesh_4x4_selflp_mcast_f : Compile *******************************: model is generated successfully. -****************************mesh_4x4_smart3 : Compile *******************************: - model is generated successfully. ****************************mesh_4x4x2_bcast_f : Compile *******************************: model is generated successfully. ****************************mesh_8x8_2cycle_adaptive : Compile *******************************: @@ -37,14 +37,14 @@ Verification Results: Passed: zero load (2,13.5991) saturation (62,98.8008) ****************************fmesh_2x2_openpiton : random traffic *******************************: Passed: zero load (2,8.27536) saturation (54,67.4686) +****************************fmesh_4x4_smart3 : random traffic *******************************: + Passed: zero load (2,10.1271) saturation (42,72.4117) ****************************mesh_3x3_v2_ssa : random traffic *******************************: Passed: zero load (2,9.86859) saturation (70,77.4433) ****************************mesh_4x4_2cycle_mcast_f : random traffic *******************************: Passed: zero load (2,14.4623) saturation (22,261.684) ****************************mesh_4x4_selflp_mcast_f : random traffic *******************************: Passed: zero load (2,14.366) saturation (22,257.065) -****************************mesh_4x4_smart3 : random traffic *******************************: - Passed: zero load (2,10.1271) saturation (42,72.4117) ****************************mesh_4x4x2_bcast_f : random traffic *******************************: Passed: zero load (2,20.5192) saturation (6,1071.58) ****************************mesh_8x8_2cycle_adaptive : random traffic *******************************: @@ -66,15 +66,15 @@ Verification Results: ****************************Fattree_k3_L3_st : transposed 1 traffic *******************************: Passed: zero load (26,13.4638) saturation (100,-) ****************************fmesh_2x2_openpiton : transposed 1 traffic *******************************: - Passed: zero load (2,8.99642) saturation (54,71.4902) + Passed: zero load (2,8.44803) saturation (54,70.7567) +****************************fmesh_4x4_smart3 : transposed 1 traffic *******************************: + Passed: zero load (2,9.95941) saturation (26,73.9415) ****************************mesh_3x3_v2_ssa : transposed 1 traffic *******************************: Passed: zero load (6,9.72718) saturation (54,69.363) ****************************mesh_4x4_2cycle_mcast_f : transposed 1 traffic *******************************: Passed: zero load (2,14.8953) saturation (26,146.747) ****************************mesh_4x4_selflp_mcast_f : transposed 1 traffic *******************************: Passed: zero load (2,14.6488) saturation (22,166.723) -****************************mesh_4x4_smart3 : transposed 1 traffic *******************************: - Passed: zero load (2,10.5055) saturation (34,60.2796) ****************************mesh_4x4x2_bcast_f : transposed 1 traffic *******************************: Passed: zero load (2,21.0549) saturation (6,863.495) ****************************mesh_8x8_2cycle_adaptive : transposed 1 traffic *******************************: diff --git a/mpsoc/Integration_test/synthetic_sim/golden_ref/general b/mpsoc/Integration_test/synthetic_sim/golden_ref/general index edfbf3e..e67bf42 100644 --- a/mpsoc/Integration_test/synthetic_sim/golden_ref/general +++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/general @@ -9,6 +9,8 @@ Verification Results: model is generated successfully. ****************************fmesh_2x2_openpiton : Compile *******************************: model is generated successfully. +****************************fmesh_4x4_smart3 : Compile *******************************: + model is generated successfully. ****************************fmesh_8x8_2cycle_xy : Compile *******************************: model is generated successfully. ****************************fmesh_8x8_openpiton : Compile *******************************: @@ -19,8 +21,6 @@ Verification Results: model is generated successfully. ****************************mesh_4x4_2cycle_mcast_f : Compile *******************************: model is generated successfully. -****************************mesh_4x4_smart3 : Compile *******************************: - model is generated successfully. ****************************mesh_4x4_v1_B15 : Compile *******************************: model is generated successfully. ****************************mesh_4x4x3_2cycle_xy : Compile *******************************: @@ -55,6 +55,8 @@ Verification Results: Passed: zero load (2,6.28966) saturation (66,50.4578) ****************************fmesh_2x2_openpiton : random traffic *******************************: Passed: zero load (2,8.27536) saturation (54,67.4686) +****************************fmesh_4x4_smart3 : random traffic *******************************: + Passed: zero load (2,10.1271) saturation (42,72.4117) ****************************fmesh_8x8_2cycle_xy : random traffic *******************************: Passed: zero load (2,19.5638) saturation (18,137.798) ****************************fmesh_8x8_openpiton : random traffic *******************************: @@ -65,8 +67,6 @@ Verification Results: Passed: zero load (2,9.86859) saturation (70,77.4433) ****************************mesh_4x4_2cycle_mcast_f : random traffic *******************************: Passed: zero load (2,14.4623) saturation (22,261.684) -****************************mesh_4x4_smart3 : random traffic *******************************: - Passed: zero load (2,10.1271) saturation (42,72.4117) ****************************mesh_4x4_v1_B15 : random traffic *******************************: Passed: zero load (6,12.719) saturation (58,93.2747) ****************************mesh_4x4x3_2cycle_xy : random traffic *******************************: @@ -98,21 +98,21 @@ Verification Results: ****************************Fattree_k3_L3_st : transposed 1 traffic *******************************: Passed: zero load (26,13.4638) saturation (100,-) ****************************fmesh_1x1_openpiton : transposed 1 traffic *******************************: - Passed: zero load (58,6.52308) saturation (100,-) + Passed: zero load (50,6.03057) saturation (100,-) ****************************fmesh_2x2_openpiton : transposed 1 traffic *******************************: - Passed: zero load (2,8.99642) saturation (54,71.4902) + Passed: zero load (2,8.44803) saturation (54,70.7567) +****************************fmesh_4x4_smart3 : transposed 1 traffic *******************************: + Passed: zero load (2,9.95941) saturation (26,73.9415) ****************************fmesh_8x8_2cycle_xy : transposed 1 traffic *******************************: - Passed: zero load (2,21.6193) saturation (14,142.818) + Passed: zero load (2,21.0207) saturation (10,197.415) ****************************fmesh_8x8_openpiton : transposed 1 traffic *******************************: - Passed: zero load (2,15.916) saturation (26,118.048) + Passed: zero load (2,15.1688) saturation (14,111.335) ****************************mesh_2x2_openpiton : transposed 1 traffic *******************************: Passed: zero load (2,8.7482) saturation (100,-) ****************************mesh_3x3_v2_ssa : transposed 1 traffic *******************************: Passed: zero load (6,9.72718) saturation (54,69.363) ****************************mesh_4x4_2cycle_mcast_f : transposed 1 traffic *******************************: Passed: zero load (2,14.8953) saturation (26,146.747) -****************************mesh_4x4_smart3 : transposed 1 traffic *******************************: - Passed: zero load (2,10.5055) saturation (34,60.2796) ****************************mesh_4x4_v1_B15 : transposed 1 traffic *******************************: Passed: zero load (2,13.6902) saturation (38,106.686) ****************************mesh_4x4x3_2cycle_xy : transposed 1 traffic *******************************: diff --git a/mpsoc/Integration_test/synthetic_sim/golden_ref/mesh_3d b/mpsoc/Integration_test/synthetic_sim/golden_ref/mesh_3d new file mode 100644 index 0000000..bc7f3bc --- /dev/null +++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/mesh_3d @@ -0,0 +1,22 @@ + +Verification Results: +****************************mesh_3d_2x2x2 : Compile *******************************: + model is generated successfully. +****************************mesh_3d_4x3x2x2 : Compile *******************************: + model is generated successfully. +****************************mesh_3d_4x3x2x2_smart : Compile *******************************: + model is generated successfully. +****************************mesh_3d_4x3x2x2_ssa : Compile *******************************: + model is generated successfully. +****************************mesh_3d_2x2x2 : random traffic *******************************: + Passed: zero load (6,10.8633) saturation (70,74.3971) +****************************mesh_3d_4x3x2x2 : random traffic *******************************: + Passed: zero load (2,12.8413) saturation (38,75.3519) +****************************mesh_3d_4x3x2x2_smart : random traffic *******************************: + Passed: zero load (2,11.3919) saturation (38,73.7525) +****************************mesh_3d_4x3x2x2_ssa : random traffic *******************************: + Passed: zero load (2,12.1337) saturation (38,85.3049) +****************************mesh_3d_2x2x2 : transposed 1 traffic *******************************: + Passed: zero load (2,9.82014) saturation (54,53.6323) +****************************mesh_3d_4x3x2x2 : transposed 1 traffic *******************************: + Passed: zero load (2,12.6931) saturation (14,165.269) diff --git a/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_2cycle_xy index ff79533..12a13c3 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_2cycle_xy +++ b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_2cycle_xy @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { "TOPOLOGY" => "\"FMESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_2cycle_xy index f0c8499..ee47bc2 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_2cycle_xy +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_2cycle_xy @@ -4,6 +4,6 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_nonspec b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_nonspec index 719d562..6bb1a40 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_nonspec +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_nonspec @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_NONSPEC\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec1 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec1 index 9d89499..1c5388c 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec1 +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec1 @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_SPEC1\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec2 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec2 index aea90d2..ed2a7f9 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec2 +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec2 @@ -4,7 +4,7 @@ $model = bless( { "T2" => "4", "T3" => "3", "TOPOLOGY" => "\"MESH\"", - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "COMBINATION_TYPE" => "\"COMB_SPEC2\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_xy index 4af7e61..7107201 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_xy +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_xy @@ -1,5 +1,5 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc index 248f91c..1914e8b 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ESCAP_VC_MASK" => "4'd1", "V" => 4, } diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_4c b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_4c index d2f38c8..26296f7 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_4c +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_4c @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "V" => 4, "C" => 4, "CLASS_SETTING" => "16'b1000010000100001", diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero1 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero1 index 5196912..89af385 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero1 +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero1 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ESCAP_VC_MASK" => "4'd1", "V" => 4, "HETERO_VC"=> "1", diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero2 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero2 index 38c6d2b..bc13a6f 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero2 +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero2 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "V" => 4, "ESCAP_VC_MASK" => "4'd1", "HETERO_VC"=> "2", diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_b2 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_b2 index 8ad895e..166ee7c 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_b2 +++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_b2 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "B"=> "2", "LB"=> 2 } diff --git a/mpsoc/Integration_test/verilator_lint/configurations/ring_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/ring_8x8_2cycle_xy index f75ef5b..d47e3d9 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/ring_8x8_2cycle_xy +++ b/mpsoc/Integration_test/verilator_lint/configurations/ring_8x8_2cycle_xy @@ -3,6 +3,6 @@ $model = bless( { 'noc_param'=> { TOPOLOGY=>"\"RING\"", "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", } }, 'ProNOC' ); diff --git a/mpsoc/Integration_test/verilator_lint/configurations/torus_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/torus_8x8_2cycle_xy index 5ade6a7..7d29733 100644 --- a/mpsoc/Integration_test/verilator_lint/configurations/torus_8x8_2cycle_xy +++ b/mpsoc/Integration_test/verilator_lint/configurations/torus_8x8_2cycle_xy @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { "TOPOLOGY" => "\"TORUS\"", - "ROUTE_NAME" => "\"TRANC_XY\"", + "ROUTE_NAME" => "\"TRANC_DOR\"", } }, 'ProNOC' ); \ No newline at end of file diff --git a/mpsoc/perl_gui/lib/emulate/tt.EML b/mpsoc/perl_gui/lib/emulate/tt.EML index 2ae815a..8397dd3 100644 --- a/mpsoc/perl_gui/lib/emulate/tt.EML +++ b/mpsoc/perl_gui/lib/emulate/tt.EML @@ -42,7 +42,7 @@ $emulate = bless( { 'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0', 'FIRST_ARBITER_EXT_P_EN' => 1, 'MIN_PCK_SIZE' => '2', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'T1' => '2', 'CONGESTION_INDEX' => 3, 'SMART_MAX' => '0' diff --git a/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP b/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP index dd714c7..2a49a3e 100644 --- a/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP +++ b/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP @@ -101,7 +101,7 @@ The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRAN 'global_param' => 'Parameter', 'redefine_param' => 1, 'content' => '', - 'default' => '"XY" ' + 'default' => '"DOR" ' }, 'Fpay' => { 'default' => ' 32', diff --git a/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC b/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC index d1a97f0..2e36799 100644 --- a/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC +++ b/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC @@ -598,7 +598,7 @@ $mpsoc = bless( { 'FIRST_ARBITER_EXT_P_EN' => 1, 'T3' => '1', 'TOPOLOGY' => '"MESH"', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'VC_REALLOCATION_TYPE' => '"NONATOMIC"', 'V' => '2', 'COMBINATION_TYPE' => '"COMB_NONSPEC"', diff --git a/mpsoc/perl_gui/lib/multi_nocs/test.phy b/mpsoc/perl_gui/lib/multi_nocs/test.phy index 1873cc8..7146d07 100644 --- a/mpsoc/perl_gui/lib/multi_nocs/test.phy +++ b/mpsoc/perl_gui/lib/multi_nocs/test.phy @@ -37,7 +37,7 @@ $phy = bless( { 'SWA_ARBITER_TYPE' => '"RRA"', 'T2' => '2', 'TOPOLOGY' => '"MESH"', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'BYTE_EN' => 0, 'DEBUG_EN' => '0' }, @@ -60,7 +60,7 @@ $phy = bless( { 'FIRST_ARBITER_EXT_P_EN' => 1, 'Fpay' => '32', 'SSA_EN' => '0', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'T2' => '3', 'TOPOLOGY' => '"MESH"', 'SWA_ARBITER_TYPE' => '"RRA"', @@ -246,7 +246,7 @@ $phy = bless( { 'TOPOLOGY' => '"MESH"', 'SWA_ARBITER_TYPE' => '"RRA"', 'T1' => '2', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'Fpay' => '32', 'SSA_EN' => '0', 'FIRST_ARBITER_EXT_P_EN' => 1, @@ -289,7 +289,7 @@ $phy = bless( { 'T1' => '2', 'T2' => '2', 'TOPOLOGY' => '"MESH"', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'CAST_TYPE' => '"UNICAST"', 'FIRST_ARBITER_EXT_P_EN' => 1, 'SSA_EN' => '0', diff --git a/mpsoc/perl_gui/lib/multi_nocs/tt.phy b/mpsoc/perl_gui/lib/multi_nocs/tt.phy index b6f0872..54885fe 100644 --- a/mpsoc/perl_gui/lib/multi_nocs/tt.phy +++ b/mpsoc/perl_gui/lib/multi_nocs/tt.phy @@ -36,7 +36,7 @@ $phy = bless( { 'VC_REALLOCATION_TYPE' => '"NONATOMIC"', 'AVC_ATOMIC_EN' => 0, 'B' => '4', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'ESCAP_VC_MASK' => '2\'b01', 'DEBUG_EN' => '0', 'SELF_LOOP_EN' => '0', @@ -202,7 +202,7 @@ $phy = bless( { 'WEIGHTw' => '4', 'DEBUG_EN' => '0', 'ESCAP_VC_MASK' => '2\'b01', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'B' => '4', 'AVC_ATOMIC_EN' => 0, 'VC_REALLOCATION_TYPE' => '"NONATOMIC"', @@ -237,7 +237,7 @@ $phy = bless( { 'SELF_LOOP_EN' => '0', 'AVC_ATOMIC_EN' => 0, 'VC_REALLOCATION_TYPE' => '"NONATOMIC"', - 'ROUTE_NAME' => '"XY"', + 'ROUTE_NAME' => '"DOR"', 'ESCAP_VC_MASK' => '2\'b01', 'B' => '4', 'SSA_EN' => '0', diff --git a/mpsoc/perl_gui/lib/perl/diagram.pl b/mpsoc/perl_gui/lib/perl/diagram.pl index 2236c55..d6194e6 100644 --- a/mpsoc/perl_gui/lib/perl/diagram.pl +++ b/mpsoc/perl_gui/lib/perl/diagram.pl @@ -1005,7 +1005,7 @@ sub generate_tree_dot_file{ my $hp= join("|",@hp); # my ($NE,$NR)=get_topology_info($self); my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($self); - #add endpoints + # add endpoints for(my $i=0; $i<$NE; $i++){ $dotfile=$dotfile."T$i\[ label = \"T$i\" @@ -1018,12 +1018,12 @@ sub generate_tree_dot_file{ ]; "; } - #add roots + # add roots my $label = "\{R0\}|\{$bp\}"; my $x=(($NE-1)/2); my $y= 1.5*($nl-1)+1; $dotfile.=get_router_dot_file("R0",$label,"$x,$y!",$gtype); - #add leaves + # add leaves my $t=1; for(my $l=$nl-1; $l>0; $l--){ my $NL = powi($k,$l); @@ -1036,7 +1036,7 @@ sub generate_tree_dot_file{ $dotfile.=get_router_dot_file("R$r",$label,"$x,$y!",$gtype); } } - #add leave connections + # add leave connections for(my $l=$nl-1; $l>0; $l--){ my $NL = powi($k,$l); for(my $pos=0; $pos<$NL; $pos++){ @@ -1045,7 +1045,7 @@ sub generate_tree_dot_file{ $dotfile=$dotfile.node_connection('R',$id1,undef,$k,'R',$id2,undef,$pos % $k,$gtype); } } - #add endpoints connection + # add endpoints connection for(my $i=0; $i<$NE; $i++){ my $r= sum_powi($k,$nl-1)+int($i/$k); $dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k),$gtype); @@ -1054,6 +1054,99 @@ sub generate_tree_dot_file{ return $dotfile; } +sub generate_3d_mesh_dot_file { + my $self=shift; + my $x_dim=$self->object_get_attribute('noc_param','T1'); + my $y_dim=$self->object_get_attribute('noc_param','T2'); + my $z_dim=$self->object_get_attribute('noc_param','T3'); + my $l_num=$self->object_get_attribute('noc_param','T4'); + # print "Generating 3D mesh dot file with dimensions: ${x_dim}x${y_dim}x${z_dim}, L_num=$l_num\n"; + my $dotfile.="digraph G {\n"; + $dotfile.=" graph [ layout = neato, rankdir = LR , splines = true, overlap = false];\n"; + $dotfile.=" node [shape=parallelogram, style=filled, color=orange, fillcolor=skyblue];\n"; + $dotfile.=" graph [splines=line, overlap=true];\n\n"; + my $node_size="width=1, height=.5, fixedsize=true"; + my $x_shift_per_layer = 0; # shift each layer slightly right + my $x_shift_per_row = .5; # shift each row slightly right + my $x_gap_mulply = 1.3; # increase the gap between two adjacent nodes in x dir + my $y_gap_mulply = 1.1; # increase the gap between two adjacent nodes in y dir + # Generate nodes with pos attributes + my $v=$z_dim*$y_dim*$x_dim; + for my $zz (0..$z_dim-1) { + for my $yy (0..$y_dim-1) { + for my $xx (0..$x_dim-1) { + my $x = $xx; + my $y = $y_dim-$yy-1; + my $z = $z_dim-$zz-1; + my $node_name = "N_${xx}_${yy}_${zz}"; + # X shifted by layer index, Y shifted by row + layer offset + my $x_pos = $x*$x_gap_mulply + $z * $x_shift_per_layer - $y * $x_shift_per_row; + my $y_pos = $y*$y_gap_mulply + $z * ($y_dim*$y_gap_mulply +.25); # space between layers + my $len = length("$v"); + my $Rnum=$xx + ($yy*$x_dim) + ($zz * $x_dim * $y_dim); + my $Rlable = sprintf("R%-${len}d", $Rnum); + $dotfile.= " $node_name [label=\"$Rlable\", pos=\"$x_pos,$y_pos!\" $node_size];\n"; + for my $ll (0..$l_num-1){ + my $Tx_pos =($ll==0 || $ll==2)? $x_pos-0.4 : $x_pos+0.3; + my $Ty_pos =($ll==0 || $ll==1)? $y_pos-0.3 : $y_pos+0.3; + my $Tnum = $ll+($Rnum*$l_num); + my $endp_name = "T_${xx}_${yy}_${zz}_$ll"; + $dotfile.= +" $endp_name [ + label=\"T$Tnum\", + pos=\"$Tx_pos,$Ty_pos!\", + shape=box, + style=filled, + fillcolor=orange, + width=0, // 0 means auto + height=0, // 0 means auto + fixedsize=false, + margin=0.01 // small margin around text +]; +"; + } + } + } + } + $dotfile.= "\n"; + # Connect nodes in X, Y, Z directions + for my $z (0..$z_dim-1) { + for my $y (0..$y_dim-1) { + for my $x (0..$x_dim-1) { + my $node = "N_${x}_${y}_${z}"; + # X direction + if ($x < $x_dim-1) { + my $neighbor = "N_" . ($x+1) . "_$y\_$z"; + $dotfile.= " $node -> $neighbor [dir=none];\n"; + } + # Y direction + if ($y < $y_dim-1) { + my $neighbor = "N_${x}_" . ($y+1) . "_$z"; + $dotfile.= " $node -> $neighbor [dir=none];\n"; + } + # Z direction + if ($z < $z_dim-1) { + my $neighbor = "N_${x}_${y}_" . ($z+1); + $dotfile.= " $node -> $neighbor [dir=none, style=dashed, constraint=false];\n"; + } + } + } + } + $dotfile.= "\n"; + # Invisible edges for column alignment + for my $z (0..$z_dim-1) { + for my $x (0..$x_dim-1) { + for my $y (0..$y_dim-2) { + my $from = "N_${x}_${y}_${z}"; + my $to = "N_${x}_" . ($y+1) . "_$z"; + $dotfile.= " $from -> $to [style=invis];\n"; + } + } + } + $dotfile.= "}\n"; + return $dotfile; +} + sub get_topology_dot_file{ my $self=shift; @@ -1062,6 +1155,7 @@ sub get_topology_dot_file{ return generate_fattree_dot_file ($self) if($topology eq '"FATTREE"'); return generate_tree_dot_file($self) if($topology eq '"TREE"'); return generate_star_dot_file($self) if($topology eq '"STAR"'); + return generate_3d_mesh_dot_file($self) if($topology eq '"MESH_3D"'); } diff --git a/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl b/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl index b574571..c00195b 100755 --- a/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl +++ b/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl @@ -97,8 +97,7 @@ sub synthetic_destination{ sub gen_synthetic_traffic_ram_line{ my ($emulate, $endp, $sample,$ratio ,$line_num,$rnd)=@_; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample); - my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($emulate,$sample); my $traffic=$emulate->object_get_attribute($sample,"traffic"); my $pck_num_to_send=$emulate->object_get_attribute($sample,"PCK_NUM_LIMIT"); my $pck_size=$emulate->object_get_attribute($sample,"PCK_SIZE"); @@ -127,8 +126,7 @@ sub gen_synthetic_traffic_ram_line{ sub get_synthetic_traffic_pattern{ my ($self, $sample)=@_; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample); - my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($self,$sample); my $rnd=random_dest_gen_no_shuffle($NE); my $traffic=$self->object_get_attribute($sample,"traffic"); my @traffics=("tornado", "transposed 1", "transposed 2", "bit reverse", "bit complement","random", "hot spot", "shuffle", "neighbor", "bit rotation" ); @@ -184,8 +182,7 @@ sub print_32_bit { sub generate_emulator_ram { my ($emulate, $sample,$ratio_in,$info)=@_; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample); - my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($emulate,$sample); my $rnd=random_dest_gen($NE); # generate a matrix of sudo random number my $traffic=$emulate->object_get_attribute($sample,"traffic"); my @traffics=("tornado", "transposed 1", "transposed 2", "bit reverse", "bit complement","random", "hot spot", "shuffle", "neighbor", "bit rotation" ); @@ -324,8 +321,7 @@ sub read_statistic_mem_fast { sub read_pack_gen{ my ($emulate,$sample,$info,$jtag_intfc,$ratio_in)= @_; my $ref=$emulate->object_get_attribute($sample,"noc_info"); - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample); - my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($emulate,$sample); #wait for done add_info($info, "wait for done\n"); my $done=0; @@ -395,4 +391,4 @@ sub read_pack_gen{ update_result ($emulate,$sample,"exe_time_result",$ratio_in,$clk_counter); return 1; } -1; \ No newline at end of file +1; diff --git a/mpsoc/perl_gui/lib/perl/emulator.pl b/mpsoc/perl_gui/lib/perl/emulator.pl index 7338905..31c6e95 100755 --- a/mpsoc/perl_gui/lib/perl/emulator.pl +++ b/mpsoc/perl_gui/lib/perl/emulator.pl @@ -279,7 +279,7 @@ sub gen_emulation_column { my $temp = __PACKAGE__->new(); my $st = ($mode eq "simulate" )? check_sim_sample($emulate,$sample,$info) : check_sample($emulate,$sample,$info); return if $st==0; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample); + my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($emulate,$sample); my $ref=$emulate->object_get_attribute($sample,"noc_info"); if (defined $ref){ my %noc_info= %$ref; @@ -293,10 +293,11 @@ sub gen_emulation_column { $traffic-> signal_connect("clicked" => sub{ my $st = ($mode eq "simulate" )? check_sim_sample($emulate,$sample,$info) : check_sample($emulate,$sample,$info); return if $st==0; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample); + my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($emulate,$sample); $emulate->object_add_attribute('noc_param','T1',$T1); $emulate->object_add_attribute('noc_param','T2',$T2); $emulate->object_add_attribute('noc_param','T3',$T3); + $emulate->object_add_attribute('noc_param','T4',$T4); $emulate->object_add_attribute('noc_param','TOPOLOGY',$topology); my $pattern=""; my $traffictype=$emulate->object_get_attribute($sample,"TRAFFIC_TYPE"); diff --git a/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl b/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl index cb4217c..aa9704a 100755 --- a/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl +++ b/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl @@ -51,19 +51,18 @@ sub initial_default_param{ ############# # get_soc_lists ############ - sub get_soc_list { my ($mpsoc,$info)=@_; - my $path=$mpsoc->object_get_attribute('setting','soc_path'); + my $path=$mpsoc->object_get_attribute('setting','soc_path'); $path =~ s/ /\\ /g; my @socs; my @files = glob "$path/*.SOC"; for my $p (@files){ - my ($soc,$r,$err) = regen_object($p); - # Read - if ($r){ + my ($soc,$r,$err) = regen_object($p); + # Read + if ($r){ add_info($info,"**Error reading $p file: $err\n"); - next; + next; } my $top=$soc->soc_get_top(); if (defined $top){ @@ -79,12 +78,10 @@ sub get_soc_list { copy_back_custom_soc_param($top,$old_top) if(defined $old_top); $mpsoc->mpsoc_add_soc($name,$top); #print" $name\n"; - } + } } - } }# files - # initial default soc parameter initial_default_param($mpsoc); return $mpsoc->mpsoc_get_soc_list; @@ -97,8 +94,7 @@ sub copy_back_custom_soc_param{ my %l =$old->top_get_custom_soc_param($tile); $new->top_add_custom_soc_param (\%l,$tile); } - -} +} sub get_NI_instance_list { my $top=shift; @@ -108,7 +104,7 @@ sub get_NI_instance_list { #check if the soc has ni port foreach my $instanc(@instance_list){ my $category=$top->top_get_def_of_instance($instanc,'category'); - push(@nis,$instanc) if($category eq 'NoC') ; + push(@nis,$instanc) if($category eq 'NoC') ; } return @nis; } @@ -116,29 +112,21 @@ sub get_NI_instance_list { #################### # get_conflict_decision ########################### - - sub get_conflict_decision{ my ($mpsoc,$name,$inserted,$conflicts,$msg)=@_; $msg="\tThe inserted tile number(s) have been mapped previously to \n\t\t\"$msg\".\n\tDo you want to remove the conflicted tiles number(s) in newly \n\tinserted range or remove them from the previous ones? "; - my $wind=def_popwin_size(10,30,"warning",'percent'); my $label= gen_label_in_left($msg); my $table=def_table(2,6,FALSE); $table->attach_defaults ($label , 0, 6, 0,1); $wind->add($table); - my $b1= def_button("Remove Previous"); my $b2= def_button("Remove Current"); my $b3= def_button("Cancel"); - $table->attach ($b1 , 0, 1, 1,2,'fill','fill',2,2); $table->attach ($b2 , 3, 4, 1,2,'fill','fill',2,2); $table->attach ($b3 , 5, 6, 1,2,'fill','fill',2,2); - - $wind->show_all(); - $b1->signal_connect( "clicked"=> sub{ #Remove Previous my @socs=$mpsoc->mpsoc_get_soc_list(); foreach my $p (@socs){ @@ -153,9 +141,7 @@ sub get_conflict_decision{ #set_gui_status($mpsoc,"ref",1); $wind->destroy(); get_soc_parameter_setting($mpsoc,$name, $inserted)if(defined $inserted ); - }); - $b2->signal_connect( "clicked"=> sub{#Remove Current my @new= get_diff_array($inserted,$conflicts); $mpsoc->mpsoc_add_soc_tiles_num($name,\@new) if(scalar @new ); @@ -163,9 +149,7 @@ sub get_conflict_decision{ #set_gui_status($mpsoc,"ref",1); $wind->destroy(); get_soc_parameter_setting($mpsoc,$name, \@new) if(scalar @new ); - }); - $b3->signal_connect( "clicked"=> sub{ $wind->destroy(); @@ -180,7 +164,6 @@ sub check_inserted_ip_nums{ my ($mpsoc,$name,$str)=@_; my @all_num=(); $str= remove_all_white_spaces ($str); - if($str !~ /^[0-9.:,]+$/){ message_dialog ("The Ip numbers contains invalid character" ); return; } my @chunks=split(/\s*,\s*/,$str); foreach my $p (@chunks){ @@ -195,16 +178,12 @@ sub check_inserted_ip_nums{ for (my $i=$min; $i<=$max; $i++){ if ( grep( /^$i$/, @all_num ) ) { message_dialog ("Multiple definition for IP number $i in $p" ); return; } push(@all_num,$i); - } - }else{message_dialog ("invalid range: [$p]" ); return; } - } #check if range does not exceed the tile numbers my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc); my $max_tile_num=$NE; - my @f=sort { $a <=> $b } @all_num; my @l; foreach my $num (@f){ @@ -212,12 +191,9 @@ sub check_inserted_ip_nums{ } @all_num=@l; - #check if any ip number exists in the rest my $conflicts_msg; my @conflicts; - - my @socs=$mpsoc->mpsoc_get_soc_list(); foreach my $p (@socs){ if($p ne $name){ @@ -231,9 +207,7 @@ sub check_inserted_ip_nums{ }#if } if (defined $conflicts_msg) { - get_conflict_decision($mpsoc,$name,\@all_num,\@conflicts,$conflicts_msg); - - + get_conflict_decision($mpsoc,$name,\@all_num,\@conflicts,$conflicts_msg); }else { #save the entered ips if( scalar @all_num>0){ @@ -253,10 +227,6 @@ sub check_inserted_ip_nums{ ################# # get_soc_parameter_setting ################ - - - - sub get_soc_parameter_setting{ my ($mpsoc,$soc_name,$tiles_ref)=@_; my @tiles = @{$tiles_ref} if defined ($tiles_ref); @@ -272,18 +242,15 @@ sub get_soc_parameter_setting_table{ my ($mpsoc,$soc_name,$window,$tiles_ref)=@_; my @tiles; @tiles = @{$tiles_ref} if defined ($tiles_ref); - # my $window = def_popwin_size(40,40,"Parameter setting for $soc_name mapped to tile(@tiles) ",'percent'); + # my $window = def_popwin_size(40,40,"Parameter setting for $soc_name mapped to tile(@tiles) ",'percent'); my $table = def_table(10, 7, FALSE); - my $scrolled_win = add_widget_to_scrolled_win($table); my $row=0; my $column=0; my $top=$mpsoc->mpsoc_get_soc($soc_name); - #read soc parameters my %param_value=(scalar @tiles ==1 ) ? $top->top_get_custom_soc_param($tiles[0]) : $top->top_get_default_soc_param(); $mpsoc->object_add_attribute('current_tile_param',undef,\%param_value); - my @insts=$top->top_get_all_instances(); my @exceptions=get_NI_instance_list($top); @insts=get_diff_array(\@insts,\@exceptions); @@ -295,82 +262,68 @@ sub get_soc_parameter_setting_table{ $default= $param_value{$p} if(defined $param_value{$p}); ($row,$column)=add_param_widget($mpsoc,$p,$p, $default,$type,$content,$info, $table,$row,$column,$show,'current_tile_param',undef,undef,'vertical'); } - - - # if ($type eq "Entry"){ - # my $entry=gen_entry($param_value{$p}); - # $table->attach_defaults ($entry, 3, 6, $row, $row+1); - # $entry-> signal_connect("changed" => sub{$param_value{$p}=$entry->get_text();}); - # } - # elsif ($type eq "Combo-box"){ - # my @combo_list=split(/\s*,\s*/,$content); - # my $pos=get_item_pos($param_value{$p}, @combo_list) if(defined $param_value{$p}); - # my $combo=gen_combo(\@combo_list, $pos); - # $table->attach_defaults ($combo, 3, 6, $row, $row+1); - # $combo-> signal_connect("changed" => sub{$param_value{$p}=$combo->get_active_text();}); - # - # } - # elsif ($type eq "Spin-button"){ - # my ($min,$max,$step)=split(/\s*,\s*/,$content); - # $param_value{$p}=~ s/\D//g; - # $min=~ s/\D//g; - # $max=~ s/\D//g; - # $step=~ s/\D//g; - # my $spin=gen_spin($min,$max,$step); - # $spin->set_value($param_value{$p}); - # $table->attach_defaults ($spin, 3, 4, $row, $row+1); - # $spin-> signal_connect("value_changed" => sub{$param_value{$p}=$spin->get_value_as_int();}); - # - # # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2); - # } - # my $label =gen_label_in_center($p); - # $table->attach_defaults ($label, 0, 3, $row, $row+1); - # if (defined $info){ - # my $info_button=def_image_button('icons/help.png'); - # $table->attach_defaults ($info_button, 6, 7, $row, $row+1); - # $info_button->signal_connect('clicked'=>sub{ - # message_dialog($info); - # - # }); - # - # } - # $row++; - # - # - # } + # if ($type eq "Entry"){ + # my $entry=gen_entry($param_value{$p}); + # $table->attach_defaults ($entry, 3, 6, $row, $row+1); + # $entry-> signal_connect("changed" => sub{$param_value{$p}=$entry->get_text();}); + # } + # elsif ($type eq "Combo-box"){ + # my @combo_list=split(/\s*,\s*/,$content); + # my $pos=get_item_pos($param_value{$p}, @combo_list) if(defined $param_value{$p}); + # my $combo=gen_combo(\@combo_list, $pos); + # $table->attach_defaults ($combo, 3, 6, $row, $row+1); + # $combo-> signal_connect("changed" => sub{$param_value{$p}=$combo->get_active_text();}); + # + # } + # elsif ($type eq "Spin-button"){ + # my ($min,$max,$step)=split(/\s*,\s*/,$content); + # $param_value{$p}=~ s/\D//g; + # $min=~ s/\D//g; + # $max=~ s/\D//g; + # $step=~ s/\D//g; + # my $spin=gen_spin($min,$max,$step); + # $spin->set_value($param_value{$p}); + # $table->attach_defaults ($spin, 3, 4, $row, $row+1); + # $spin-> signal_connect("value_changed" => sub{$param_value{$p}=$spin->get_value_as_int();}); + # + # # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2); + # } + # my $label =gen_label_in_center($p); + # $table->attach_defaults ($label, 0, 3, $row, $row+1); + # if (defined $info){ + # my $info_button=def_image_button('icons/help.png'); + # $table->attach_defaults ($info_button, 6, 7, $row, $row+1); + # $info_button->signal_connect('clicked'=>sub{ + # message_dialog($info); + # + # }); + # } + # $row++; + # } } my $ok = def_image_button('icons/select.png','OK'); my $okbox=def_hbox(TRUE,0); $okbox->pack_start($ok, FALSE, FALSE,0); - - my $mtable = def_table(10, 1, TRUE); - $mtable->attach_defaults($scrolled_win,0,1,0,9); $mtable->attach_defaults($okbox,0,1,9,10); - - - $ok-> signal_connect("clicked" => sub{ $window->destroy if(defined $window); #save new values my $ref=$mpsoc->object_get_attribute('current_tile_param'); %param_value=%{$ref}; - - # if(!defined $tile ) { + # if(!defined $tile ) { # $top->top_add_default_soc_param(\%param_value); # $mpsoc->object_add_attribute('soc_param',"default",\%param_value); - # } - # else { - foreach my $tile (@tiles){ + # } + # else { + foreach my $tile (@tiles){ $top->top_add_custom_soc_param(\%param_value,$tile); $mpsoc->object_add_attribute('soc_param',"custom_${soc_name}",\%param_value); } $mpsoc->object_add_attribute('current_tile_param',undef,undef); set_gui_status($mpsoc,"refresh_soc",1); - - }); $mtable->show_all(); return $mtable; @@ -379,7 +332,6 @@ sub get_soc_parameter_setting_table{ ################ # tile_set_widget ################ - sub tile_set_widget{ my ($mpsoc,$soc_name,$num,$table,$show,$row)=@_; #my $label=gen_label_in_left($soc); @@ -391,11 +343,9 @@ sub tile_set_widget{ my $set= def_image_button('icons/right.png'); my $remove= def_image_button('icons/cancel.png'); #my $setting= def_image_button('icons/setting.png','setting'); - - my $button = def_colored_button($soc_name,$num); $button->signal_connect("clicked"=> sub{ - # get_soc_parameter_setting($mpsoc,$soc_name,undef); + # get_soc_parameter_setting($mpsoc,$soc_name,undef); }); $set->signal_connect("clicked"=> sub{ @@ -406,39 +356,25 @@ sub tile_set_widget{ get_soc_parameter_setting($mpsoc,$soc_name,\@all_num); } }); - $remove->signal_connect("clicked"=> sub{ $mpsoc->mpsoc_remove_soc($soc_name); set_gui_status($mpsoc,"ref",1); }); - - -if($show){ - $table->attach ( $button, 0, 1, $row,$row+1,'fill','fill',2,2); - $table->attach ( $remove, 1, 2, $row,$row+1,'fill','shrink',2,2); - $table->attach ( $entry , 2, 3, $row,$row+1,'fill','shrink',2,2); - $table->attach ( $set, 3, 4, $row,$row+1,'fill','shrink',2,2); - - - - $row++; -} - + if($show){ + $table->attach ( $button, 0, 1, $row,$row+1,'fill','fill',2,2); + $table->attach ( $remove, 1, 2, $row,$row+1,'fill','shrink',2,2); + $table->attach ( $entry , 2, 3, $row,$row+1,'fill','shrink',2,2); + $table->attach ( $set, 3, 4, $row,$row+1,'fill','shrink',2,2); + $row++; + } return $row; - - -} - - - +} ################## # defualt_tilles_setting ################### - sub defualt_tilles_setting { my ($mpsoc,$table,$show,$row,$info)=@_; - #title my $separator1 = gen_Hsep(); my $separator2 = gen_Hsep(); @@ -448,15 +384,11 @@ sub defualt_tilles_setting { $box1->pack_start( $title2, FALSE, FALSE, 3); $box1->pack_start( $separator2, FALSE, FALSE, 3); if($show){$table->attach_defaults ($box1 ,0,4, $row,$row+1);$row++;} - - my $label = gen_label_in_left("Tiles path:"); my $entry = gen_entry(); my $browse= def_image_button("icons/browse.png"); my $file= $mpsoc->object_get_attribute('setting','soc_path'); if(defined $file){$entry->set_text($file);} - - $browse->signal_connect("clicked"=> sub{ my $entry_ref=$_[1]; my $file; @@ -468,13 +400,10 @@ sub defualt_tilles_setting { $mpsoc->mpsoc_remove_all_soc(); set_gui_status($mpsoc,"ref",1); #check_input_file($file,$socgen,$info); - #print "file = $file\n"; + #print "file = $file\n"; } $dialog->destroy; - } , \$entry); - - $entry->signal_connect("activate"=>sub{ my $file_name=$entry->get_text(); $mpsoc->object_add_attribute('setting','soc_path',$file_name); @@ -482,9 +411,6 @@ sub defualt_tilles_setting { set_gui_status($mpsoc,"ref",1); #check_input_file($file_name,$socgen,$info); }); - - - if($show){ my $tmp=gen_label_in_left(" "); $table->attach ($label, 0, 1 , $row,$row+1,'fill','shrink',2,2); @@ -493,20 +419,12 @@ sub defualt_tilles_setting { $table->attach ($browse, 3, 4, $row,$row+1,'fill','shrink',2,2); $row++; } - - - my @socs=$mpsoc->mpsoc_get_soc_list(); - if( scalar @socs == 0){ + if( scalar @socs == 0){ @socs=get_soc_list($mpsoc,$info); - } @socs=$mpsoc->mpsoc_get_soc_list(); - - - my $lab1=gen_label_in_center(' Tile name'); - my $lab2=gen_label_help('Define the tile numbers that each IP is mapped to. you can add individual numbers or ranges as follow e.g. individual numbers: 5,6,7,8,9,10 @@ -516,25 +434,18 @@ sub defualt_tilles_setting { $table->attach_defaults ($lab1 ,0,1, $row,$row+1); $table->attach_defaults ($lab2 ,2,3, $row,$row+1);$row++; } - my $soc_num=0; - foreach my $soc_name (@socs){ + foreach my $soc_name (@socs){ $row=tile_set_widget ($mpsoc,$soc_name,$soc_num,$table,$show,$row); - $soc_num++; - - } + $soc_num++; + } return $row; - } - - ####################### # noc_config ###################### - - sub noc_topology_setting_gui { my ($mpsoc,$table,$txview,$row,$show_noc,$noc_id)=@_; my $noc_param="noc_param$noc_id"; @@ -543,15 +454,13 @@ sub noc_topology_setting_gui { my $label='Topology'; my $param='TOPOLOGY'; my $default='"MESH"'; - my $content='"MESH","FMESH","TORUS","RING","LINE","FATTREE","TREE","STAR","CUSTOM"'; + my $content='"MESH","FMESH","MESH_3D","TORUS","RING","LINE","FATTREE","TREE","STAR","CUSTOM"'; my $type='Combo-box'; my $info="Specifies the NoC topology. Options include $content"; $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1); - my $topology=$mpsoc->object_get_attribute($noc_param,'TOPOLOGY'); - if($topology ne '"CUSTOM"' ){ #topology T1 parameter $label= @@ -560,80 +469,83 @@ sub noc_topology_setting_gui { $param= 'T1'; $default= '2'; $content= - ($topology eq '"MESH"' || $topology eq '"TORUS"') ? '2,16,1': + ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"MESH_3D"') ? '2,16,1': ($topology eq '"FMESH"')? '1,16,1': ($topology eq '"FATTREE"' || $topology eq '"TREE"' )? '2,6,1':'2,64,1'; $info= ($topology eq '"FATTREE"' || $topology eq '"TREE"' )? 'number of last level individual router`s endpoints.' :'Number of NoC routers in row (X dimension)'; $type= 'Spin-button'; - $noc_param_comment{$param}="$info"; + $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1); - #Topology T2 parameter - if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"FATTREE"' || $topology eq '"TREE"' ) { + if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"FATTREE"' || $topology eq '"TREE"' || $topology eq '"MESH_3D"') { $label= ($topology eq '"FATTREE"' || $topology eq '"TREE"')? 'L' :'Routers per column'; $param= 'T2'; $default='2'; $content= ($topology eq '"FMESH"')? '1,16,1': '2,16,1'; $info= ($topology eq '"FATTREE"' || $topology eq '"TREE"')? 'Fattree layer number (The height of FT)':'Number of NoC routers in column (Y dimension)'; $type= 'Spin-button'; - $noc_param_comment{$param}="$info"; + $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1); } else { - $mpsoc->object_add_attribute($noc_param,'T2',1); + $mpsoc->object_add_attribute($noc_param,'T2',1); } #Topology T3 parameter - if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"RING"' || $topology eq '"LINE"') { - $label="Router's endpoint number"; + if($topology eq '"MESH_3D"') { + $label= 'Routers per layer'; $param= 'T3'; $default='1'; + $content= '1,16,1'; + $info= 'Number of NoC layers (Z dimension)'; + $type= 'Spin-button'; + $noc_param_comment{$param}="$info"; + ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1); + } else { + $mpsoc->object_add_attribute($noc_param,'T4',1); + $mpsoc->object_add_attribute_order($noc_param,"T4"); + } + #Topology T3/T4 parameter + if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"RING"' || $topology eq '"LINE"' || $topology eq '"MESH_3D"') { + $label="Router's endpoint number"; + $param= $topology eq '"MESH_3D"' ? 'T4' : 'T3'; + $default='1'; $content='1,4,1'; $info= "Number of endpoints per router. In $topology topology, each router can have up to 4 endpoint processing tile."; $type= 'Spin-button'; - $noc_param_comment{$param}="$info"; + $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1); } - - }else{#its a custom Topology ($row,$coltmp)=config_custom_topology_gui($mpsoc,$table,$txview,$row,$noc_id); } return ($row,$coltmp); - } - sub noc_config{ my ($mpsoc,$table,$txview,$noc_id)=@_; $noc_id = "" if(!defined $noc_id); my $noc_param="noc_param$noc_id"; my $noc_type="noc_type$noc_id"; - #title my $row=0; my $title=gen_label_in_center("NoC Configuration"); $table->attach ($title , 0, 4, $row, $row+1,'expand','shrink',2,2); $row++; add_Hsep_to_table ($table,0,4,$row); $row++; - my $label; my $param; my $default; my $type; my $content; my $info; - - - #parameter start my $b1; my $show_noc=$mpsoc->object_get_attribute('setting','show_noc_setting'); if(!defined $show_noc){ $show_noc=1; $mpsoc->object_add_attribute('setting','show_noc_setting',$show_noc); - } if($show_noc == 0){ $b1= def_image_button("icons/down.png","NoC Parameters"); @@ -642,9 +554,7 @@ sub noc_config{ $table->attach ( $b1 , 0, 2, $row,$row+1,'fill','shrink',2,2); $row++; } - my $coltmp=0; - #NoC_ID $label='NoC ID'; $param='NOC_ID'; @@ -654,7 +564,6 @@ sub noc_config{ $info="Unique identifier for the NoC. Will be modified by phy_noc_gen.pl script."; $noc_param_comment{'NOC_ID'}="Unique identifier for the NoC. Will be modified by phy_noc_gen.pl script"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param,1); - #Router type $label='Router Type'; $param='ROUTER_TYPE'; @@ -665,11 +574,8 @@ sub noc_config{ VC-based routers offer higher performance, fully adaptive routing and traffic isolation for different packet classes."; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_type,1); my $router_type=$mpsoc->object_get_attribute($noc_type,"ROUTER_TYPE"); - - ($row,$coltmp) =noc_topology_setting_gui($mpsoc,$table,$txview,$row,$show_noc,$noc_id); my $topology=$mpsoc->object_get_attribute($noc_param,'TOPOLOGY'); - #VC number per port if($router_type eq '"VC_BASED"'){ my $v=$mpsoc->object_get_attribute($noc_param,'V'); @@ -697,8 +603,6 @@ sub noc_config{ $info=($router_type eq '"VC_BASED"')? 'Buffer queue size per VC in flits' : 'Buffer queue size in flits'; $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,undef); - - #Local port buffer width per VC $label=($router_type eq '"VC_BASED"')? 'Local port Buffer flits per VC': "Local Port Buffer flits"; $param='LB'; @@ -715,7 +619,6 @@ sub noc_config{ }else{ $mpsoc->object_add_attribute($noc_param,'LB','B'); } - #packet payload width $label='Payload width'; $param='Fpay'; @@ -725,42 +628,46 @@ sub noc_config{ $info="The packet payload width in bits"; $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info,$table,$row,undef,$show_noc,$noc_param,undef); - -if($topology ne '"CUSTOM"' ){ - #routing algorithm - $label='Routing Algorithm'; - $param="ROUTE_NAME"; - $type="Combo-box"; - if($router_type eq '"VC_BASED"'){ - $content=($topology eq '"MESH"' || $topology eq '"FMESH"')? '"XY","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN","FULL_ADPT"' : - ($topology eq '"TORUS"')? '"TRANC_XY","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST","TRANC_FULL_ADPT"': - ($topology eq '"RING"')? '"TRANC_XY"' : - ($topology eq '"LINE"')? '"XY"': - ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"': - ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"'; - }else{ - $content=($topology eq '"MESH"' || $topology eq '"FMESH"')? '"XY","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN"' : - ($topology eq '"TORUS"')? '"TRANC_XY","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST"': - ($topology eq '"RING"')? '"TRANC_XY"' : - ($topology eq '"LINE"')? '"XY"': - ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"' : - ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"'; - } - $default=($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"LINE"' )? '"XY"': - ($topology eq '"TORUS"'|| $topology eq '"RING"')? '"TRANC_XY"' : - ($topology eq '"FATTREE"')? '"NCA_STRAIGHT_UP"' : - ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"'; - + + if($topology ne '"CUSTOM"' ){ + #routing algorithm + $label='Routing Algorithm'; + $param="ROUTE_NAME"; + $type="Combo-box"; + if($router_type eq '"VC_BASED"'){ + $content= + ($topology eq '"MESH_3D"') ? '"DOR"' : + ($topology eq '"MESH"' || $topology eq '"FMESH"')? '"DOR","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN","FULL_ADPT"' : + ($topology eq '"TORUS"')? '"TRANC_DOR","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST","TRANC_FULL_ADPT"': + ($topology eq '"RING"')? '"TRANC_DOR"' : + ($topology eq '"LINE"')? '"DOR"': + ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"': + ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"'; + }else{ + $content= + ($topology eq '"MESH_3D"') ? '"DOR"' : + ($topology eq '"MESH"' || $topology eq '"FMESH"')? '"DOR","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN"' : + ($topology eq '"TORUS"')? '"TRANC_DOR","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST"': + ($topology eq '"RING"')? '"TRANC_DOR"' : + ($topology eq '"LINE"')? '"DOR"': + ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"' : + ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"'; + } + $default= + ($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"LINE"'|| $topology eq '"MESH_3D"' )? '"DOR"': + ($topology eq '"TORUS"'|| $topology eq '"RING"')? '"TRANC_DOR"' : + ($topology eq '"FATTREE"')? '"NCA_STRAIGHT_UP"' : + ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"'; my $info_mesh="Select the routing algorithm. Options are: - - XY: Deterministic routing (Dimension-Order Routing, DoR). + - DOR: Dimension-Order Deterministic routing (XY). - WEST_FIRST, NORTH_LAST, NEGATIVE_FIRST, ODD_EVEN: Partially adaptive routing algorithms based on turn model restrictions. - FULL_ADPT: Fully adaptive routing based on Duato's algorithm; requires at least two virtual channels (VCs) per port."; my $info_fat="Nearest common ancestor (NCA) where the up port is selected randomly (RND), based on destination endpoint address (DST) or it is the top port that is located in front of the port which has received the packet (STRAIGHT) "; - - $info=($topology eq '"FATTREE"')? $info_fat : - ($topology eq '"TREE"') ? "Nearest common ancestor": $info_mesh; + $info= + ($topology eq '"FATTREE"')? $info_fat : + ($topology eq '"TREE"') ? "Nearest common ancestor": $info_mesh; $noc_param_comment{$param}="$info options are $content"; my $show_routing =($topology eq '"STAR"' )? 0 : $show_noc; @@ -781,7 +688,6 @@ sub noc_config{ $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,1,$noc_param,1); } - #PCK_TYPE $label='Packet type'; $param='PCK_TYPE'; @@ -795,13 +701,9 @@ sub noc_config{ b) Two-flit: Separate header and tail flits. c) Multi-flit: Header, one or more body flits, and a tail flit."; $noc_param_comment{$param}="$info"; - ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1); - my $pck_type=$mpsoc->object_get_attribute($noc_param,'PCK_TYPE'); - if($pck_type eq '"MULTI_FLIT"'){ - #MIN_PCK_SIZE # 2 //minimum packet size in flits. The minimum value is 1. $label='Minimum packet size'; @@ -818,7 +720,6 @@ sub noc_config{ }else{ $mpsoc->object_add_attribute($noc_param,'MIN_PCK_SIZE',1); } - # BYTE_EN $label='Byte Enable'; $param='BYTE_EN'; @@ -831,7 +732,6 @@ sub noc_config{ $type="Combo-box"; $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param); - #CAST_TYPE $label='Casting Type'; $param='CAST_TYPE'; @@ -925,7 +825,7 @@ sub noc_config{ from neighboring routers. Please refer to the usere manual for more information"; $noc_param_comment{$param}="$info"; $default=3; - if($topology ne '"CUSTOM"' && $route ne '"XY"' && $route ne '"TRANC_XY"' ){ + if($topology ne '"CUSTOM"' && $route ne '"DOR"' && $route ne '"TRANC_DOR"' ){ ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef); } else { ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param,undef); @@ -933,7 +833,7 @@ sub noc_config{ #Fully adaptive routing setting my $v=$mpsoc->object_get_attribute($noc_param,"V"); - $label="Select Escap VC"; + $label="Select Escap VC"; $param="ESCAP_VC_MASK"; $type="Check-box"; $content=$v; @@ -960,8 +860,6 @@ sub noc_config{ $type='Combo-box'; $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef); - - #vc/sw allocator type $label = 'VC/SW combination type'; $param='COMBINATION_TYPE'; @@ -998,8 +896,6 @@ sub noc_config{ $content='0,16,1'; $type='Spin-button'; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,5); - - my $class=$mpsoc->object_get_attribute($noc_param,"C"); my $v=$mpsoc->object_get_attribute($noc_param,"V"); $default= "$v\'b"; @@ -1016,9 +912,7 @@ sub noc_config{ $info="Select the permitted VCs which the message class $i can be sent via them."; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,'class_param',undef); } - }#($router_type eq '"VC_BASED"') - #simulation debuge enable $label='Debug enable'; $param='DEBUG_EN'; @@ -1075,9 +969,6 @@ sub noc_config{ $noc_param_comment{$param}="$info"; $type= 'Spin-button'; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$wrra_show,$noc_param,undef); - - - $label='Self loop enable'; $param='SELF_LOOP_EN'; $default='0'; @@ -1113,8 +1004,7 @@ sub noc_config{ $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,1); $noc_param_comment{$param}="$info"; - - + #VC_CONFIG_TABLE my $hetero_en=$mpsoc->object_get_attribute($noc_param,'HETERO_VC'); $label='Heterogeneous VC setting'; @@ -1146,12 +1036,9 @@ sub noc_config{ $mpsoc->object_add_attribute($noc_param,"MAX_PORT",$MAX_P); $row=hetero_vc_widget($mpsoc,$row,$NR,$MAX_P,$label,$info,$table,$noc_id,$param,$v); } - - $mpsoc->object_add_attribute_order($noc_param,"MAX_ROUTER"); $mpsoc->object_add_attribute_order($noc_param,"MAX_PORT"); $mpsoc->object_add_attribute_order($noc_param,$param); - if($show_noc == 1){ $b1= def_image_button("icons/up.png","NoC Parameters"); $table->attach ( $b1 , 0, 2, $row,$row+1,'fill','shrink',2,2); @@ -1162,10 +1049,7 @@ sub noc_config{ $mpsoc->object_add_attribute('setting','show_noc_setting',$show_noc); set_gui_status($mpsoc,"ref",1); }); - - #other fixed parameters - # AVC_ATOMIC_EN $label='AVC_ATOMIC_EN'; $param='AVC_ATOMIC_EN'; @@ -1175,10 +1059,7 @@ sub noc_config{ $type="Combo-box"; $noc_param_comment{$param}="$info"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param); - - $mpsoc->object_add_attribute('noc_param_comments',undef,\%noc_param_comment); - return $row; } @@ -1206,7 +1087,6 @@ sub set_hetero_vc_list{ my $row=0; my $col=0; my $init = $mpsoc->object_get_attribute($noc_param,$param); - my $label = "$param="; my ($Ebox,$entry) = def_h_labeled_entry ($label); $entry->set_sensitive (FALSE); @@ -1225,7 +1105,6 @@ sub set_hetero_vc_list{ for(my $r=0;$r<$nr;$r++){ my $label= gen_label_in_center("R$r"); $table->attach ($label , $col, $col+4, $row,$row+1,'fill','shrink',2,2);$col+=4; - for(my $p=0;$p<$np;$p++){ my $w; ($row,$col,$w)=add_param_widget ($mpsoc,undef,"R$r-P$p", $v,"Combo-box",$content,undef, $table,$row,$col,1,$vc_param,undef,undef,"horizental"); @@ -1281,27 +1160,20 @@ sub set_multicast_list{ my $init = $mpsoc->object_get_attribute($noc_param,"MCAST_ENDP_LIST"); $init =~ s/'h//g; my @arr= reverse split (//, $init); - - my $label = "Multicast Node list (hex fromat)"; my ($Ebox,$entry) = def_h_labeled_entry ($label); $entry->set_sensitive (FALSE); - my @sel_options= ("Select","All","None","2n","3n","4n","2n+1","3n+1","3n+2","4n+1","4n+2","4n+3"); my $combo= gen_combo(\@sel_options, 0); $table->attach ($combo , 0, 1, $row,$row+1,'fill','shrink',2,2); #get the number of endpoints my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc,$noc_id); my @check; - - - my $sel_val="Init"; for (my $i=0; $i<$NE; $i++){ if($i%10 == 0){ $row++;$col=0;} my $box; my $l=$NE -$i-1; - my $char = $arr[$l/4]; $char=0 if (!defined $char); my $hex = hex($char); @@ -1309,21 +1181,17 @@ sub set_multicast_list{ ($box,$check[$l])=def_h_labeled_checkbutton("$l"); $table->attach ($box , $col, $col+1, $row,$row+1,'fill','shrink',2,2); $col++; - if($bit==1){ $check[$l]->set_active(TRUE); } - $check[$l]-> signal_connect("toggled" => sub{ get_multicast_val ($mpsoc,$entry,$NE,@check)if($sel_val eq "Select"); }); } $row++; $col=0; - $sel_val="Select"; get_multicast_val ($mpsoc,$entry,$NE,@check); - $combo-> signal_connect("changed" => sub{ $sel_val=$combo->get_active_text(); my $n=1; @@ -1341,25 +1209,17 @@ sub set_multicast_list{ $r=0; $n=1 if(!defined $n); } - for (my $i=0; $i<$NE; $i++){ if($i % $n == $r){ $check[$i]->set_active(TRUE);} } $combo->set_active(0); get_multicast_val ($mpsoc,$entry,$NE,@check); - }); - - - $table->attach ($Ebox , 0, 10, $row,$row+1,'fill','shrink',2,2);$row++; - my $main_table=def_table(10,10,FALSE); - my $ok = def_image_button('icons/select.png','OK'); $main_table->attach_defaults ($table , 0, 12, 0,11); $main_table->attach ($ok,5, 6, 11,12,'shrink','shrink',0,0); - $ok->signal_connect('clicked', sub { my $s=get_multicast_val ($mpsoc,$entry,$NE,@check); my $n=$entry->get_text( ); @@ -1368,10 +1228,6 @@ sub set_multicast_list{ set_gui_status($mpsoc,"ref",1); $window->destroy; }); - - - - my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_multicast'); add_widget_to_scrolled_win($main_table,$scrolled_win); $window->add($scrolled_win); @@ -1391,17 +1247,14 @@ sub get_multicast_val { $h=0; } } - $n="$h".$n if($NE%4!=0); $n="'h".$n; $entry->set_text("$n"); return $s; - } ############# # config_custom_topology_gui ############ - sub config_custom_topology_gui{ my($mpsoc,$table,$txview,$row,$noc_id)=@_; my $noc_param="noc_param$noc_id"; @@ -1411,19 +1264,17 @@ sub config_custom_topology_gui{ my $file="$dir/param.obj"; unless (-f $file){ add_colored_info($txview,"No Custom topology find in $dir. You can define a Custom Topology using ProNoC Topology maker.\n",'red'); - return; - } + return; + } - my %param; + my %param; my ($pp,$r,$err) = regen_object($file ); - if ($r){ + if ($r){ add_colored_info($txview,"Error: cannot open $file file: $err\n",'red'); return; - } - + } %param=%{$pp}; my @topologies=sort keys %param; - my $label='Topology_name'; my $param='CUSTOM_TOPOLOGY_NAME'; my $default=$topologies[0]; @@ -1431,59 +1282,40 @@ sub config_custom_topology_gui{ my $type='Combo-box'; my $info="Custom topology name"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,1,$noc_param,1); - - my $topology_name=$mpsoc->object_get_attribute($noc_param,'CUSTOM_TOPOLOGY_NAME'); - - + my $topology_name=$mpsoc->object_get_attribute($noc_param,'CUSTOM_TOPOLOGY_NAME'); $label='Routing Algorithm'; $param="ROUTE_NAME"; $type="Combo-box"; - $content=$param{$topology_name}{'ROUTE_NAME'}; + $content=$param{$topology_name}{'ROUTE_NAME'}; my @rr=split(/\s*,\s*/,$content); $default=$rr[0]; $info="Select the routing algorithm"; ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,1,$noc_param,1); - - $mpsoc->object_add_attribute($noc_param,'T1',$param{$topology_name}{'T1'}); - $mpsoc->object_add_attribute($noc_param,'T2',$param{$topology_name}{'T2'}); - $mpsoc->object_add_attribute($noc_param,'T3',$param{$topology_name}{'T3'}); - $mpsoc->object_add_attribute('noc_connection','er_addr',$param{$topology_name}{'er_addr'}); - - + $mpsoc->object_add_attribute($noc_param,'T1',$param{$topology_name}{'T1'}); + $mpsoc->object_add_attribute($noc_param,'T2',$param{$topology_name}{'T2'}); + $mpsoc->object_add_attribute($noc_param,'T3',$param{$topology_name}{'T3'}); + $mpsoc->object_add_attribute($noc_param,'T4',$param{$topology_name}{'T4'}); + $mpsoc->object_add_attribute('noc_connection','er_addr',$param{$topology_name}{'er_addr'}); return ($row,$coltmp); - } - - - ####################### # get_config ###################### - sub get_config{ my ($mpsoc,$info)=@_; my $table=def_table(20,10,FALSE);# my ($row,$col,$homogeneous)=@_; - - #noc_setting my $row=noc_config ($mpsoc,$table,$info); - - #tiles setting my $tile_set; my $show=$mpsoc->object_get_attribute('setting','show_tile_setting'); - if($show == 0){ $tile_set= def_image_button("icons/down.png","Tiles setting"); $table->attach ( $tile_set , 0, 2, $row,$row+1,'fill','shrink',2,2); $row++; - } - $row=defualt_tilles_setting($mpsoc,$table,$show,$row,$info); - - #end tile setting if($show == 1){ $tile_set= def_image_button("icons/up.png","Tiles setting"); @@ -1494,10 +1326,7 @@ sub get_config{ $show=($show==1)?0:1; $mpsoc->object_add_attribute('setting','show_tile_setting',$show); set_gui_status($mpsoc,"ref",1); - - }); - my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'get_config_adj'); add_widget_to_scrolled_win($table,$scrolled_win); return $scrolled_win; @@ -1507,28 +1336,24 @@ sub get_config{ ############# # gen_all_tiles ########### - sub gen_all_tiles{ my ($mpsoc,$info, $hw_dir,$sw_dir)=@_; - my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc); + my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc); my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name'); - my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; + my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; my @generated_tiles; for (my $tile_num=0;$tile_num<$NE;$tile_num++){ #print "$tile_num\n"; my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num); next if(!defined $soc_name); - - - my $path=$mpsoc->object_get_attribute('setting','soc_path'); + my $path=$mpsoc->object_get_attribute('setting','soc_path'); $path=~ s/ /\\ /g; my $p = "$path/$soc_name.SOC"; my ($soc,$r,$err) = regen_object($p); - if ($r){ + if ($r){ show_info($info,"**Error reading $p file: $err\n"); next; } - #update core id $soc->object_add_attribute('global_param','CORE_ID',$tile_num); #update NoC param @@ -1540,13 +1365,11 @@ sub gen_all_tiles{ my %z; foreach my $p (sort keys %{$nocparam}){ $z{$p}="Parameter"; - } + } $soc->soc_add_instance_param_type($nis[0] ,\%z); #foreach my $p ( sort keys %nocparam ) { - - # print "$p = $nocparam{$p} \n"; + # print "$p = $nocparam{$p} \n"; #} - my $sw_path = "$sw_dir/tile$tile_num"; #print "$sw_path\n"; if( grep (/^$soc_name$/,@generated_tiles)){ # This soc is generated before only create the software file @@ -1555,24 +1378,19 @@ sub gen_all_tiles{ generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,1,"merge",1); move ("$hw_dir/$soc_name.sv","$hw_dir/tiles/"); my @tmp= ("$hw_dir/tiles/$soc_name.sv"); - add_to_project_file_list(\@tmp,"$hw_dir/tiles",$hw_dir); - - } + add_to_project_file_list(\@tmp,"$hw_dir/tiles",$hw_dir); + } }#$tile_num - - } ################ # generate_soc ################# - sub generate_soc_files{ my ($mpsoc,$soc,$info)=@_; my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name'); my $soc_name=$soc->object_get_attribute('soc_name'); - # copy all files in project work directory my $dir = Cwd::getcwd(); my $project_dir = abs_path("$dir/../../"); @@ -1581,95 +1399,73 @@ sub generate_soc_files{ mkpath("$target_dir/src_verilog/lib/",1,0755); mkpath("$target_dir/src_verilog/tiles/",1,0755); mkpath("$target_dir/sw",1,0755); - my ($file_v,$tmp)=soc_generate_verilog($soc,"$target_dir/sw",$info); - # Write object file open(FILE, ">lib/soc/$soc_name.SOC") || die "Can not open: $!"; print FILE perl_file_header("$soc_name.SOC"); print FILE Data::Dumper->Dump([\%$soc],['soc']); close(FILE) || die "Error closing file: $!"; - # Write verilog file open(FILE, ">lib/verilog/$soc_name.sv") || die "Can not open: $!"; print FILE $file_v; close(FILE) || die "Error closing file: $!"; - - - #copy hdl codes in src_verilog my ($hdl_ref,$warnings)= get_all_files_list($soc,"hdl_files"); my ($sim_ref,$warnings2)= get_all_files_list($soc,"hdl_files_ticked"); #hdl_ref-sim_ref my @n= get_diff_array($hdl_ref,$sim_ref); $hdl_ref=\@n; - - foreach my $f(@{$hdl_ref}){ + foreach my $f(@{$hdl_ref}){ my $n="$project_dir$f"; - if (-f "$n") { - copy ("$n","$target_dir/src_verilog/lib"); - }elsif(-f "$f" ){ - copy ("$f","$target_dir/src_verilog/lib"); - } + if (-f "$n") { + copy ("$n","$target_dir/src_verilog/lib"); + }elsif(-f "$f" ){ + copy ("$f","$target_dir/src_verilog/lib"); + } } - show_colored_info($info,$warnings,'green') if(defined $warnings); - - - - foreach my $f(@{$sim_ref}){ - my $n="$project_dir$f"; - if (-f "$n") { - copy ("$n","$target_dir/src_sim"); - }elsif(-f "$f" ){ - copy ("$f","$target_dir/src_sim"); - } - } - show_colored_info($info,$warnings2,'green') if(defined $warnings2); - - + show_colored_info($info,$warnings,'green') if(defined $warnings); + foreach my $f(@{$sim_ref}){ + my $n="$project_dir$f"; + if (-f "$n") { + copy ("$n","$target_dir/src_sim"); + }elsif(-f "$f" ){ + copy ("$f","$target_dir/src_sim"); + } + } + show_colored_info($info,$warnings2,'green') if(defined $warnings2); #save project hdl file/folder list my @new_file_ref; foreach my $f(@{$hdl_ref}){ - my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$"); - push(@new_file_ref,"$target_dir/src_verilog/lib/$name$suffix"); + my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$"); + push(@new_file_ref,"$target_dir/src_verilog/lib/$name$suffix"); } foreach my $f(@{$sim_ref}){ - my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$"); - push(@new_file_ref,"$target_dir/src_sim/$name$suffix"); + my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$"); + push(@new_file_ref,"$target_dir/src_sim/$name$suffix"); } open(FILE, ">$target_dir/src_verilog/file_list") || die "Can not open: $!"; print FILE Data::Dumper->Dump([\@new_file_ref],['files']); close(FILE) || die "Error closing file: $!"; - - - - move ("$dir/lib/verilog/$soc_name.sv","$target_dir/src_verilog/tiles/"); copy_noc_files($project_dir,"$target_dir/src_verilog/lib"); - - # Write header file generate_header_file($soc,$project_dir,$target_dir,$target_dir,$dir); #use File::Copy::Recursive qw(dircopy); #dircopy("$dir/../src_processor/aeMB/compiler","$target_dir/sw/") or die("$!\n"); my $msg="SoC \"$soc_name\" has been created successfully at $target_dir/ "; - return $msg; -} - + return $msg; +} sub generate_mpsoc_lib_file { my ($mpsoc,$info) = @_; my $tmp = $mpsoc; my $name=$mpsoc->object_get_attribute('mpsoc_name'); - open(FILE, ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!"; print FILE perl_file_header("$name.MPSOC"); print FILE Data::Dumper->Dump([\%$tmp],['mpsoc']); close(FILE) || die "Error closing file: $!"; - #get_soc_list($mpsoc,$info); - -} +} sub check_mpsoc_name { my ($name,$info,$label)= @_; @@ -1686,63 +1482,53 @@ sub check_mpsoc_name { message_dialog("Please define the $label filed!"); return 1; } - return 0; + return 0; } ################ # generate_mpsoc ################# - sub generate_mpsoc{ my ($mpsoc,$info,$show_sucess_msg)=@_; my $name=$mpsoc->object_get_attribute('mpsoc_name'); return 0 if (check_mpsoc_name($name,$info)); - # make target dir my $dir = Cwd::getcwd(); my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$name"; my $hw_dir = "$target_dir/src_verilog"; my $sw_dir = "$target_dir/sw"; - # rmtree ($hw_dir); mkpath("$hw_dir",1,01777); mkpath("$hw_dir/lib/",1,0755); mkpath("$hw_dir/tiles",1,0755); mkpath("$sw_dir",1,0755); - #remove old rtl files that were copied by ProNoC my ($old_file_ref,$r,$err) = regen_object("$hw_dir/file_list"); if (defined $old_file_ref){ remove_file_and_folders($old_file_ref,$target_dir); } unlink "$hw_dir/file_list"; - #generate/copy all tiles HDL/SW codes gen_all_tiles($mpsoc,$info, $hw_dir,$sw_dir ); - #copy clk setting hdl codes in src_verilog my $project_dir = abs_path("$dir/../../"); my $sc_soc =get_source_set_top($mpsoc,'mpsoc'); - my ($file_ref,$warnings)= get_all_files_list($sc_soc,"hdl_files"); - my ($sim_ref,$warnings2)= get_all_files_list($sc_soc,"hdl_files_ticked"); + my ($file_ref,$warnings)= get_all_files_list($sc_soc,"hdl_files"); + my ($sim_ref,$warnings2)= get_all_files_list($sc_soc,"hdl_files_ticked"); #file_ref-sim_ref my @n= get_diff_array($file_ref,$sim_ref); $file_ref=\@n; - copy_file_and_folders($file_ref,$project_dir,"$hw_dir/lib"); show_colored_info($info,$warnings,'green') if(defined $warnings); add_to_project_file_list($file_ref,"$hw_dir/lib/",$hw_dir); - + copy_file_and_folders($sim_ref,$project_dir,"$hw_dir/../src_sim"); show_colored_info($info,$warnings2,'green') if(defined $warnings2); add_to_project_file_list($sim_ref,"$hw_dir/../src_sim",$hw_dir); - - #generate header file containig the tiles physical addresses gen_tiles_physical_addrsses_header_file($mpsoc,"$sw_dir/phy_addr.h"); - #copy all NoC HDL files #my @files = glob( "$dir/../rtl/src_noc/*.v" ); #copy_file_and_folders(\@files,$project_dir,"$hw_dir/lib/"); @@ -1764,19 +1550,17 @@ sub generate_mpsoc{ @files = File::Find::Rule->file() ->name( '*.v','*.V') ->in( "$dir2" ); - copy_file_and_folders (\@files,$project_dir,"$hw_dir/lib/"); } - - + # Write object file generate_mpsoc_lib_file($mpsoc,$info); - + # Write verilog file open(FILE, ">$target_dir/src_verilog/$name.sv") || die "Can not open: $!"; print FILE $file_v; close(FILE) || die "Error closing file: $!"; - + my $l=autogen_warning().get_license_header("${name}_top.v"); open(FILE, ">$target_dir/src_verilog/${name}_top.v") || die "Can not open: $!"; print FILE "$l\n$top_v"; @@ -1784,16 +1568,10 @@ sub generate_mpsoc{ gen_noc_localparam_v_file($mpsoc,"$target_dir/src_verilog/lib/src_noc"); - - - - - - # $l=autogen_warning().get_license_header("${name}_mp.v"); - # open(FILE, ">$target_dir/src_verilog/${name}_mp.v") || die "Can not open: $!"; - # print FILE "$l\n$mp_v"; - # close(FILE) || die "Error closing file: $!"; - + # $l=autogen_warning().get_license_header("${name}_mp.v"); + # open(FILE, ">$target_dir/src_verilog/${name}_mp.v") || die "Can not open: $!"; + # print FILE "$l\n$mp_v"; + # close(FILE) || die "Error closing file: $!"; #generate makefile open(FILE, ">$sw_dir/Makefile") || die "Can not open: $!"; @@ -1806,7 +1584,7 @@ sub generate_mpsoc{ open(FILE, ">$sw_dir/program.sh") || die "Can not open: $!"; print FILE mpsoc_mem_prog($m_chain); close(FILE) || die "Error closing file: $!"; - + my @ff= ("$target_dir/src_verilog/$name.sv","$target_dir/src_verilog/${name}_top.v"); add_to_project_file_list(\@ff,"$hw_dir/lib/",$hw_dir); @@ -1818,14 +1596,13 @@ sub generate_mpsoc{ #regenerate linker var file create_linker_var_file($mpsoc); - - + message_dialog("MPSoC \"$name\" has been created successfully at $target_dir/ " ) if($show_sucess_msg); return 1; -} +} sub mpsoc_sw_make { - my $make="TOPTARGETS := all clean + my $make="TOPTARGETS := all clean SUBDIRS := \$(wildcard */.) \$(TOPTARGETS): \$(SUBDIRS) \$(SUBDIRS): @@ -1839,9 +1616,7 @@ sub mpsoc_sw_make { sub mpsoc_mem_prog { my $chain=shift; - - my $string="#!/bin/bash - + my $string="#!/bin/bash #JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/JTAG_INTFC\" source ./jtag_intfc.sh @@ -1871,7 +1646,7 @@ sub mpsoc_mem_prog { bash write_memory.sh cd .. done - + #Enable the cpu \$JTAG_INTFC -t $chain -n 127 -d \"I:1,D:2:0,I:0\" # I:1 set jtag_enable in active mode @@ -1927,9 +1702,8 @@ sub get_tile{ } $button->signal_connect("clicked" => sub{ - get_tile_setting ($mpsoc,$tile); - }); - + get_tile_setting ($mpsoc,$tile); + }); #$button->show_all; return $button; } @@ -1940,26 +1714,21 @@ sub define_empty_param_setting { my $okbox=def_hbox(TRUE,0); $okbox->pack_start($ok, FALSE, FALSE,0); $ok-> signal_connect("clicked" => sub{ - set_gui_status($mpsoc,"refresh_soc",1); - $window->destroy; - - }); - my $param_table = def_table(1, 1, TRUE); - $param_table->attach_defaults($okbox,0,1,3,4); - return $param_table; - - + set_gui_status($mpsoc,"refresh_soc",1); + $window->destroy; + }); + my $param_table = def_table(1, 1, TRUE); + $param_table->attach_defaults($okbox,0,1,3,4); + return $param_table; } sub get_tile_setting { my($mpsoc,$tile)=@_; my $window = def_popwin_size(50,40,"Parameter setting for Tile $tile ",'percent'); my $table = def_table(6, 2, FALSE); - my $scrolled_win = add_widget_to_scrolled_win($table); my $row=0; my ($soc_name,$g,$t)=$mpsoc->mpsoc_get_tile_soc_name($tile); - my @socs=$mpsoc->mpsoc_get_soc_list(); my @list=(' ',@socs); my $pos=(defined $soc_name)? get_scolar_pos($soc_name,@list): 0; @@ -1969,13 +1738,11 @@ sub get_tile_setting { $table->attach($combo,2,3,$row,$row+1,'shrink','shrink',2,2);$row++; add_Hsep_to_table($table,0,3,$row);$row++; $soc_name = ' ' if (!defined $soc_name); - my $param_table = ($soc_name eq ' ')? define_empty_param_setting($mpsoc,$window) : - get_soc_parameter_setting_table($mpsoc,$soc_name,$window,[$tile]); - - $table->attach_defaults($param_table,0,3,2,3); - - - $combo->signal_connect('changed'=>sub{ + my $param_table = ($soc_name eq ' ')? + define_empty_param_setting($mpsoc,$window) : + get_soc_parameter_setting_table($mpsoc,$soc_name,$window,[$tile]); + $table->attach_defaults($param_table,0,3,2,3); + $combo->signal_connect('changed'=>sub{ my $new_soc=$combo->get_active_text(); if ($new_soc eq ' '){ #unconnect tile @@ -1996,7 +1763,6 @@ sub get_tile_setting { $window->show_all; } - ########## # gen_tiles ######### @@ -2005,15 +1771,14 @@ sub gen_tiles{ my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc); my $table; my $dim_y = floor(sqrt($NE)); - $table=def_table($NE%8,$NE/8,FALSE);# my ($row,$col,$homogeneous)=@_; - for (my $i=0; $i<$NE;$i++){ - my $tile=get_tile($mpsoc,$i); - my $y= int($i/$dim_y); - my $x= $i % $dim_y; + $table=def_table($NE%8,$NE/8,FALSE);# my ($row,$col,$homogeneous)=@_; + for (my $i=0; $i<$NE;$i++){ + my $tile=get_tile($mpsoc,$i); + my $y= int($i/$dim_y); + my $x= $i % $dim_y; $table->attach_defaults ($tile, $x, $x+1 , $y, $y+1); - } - - my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_tiles_adj'); + } + my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_tiles_adj'); add_widget_to_scrolled_win($table,$scrolled_win); return $scrolled_win; } @@ -2024,22 +1789,20 @@ sub get_elf_file_addr_range { #my $command= "size -A $file"; my $command= "nm $file"; #add_info($tview,"$command\n"); - my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command); + my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command); if(length $stderr>1){ add_colored_info($tview,"$stderr\n",'red'); add_colored_info($tview,"$command was not run successfully!\n",'red'); return ("Err","Err"); - } + } if($exit){ add_colored_info($tview,"$stdout\n",'red'); add_colored_info($tview,"$command was not run successfully!\n",'red'); return ("Err","Err"); } - my @lines = split ("\n" ,$stdout); my $max_addr=0; my $sec_name; - foreach my $p (@lines ){ $p =~ s/\s+/ /g; # remove extra spaces $p =~ s/^\s+//; #ltrim @@ -2062,7 +1825,7 @@ sub show_reqired_brams{ my $table= def_table(10,10,FALSE); add_widget_to_scrolled_win($table,$sc_win); my $row=0; - my $col=0; + my $col=0; my @clmns =('Tile#', 'Section located in Upper Bound Address (UBA) ','UBA in Bytes','UBA in Words','Minimum Memory Address Width'); my $target_dir; @@ -2070,11 +1833,8 @@ sub show_reqired_brams{ my $mpsoc_name=$self->object_get_attribute('mpsoc_name'); if(defined $mpsoc_name){#it is an soc - my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self); - $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; - for (my $tile_num=0;$tile_num<$NE;$tile_num++){ my $ram_file = "$target_dir/sw/tile$tile_num/image"; my ($size,$sec) = get_elf_file_addr_range($ram_file,$tview); @@ -2086,8 +1846,7 @@ sub show_reqired_brams{ $clmn{3}="$w"; $clmn{4}=ceil(log($w)/log(2)); push(@data,\%clmn); - - }#$tile_num + }#$tile_num } else { @@ -2105,27 +1864,26 @@ sub show_reqired_brams{ push(@data,\%clmn); } - my @clmn_type = (#'Glib::Boolean', # => G_TYPE_BOOLEAN - #'Glib::Uint', # => G_TYPE_UINT - 'Glib::String', # => G_TYPE_STRING - 'Glib::String', - 'Glib::String', - 'Glib::String', - 'Glib::String'); # you get the idea + my @clmn_type = ( + #'Glib::Boolean', # => G_TYPE_BOOLEAN + #'Glib::Uint', # => G_TYPE_UINT + 'Glib::String', # => G_TYPE_STRING + 'Glib::String', + 'Glib::String', + 'Glib::String', + 'Glib::String' + ); my $list= gen_list_store (\@data,\@clmn_type,\@clmns); $table-> attach ($list, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $row++; - $win->add($sc_win); $win->show_all(); } sub check_conflict { my ($self,$tile_num,$label)=@_; - my $r1 =$self->object_get_attribute("ROM$tile_num",'end'); my $r2 =$self->object_get_attribute("RAM$tile_num",'start'); - if(defined $r1 && defined $r2){ if(hex($r1)> hex($r2)){ $label->set_markup("RAM-ROM range Conflict"); @@ -2145,7 +1903,6 @@ sub update_ram_rom_size { my ($self,$tile_num,$name,$label,$start,$end,$conflict)=@_; my $s = $start->get_value(); my $e = $end->get_value(); - $self->object_add_attribute($name.$tile_num,'start',$start->get_value()); $self->object_add_attribute($name.$tile_num,'end',$end->get_value()); if($e <= $s){ @@ -2154,13 +1911,8 @@ sub update_ram_rom_size { }else { $label->set_label( metric_conversion($e - $s) . "B"); - } - check_conflict($self,$tile_num,$conflict); - - - } sub get_tile_peripheral_patameter { @@ -2184,8 +1936,7 @@ sub get_tile_peripheral_patameter { } } } - return undef; - + return undef; } sub get_soc_peripheral_parameter { @@ -2199,7 +1950,6 @@ sub get_soc_peripheral_parameter { return undef; } - sub linker_initial_setting { my ($self,$tview)=@_; my $mpsoc_name=$self->object_get_attribute('mpsoc_name'); @@ -2208,32 +1958,23 @@ sub linker_initial_setting { if(defined $mpsoc_name){#it is an mpsoc my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self); - $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; for (my $tile_num=0;$tile_num<$NE;$tile_num++){ - my $v=get_tile_peripheral_patameter($self,$tile_num,"_ram","Aw"); $v = 13 if (!defined $v); $self->object_add_attribute('MEM'.$tile_num,'width',$v); $self->object_add_attribute('MEM'.$tile_num,'percent',75); - my $s =(1 << ($v+2)) ; my $p = 75; - my $rom_start = 0; my $rom_end= int ( ($s*$p)/100); my $ram_start= int (($s*$p)/100); my $ram_end= $s; - $self->object_add_attribute('ROM'.$tile_num,'start',$rom_start); $self->object_add_attribute('ROM'.$tile_num,'end',$rom_end); $self->object_add_attribute('RAM'.$tile_num,'start',$ram_start); $self->object_add_attribute('RAM'.$tile_num,'end',$ram_end); - - } - - } else { @@ -2243,66 +1984,47 @@ sub linker_initial_setting { $self->object_add_attribute('MEM0','percent',75); my $s =(1 << ($v+2)) ; my $p = 75; - my $rom_start = 0; my $rom_end= int ( ($s*$p)/100); my $ram_start= int (($s*$p)/100); my $ram_end= $s; - $self->object_add_attribute('ROM0','start',$rom_start); $self->object_add_attribute('ROM0','end',$rom_end); $self->object_add_attribute('RAM0','start',$ram_start); $self->object_add_attribute('RAM0','end',$ram_end); } - - } - - sub linker_setting{ my ($self,$tview)=@_; my $win=def_popwin_size (80,50,"BRAM info", 'percent'); my $sc_win = gen_scr_win_with_adjst($self,'liststore'); my $table= def_table(10,10,FALSE); - - my $row=0; my $col=0; - $table-> attach (gen_label_in_center("Tile"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col+=1; $table-> attach (gen_label_in_center("Memory Addr"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col+=1; $table-> attach (gen_label_in_center("ROM/(ROM+RAM)"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col+=1; - $table-> attach (gen_label_in_center("ROM index addr (hex)"), $col, $col+2, $row, $row+1,'shrink','shrink',2,2); $col+=3; $table-> attach (gen_label_in_center("RAM index addr (hex)"), $col, $col+2, $row, $row+1,'shrink','shrink',2,2); $col+=3; - - $col=0;$row++; $table-> attach (gen_label_in_center("#"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; $table-> attach (gen_label_in_center("Width"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; $table-> attach (gen_label_in_center("(%)"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - $table-> attach (gen_label_in_center("Beginning"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col+=1; $table-> attach (gen_label_in_center("End"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; $table-> attach (gen_label_in_center("Size"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - $table-> attach (gen_label_in_center("Beginning"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col+=1; $table-> attach (gen_label_in_center("End"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; $table-> attach (gen_label_in_center("Size"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - $col=0;$row++; - my $target_dir; my @data; - my $mpsoc_name=$self->object_get_attribute('mpsoc_name'); my $tnum; if(defined $mpsoc_name){#it is an mpsoc - my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self); - $tnum=$NE; + $tnum=$NE; $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; } else @@ -2311,121 +2033,82 @@ sub linker_setting{ $target_dir = "$ENV{'PRONOC_WORK'}/SOC/$soc_name"; $tnum=1; } - for (my $j=0;$j<$tnum;$j++){ - my $tile_num=$j; - my $conflict =gen_label_in_center(" ") ; - - $table-> attach (gen_label_in_center("$tile_num"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2);$col++; - my $ram_width = gen_spin(2,64,1); - my $width = $self->object_get_attribute('MEM'.$tile_num,'width'); - if(!defined $width){ - linker_initial_setting ($self,$tview); - $width = $self->object_get_attribute('MEM'.$tile_num,'width'); - } - $ram_width->set_value($width); - my $size =gen_label_in_center(metric_conversion(1 << 15). "B") ; - - - $table-> attach (def_pack_hbox('FALSE',0,$ram_width,$size), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - - - - my $percent = gen_spin_float(6.25,93.75,6.25,2); - my $p=$self->object_get_attribute('MEM'.$tile_num,'percent'); - $percent->set_value($p); - - my $enter= def_image_button("icons/enter.png"); - $table-> attach (def_pack_hbox('FALSE',0,$percent,$enter), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - my $rom_start_v =$self->object_get_attribute('ROM'.$tile_num,'start'); - my $rom_end_v = $self->object_get_attribute('ROM'.$tile_num,'end'); - my $ram_start_v = $self->object_get_attribute('RAM'.$tile_num,'start'); - my $ram_end_v = $self->object_get_attribute('RAM'.$tile_num,'end'); - - - - my $rom_start = HexSpin->new ( $rom_start_v, 0, 0xffffffff ,4); - $rom_start->set_digits(8); - $table-> attach ($rom_start, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - - - my $rom_end = HexSpin->new ( $rom_end_v, 0, 0xffffffff ,4); - $rom_end->set_digits(8); - $table-> attach ($rom_end, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - my $rom_size =gen_label_in_center(" ") ; - $table-> attach ($rom_size, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + for (my $j=0;$j<$tnum;$j++){ + my $tile_num=$j; + my $conflict =gen_label_in_center(" ") ; + $table-> attach (gen_label_in_center("$tile_num"), $col, $col+1, $row, $row+1,'shrink','shrink',2,2);$col++; + my $ram_width = gen_spin(2,64,1); + my $width = $self->object_get_attribute('MEM'.$tile_num,'width'); + if(!defined $width){ + linker_initial_setting ($self,$tview); + $width = $self->object_get_attribute('MEM'.$tile_num,'width'); + } + $ram_width->set_value($width); + my $size =gen_label_in_center(metric_conversion(1 << 15). "B") ; + $table-> attach (def_pack_hbox('FALSE',0,$ram_width,$size), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + my $percent = gen_spin_float(6.25,93.75,6.25,2); + my $p=$self->object_get_attribute('MEM'.$tile_num,'percent'); + $percent->set_value($p); + my $enter= def_image_button("icons/enter.png"); + $table-> attach (def_pack_hbox('FALSE',0,$percent,$enter), $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + my $rom_start_v =$self->object_get_attribute('ROM'.$tile_num,'start'); + my $rom_end_v = $self->object_get_attribute('ROM'.$tile_num,'end'); + my $ram_start_v = $self->object_get_attribute('RAM'.$tile_num,'start'); + my $ram_end_v = $self->object_get_attribute('RAM'.$tile_num,'end'); + my $rom_start = HexSpin->new ( $rom_start_v, 0, 0xffffffff ,4); + $rom_start->set_digits(8); + $table-> attach ($rom_start, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + my $rom_end = HexSpin->new ( $rom_end_v, 0, 0xffffffff ,4); + $rom_end->set_digits(8); + $table-> attach ($rom_end, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + my $rom_size =gen_label_in_center(" ") ; + $table-> attach ($rom_size, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict); + $rom_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);}); + $rom_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);}); + my $ram_start = HexSpin->new ( $ram_start_v, 0, 0xffffffff ,4); + $ram_start->set_digits(8); + $table-> attach ($ram_start, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + my $ram_end = HexSpin->new ( $ram_end_v, 0, 0xffffffff ,4); + $ram_end->set_digits(8); + $table-> attach ($ram_end, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + my $ram_size =gen_label_in_center(" ") ; + $table-> attach ($ram_size, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict); + $ram_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);}); + $ram_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);}); + $ram_width->signal_connect("value_changed" => sub{ + my $w=$ram_width->get_value(); + $self->object_add_attribute('MEM'.$tile_num,'width',$w); + $size->set_label (metric_conversion(1 << ($w+2)). "B") ; + $size->show_all; + $enter->clicked; + }); + $percent->signal_connect("value_changed" => sub{ + $self->object_add_attribute('MEM'.$tile_num,'percent',$percent->get_value()); + }); + $table-> attach ($conflict, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; + $enter-> signal_connect ( 'clicked' , sub { + my $w=$ram_width->get_value(); + my $s =(1 << ($w+2)); + my $p = $percent->get_value(); + my $rom_start_v = 0; + my $rom_end_v= int ( ($s*$p)/100); + my $ram_start_v= int (($s*$p)/100); + my $ram_end_v= $s; + $rom_start->set_value($rom_start_v); + $rom_end->set_value($rom_end_v); + $ram_start->set_value($ram_start_v); + $ram_end->set_value($ram_end_v); update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict); - $rom_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);}); - $rom_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);}); - - my $ram_start = HexSpin->new ( $ram_start_v, 0, 0xffffffff ,4); - $ram_start->set_digits(8); - $table-> attach ($ram_start, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - - my $ram_end = HexSpin->new ( $ram_end_v, 0, 0xffffffff ,4); - $ram_end->set_digits(8); - $table-> attach ($ram_end, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - my $ram_size =gen_label_in_center(" ") ; - $table-> attach ($ram_size, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - - - update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict); - - $ram_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);}); - $ram_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);}); - - $ram_width->signal_connect("value_changed" => sub{ - my $w=$ram_width->get_value(); - $self->object_add_attribute('MEM'.$tile_num,'width',$w); - $size->set_label (metric_conversion(1 << ($w+2)). "B") ; - $size->show_all; - $enter->clicked; - }); - $percent->signal_connect("value_changed" => sub{ - $self->object_add_attribute('MEM'.$tile_num,'percent',$percent->get_value()); - }); - - $table-> attach ($conflict, $col, $col+1, $row, $row+1,'shrink','shrink',2,2); $col++; - - - - - $enter-> signal_connect ( 'clicked' , sub { - my $w=$ram_width->get_value(); - my $s =(1 << ($w+2)); - my $p = $percent->get_value(); - - my $rom_start_v = 0; - my $rom_end_v= int ( ($s*$p)/100); - my $ram_start_v= int (($s*$p)/100); - my $ram_end_v= $s; - - $rom_start->set_value($rom_start_v); - $rom_end->set_value($rom_end_v); - $ram_start->set_value($ram_start_v); - $ram_end->set_value($ram_end_v); - update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict); - update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict); - - }); - - $col=0; $row++; - + }); + $col=0; $row++; }#$tile_num - my $main_table=def_table(10,10,FALSE); - my $ok = def_image_button('icons/select.png','OK'); $main_table->attach_defaults ($table , 0, 12, 0,11); $main_table->attach ($ok,5, 6, 11,12,'shrink','shrink',0,0); - $ok->signal_connect('clicked', sub { for (my $t=0;$t<$tnum;$t++){ my $r0 =$self->object_get_attribute("ROM$t",'start'); @@ -2433,31 +2116,20 @@ sub linker_setting{ my $r2 =$self->object_get_attribute("RAM$t",'start'); my $r3 =$self->object_get_attribute("RAM$t",'end'); if(hex($r1) hex($r2) ){ - message_dialog("Please fix tile $t conflict range !"); - return ; - + message_dialog("Please fix tile $t conflict range !"); + return ; } - - - } create_linker_var_file($self); $win->destroy(); - - }); - - add_widget_to_scrolled_win($main_table,$sc_win); $win->add($sc_win); $win->show_all(); - } @@ -2473,20 +2145,17 @@ sub create_linker_var_file{ if(defined $mpsoc_name){#it is an mpsoc my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self); - $tnum=$NE; + $tnum=$NE; } else { - $tnum=1; } - for (my $t=0;$t<$tnum;$t++){ my $r0 =$self->object_get_attribute("ROM$t",'start'); my $r1 =$self->object_get_attribute("ROM$t",'end'); my $r2 =$self->object_get_attribute("RAM$t",'start'); my $r3 =$self->object_get_attribute("RAM$t",'end'); - my $file=sprintf(" MEMORY @@ -2539,9 +2208,7 @@ sub software_edit_mpsoc { $ram -> signal_connect("clicked" => sub{ show_reqired_brams($self,$tview); }); - - my $load; - + my $load; $make -> signal_connect("clicked" => sub{ $load->destroy if(defined $load); $load= show_gif("icons/load.gif"); @@ -2556,27 +2223,23 @@ sub software_edit_mpsoc { $load->show_all; return; }; - unless (run_make_file($sw,$tview)){ - $load->destroy; - $load=def_icon("icons/cancel.png"); - $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); - $load->show_all; - return; - } + unless (run_make_file($sw,$tview)){ + $load->destroy; + $load=def_icon("icons/cancel.png"); + $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); + $load->show_all; + return; + } $load->destroy; $load=def_icon("icons/button_ok.png"); $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); $load->show_all; - - }); - #Programe the board $prog-> signal_connect("clicked" => sub{ my $error = 0; my $bash_file="$sw/program.sh"; my $jtag_intfc="$sw/jtag_intfc.sh"; - add_info($tview,"Program the board using quartus_pgm and $bash_file file\n"); #check if the programming file exists unless (-f $bash_file) { @@ -2588,7 +2251,6 @@ sub software_edit_mpsoc { add_colored_info($tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red'); $error=1; } - return if($error); my $command = "cd $sw; bash program.sh"; add_info($tview,"$command\n"); @@ -2597,32 +2259,22 @@ sub software_edit_mpsoc { add_colored_info($tview,"$stderr\n",'red'); add_colored_info($tview,"Memory was not programmed successfully!\n",'red'); }else { - if($exit){ add_colored_info($tview,"$stdout\n",'red'); add_colored_info($tview,"Memory was not programmed successfully!\n",'red'); }else{ add_info($tview,"$stdout\n"); add_colored_info($tview,"Memory is programmed successfully!\n",'blue'); - } - } }); - - $linker -> signal_connect("clicked" => sub{ linker_setting($self,$tview); }); - } - - - ############# # load_mpsoc ############# - sub load_mpsoc{ my ($mpsoc,$info)=@_; my $file; @@ -2641,13 +2293,10 @@ sub load_mpsoc{ $dialog->destroy; return; } - - clone_obj($mpsoc,$pp); #read save mpsoc socs my @oldsocs=$mpsoc->mpsoc_get_soc_list(); #add existing SoCs and add them to mpsoc - my $error; #print "old: @oldsocs\n new @newsocs \n"; foreach my $p (@oldsocs) { @@ -2655,67 +2304,50 @@ sub load_mpsoc{ my @num= $mpsoc->mpsoc_get_soc_tiles_num($p); if (scalar @num && ( grep (/^$p$/,@newsocs)==0)){ my $m="Processing tile $p that has been used for ties @num but is not located in library anymore\n"; - $error = (defined $error ) ? "$error $m" : $m; + $error = (defined $error ) ? "$error $m" : $m; } $mpsoc->mpsoc_remove_soc ($p) if (grep (/^$p$/,@newsocs)==0); - - } @newsocs=get_soc_list($mpsoc,$info); # add all existing socs add_info($info,"**Error: \n $error\n") if(defined $error); - set_gui_status($mpsoc,"load_file",0); - - } - } - $dialog->destroy; + } + } + $dialog->destroy; } ####### # CLK setting ####### - sub clk_setting_win1{ my ($self,$info,$type)=@_; - my $window = def_popwin_size(80,80,"CLK setting",'percent'); - my $next=def_image_button('icons/right.png','Next'); my $mtable = def_table(10, 1, FALSE); #get the list of all tiles clk sources - my @sources=('clk','reset'); - my $table = def_table(10, 7, FALSE); my $notebook = gen_notebook(); $notebook->set_scrollable(TRUE); #$notebook->can_focus(FALSE); $notebook->set_tab_pos ('left'); - - - my($row,$column)=(0,0); - my %all = ($type eq 'mpsoc') ? get_all_tiles_clk_sources_list($self): get_soc_clk_source_list($self) ; foreach my $s (@sources){ - my $spin; - ($row,$column,$spin)= add_param_widget($self,"$s number","${s}_number", 1,'Spin-button',"1,1024,1","Define total number of ${s} input ports mpsoc", $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal'); - - my $w=get_source_assignment_win($self,$s,$all{$s},$type); - my $box=def_hbox(FALSE,0); - $box->pack_start($w, TRUE, TRUE, 0); - $notebook->append_page ($box,gen_label_in_center ($s)); - $spin->signal_connect("value_changed" => sub{ - $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",1); - $w->destroy; - $w=get_source_assignment_win($self,$s,$all{$s},$type); - $box->pack_start($w, TRUE, TRUE, 0); - $box->show_all; - + my $spin; + ($row,$column,$spin)= add_param_widget($self,"$s number","${s}_number", 1,'Spin-button',"1,1024,1","Define total number of ${s} input ports mpsoc", $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal'); + my $w=get_source_assignment_win($self,$s,$all{$s},$type); + my $box=def_hbox(FALSE,0); + $box->pack_start($w, TRUE, TRUE, 0); + $notebook->append_page ($box,gen_label_in_center ($s)); + $spin->signal_connect("value_changed" => sub{ + $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",1); + $w->destroy; + $w=get_source_assignment_win($self,$s,$all{$s},$type); + $box->pack_start($w, TRUE, TRUE, 0); + $box->show_all; }); - } - $mtable->attach_defaults($table,0,1,0,1); $mtable->attach_defaults( $notebook,0,1,1,20); $mtable->attach($next,0,1,20,21,'expand','fill',2,2); @@ -2724,9 +2356,7 @@ sub clk_setting_win1{ $next-> signal_connect("clicked" => sub{ clk_setting_win2($self,$info,$type); $window->destroy; - }); - } @@ -2767,10 +2397,8 @@ sub get_source_assignment_win{ my $enter= def_image_button("icons/enter.png"); my $box=def_hbox(FALSE,0); $box->pack_start( $enter, FALSE, FALSE, 0); - ($row,$column,$entry)= add_param_widget($mpsoc,"$n-","${s}_${n}_name", "${s}$n",'Entry',undef,undef, $table1,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal'); $table1->attach ($box,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column++; - $enter->signal_connect ("clicked" => sub{ $mpsoc->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",1); $win2->destroy; @@ -2778,24 +2406,18 @@ sub get_source_assignment_win{ $v2-> pack2($win2, TRUE, TRUE); $v2->show_all; }); - - if($s eq 'clk'){ ($column,$row)=get_clk_constrain_widget($mpsoc,$table1,$column,$row, $s,$n); } - - - - # if((($n+1) % 4)==0){ - $column=0; - $row++; - #} - } - - #source assigmnmet + # if((($n+1) % 4)==0){ + $column=0; + $row++; + #} + } + #source assigmnmet $win2= get_source_assignment_win2($mpsoc,$s,$ports_ref,$type); - $v2=gen_vpaned($win1,.2,$win2); - return $v2; + $v2=gen_vpaned($win1,.2,$win2); + return $v2; } @@ -2820,11 +2442,11 @@ sub get_clk_constrain_widget { $table->attach ($f_lab,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=1; update_wave_form($period,$rise,$fall,$r_lab,$f_lab); $frequency-> signal_connect("value_changed" => sub{ - my $fr =$frequency->get_value(); + my $fr =$frequency->get_value(); my $p = 1000/$fr; - $period->set_value($p); - update_wave_form($period,$rise,$fall,$r_lab,$f_lab); - }); + $period->set_value($p); + update_wave_form($period,$rise,$fall,$r_lab,$f_lab); + }); $period-> signal_connect("value_changed" => sub{ my $p =$period->get_value(); my $fr = 1000/$p; @@ -2832,27 +2454,25 @@ sub get_clk_constrain_widget { update_wave_form($period,$rise,$fall,$r_lab,$f_lab); }); $rise-> signal_connect("value_changed" => sub{ - update_wave_form($period,$rise,$fall,$r_lab,$f_lab); + update_wave_form($period,$rise,$fall,$r_lab,$f_lab); }); $fall-> signal_connect("value_changed" => sub{ - update_wave_form($period,$rise,$fall,$r_lab,$f_lab); - }); + update_wave_form($period,$rise,$fall,$r_lab,$f_lab); + }); return ($column,$row); } - sub get_source_assignment_win2{ my ($mpsoc,$s,$ports_ref,$type)=@_; my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number"); my $table2 = def_table(10, 7, FALSE); - my $win2=add_widget_to_scrolled_win($table2); - my %ports = %{$ports_ref} if(defined $ports_ref); - + my $win2=add_widget_to_scrolled_win($table2); + my %ports = %{$ports_ref} if(defined $ports_ref); my $contents; for(my $n=0;$n<$num; $n++ ){ - my $m=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_${n}_name"); - $contents=(defined $contents)? "$contents,$m":$m; + my $m=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_${n}_name"); + $contents=(defined $contents)? "$contents,$m":$m; } my $default=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_0_name"); my $n=0; @@ -2861,18 +2481,16 @@ sub get_source_assignment_win2{ add_param_widget($mpsoc," NoC $s","NoC_${s}", $default,'Combo-box',$contents,undef, $table2,$row,$column,1,'SOURCE_SET_CONNECT',undef,undef,'horizontal'); ($row,$column)=(1,0); } - foreach my $p (sort keys %ports){ - my @array=@{$ports{$p}}; - foreach my $q (@array){ - my $param="${p}_$q"; - my $label=" ${p}_$q"; - ($row,$column)= add_param_widget($mpsoc,$label,$param, $default,'Combo-box',$contents,undef, $table2,$row,$column,1,'SOURCE_SET_CONNECT',undef,undef,'horizontal'); - if((($n+1) % 4)==0){$column=0;$row++;}$n++; - } + my @array=@{$ports{$p}}; + foreach my $q (@array){ + my $param="${p}_$q"; + my $label=" ${p}_$q"; + ($row,$column)= add_param_widget($mpsoc,$label,$param, $default,'Combo-box',$contents,undef, $table2,$row,$column,1,'SOURCE_SET_CONNECT',undef,undef,'horizontal'); + if((($n+1) % 4)==0){$column=0;$row++;}$n++; + } } return $win2; - } @@ -2885,9 +2503,7 @@ sub get_all_tiles_clk_sources_list{ next if(!defined $soc_name); my $top=$mpsoc->mpsoc_get_soc($soc_name); my @intfcs=$top->top_get_intfc_list(); - my @sources=('clk','reset'); - foreach my $intfc (@intfcs){ my($type,$name,$num)= split("[:\[ \\]]", $intfc); foreach my $s (@sources){ @@ -2896,17 +2512,13 @@ sub get_all_tiles_clk_sources_list{ $all_sources{$s}{"T$tile_num"}=\@ports; } } - } } - return %all_sources; + return %all_sources; } - - sub clk_setting_win2{ my ($self,$info,$type)=@_; - my $window = def_popwin_size(70,70,"CLK setting",'percent'); my $table = def_table(10, 7, FALSE); my $scrolled_win=add_widget_to_scrolled_win($table); @@ -2916,79 +2528,61 @@ sub clk_setting_win2{ my $ip = ip->lib_new (); #print "get_top_ip(\$self,$type);\n"; my $mpsoc_ip=get_top_ip($self,$type); - $ip->add_ip($mpsoc_ip); my $soc =get_source_set_top($self,$type); my $infc = interface->interface_new(); - - set_gui_status($soc,"ideal",0); # A tree view for holding a library my %tree_text; my @categories= ('Source'); foreach my $p (@categories) { - my @modules= $ip->get_modules($p); - $tree_text{$p}=\@modules; + my @modules= $ip->get_modules($p); + $tree_text{$p}=\@modules; } - my $tree_box = create_tree ($soc,'IP list', $info,\%tree_text,\&tmp,\&add_module_to_mpsoc); my $device_win=show_active_dev($soc,$ip,$infc,$info); my $h1=gen_hpaned($tree_box,.15,$device_win); $table->attach_defaults ($h1,0, 10, 0, 10); - my $event =Event->timer (after => 1, interval => 1, cb => sub { - -my ($state,$timeout)= get_gui_status($soc); - - - if ($timeout>0){ - $timeout--; - set_gui_status($soc,$state,$timeout); + my ($state,$timeout)= get_gui_status($soc); + if ($timeout>0){ + $timeout--; + set_gui_status($soc,$state,$timeout); + } + elsif( $state ne "ideal" ){ + #check if top is removed add it + my @instances=$soc->soc_get_all_instances(); + my $redefine =1; + foreach my $inst (@instances){ + $redefine = 0 if ($inst eq 'TOP'); } - elsif( $state ne "ideal" ){ - - #check if top is removed add it - my @instances=$soc->soc_get_all_instances(); - my $redefine =1; - foreach my $inst (@instances){ - $redefine = 0 if ($inst eq 'TOP'); - } - if($redefine == 1){ - my $ip = ip->lib_new (); - #print "get_top_ip(\$self,$type);\n"; - my $mpsoc_ip=get_top_ip($self,$type); - - $ip->add_ip($mpsoc_ip); - $soc ->object_add_attribute('SOURCE_SET',"IP",$mpsoc_ip); - $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",0); - add_mpsoc_to_device($soc,$ip); - $self->object_add_attribute('SOURCE_SET',"SOC",$soc); - } - - $device_win->destroy; - - $device_win=show_active_dev($soc,$ip,$infc,$info); - $h1 -> pack2($device_win, TRUE, TRUE); - $h1 -> show_all; - $table->show_all(); - $device_win->show_all(); - - $self->object_add_attribute('SOURCE_SET',"SOC",$soc); - set_gui_status($soc,"ideal",0); - - } - return TRUE; - - - }); - - my $mtable = def_table(10, 5, FALSE); + if($redefine == 1){ + my $ip = ip->lib_new (); + #print "get_top_ip(\$self,$type);\n"; + my $mpsoc_ip=get_top_ip($self,$type); + $ip->add_ip($mpsoc_ip); + $soc ->object_add_attribute('SOURCE_SET',"IP",$mpsoc_ip); + $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",0); + add_mpsoc_to_device($soc,$ip); + $self->object_add_attribute('SOURCE_SET',"SOC",$soc); + } + $device_win->destroy; + $device_win=show_active_dev($soc,$ip,$infc,$info); + $h1 -> pack2($device_win, TRUE, TRUE); + $h1 -> show_all; + $table->show_all(); + $device_win->show_all(); + $self->object_add_attribute('SOURCE_SET',"SOC",$soc); + set_gui_status($soc,"ideal",0); + } + return TRUE; + }); + my $mtable = def_table(10, 5, FALSE); $mtable->attach_defaults($scrolled_win,0,5,0,9); $mtable->attach($back,0,1,9,10,'expand','fill',2,2) if($type ne 'soc'); $mtable->attach($diagram,2,4,9,10,'expand','fill',2,2); $mtable->attach($ok,4,5,9,10,'expand','fill',2,2); - $window->add ($mtable); $window->show_all(); $self->object_add_attribute('SOURCE_SET',"SOC",$soc); @@ -2996,9 +2590,8 @@ sub clk_setting_win2{ $self->object_add_attribute('SOURCE_SET',"SOC",$soc); clk_setting_win1($self,$info,$type); $window->destroy; - $event->cancel; - }); - + $event->cancel; + }); $diagram-> signal_connect("clicked" => sub{ show_tile_diagram ($soc); }); @@ -3007,13 +2600,7 @@ sub clk_setting_win2{ set_gui_status($self,"ref",1); $window->destroy; $event->cancel; - }); - - - - - - + }); } sub tmp{ @@ -3023,12 +2610,9 @@ sub tmp{ sub add_module_to_mpsoc{ my ($soc,$category,$module,$info)=@_; my $ip = ip->lib_new (); - my ($instance_id,$id)= get_instance_id($soc,$category,$module); - - #add module instance + # add module instance my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip); - if($result == 0){ my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist."; show_info($info,$info_text); @@ -3042,7 +2626,6 @@ sub add_module_to_mpsoc{ $soc->object_add_attribute($instance_id,"version",$v); # Read default parameter from lib and add them to soc my %param_default= $ip->get_param_default($category,$module); - my $rr=$soc->soc_add_instance_param($instance_id,\%param_default); if($rr == 0){ my $info_text= "Failed to add default parameter to \"$instance_id\". $instance_id does not exist."; @@ -3051,19 +2634,14 @@ sub add_module_to_mpsoc{ } my @r=$ip->ip_get_param_order($category,$module); $soc->soc_add_instance_param_order($instance_id,\@r); - get_module_parameter($soc,$ip,$instance_id); undef $ip; set_gui_status($soc,"refresh_soc",0); } - - - #$mpsoc,$top_ip,$sw_dir,$soc_name,$id,$soc_num,$txview sub get_top_ip{ my ($self,$type)=@_; - my $mpsoc_ip=ip_gen->ip_gen_new(); $mpsoc_ip->ipgen_add("module_name",'TOP'); $mpsoc_ip->ipgen_add("ip_name",'TOP'); @@ -3076,11 +2654,9 @@ sub get_top_ip{ $num=1 if(!defined $num); $mpsoc_ip->ipgen_add_plug("$s",'num',$num); for (my $n=0; $n<$num; $n++ ){ - my $name=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_name"); $mpsoc_ip->ipgen_set_plug_name($s,$n,$name); $mpsoc_ip->ipgen_add_port($name,undef,'input',"plug:${s}\[$n\]","${s}_i"); - } } # add_mpsoc_ip_other_interfaces($mpsoc,$mpsoc_ip); @@ -3099,44 +2675,33 @@ sub get_top_ip{ } } } - return $mpsoc_ip; + return $mpsoc_ip; } sub add_mpsoc_ip_other_interfaces{ my ($mpsoc,$mpsoc_ip)=@_; -my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); + my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); my $processors_en=0; my %intfc_num; my @parameters_order; for (my $tile_num=0;$tile_num<$NE;$tile_num++){ my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num); - - my $top=$mpsoc->mpsoc_get_soc($soc_name); my @nis=get_NI_instance_list($top); my @noc_param=$top->top_get_parameter_list($nis[0]); my $inst_name=$top->top_get_def_of_instance($nis[0],'instance'); - #other parameters my %params=$top->top_get_default_soc_param(); - my @intfcs=$top->top_get_intfc_list(); - my $i=0; - my $dir = Cwd::getcwd(); my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name'); my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; my $soc_file="$target_dir/src_verilog/tiles/$soc_name.sv"; - my $vdb =read_verilog_file($soc_file); - my %soc_localparam = $vdb->get_modules_parameters($soc_name); - - foreach my $intfc (@intfcs){ - # Auto connected/not connected interface if( $intfc eq 'socket:ni[0]' || ($intfc =~ /plug:clk\[/) || ( $intfc =~ /plug:reset\[/)|| ($intfc =~ /socket:RxD_sim\[/ ) || $intfc =~ /plug:enable\[/){ #do nothing @@ -3146,12 +2711,8 @@ sub add_mpsoc_ip_other_interfaces{ foreach my $p (@ports){ my ($io_port,$type,$new_range,$intfc_name,$intfc_port)= get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam); $mpsoc_ip->ipgen_add_port($io_port,$new_range,$type,'IO','IO'); - - } - } - else { #other interface my($if_type,$if_name,$if_num)= split("[:\[ \\]]", $intfc); @@ -3160,31 +2721,25 @@ sub add_mpsoc_ip_other_interfaces{ $intfc_num{"$if_type:$if_name"}=$num; $mpsoc_ip->ipgen_add_plug("$if_name",'num',$num) if ($if_type eq 'plug'); $mpsoc_ip->ipgen_add_soket("$if_name",'num',$num) if ($if_type eq 'socket'); - my @ports=$top->top_get_intfc_ports_list($intfc); foreach my $p (@ports){ my ($io_port,$type,$new_range,$intfc_name,$intfc_port)= get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam); $mpsoc_ip->ipgen_add_port($io_port,$new_range,$type,"$if_type:$if_name\[$num\]",$intfc_port); - } } } - - my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num); #if ($setting eq 'Custom'){ - %params= $top->top_get_custom_soc_param($tile_num); + %params= $top->top_get_custom_soc_param($tile_num); #}else{ # %params=$top->top_get_default_soc_param(); #} - foreach my $p (sort keys %params){ $params{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$params{$p}); $params{$p}=add_instantc_name_to_parameters(\%soc_localparam,"T$tile_num",$params{$p}); my $pname="T${tile_num}_$p"; $mpsoc_ip-> ipgen_add_parameter ($pname,$params{$p},'Fixed',undef,undef,'Localparam',1); push (@parameters_order,$pname); - } foreach my $p (sort keys %soc_localparam){ $soc_localparam{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$soc_localparam{$p}); @@ -3194,13 +2749,9 @@ sub add_mpsoc_ip_other_interfaces{ push (@parameters_order,$pname); } - - - } #TODO get parameter order $mpsoc_ip->ipgen_add("parameters_order",\@parameters_order); - } sub get_source_set_top{ @@ -3217,7 +2768,6 @@ sub get_source_set_top{ my $ip = ip->lib_new (); #print "get_top_ip(\$self,$type);\n"; my $mpsoc_ip=get_top_ip($self,$type); - $ip->add_ip($mpsoc_ip); $soc ->object_add_attribute('SOURCE_SET',"IP",$mpsoc_ip); $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",0); @@ -3233,14 +2783,10 @@ sub add_mpsoc_to_device{ my $category='TOP'; my $module='TOP'; my ($instance_id,$id) =('TOP',1); - #my ($instance_id,$id)= get_instance_id($soc,$category,$module); - remove_instance_from_soc($soc,$instance_id); - - #add module instanance + # add module instanance my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip); - if($result == 0){ my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist."; # show_info($info,$info_text); @@ -3254,7 +2800,6 @@ sub add_mpsoc_to_device{ $soc->object_add_attribute($instance_id,"version",$v); # Read default parameter from lib and add them to soc my %param_default= $ip->get_param_default($category,$module); - my $rr=$soc->soc_add_instance_param($instance_id,\%param_default); if($rr == 0){ my $info_text= "Failed to add default parameter to \"$instance_id\". $instance_id does not exist."; @@ -3344,7 +2889,7 @@ sub ctrl_box{ }); $clk-> signal_connect("clicked" => sub{ - clk_setting_win1($mpsoc,$info,'mpsoc'); + clk_setting_win1($mpsoc,$info,'mpsoc'); }); return $table; } @@ -3373,7 +2918,7 @@ sub gen_save_load_widget { $entrybox->pack_start( $save, FALSE, FALSE, 0); $entrybox->pack_start( $load, FALSE, FALSE, 0); $entrybox->pack_start( $open_dir , FALSE, FALSE, 0) if (defined $target_dir); - $open_dir-> signal_connect("clicked" => sub{ + $open_dir-> signal_connect("clicked" => sub{ my $name=$self->object_get_attribute($param_name); $name="" if (!defined $name); if (length($name)==0){ diff --git a/mpsoc/perl_gui/lib/perl/network_maker.pl b/mpsoc/perl_gui/lib/perl/network_maker.pl index 8c556a0..cddfe6f 100644 --- a/mpsoc/perl_gui/lib/perl/network_maker.pl +++ b/mpsoc/perl_gui/lib/perl/network_maker.pl @@ -217,7 +217,7 @@ sub generate_custom_topology_dot_file{ graph [layout = twopi, rankdir = RL , splines = true, overlap = false]; node[shape=record]; "; - #Add endpoints + # Add endpoints my @nodes=get_list_of_all_endpoints($self); my $i=0; foreach my $p (@nodes){ @@ -226,7 +226,7 @@ sub generate_custom_topology_dot_file{ $dotfile.= ($gtype eq 'simple')? endp_node_dot_sim($p,$instance) : endp_node_dot_comp($p,$instance); $i++; } - #add routers + # add routers @nodes=get_list_of_all_routers($self); $i=0; foreach my $p (@nodes){ @@ -236,7 +236,7 @@ sub generate_custom_topology_dot_file{ $dotfile.=($gtype eq 'simple')? router_node_dot_sim($pnum,$p,$instance): router_node_dot_comp($pnum,$p,$instance); $i++; } - #add connections + # add connections my @all_nodes=get_list_of_all_nodes($self); my @draw; foreach my $p (@all_nodes){ @@ -2448,4 +2448,4 @@ sub build_network_maker_gui { } ); return $sc_win; } -1; \ No newline at end of file +1; diff --git a/mpsoc/perl_gui/lib/perl/simulator.pl b/mpsoc/perl_gui/lib/perl/simulator.pl index 4142cbe..0549fe5 100755 --- a/mpsoc/perl_gui/lib/perl/simulator.pl +++ b/mpsoc/perl_gui/lib/perl/simulator.pl @@ -445,8 +445,7 @@ sub get_simulator_noc_configuration{ if ($st==0){ $NE=100; }else{ - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample); - my ($NEe, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($NEe, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info($self,$sample); $NE=$NEe; } if ($traffic eq 'custom'){ @@ -749,8 +748,7 @@ sub run_synthetic_simulation { my $dst = $simulate->object_get_attribute($sample,"DST_$i"); $custom.=($i==0)? "-H \"$src,$dst" : ",$src,$dst"; } - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($simulate,$sample); - my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($simulate,$sample); for (my $i=0;$i<$NE; $i++){ my ($src,$dst) = custom_traffic_dest ($simulate,$sample,$i); $custom_sv.="\tassign custom_traffic_t[$src]=$dst;\n"; diff --git a/mpsoc/perl_gui/lib/perl/topology.pl b/mpsoc/perl_gui/lib/perl/topology.pl index 7024415..0ae06f0 100644 --- a/mpsoc/perl_gui/lib/perl/topology.pl +++ b/mpsoc/perl_gui/lib/perl/topology.pl @@ -17,9 +17,10 @@ sub get_topology_info { my $T1=$self->object_get_attribute($noc_param,'T1'); my $T2=$self->object_get_attribute($noc_param,'T2'); my $T3=$self->object_get_attribute($noc_param,'T3'); + my $T4=$self->object_get_attribute($noc_param,'T4'); my $V = $self->object_get_attribute($noc_param,'V'); my $Fpay = $self->object_get_attribute($noc_param,'Fpay'); - return get_topology_info_sub($topology, $T1, $T2, $T3,$V, $Fpay); + return get_topology_info_sub($topology, $T1, $T2, $T3, $T4, $V, $Fpay); } sub get_topology_info_from_parameters { @@ -30,13 +31,14 @@ sub get_topology_info_from_parameters { my $T1 =$param{'T1'}; my $T2 =$param{'T2'}; my $T3 =$param{'T3'}; + my $T4 =$param{'T4'}; my $V =$param{'V'}; - my $Fpay=$param{'Fpay'}; - return get_topology_info_sub($topology, $T1, $T2, $T3,$V, $Fpay); + my $Fpay=$param{'Fpay'}; + return get_topology_info_sub($topology, $T1, $T2, $T3, $T4,$V, $Fpay); } sub get_topology_info_sub { - my ($topology, $T1, $T2, $T3,$V, $Fpay)=@_; + my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay)=@_; my $NE; # Total number of end points (local ports) in the NoC my $NR; # Total number of routers in NoC my $RAw; # Routers address width @@ -89,6 +91,20 @@ sub get_topology_info_sub { $RAw = $Xw + $Yw; $EAw = ($NL==1) ? $RAw : $RAw + $Lw; $MAX_P = 4 + $NL; + }elsif ($topology eq '"MESH_3D"' ) { + my $NX=$T1; + my $NY=$T2; + my $NZ=$T3; + my $NL=$T4; + $NE = $NX*$NY*$NL*$NZ; + $NR = $NX*$NY*$NZ; + my $Xw=log2($NX); + my $Yw=log2($NY); + my $Lw=log2($NL); + my $Zw=log2($NZ); + $RAw = $Xw + $Yw + $Zw; + $EAw = ($NL==1) ? $RAw : $RAw + $Lw; + $MAX_P = 6 + $NL; }elsif ($topology eq '"FMESH"'){ my $NX=$T1; my $NY=$T2; @@ -415,9 +431,10 @@ sub get_noc_verilator_top_modules_info { my $T1=$self->object_get_attribute('noc_param','T1'); my $T2=$self->object_get_attribute('noc_param','T2'); my $T3=$self->object_get_attribute('noc_param','T3'); - my $cast = $self->object_get_attribute('noc_param','MCAST_ENDP_LIST'); - my $CAST_TYPE= $self->object_get_attribute('noc_param','CAST_TYPE'); - my $DAw_OFFSETw = ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"')? $T1 : 0; + my $T4=$self->object_get_attribute('noc_param','T4'); + my $cast = $self->object_get_attribute('noc_param','MCAST_ENDP_LIST'); + my $CAST_TYPE= $self->object_get_attribute('noc_param','CAST_TYPE'); + my $DAw_OFFSETw = ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"' || $topology eq '"MESH_3D"')? $T1 : 0; my %tops; my %nr_p; # number of routers have $p port num my $router_p; #number of routers with different port number in topology @@ -432,8 +449,8 @@ sub get_noc_verilator_top_modules_info { my $custom_include=""; if($topology eq '"FATTREE"') { my $K = $T1; - my $L = $T2; - my $p2 = 2*$K; + my $L = $T2; + my $p2 = 2*$K; $router_p=2; my $NRL= $ne/$K; #number of router in each layer $nr_p{1}=$NRL; @@ -449,8 +466,8 @@ sub get_noc_verilator_top_modules_info { ); }elsif ($topology eq '"TREE"'){ my $K = $T1; - my $L = $T2; - my $p2 = $K+1; + my $L = $T2; + my $p2 = $K+1; $router_p=2;# number of router with different port number $nr_p{1}=1; $nr_p{2}=$nr-1; @@ -484,7 +501,18 @@ sub get_noc_verilator_top_modules_info { "Vrouter1" => "--top-module router_top_v -GP=${ports} ", # "Vnoc" => " --top-module noc_connection", ); - }elsif ($topology eq '"STAR"') { + } elsif ($topology eq '"MESH_3D"') { + $router_p=1; + $nr_p{1}=$nr; + my $ports= 7+$T4-1; + $nr_p{p1}=$ports; + %tops = ( + #"Vrouter1" => "router_top_v_p${ports}.v", + "Vrouter1" => "--top-module router_top_v -GP=${ports} ", + # "Vnoc" => " --top-module noc_connection", + ); + } + elsif ($topology eq '"STAR"') { $router_p=1;# number of router with different port number my $ports= $T1; $nr_p{p1}=$ports; @@ -496,15 +524,15 @@ sub get_noc_verilator_top_modules_info { ); }else {#custom my $dir =get_project_dir()."/mpsoc/rtl/src_topology"; - my $file="$dir/param.obj"; + my $file="$dir/param.obj"; my %param; if(-f $file){ my ($pp,$r,$err) = regen_object($file ); - if ($r){ + if ($r){ print "**Error: cannot open $file file: $err\n"; return; } - %param=%{$pp}; + %param=%{$pp}; }else { print "**Error: cannot find $file \n"; return; @@ -523,8 +551,8 @@ sub get_noc_verilator_top_modules_info { $tops{"Vrouter$i"}= "--top-module router_top_v -GP=${p} ", $i++; - } - $router_p=$i-1; + } + $router_p=$i-1; ${topology_name} =~ s/\"+//g; $custom_include="#define IS_${topology_name}_noc\n"; }#else @@ -709,7 +737,7 @@ sub get_noc_verilator_top_modules_info { # } #} #$includ_h.="\n}\n"; - return ($nr,$ne,$router_p,\%tops,$includ_h); + return ($nr,$ne,$router_p,\%tops,$includ_h); } sub connect_sim_nodes{ @@ -760,7 +788,7 @@ sub gen_tiles_physical_addrsses_header_file{ $txt=$txt."\t#define PHY_ADDR_ENDP_$id $hex\n"; } $txt=$txt."#endif\n"; - save_file($file,$txt); + save_file($file,$txt); } sub get_endpoints_mah_distance { @@ -775,7 +803,7 @@ sub get_endpoints_mah_distance { }elsif ($topology eq '"STAR"'){ return 1; }else { #custom - return undef; + return undef; } } @@ -803,13 +831,13 @@ sub fattree_mah_distance { $pow=1; for (my $i = 0; $i <$l; $i=$i+1 ) { $tmp1=int($router1/$pow); - $tmp2=int($router2/$pow); + $tmp2=int($router2/$pow); $tmp1=$tmp1 % $k; - $tmp2=$tmp2 % $k; - $pow=$pow * $k; + $tmp2=$tmp2 % $k; + $pow=$pow * $k; $distance= ($i+1)*2-1 if($tmp1!=$tmp2); # distance obtained based on the highest level index which differ } - return $distance; + return $distance; } 1 diff --git a/mpsoc/perl_gui/lib/perl/traffic_pattern.pl b/mpsoc/perl_gui/lib/perl/traffic_pattern.pl index ec017d8..b440818 100644 --- a/mpsoc/perl_gui/lib/perl/traffic_pattern.pl +++ b/mpsoc/perl_gui/lib/perl/traffic_pattern.pl @@ -14,9 +14,17 @@ sub get_sample_emulation_param { my $T1=$noc_info{'T1'}; my $T2=$noc_info{'T2'}; my $T3=$noc_info{'T3'}; + my $T4=$noc_info{'T4'}; my $V =$noc_info{'V'}; my $Fpay = $noc_info{'Fpay'}; - return ($topology, $T1, $T2, $T3, $V, $Fpay); + return ($topology, $T1, $T2, $T3, $T4, $V, $Fpay); +} + +sub get_sample_topology_info{ + my ($self,$sample)= @_; + my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $T4, $V, $Fpay); + return ($NE, $NR, $RAw, $EAw, $Fw); } sub getBit{ @@ -38,8 +46,8 @@ sub setBit{ sub pck_dst_gen_2D { my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample); - my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $T4, $V, $Fpay); my $NEw=log2($NE); #for mesh-tori my ($current_l,$current_x, $current_y); @@ -127,8 +135,8 @@ sub pck_dst_gen_2D { sub pck_dst_gen_1D { my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample); - my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay); + my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample); + my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $T4, $V, $Fpay); my $NEw=log2($NE); if( $traffic eq "random") { my @randoms=@{$rnd}; @@ -186,7 +194,7 @@ sub pck_dst_gen_1D { sub pck_dst_gen{ my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_; - my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample); + my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample); return pck_dst_gen_2D ($self,$sample,$traffic,$core_num,$line_num,$rnd) if(( $topology eq '"MESH"') ||( $topology eq '"TORUS"')); return pck_dst_gen_1D ($self,$sample,$traffic,$core_num,$line_num,$rnd); } diff --git a/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC b/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC index ae99c39..d758604 100644 --- a/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC +++ b/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC @@ -1517,7 +1517,7 @@ For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCA 'value' => '4' }, 'ROUTE_NAME' => { - 'value' => '"XY"' + 'value' => '"DOR"' }, 'SELF_LOOP_EN' => { 'value' => '0' diff --git a/mpsoc/rtl/arch/iport_reg_base.sv b/mpsoc/rtl/arch/iport_reg_base.sv index 38ad74f..fdfa09f 100644 --- a/mpsoc/rtl/arch/iport_reg_base.sv +++ b/mpsoc/rtl/arch/iport_reg_base.sv @@ -52,7 +52,7 @@ module iport_reg_base #( parameter VC_REALLOCATION_TYPE = "ATOMIC", parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC" parameter TOPOLOGY = "MESH",//"MESH","TORUS" - parameter ROUTE_NAME="XY",// "XY", "TRANC_XY" + parameter ROUTE_NAME="DOR",// "DOR", "TRANC_DOR" parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE" parameter DEBUG_EN =1, parameter AVC_ATOMIC_EN= 0, @@ -315,10 +315,7 @@ generate .wr_en (flit_wr[i]), // Write enable .rd_en (ivc_num_getting_sw_grant[i]), // Read the next word .dout (flit_is_tail[i]), // Data out - .full ( ), - .nearly_full ( ), - .recieve_more_than_0 ( ), - .recieve_more_than_1 ( ), + .status_o(), .reset (reset), .clk (clk) ); @@ -335,10 +332,7 @@ generate .wr_en (hdr_flit_wr[i]), // Write enable .rd_en (class_rd_fifo[i]), // Read the next word .dout (class_out[i]), // Data out - .full ( ), - .nearly_full ( ), - .recieve_more_than_0 ( ), - .recieve_more_than_1 ( ), + .status_o(), .reset (reset), .clk (clk) @@ -358,10 +352,7 @@ generate .wr_en (hdr_flit_wr_delayed [i]), // Write enable .rd_en (lk_dst_rd_fifo [i]), // Read the next word .dout (lk_destination_encoded [(i+1)*DSTPw-1 : i*DSTPw]), // Data out - .full (), - .nearly_full (), - .recieve_more_than_0 (), - .recieve_more_than_1 (), + .status_o(), .reset (reset), .clk (clk) @@ -381,10 +372,7 @@ generate .wr_en(hdr_flit_wr[i]), // Write enable .rd_en(dst_rd_fifo[i]), // Read the next word .dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out - .full(), - .nearly_full(), - .recieve_more_than_0(), - .recieve_more_than_1(), + .status_o(), .reset(reset), .clk(clk) ); @@ -401,10 +389,7 @@ generate .wr_en(hdr_flit_wr[i]), // Write enable .rd_en(dst_rd_fifo[i]), // Read the next word .dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]), // Data out - .full(), - .nearly_full(), - .recieve_more_than_0(), - .recieve_more_than_1(), + .status_o(), .reset(reset), .clk(clk), .clear(destport_clear[(i+1)*DSTPw-1 : i*DSTPw]) // clear other destination ports once one of them is selected @@ -455,10 +440,7 @@ generate .wr_en(hdr_flit_wr[i]), // Write enable .rd_en(dst_rd_fifo[i]), // Read the next word .dout(endp_localp_num[(i+1)*ELw-1 : i*ELw]), // Data out - .full( ), - .nearly_full( ), - .recieve_more_than_0(), - .recieve_more_than_1(), + .status_o(), .reset(reset), .clk(clk) ); diff --git a/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold b/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold index 2a67880..b23be17 100755 --- a/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold +++ b/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold @@ -15,7 +15,7 @@ module noc_emulator #( parameter T2 = 4, parameter T3 = 1, parameter TOPOLOGY = "MESH", - parameter ROUTE_NAME = "XY", + parameter ROUTE_NAME = "DOR", parameter C = 4, parameter Fpay = 32, parameter MUX_TYPE = "BINARY", @@ -215,7 +215,7 @@ module Jtag_traffic_gen #( parameter Fpay = 32, parameter VC_REALLOCATION_TYPE = "NONATOMIC",// "ATOMIC" , "NONATOMIC" parameter TOPOLOGY = "MESH", - parameter ROUTE_NAME = "XY", + parameter ROUTE_NAME = "DOR", parameter C = 4 , // number of flit class parameter MIN_PCK_SIZE = 2, parameter BYTE_EN=0, @@ -475,7 +475,7 @@ module traffic_gen_ram #( parameter Fpay = 32, parameter VC_REALLOCATION_TYPE = "NONATOMIC",// "ATOMIC" , "NONATOMIC" parameter TOPOLOGY = "MESH", - parameter ROUTE_NAME = "XY", + parameter ROUTE_NAME = "DOR", parameter C = 4, // number of flit class parameter RAM_Aw=7, parameter STATISTIC_NUM=8, // the last 8 rows of RAM is reserved for collecting statistic values; diff --git a/mpsoc/rtl/src_modelsim/traffic_pattern.sv b/mpsoc/rtl/src_modelsim/traffic_pattern.sv index 2da7650..6c6c530 100755 --- a/mpsoc/rtl/src_modelsim/traffic_pattern.sv +++ b/mpsoc/rtl/src_modelsim/traffic_pattern.sv @@ -270,11 +270,11 @@ module pck_dst_gen_unicast input custom_traffic_en; input hotspot_t hotspot_info [HOTSPOT_NUM-1 : 0]; generate - if ( ADDR_DIMENSION == 2) begin :two_dim - two_dimension_pck_dst_gen #( + if ( IS_2D_TOPO | IS_3D_TOPO) begin : MD_ + multi_dimension_pck_dst_gen #( .TRAFFIC(TRAFFIC), .HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM) - ) the_two_dimension_pck_dst_gen ( + ) the_multi_dim_pck_dst_gen ( .reset(reset), .clk(clk), .en(en), @@ -309,9 +309,9 @@ module pck_dst_gen_unicast endmodule /********************************** -* two_dimension_pck_dst_gen +* multi_dimension_pck_dst_gen **********************************/ -module two_dimension_pck_dst_gen +module multi_dimension_pck_dst_gen #( parameter TRAFFIC = "RANDOM", parameter HOTSPOT_NODE_NUM = 4 @@ -332,51 +332,37 @@ module two_dimension_pck_dst_gen localparam PCK_CNTw = log2(MAX_PCK_NUM+1), HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1; - input reset,clk,en; input [NEw-1 : 0] core_num; input [PCK_CNTw-1 : 0] pck_number; input [EAw-1 : 0] current_e_addr; - output [EAw-1 : 0] dest_e_addr; + output logic [EAw-1 : 0] dest_e_addr; output valid_dst; input hotspot_t hotspot_info [HOTSPOT_NUM-1 : 0]; input [NEw-1 : 0] custom_traffic_t; input custom_traffic_en; - wire [NXw-1 : 0] current_x; - wire [NYw-1 : 0] current_y; - wire [NLw-1 : 0] current_l; - wire [NXw-1 : 0] dest_x; - wire [NYw-1 : 0] dest_y; - wire [NLw-1 : 0] dest_l; + regular_topo_endp_addr_t current_addr, dest_addr; + always_comb begin + current_addr = regular_topo_endp_addr_t'(current_e_addr); + //for 2d we need to re-extact the l + current_addr.l=current_e_addr[EAw-1: EAw-NLw]; + end - regular_topo_endp_addr_decode src_addr_decode ( - .e_addr(current_e_addr), - .ex(current_x), - .ey(current_y), - .el(current_l), - .valid( ) - ); wire off_flag; - wire [NEw-1 : 0] dest_ip_num; + wire [NEw-1 : 0] dest_ip_num; genvar i; - generate if (TRAFFIC == "RANDOM") begin logic [6 : 0] rnd_reg; always @(posedge clk ) begin if(en | `pronoc_reset) begin rnd_reg = $urandom_range(NE-1,0); - if(SELF_LOOP_EN == 0) while(rnd_reg==core_num) rnd_reg = $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core - + if(SELF_LOOP_EN == 0) while(rnd_reg==core_num) rnd_reg = $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core end end assign dest_ip_num = rnd_reg; - endp_addr_encoder addr_encoder ( - .id_in(dest_ip_num), - .code_out(dest_e_addr) - ); - + endp_addr_encoder addr_encoder (.id_in(dest_ip_num), .code_out(dest_e_addr)); end else if (TRAFFIC == "HOTSPOT") begin hot_spot_dest_gen #( .HOTSPOT_NUM(HOTSPOT_NUM), @@ -391,110 +377,87 @@ module two_dimension_pck_dst_gen .core_num(core_num), .off_flag(off_flag) ); - endp_addr_encoder addr_encoder ( - .id_in(dest_ip_num), - .code_out(dest_e_addr) - ); + endp_addr_encoder addr_encoder (.id_in(dest_ip_num), .code_out(dest_e_addr)); + end else if( TRAFFIC == "BIT_REVERSE") begin :bitreverse + for(i=0; i<(EAw); i=i+1'b1) begin :lp //reverse the address + assign dest_e_addr[i] = current_e_addr [((EAw)-1)-i]; + end + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); + end else if( TRAFFIC == "BIT_COMPLEMENT") begin :bitcomp + assign dest_e_addr = ~ current_e_addr; + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); end else if( TRAFFIC == "TRANSPOSE1") begin - assign dest_x = NX-current_y-1; - assign dest_y = NY-current_x-1; - assign dest_l = NL-current_l-1; - assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x}; - - endp_addr_decoder enc - ( - .code_in(dest_e_addr), - .id_out(dest_ip_num) - ); - + assign dest_addr.x = (NZ==1 && NY==1)? NX-current_addr.x-1 : NY-current_addr.y-1 ; + assign dest_addr.y = (NZ==1)? NX-current_addr.x-1 : NZ-current_addr.z-1 ; + assign dest_addr.z = NX-current_addr.x-1; + assign dest_addr.l = NL-current_addr.l-1; + always @(*) begin + dest_e_addr = EAw'(dest_addr); + if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l; + end + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); end else if( TRAFFIC == "TRANSPOSE2") begin :transpose2 - assign dest_x = current_y; - assign dest_y = current_x; - assign dest_l = current_l; - assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x}; - endp_addr_decoder enc ( - .code_in(dest_e_addr), - .id_out(dest_ip_num) - ); - end else if( TRAFFIC == "BIT_REVERSE") begin :bitreverse - - for(i=0; i<(EAw); i=i+1'b1) begin :lp//reverse the address - assign dest_ip_num[i] = current_e_addr [((EAw)-1)-i]; + assign dest_addr.x = (NZ==1 && NY==1)? NX-current_addr.x-1 : current_addr.y; + assign dest_addr.y = ( NZ==1)? current_addr.x : current_addr.z; + assign dest_addr.z = current_addr.x; + assign dest_addr.l = current_addr.l; + always @(*) begin + dest_e_addr = EAw'(dest_addr); + if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l; end - - endp_addr_encoder addr_encoder( - .id_in(dest_ip_num), - .code_out(dest_e_addr) - ); - - end else if( TRAFFIC == "BIT_COMPLEMENT") begin :bitcomp - assign dest_x = ~current_x; - assign dest_y = ~current_y; - assign dest_l = ~dest_l; - assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x}; - endp_addr_decoder enc ( - .code_in(dest_e_addr), - .id_out(dest_ip_num) - ); + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); end else if( TRAFFIC == "TORNADO" ) begin :tornado //[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k], - assign dest_x = (current_x> ((NX+1)/2))? current_x- ((NX+1)/2) -1 : (NX/2)+current_x-1; // = ((current_x + ((NX/2)-1))%NX); - assign dest_y = (current_y> ((NY+1)/2))? current_y- ((NY+1)/2) -1 : (NY/2)+current_y-1; // = ((current_y + ((NY/2)-1))%NY); - assign dest_l = current_l; - assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x}; - - endp_addr_decoder enc ( - .code_in(dest_e_addr), - .id_out(dest_ip_num) - ); + assign dest_addr.x = (current_addr.x> ((NX+1)/2))? current_addr.x- ((NX+1)/2) -1 : (NX/2)+current_addr.x-1; // = ((current_x + ((NX/2)-1))%NX); + assign dest_addr.y = (current_addr.y> ((NY+1)/2))? current_addr.y- ((NY+1)/2) -1 : (NY/2)+current_addr.y-1; // = ((current_y + ((NY/2)-1))%NY); + assign dest_addr.z = (current_addr.z> ((NZ+1)/2))? current_addr.z- ((NZ+1)/2) -1 : (NZ/2)+current_addr.z-1; // = ((current_z + ((NZ/2)-1))%NZ); + assign dest_addr.l = current_addr.l; + always @(*) begin + dest_e_addr = EAw'(dest_addr); + if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l; + end + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); end else if( TRAFFIC == "NEIGHBOR") begin :neighbor //dx = sx + 1 mod k - assign dest_x = (current_x + 1) >= NX? 0 : (current_x + 1); - assign dest_y = (current_y + 1) >= NY? 0 : (current_y + 1); - assign dest_l = current_l; - assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x}; - endp_addr_decoder enc( - .code_in(dest_e_addr), - .id_out(dest_ip_num) - ); + assign dest_addr.x = ((current_addr.x + 1) >= NX) ? 0 : (current_addr.x + 1); + assign dest_addr.y = ((current_addr.y + 1) >= NY) ? 0 : (current_addr.y + 1); + assign dest_addr.z = ((current_addr.z + 1) >= NZ) ? 0 : (current_addr.z + 1); + assign dest_addr.l = current_addr.l; + always @(*) begin + dest_e_addr = EAw'(dest_addr); + if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l; + end + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); end else if( TRAFFIC == "SHUFFLE") begin: shuffle - //di = si−1 mod b + //di = si-1 mod b for(i=1; i<(EAw); i=i+1'b1) begin :lp//reverse the address - assign dest_ip_num[i] = current_e_addr [i-1]; + assign dest_e_addr[i] = current_e_addr [i-1]; end - assign dest_ip_num[0] = current_e_addr [EAw-1]; - endp_addr_encoder addr_encoder( - .id(dest_ip_num), - .code(dest_e_addr) - ); + assign dest_e_addr[0] = current_e_addr [EAw-1]; + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); end else if(TRAFFIC == "BIT_ROTATION") begin :bitrot //di = si+1 mod b for(i=0; i<(EAw-1); i=i+1'b1) begin :lp//reverse the address - assign dest_ip_num[i] = current_e_addr [i+1]; + assign dest_e_addr[i] = current_e_addr [i+1]; end - assign dest_ip_num[EAw-1] = current_e_addr [0]; - endp_addr_encoder addr_encoder( - .id_in(dest_ip_num), - .code_out(dest_e_addr) - ); + assign dest_e_addr[EAw-1] = current_e_addr [0]; + endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num)); end else if(TRAFFIC == "CUSTOM" )begin - assign dest_ip_num = custom_traffic_t; endp_addr_encoder addr_encoder ( .id_in(dest_ip_num), .code_out(dest_e_addr) ); assign off_flag = ~custom_traffic_en; - end else begin initial begin $display("ERROR: Undefined Traffic pattern:%s",TRAFFIC); $stop; end end - + wire valid_temp = (dest_ip_num <= (NE-1)); - + if (TRAFFIC == "HOTSPOT" || TRAFFIC == "CUSTOM") begin assign valid_dst = ~off_flag & valid_temp; end else begin diff --git a/mpsoc/rtl/src_noc/congestion_analyzer.sv b/mpsoc/rtl/src_noc/congestion_analyzer.sv index c9748ca..d616d6e 100755 --- a/mpsoc/rtl/src_noc/congestion_analyzer.sv +++ b/mpsoc/rtl/src_noc/congestion_analyzer.sv @@ -33,23 +33,12 @@ ***************************************/ //congestion analyzer based on number of occupied VCs module port_presel_based_dst_ports_vc #( - parameter PPSw=4, - parameter P = 5, - parameter V = 4 + parameter P = 5 )( ovc_status, port_pre_sel ); - - function integer log2; - input integer number; begin - log2=(number <=1) ? 1: 0; - while(2**log2 congestion_y_plus)? YDIR : XDIR; assign conjestion_cmp[X_MINUS_Y_PLUS] = (congestion_x_min > congestion_y_plus)? YDIR : XDIR; assign conjestion_cmp[X_PLUS_Y_MINUS] = (congestion_x_plus > congestion_y_min)? YDIR : XDIR; @@ -263,14 +238,12 @@ endmodule * CONGESTION_INDEX==8,10 ********************************/ module port_presel_based_dst_routers_ovc #( - parameter PPSw=4, - parameter P=5, - parameter V=4, - parameter CONGw=2 //congestion width per port + parameter P=5 )( port_pre_sel, congestion_in_all ); + import pronoc_pkg::*; localparam P_1 = P-1, CONG_ALw = CONGw* P; // congestion width per router; @@ -289,16 +262,18 @@ module port_presel_based_dst_routers_ovc #( Q1 = 1, Q2 = 2, Q0 = 0; - localparam - EAST = 0, - NORTH = 1, - WEST = 2, - SOUTH = 3; + localparam XDIR =1'b0, YDIR =1'b1; - wire [CONGw-1 : 0] congestion_in [P_1-1 : 0]; - assign {congestion_in[SOUTH],congestion_in[WEST],congestion_in[NORTH],congestion_in[EAST]} = congestion_in_all[CONG_ALw-1 : CONGw]; + wire [CONGw-1 : 0] congestion_in [P-1 : 0]; + genvar i; + generate + for(i=0;i (2**INw)-1) ? {INw{1'b1}} : INw'(MAX_IN); + // One-hot output + logic [OUT_ON_HOT_NUM-1:0] one_hot_out; + // Saturate input + logic [INw-1:0] D_clamped; + assign D_clamped = (D_in > MAX) ? MAX : D_in; + // Generate one-hot bins genvar i; - generate - for(i=0;i< OUT_ON_HOT_NUM;i=i+1)begin :lp - /* verilator lint_off WIDTH */ - if(i==0) begin : i0 assign one_hot_out[i]= (D_in <= (MAX_IN /OUT_ON_HOT_NUM)); end - else begin :ib0 assign one_hot_out[i]= ((D_in> ((MAX_IN *i)/OUT_ON_HOT_NUM)) && (D_in<= ((MAX_IN *(i+1))/OUT_ON_HOT_NUM))); end - /* verilator lint_on WIDTH */ - end//for + generate + for (i = 0; i < OUT_ON_HOT_NUM; i++) begin : BIN_GEN + localparam LOW = (MAX_IN * i) / OUT_ON_HOT_NUM; + localparam HIGH = (MAX_IN * (i+1)) / OUT_ON_HOT_NUM; + assign one_hot_out[i] = + (i == 0) ? (D_clamped < INw'(HIGH)) : // first bin: include MIN_IN + (i == OUT_ON_HOT_NUM-1) ? (D_clamped >= INw'(LOW)) : // last bin: include MAX_IN + (D_clamped >= INw'(LOW)) && (D_clamped < INw'(HIGH)); + end endgenerate - - one_hot_to_bin#( + // Convert one-hot to binary + one_hot_to_bin #( .ONE_HOT_WIDTH(OUT_ON_HOT_NUM) - )cnv ( + ) cnv ( .one_hot_code(one_hot_out), .bin_code(Q_out) ); endmodule + /************************** - congestion_out_gen +* congestion_out_gen *************************/ module congestion_out_gen #( - parameter P=5, - parameter V=4, - parameter ROUTE_TYPE ="ADAPTIVE", - parameter CONGESTION_INDEX=2, - parameter CONGw=2 + parameter P=5 )( ivc_request_all, ivc_num_getting_sw_grant, @@ -950,10 +861,10 @@ module congestion_out_gen #( clk, reset ); - -localparam - PV = P*V, - CONG_ALw = CONGw* P; // congestion width per router;; + import pronoc_pkg::*; + localparam + PV = P*V, + CONG_ALw = CONGw* P; // congestion width per router;; input [PV-1 : 0] ovc_avalable_all; input [PV-1 : 0] ivc_request_all; @@ -962,22 +873,23 @@ localparam input clk,reset; wire [CONG_ALw-1 : 0] congestion_out_all_next; + wire [V-1 : 0] ovc_avalable [P-1 : 0]; + genvar i; generate + for (i=0;i 2) begin :mwb2 wire [MUX_SEL_WIDTH-1 : 0] mux_sel; - wire [DEPTH_DATA_WIDTH-1 : 0] depth_2; - wire empty; + wire [DEPTHw-1 : 0] depth_2; wire out_sel ; if(DATA_WIDTH>1) begin :wb1 wire [MAX_DEPTH-2 : 0] mux_in [DATA_WIDTH-1 :0]; wire [DATA_WIDTH-1 : 0] mux_out; reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0]; - for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1; - assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}}; - assign recieve_more_than_0 = ~ empty; - assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== DEPTH_DATA_WIDTH'(1) ); - assign out_sel = (recieve_more_than_1) ? 1'b1 : 1'b0; - assign out_ld = (depth !=DEPTH_DATA_WIDTH'(0) )? rd_en : wr_en; - assign depth_2 = depth - DEPTH_DATA_WIDTH'(2); + assign out_sel = (status_o.has_multiple) ? 1'b1 : 1'b0; + assign out_ld = (depth !=DEPTHw'(0) )? rd_en : wr_en; + assign depth_2 = depth - DEPTHw'(2); assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0]; - end else if ( MAX_DEPTH == 2) begin :mw2 - reg [DATA_WIDTH-1 : 0] din_f; - always @(posedge clk ) begin if(wr_en) din_f <= din; end //always - - assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0]; - assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1; assign out_ld = (depth !=0 )? rd_en : wr_en; - assign recieve_more_than_0 = (depth != {DEPTH_DATA_WIDTH{1'b0}}); - assign recieve_more_than_1 = ~( depth == 0 || depth== 1 ); - assign dout_next = (recieve_more_than_1) ? din_f : din; - + assign dout_next = (status_o.has_multiple) ? din_f : din; end else begin :mw1 // MAX_DEPTH == 1 assign out_ld = wr_en; assign dout_next = din; - assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0]; - assign nearly_full= 1'b1; - assign recieve_more_than_0 = full; - assign recieve_more_than_1 = 1'b0; end endgenerate - always_ff @ (`pronoc_clk_reset_edge )begin - if(`pronoc_reset) begin - depth <= {DEPTH_DATA_WIDTH{1'b0}}; - dout <= {DATA_WIDTH{1'b0}}; - end else begin - depth <= depth_next; - dout <= dout_next_ld; - end + + always_ff @ (`pronoc_clk_reset_edge ) begin + if(`pronoc_reset) begin + depth <= {DEPTHw{1'b0}}; + dout <= {DATA_WIDTH{1'b0}}; + end else begin + depth <= depth_next; + dout <= dout_next_ld; end + end always_comb begin depth_next = depth; @@ -614,22 +572,31 @@ module fwft_fifo #( if (wr_en & ~rd_en) depth_next = depth + 1'h1; else if (~wr_en & rd_en) depth_next = depth - 1'h1; if (out_ld) dout_next_ld = dout_next; + status_o.full = (depth == MAX_DEPTH [DEPTHw-1 : 0]); + status_o.nearly_full = + (MAX_DEPTH == 1)? 1'b1 : + (depth >= MAX_DEPTH [DEPTHw-1 : 0] -1'b1); + status_o.empty = (depth == {DEPTHw{1'b0}}); + status_o.has_data = ~ status_o.empty; + status_o.has_multiple = + (MAX_DEPTH == 1)? 1'b0 : + ~( depth == DEPTHw'(0) || depth== DEPTHw'(1) ); end//always -/********************************************* -* Validating Parameters/Simulation -*********************************************/ + /********************************************* + * Validating Parameters/Simulation + *********************************************/ `ifdef SIMULATION always @(posedge clk) begin - if (wr_en & ~rd_en & full) begin + if (wr_en & ~rd_en & status_o.full) begin $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH); $finish; end - if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == 0) begin + if (rd_en & status_o.empty & IGNORE_SAME_LOC_RD_WR_WARNING == 0) begin $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); $finish; end - if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin + if (rd_en & ~wr_en & status_o.empty & (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); $finish; end @@ -637,14 +604,13 @@ module fwft_fifo #( `endif//SIMULATION endmodule -/********************* - - fwft_fifo_with_output_clear - each individual output bit has - its own clear signal - - **********************/ - +/*************************** + * + * fwft_fifo_with_output_clear + * each individual output bit has + * its own clear signal + * + ***************************/ module fwft_fifo_with_output_clear #( parameter DATA_WIDTH = 2, parameter MAX_DEPTH = 2, @@ -652,59 +618,42 @@ module fwft_fifo_with_output_clear #( ) ( din, // Data in wr_en, // Write enable - rd_en, // Read the next word dout, // Data out - full, - nearly_full, - recieve_more_than_0, - recieve_more_than_1, + rd_en, // Read the next word + status_o,// fifo status reset, clk, clear ); - input [DATA_WIDTH-1:0] din; - input wr_en; - input rd_en; - output logic [DATA_WIDTH-1:0] dout; - output full; - output nearly_full; - output recieve_more_than_0; - output recieve_more_than_1; - input reset; - input clk; + import pronoc_pkg::*; + input [DATA_WIDTH-1:0] din; // Data in + input wr_en; // Write enable + input rd_en; // Read the next word + output logic [DATA_WIDTH-1:0] dout; // Data out + input reset, clk; + output fifo_stat_t status_o; input [DATA_WIDTH-1:0] clear; - function integer log2; - input integer number; begin - log2=(number <=1) ? 1: 0; - while(2**log22) begin :mwb2 wire [MUX_SEL_WIDTH-1 : 0] mux_sel; - wire [DEPTH_DATA_WIDTH-1 : 0] depth_2; - wire empty; + wire [DEPTHw-1 : 0] depth_2; wire out_sel ; if(DATA_WIDTH>1) begin :wb1 wire [MAX_DEPTH-2 : 0] mux_in [DATA_WIDTH-1 :0]; wire [DATA_WIDTH-1 : 0] mux_out; reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0]; - for(i=0;i= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1; - assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}}; - assign recieve_more_than_0 = ~ empty; - assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 ); - assign out_sel = (recieve_more_than_1) ? 1'b1 : 1'b0; + assign out_sel = (status_o.has_multiple) ? 1'b1 : 1'b0; assign out_ld = (depth !=0 )? rd_en : wr_en; assign depth_2 = depth-'d2; assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0]; - end else if ( MAX_DEPTH == 2) begin :mw2 - reg [DATA_WIDTH-1 : 0] din_f; - always @(posedge clk ) begin if(wr_en) din_f <= din; end //always - - assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0]; - assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1; assign out_ld = (depth !=0 )? rd_en : wr_en; - assign recieve_more_than_0 = (depth != {DEPTH_DATA_WIDTH{1'b0}}); - assign recieve_more_than_1 = ~( depth == 0 || depth== 1 ); - assign dout_next = (recieve_more_than_1) ? din_f : din; - + assign dout_next = (status_o.has_multiple) ? din_f : din; end else begin :mw1 // MAX_DEPTH == 1 assign out_ld = wr_en; assign dout_next = din; - assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0]; - assign nearly_full= 1'b1; - assign recieve_more_than_0 = full; - assign recieve_more_than_1 = 1'b0; end endgenerate always_ff @ (`pronoc_clk_reset_edge) begin @@ -781,6 +707,15 @@ module fwft_fifo_with_output_clear #( depth_next = depth; if (wr_en & ~rd_en) depth_next = depth + 1'h1; else if (~wr_en & rd_en) depth_next = depth - 1'h1; + status_o.full = (depth == MAX_DEPTH [DEPTHw-1 : 0]); + status_o.nearly_full = + (MAX_DEPTH == 1)? 1'b1 : + (depth >= MAX_DEPTH [DEPTHw-1 : 0] -1'b1); + status_o.empty = (depth == {DEPTHw{1'b0}}); + status_o.has_data = ~ status_o.empty; + status_o.has_multiple = + (MAX_DEPTH == 1)? 1'b0 : + ~( depth == DEPTHw'(0) || depth== DEPTHw'(1) ); end//always always_comb begin @@ -791,22 +726,21 @@ module fwft_fifo_with_output_clear #( end end - -/********************************************* -* Validating Parameters/Simulation -*********************************************/ + /********************************************* + * Validating Parameters/Simulation + *********************************************/ `ifdef SIMULATION always @(posedge clk) begin if(`pronoc_reset==0)begin - if (wr_en && ~rd_en && full) begin + if (wr_en && ~rd_en && status_o.full) begin $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH); $finish; end - if (rd_en && !recieve_more_than_0 && (IGNORE_SAME_LOC_RD_WR_WARNING == 0)) begin + if (rd_en && status_o.empty && (IGNORE_SAME_LOC_RD_WR_WARNING == 0)) begin $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); $finish; end - if (rd_en && ~wr_en && !recieve_more_than_0 && (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin + if (rd_en && ~wr_en && status_o.empty && (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); $finish; end @@ -815,64 +749,63 @@ module fwft_fifo_with_output_clear #( `endif // SIMULATION endmodule -/*************** -fwft_fifo_bram -****************/ +/*************************** +*fwft_fifo_bram +* An FWFT FIFO implementation based on BRAMs +* optimized for low LUTs utilization. +***************************/ module fwft_fifo_bram #( parameter DATA_WIDTH = 2, parameter MAX_DEPTH = 2, parameter IGNORE_SAME_LOC_RD_WR_WARNING=1 // 1 : "YES" , 0: "NO" - ) ( - input [DATA_WIDTH-1:0] din, // Data in - input wr_en, // Write enable - input rd_en, // Read the next word - output [DATA_WIDTH-1:0] dout, // Data out - output full, - output nearly_full, - output recieve_more_than_0, - output recieve_more_than_1, - input reset, - input clk + )( + din, // Data in + wr_en, // Write enable + rd_en, // Read the next word + dout, // Data out + stat_o, + reset, + clk ); + import pronoc_pkg::*; + input [DATA_WIDTH-1:0] din; // Data in + input wr_en; // Write enable + input rd_en; // Read the next word + output [DATA_WIDTH-1:0] dout; // Data out + output fifo_stat_t stat_o; + input reset; + input clk; - function integer log2; - input integer number; begin - log2=(number <=1) ? 1: 0; - while(2**log2= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1; - assign empty = depth == {DEPTH_DATA_WIDTH{1'b0}}; - assign recieve_more_than_0 = ~ empty; - assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} || depth== 1 ); + assign stat_o.full = (depth == MAX_DEPTH [DEPTHw-1 : 0]); + assign stat_o.nearly_full = (depth >= MAX_DEPTH [DEPTHw-1 : 0] -1'b1); + assign stat_o.empty = (depth == {DEPTHw{1'b0}}); + assign stat_o.has_data = ~(depth == {DEPTHw{1'b0}}); + assign stat_o.has_multiple = ~((depth == DEPTHw'(0)) || (depth == DEPTHw'(1))); `ifdef SIMULATION always @(posedge clk) begin - if (wr_en & ~rd_en & full) begin + if (wr_en & ~rd_en & stat_o.full) begin $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH); $finish; end - if (rd_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == 0)) begin + if (rd_en & stat_o.empty & (IGNORE_SAME_LOC_RD_WR_WARNING == 0)) begin $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); $finish; end - if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin + if (rd_en & ~wr_en & stat_o.empty & (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); $finish; end end // always `endif // SIMULATION - endmodule /********************************** - bram_based_fifo - *********************************/ +* bram_based_fifo +*********************************/ module bram_based_fifo #( parameter Dw = 72,//data_width parameter B = 10// buffer num @@ -949,22 +878,11 @@ module bram_based_fifo #( wr_en, rd_en, dout, - full, - nearly_full, - empty, + stat_o, reset, clk ); - - function integer log2; - input integer number; begin - log2=(number <=1) ? 1: 0; - while(2**log2=Bint2; // B-1 - assign empty = depth == {DEPTHw{1'b0}}; - + always_comb begin + stat_o.full = depth == B [DEPTHw-1 : 0]; + stat_o.nearly_full = depth >=Bint2; // B-1 + stat_o.empty = depth == {DEPTHw{1'b0}}; + stat_o.has_data = ~(depth == {DEPTHw{1'b0}}); + stat_o.has_multiple = ~((depth == DEPTHw'(0)) || (depth == DEPTHw'(1))); + end `ifdef SIMULATION always @(posedge clk) begin if(`pronoc_reset==1'b0)begin @@ -1041,5 +956,4 @@ module bram_based_fifo #( end//~reset end `endif - endmodule diff --git a/mpsoc/rtl/src_noc/fmesh.sv b/mpsoc/rtl/src_noc/fmesh.sv index 88e5bc8..bb8642f 100644 --- a/mpsoc/rtl/src_noc/fmesh.sv +++ b/mpsoc/rtl/src_noc/fmesh.sv @@ -79,15 +79,9 @@ endmodule module fmesh_destp_generator #( - parameter ROUTE_NAME = "XY", - parameter ROUTE_TYPE = "DETERMINISTIC", parameter P=5, - parameter DSTPw=4, - parameter NL=1, parameter PLw=1, - parameter PPSw=4, - parameter SW_LOC=0, - parameter SELF_LOOP_EN=0 + parameter SW_LOC=0 )( dest_port_out, dest_port_coded, @@ -96,7 +90,7 @@ module fmesh_destp_generator #( port_pre_sel, odd_column ); - + import pronoc_pkg::*; localparam P_1 = (SELF_LOOP_EN )? P : P-1; input [DSTPw-1 : 0] dest_port_coded; @@ -109,14 +103,9 @@ module fmesh_destp_generator #( wire [P_1-1 : 0] dest_port_in; fmesh_destp_decoder #( - .ROUTE_TYPE(ROUTE_TYPE), .P(P), - .DSTPw(DSTPw), - .NL(NL), .PLw(PLw), - .PPSw(PPSw), - .SW_LOC(SW_LOC), - .SELF_LOOP_EN(SELF_LOOP_EN) + .SW_LOC(SW_LOC) ) decoder ( .dest_port_coded(dest_port_coded), .dest_port_out(dest_port_in), @@ -130,14 +119,9 @@ endmodule module fmesh_destp_decoder #( - parameter ROUTE_TYPE="DETERMINISTIC", parameter P=6, - parameter DSTPw=4, - parameter NL=2, parameter PLw=1, - parameter PPSw=4, - parameter SW_LOC=0, - parameter SELF_LOOP_EN=0 + parameter SW_LOC=0 )( dest_port_coded, endp_localp_num, @@ -145,6 +129,7 @@ module fmesh_destp_decoder #( swap_port_presel, port_pre_sel ); + import pronoc_pkg::*; localparam P_1 = (SELF_LOOP_EN )? P : P-1; input [DSTPw-1 : 0] dest_port_coded; @@ -159,7 +144,7 @@ module fmesh_destp_decoder #( assign {x,y,a,b} = dest_port_coded; wire [PPSw-1:0] port_pre_sel_final; assign port_pre_sel_final = - ( ROUTE_TYPE == "DETERMINISTIC") ? {PPSw{1'b1}}: + ( IS_DETERMINISTIC ) ? {PPSw{1'b1}}: (swap_port_presel) ? ~port_pre_sel : port_pre_sel; always_comb begin case({a,b}) @@ -176,7 +161,7 @@ module fmesh_destp_decoder #( endp_localp_onehot = {P{1'b0}}; endp_localp_onehot[endp_localp_num] = 1'b1; end - + generate if(NL>1) begin :multi assign destport_onehot =(portout[0])? endp_localp_onehot : /*select local destination*/ @@ -184,19 +169,17 @@ module fmesh_destp_decoder #( end else begin assign destport_onehot =(portout[0])? endp_localp_onehot : /*select local destination*/ portout; - end - if(SELF_LOOP_EN == 0) begin :nslp - remove_sw_loc_one_hot #( - .P(P), - .SW_LOC(SW_LOC) - ) remove_sw_loc ( - .destport_in(destport_onehot), - .destport_out(dest_port_out) - ); - end else begin: slp - assign dest_port_out = destport_onehot; - end - endgenerate + end + endgenerate + + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(P), + .SW_LOC(SW_LOC) + ) fix ( + .destport_in(destport_onehot), + .destport_out(dest_port_out) + ); endmodule diff --git a/mpsoc/rtl/src_noc/header_flit.sv b/mpsoc/rtl/src_noc/header_flit.sv index b7cfb27..0119721 100644 --- a/mpsoc/rtl/src_noc/header_flit.sv +++ b/mpsoc/rtl/src_noc/header_flit.sv @@ -180,6 +180,46 @@ module extract_header_flit_info # ( assign hdr_flit_wr_o= (flit_in_wr & hdr_flg_o )? vc_num_o : {V{1'b0}}; endmodule +module header_flit_info #( + parameter DATA_w = 0 +)( + flit, + hdr_flit, + data_o +); + + import pronoc_pkg::*; + + localparam + Dw = (DATA_w==0)? 1 : DATA_w; + + input flit_t flit; + output hdr_flit_t hdr_flit; + output [Dw-1 : 0] data_o; + + localparam + DATA_LSB= MSB_BE+1, + DATA_MSB= (DATA_LSB + DATA_w)1)? flit.payload [CLASS_MSB : CLASS_LSB] : {Cw{1'b0}}; + hdr_flit.weight = (IS_WRRA)? flit.payload [WEIGHT_MSB : WEIGHT_LSB] : {WEIGHTw{1'b0}}; + hdr_flit.be = (BYTE_EN)? flit.payload [BE_MSB : BE_LSB]: {BEw{1'b0}}; + end + + wire [OFFSETw-1 : 0 ] offset = flit.payload [DATA_MSB : DATA_LSB]; + generate + if(Dw > OFFSETw) begin : if1 + assign data_o={{(Dw-OFFSETw){1'b0}},offset}; + end else begin : if2 + assign data_o=offset[Dw-1 : 0]; + end + endgenerate +endmodule /*********************************** * flit_update diff --git a/mpsoc/rtl/src_noc/inout_ports.sv b/mpsoc/rtl/src_noc/inout_ports.sv index ac65f6e..f04e998 100755 --- a/mpsoc/rtl/src_noc/inout_ports.sv +++ b/mpsoc/rtl/src_noc/inout_ports.sv @@ -251,11 +251,7 @@ module inout_ports #( ); congestion_out_gen #( - .P(P), - .V(V), - .ROUTE_TYPE(ROUTE_TYPE), - .CONGESTION_INDEX(CONGESTION_INDEX), - .CONGw(CONGw) + .P(P) ) congestion_out ( .ovc_avalable_all(ovc_avalable_all), .ivc_request_all(ivc_request_all), @@ -267,7 +263,7 @@ module inout_ports #( genvar i; generate - + if( SSA_EN == 1 ) begin : ssa ss_allocator #( .P(P) @@ -313,14 +309,12 @@ module inout_ports #( endmodule /****************** - output_vc_status +* output_vc_status ******************/ module output_vc_status #( - parameter V = 4, - parameter B = 16, + parameter PORT_B = 16, parameter CAND_VC_SEL_MODE = 0, // 0: use arbiteration between not full vcs, 1: select the vc with most availble free space - parameter CRDTw = 4, - parameter HETERO_VC=0 + parameter CRDTw = 4 )( credit_init_val_in, ovc_presence, @@ -334,7 +328,7 @@ module output_vc_status #( clk, reset ); - + import pronoc_pkg::*; input [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in ; input [V-1 : 0] ovc_presence; input [V-1 : 0] wr_in; @@ -347,16 +341,7 @@ module output_vc_status #( input clk; input reset; - function integer log2; - input integer number; begin - log2=(number <=1) ? 1: 0; - while(2**log20 && vc_num_in[j] && t1[j]==0)begin - $display("%t : Parser:current_r=%h, class_in=%h, destport_in=%h, dest_e_addr_in=%h, src_e_addr_in=%h, vc_num_in=%h,hdr_flit_wr=%h, hdr_flg_in=%h,tail_flg_in=%h ",$time,current_r_addr, class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in); + if(flit_in_wr > 0 && flit_in.vc[j] && t1[j]==0)begin + $display("%t : Parser:current_r=%h, hdr_info:%p, vc_num_in=%h,hdr_flit_wr=%h",$time,current_r_addr, hdr_flit_i, flit_in.vc,hdr_flit_wr); t1[j]<=1; end end @@ -993,7 +894,7 @@ module destp_generator #( Pw = log2(P), PLw = (IS_FMESH) ? Pw : ELw, P_1 = (SELF_LOOP_EN )? P : P-1; - + input [DSTPw-1 : 0] dest_port_encoded; input [PLw-1 : 0] endp_localp_num; output [P_1-1: 0] dest_port_out; @@ -1004,18 +905,14 @@ module destp_generator #( generate if( ~IS_UNICAST ) begin : muticast - // destination port is not coded for multicast/broadcast - if( SELF_LOOP_EN==0) begin : nslp - remove_sw_loc_one_hot #( - .P(P), - .SW_LOC(SW_LOC) - ) remove_sw_loc ( - .destport_in(dest_port_encoded), - .destport_out(dest_port_out) - ); - end else begin : slp - assign dest_port_out = dest_port_encoded; - end + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(P), + .SW_LOC(SW_LOC) + ) fix_sw_loc ( + .destport_in(dest_port_encoded), + .destport_out(dest_port_out) + ); end else if( IS_FATTREE ) begin : fat fattree_destp_generator #( .K(T1), @@ -1042,16 +939,9 @@ module destp_generator #( ); end else if( IS_REGULAR_TOPO ) begin : regular regular_topo_destp_generator #( - .TOPOLOGY(TOPOLOGY), - .ROUTE_NAME(ROUTE_NAME), - .ROUTE_TYPE(ROUTE_TYPE), .P(P), - .DSTPw(DSTPw), - .NL(NL), .PLw(PLw), - .PPSw(PPSw), - .SW_LOC(SW_LOC), - .SELF_LOOP_EN(SELF_LOOP_EN) + .SW_LOC(SW_LOC) ) destp_generator ( .dest_port_coded(dest_port_encoded), .endp_localp_num(endp_localp_num), @@ -1062,15 +952,9 @@ module destp_generator #( ); end else if ( IS_FMESH ) begin :fmesh fmesh_destp_generator #( - .ROUTE_NAME(ROUTE_NAME), - .ROUTE_TYPE(ROUTE_TYPE), .P(P), - .DSTPw(DSTPw), - .NL(NL), .PLw(PLw), - .PPSw(PPSw), - .SW_LOC(SW_LOC), - .SELF_LOOP_EN(SELF_LOOP_EN) + .SW_LOC(SW_LOC) ) destp_generator ( .dest_port_coded(dest_port_encoded), .endp_localp_num(endp_localp_num), @@ -1132,19 +1016,14 @@ module custom_topology_destp_decoder #( dest_port_one_hot[dest_port_in_encoded] = 1'b1; end - generate - if( SELF_LOOP_EN==0) begin : nslp - remove_sw_loc_one_hot #( - .P(P), - .SW_LOC(SW_LOC) - ) remove_sw_loc ( - .destport_in(dest_port_one_hot[P-1 : 0]), - .destport_out(dest_port_out) - ); - end else begin : slp - assign dest_port_out = dest_port_one_hot; - end - endgenerate + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(P), + .SW_LOC(SW_LOC) + ) remove_sw_loc ( + .destport_in(dest_port_one_hot[P-1 : 0]), + .destport_out(dest_port_out) + ); `ifdef SIMULATION initial begin diff --git a/mpsoc/rtl/src_noc/mesh_3d_top.sv b/mpsoc/rtl/src_noc/mesh_3d_top.sv new file mode 100644 index 0000000..67ff523 --- /dev/null +++ b/mpsoc/rtl/src_noc/mesh_3d_top.sv @@ -0,0 +1,151 @@ +`include "pronoc_def.v" +/********************************************************************** +** File: mesh_cluster.sv +** +** Copyright (C) 2014-2017 Alireza Monemi +** +** This file is part of ProNoC +** +** ProNoC ( stands for Prototype Network-on-chip) is free software: +** you can redistribute it and/or modify it under the terms of the GNU +** Lesser General Public License as published by the Free Software Foundation, +** either version 2 of the License, or (at your option) any later version. +** +** ProNoC is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with ProNoC. If not, see . +** +** +** +** Description: +** A `mesh_cluster` refers to a group of interconnected routers arranged in a **3D Mesh topology** +** within a larger **Multi-Mesh NoC** for chiplets. In this architecture, each chiplet functions +** as an independent cluster of nodes, featuring its own local mesh-based communication network. +** +** Each router in the `mesh_cluster` drives two I/O channels: +** 1. **Endpoint Channel** – Connects to processing elements (PEs) or memory endpoints. +** 2. **Vertical Link Channel** – Facilitates inter-cluster communication. +** +** If an endpoint or vertical link is not present in the target Multi-Mesh topology, +** the corresponding input is tied to **ground**, enabling synthesis optimizations +** that effectively remove unused logic. +** +***************************************/ + +module mesh_3d_noc_top ( + reset, + clk, + chan_in_all, + chan_out_all, + router_event +); + import pronoc_pkg::*; + input clk,reset; + //Endpoints ports + input smartflit_chanel_t chan_in_all [NE-1 : 0]; + output smartflit_chanel_t chan_out_all [NE-1 : 0]; + //Events + output router_event_t router_event [NR-1 : 0][MAX_P-1 : 0]; + + //indididual routers interconnect ports + smartflit_chanel_t router_chan_in [NZ-1:0][NY-1:0][NX-1:0][MAX_P-1:0]; + smartflit_chanel_t router_chan_out [NZ-1:0][NY-1:0][NX-1:0][MAX_P-1:0]; + //Unused Input channels are connected to ground + smartflit_chanel_t is_grounded; + assign is_grounded= {SMARTFLIT_CHANEL_w{1'b0}}; + + regular_topo_router_addr_t current_r_addr [NR-1:0]; + regular_topo_endp_addr_t endp_addr [NE-1:0]; + router_config_t router_config_in [NR-1 : 0]; + + genvar x,y,z,l; + generate + if(IS_MESH_3D) begin + for (z=0; z current_router_addr_i.x)? MASS:(dest_router_addr_i.x == current_router_addr_i.x)?EQUAL : LESS; + assign Dy = (dest_router_addr_i.y > current_router_addr_i.y)? MASS:(dest_router_addr_i.y == current_router_addr_i.y)?EQUAL : LESS; + assign Dz = (dest_router_addr_i.z > current_router_addr_i.z)? MASS:(dest_router_addr_i.z == current_router_addr_i.z)?EQUAL : LESS; + + always_comb begin + destport=0; + if(Dx==MASS) destport =DSTPw'(EAST); + else if(Dx==LESS) destport =DSTPw'(WEST); + else if(Dy==MASS) destport =DSTPw'(SOUTH); + else if(Dy==LESS) destport =DSTPw'(NORTH); + else if(Dz==MASS) destport =DSTPw'(UP); + else if(Dz==LESS) destport =DSTPw'(DOWN); + else destport = DSTPw'(LOCAL); + end +endmodule + diff --git a/mpsoc/rtl/src_noc/mesh_torus.sv b/mpsoc/rtl/src_noc/mesh_torus.sv index 73d6cae..5b40cd1 100755 --- a/mpsoc/rtl/src_noc/mesh_torus.sv +++ b/mpsoc/rtl/src_noc/mesh_torus.sv @@ -33,14 +33,7 @@ * ---------x * 0 | 2 ***************************/ -module regular_topo_vc_alloc_request_gen_adaptive #( - parameter ROUTE_TYPE = "FULL_ADAPTIVE", // "FULL_ADAPTIVE", "PAR_ADAPTIVE" - parameter V = 4, - parameter DSTPw=4, - parameter SSA_EN = 0, - parameter PPSw=4, - parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000 // mask scape vc, valid only for full adaptive -)( +module regular_topo_vc_alloc_request_gen_adaptive ( ovc_avalable_all, dest_port_coded_all, candidate_ovc_all, @@ -56,6 +49,7 @@ module regular_topo_vc_alloc_request_gen_adaptive #( reset, clk ); + import pronoc_pkg::*; localparam P = 5, P_1 = P-1, @@ -64,13 +58,6 @@ module regular_topo_vc_alloc_request_gen_adaptive #( VP_1 = V * P_1, PVDSTPw = PV * DSTPw; - localparam - LOCAL = 3'd0, - EAST = 3'd1, - NORTH = 3'd2, - WEST = 3'd3, - SOUTH = 3'd4; - input [PV-1 : 0] ovc_avalable_all; input [PVDSTPw-1 : 0] dest_port_coded_all; input [PV-1 : 0] ivc_request_all; @@ -85,7 +72,6 @@ module regular_topo_vc_alloc_request_gen_adaptive #( input [PV-1 : 0] ssa_ivc_num_getting_ovc_grant_all; input reset,clk; - wire [PV-1 : 0] non_assigned_ovc_request_all; wire [PV-1 : 0] y_evc_forbiden,x_evc_forbiden; wire [V-1 : 0] ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus,ovc_avb_local; @@ -93,7 +79,6 @@ module regular_topo_vc_alloc_request_gen_adaptive #( wire [PPSw-1 : 0] port_pre_sel_perport [P-1 : 0]; wire [PVV-1 : 0] candidate_ovc_x_all, candidate_ovc_y_all; - assign non_assigned_ovc_request_all = ivc_request_all & ~ovc_is_assigned_all; assign {ovc_avb_y_minus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_x_plus,ovc_avb_local} = ovc_avalable_all; assign ovc_avalable_perport[LOCAL] = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus}; @@ -124,8 +109,7 @@ module regular_topo_vc_alloc_request_gen_adaptive #( ); regular_topo_port_selector #( - .SW_LOC (i/V), - .PPSw(PPSw) + .SW_LOC (i/V) ) the_portsel ( .port_pre_sel (port_pre_sel_perport[i/V]), .swap_port_presel (swap_port_presel[i]), @@ -136,8 +120,6 @@ module regular_topo_vc_alloc_request_gen_adaptive #( ); regular_topo_dspt_clear_gen #( - .SSA_EN(SSA_EN), - .DSTPw(DSTPw), .SW_LOC(i/V) ) dspt_clear_gen ( .destport_clear(destport_clear_all[((i+1)*DSTPw)-1 : i*DSTPw]), @@ -154,8 +136,6 @@ module regular_topo_vc_alloc_request_gen_adaptive #( assign avc_unavailable[i] = (masked_ovc_request_all [((i+1)*V)-1 : i*V] & ~ESCAP_VC_MASK) == {V{1'b0}}; regular_topo_swap_port_presel_gen #( - .V(V), - .ESCAP_VC_MASK(ESCAP_VC_MASK), .VC_NUM(i) ) swap_presel ( .avc_unavailable(avc_unavailable[i]), @@ -179,8 +159,6 @@ endmodule module regular_topo_dspt_clear_gen #( - parameter SSA_EN = 1, - parameter DSTPw =4, parameter SW_LOC=0 )( destport_clear, @@ -188,16 +166,12 @@ module regular_topo_dspt_clear_gen #( sel, ssa_ivc_num_getting_ovc_grant ); - + import pronoc_pkg::*; output [DSTPw-1 : 0] destport_clear; input ivc_num_getting_ovc_grant; input sel; input ssa_ivc_num_getting_ovc_grant; - localparam - LOCAL = 3'd0, - EAST = 3'd1, - WEST = 3'd3; generate if ( SSA_EN==1 ) begin :predict_if if (SW_LOC == LOCAL ) begin :local_if @@ -220,18 +194,15 @@ module regular_topo_dspt_clear_gen #( endmodule -module regular_topo_mask_non_assignable_destport #( - parameter TOPOLOGY="MESH", - parameter ROUTE_NAME="XY", +module regular_topo_mask_non_assignable_destport #( parameter SW_LOC=0, - parameter P=5, - parameter SELF_LOOP_EN=0 + parameter P=5 ) ( odd_column,// use only for odd even routing dest_port_in, dest_port_out ); - + import pronoc_pkg::*; localparam P_1 = (SELF_LOOP_EN )? P : P-1; input [P_1-1 : 0 ] dest_port_in; output [P_1-1 : 0 ] dest_port_out; @@ -266,8 +237,6 @@ module regular_topo_mask_non_assignable_destport #( endgenerate regular_topo_mask_non_assignable_destport_no_self_loop # ( - .TOPOLOGY(TOPOLOGY), - .ROUTE_NAME(ROUTE_NAME), .SW_LOC(SW_LOC), .P(P) ) mask_no_self_loop ( @@ -278,8 +247,6 @@ module regular_topo_mask_non_assignable_destport #( endmodule module regular_topo_mask_non_assignable_destport_no_self_loop #( - parameter TOPOLOGY="MESH", - parameter ROUTE_NAME="XY", parameter SW_LOC=0, parameter P=5 )( @@ -287,12 +254,7 @@ module regular_topo_mask_non_assignable_destport_no_self_loop #( dest_port_in, dest_port_out ); - - localparam - EAST = 1, - NORTH = 2, - WEST = 3, - SOUTH = 4; + import pronoc_pkg::*; //port number in north port localparam N_LOCAL = 0, @@ -333,7 +295,7 @@ module regular_topo_mask_non_assignable_destport_no_self_loop #( assign dest_port_out[P_1-1:4] = dest_port_in[P_1-1:4]; //other local ports end /* verilator lint_off WIDTH */ - if ( ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY") begin :xy + if ( ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR") begin :xy /* verilator lint_on WIDTH */ if (SW_LOC == NORTH ) begin : nort_p // The port located in y axsis does not send packets to x dimension assign dest_port_out[N_LOCAL]= dest_port_in[N_LOCAL]; @@ -427,8 +389,6 @@ endmodule module regular_topo_swap_port_presel_gen #( - parameter V = 4, - parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000, // mask scape vc, valid only for full adaptive parameter VC_NUM=0 )( avc_unavailable, @@ -440,7 +400,7 @@ module regular_topo_swap_port_presel_gen #( clk, reset ); - + import pronoc_pkg::*; localparam LOCAL_VC_NUM= VC_NUM % V; input avc_unavailable; input y_evc_forbiden,x_evc_forbiden; @@ -528,8 +488,7 @@ endmodule module regular_topo_port_selector #( - parameter SW_LOC = 0, - parameter PPSw=4 + parameter SW_LOC = 0 )( port_pre_sel, dest_port_in, @@ -538,7 +497,7 @@ module regular_topo_port_selector #( y_evc_forbiden, x_evc_forbiden ); - + import pronoc_pkg::*; /************************ * * destination-port_in @@ -666,15 +625,15 @@ module mesh_line_distance_gen ( input [EAw-1 : 0] src_e_addr; input [EAw-1 : 0] dest_e_addr; output[DISTw-1: 0]distance; - wire [NXw-1 : 0]src_x,dest_x; - wire [NYw-1 : 0]src_y,dest_y; - regular_topo_endp_addr_decode src_addr_decode (.e_addr(src_e_addr), .ex(src_x), .ey(src_y), .el(), .valid()); - regular_topo_endp_addr_decode dst_addr_decode (.e_addr(dest_e_addr), .ex(dest_x), .ey(dest_y), .el(), .valid()); + regular_topo_router_addr_t src_router_addr, dest_router_addr; + assign src_router_addr = regular_topo_router_addr_t'(src_e_addr); + assign dest_router_addr = regular_topo_router_addr_t'(dest_e_addr); + logic [NXw-1 : 0] x_offset; logic [NYw-1 : 0] y_offset; always_comb begin - x_offset = (src_x > dest_x) ? src_x - dest_x : dest_x - src_x; - y_offset = (src_y > dest_y) ? src_y - dest_y : dest_y - src_y; + x_offset = (src_router_addr.x > dest_router_addr.x) ? src_router_addr.x - dest_router_addr.x : dest_router_addr.x - src_router_addr.x; + y_offset = (src_router_addr.y > dest_router_addr.y) ? src_router_addr.y - dest_router_addr.y : dest_router_addr.y - src_router_addr.y; end /* verilator lint_off WIDTH */ assign distance = x_offset+y_offset+1'b1; @@ -692,8 +651,13 @@ module ring_torus_distance_gen ( output[DISTw-1: 0]distance; wire [NXw-1 : 0]src_x,dest_x; wire [NYw-1 : 0]src_y,dest_y; - regular_topo_endp_addr_decode src_addr_decode (.e_addr(src_e_addr), .ex(src_x), .ey(src_y), .el(), .valid()); - regular_topo_endp_addr_decode dest_addr_decode (.e_addr(dest_e_addr), .ex(dest_x), .ey(dest_y), .el(), .valid()); + regular_topo_router_addr_t src_router_addr, dest_router_addr; + assign src_router_addr = regular_topo_router_addr_t'(src_e_addr); + assign dest_router_addr = regular_topo_router_addr_t'(dest_e_addr); + assign src_x = src_router_addr.x; + assign src_y = src_router_addr.y; + assign dest_x = dest_router_addr.x; + assign dest_y = dest_router_addr.y; logic [NXw-1 : 0] x_offset; logic [NYw-1 : 0] y_offset; wire tranc_x_plus,tranc_x_min,tranc_y_plus,tranc_y_min,same_x,same_y; @@ -744,36 +708,26 @@ module ring_torus_distance_gen ( endmodule -module regular_topo_ssa_check_destport #( - parameter ROUTE_TYPE="DETERMINISTIC", +module two_dim_ssa_check_destport #( parameter SW_LOC = 0, - parameter P=5, - parameter DEBUG_EN = 0, - parameter DSTPw = P-1, parameter SS_PORT=0 )( destport_encoded, //exsited packet dest port destport_in_encoded, // incomming packet dest port ss_port_hdr_flit, - ss_port_nonhdr_flit + ss_port_nonhdr_flit `ifdef SIMULATION ,clk, ivc_num_getting_sw_grant, hdr_flg `endif ); - + import pronoc_pkg::*; input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; output ss_port_hdr_flit, ss_port_nonhdr_flit; `ifdef SIMULATION input clk, ivc_num_getting_sw_grant,hdr_flg; `endif - //MESH, TORUS Topology p=5 - localparam - LOCAL = 0, - EAST = 1, - WEST = 3; - /************************* * destination port is coded * destination-port_in @@ -818,12 +772,8 @@ endgenerate endmodule -module line_ring_ssa_check_destport #( - parameter ROUTE_TYPE="DETERMINISTIC", +module one_dim_ssa_check_destport #( parameter SW_LOC = 0, - parameter P=3, - parameter DEBUG_EN = 0, - parameter DSTPw = P-1, parameter SS_PORT=0 )( destport_encoded, //exsited packet dest port @@ -831,9 +781,10 @@ module line_ring_ssa_check_destport #( ss_port_hdr_flit, ss_port_nonhdr_flit ); + import pronoc_pkg::*; input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; output ss_port_hdr_flit, ss_port_nonhdr_flit; - wire [P-1 : 0] dest_port_num,assigned_dest_port_num; + wire [MAX_P-1 : 0] dest_port_num,assigned_dest_port_num; line_ring_decode_dstport cnv1( .dstport_one_hot(dest_port_num), @@ -859,7 +810,7 @@ module regular_topo_router_addr_decode ( localparam RXw = log2(NX), // number of node in x axis - RYw = (IS_RING | IS_LINE) ? 1 : log2(NY); // number of node in y axis + RYw = (IS_1D_TOPO) ? 1 : log2(NY); // number of node in y axis /* verilator lint_off WIDTH */ localparam [RXw-1 : 0] MAXX = (NX-1); localparam [RYw-1 : 0] MAXY = (NY-1); @@ -871,7 +822,7 @@ module regular_topo_router_addr_decode ( output valid; generate - if (IS_RING | IS_LINE) begin :oneD + if (IS_1D_TOPO) begin :D1_ assign rx = r_addr; assign ry = 1'b0; end else begin : twoD @@ -883,63 +834,32 @@ module regular_topo_router_addr_decode ( /* verilator lint_on CMPCONST */ endmodule - -module regular_topo_endp_addr_decode -( - e_addr, - ex, - ey, - el, +module regular_topo_address_validator ( + addr, valid ); import pronoc_pkg::*; - localparam - EXw = log2(NX), // number of node in x axis - EYw = (IS_RING | IS_LINE) ? 1 : log2(NY), - ELw = log2(NL); // number of node in y axis - /* verilator lint_off WIDTH */ - localparam [EXw-1 : 0] MAXX = (NX-1); - localparam [EYw-1 : 0] MAXY = (NY-1); - localparam [ELw-1 : 0] MAXL = (NL-1); - /* verilator lint_on WIDTH */ - - input [EAw-1 : 0] e_addr; - output [EXw-1 : 0] ex; - output [EYw-1 : 0] ey; - output [ELw-1 : 0] el; - output valid; - - generate - if (IS_RING | IS_LINE) begin :oneD - if(NL==1) begin:one_local - assign ex = e_addr; - assign ey = 1'b0; - assign el = 1'b0; - /* verilator lint_off CMPCONST */ - assign valid = ex<= MAXX; - /* verilator lint_on CMPCONST */ - end else begin: multi_local - assign {el,ex} = e_addr; - assign ey = 1'b0; - /* verilator lint_off CMPCONST */ - assign valid = ((ex<= MAXX) & (el<=MAXL)); - /* verilator lint_on CMPCONST */ + input [EAw-1 : 0] addr; + output logic valid; + regular_topo_endp_addr_t endp_addr; + always_comb begin + endp_addr = regular_topo_endp_addr_t'(addr); + //for 2/1d we need to re-extact the l + endp_addr.l=addr[EAw-1: EAw-NLw]; + end + always_comb begin + valid = 1'b1; + if(32'(endp_addr.x) >= NX) valid = 1'b0; + if((IS_2D_TOPO | IS_3D_TOPO) && ((NY & (NY - 1)) != 0) ) begin + if(32'(endp_addr.y) >= NY) valid = 1'b0; end - end else begin : twoD - if(NL==1)begin:one_local - assign {ey,ex} = e_addr; - assign el = 1'b0; - /* verilator lint_off CMPCONST */ - assign valid = (ex<= MAXX) & (ey <= MAXY); - /* verilator lint_on CMPCONST */ - end else begin :multi_l - assign {el,ey,ex} = e_addr; - /* verilator lint_off CMPCONST */ - assign valid = ( (ex<= MAXX) & (ey <= MAXY) & (el<=MAXL) ); - /* verilator lint_on CMPCONST */ + if(IS_3D_TOPO) begin + if(32'(endp_addr.z) >= NZ) valid = 1'b0; + end + if(NL>1) begin + if(32'(endp_addr.l) >= NL) valid = 1'b0; end end - endgenerate endmodule @@ -947,7 +867,6 @@ endmodule * Regular_topo_endp_addr_encoder * most probably it is only needed for simulation purposes ***************/ - module regular_topo_endp_addr_encoder ( id, @@ -989,16 +908,9 @@ module regular_topo_addr_coder ( endmodule module regular_topo_destp_generator #( - parameter TOPOLOGY = "MESH", - parameter ROUTE_NAME = "XY", - parameter ROUTE_TYPE = "DETERMINISTIC", parameter P=5, - parameter DSTPw=4, - parameter NL=1, parameter PLw=1, - parameter PPSw=4, - parameter SW_LOC=0, - parameter SELF_LOOP_EN=0 + parameter SW_LOC=0 )( dest_port_out, dest_port_coded, @@ -1007,46 +919,53 @@ module regular_topo_destp_generator #( port_pre_sel, odd_column ); - localparam P_1 = (SELF_LOOP_EN )? P : P-1; + import pronoc_pkg::*; + localparam + P_1 = (SELF_LOOP_EN )? P : P-1, + Pw = log2(P); input [DSTPw-1 : 0] dest_port_coded; input [PLw-1 : 0] endp_localp_num; output [P_1-1 : 0] dest_port_out; - input swap_port_presel; + input swap_port_presel; input [PPSw-1 : 0] port_pre_sel; input odd_column; wire [P_1-1 : 0] dest_port_in; generate - /* verilator lint_off WIDTH */ - if (TOPOLOGY == "RING" || TOPOLOGY == "LINE" ) begin : one_D - /* verilator lint_on WIDTH */ + if (IS_1D_TOPO) begin : D1_ line_ring_destp_decoder #( - .ROUTE_TYPE(ROUTE_TYPE), .P(P), - .DSTPw(DSTPw), - .NL(NL), .ELw(PLw), - .PPSw(PPSw), - .SW_LOC(SW_LOC), - .SELF_LOOP_EN(SELF_LOOP_EN) + .SW_LOC(SW_LOC) ) decoder ( - .dest_port_coded(dest_port_coded), + .dest_port_coded(dest_port_coded), .dest_port_out(dest_port_in), - .endp_localp_num(endp_localp_num) + .endp_localp_num(endp_localp_num) + ); + end else if (IS_MESH_3D) begin : three_D + logic [P-1 : 0] mesh_3d_one_hot_dest_port; + logic [Pw-1 : 0] local_dest_port; + always @(*) begin + local_dest_port =Pw'(endp_localp_num) + Pw'(DOWN); + mesh_3d_one_hot_dest_port = {P{1'b0}}; + if(dest_port_coded == 0 && endp_localp_num!=0 && NL >1) mesh_3d_one_hot_dest_port[local_dest_port] = 1'b1; + else mesh_3d_one_hot_dest_port[dest_port_coded] = 1'b1; + end + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(P), + .SW_LOC(SW_LOC) + ) remove_sw_loc ( + .destport_in(mesh_3d_one_hot_dest_port[P-1 : 0]), + .destport_out(dest_port_out) ); - end else begin :two_D regular_topo_destp_decoder #( - .ROUTE_TYPE(ROUTE_TYPE), .P(P), - .DSTPw(DSTPw), - .NL(NL), .ELw(PLw), - .PPSw(PPSw), - .SW_LOC(SW_LOC), - .SELF_LOOP_EN(SELF_LOOP_EN) + .SW_LOC(SW_LOC) ) decoder ( .dest_port_coded(dest_port_coded), .dest_port_out(dest_port_in), @@ -1058,11 +977,8 @@ module regular_topo_destp_generator #( endgenerate regular_topo_mask_non_assignable_destport #( - .TOPOLOGY(TOPOLOGY), - .ROUTE_NAME(ROUTE_NAME), .SW_LOC(SW_LOC), - .P(P), - .SELF_LOOP_EN(SELF_LOOP_EN) + .P(P) ) mask_destport ( .dest_port_in(dest_port_in), .dest_port_out(dest_port_out), @@ -1071,14 +987,9 @@ module regular_topo_destp_generator #( endmodule module regular_topo_destp_decoder #( - parameter ROUTE_TYPE="DETERMINISTIC", parameter P=6, - parameter DSTPw=4, - parameter NL=2, parameter ELw=1, - parameter PPSw=4, - parameter SW_LOC=0, - parameter SELF_LOOP_EN=0 + parameter SW_LOC=0 )( dest_port_coded, endp_localp_num, @@ -1086,11 +997,12 @@ module regular_topo_destp_decoder #( swap_port_presel, port_pre_sel ); + import pronoc_pkg::*; localparam P_1 = (SELF_LOOP_EN )? P : P-1; input [DSTPw-1 : 0] dest_port_coded; input [ELw-1 : 0] endp_localp_num; output [P_1-1 : 0] dest_port_out; - input swap_port_presel; + input swap_port_presel; input [PPSw-1 : 0] port_pre_sel; logic [NL-1 : 0] endp_localp_onehot; @@ -1117,34 +1029,27 @@ module regular_topo_destp_decoder #( end generate if(NL==1) begin :slp - if(SELF_LOOP_EN == 0) begin :nslp - remove_sw_loc_one_hot #( - .P(5), - .SW_LOC(SW_LOC) - ) conv ( - .destport_in(portout), - .destport_out(dest_port_out) - ); - end else begin : slp - assign dest_port_out = portout; - end + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(5), + .SW_LOC(SW_LOC) + ) conv ( + .destport_in(portout), + .destport_out(dest_port_out) + ); end else begin :mlp wire [P-1 : 0] destport_onehot; - assign destport_onehot =(portout[0])? { endp_localp_onehot[NL-1 : 1] ,{(P-NL){1'b0}},endp_localp_onehot[0]}: /*select local destination*/ { {(NL-1){1'b0}} ,portout}; - if(SELF_LOOP_EN == 0) begin :nslp - remove_sw_loc_one_hot #( - .P(P), - .SW_LOC(SW_LOC) - ) remove_sw_loc ( - .destport_in(destport_onehot), - .destport_out(dest_port_out) - ); - end else begin: slp - assign dest_port_out = destport_onehot; - end + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(P), + .SW_LOC(SW_LOC) + ) remove_sw_loc ( + .destport_in(destport_onehot), + .destport_out(dest_port_out) + ); end endgenerate endmodule @@ -1154,19 +1059,15 @@ endmodule * line_ring_destp_decoder **************************/ module line_ring_destp_decoder #( - parameter ROUTE_TYPE="DETERMINISTIC", parameter P=4, - parameter DSTPw=2, - parameter NL=2, parameter ELw=1, - parameter PPSw=4, - parameter SW_LOC=0, - parameter SELF_LOOP_EN= 0 + parameter SW_LOC=0 )( dest_port_coded, endp_localp_num, dest_port_out ); + import pronoc_pkg::*; localparam P_1 = (SELF_LOOP_EN )? P : P-1; input [DSTPw-1 : 0] dest_port_coded; input [ELw-1 : 0] endp_localp_num; @@ -1186,34 +1087,27 @@ module line_ring_destp_decoder #( end generate if(NL==1) begin :_se - if(SELF_LOOP_EN == 0) begin :nslp - remove_sw_loc_one_hot #( - .P(3), - .SW_LOC(SW_LOC) - ) conv ( - .destport_in(portout), - .destport_out(dest_port_out) - ); - end else begin : slp - assign dest_port_out = portout; - end + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(3), + .SW_LOC(SW_LOC) + ) conv ( + .destport_in(portout), + .destport_out(dest_port_out) + ); end else begin :_me wire [P-1 : 0] destport_onehot; - assign destport_onehot =(portout[0])? { endp_localp_onehot[NL-1 : 1] ,{(P-NL){1'b0}},endp_localp_onehot[0]}: /*select local destination*/ { {(NL-1){1'b0}} ,portout}; - if(SELF_LOOP_EN == 0) begin :nslp - remove_sw_loc_one_hot #( - .P(P), - .SW_LOC(SW_LOC) - ) remove_sw_loc ( - .destport_in(destport_onehot), - .destport_out(dest_port_out) - ); - end else begin :slp - assign dest_port_out = destport_onehot; - end + destport_non_selfloop_fix #( + .SELF_LOOP_EN(SELF_LOOP_EN), + .P(P), + .SW_LOC(SW_LOC) + ) remove_sw_loc ( + .destport_in(destport_onehot), + .destport_out(dest_port_out) + ); end endgenerate endmodule @@ -1222,13 +1116,7 @@ endmodule * regular_topo_dynamic_portsel_control *****************/ module regular_topo_dynamic_portsel_control #( - parameter P = 5, - parameter ROUTE_TYPE = "FULL_ADAPTIVE", // "FULL_ADAPTIVE", "PAR_ADAPTIVE" - parameter V = 4, - parameter DSTPw=4, - parameter SSA_EN = 0, // 1: SSA enabled, 0: SSA disabled - parameter PPSw=4, - parameter [V-1 : 0] ESCAP_VC_MASK = 4'b1000 // mask scape vc, valid only for full adaptive + parameter P = 5 )( dest_port_coded_all, ivc_request_all, @@ -1243,15 +1131,12 @@ module regular_topo_dynamic_portsel_control #( reset, clk ); + import pronoc_pkg::*; localparam PV = V * P, PVV= PV * V, PVDSTPw = PV * DSTPw; - localparam LOCAL = 0, - EAST = 1, - NORTH = 2, - WEST = 3, - SOUTH = 4; + input [PVDSTPw-1 : 0] dest_port_coded_all; input [PV-1 : 0] ivc_request_all; input [PV-1 : 0] ovc_is_assigned_all; @@ -1262,11 +1147,11 @@ module regular_topo_dynamic_portsel_control #( output [PVDSTPw-1 : 0] destport_clear_all; input [PV-1 : 0] ivc_num_getting_ovc_grant; input [PV-1 : 0] ssa_ivc_num_getting_ovc_grant_all; - input reset,clk; + input reset,clk; - wire [PV-1 : 0] non_assigned_ovc_request_all; - wire [PV-1 : 0] y_evc_forbiden,x_evc_forbiden; - wire [PPSw-1 : 0] port_pre_sel_perport [P-1 : 0]; + wire [PV-1 : 0] non_assigned_ovc_request_all; + wire [PV-1 : 0] y_evc_forbiden,x_evc_forbiden; + wire [PPSw-1 : 0] port_pre_sel_perport [P-1 : 0]; assign non_assigned_ovc_request_all = ivc_request_all & ~ovc_is_assigned_all; assign port_pre_sel_perport[LOCAL] = port_pre_sel; assign port_pre_sel_perport[EAST] = {2'b00,port_pre_sel[1:0]}; @@ -1279,8 +1164,7 @@ module regular_topo_dynamic_portsel_control #( for(i=0;i< PV;i=i+1) begin : PV_ localparam SW_LOC = ((i/V)<5)? i/V : LOCAL; regular_topo_port_selector #( - .SW_LOC (SW_LOC), - .PPSw(PPSw) + .SW_LOC (SW_LOC) ) the_portsel ( .port_pre_sel (port_pre_sel_perport[SW_LOC]), .swap_port_presel (swap_port_presel[i]), @@ -1290,8 +1174,6 @@ module regular_topo_dynamic_portsel_control #( .x_evc_forbiden (x_evc_forbiden[i]) ); regular_topo_dspt_clear_gen #( - .SSA_EN(SSA_EN), - .DSTPw(DSTPw), .SW_LOC(SW_LOC) ) dspt_clear_gen( .destport_clear(destport_clear_all[((i+1)*DSTPw)-1 : i*DSTPw]), @@ -1304,8 +1186,6 @@ module regular_topo_dynamic_portsel_control #( /* verilator lint_on WIDTH */ assign avc_unavailable[i] = (masked_ovc_request_all [((i+1)*V)-1 : i*V] & ~ESCAP_VC_MASK) == {V{1'b0}}; regular_topo_swap_port_presel_gen #( - .V(V), - .ESCAP_VC_MASK(ESCAP_VC_MASK), .VC_NUM(i) ) the_swap_port_presel ( .avc_unavailable(avc_unavailable[i]), diff --git a/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv b/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv index 067b0db..60473e0 100644 --- a/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv +++ b/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv @@ -56,7 +56,7 @@ module regular_topo_noc_top ( genvar x,y,l; generate - if( IS_RING | IS_LINE) begin : D1_ + if( IS_1D_TOPO ) begin : D1_ for (x=0; x YY); /* verilator lint_on CMPCONST */ @@ -218,13 +212,10 @@ module multicast_routing_fmesh #( wire [NE-1 : 0] y_plus,y_min; //Only one-bit is asserted for each local_p[i] wire [NE-1 : 0] local_p [MAX_P_FMESH-1 : 0]; - regular_topo_router_addr_decode router_addr_decode - ( - .r_addr(current_r_addr), - .rx(current_rx), - .ry(current_ry), - .valid( ) - ); + regular_topo_router_addr_t current_router_addr_struct; + assign current_router_addr_struct = regular_topo_router_addr_t'(current_r_addr); + assign current_rx = current_router_addr_struct.x; + assign current_ry = current_router_addr_struct.y; wire [NX-1 : 0] row_has_any_dest; wire [NE-1 : 0] dest_mcast_all_endp; @@ -540,29 +531,45 @@ module multicast_dst_sel ( input [DSTPw-1 : 0] destport_in; output [DSTPw-1 : 0] destport_out; wire [DSTPw-1 : 0] arb_in, arb_out; + + function integer three_dim_topo_priority_order; + input integer x; + begin + case(x) + 0 : three_dim_topo_priority_order = DOWN; + 1 : three_dim_topo_priority_order = UP; + 2 : three_dim_topo_priority_order = EAST; + 3 : three_dim_topo_priority_order = WEST; + 4 : three_dim_topo_priority_order = NORTH; + 5 : three_dim_topo_priority_order = SOUTH; + 6 : three_dim_topo_priority_order = LOCAL; + default : three_dim_topo_priority_order =x; + endcase + end + endfunction // pririty_order - function integer regular_topo_pririty_order; + function integer two_dim_topo_priority_order; input integer x; begin case(x) - 0 : regular_topo_pririty_order = EAST; - 1 : regular_topo_pririty_order = WEST; - 2 : regular_topo_pririty_order = NORTH; - 3 : regular_topo_pririty_order = SOUTH; - 4 : regular_topo_pririty_order = LOCAL; - default : regular_topo_pririty_order =x; + 0 : two_dim_topo_priority_order = EAST; + 1 : two_dim_topo_priority_order = WEST; + 2 : two_dim_topo_priority_order = NORTH; + 3 : two_dim_topo_priority_order = SOUTH; + 4 : two_dim_topo_priority_order = LOCAL; + default : two_dim_topo_priority_order =x; endcase end endfunction // pririty_order - function integer ring_lin_pririty_order; + function integer one_dim_topo_priority_order; input integer x; begin case(x) - 0 : ring_lin_pririty_order = FORWARD; - 1 : ring_lin_pririty_order = BACKWARD; - 2 : ring_lin_pririty_order = LOCAL; - default : ring_lin_pririty_order =x; + 0 : one_dim_topo_priority_order = FORWARD; + 1 : one_dim_topo_priority_order = BACKWARD; + 2 : one_dim_topo_priority_order = LOCAL; + default : one_dim_topo_priority_order =x; endcase end endfunction // pririty_order @@ -571,8 +578,9 @@ module multicast_dst_sel ( generate for (i=0; i1)? flit.payload [CLASS_MSB : CLASS_LSB] : {Cw{1'b0}}; - hdr_flit.weight = (IS_WRRA)? flit.payload [WEIGHT_MSB : WEIGHT_LSB] : {WEIGHTw{1'b0}}; - hdr_flit.be = (BYTE_EN)? flit.payload [BE_MSB : BE_LSB]: {BEw{1'b0}}; - end - - wire [OFFSETw-1 : 0 ] offset = flit.payload [DATA_MSB : DATA_LSB]; - generate - if(Dw > OFFSETw) begin : if1 - assign data_o={{(Dw-OFFSETw){1'b0}},offset}; - end else begin : if2 - assign data_o=offset[Dw-1 : 0]; - end - endgenerate -endmodule - `ifdef SIMULATION module smart_chanel_check ( flit_chanel, @@ -367,10 +325,25 @@ module check_straight_oport #( import pronoc_pkg::*; input [DSTPw-1 : 0] destport_coded_i; output goes_straight_o; - + generate - if(IS_MESH | IS_TORUS | IS_FMESH) begin :twoD - if (SS_PORT_LOC == 0 || SS_PORT_LOC > 4) begin : local_ports + if(IS_3D_TOPO) begin : D3_ + if (SS_PORT_LOC == 0 || SS_PORT_LOC > DOWN) begin : local_ports + assign goes_straight_o = 1'b0; // There is not a next router in this case at all + end else begin :non_local + logic [MAX_P-1 : 0 ] destport_one_hot; + always @(*) begin + destport_one_hot = '0; + //for deterministic routing destination port is decimal encoded + if(IS_DETERMINISTIC) destport_one_hot[destport_coded_i] = 1'b1; + //for non-deterministic routing destination port is one-hot encoded + else destport_one_hot [DSTPw-1 : 0] = destport_coded_i; + end + assign goes_straight_o = destport_one_hot [SS_PORT_LOC]; + end//else + end//regular_topo + if(IS_2D_TOPO) begin : D2_ + if (SS_PORT_LOC == 0 || SS_PORT_LOC > SOUTH) begin : local_ports assign goes_straight_o = 1'b0; // There is not a next router in this case at all end else begin :non_local wire [4 : 0 ] destport_one_hot; @@ -378,12 +351,11 @@ module check_straight_oport #( .dstport_encoded(destport_coded_i), .dstport_one_hot(destport_one_hot) ); - assign goes_straight_o = destport_one_hot [SS_PORT_LOC]; end//else end//regular_topo - else if(IS_RING | IS_LINE) begin :oneD - if (SS_PORT_LOC == 0 || SS_PORT_LOC > 2) begin : local_ports + else if(IS_1D_TOPO) begin : D1_ + if (SS_PORT_LOC == 0 || SS_PORT_LOC > BACKWARD) begin : local_ports assign goes_straight_o = 1'b0; // There is not a next router in this case at all end else begin :non_local wire [2: 0 ] destport_one_hot; @@ -394,7 +366,6 @@ module check_straight_oport #( assign goes_straight_o = destport_one_hot [SS_PORT_LOC]; end //non_local end// oneD - //TODO Add fattree & custom endgenerate endmodule @@ -595,8 +566,8 @@ module smart_allocator_per_iport # ( wire goes_straight; localparam LOCATED_IN_NI = - (IS_RING | IS_LINE) ? (SW_LOC == 0 || SW_LOC > 2) : - (IS_MESH | IS_TORUS | IS_FMESH) ? (SW_LOC == 0 || SW_LOC > 4 ) : 0; + (IS_1D_TOPO) ? (SW_LOC == 0 || SW_LOC > 2) : + (IS_2D_TOPO) ? (SW_LOC == 0 || SW_LOC > 4 ) : 0; // does the route computation for the current router conventional_routing #( diff --git a/mpsoc/rtl/src_noc/router_top.sv b/mpsoc/rtl/src_noc/router_top.sv index 548e891..673c286 100644 --- a/mpsoc/rtl/src_noc/router_top.sv +++ b/mpsoc/rtl/src_noc/router_top.sv @@ -424,4 +424,11 @@ module router_top_v .reset(reset) ); + `ifdef SIMULATION + initial begin + if (current_r_addr==0) begin + display_noc_parameters(); + end + end + `endif endmodule diff --git a/mpsoc/rtl/src_noc/router_two_stage.sv b/mpsoc/rtl/src_noc/router_two_stage.sv index a56c270..6d71110 100644 --- a/mpsoc/rtl/src_noc/router_two_stage.sv +++ b/mpsoc/rtl/src_noc/router_two_stage.sv @@ -161,8 +161,12 @@ module router_two_stage #( wire [EAw-1 : 0] endp_addrs [NE_PER_R-1 : 0]; function automatic int get_enp_num(input int i); - if(IS_LINE | IS_RING | IS_MESH | IS_FMESH | IS_TORUS) begin - return (i > SOUTH) ? i - SOUTH : LOCAL; + if(IS_1D_TOPO) begin + return (i > BACKWARD) ? i - BACKWARD : LOCAL; + end else if(IS_2D_TOPO) begin + return (i > SOUTH) ? i - SOUTH : LOCAL; + end else if(IS_3D_TOPO) begin + return (i > DOWN) ? i - DOWN : LOCAL; end else if (IS_MULTI_MESH) begin return LOCAL; end else return 0; //TODO complete it for fattree and bin tree @@ -458,9 +462,6 @@ module router_two_stage #( generate if(DEBUG_EN & IS_MESH)begin :dbg debug_mesh_edges #( - .T1(T1), - .T2(T2), - .RAw(RAw), .P(P) ) debug_edges ( .clk(clk), diff --git a/mpsoc/rtl/src_noc/routing.sv b/mpsoc/rtl/src_noc/routing.sv index 0ea5f5d..e8332d1 100755 --- a/mpsoc/rtl/src_noc/routing.sv +++ b/mpsoc/rtl/src_noc/routing.sv @@ -47,47 +47,17 @@ module conventional_routing #( output [DSTPw-1 :0] destport; generate - if( IS_MESH | IS_FMESH | IS_TORUS | IS_RING | IS_LINE ) begin : regular_topo - localparam - RXw = log2(NX), - RYw = (IS_RING | IS_LINE) ? 1 :log2(NY), - EXw = RXw, - EYw =(IS_RING | IS_LINE) ? 1 : RYw; - wire [RXw-1 : 0] current_rx; - wire [RYw-1 : 0] current_ry; - wire [EXw-1 : 0] dest_ex; - wire [EYw-1 : 0] dest_ey; - - regular_topo_router_addr_decode router_addr_decode ( - .r_addr(current_r_addr), - .rx(current_rx), - .ry(current_ry), - .valid( ) - ); - if( IS_FMESH) begin :fmesh - fmesh_endp_addr_decode end_addr_decode ( - .e_addr(dest_e_addr), - .ex(dest_ex), - .ey(dest_ey), - .ep( ), - .valid() - ); - end else begin : mesh - regular_topo_endp_addr_decode end_addr_decode ( - .e_addr(dest_e_addr), - .ex(dest_ex), - .ey(dest_ey), - .el( ), - .valid() - ); - end//mesh + if( IS_REGULAR_TOPO | IS_FMESH ) begin : regular_topo + regular_topo_router_addr_t dest_router_addr, current_router_addr; + always @(*) begin + dest_router_addr = regular_topo_router_addr_t'(dest_e_addr); + current_router_addr = regular_topo_router_addr_t'(current_r_addr); + end regular_topo_conventional_routing #( .LOCATED_IN_NI(LOCATED_IN_NI) ) the_conventional_routing ( - .current_x(current_rx), - .current_y(current_ry), - .dest_x(dest_ex), - .dest_y(dest_ey), + .current_router_addr_i(current_router_addr), + .dest_router_addr_i(dest_router_addr), .destport(destport) ); end else if(IS_FATTREE | IS_TREE ) begin : ftree @@ -184,48 +154,23 @@ module look_ahead_routing #( input [DSTPw-1 : 0] destport_encoded; output [DSTPw-1 : 0] lkdestport_encoded; input reset,clk; + localparam PP = ( IS_MESH | IS_FMESH | IS_TORUS ) ? 5 : (IS_MESH_3D) ? 7 : 3; + logic [RAw-1 : 0] neighbors_r_addr_array [PP-1 : 0]; genvar i; generate + for (i=0;i SOUTH) ) : - (IS_RING | IS_LINE) ? ((SW_LOC==LOCAL) || (SW_LOC > BACKWARD) ) : 0; + (IS_3D_TOPO)? ((SW_LOC==LOCAL) || (SW_LOC > DOWN) ) : + (IS_2D_TOPO)? ((SW_LOC==LOCAL) || (SW_LOC > SOUTH) ) : + (IS_1D_TOPO) ? ((SW_LOC==LOCAL) || (SW_LOC > BACKWARD) ) : 0; hdr_flit_t hdr_flit_i; wire [DSTPw-1 :0] destport; header_flit_info #( diff --git a/mpsoc/rtl/src_noc/ss_allocator.sv b/mpsoc/rtl/src_noc/ss_allocator.sv index 8b090e5..924d2fd 100755 --- a/mpsoc/rtl/src_noc/ss_allocator.sv +++ b/mpsoc/rtl/src_noc/ss_allocator.sv @@ -282,7 +282,6 @@ module ssa_per_vc #( ssa_check_destport #( .SW_LOC(SW_LOC), - .P(P), .SS_PORT(SS_PORT) ) check_destport ( .destport_encoded(destport_encoded), @@ -335,7 +334,6 @@ endmodule module ssa_check_destport #( parameter SW_LOC = 0, - parameter P=5, parameter SS_PORT=0 ) ( destport_encoded, //non header flit dest port @@ -370,13 +368,9 @@ module ssa_check_destport #( .ss_port_hdr_flit(ss_port_hdr_flit), .ss_port_nonhdr_flit(ss_port_nonhdr_flit) ); - end else if (IS_MESH | IS_TORUS ) begin : mesh - regular_topo_ssa_check_destport #( - .ROUTE_TYPE(ROUTE_TYPE), + end else if (IS_MESH | IS_TORUS ) begin : D2_ + two_dim_ssa_check_destport #( .SW_LOC(SW_LOC), - .P(P), - .DEBUG_EN(DEBUG_EN), - .DSTPw(DSTPw), .SS_PORT(SS_PORT) ) destport_check ( .destport_encoded(destport_encoded), @@ -392,21 +386,13 @@ module ssa_check_destport #( end else if (IS_FMESH) begin :fmesh localparam ELw = log2(T3), - Pw = log2(P); + Pw = log2(MAX_P); wire [Pw-1 : 0] endp_p_in; wire [MAX_P-1 : 0] destport_one_hot_in; - - fmesh_endp_addr_decode endp_addr_decode ( - .e_addr(dest_e_addr_in), - .ex(), - .ey(), - .ep(endp_p_in), - .valid() - ); - + assign endp_p_in = dest_e_addr_in[DAw-1 : DAw-Pw]; destp_generator #( - .P(P), + .P(MAX_P), .SW_LOC(SW_LOC) ) decoder ( .destport_one_hot (destport_one_hot_in), @@ -419,13 +405,9 @@ module ssa_check_destport #( ); assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT]; assign ss_port_hdr_flit = destport_one_hot_in [SS_PORT]; - end else begin : line - line_ring_ssa_check_destport #( - .ROUTE_TYPE(ROUTE_TYPE), + end else if(IS_LINE | IS_RING) begin : D1_ + one_dim_ssa_check_destport #( .SW_LOC(SW_LOC), - .P(P), - .DEBUG_EN(DEBUG_EN), - .DSTPw(DSTPw), .SS_PORT(SS_PORT) ) destport_check ( .destport_encoded(destport_encoded), @@ -433,6 +415,17 @@ module ssa_check_destport #( .ss_port_hdr_flit(ss_port_hdr_flit), .ss_port_nonhdr_flit(ss_port_nonhdr_flit) ); + end else begin : other + logic [MAX_P-1 : 0] destport_one_hot_in; + always @(*) begin + destport_one_hot_in = '0; + //for deterministic routing destination port is decimal encoded + if(IS_DETERMINISTIC) destport_one_hot_in[destport_in_encoded] = 1'b1; + //for non-deterministic routing destination port is one-hot encoded + else destport_one_hot_in [DSTPw-1 : 0] = destport_in_encoded; + end + assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT]; + assign ss_port_hdr_flit = destport_one_hot_in [SS_PORT]; end endgenerate endmodule diff --git a/mpsoc/rtl/src_noc/topology_localparam.v b/mpsoc/rtl/src_noc/topology_localparam.v index c16f8f5..6b03106 100644 --- a/mpsoc/rtl/src_noc/topology_localparam.v +++ b/mpsoc/rtl/src_noc/topology_localparam.v @@ -19,7 +19,11 @@ IS_TREE= (TOPOLOGY == "TREE"), IS_STAR= (TOPOLOGY == "STAR"), IS_MULTI_MESH=(TOPOLOGY == "MULTI_MESH"), - IS_REGULAR_TOPO = (IS_RING | IS_LINE | IS_MESH | IS_TORUS), + IS_MESH_3D= (TOPOLOGY == "MESH_3D"), + IS_REGULAR_TOPO = (IS_RING | IS_LINE | IS_MESH | IS_TORUS | IS_MESH_3D), + IS_1D_TOPO = (IS_LINE | IS_RING), + IS_2D_TOPO = (IS_MESH | IS_TORUS | IS_FMESH), + IS_3D_TOPO = (IS_MESH_3D | IS_MULTI_MESH), IS_MULTI_ENDP_ROUTER = (T3 > 1) ; /* verilator lint_on WIDTH */ @@ -96,16 +100,16 @@ input integer router_port_num; //router port num input integer current_port; begin - if(IS_MESH | IS_FMESH | IS_TORUS | IS_MULTI_MESH) begin + if(IS_2D_TOPO | IS_3D_TOPO) begin strieght_port = (current_port == EAST)? WEST: (current_port == WEST)? EAST: (current_port == SOUTH)? NORTH: (current_port == NORTH)? SOUTH: - (IS_MULTI_MESH && current_port== UP)? DOWN: - (IS_MULTI_MESH && current_port== DOWN)? UP: + (IS_3D_TOPO && current_port== UP)? DOWN: + (IS_3D_TOPO && current_port== DOWN)? UP: router_port_num; //DISABLED; - end else if (IS_RING | IS_LINE) begin + end else if (IS_1D_TOPO) begin strieght_port = (current_port== FORWARD )? BACKWARD: (current_port== BACKWARD)? FORWARD: @@ -131,38 +135,42 @@ input integer router_port_num; //router port num begin port_buffer_size = B; - if(IS_MESH || IS_FMESH || IS_TORUS || IS_RING || IS_LINE)begin - if (router_port_num == 0 || router_port_num > 4 ) port_buffer_size = LB; - end else if (IS_MULTI_MESH) begin - if (router_port_num == 0) port_buffer_size = LB; + if(IS_1D_TOPO) begin + if (router_port_num == 0 || router_port_num > BACKWARD ) port_buffer_size = LB; + end else if (IS_2D_TOPO) begin + if (router_port_num == 0 || router_port_num > SOUTH ) port_buffer_size = LB; + end else if (IS_3D_TOPO) begin + if (router_port_num == 0 || router_port_num > DOWN) port_buffer_size = LB; end end endfunction /******************* - * REGULAR_TOPO: "RING" "LINE" "MESH" TORUS" "FMESH" + * REGULAR_TOPO: "RING" "LINE" "MESH" TORUS" "FMESH" "MESH_3D" ******************/ localparam NX = T1, - NY = (IS_RING | IS_LINE) ? 1 : T2, - NL = T3, + NY = (IS_1D_TOPO) ? 1 : T2, + NL = (IS_3D_TOPO)? T4 : T3, + NZ = (IS_3D_TOPO)? T3 : 1, NXw = log2(NX), NYw = log2(NY), NLw = log2(NL), + NZw= log2(NZ), PPSw_REGULAR = 4, //port presel width for adaptive routing /* verilator lint_off WIDTH */ ROUTE_TYPE_REGULAR = - (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" )? "DETERMINISTIC" : + (ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR" )? "DETERMINISTIC" : (ROUTE_NAME == "FULL_ADPT" || ROUTE_NAME == "TRANC_FULL_ADPT" )? "FULL_ADAPTIVE": "PAR_ADAPTIVE", /* verilator lint_on WIDTH */ - R2R_CHANELS_REGULAR= (IS_RING || IS_LINE)? 2 : 4, + R2R_CHANELS_REGULAR= (IS_1D_TOPO)? 2 : (IS_3D_TOPO)? 6 : 4, R2E_CHANELS_REGULAR= NL, - RAw_REGULAR = ( IS_RING | IS_LINE)? NXw : NXw + NYw, - EAw_REGULAR = (NL==1) ? RAw_REGULAR : RAw_REGULAR + NLw, - NR_REGULAR = (IS_RING || IS_LINE)? NX : NX*NY, + RAw_REGULAR = ( IS_1D_TOPO )? NXw : (IS_3D_TOPO)? NXw + NYw + NZw : NXw + NYw, + EAw_REGULAR = (NL==1 ) ? RAw_REGULAR : RAw_REGULAR + NLw, + NR_REGULAR = (IS_1D_TOPO)? NX :(IS_3D_TOPO)? NX*NY*NZ : NX*NY, NE_REGULAR = NR_REGULAR * NL, MAX_P_REGULAR = R2R_CHANELS_REGULAR + R2E_CHANELS_REGULAR, - DSTPw_REGULAR = R2R_CHANELS_REGULAR, // P-1 + DSTPw_REGULAR = (IS_3D_TOPO)? log2(MAX_P_REGULAR) : R2R_CHANELS_REGULAR, // P-1 NE_PER_R_REGULAR = NL; /**************** @@ -213,7 +221,7 @@ localparam ROUTE_TYPE_STAR = "DETERMINISTIC", NE_STAR = T1, //total number of endpoints - NR_STAR = 1, // total number of routers + NR_STAR = 1, // total number of routers RAw_STAR = 1, EAw_STAR = log2(NE_STAR), DSTPw_STAR = (~IS_UNICAST) ? NE_STAR :EAw_STAR, @@ -244,6 +252,20 @@ EAw_MULTI_MESH = T2, MAX_P_MULTI_MESH = 7, DSTPw_MULTI_MESH = log2(MAX_P_MULTI_MESH); + /************************* + * regular_topo address struct + **************************/ + typedef struct packed { + logic [NZw-1 : 0] z; + logic [NYw-1 : 0] y; + logic [NXw-1 : 0] x; + } regular_topo_router_addr_t; + typedef struct packed { + logic [NLw-1 : 0] l; + logic [NZw-1 : 0] z; + logic [NYw-1 : 0] y; + logic [NXw-1 : 0] x; + } regular_topo_endp_addr_t; localparam PPSw = PPSw_REGULAR, @@ -390,12 +412,17 @@ function automatic integer regular_topo_endp_addr; input integer endp_id; - integer y, x, l,p, diff,mul; + integer y, x, z, l,rid; begin - y = ((endp_id/NL) / NX ); - x = ((endp_id/NL) % NX ); - l = (endp_id % NL); - regular_topo_endp_addr = ( l << ( NXw+NYw) | (y<> parameter.v printf " parameter MAX_PCK_SIZ=$MAX_PCK_SIZ;\n" >> parameter.v printf " parameter TIMSTMP_FIFO_NUM=$TIMSTMP_FIFO_NUM;\n" >> parameter.v - printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )? \"DETERMINISTIC\" : \n" >> parameter.v + printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"DOR\" || ROUTE_NAME == \"TRANC_DOR\" )? \"DETERMINISTIC\" : \n" >> parameter.v printf " (ROUTE_NAME == \"FULL_ADPT\" || ROUTE_NAME == \"TRANC_FULL_ADPT\" )? \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v printf " parameter DEBUG_EN=$DEBUG_EN;\n" >> parameter.v printf " parameter ROUTE_SUBFUNC= \"$ROUTE_SUBFUNC\";\n">> parameter.v diff --git a/mpsoc/script/synfull/noc_localparam.v b/mpsoc/script/synfull/noc_localparam.v index 09a939c..feff061 100644 --- a/mpsoc/script/synfull/noc_localparam.v +++ b/mpsoc/script/synfull/noc_localparam.v @@ -38,7 +38,7 @@ localparam B=4; localparam LB=4; localparam Fpay=64; - localparam ROUTE_NAME="XY"; + localparam ROUTE_NAME="DOR"; localparam PCK_TYPE="MULTI_FLIT"; localparam MIN_PCK_SIZE=1; localparam BYTE_EN=0; diff --git a/mpsoc/script/verilator_2D_mesh.sh b/mpsoc/script/verilator_2D_mesh.sh index 4a1d247..a4cf231 100755 --- a/mpsoc/script/verilator_2D_mesh.sh +++ b/mpsoc/script/verilator_2D_mesh.sh @@ -42,8 +42,8 @@ CORE_NUM(){ FIRST_ARBITER_EXT_P_EN=1 TOPOLOGY="MESH" #"MESH" or "TORUS" ROUTE_NAME="FULL_ADPT" # Routing algorithm - # mesh : "XY" , "WEST_FIRST" , "NORTH_LAST" , "NEGETIVE_FIRST" , "FULL_ADPT" - # torus: "TRANC_XY" , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_FULL_ADPT" + # mesh : "DOR" , "WEST_FIRST" , "NORTH_LAST" , "NEGETIVE_FIRST" , "FULL_ADPT" + # torus: "TRANC_DOR" , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_FULL_ADPT" CONGESTION_INDEX="VC" #"CREDIT","VC" CLASS_SETTING="4'b1111" #0: no class. packets can be sent to any available OVC @@ -81,7 +81,7 @@ CORE_NUM(){ # for minimal fully adaptive on 2D mesh paper - ROUTING_SUBFUNCTION= "XY" # "XY" "NORTH_LAST" + ROUTING_SUBFUNCTION= "DOR" # "DOR" "NORTH_LAST" AVC_REALLOCATION= "" generate_parameter_v (){ @@ -112,7 +112,7 @@ generate_parameter_v (){ printf " parameter TOTAL_PKT_PER_ROUTER=$TOTAL_PKT_PER_ROUTER;\n" >> parameter.v printf " parameter MAX_DELAY_BTWN_PCKTS=$MAX_DELAY_BTWN_PCKTS;\n" >> parameter.v printf " parameter DEBUG_EN=$DEBUG_EN;\n" >> parameter.v - printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )? \"DETERMINISTIC\" : \n" >> parameter.v + printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"DOR\" || ROUTE_NAME == \"TRANC_DOR\" )? \"DETERMINISTIC\" : \n" >> parameter.v printf " (ROUTE_NAME == \"FULL_ADPT\" || ROUTE_NAME == \"TRANC_FULL_ADPT\" )? \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v printf " parameter ADD_PIPREG_AFTER_CROSSBAR= $ADD_PIPREG_AFTER_CROSSBAR;\n" >> parameter.v printf " parameter CVw=(C==0)? V : C * V;\n" >> parameter.v @@ -168,7 +168,7 @@ for PACKET_SIZE in 3 2 4 6 for TRAFFIC in "RANDOM" "TRANSPOSE1" "TRANSPOSE2" "HOTSPOT" do - for ROUTE_NAME in "XY" "WEST_FIRST" "NORTH_LAST" "NEGETIVE_FIRST" "FULL_ADPT" + for ROUTE_NAME in "DOR" "WEST_FIRST" "NORTH_LAST" "NEGETIVE_FIRST" "FULL_ADPT" do # regenerate NoC generate_parameter_v @@ -190,7 +190,7 @@ for PACKET_SIZE in 3 2 4 6 #run multiple testbench files in the same time cd $multiple_path - for ROUTE_NAME in "XY" "WEST_FIRST" "NORTH_LAST" "NEGETIVE_FIRST" "FULL_ADPT" + for ROUTE_NAME in "DOR" "WEST_FIRST" "NORTH_LAST" "NEGETIVE_FIRST" "FULL_ADPT" do ./$ROUTE_NAME$TRAFFIC"_"$PACKET_SIZE $ROUTE_NAME$TRAFFIC"_"$PACKET_SIZE & @@ -200,7 +200,7 @@ for PACKET_SIZE in 3 2 4 6 wait # merge the result in one file - for ROUTE_NAME in "XY" "WEST_FIRST" "NORTH_LAST" "NEGETIVE_FIRST" "FULL_ADPT" + for ROUTE_NAME in "DOR" "WEST_FIRST" "NORTH_LAST" "NEGETIVE_FIRST" "FULL_ADPT" do data_file=$data_path/$TRAFFIC"_"$PACKET_SIZE"_all.txt" plot_file=$plot_path/$TRAFFIC"_"$PACKET_SIZE".eps" diff --git a/mpsoc/smart-netrace/models/B4_V1_S0 b/mpsoc/smart-netrace/models/B4_V1_S0 index 3b9e23c..6f9937f 100644 --- a/mpsoc/smart-netrace/models/B4_V1_S0 +++ b/mpsoc/smart-netrace/models/B4_V1_S0 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ADD_PIPREG_AFTER_CROSSBAR" => "1'b1", "V" => "1", "B" => "4", diff --git a/mpsoc/smart-netrace/models/B4_V1_S2 b/mpsoc/smart-netrace/models/B4_V1_S2 index 893796d..94c23d7 100644 --- a/mpsoc/smart-netrace/models/B4_V1_S2 +++ b/mpsoc/smart-netrace/models/B4_V1_S2 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ADD_PIPREG_AFTER_CROSSBAR" => "1'b1", "V" => "1", "B" => "4", diff --git a/mpsoc/smart-netrace/models/B4_V1_S4 b/mpsoc/smart-netrace/models/B4_V1_S4 index 87959c4..8bcb6e2 100644 --- a/mpsoc/smart-netrace/models/B4_V1_S4 +++ b/mpsoc/smart-netrace/models/B4_V1_S4 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ADD_PIPREG_AFTER_CROSSBAR" => "1'b1", "V" => "1", "B" => "4", diff --git a/mpsoc/smart-netrace/models/B4_V1_S7 b/mpsoc/smart-netrace/models/B4_V1_S7 index c624e39..936f5e9 100644 --- a/mpsoc/smart-netrace/models/B4_V1_S7 +++ b/mpsoc/smart-netrace/models/B4_V1_S7 @@ -1,6 +1,6 @@ $model = bless( { 'noc_param'=> { - "ROUTE_NAME" => "\"XY\"", + "ROUTE_NAME" => "\"DOR\"", "ADD_PIPREG_AFTER_CROSSBAR" => "1'b1", "V" => "1", "B" => "4", diff --git a/mpsoc/smart-netrace/src/deafult_noc_param b/mpsoc/smart-netrace/src/deafult_noc_param index 1affbb5..4c3b565 100644 --- a/mpsoc/smart-netrace/src/deafult_noc_param +++ b/mpsoc/smart-netrace/src/deafult_noc_param @@ -8,7 +8,7 @@ $model = bless( { "B" => "4", "LB" => "B", "Fpay" => "32", -"ROUTE_NAME" => "\"XY\"", +"ROUTE_NAME" => "\"DOR\"", "PCK_TYPE" => " \"MULTI_FLIT\"", "MIN_PCK_SIZE" => "2", "BYTE_EN" => "0", diff --git a/mpsoc/src_c/plot/parameter.v b/mpsoc/src_c/plot/parameter.v index aa4c112..66b4001 100755 --- a/mpsoc/src_c/plot/parameter.v +++ b/mpsoc/src_c/plot/parameter.v @@ -12,7 +12,7 @@ parameter COMBINATION_TYPE="BASELINE"; parameter FIRST_ARBITER_EXT_P_EN=0; parameter TOPOLOGY="MESH"; - parameter ROUTE_NAME="XY"; + parameter ROUTE_NAME="DOR"; parameter CONGESTION_INDEX=3; parameter CLASS_CONFIG_NUM=0; parameter C0_p=100; @@ -32,7 +32,7 @@ parameter MAX_PCK_SIZ=10; parameter TIMSTMP_FIFO_NUM=64; parameter [V-1 : 0] ESCAP_VC_MASK=1; - parameter ROUTE_TYPE = (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" || ROUTE_NAME == "TRANC")? "DETERMINISTIC" : + parameter ROUTE_TYPE = (ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR" || ROUTE_NAME == "TRANC")? "DETERMINISTIC" : (ROUTE_NAME == "FULL_ADPT" || ROUTE_NAME == "TRANC_FULL_ADPT" )? "FULL_ADAPTIVE": "PAR_ADAPTIVE"; parameter DEBUG_EN=0; parameter ROUTE_SUBFUNC= "NORTH_LAST"; diff --git a/mpsoc/src_verilator/simulator.cpp b/mpsoc/src_verilator/simulator.cpp index 1be9cb2..f773427 100755 --- a/mpsoc/src_verilator/simulator.cpp +++ b/mpsoc/src_verilator/simulator.cpp @@ -52,7 +52,7 @@ int main(int argc, char** argv) { mcast_init(); topology_init(); - + if( TRAFFIC_TYPE == NETRACE){ netrace_init(netrace_file); // should be called first to initiate header pck_inj_init((int)header->num_nodes); @@ -64,10 +64,9 @@ int main(int argc, char** argv) { else traffic_gen_init(); main_time=0; - print_parameter(); if( thread_num>1) initial_threads(); - while (!Verilated::gotFinish()) { + if(main_time == 1) print_parameter(); if(main_time - saved_time < 50) {//set reset and start #ifdef FLAT_MODE reset_active_high = ((noc_top->router_event[0][0] & ACTIVE_HIGH_RST)!=0) ? 1 : 0; @@ -371,8 +370,7 @@ int parse_string ( char * str, int * array) unsigned int pck_dst_gen_unicast ( unsigned int core_num, unsigned char * inject_en) { if(TRAFFIC_TYPE==TASK) return pck_dst_gen_task_graph ( core_num, inject_en); - if((strcmp (TOPOLOGY,"MESH")==0)||(strcmp (TOPOLOGY,"TORUS")==0)) return pck_dst_gen_2D (core_num, inject_en); - return pck_dst_gen_1D (core_num, inject_en); + return pck_dst_gen_synthetic (core_num, inject_en); } void mcast_full_rnd (unsigned int core_num){ @@ -645,7 +643,7 @@ void traffic_gen_init( void ){ unsigned int dest_e_addr; for (i=0;icurrent_e_addr = endp_addr_encoder(i); traffic[i]->start=0; traffic[i]->pck_class_in= pck_class_in_gen( i); @@ -1232,45 +1230,6 @@ void print_statistic_new (unsigned long int total_clk){ } void print_parameter (){ - printf ("NoC parameters:---------------- \n"); - printf ("\tTopology: %s\n",TOPOLOGY); - printf ("\tRouting algorithm: %s\n",ROUTE_NAME); - printf ("\tVC_per port: %d\n", V); - printf ("\tNon-local port buffer_width per VC: %d\n", B); - printf ("\tLocal port buffer_width per VC: %d\n", LB); - #if defined (IS_MESH) || defined (IS_FMESH) || defined (IS_TORUS) - printf ("\tRouter num in row: %d \n",T1); - printf ("\tRouter num in column: %d \n",T2); - printf ("\tEndpoint num per router: %d\n",T3); - #elif defined (IS_LINE) || defined (IS_RING ) - printf ("\tTotal Router num: %d \n",T1); - printf ("\tEndpoint num per router: %d\n",T3); - #elif defined (IS_FATTREE) || defined (IS_TREE) - printf ("\tK: %d \n",T1); - printf ("\tL: %d \n",T2); - #elif defined (IS_STAR) - printf ("\tTotal Endpoints number: %d \n",T1); - #else//CUSTOM - printf ("\tTotal Endpoints number: %d \n",T1); - printf ("\tTotal Routers number: %d \n",T2); - #endif - printf ("\tNumber of Class: %d\n", C); - printf ("\tFlit data width: %d \n", Fpay); - printf ("\tVC reallocation mechanism: %s \n", VC_REALLOCATION_TYPE); - printf ("\tVC/sw combination mechanism: %s \n", COMBINATION_TYPE); - printf ("\tAVC_ATOMIC_EN:%d \n", AVC_ATOMIC_EN); - printf ("\tCongestion Index:%d \n",CONGESTION_INDEX); - printf ("\tADD_PIPREG_AFTER_CROSSBAR:%d\n",ADD_PIPREG_AFTER_CROSSBAR); - printf ("\tSSA_EN enabled: %d \n",SSA_EN); - printf ("\tSwitch allocator arbitration type:%s \n",SWA_ARBITER_TYPE); - printf ("\tMinimum supported packet size:%d flit(s) \n",MIN_PCK_SIZE); - printf ("\tLoop back is enabled:%d \n",SELF_LOOP_EN); - printf ("\tNumber of multihop bypass (SMART max):%d \n",SMART_MAX); - printf ("\tCastying type:%s.\n",CAST_TYPE); - if (IS_MCAST_PARTIAL){ - printf ("\tCAST LIST:%s\n",MCAST_ENDP_LIST); - } - printf ("NoC parameters:---------------- \n"); printf ("\nSimulation parameters-------------\n"); #if(DEBUG_EN) printf ("\tDebuging is enabled\n"); diff --git a/mpsoc/src_verilator/topology/mesh.h b/mpsoc/src_verilator/topology/mesh.h index f64b633..5f9ba85 100644 --- a/mpsoc/src_verilator/topology/mesh.h +++ b/mpsoc/src_verilator/topology/mesh.h @@ -1,491 +1,294 @@ #ifndef MESH_H - #define MESH_H - - #define LOCAL 0 - #define EAST 1 - #define NORTH 2 - #define WEST 3 - #define SOUTH 4 - //ring line - #define FORWARD 1 - #define BACKWARD 2 - #define router_id(x,y) ((y * T1) + x) - #define endp_id(x,y,l) ((y * T1) + x) * T3 + l +#define MESH_H - unsigned int nxw=0; - unsigned int nyw=0; - unsigned int maskx=0; - unsigned int masky=0; +#define LOCAL 0 +#define EAST 1 +#define NORTH 2 +#define SOUTH 4 +//ring line +#define FORWARD 1 +#define BACKWARD 2 - void mesh_tori_addrencod_sep(unsigned int id, unsigned int *x, unsigned int *y, unsigned int *l){ - (*l)=id%T3; // id%NL - (*x)=(id/T3)%T1;// (id/NL)%NX - (*y)=(id/T3)/T1;// (id/NL)/NX - } +#define UP 5 +#define DOWN 6 - void mesh_tori_addr_sep(unsigned int code, unsigned int *x, unsigned int *y, unsigned int *l){ - (*x) = code & maskx; - code>>=nxw; - (*y) = code & masky; - code>>=nyw; - (*l) = code; - } +#if defined (IS_LINE) || defined (IS_RING ) + #define X_MAX T1 + #define Y_MAX 1 + #define Z_MAX 1 + #define L_MAX T3 + #define DIM 1 +#elif defined (IS_MESH_3D) + #define X_MAX T1 + #define Y_MAX T2 + #define Z_MAX T3 + #define L_MAX T4 + #define DIM 3 +#elif defined (IS_TORUS) || defined (IS_MESH) || defined (IS_FMESH) + #define X_MAX T1 + #define Y_MAX T2 + #define Z_MAX 1 + #define L_MAX T3 + #define DIM 2 +#endif - void ring_line_addr_sep(unsigned int code, unsigned int *x, unsigned int *l){ - (*x) = code & maskx; - code>>=nxw; - (*l) = code; - } +#if defined (IS_LINE) || defined (IS_RING ) + #define WEST BACKWARD + #define R2R_CHANELS_MESH_TORI 2 +#else + #define WEST 3 + #if defined (IS_MESH_3D) + #define R2R_CHANELS_MESH_TORI 6 + #else + #define R2R_CHANELS_MESH_TORI 4 + #endif //IS_MESH_3D +#endif - unsigned int mesh_tori_addr_join(unsigned int x, unsigned int y, unsigned int l){ - unsigned int addrencode=0; - addrencode =(T3==1)? (y< SOUTH) return l; + if(x==0 && l == WEST) return l; + if(x== (T1-1) && l == EAST) return l; + if(y==0 && l == NORTH) return l; + if(y== (T2-1) && l == SOUTH) return l; + if(x==0) return WEST; + if(x== (T1-1)) return EAST; + if(y==0) return NORTH; + if(y== (T2-1)) return SOUTH; + return LOCAL; +} - void fmesh_addrencod_sep(unsigned int id, unsigned int *x, unsigned int *y, unsigned int *p){ - unsigned int l, diff,mul,addrencode; - mul = T1*T2*T3; - if(id < mul) { - *y = ((id/T3) / T1 ); - *x = ((id/T3) % T1 ); - l = (id % T3); - *p = (l==0)? LOCAL : 4+l; - }else{ - diff = id - mul ; - if( diff < T1) { //top mesh edge - *y = 0; - *x = diff; - *p = NORTH; - } else if ( diff < 2* T1) { //bottom mesh edge - *y = T2-1; - *x = diff-T1; - *p = SOUTH; - } else if ( diff < (2* T1) + T2 ) { //left mesh edge - *y = diff - (2* T1); - *x = 0; - *p = WEST; - } else { //right mesh edge - *y = diff - (2* T1) -T2; - *x = T1-1; - *p = EAST; - } +void fmesh_Eid_to_coords(unsigned int id, unsigned int *x, unsigned int *y, unsigned int *p){ + unsigned int l, diff,mul,addrencode; + mul = T1*T2*T3; + if(id < mul) { + *y = ((id/T3) / T1 ); + *x = ((id/T3) % T1 ); + l = (id % T3); + *p = (l==0)? LOCAL : 4+l; + }else{ + diff = id - mul ; + if( diff < T1) { //top mesh edge + *y = 0; + *x = diff; + *p = NORTH; + } else if ( diff < 2* T1) { //bottom mesh edge + *y = T2-1; + *x = diff-T1; + *p = SOUTH; + } else if ( diff < (2* T1) + T2 ) { //left mesh edge + *y = diff - (2* T1); + *x = 0; + *p = WEST; + } else { //right mesh edge + *y = diff - (2* T1) -T2; + *x = T1-1; + *p = EAST; } } +} - unsigned int fmesh_addrencode(unsigned int id){ - //input integer in,nx,nxw,nl,nyw,ny; - unsigned int y, x, p, addrencode; - fmesh_addrencod_sep(id, &x, &y, &p); - addrencode = ( p<<(nxw+nyw) | (y< SOUTH) return ((y*T1)+x)*T3+(p-SOUTH); - if(p== NORTH) return ((T1*T2*T3) + x); - if(p== SOUTH) return ((T1*T2*T3) + T1 + x); - if(p== WEST ) return ((T1*T2*T3) + 2*T1 + y); - if(p== EAST ) return ((T1*T2*T3) + 2*T1 + T2 + y); - return 0;//should not reach here +unsigned int regular_topo_coords_to_Eaddr(unsigned int x, unsigned int y, unsigned int z, unsigned int l){ + unsigned int code=x; + unsigned int shift =nxw; + if(DIM > 1) { + code|=y< 2) { + code|=z<>=nxw; + if(DIM > 1) { + (*y) = code & masky; + code>>=nyw; + } else (*y)=0; + if(DIM > 2) { + (*z) = code & maskz; + code>>=nzw; + } else (*z)=0; + (*l) = code; +} + +unsigned int reqular_topo_addr_encode (unsigned int id){ + unsigned int y, x, z, l; + regular_topo_Eid_to_coords(id,&x,&y,&z,&l); + return regular_topo_coords_to_Eaddr(x,y,z,l); +} + +unsigned int regular_topo_addr_decoder (unsigned int code){ + unsigned int y, x, z, l; + regular_topo_Eaddr_to_coords(code,&x,&y,&z,&l); + return endp_id(x,y,z,l); +} + +unsigned int fmesh_endp_addr_decoder (unsigned int code){ + unsigned int x, y, z, p; + regular_topo_Eaddr_to_coords(code,&x,&y,&z,&p); + if(p== LOCAL) return ((y*T1)+x)*T3; + if(p > SOUTH) return ((y*T1)+x)*T3+(p-SOUTH); + if(p== NORTH) return ((T1*T2*T3) + x); + if(p== SOUTH) return ((T1*T2*T3) + T1 + x); + if(p== WEST ) return ((T1*T2*T3) + 2*T1 + y); + if(p== EAST ) return ((T1*T2*T3) + 2*T1 + T2 + y); + return 0;//should not reach here +} + +unsigned int fmesh_addrencode(unsigned int id){ + unsigned int y, x, p, addrencode; + fmesh_Eid_to_coords(id, &x, &y, &p); + addrencode = ( p<<(nxw+nyw) | (y< %d,%d\n",r2r_cnt_all[n].r1, r2r_cnt_all[n].p1,r2r_cnt_all[n].r2,r2r_cnt_all[n].p2); + conect_r2r(1,r2r_cnt_all[n].r1,r2r_cnt_all[n].p1,1,r2r_cnt_all[n].r2,r2r_cnt_all[n].p2); +} + +static inline void topology_connect_r2e (int n){ + //printf ("%d,%d -> %d\n",r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n); + connect_r2e(1,r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n); +} + +#define fill_r2r_cnt(T1,R1,P1,T2,R2,P2) (r2r_cnt_table_t){.id1=R1,.t1=T1,.r1=R1,.p1=P1,.id2=R2,.t2=T2,.r2=R2,.p2=P2} -/* -void topology_connect_all_nodes_old (void){ + +static inline void topology_edge_connect(unsigned id1, unsigned id2, unsigned int p1, unsigned int p2, unsigned int fmesh_id,unsigned int R_ADDR, unsigned *num) { + #if defined (IS_MESH) || defined (IS_MESH_3D) || defined (IS_LINE) + connect_r2gnd(1,id1,p1); + #elif defined (IS_TORUS) || defined (IS_RING) + r2r_cnt_all[*num]=fill_r2r_cnt(1,id1,p1,1,id2,p2); + (*num)++; + #elif defined (IS_FMESH) + r2e_cnt_all[fmesh_id].r1=id1; + r2e_cnt_all[fmesh_id].p1=p1; + er_addr [fmesh_id] = R_ADDR; + #endif//topology +} + +void topology_init(void){ + nxw=Log2(X_MAX); + nyw=Log2(Y_MAX); + nzw=Log2(Z_MAX); - unsigned int x,y,l; - #if defined (IS_LINE) || defined (IS_RING ) - #define R2R_CHANELS_MESH_TORI 2 - for (x=0; xcurrent_r_addr = x; - router1[x]->current_r_id = x; - if(x < T1-1){// not_last_node - //assign router_chan_in[x][FORWARD] = router_chan_out [(x+1)][BACKWARD]; - conect_r2r(1,x,FORWARD,1,(x+1),BACKWARD); - } else { //last_node - - #if defined (IS_LINE) // : line_last_x - //assign router_chan_in[x][FORWARD]= {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,x,FORWARD); - #else // : ring_last_x - //assign router_chan_in[x][FORWARD]= router_chan_out [0][BACKWARD]; - conect_r2r(1,x,FORWARD,1,0,BACKWARD); - #endif - } - if(x>0){// :not_first_x - //assign router_chan_in[x][BACKWARD]= router_chan_out [(x-1)][FORWARD]; - conect_r2r(1,x,BACKWARD,1,(x-1),FORWARD); - - }else {// :first_x - #if defined (IS_LINE) // : line_first_x - //assign router_chan_in[x][BACKWARD]={SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,x,BACKWARD); - #else // : ring_first_x - //assign router_chan_in[x][BACKWARD]= router_chan_out [(NX-1)][FORWARD]; - conect_r2r(1,x,BACKWARD,1,(T1-1),FORWARD); - #endif - } - // connect other local ports - for (l=0; lcurrent_r_addr = R_ADDR; router1[ROUTER_NUM]->current_r_id = ROUTER_NUM; - if(x < T1-1) {//: not_last_x - //assign router_chan_in[`router_id(x,y)][EAST]= router_chan_out [`router_id(x+1,y)][WEST]; - conect_r2r(1,router_id(x,y),EAST,1,router_id(x+1,y),WEST); - - }else {// :last_x - #if defined (IS_MESH) // :last_x_mesh - // assign router_chan_in[`router_id(x,y)][EAST] = {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),EAST); - #elif defined (IS_TORUS) // : last_x_torus - //assign router_chan_in[`router_id(x,y)][EAST] = router_chan_out [`router_id(0,y)][WEST]; - conect_r2r(1,router_id(x,y),EAST,1,router_id(0,y),WEST); - #elif defined (IS_FMESH) //:last_x_fmesh - //connect to endp - unsigned int EAST_ID = T1*T2*T3 + 2*T1 + T2 + y; - connect_r2e(1,router_id(x,y),EAST,EAST_ID); - er_addr [EAST_ID] = R_ADDR; - #endif//topology - } - if(y>0) {// : not_first_y - //assign router_chan_in[`router_id(x,y)][NORTH] = router_chan_out [`router_id(x,(y-1))][SOUTH]; - conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(y-1)),SOUTH); - }else {// :first_y - #if defined (IS_MESH) // : first_y_mesh - //assign router_chan_in[`router_id(x,y)][NORTH] = {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),NORTH); - #elif defined (IS_TORUS)// :first_y_torus - //assign router_chan_in[`router_id(x,y)][NORTH] = router_chan_out [`router_id(x,(T2-1))][SOUTH]; - conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(T2-1)),SOUTH); - #elif defined (IS_FMESH) // :first_y_fmesh - unsigned int NORTH_ID = T1*T2*T3 + x; - connect_r2e(1,router_id(x,y),NORTH,NORTH_ID); - er_addr [NORTH_ID] = R_ADDR; - #endif//topology - }//y>0 - if(x>0){// :not_first_x - //assign router_chan_in[`router_id(x,y)][WEST] = router_chan_out [`router_id((x-1),y)][EAST]; - conect_r2r(1,router_id(x,y),WEST,1,router_id((x-1),y),EAST); - }else {// :first_x - - #if defined (IS_MESH) // :first_x_mesh - //assign router_chan_in[`router_id(x,y)][WEST] = {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),WEST); - - #elif defined (IS_TORUS) // :first_x_torus - //assign router_chan_in[`router_id(x,y)][WEST] = router_chan_out [`router_id((NX-1),y)][EAST] ; - conect_r2r(1,router_id(x,y),WEST,1,router_id((T1-1),y),EAST); - #elif defined (IS_FMESH) // :first_x_fmesh - unsigned int WEST_ID = T1*T2*T3 + 2*T1 + y; - connect_r2e(1,router_id(x,y),WEST,WEST_ID); - er_addr [WEST_ID] = R_ADDR; - #endif//topology - } - if(y < T2-1) {// : firsty - //assign router_chan_in[`router_id(x,y)][SOUTH] = router_chan_out [`router_id(x,(y+1))][NORTH]; - conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,(y+1)),NORTH); - }else {// : lasty - - #if defined (IS_MESH) // :ly_mesh - - //assign router_chan_in[`router_id(x,y)][SOUTH]= {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),SOUTH); - - #elif defined (IS_TORUS) // :ly_torus - //assign router_chan_in[`router_id(x,y)][SOUTH]= router_chan_out [`router_id(x,0)][NORTH]; - conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,0),NORTH); - #elif defined (IS_FMESH) // :ly_Fmesh - unsigned int SOUTH_ID = T1*T2*T3 + T1 + x; - connect_r2e(1,router_id(x,y),SOUTH,SOUTH_ID); - er_addr [SOUTH_ID] = R_ADDR; - #endif//topology - } + unsigned int FMESH_EAST_ID = T1*T2*T3 + 2*T1 + T2 + y; + unsigned int FMESH_WEST_ID = T1*T2*T3 + 2*T1 + y; + unsigned int FMESH_SOUTH_ID = T1*T2*T3 + T1 + x; + unsigned int FMESH_NORTH_ID = T1*T2*T3 + x; // endpoint(s) connection - // connect other local ports - for (l=0; l0) r2r_cnt_all[num++]=fill_r2r_cnt(1,ROUTER_NUM,WEST,1,router_id((x-1),y,z),EAST); + else topology_edge_connect(ROUTER_NUM, router_id((X_MAX-1),y,z), WEST, EAST, FMESH_WEST_ID, R_ADDR, &num); + if(DIM==1) continue; + if (y < Y_MAX-1) r2r_cnt_all[num++] = fill_r2r_cnt(1, ROUTER_NUM, SOUTH, 1, router_id(x, y + 1, z), NORTH); + else topology_edge_connect(ROUTER_NUM, router_id(x, 0, z), SOUTH, NORTH, FMESH_SOUTH_ID, R_ADDR, &num); + + if (y>0) r2r_cnt_all[num++] = fill_r2r_cnt(1, ROUTER_NUM, NORTH, 1, router_id(x, y - 1, z), SOUTH); + else topology_edge_connect(ROUTER_NUM, router_id(x, (Y_MAX-1), z), NORTH, SOUTH, FMESH_NORTH_ID, R_ADDR, &num); + if(DIM==2) continue; + if (z < Z_MAX-1) r2r_cnt_all[num++] = fill_r2r_cnt(1, router_id(x, y, z), UP, 1, router_id(x, y, z + 1), DOWN); + else connect_r2gnd(1,ROUTER_NUM,UP); + if (z > 0) r2r_cnt_all[num++] = fill_r2r_cnt(1, ROUTER_NUM, DOWN, 1, router_id(x, y, z - 1), UP); + else connect_r2gnd(1,ROUTER_NUM,DOWN); }//y }//x - #endif -} -*/ -#define fill_r2r_cnt(T1,R1,P1,T2,R2,P2) (r2r_cnt_table_t){.id1=R1,.t1=T1,.r1=R1,.p1=P1,.id2=R2,.t2=T2,.r2=R2,.p2=P2} - -void topology_init(void){ - nxw=Log2(T1); - nyw=Log2(T2); - maskx = (0x1<current_r_addr = x; - router1[x]->current_r_id = x; - if(x < T1-1){// not_last_node - //assign router_chan_in[x][FORWARD] = router_chan_out [(x+1)][BACKWARD]; - //conect_r2r(1,x,FORWARD,1,(x+1),BACKWARD); - r2r_cnt_all[num]=fill_r2r_cnt(1,x,FORWARD,1,(x+1),BACKWARD); - num++; - } else { //last_node - #if defined (IS_LINE) // : line_last_x - //assign router_chan_in[x][FORWARD]= {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,x,FORWARD); - #else // : ring_last_x - //assign router_chan_in[x][FORWARD]= router_chan_out [0][BACKWARD]; - //conect_r2r(1,x,FORWARD,1,0,BACKWARD); - r2r_cnt_all[num]=fill_r2r_cnt(1,x,FORWARD,1,0,BACKWARD); - num++; - #endif - } - if(x>0){// :not_first_x - //assign router_chan_in[x][BACKWARD]= router_chan_out [(x-1)][FORWARD]; - //conect_r2r(1,x,BACKWARD,1,(x-1),FORWARD); - r2r_cnt_all[num]=fill_r2r_cnt(1,x,BACKWARD,1,(x-1),FORWARD); - num++; - }else {// :first_x - #if defined (IS_LINE) // : line_first_x - //assign router_chan_in[x][BACKWARD]={SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,x,BACKWARD); - #else // : ring_first_x - //assign router_chan_in[x][BACKWARD]= router_chan_out [(NX-1)][FORWARD]; - //conect_r2r(1,x,BACKWARD,1,(T1-1),FORWARD); - r2r_cnt_all[num]=fill_r2r_cnt(1,x,BACKWARD,1,(T1-1),FORWARD); - num++; - #endif - } - // connect other local ports - for (l=0; lcurrent_r_addr = R_ADDR; - router1[ROUTER_NUM]->current_r_id = ROUTER_NUM; - if(x < T1-1) {//: not_last_x - //assign router_chan_in[`router_id(x,y)][EAST]= router_chan_out [`router_id(x+1,y)][WEST]; - //conect_r2r(1,router_id(x,y),EAST,1,router_id(x+1,y),WEST); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),EAST,1,router_id(x+1,y),WEST); - num++; - }else {// :last_x - #if defined (IS_MESH) // :last_x_mesh - // assign router_chan_in[`router_id(x,y)][EAST] = {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),EAST); - #elif defined (IS_TORUS) // : last_x_torus - //assign router_chan_in[`router_id(x,y)][EAST] = router_chan_out [`router_id(0,y)][WEST]; - //conect_r2r(1,router_id(x,y),EAST,1,router_id(0,y),WEST); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),EAST,1,router_id(0,y),WEST); - num++; - #elif defined (IS_FMESH) //:last_x_fmesh - //connect to endp - unsigned int EAST_ID = T1*T2*T3 + 2*T1 + T2 + y; - //connect_r2e(1,router_id(x,y),EAST,EAST_ID); - r2e_cnt_all[EAST_ID].r1=router_id(x,y); - r2e_cnt_all[EAST_ID].p1=EAST; - er_addr [EAST_ID] = R_ADDR; - #endif//topology - } - if(y>0) {// : not_first_y - //assign router_chan_in[`router_id(x,y)][NORTH] = router_chan_out [`router_id(x,(y-1))][SOUTH]; - //conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(y-1)),SOUTH); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),NORTH,1,router_id(x,(y-1)),SOUTH); - num++; - }else {// :first_y - #if defined (IS_MESH) // : first_y_mesh - //assign router_chan_in[`router_id(x,y)][NORTH] = {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),NORTH); - #elif defined (IS_TORUS)// :first_y_torus - //assign router_chan_in[`router_id(x,y)][NORTH] = router_chan_out [`router_id(x,(T2-1))][SOUTH]; - //conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(T2-1)),SOUTH); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),NORTH,1,router_id(x,(T2-1)),SOUTH); - num++; - #elif defined (IS_FMESH) // :first_y_fmesh - unsigned int NORTH_ID = T1*T2*T3 + x; - //connect_r2e(1,router_id(x,y),NORTH,NORTH_ID); - r2e_cnt_all[NORTH_ID].r1=router_id(x,y); - r2e_cnt_all[NORTH_ID].p1=NORTH; - er_addr [NORTH_ID] = R_ADDR; - #endif//topology - }//y>0 - if(x>0){// :not_first_x - //assign router_chan_in[`router_id(x,y)][WEST] = router_chan_out [`router_id((x-1),y)][EAST]; - //conect_r2r(1,router_id(x,y),WEST,1,router_id((x-1),y),EAST); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),WEST,1,router_id((x-1),y),EAST); - num++; - }else {// :first_x - #if defined (IS_MESH) // :first_x_mesh - //assign router_chan_in[`router_id(x,y)][WEST] = {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),WEST); - #elif defined (IS_TORUS) // :first_x_torus - //assign router_chan_in[`router_id(x,y)][WEST] = router_chan_out [`router_id((NX-1),y)][EAST] ; - //conect_r2r(1,router_id(x,y),WEST,1,router_id((T1-1),y),EAST); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),WEST,1,router_id((T1-1),y),EAST); - num++; - #elif defined (IS_FMESH) // :first_x_fmesh - unsigned int WEST_ID = T1*T2*T3 + 2*T1 + y; - //connect_r2e(1,router_id(x,y),WEST,WEST_ID); - r2e_cnt_all[WEST_ID].r1=router_id(x,y); - r2e_cnt_all[WEST_ID].p1=WEST; - er_addr [WEST_ID] = R_ADDR; - #endif//topology - } - if(y < T2-1) {// : firsty - //assign router_chan_in[`router_id(x,y)][SOUTH] = router_chan_out [`router_id(x,(y+1))][NORTH]; - // conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,(y+1)),NORTH); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),SOUTH,1,router_id(x,(y+1)),NORTH); - num++; - }else {// : lasty - #if defined (IS_MESH) // :ly_mesh - //assign router_chan_in[`router_id(x,y)][SOUTH]= {SMARTFLIT_CHANEL_w{1'b0}}; - connect_r2gnd(1,router_id(x,y),SOUTH); - #elif defined (IS_TORUS) // :ly_torus - //assign router_chan_in[`router_id(x,y)][SOUTH]= router_chan_out [`router_id(x,0)][NORTH]; - // conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,0),NORTH); - r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),SOUTH,1,router_id(x,0),NORTH); - num++; - #elif defined (IS_FMESH) // :ly_Fmesh - unsigned int SOUTH_ID = T1*T2*T3 + T1 + x; - //connect_r2e(1,router_id(x,y),SOUTH,SOUTH_ID); - r2e_cnt_all[SOUTH_ID].r1=router_id(x,y); - r2e_cnt_all[SOUTH_ID].p1=SOUTH; - er_addr [SOUTH_ID] = R_ADDR; - #endif//topology - } - // endpoint(s) connection - // connect other local ports - for (l=0; l x2) ? (x1 - x2) : (x2 - x1); unsigned int y_diff = (y1 > y2) ? (y1 - y2) : (y2 - y1); - return x_diff + y_diff; + unsigned int z_diff = (z1 > z2) ? (z1 - z2) : (z2 - z1); + return x_diff + y_diff + z_diff; } -#endif +#endif \ No newline at end of file diff --git a/mpsoc/src_verilator/topology/topology_top.h b/mpsoc/src_verilator/topology/topology_top.h index 361292c..5143e4d 100644 --- a/mpsoc/src_verilator/topology/topology_top.h +++ b/mpsoc/src_verilator/topology/topology_top.h @@ -37,7 +37,7 @@ NR_num-=1; offset += router_NRs[NR_num]; } - return offset + NR_id; + return offset + NR_id; } #endif @@ -52,12 +52,12 @@ } unsigned int powi (unsigned int x, unsigned int y){ // x^y - unsigned int i; + unsigned int i; unsigned int pow=1; for (int i = 0; i >1; mcast_list_array[i*4+2] = (ch & 0x4)>>2; mcast_list_array[i*4+3] = (ch & 0x8)>>3; @@ -350,28 +158,152 @@ void mcast_init(){ ch&=0xf; mcast_list_array[i ] = ch; } - } - for (i=0;i