From e37ce1a192dfdb8fd0b99ea4f06b7e3d25551f56 Mon Sep 17 00:00:00 2001
From: Tudor Andrei Dicu <tudor@dicu.org>
Date: Mon, 2 Feb 2026 12:33:30 +0200
Subject: [PATCH] esp: spi: Fix `connect_pins`

---
 port/espressif/esp/src/hal/spi.zig | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/port/espressif/esp/src/hal/spi.zig b/port/espressif/esp/src/hal/spi.zig
index bda596b81..2abc26370 100644
--- a/port/espressif/esp/src/hal/spi.zig
+++ b/port/espressif/esp/src/hal/spi.zig
@@ -160,7 +160,6 @@ pub const SPI = enum(u2) {
         self.set_bit_order(config.bit_order);
     }
 
-    // TODO: not sure if this is the best way to do this
     pub inline fn connect_pins(_: SPI, pins: struct {
         data: union(enum) {
             single_one_wire: ?gpio.Pin,
@@ -188,7 +187,7 @@ pub const SPI = enum(u2) {
             },
             .single_two_wires => |maybe_pins| {
                 if (maybe_pins.mosi) |mosi| {
-                    mosi.connect_input_to_peripheral(.{ .signal = .fspid });
+                    mosi.connect_peripheral_to_output(.{ .signal = .fspid });
                 }
                 if (maybe_pins.miso) |miso| {
                     miso.connect_input_to_peripheral(.{ .signal = .fspiq });
@@ -223,6 +222,10 @@ pub const SPI = enum(u2) {
                 }
             },
         }
+
+        if (pins.clk) |clk_pin| {
+            clk_pin.connect_peripheral_to_output(.{ .signal = .spiclk });
+        }
     }
 
     pub fn writev_blocking(