From aadb3424bd92503e7f8385d8d77a24cb24852cfa Mon Sep 17 00:00:00 2001 From: wnew Date: Wed, 2 Aug 2023 16:54:23 +0200 Subject: [PATCH] Changing "enable VP/VN" to false The Vivado IP "system management wizard" sets the "enable VP/VN" to true by default. This exposes these 2 ports on the IP which are supposed to be connected to pins on the FPGA. But these signals are not broken out in the wrapper nor to the top level. The problem comes in where the IP automatically adds "IOSTANDARD Analog" pin constraints to the design which causes a critical warning because these pins do not exist. See System Management Wizard v1.3 Product Guide (PG185) "The System Management Wizard writes the required ANALOG IOSTANDARD constraint on VP/VN ports. Setting the Analog Bank Selection for vaux pins (shown in Figure 4-14) writes the pin LOC and IOSTANDARD constraint for vaux ports." It makes sense that if these signals are not being routed to the top level that they not be configured in the first place. -Wes --- src/system_config/vivado_ip/system_management_wiz.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/system_config/vivado_ip/system_management_wiz.tcl b/src/system_config/vivado_ip/system_management_wiz.tcl index 8e92afe..d1f51cd 100644 --- a/src/system_config/vivado_ip/system_management_wiz.tcl +++ b/src/system_config/vivado_ip/system_management_wiz.tcl @@ -25,7 +25,7 @@ set_property -dict { CONFIG.VCCINT_ALARM {false} CONFIG.VCCAUX_ALARM {false} CONFIG.ENABLE_VBRAM_ALARM {false} - CONFIG.CHANNEL_ENABLE_VP_VN {true} + CONFIG.CHANNEL_ENABLE_VP_VN {false} CONFIG.AVERAGE_ENABLE_VBRAM {true} CONFIG.AVERAGE_ENABLE_TEMPERATURE {true} CONFIG.AVERAGE_ENABLE_VCCINT {true}