Guidelines for new SIMD instructions

[ngzhian]

Now that SIMD proposal has reached Phase 5, there is a question of where new SIMD instructions should go, what is the process to add new SIMD instructions to Wasm. This issue tries to capture the process and requirements (we might be able to move this somewhere else).

1. Are the instructions you are suggesting deterministic (modulo existing NaN behaviors for floating points already in the spec? If yes, go to 2. If no, go to https://github.com/WebAssembly/relaxed-simd/
2. What are the use cases for these instructions. Share links to projects that use and will benefit from these instructions. Bonus if these projects already target Wasm or have plans to.
3. How widely supported are the instructions? What does the lowering look like on major architectures?

With the answers to the above question in mind, you should then file an issue in https://github.com/WebAssembly/design. These new instructions can be advanced as their own proposal following the process. The usual process might look heavyweight for adding a couple of new instructions, but recent CG discussions have indicated that the CG is will to ty to advance small proposals that don't change the spec in major ways more quickly, and you can poll for multiple phase advancements at one go, as long as the requirements are satisfied.

[ngzhian]

Drafted the above to be something easily shareable to anyone who wishes to add new SIMD instructions but not sure how to do so. Comments/edits welcome.

[dtig]

Thanks for drafting this, I would like to suggest one edit to the third point. Instead of "How widely supported are the instructions? Are there single instruction lowering on all major architectures?", how about "How widely supported are the instructions? What does the lowering look like on major architectures?".

I think phrasing it in terms of looking at the lowering doesn't set expectations that single instruction lowerings are required for a useful set of instructions to be proposed. The subsequent questions are a good framework for discussing performance across architectures.