From f97fe801558ce1c98712661ea45203d2142c9131 Mon Sep 17 00:00:00 2001 From: Anthony Tarbinian Date: Wed, 19 Mar 2025 22:16:31 -0700 Subject: [PATCH 1/2] organize add test --- src/utils.rs | 3 +- .../add/add.arm.s | 4 - tests/{binaries => add}/add.riscv.s | 0 tests/add/test_add.rs | 125 ++++++++++++++++++ tests/tests.rs | 3 + 5 files changed, 130 insertions(+), 5 deletions(-) rename test_binary_translate_add.S => tests/add/add.arm.s (89%) rename tests/{binaries => add}/add.riscv.s (100%) create mode 100644 tests/add/test_add.rs create mode 100644 tests/tests.rs diff --git a/src/utils.rs b/src/utils.rs index a0c9f46..eb35249 100644 --- a/src/utils.rs +++ b/src/utils.rs @@ -27,5 +27,6 @@ pub fn translate_to_file(instrs: Vec, path: String) { contents.push_str(&x); contents.push_str("\n"); } - fs::write(path, contents).expect("Unable to write file"); + fs::write(&path, contents).expect("Unable to write file"); + println!("Saved ARM assembly to {}", path); } diff --git a/test_binary_translate_add.S b/tests/add/add.arm.s similarity index 89% rename from test_binary_translate_add.S rename to tests/add/add.arm.s index 391c523..e31b145 100644 --- a/test_binary_translate_add.S +++ b/tests/add/add.arm.s @@ -2,16 +2,12 @@ .text .global _start -.global _main -.balign 4 _start: bl main mov x8, #93 svc #0 -.balign 4 -_main: main: sub sp, sp, 32 diff --git a/tests/binaries/add.riscv.s b/tests/add/add.riscv.s similarity index 100% rename from tests/binaries/add.riscv.s rename to tests/add/add.riscv.s diff --git a/tests/add/test_add.rs b/tests/add/test_add.rs new file mode 100644 index 0000000..a2686d3 --- /dev/null +++ b/tests/add/test_add.rs @@ -0,0 +1,125 @@ +#[cfg(test)] +mod tests { + use binary_room::instruction::*; + use binary_room::translate::*; + use binary_room::utils; + use binary_room::utils::translate_to_file; + use binary_room::utils::START; + + #[test] + fn test_binary_translate() { + let riscv_asm: Vec = vec![ + RiscVInstruction::Verbatim { text: START.to_string() }, + RiscVInstruction::Addi { + dest: RiscVRegister::SP, + src: RiscVRegister::SP, + imm: -32, + }, + RiscVInstruction::S { + width: RiscVWidth::Double, + src: RiscVRegister::RA, + dest: RiscVVal::Offset { + register: RiscVRegister::SP, + offset: 24, + }, + }, + RiscVInstruction::S { + width: RiscVWidth::Double, + src: RiscVRegister::S0FP, + dest: RiscVVal::Offset { + register: RiscVRegister::SP, + offset: 16, + }, + }, + RiscVInstruction::Addi { + dest: RiscVRegister::S0FP, + src: RiscVRegister::SP, + imm: 32, + }, + RiscVInstruction::Li { + dest: RiscVRegister::A5, + imm: 3, + }, + RiscVInstruction::S { + width: RiscVWidth::Word, + src: RiscVRegister::A5, + dest: RiscVVal::Offset { + register: RiscVRegister::S0FP, + offset: -20, + }, + }, + RiscVInstruction::Li { + dest: RiscVRegister::A5, + imm: 4, + }, + RiscVInstruction::S { + width: RiscVWidth::Word, + src: RiscVRegister::A5, + dest: RiscVVal::Offset { + register: RiscVRegister::S0FP, + offset: -24, + }, + }, + RiscVInstruction::L { + width: RiscVWidth::Word, + dest: RiscVRegister::A5, + src: RiscVVal::Offset { + register: RiscVRegister::S0FP, + offset: -20, + }, + }, + RiscVInstruction::Mv { + dest: RiscVRegister::A4, + src: RiscVRegister::A5, + }, + RiscVInstruction::L { + width: RiscVWidth::Word, + dest: RiscVRegister::A5, + src: RiscVVal::Offset { + register: RiscVRegister::S0FP, + offset: -24, + }, + }, + RiscVInstruction::Add { + width: RiscVWidth::Word, + dest: RiscVRegister::A5, + arg1: RiscVRegister::A4, + arg2: RiscVRegister::A5, + }, + RiscVInstruction::SextW { + dest: RiscVRegister::A5, + src: RiscVRegister::A5, + }, + RiscVInstruction::Mv { + dest: RiscVRegister::A0, + src: RiscVRegister::A5, + }, + RiscVInstruction::L { + width: RiscVWidth::Double, + dest: RiscVRegister::RA, + src: RiscVVal::Offset { + register: RiscVRegister::SP, + offset: 24, + }, + }, + RiscVInstruction::L { + width: RiscVWidth::Double, + dest: RiscVRegister::S0FP, + src: RiscVVal::Offset { + register: RiscVRegister::SP, + offset: 16, + }, + }, + RiscVInstruction::Addi { + dest: RiscVRegister::SP, + src: RiscVRegister::SP, + imm: 32, + }, + RiscVInstruction::Jr { + target: RiscVRegister::RA, + }, + ]; + + translate_to_file(riscv_asm, "./tests/add/add.arm.s".to_string()); + } +} diff --git a/tests/tests.rs b/tests/tests.rs new file mode 100644 index 0000000..b62532c --- /dev/null +++ b/tests/tests.rs @@ -0,0 +1,3 @@ + +#[path = "add/test_add.rs"] +mod add; From 61b37eca130d7080cec5ffe7015301a28ee089ba Mon Sep 17 00:00:00 2001 From: Anthony Tarbinian Date: Thu, 20 Mar 2025 08:50:36 -0700 Subject: [PATCH 2/2] organized echo and print tests --- tests/add/add.arm.s | 4 ++++ tests/echo/echo.arm.s | 29 +++++++++++++++++++++++++++++ tests/{ => echo}/test_echo.rs | 2 +- tests/print/print.arm.s | 28 ++++++++++++++++++++++++++++ tests/{ => print}/test_print.rs | 2 +- tests/tests.rs | 7 ++++++- 6 files changed, 69 insertions(+), 3 deletions(-) create mode 100644 tests/echo/echo.arm.s rename tests/{ => echo}/test_echo.rs (96%) create mode 100644 tests/print/print.arm.s rename tests/{ => print}/test_print.rs (95%) diff --git a/tests/add/add.arm.s b/tests/add/add.arm.s index e31b145..391c523 100644 --- a/tests/add/add.arm.s +++ b/tests/add/add.arm.s @@ -2,12 +2,16 @@ .text .global _start +.global _main +.balign 4 _start: bl main mov x8, #93 svc #0 +.balign 4 +_main: main: sub sp, sp, 32 diff --git a/tests/echo/echo.arm.s b/tests/echo/echo.arm.s new file mode 100644 index 0000000..44c8b7a --- /dev/null +++ b/tests/echo/echo.arm.s @@ -0,0 +1,29 @@ + +.text + +.global _start +.global _main + +.balign 4 +_start: +bl main +mov x8, #93 +svc #0 + +.balign 4 +_main: +main: + +sub sp, sp, 32 +mov x8, 63 +mov x2, 32 +add x1, sp, 0 +mov x0, 0 +svc 0 +mov x8, 64 +mov x2, 14 +add x1, sp, 0 +mov x0, 1 +svc 0 +mov x8, 93 +svc 0 diff --git a/tests/test_echo.rs b/tests/echo/test_echo.rs similarity index 96% rename from tests/test_echo.rs rename to tests/echo/test_echo.rs index 33725b8..36cd6f5 100644 --- a/tests/test_echo.rs +++ b/tests/echo/test_echo.rs @@ -68,6 +68,6 @@ mod tests { RiscVInstruction::ECall, ]; - translate_to_file(riscv_asm, "test_binary_translate_echo.S".to_string()); + translate_to_file(riscv_asm, "./tests/echo/echo.arm.s".to_string()); } } diff --git a/tests/print/print.arm.s b/tests/print/print.arm.s new file mode 100644 index 0000000..392f418 --- /dev/null +++ b/tests/print/print.arm.s @@ -0,0 +1,28 @@ + +.buf: + .string "hello world\n" + + +.text + +.global _start +.global _main + +.balign 4 +_start: +bl main +mov x8, #93 +svc #0 + +.balign 4 +_main: +main: + +mov x8, 64 +mov x2, 14 +adrp x0, .buf +add x1, x0, :lo12:.buf +mov x0, 1 +svc 0 +mov x8, 93 +svc 0 diff --git a/tests/test_print.rs b/tests/print/test_print.rs similarity index 95% rename from tests/test_print.rs rename to tests/print/test_print.rs index 07840dc..8471e92 100644 --- a/tests/test_print.rs +++ b/tests/print/test_print.rs @@ -58,6 +58,6 @@ mod tests { RiscVInstruction::ECall, ]; - translate_to_file(riscv_asm, "test_binary_translate_print.S".to_string()); + translate_to_file(riscv_asm, "./tests/print/print.arm.s".to_string()); } } diff --git a/tests/tests.rs b/tests/tests.rs index b62532c..3bfde3f 100644 --- a/tests/tests.rs +++ b/tests/tests.rs @@ -1,3 +1,8 @@ - #[path = "add/test_add.rs"] mod add; + +#[path = "echo/test_echo.rs"] +mod echo; + +#[path = "print/test_print.rs"] +mod print;