From d2fa727539574aa4d354df98dc89e84c8208bee0 Mon Sep 17 00:00:00 2001 From: xxqfhj Date: Sun, 14 Jul 2019 17:57:12 +0800 Subject: [PATCH] Fix combination loop in icb_claim_irq and icb_complete_irq. There is combination loop in icb_claim_irq and icb_complete_irq assign logic. This loop will make the simulation tool time stuck(the tool is ncsim), and lint/synthesize can't found this loop. After analysis, I think lint tool treat the logic "a=0; a=a|b;" same as "a=b;" in function, so lint and synthesize tool don't report this loop because it optimize this logic. After change this logic to "a=b;" directly, simulation could runs to final. Signed-off-by: xxqfhj --- rtl/e203/perips/sirv_plic_man.v | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/rtl/e203/perips/sirv_plic_man.v b/rtl/e203/perips/sirv_plic_man.v index 87ca78b7..57bcb8b3 100644 --- a/rtl/e203/perips/sirv_plic_man.v +++ b/rtl/e203/perips/sirv_plic_man.v @@ -413,8 +413,8 @@ localparam PLIC_PEND_ARRAY = (((PLIC_IRQ_NUM-1)/32) + 1); end//} // - //0x0C00 1000 Start of target 0 enable array - //0x0C00 107C End of target 0 enable array + //0x0C00 2000 Start of target 0 enable array + //0x0C00 207C End of target 0 enable array //.... target 1 //.... target 2 for(i=0; i<(PLIC_PEND_ARRAY);i=i+1) begin: sel_enab_i//{ @@ -504,7 +504,6 @@ localparam PLIC_PEND_ARRAY = (((PLIC_IRQ_NUM-1)/32) + 1); endgenerate - generate // for(i=0; i