diff --git a/library/SubcircuitLibrary/ICM7555/ICM7555-cache.lib b/library/SubcircuitLibrary/ICM7555/ICM7555-cache.lib new file mode 100644 index 000000000..f81b8a9a1 --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/ICM7555-cache.lib @@ -0,0 +1,201 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ICM7555/ICM7555.cir b/library/SubcircuitLibrary/ICM7555/ICM7555.cir new file mode 100644 index 000000000..9dca20924 --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/ICM7555.cir @@ -0,0 +1,38 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\ICM7555\ICM7555.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/11/25 10:14:45 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 /8 Net-_M2-Pad2_ Net-_M1-Pad1_ /8 eSim_MOS_P +M3 /8 Net-_M2-Pad2_ Net-_M2-Pad2_ /8 eSim_MOS_P +M1 Net-_M1-Pad1_ /6 Net-_I1-Pad1_ Net-_I1-Pad1_ eSim_MOS_N +M4 Net-_M2-Pad2_ /5 Net-_I1-Pad1_ Net-_I1-Pad1_ eSim_MOS_N +R1 /8 /5 100k +R2 /5 Net-_M5-Pad2_ 100k +R3 Net-_M5-Pad2_ /1 100k +M5 Net-_I2-Pad2_ Net-_M5-Pad2_ Net-_M5-Pad3_ Net-_I2-Pad2_ eSim_MOS_P +M8 Net-_I2-Pad2_ /2 Net-_M10-Pad2_ Net-_I2-Pad2_ eSim_MOS_P +M6 Net-_M5-Pad3_ Net-_M5-Pad3_ /1 /1 eSim_MOS_N +M7 Net-_M10-Pad2_ Net-_M5-Pad3_ /1 /1 eSim_MOS_N +M11 /8 Net-_M1-Pad1_ Net-_M10-Pad1_ /8 eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ /1 /1 eSim_MOS_N +M9 Net-_M10-Pad2_ Net-_M9-Pad2_ /1 /1 eSim_MOS_N +U2 /4 Net-_U2-Pad2_ d_inverter +U3 Net-_U11-Pad2_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_nor +U5 Net-_U3-Pad3_ Net-_U10-Pad1_ d_inverter +U4 Net-_U3-Pad3_ Net-_U4-Pad2_ d_inverter +U6 Net-_U10-Pad1_ /3 d_inverter +M12 /7 Net-_M12-Pad2_ /1 /1 eSim_MOS_N +U1 /1 /2 /3 /4 /5 /6 /7 /8 PORT +U8 Net-_U2-Pad2_ Net-_M9-Pad2_ dac_bridge_1 +U7 Net-_M9-Pad2_ Net-_U3-Pad2_ adc_bridge_1 +U10 Net-_U10-Pad1_ Net-_M12-Pad2_ dac_bridge_1 +U9 Net-_U4-Pad2_ Net-_M10-Pad1_ dac_bridge_1 +U11 Net-_M10-Pad1_ Net-_U11-Pad2_ adc_bridge_1 +I1 Net-_I1-Pad1_ /1 120u +I2 /8 Net-_I2-Pad2_ 120u + +.end diff --git a/library/SubcircuitLibrary/ICM7555/ICM7555.cir.out b/library/SubcircuitLibrary/ICM7555/ICM7555.cir.out new file mode 100644 index 000000000..a5347e5bb --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/ICM7555.cir.out @@ -0,0 +1,71 @@ +* d:\fossee\esim\library\subcircuitlibrary\icm7555\icm7555.cir + +.include PMOS-0.5um.lib +.include NMOS-0.5um.lib +m2 /8 net-_m2-pad2_ net-_m1-pad1_ /8 mos_p W=100u L=100u M=1 +m3 /8 net-_m2-pad2_ net-_m2-pad2_ /8 mos_p W=100u L=100u M=1 +m1 net-_m1-pad1_ /6 net-_i1-pad1_ net-_i1-pad1_ mos_n W=100u L=100u M=1 +m4 net-_m2-pad2_ /5 net-_i1-pad1_ net-_i1-pad1_ mos_n W=100u L=100u M=1 +r1 /8 /5 100k +r2 /5 net-_m5-pad2_ 100k +r3 net-_m5-pad2_ /1 100k +m5 net-_i2-pad2_ net-_m5-pad2_ net-_m5-pad3_ net-_i2-pad2_ mos_p W=100u L=100u M=1 +m8 net-_i2-pad2_ /2 net-_m10-pad2_ net-_i2-pad2_ mos_p W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m5-pad3_ /1 /1 mos_n W=100u L=100u M=1 +m7 net-_m10-pad2_ net-_m5-pad3_ /1 /1 mos_n W=100u L=100u M=1 +m11 /8 net-_m1-pad1_ net-_m10-pad1_ /8 mos_p W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ /1 /1 mos_n W=100u L=100u M=1 +m9 net-_m10-pad2_ net-_m9-pad2_ /1 /1 mos_n W=100u L=100u M=1 +* u2 /4 net-_u2-pad2_ d_inverter +* u3 net-_u11-pad2_ net-_u3-pad2_ net-_u3-pad3_ d_nor +* u5 net-_u3-pad3_ net-_u10-pad1_ d_inverter +* u4 net-_u3-pad3_ net-_u4-pad2_ d_inverter +* u6 net-_u10-pad1_ /3 d_inverter +m12 /7 net-_m12-pad2_ /1 /1 mos_n W=100u L=100u M=1 +* u1 /1 /2 /3 /4 /5 /6 /7 /8 port +* u8 net-_u2-pad2_ net-_m9-pad2_ dac_bridge_1 +* u7 net-_m9-pad2_ net-_u3-pad2_ adc_bridge_1 +* u10 net-_u10-pad1_ net-_m12-pad2_ dac_bridge_1 +* u9 net-_u4-pad2_ net-_m10-pad1_ dac_bridge_1 +* u11 net-_m10-pad1_ net-_u11-pad2_ adc_bridge_1 +i1 net-_i1-pad1_ /1 dc 30ua +i2 /8 net-_i2-pad2_ dc 30ua +a1 /4 net-_u2-pad2_ u2 +a2 [net-_u11-pad2_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +a3 net-_u3-pad3_ net-_u10-pad1_ u5 +a4 net-_u3-pad3_ net-_u4-pad2_ u4 +a5 net-_u10-pad1_ /3 u6 +a6 [net-_u2-pad2_ ] [net-_m9-pad2_ ] u8 +a7 [net-_m9-pad2_ ] [net-_u3-pad2_ ] u7 +a8 [net-_u10-pad1_ ] [net-_m12-pad2_ ] u10 +a9 [net-_u4-pad2_ ] [net-_m10-pad1_ ] u9 +a10 [net-_m10-pad1_ ] [net-_u11-pad2_ ] u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 1e-00 9e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ICM7555/ICM7555.pro b/library/SubcircuitLibrary/ICM7555/ICM7555.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/ICM7555.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ICM7555/ICM7555.sch b/library/SubcircuitLibrary/ICM7555/ICM7555.sch new file mode 100644 index 000000000..6e125cdf9 --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/ICM7555.sch @@ -0,0 +1,741 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ICM7555-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M2 +U 1 1 683DBDC6 +P 2650 2400 +F 0 "M2" H 2600 2450 50 0000 R CNN +F 1 "eSim_MOS_P" H 3300 2450 50 0000 R CNN +F 2 "" H 2900 2500 29 0000 C CNN +F 3 "" H 2700 2400 60 0000 C CNN + 1 2650 2400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 683DBE23 +P 3400 2400 +F 0 "M3" H 3350 2450 50 0000 R CNN +F 1 "eSim_MOS_P" H 4100 2450 50 0000 R CNN +F 2 "" H 3650 2500 29 0000 C CNN +F 3 "" H 3450 2400 60 0000 C CNN + 1 3400 2400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 683DBF34 +P 2300 2800 +F 0 "M1" H 2300 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 2400 2750 50 0000 R CNN +F 2 "" H 2600 2500 29 0000 C CNN +F 3 "" H 2400 2600 60 0000 C CNN + 1 2300 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 683DBF95 +P 3750 2800 +F 0 "M4" H 3750 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 3850 2750 50 0000 R CNN +F 2 "" H 4050 2500 29 0000 C CNN +F 3 "" H 3850 2600 60 0000 C CNN + 1 3750 2800 + -1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 683DC0E2 +P 4250 2300 +F 0 "R1" H 4300 2430 50 0000 C CNN +F 1 "100k" H 4300 2250 50 0000 C CNN +F 2 "" H 4300 2280 30 0000 C CNN +F 3 "" V 4300 2350 30 0000 C CNN + 1 4250 2300 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 683DC157 +P 4250 3200 +F 0 "R2" H 4300 3330 50 0000 C CNN +F 1 "100k" H 4300 3150 50 0000 C CNN +F 2 "" H 4300 3180 30 0000 C CNN +F 3 "" V 4300 3250 30 0000 C CNN + 1 4250 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 683DC260 +P 4250 4050 +F 0 "R3" H 4300 4180 50 0000 C CNN +F 1 "100k" H 4300 4000 50 0000 C CNN +F 2 "" H 4300 4030 30 0000 C CNN +F 3 "" V 4300 4100 30 0000 C CNN + 1 4250 4050 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 683DCCCC +P 4600 3650 +F 0 "M5" H 4550 3700 50 0000 R CNN +F 1 "eSim_MOS_P" H 4650 3800 50 0000 R CNN +F 2 "" H 4850 3750 29 0000 C CNN +F 3 "" H 4650 3650 60 0000 C CNN + 1 4600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 683DCD34 +P 5550 3650 +F 0 "M8" H 5500 3700 50 0000 R CNN +F 1 "eSim_MOS_P" H 5600 3800 50 0000 R CNN +F 2 "" H 5800 3750 29 0000 C CNN +F 3 "" H 5600 3650 60 0000 C CNN + 1 5550 3650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 683DCD54 +P 4950 4050 +F 0 "M6" H 4950 3900 50 0000 R CNN +F 1 "eSim_MOS_N" H 5050 4000 50 0000 R CNN +F 2 "" H 5250 3750 29 0000 C CNN +F 3 "" H 5050 3850 60 0000 C CNN + 1 4950 4050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 683DCDE2 +P 5250 4050 +F 0 "M7" H 5250 3900 50 0000 R CNN +F 1 "eSim_MOS_N" H 5350 4000 50 0000 R CNN +F 2 "" H 5550 3750 29 0000 C CNN +F 3 "" H 5350 3850 60 0000 C CNN + 1 5250 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 2400 3250 2400 +Wire Wire Line + 3550 2600 3550 2800 +Wire Wire Line + 2500 2600 2500 2800 +Wire Wire Line + 2500 3200 2500 3300 +Wire Wire Line + 2500 3300 3550 3300 +Wire Wire Line + 3550 3300 3550 3200 +Wire Wire Line + 2600 3150 2600 3200 +Wire Wire Line + 2600 3200 2500 3200 +Wire Wire Line + 3450 3150 3450 3200 +Wire Wire Line + 3450 3200 3550 3200 +Wire Wire Line + 3050 2400 3050 2700 +Wire Wire Line + 3050 2700 3550 2700 +Connection ~ 3550 2700 +Connection ~ 3050 2400 +Wire Wire Line + 3550 1950 3550 2200 +Wire Wire Line + 2500 2200 2500 1950 +Wire Wire Line + 3650 2550 3850 2550 +Wire Wire Line + 3850 2550 3850 1950 +Wire Wire Line + 2250 1950 9850 1950 +Wire Wire Line + 2400 2550 2250 2550 +Wire Wire Line + 2250 2550 2250 1950 +Connection ~ 2500 1950 +Connection ~ 3550 1950 +Wire Wire Line + 2200 3000 1600 3000 +Connection ~ 3850 1950 +Wire Wire Line + 4300 2200 4300 1950 +Connection ~ 4300 1950 +Wire Wire Line + 4300 2500 4300 3100 +Wire Wire Line + 3850 3000 4300 3000 +Connection ~ 4300 3000 +Wire Wire Line + 4050 3000 4050 3500 +Wire Wire Line + 4050 3500 1600 3500 +Connection ~ 4050 3000 +Wire Wire Line + 4300 3400 4300 3950 +Wire Wire Line + 4300 4650 4300 4250 +Wire Wire Line + 2900 4650 9950 4650 +Connection ~ 2900 3300 +Connection ~ 5000 1950 +Wire Wire Line + 4750 3300 4750 3450 +Wire Wire Line + 5400 3300 5400 3450 +Wire Wire Line + 5400 3850 5400 4050 +Wire Wire Line + 4750 3850 4750 4050 +Wire Wire Line + 5050 4250 5150 4250 +Wire Wire Line + 4750 3900 5100 3900 +Connection ~ 4750 3900 +Wire Wire Line + 5100 3900 5100 4250 +Connection ~ 5100 4250 +Wire Wire Line + 5400 4050 5450 4050 +Wire Wire Line + 4750 4450 4750 4650 +Connection ~ 4300 4650 +Wire Wire Line + 5450 4450 5450 4650 +Connection ~ 4750 4650 +Wire Wire Line + 4450 3650 4300 3650 +Connection ~ 4300 3650 +Wire Wire Line + 5700 3650 5700 3850 +Wire Wire Line + 5700 3850 2550 3850 +Wire Wire Line + 4650 4400 4650 4500 +Wire Wire Line + 4650 4500 4750 4500 +Connection ~ 4750 4500 +Wire Wire Line + 5550 4400 5550 4500 +Wire Wire Line + 5550 4500 5450 4500 +Connection ~ 5450 4500 +Connection ~ 5000 3300 +Wire Wire Line + 4750 3300 5400 3300 +Wire Wire Line + 4850 3800 5000 3800 +Wire Wire Line + 5000 3800 5000 3350 +Wire Wire Line + 5000 3350 4750 3350 +Connection ~ 4750 3350 +Wire Wire Line + 5300 3800 5200 3800 +Wire Wire Line + 5200 3800 5200 3350 +Wire Wire Line + 5200 3350 5400 3350 +Connection ~ 5400 3350 +$Comp +L eSim_MOS_P M11 +U 1 1 683DF725 +P 6450 2350 +F 0 "M11" H 6400 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 6500 2500 50 0000 R CNN +F 2 "" H 6700 2450 29 0000 C CNN +F 3 "" H 6500 2350 60 0000 C CNN + 1 6450 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 683DF76C +P 6400 4150 +F 0 "M10" H 6400 4000 50 0000 R CNN +F 1 "eSim_MOS_N" H 6500 4100 50 0000 R CNN +F 2 "" H 6700 3850 29 0000 C CNN +F 3 "" H 6500 3950 60 0000 C CNN + 1 6400 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6600 1950 6600 2150 +Wire Wire Line + 6700 2500 6900 2500 +Wire Wire Line + 6900 2500 6900 2050 +Wire Wire Line + 6900 2050 6600 2050 +Connection ~ 6600 2050 +Wire Wire Line + 2500 2750 5850 2750 +Wire Wire Line + 5850 2750 5850 2350 +Wire Wire Line + 5850 2350 6300 2350 +Connection ~ 2500 2750 +Wire Wire Line + 6600 2550 6600 4150 +Wire Wire Line + 6600 4550 6600 4650 +Connection ~ 5450 4650 +Wire Wire Line + 6700 4500 6700 4600 +Wire Wire Line + 6700 4600 6600 4600 +Connection ~ 6600 4600 +Wire Wire Line + 6300 3900 6300 4350 +Wire Wire Line + 5400 3900 6300 3900 +Connection ~ 5400 3900 +$Comp +L eSim_MOS_N M9 +U 1 1 683DFECE +P 5950 4150 +F 0 "M9" H 5950 4000 50 0000 R CNN +F 1 "eSim_MOS_N" H 6050 3800 50 0000 R CNN +F 2 "" H 6250 3850 29 0000 C CNN +F 3 "" H 6050 3950 60 0000 C CNN + 1 5950 4150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5750 4550 5750 4650 +Connection ~ 5750 4650 +Wire Wire Line + 5750 4150 5750 3900 +Connection ~ 5750 3900 +Wire Wire Line + 5650 4500 5650 4600 +Wire Wire Line + 5650 4600 5750 4600 +Connection ~ 5750 4600 +Wire Wire Line + 6050 4350 6200 4350 +$Comp +L d_inverter U2 +U 1 1 683E01E6 +P 6200 6350 +F 0 "U2" H 6200 6250 60 0000 C CNN +F 1 "d_inverter" H 6200 6500 60 0000 C CNN +F 2 "" H 6250 6300 60 0000 C CNN +F 3 "" H 6250 6300 60 0000 C CNN + 1 6200 6350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6200 6650 6200 6750 +$Comp +L d_nor U3 +U 1 1 683E0CFE +P 7450 2750 +F 0 "U3" H 7450 2750 60 0000 C CNN +F 1 "d_nor" H 7500 2850 60 0000 C CNN +F 2 "" H 7450 2750 60 0000 C CNN +F 3 "" H 7450 2750 60 0000 C CNN + 1 7450 2750 + 1 0 0 -1 +$EndComp +Connection ~ 6600 2650 +Wire Wire Line + 6200 2750 7000 2750 +Connection ~ 6200 4350 +Wire Wire Line + 7900 2700 8350 2700 +$Comp +L d_inverter U5 +U 1 1 683E0ED7 +P 8650 2700 +F 0 "U5" H 8650 2600 60 0000 C CNN +F 1 "d_inverter" H 8650 2850 60 0000 C CNN +F 2 "" H 8700 2650 60 0000 C CNN +F 3 "" H 8700 2650 60 0000 C CNN + 1 8650 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 683E0F56 +P 7650 3150 +F 0 "U4" H 7650 3050 60 0000 C CNN +F 1 "d_inverter" H 7650 3300 60 0000 C CNN +F 2 "" H 7700 3100 60 0000 C CNN +F 3 "" H 7700 3100 60 0000 C CNN + 1 7650 3150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 8150 2700 8150 3150 +Wire Wire Line + 8150 3150 7950 3150 +Connection ~ 8150 2700 +Connection ~ 6600 3150 +$Comp +L d_inverter U6 +U 1 1 683E1695 +P 9450 2700 +F 0 "U6" H 9450 2600 60 0000 C CNN +F 1 "d_inverter" H 9450 2850 60 0000 C CNN +F 2 "" H 9500 2650 60 0000 C CNN +F 3 "" H 9500 2650 60 0000 C CNN + 1 9450 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 2700 9150 2700 +$Comp +L eSim_MOS_N M12 +U 1 1 683E1C36 +P 9500 3200 +F 0 "M12" H 9500 3050 50 0000 R CNN +F 1 "eSim_MOS_N" H 9600 3150 50 0000 R CNN +F 2 "" H 9800 2900 29 0000 C CNN +F 3 "" H 9600 3000 60 0000 C CNN + 1 9500 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9700 3200 9700 3000 +Wire Wire Line + 9700 3000 9950 3000 +Wire Wire Line + 9700 3600 9700 4650 +Connection ~ 6600 4650 +Connection ~ 9700 4650 +Wire Wire Line + 9800 3550 9800 3700 +Wire Wire Line + 9800 3700 9700 3700 +Connection ~ 9700 3700 +Wire Wire Line + 8950 3400 9400 3400 +Connection ~ 9050 2700 +Connection ~ 6600 1950 +Text Label 1600 3000 0 60 ~ 0 +6 +Text Label 1600 3500 0 60 ~ 0 +5 +Text Label 2550 3850 0 60 ~ 0 +2 +Text Label 6200 6750 0 60 ~ 0 +4 +Text Label 9850 1950 0 60 ~ 0 +8 +Text Label 10800 2750 0 60 ~ 0 +3 +Text Label 9950 3000 0 60 ~ 0 +7 +Text Label 9950 4650 0 60 ~ 0 +1 +$Comp +L PORT U1 +U 1 1 683E5D9E +P 10200 4650 +F 0 "U1" H 10250 4750 30 0000 C CNN +F 1 "PORT" H 10200 4650 30 0000 C CNN +F 2 "" H 10200 4650 60 0000 C CNN +F 3 "" H 10200 4650 60 0000 C CNN + 1 10200 4650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 683E5DFF +P 2300 3850 +F 0 "U1" H 2350 3950 30 0000 C CNN +F 1 "PORT" H 2300 3850 30 0000 C CNN +F 2 "" H 2300 3850 60 0000 C CNN +F 3 "" H 2300 3850 60 0000 C CNN + 2 2300 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 683E5E62 +P 11050 2750 +F 0 "U1" H 11100 2850 30 0000 C CNN +F 1 "PORT" H 11050 2750 30 0000 C CNN +F 2 "" H 11050 2750 60 0000 C CNN +F 3 "" H 11050 2750 60 0000 C CNN + 3 11050 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 683E5ED1 +P 6200 7000 +F 0 "U1" H 6250 7100 30 0000 C CNN +F 1 "PORT" H 6200 7000 30 0000 C CNN +F 2 "" H 6200 7000 60 0000 C CNN +F 3 "" H 6200 7000 60 0000 C CNN + 4 6200 7000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 683E5F60 +P 1350 3500 +F 0 "U1" H 1400 3600 30 0000 C CNN +F 1 "PORT" H 1350 3500 30 0000 C CNN +F 2 "" H 1350 3500 60 0000 C CNN +F 3 "" H 1350 3500 60 0000 C CNN + 5 1350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 683E5FC9 +P 1350 3000 +F 0 "U1" H 1400 3100 30 0000 C CNN +F 1 "PORT" H 1350 3000 30 0000 C CNN +F 2 "" H 1350 3000 60 0000 C CNN +F 3 "" H 1350 3000 60 0000 C CNN + 6 1350 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 683E6026 +P 10200 3000 +F 0 "U1" H 10250 3100 30 0000 C CNN +F 1 "PORT" H 10200 3000 30 0000 C CNN +F 2 "" H 10200 3000 60 0000 C CNN +F 3 "" H 10200 3000 60 0000 C CNN + 7 10200 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 683E6085 +P 10100 1950 +F 0 "U1" H 10150 2050 30 0000 C CNN +F 1 "PORT" H 10100 1950 30 0000 C CNN +F 2 "" H 10100 1950 60 0000 C CNN +F 3 "" H 10100 1950 60 0000 C CNN + 8 10100 1950 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U8 +U 1 1 683F2761 +P 6250 5350 +F 0 "U8" H 6250 5350 60 0000 C CNN +F 1 "dac_bridge_1" H 6250 5500 60 0000 C CNN +F 2 "" H 6250 5350 60 0000 C CNN +F 3 "" H 6250 5350 60 0000 C CNN + 1 6250 5350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6200 6050 6200 5950 +Wire Wire Line + 6200 4050 6200 4800 +$Comp +L adc_bridge_1 U7 +U 1 1 683F5E1B +P 6250 3450 +F 0 "U7" H 6250 3450 60 0000 C CNN +F 1 "adc_bridge_1" H 6250 3600 60 0000 C CNN +F 2 "" H 6250 3450 60 0000 C CNN +F 3 "" H 6250 3450 60 0000 C CNN + 1 6250 3450 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6200 2900 6200 2750 +Wire Wire Line + 6600 3150 6650 3150 +Wire Wire Line + 6650 3150 6650 4000 +Wire Wire Line + 6650 4000 6750 4000 +Wire Wire Line + 6600 2650 6700 2650 +Wire Wire Line + 6700 2650 6700 3550 +Wire Wire Line + 6700 3550 6750 3550 +Wire Wire Line + 7900 3550 7900 3350 +Wire Wire Line + 7900 3350 6800 3350 +Wire Wire Line + 6800 3350 6800 2650 +Wire Wire Line + 6800 2650 7000 2650 +Wire Wire Line + 7900 4000 8050 4000 +Wire Wire Line + 8050 4000 8050 3300 +Wire Wire Line + 8050 3300 7050 3300 +Wire Wire Line + 7050 3300 7050 3150 +Wire Wire Line + 7050 3150 7350 3150 +$Comp +L dac_bridge_1 U10 +U 1 1 683F6FDE +P 8950 3700 +F 0 "U10" H 8950 3700 60 0000 C CNN +F 1 "dac_bridge_1" H 8950 3850 60 0000 C CNN +F 2 "" H 8950 3700 60 0000 C CNN +F 3 "" H 8950 3700 60 0000 C CNN + 1 8950 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 2700 9050 3100 +Wire Wire Line + 9050 3100 8250 3100 +Wire Wire Line + 8250 3100 8250 3650 +Wire Wire Line + 8250 3650 8350 3650 +Wire Wire Line + 9500 3650 9500 3450 +Wire Wire Line + 9500 3450 8950 3450 +Wire Wire Line + 8950 3450 8950 3400 +$Comp +L dac_bridge_1 U9 +U 1 1 683FEE44 +P 7300 3950 +F 0 "U9" H 7300 3950 60 0000 C CNN +F 1 "dac_bridge_1" H 7300 4100 60 0000 C CNN +F 2 "" H 7300 3950 60 0000 C CNN +F 3 "" H 7300 3950 60 0000 C CNN + 1 7300 3950 + -1 0 0 1 +$EndComp +$Comp +L adc_bridge_1 U11 +U 1 1 683FEF25 +P 7350 3600 +F 0 "U11" H 7350 3600 60 0000 C CNN +F 1 "adc_bridge_1" H 7350 3750 60 0000 C CNN +F 2 "" H 7350 3600 60 0000 C CNN +F 3 "" H 7350 3600 60 0000 C CNN + 1 7350 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9750 2700 9750 2450 +Wire Wire Line + 10900 2450 10900 2550 +Wire Wire Line + 10900 2550 10750 2550 +Wire Wire Line + 10750 2550 10750 2750 +Wire Wire Line + 10750 2750 10800 2750 +Wire Wire Line + 9750 2450 10900 2450 +$Comp +L dc I1 +U 1 1 684092B5 +P 2650 4550 +F 0 "I1" H 2450 4650 60 0000 C CNN +F 1 "120u" H 2450 4500 60 0000 C CNN +F 2 "R1" H 2350 4550 60 0000 C CNN +F 3 "" H 2650 4550 60 0000 C CNN + 1 2650 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 4650 2900 5250 +Wire Wire Line + 2900 5250 2650 5250 +Wire Wire Line + 2650 5250 2650 5000 +Wire Wire Line + 2650 4100 2900 4100 +Wire Wire Line + 2900 4100 2900 3300 +$Comp +L dc I2 +U 1 1 68409587 +P 5250 2700 +F 0 "I2" H 5050 2800 60 0000 C CNN +F 1 "120u" H 5050 2650 60 0000 C CNN +F 2 "R1" H 4950 2700 60 0000 C CNN +F 3 "" H 5250 2700 60 0000 C CNN + 1 5250 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 3150 5250 3200 +Wire Wire Line + 5250 3200 5000 3200 +Wire Wire Line + 5000 3200 5000 3300 +Wire Wire Line + 5250 2250 5000 2250 +Wire Wire Line + 5000 2250 5000 1950 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ICM7555/ICM7555.sub b/library/SubcircuitLibrary/ICM7555/ICM7555.sub new file mode 100644 index 000000000..011fa5e1d --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/ICM7555.sub @@ -0,0 +1,65 @@ +* Subcircuit ICM7555 +.subckt ICM7555 /1 /2 /3 /4 /5 /6 /7 /8 +* d:\fossee\esim\library\subcircuitlibrary\icm7555\icm7555.cir +.include PMOS-0.5um.lib +.include NMOS-0.5um.lib +m2 /8 net-_m2-pad2_ net-_m1-pad1_ /8 mos_p W=100u L=100u M=1 +m3 /8 net-_m2-pad2_ net-_m2-pad2_ /8 mos_p W=100u L=100u M=1 +m1 net-_m1-pad1_ /6 net-_i1-pad1_ net-_i1-pad1_ mos_n W=100u L=100u M=1 +m4 net-_m2-pad2_ /5 net-_i1-pad1_ net-_i1-pad1_ mos_n W=100u L=100u M=1 +r1 /8 /5 100k +r2 /5 net-_m5-pad2_ 100k +r3 net-_m5-pad2_ /1 100k +m5 net-_i2-pad2_ net-_m5-pad2_ net-_m5-pad3_ net-_i2-pad2_ mos_p W=100u L=100u M=1 +m8 net-_i2-pad2_ /2 net-_m10-pad2_ net-_i2-pad2_ mos_p W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m5-pad3_ /1 /1 mos_n W=100u L=100u M=1 +m7 net-_m10-pad2_ net-_m5-pad3_ /1 /1 mos_n W=100u L=100u M=1 +m11 /8 net-_m1-pad1_ net-_m10-pad1_ /8 mos_p W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ /1 /1 mos_n W=100u L=100u M=1 +m9 net-_m10-pad2_ net-_m9-pad2_ /1 /1 mos_n W=100u L=100u M=1 +* u2 /4 net-_u2-pad2_ d_inverter +* u3 net-_u11-pad2_ net-_u3-pad2_ net-_u3-pad3_ d_nor +* u5 net-_u3-pad3_ net-_u10-pad1_ d_inverter +* u4 net-_u3-pad3_ net-_u4-pad2_ d_inverter +* u6 net-_u10-pad1_ /3 d_inverter +m12 /7 net-_m12-pad2_ /1 /1 mos_n W=100u L=100u M=1 +* u8 net-_u2-pad2_ net-_m9-pad2_ dac_bridge_1 +* u7 net-_m9-pad2_ net-_u3-pad2_ adc_bridge_1 +* u10 net-_u10-pad1_ net-_m12-pad2_ dac_bridge_1 +* u9 net-_u4-pad2_ net-_m10-pad1_ dac_bridge_1 +* u11 net-_m10-pad1_ net-_u11-pad2_ adc_bridge_1 +i1 net-_i1-pad1_ /1 dc 30ua +i2 /8 net-_i2-pad2_ dc 30ua +a1 /4 net-_u2-pad2_ u2 +a2 [net-_u11-pad2_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +a3 net-_u3-pad3_ net-_u10-pad1_ u5 +a4 net-_u3-pad3_ net-_u4-pad2_ u4 +a5 net-_u10-pad1_ /3 u6 +a6 [net-_u2-pad2_ ] [net-_m9-pad2_ ] u8 +a7 [net-_m9-pad2_ ] [net-_u3-pad2_ ] u7 +a8 [net-_u10-pad1_ ] [net-_m12-pad2_ ] u10 +a9 [net-_u4-pad2_ ] [net-_m10-pad1_ ] u9 +a10 [net-_m10-pad1_ ] [net-_u11-pad2_ ] u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends ICM7555 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ICM7555/ICM7555_Previous_Values.xml b/library/SubcircuitLibrary/ICM7555/ICM7555_Previous_Values.xml new file mode 100644 index 000000000..bb8798a16 --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/ICM7555_Previous_Values.xml @@ -0,0 +1 @@ +dc30uadc30uad_inverterd_nord_inverterd_inverterd_inverterdac_bridgeadc_bridgeadc_bridgedac_bridgedac_bridgeadc_bridgeD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.libD:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes019secsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ICM7555/NMOS-0.5um.lib b/library/SubcircuitLibrary/ICM7555/NMOS-0.5um.lib new file mode 100644 index 000000000..2e6f4635c --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 ) \ No newline at end of file diff --git a/library/SubcircuitLibrary/ICM7555/PMOS-0.5um.lib b/library/SubcircuitLibrary/ICM7555/PMOS-0.5um.lib new file mode 100644 index 000000000..848e8b051 --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/PMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 ) \ No newline at end of file diff --git a/library/SubcircuitLibrary/ICM7555/analysis b/library/SubcircuitLibrary/ICM7555/analysis new file mode 100644 index 000000000..f1532c673 --- /dev/null +++ b/library/SubcircuitLibrary/ICM7555/analysis @@ -0,0 +1 @@ +.tran 1e-00 9e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS295B/SN74LS295B-cache.lib b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B-cache.lib new file mode 100644 index 000000000..5cbb975fd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B-cache.lib @@ -0,0 +1,140 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# SR_FF1 +# +DEF SR_FF1 X 0 40 Y Y 1 F N +F0 "X" 0 -550 60 H V C CNN +F1 "SR_FF1" 0 250 60 H V C CNN +F2 "" 0 250 60 H I C CNN +F3 "" 0 250 60 H I C CNN +DRAW +S -250 200 250 -500 0 1 0 N +X S 1 -450 100 200 R 50 50 1 1 I +X CLK 2 -450 -100 200 R 50 50 1 1 I +X R 3 -450 -300 200 R 50 50 1 1 I +X QBar 4 450 -200 200 L 50 50 1 1 O +X Q 5 450 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.cir b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.cir new file mode 100644 index 000000000..815836afc --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.cir @@ -0,0 +1,39 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS295B\SN74LS295B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 11:49:39 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad2_ /1 Net-_U5-Pad3_ d_and +U8 /2 Net-_U13-Pad2_ Net-_U7-Pad1_ d_and +U7 Net-_U7-Pad1_ Net-_U5-Pad3_ Net-_U6-Pad1_ d_nor +U9 Net-_U1-Pad2_ Net-_U10-Pad1_ Net-_U11-Pad2_ d_and +U13 /3 Net-_U13-Pad2_ Net-_U11-Pad1_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nor +U14 Net-_U1-Pad2_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U18 /4 Net-_U13-Pad2_ Net-_U15-Pad1_ d_and +U15 Net-_U15-Pad1_ Net-_U14-Pad3_ Net-_U15-Pad3_ d_nor +U19 Net-_U1-Pad2_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and +U22 /5 Net-_U13-Pad2_ Net-_U20-Pad1_ d_and +U20 Net-_U20-Pad1_ Net-_U19-Pad3_ Net-_U20-Pad3_ d_nor +X1 Net-_U6-Pad2_ Net-_U2-Pad2_ Net-_U6-Pad1_ ? Net-_U10-Pad1_ SR_FF1 +X2 Net-_U12-Pad2_ Net-_U2-Pad2_ Net-_U11-Pad3_ ? Net-_U14-Pad2_ SR_FF1 +X3 Net-_U16-Pad2_ Net-_U2-Pad2_ Net-_U15-Pad3_ ? Net-_U19-Pad2_ SR_FF1 +X4 Net-_U21-Pad2_ Net-_U2-Pad2_ Net-_U20-Pad3_ ? Net-_U24-Pad1_ SR_FF1 +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ d_inverter +U2 /9 Net-_U2-Pad2_ d_inverter +U12 Net-_U11-Pad3_ Net-_U12-Pad2_ d_inverter +U16 Net-_U15-Pad3_ Net-_U16-Pad2_ d_inverter +U21 Net-_U20-Pad3_ Net-_U21-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ /13 d_tristate +U17 Net-_U14-Pad2_ Net-_U10-Pad2_ /12 d_tristate +U23 Net-_U19-Pad2_ Net-_U10-Pad2_ /11 d_tristate +U24 Net-_U24-Pad1_ Net-_U10-Pad2_ /10 d_tristate +U3 /8 Net-_U10-Pad2_ d_buffer +U1 /6 Net-_U1-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U13-Pad2_ d_inverter +U25 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.cir.out b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.cir.out new file mode 100644 index 000000000..a695bbee1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.cir.out @@ -0,0 +1,113 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls295b\sn74ls295b.cir + +.include SR_FF1.sub +* u5 net-_u1-pad2_ /1 net-_u5-pad3_ d_and +* u8 /2 net-_u13-pad2_ net-_u7-pad1_ d_and +* u7 net-_u7-pad1_ net-_u5-pad3_ net-_u6-pad1_ d_nor +* u9 net-_u1-pad2_ net-_u10-pad1_ net-_u11-pad2_ d_and +* u13 /3 net-_u13-pad2_ net-_u11-pad1_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor +* u14 net-_u1-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u18 /4 net-_u13-pad2_ net-_u15-pad1_ d_and +* u15 net-_u15-pad1_ net-_u14-pad3_ net-_u15-pad3_ d_nor +* u19 net-_u1-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u22 /5 net-_u13-pad2_ net-_u20-pad1_ d_and +* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_nor +x1 net-_u6-pad2_ net-_u2-pad2_ net-_u6-pad1_ ? net-_u10-pad1_ SR_FF1 +x2 net-_u12-pad2_ net-_u2-pad2_ net-_u11-pad3_ ? net-_u14-pad2_ SR_FF1 +x3 net-_u16-pad2_ net-_u2-pad2_ net-_u15-pad3_ ? net-_u19-pad2_ SR_FF1 +x4 net-_u21-pad2_ net-_u2-pad2_ net-_u20-pad3_ ? net-_u24-pad1_ SR_FF1 +* u6 net-_u6-pad1_ net-_u6-pad2_ d_inverter +* u2 /9 net-_u2-pad2_ d_inverter +* u12 net-_u11-pad3_ net-_u12-pad2_ d_inverter +* u16 net-_u15-pad3_ net-_u16-pad2_ d_inverter +* u21 net-_u20-pad3_ net-_u21-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ /13 d_tristate +* u17 net-_u14-pad2_ net-_u10-pad2_ /12 d_tristate +* u23 net-_u19-pad2_ net-_u10-pad2_ /11 d_tristate +* u24 net-_u24-pad1_ net-_u10-pad2_ /10 d_tristate +* u3 /8 net-_u10-pad2_ d_buffer +* u1 /6 net-_u1-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u13-pad2_ d_inverter +* u25 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? port +a1 [net-_u1-pad2_ /1 ] net-_u5-pad3_ u5 +a2 [/2 net-_u13-pad2_ ] net-_u7-pad1_ u8 +a3 [net-_u7-pad1_ net-_u5-pad3_ ] net-_u6-pad1_ u7 +a4 [net-_u1-pad2_ net-_u10-pad1_ ] net-_u11-pad2_ u9 +a5 [/3 net-_u13-pad2_ ] net-_u11-pad1_ u13 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a7 [net-_u1-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a8 [/4 net-_u13-pad2_ ] net-_u15-pad1_ u18 +a9 [net-_u15-pad1_ net-_u14-pad3_ ] net-_u15-pad3_ u15 +a10 [net-_u1-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a11 [/5 net-_u13-pad2_ ] net-_u20-pad1_ u22 +a12 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20 +a13 net-_u6-pad1_ net-_u6-pad2_ u6 +a14 /9 net-_u2-pad2_ u2 +a15 net-_u11-pad3_ net-_u12-pad2_ u12 +a16 net-_u15-pad3_ net-_u16-pad2_ u16 +a17 net-_u20-pad3_ net-_u21-pad2_ u21 +a18 net-_u10-pad1_ net-_u10-pad2_ /13 u10 +a19 net-_u14-pad2_ net-_u10-pad2_ /12 u17 +a20 net-_u19-pad2_ net-_u10-pad2_ /11 u23 +a21 net-_u24-pad1_ net-_u10-pad2_ /10 u24 +a22 /8 net-_u10-pad2_ u3 +a23 /6 net-_u1-pad2_ u1 +a24 net-_u1-pad2_ net-_u13-pad2_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.pro b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.pro new file mode 100644 index 000000000..54ab6e2be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.pro @@ -0,0 +1,83 @@ +update=07/06/25 11:31:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.sch b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.sch new file mode 100644 index 000000000..066be999b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.sch @@ -0,0 +1,818 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U5 +U 1 1 686A1170 +P 5400 4000 +F 0 "U5" H 5400 4000 60 0000 C CNN +F 1 "d_and" H 5450 4100 60 0000 C CNN +F 2 "" H 5400 4000 60 0000 C CNN +F 3 "" H 5400 4000 60 0000 C CNN + 1 5400 4000 + 0 1 1 0 +$EndComp +$Comp +L d_and U8 +U 1 1 686A1251 +P 6100 4000 +F 0 "U8" H 6100 4000 60 0000 C CNN +F 1 "d_and" H 6150 4100 60 0000 C CNN +F 2 "" H 6100 4000 60 0000 C CNN +F 3 "" H 6100 4000 60 0000 C CNN + 1 6100 4000 + 0 1 1 0 +$EndComp +$Comp +L d_nor U7 +U 1 1 686A125B +P 5750 5200 +F 0 "U7" H 5750 5200 60 0000 C CNN +F 1 "d_nor" H 5800 5300 60 0000 C CNN +F 2 "" H 5750 5200 60 0000 C CNN +F 3 "" H 5750 5200 60 0000 C CNN + 1 5750 5200 + 0 1 1 0 +$EndComp +$Comp +L d_and U9 +U 1 1 686A1394 +P 6850 3950 +F 0 "U9" H 6850 3950 60 0000 C CNN +F 1 "d_and" H 6900 4050 60 0000 C CNN +F 2 "" H 6850 3950 60 0000 C CNN +F 3 "" H 6850 3950 60 0000 C CNN + 1 6850 3950 + 0 1 1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 686A139A +P 7550 3950 +F 0 "U13" H 7550 3950 60 0000 C CNN +F 1 "d_and" H 7600 4050 60 0000 C CNN +F 2 "" H 7550 3950 60 0000 C CNN +F 3 "" H 7550 3950 60 0000 C CNN + 1 7550 3950 + 0 1 1 0 +$EndComp +$Comp +L d_nor U11 +U 1 1 686A13A0 +P 7200 5150 +F 0 "U11" H 7200 5150 60 0000 C CNN +F 1 "d_nor" H 7250 5250 60 0000 C CNN +F 2 "" H 7200 5150 60 0000 C CNN +F 3 "" H 7200 5150 60 0000 C CNN + 1 7200 5150 + 0 1 1 0 +$EndComp +$Comp +L d_and U14 +U 1 1 686A1494 +P 8350 3950 +F 0 "U14" H 8350 3950 60 0000 C CNN +F 1 "d_and" H 8400 4050 60 0000 C CNN +F 2 "" H 8350 3950 60 0000 C CNN +F 3 "" H 8350 3950 60 0000 C CNN + 1 8350 3950 + 0 1 1 0 +$EndComp +$Comp +L d_and U18 +U 1 1 686A149A +P 9050 3950 +F 0 "U18" H 9050 3950 60 0000 C CNN +F 1 "d_and" H 9100 4050 60 0000 C CNN +F 2 "" H 9050 3950 60 0000 C CNN +F 3 "" H 9050 3950 60 0000 C CNN + 1 9050 3950 + 0 1 1 0 +$EndComp +$Comp +L d_nor U15 +U 1 1 686A14A0 +P 8700 5150 +F 0 "U15" H 8700 5150 60 0000 C CNN +F 1 "d_nor" H 8750 5250 60 0000 C CNN +F 2 "" H 8700 5150 60 0000 C CNN +F 3 "" H 8700 5150 60 0000 C CNN + 1 8700 5150 + 0 1 1 0 +$EndComp +$Comp +L d_and U19 +U 1 1 686A14AA +P 9800 3900 +F 0 "U19" H 9800 3900 60 0000 C CNN +F 1 "d_and" H 9850 4000 60 0000 C CNN +F 2 "" H 9800 3900 60 0000 C CNN +F 3 "" H 9800 3900 60 0000 C CNN + 1 9800 3900 + 0 1 1 0 +$EndComp +$Comp +L d_and U22 +U 1 1 686A14B0 +P 10500 3900 +F 0 "U22" H 10500 3900 60 0000 C CNN +F 1 "d_and" H 10550 4000 60 0000 C CNN +F 2 "" H 10500 3900 60 0000 C CNN +F 3 "" H 10500 3900 60 0000 C CNN + 1 10500 3900 + 0 1 1 0 +$EndComp +$Comp +L d_nor U20 +U 1 1 686A14B6 +P 10150 5100 +F 0 "U20" H 10150 5100 60 0000 C CNN +F 1 "d_nor" H 10200 5200 60 0000 C CNN +F 2 "" H 10150 5100 60 0000 C CNN +F 3 "" H 10150 5100 60 0000 C CNN + 1 10150 5100 + 0 1 1 0 +$EndComp +$Comp +L SR_FF1 X1 +U 1 1 686A171A +P 6500 6450 +F 0 "X1" H 6500 5900 60 0000 C CNN +F 1 "SR_FF1" H 6500 6700 60 0000 C CNN +F 2 "" H 6500 6700 60 0001 C CNN +F 3 "" H 6500 6700 60 0001 C CNN + 1 6500 6450 + 1 0 0 -1 +$EndComp +$Comp +L SR_FF1 X2 +U 1 1 686A1934 +P 8050 6500 +F 0 "X2" H 8050 5950 60 0000 C CNN +F 1 "SR_FF1" H 8050 6750 60 0000 C CNN +F 2 "" H 8050 6750 60 0001 C CNN +F 3 "" H 8050 6750 60 0001 C CNN + 1 8050 6500 + 1 0 0 -1 +$EndComp +$Comp +L SR_FF1 X3 +U 1 1 686A198B +P 9600 6500 +F 0 "X3" H 9600 5950 60 0000 C CNN +F 1 "SR_FF1" H 9600 6750 60 0000 C CNN +F 2 "" H 9600 6750 60 0001 C CNN +F 3 "" H 9600 6750 60 0001 C CNN + 1 9600 6500 + 1 0 0 -1 +$EndComp +$Comp +L SR_FF1 X4 +U 1 1 686A19FA +P 11300 6500 +F 0 "X4" H 11300 5950 60 0000 C CNN +F 1 "SR_FF1" H 11300 6750 60 0000 C CNN +F 2 "" H 11300 6750 60 0001 C CNN +F 3 "" H 11300 6750 60 0001 C CNN + 1 11300 6500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 686A1A24 +P 5550 6250 +F 0 "U6" H 5550 6150 60 0000 C CNN +F 1 "d_inverter" H 5550 6400 60 0000 C CNN +F 2 "" H 5600 6200 60 0000 C CNN +F 3 "" H 5600 6200 60 0000 C CNN + 1 5550 6250 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U2 +U 1 1 686A1B29 +P 4200 5800 +F 0 "U2" H 4200 5700 60 0000 C CNN +F 1 "d_inverter" H 4200 5950 60 0000 C CNN +F 2 "" H 4250 5750 60 0000 C CNN +F 3 "" H 4250 5750 60 0000 C CNN + 1 4200 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 686A1C6A +P 7250 6300 +F 0 "U12" H 7250 6200 60 0000 C CNN +F 1 "d_inverter" H 7250 6450 60 0000 C CNN +F 2 "" H 7300 6250 60 0000 C CNN +F 3 "" H 7300 6250 60 0000 C CNN + 1 7250 6300 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U16 +U 1 1 686A1DEE +P 8750 6250 +F 0 "U16" H 8750 6150 60 0000 C CNN +F 1 "d_inverter" H 8750 6400 60 0000 C CNN +F 2 "" H 8800 6200 60 0000 C CNN +F 3 "" H 8800 6200 60 0000 C CNN + 1 8750 6250 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U21 +U 1 1 686A1EE7 +P 10350 6250 +F 0 "U21" H 10350 6150 60 0000 C CNN +F 1 "d_inverter" H 10350 6400 60 0000 C CNN +F 2 "" H 10400 6200 60 0000 C CNN +F 3 "" H 10400 6200 60 0000 C CNN + 1 10350 6250 + 0 1 1 0 +$EndComp +NoConn ~ 6950 6650 +NoConn ~ 8500 6700 +NoConn ~ 10050 6700 +NoConn ~ 11750 6700 +$Comp +L d_tristate U10 +U 1 1 686A2686 +P 6950 8100 +F 0 "U10" H 6700 8350 60 0000 C CNN +F 1 "d_tristate" H 6750 8550 60 0000 C CNN +F 2 "" H 6850 8450 60 0000 C CNN +F 3 "" H 6850 8450 60 0000 C CNN + 1 6950 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U17 +U 1 1 686A277C +P 8850 8100 +F 0 "U17" H 8600 8350 60 0000 C CNN +F 1 "d_tristate" H 8650 8550 60 0000 C CNN +F 2 "" H 8750 8450 60 0000 C CNN +F 3 "" H 8750 8450 60 0000 C CNN + 1 8850 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U23 +U 1 1 686A281A +P 10550 8100 +F 0 "U23" H 10300 8350 60 0000 C CNN +F 1 "d_tristate" H 10350 8550 60 0000 C CNN +F 2 "" H 10450 8450 60 0000 C CNN +F 3 "" H 10450 8450 60 0000 C CNN + 1 10550 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U24 +U 1 1 686A2820 +P 12450 8100 +F 0 "U24" H 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+Connection ~ 8450 3000 +Wire Wire Line + 6950 3500 6950 3000 +Connection ~ 6950 3000 +Wire Wire Line + 5500 3550 5500 3000 +Connection ~ 5500 3000 +Wire Wire Line + 3250 2700 2700 2700 +Text Label 6200 2300 0 60 ~ 0 +2 +Text Label 7650 2300 0 60 ~ 0 +3 +Text Label 9150 2300 0 60 ~ 0 +4 +Text Label 10600 2250 0 60 ~ 0 +5 +Text Label 2700 2700 0 60 ~ 0 +6 +Text Label 3600 3400 0 60 ~ 0 +1 +Text Label 3300 5800 0 60 ~ 0 +9 +Text Label 3400 8550 0 60 ~ 0 +8 +Text Label 7900 8850 0 60 ~ 0 +13 +Text Label 9600 8800 0 60 ~ 0 +12 +Text Label 11300 8800 0 60 ~ 0 +11 +Text Label 13350 8800 0 60 ~ 0 +10 +$Comp +L PORT U25 +U 1 1 686A7E3C +P 3350 3400 +F 0 "U25" H 3400 3500 30 0000 C CNN +F 1 "PORT" H 3350 3400 30 0000 C CNN +F 2 "" H 3350 3400 60 0000 C CNN +F 3 "" H 3350 3400 60 0000 C CNN + 1 3350 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 4 1 686A7EE5 +P 9150 2050 +F 0 "U25" H 9200 2150 30 0000 C CNN +F 1 "PORT" H 9150 2050 30 0000 C CNN +F 2 "" H 9150 2050 60 0000 C CNN +F 3 "" H 9150 2050 60 0000 C CNN + 4 9150 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U25 +U 7 1 686A7FAA +P 3400 3900 +F 0 "U25" H 3450 4000 30 0000 C CNN +F 1 "PORT" H 3400 3900 30 0000 C CNN +F 2 "" H 3400 3900 60 0000 C CNN +F 3 "" H 3400 3900 60 0000 C CNN + 7 3400 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 10 1 686A8005 +P 13350 9050 +F 0 "U25" H 13400 9150 30 0000 C CNN +F 1 "PORT" H 13350 9050 30 0000 C CNN +F 2 "" H 13350 9050 60 0000 C CNN +F 3 "" H 13350 9050 60 0000 C CNN + 10 13350 9050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U25 +U 14 1 686A805E +P 4350 3900 +F 0 "U25" H 4400 4000 30 0000 C CNN +F 1 "PORT" H 4350 3900 30 0000 C CNN +F 2 "" H 4350 3900 60 0000 C CNN +F 3 "" H 4350 3900 60 0000 C CNN + 14 4350 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 2 1 686A80C7 +P 6200 2050 +F 0 "U25" H 6250 2150 30 0000 C CNN +F 1 "PORT" H 6200 2050 30 0000 C CNN +F 2 "" H 6200 2050 60 0000 C CNN +F 3 "" H 6200 2050 60 0000 C CNN + 2 6200 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U25 +U 5 1 686A8134 +P 10600 2000 +F 0 "U25" H 10650 2100 30 0000 C CNN +F 1 "PORT" H 10600 2000 30 0000 C CNN +F 2 "" H 10600 2000 60 0000 C CNN +F 3 "" H 10600 2000 60 0000 C CNN + 5 10600 2000 + 0 1 1 0 +$EndComp +$Comp +L PORT U25 +U 8 1 686A8191 +P 3150 8550 +F 0 "U25" H 3200 8650 30 0000 C CNN +F 1 "PORT" H 3150 8550 30 0000 C CNN +F 2 "" H 3150 8550 60 0000 C CNN +F 3 "" H 3150 8550 60 0000 C CNN + 8 3150 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 11 1 686A81F2 +P 11300 9050 +F 0 "U25" H 11350 9150 30 0000 C CNN +F 1 "PORT" H 11300 9050 30 0000 C CNN +F 2 "" H 11300 9050 60 0000 C CNN +F 3 "" H 11300 9050 60 0000 C CNN + 11 11300 9050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U25 +U 13 1 686A8253 +P 7900 9100 +F 0 "U25" H 7950 9200 30 0000 C CNN +F 1 "PORT" H 7900 9100 30 0000 C CNN +F 2 "" H 7900 9100 60 0000 C CNN +F 3 "" H 7900 9100 60 0000 C CNN + 13 7900 9100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U25 +U 3 1 686A82C2 +P 7650 2050 +F 0 "U25" H 7700 2150 30 0000 C CNN +F 1 "PORT" H 7650 2050 30 0000 C CNN +F 2 "" H 7650 2050 60 0000 C CNN +F 3 "" H 7650 2050 60 0000 C CNN + 3 7650 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U25 +U 6 1 686A832D +P 2450 2700 +F 0 "U25" H 2500 2800 30 0000 C CNN +F 1 "PORT" H 2450 2700 30 0000 C CNN +F 2 "" H 2450 2700 60 0000 C CNN +F 3 "" H 2450 2700 60 0000 C CNN + 6 2450 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 9 1 686A8396 +P 3050 5800 +F 0 "U25" H 3100 5900 30 0000 C CNN +F 1 "PORT" H 3050 5800 30 0000 C CNN +F 2 "" H 3050 5800 60 0000 C CNN +F 3 "" H 3050 5800 60 0000 C CNN + 9 3050 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 12 1 686A8401 +P 9600 9050 +F 0 "U25" H 9650 9150 30 0000 C CNN +F 1 "PORT" H 9600 9050 30 0000 C CNN +F 2 "" H 9600 9050 60 0000 C CNN +F 3 "" H 9600 9050 60 0000 C CNN + 12 9600 9050 + 0 -1 -1 0 +$EndComp +NoConn ~ 4600 3900 +NoConn ~ 3650 3900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.sub b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.sub new file mode 100644 index 000000000..6d06c32df --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B.sub @@ -0,0 +1,107 @@ +* Subcircuit SN74LS295B +.subckt SN74LS295B /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? +* d:\fossee\esim\library\subcircuitlibrary\sn74ls295b\sn74ls295b.cir +.include SR_FF1.sub +* u5 net-_u1-pad2_ /1 net-_u5-pad3_ d_and +* u8 /2 net-_u13-pad2_ net-_u7-pad1_ d_and +* u7 net-_u7-pad1_ net-_u5-pad3_ net-_u6-pad1_ d_nor +* u9 net-_u1-pad2_ net-_u10-pad1_ net-_u11-pad2_ d_and +* u13 /3 net-_u13-pad2_ net-_u11-pad1_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor +* u14 net-_u1-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u18 /4 net-_u13-pad2_ net-_u15-pad1_ d_and +* u15 net-_u15-pad1_ net-_u14-pad3_ net-_u15-pad3_ d_nor +* u19 net-_u1-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u22 /5 net-_u13-pad2_ net-_u20-pad1_ d_and +* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_nor +x1 net-_u6-pad2_ net-_u2-pad2_ net-_u6-pad1_ ? net-_u10-pad1_ SR_FF1 +x2 net-_u12-pad2_ net-_u2-pad2_ net-_u11-pad3_ ? net-_u14-pad2_ SR_FF1 +x3 net-_u16-pad2_ net-_u2-pad2_ net-_u15-pad3_ ? net-_u19-pad2_ SR_FF1 +x4 net-_u21-pad2_ net-_u2-pad2_ net-_u20-pad3_ ? net-_u24-pad1_ SR_FF1 +* u6 net-_u6-pad1_ net-_u6-pad2_ d_inverter +* u2 /9 net-_u2-pad2_ d_inverter +* u12 net-_u11-pad3_ net-_u12-pad2_ d_inverter +* u16 net-_u15-pad3_ net-_u16-pad2_ d_inverter +* u21 net-_u20-pad3_ net-_u21-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ /13 d_tristate +* u17 net-_u14-pad2_ net-_u10-pad2_ /12 d_tristate +* u23 net-_u19-pad2_ net-_u10-pad2_ /11 d_tristate +* u24 net-_u24-pad1_ net-_u10-pad2_ /10 d_tristate +* u3 /8 net-_u10-pad2_ d_buffer +* u1 /6 net-_u1-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u13-pad2_ d_inverter +a1 [net-_u1-pad2_ /1 ] net-_u5-pad3_ u5 +a2 [/2 net-_u13-pad2_ ] net-_u7-pad1_ u8 +a3 [net-_u7-pad1_ net-_u5-pad3_ ] net-_u6-pad1_ u7 +a4 [net-_u1-pad2_ net-_u10-pad1_ ] net-_u11-pad2_ u9 +a5 [/3 net-_u13-pad2_ ] net-_u11-pad1_ u13 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a7 [net-_u1-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a8 [/4 net-_u13-pad2_ ] net-_u15-pad1_ u18 +a9 [net-_u15-pad1_ net-_u14-pad3_ ] net-_u15-pad3_ u15 +a10 [net-_u1-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a11 [/5 net-_u13-pad2_ ] net-_u20-pad1_ u22 +a12 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20 +a13 net-_u6-pad1_ net-_u6-pad2_ u6 +a14 /9 net-_u2-pad2_ u2 +a15 net-_u11-pad3_ net-_u12-pad2_ u12 +a16 net-_u15-pad3_ net-_u16-pad2_ u16 +a17 net-_u20-pad3_ net-_u21-pad2_ u21 +a18 net-_u10-pad1_ net-_u10-pad2_ /13 u10 +a19 net-_u14-pad2_ net-_u10-pad2_ /12 u17 +a20 net-_u19-pad2_ net-_u10-pad2_ /11 u23 +a21 net-_u24-pad1_ net-_u10-pad2_ /10 u24 +a22 /8 net-_u10-pad2_ u3 +a23 /6 net-_u1-pad2_ u1 +a24 net-_u1-pad2_ net-_u13-pad2_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS295B \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS295B/SN74LS295B_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B_Previous_Values.xml new file mode 100644 index 000000000..3ec070974 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SN74LS295B_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nord_andd_andd_nord_andd_andd_nord_andd_andd_nord_inverterd_inverterd_inverterd_inverterd_inverterd_tristated_tristated_tristated_tristated_bufferd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS295B/SR_FF1-cache.lib b/library/SubcircuitLibrary/SN74LS295B/SR_FF1-cache.lib new file mode 100644 index 000000000..ce6d8814c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SR_FF1-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS295B/SR_FF1.cir b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.cir new file mode 100644 index 000000000..ba6a8f971 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.cir @@ -0,0 +1,15 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF\SR_FF.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 17:59:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U4 Net-_U2-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_nand +U5 Net-_U1-Pad5_ Net-_U3-Pad3_ Net-_U1-Pad4_ d_nand +U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS295B/SR_FF1.cir.out b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.cir.out new file mode 100644 index 000000000..33d1c4912 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.cir.out @@ -0,0 +1,28 @@ +* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand +* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4 +a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS295B/SR_FF1.pro b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS295B/SR_FF1.sch b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.sch new file mode 100644 index 000000000..58667c880 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.sch @@ -0,0 +1,198 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 686919A7 +P 4350 2800 +F 0 "U2" H 4350 2800 60 0000 C CNN +F 1 "d_nand" H 4400 2900 60 0000 C CNN +F 2 "" H 4350 2800 60 0000 C CNN +F 3 "" H 4350 2800 60 0000 C CNN + 1 4350 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 686919EC +P 5850 2800 +F 0 "U4" H 5850 2800 60 0000 C CNN +F 1 "d_nand" H 5900 2900 60 0000 C CNN +F 2 "" H 5850 2800 60 0000 C CNN +F 3 "" H 5850 2800 60 0000 C CNN + 1 5850 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68691A1F +P 5900 4000 +F 0 "U5" H 5900 4000 60 0000 C CNN +F 1 "d_nand" H 5950 4100 60 0000 C CNN +F 2 "" H 5900 4000 60 0000 C CNN +F 3 "" H 5900 4000 60 0000 C CNN + 1 5900 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 2750 6800 2750 +Wire Wire Line + 6350 3950 7000 3950 +Wire Wire Line + 6700 2750 6700 3300 +Wire Wire Line + 6700 3300 5200 3300 +Wire Wire Line + 5200 3300 5200 3900 +Wire Wire Line + 5200 3900 5450 3900 +Connection ~ 6700 2750 +Wire Wire Line + 6550 3950 6550 3050 +Wire Wire Line + 6550 3050 5250 3050 +Wire Wire Line + 5250 3050 5250 2800 +Wire Wire Line + 5250 2800 5400 2800 +Connection ~ 6550 3950 +$Comp +L d_nand U3 +U 1 1 68691A8B +P 4350 4050 +F 0 "U3" H 4350 4050 60 0000 C CNN +F 1 "d_nand" H 4400 4150 60 0000 C CNN +F 2 "" H 4350 4050 60 0000 C CNN +F 3 "" H 4350 4050 60 0000 C CNN + 1 4350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 2750 4900 2750 +Wire Wire Line + 4900 2750 4900 2700 +Wire Wire Line + 4900 2700 5400 2700 +Wire Wire Line + 4800 4000 5450 4000 +Wire Wire Line + 3900 2800 3600 2800 +Wire Wire Line + 3600 2800 3600 3950 +Wire Wire Line + 3600 3950 3900 3950 +Wire Wire Line + 3900 2700 3150 2700 +Wire Wire Line + 3900 4050 3150 4050 +Wire Wire Line + 3600 3350 2400 3350 +Connection ~ 3600 3350 +$Comp +L PORT U1 +U 4 1 68691B28 +P 7250 3950 +F 0 "U1" H 7300 4050 30 0000 C CNN +F 1 "PORT" H 7250 3950 30 0000 C CNN +F 2 "" H 7250 3950 60 0000 C CNN +F 3 "" H 7250 3950 60 0000 C CNN + 4 7250 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68691BB8 +P 7050 2750 +F 0 "U1" H 7100 2850 30 0000 C CNN +F 1 "PORT" H 7050 2750 30 0000 C CNN +F 2 "" H 7050 2750 60 0000 C CNN +F 3 "" H 7050 2750 60 0000 C CNN + 5 7050 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 68691BFB +P 2900 4050 +F 0 "U1" H 2950 4150 30 0000 C CNN +F 1 "PORT" H 2900 4050 30 0000 C CNN +F 2 "" H 2900 4050 60 0000 C CNN +F 3 "" H 2900 4050 60 0000 C CNN + 3 2900 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68691C28 +P 2150 3350 +F 0 "U1" H 2200 3450 30 0000 C CNN +F 1 "PORT" H 2150 3350 30 0000 C CNN +F 2 "" H 2150 3350 60 0000 C CNN +F 3 "" H 2150 3350 60 0000 C CNN + 2 2150 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68691C55 +P 2900 2700 +F 0 "U1" H 2950 2800 30 0000 C CNN +F 1 "PORT" H 2900 2700 30 0000 C CNN +F 2 "" H 2900 2700 60 0000 C CNN +F 3 "" H 2900 2700 60 0000 C CNN + 1 2900 2700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS295B/SR_FF1.sub b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.sub new file mode 100644 index 000000000..97dd47178 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SR_FF1.sub @@ -0,0 +1,22 @@ +* Subcircuit SR_FF +.subckt SR_FF net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand +* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4 +a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SR_FF \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS295B/SR_FF1_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS295B/SR_FF1_Previous_Values.xml new file mode 100644 index 000000000..d73809c15 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/SR_FF1_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_nandd_nand \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS295B/analysis b/library/SubcircuitLibrary/SN74LS295B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS295B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file