diff --git a/edg/BoardTop.py b/edg/BoardTop.py index 498b26369..f42ed7d41 100644 --- a/edg/BoardTop.py +++ b/edg/BoardTop.py @@ -3,7 +3,7 @@ class BaseBoardTop(DesignTop): """Design top with refinements for intermediate-level (0603+ SMD), hand-solderable components.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.refdes_prefix = self.Parameter(StringExpr()) self.assign(self.refdes_prefix, "") # override with refinements @@ -52,7 +52,7 @@ class BoardTop(BaseBoardTop): class JlcToolingHole(InternalSubcircuit, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'H', 'edg:JlcToolingHole_1.152mm', @@ -62,7 +62,7 @@ def contents(self): class JlcToolingHoles(InternalSubcircuit, Block): - def contents(self): + def contents(self) -> None: super().contents() self.th1 = self.Block(JlcToolingHole()) self.th2 = self.Block(JlcToolingHole()) @@ -111,7 +111,7 @@ def refinements(self) -> Refinements: class JlcBoardTop(JlcTopRefinements): """Design top with refinements to use parts from JLC's assembly service and including the tooling holes""" - def contents(self): + def contents(self) -> None: super().contents() self.jlc_th = self.Block(JlcToolingHoles()) diff --git a/edg/abstract_parts/AbstractAnalogSwitch.py b/edg/abstract_parts/AbstractAnalogSwitch.py index ba059503b..aba05c034 100644 --- a/edg/abstract_parts/AbstractAnalogSwitch.py +++ b/edg/abstract_parts/AbstractAnalogSwitch.py @@ -43,7 +43,7 @@ def __init__(self, switch_size: IntLike = 0): self.switch_size = self.ArgParameter(switch_size) self.generator_param(self.switch_size, self.inputs.requested(), self.control_gnd.is_connected()) - def generate(self): + def generate(self) -> None: import math super().generate() @@ -132,7 +132,7 @@ def __init__(self) -> None: self.generator_param(self.inputs.requested(), self.control_gnd.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() self.inputs.defined() for elt in self.get(self.inputs.requested()): @@ -175,7 +175,7 @@ def __init__(self) -> None: self.generator_param(self.outputs.requested()) - def generate(self): + def generate(self) -> None: super().generate() self.outputs.defined() for elt in self.get(self.outputs.requested()): diff --git a/edg/abstract_parts/AbstractAntenna.py b/edg/abstract_parts/AbstractAntenna.py index 2aea463c1..752a9087f 100644 --- a/edg/abstract_parts/AbstractAntenna.py +++ b/edg/abstract_parts/AbstractAntenna.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .Categories import * from .PartsTable import PartsTableColumn, PartsTableRow @@ -30,7 +32,7 @@ class TableAntenna(Antenna, PartsTableSelector, GeneratorBlock): IMPEDANCE = PartsTableColumn(Range) POWER_RATING = PartsTableColumn(Range) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.frequency, self.power, self.impedance) diff --git a/edg/abstract_parts/AbstractBjt.py b/edg/abstract_parts/AbstractBjt.py index 09dbbb534..74c82d126 100644 --- a/edg/abstract_parts/AbstractBjt.py +++ b/edg/abstract_parts/AbstractBjt.py @@ -1,4 +1,4 @@ -from typing import Dict +from typing import Dict, Any from ..electronics_model import * from .Categories import * @@ -41,11 +41,11 @@ def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]: return {'B': self.base, 'C': self.collector, 'E': self.emitter} @staticmethod - def Npn(*args, **kwargs) -> 'Bjt': + def Npn(*args: Any, **kwargs: Any) -> 'Bjt': return Bjt(*args, **kwargs, channel='NPN') @staticmethod - def Pnp(*args, **kwargs) -> 'Bjt': + def Pnp(*args: Any, **kwargs: Any) -> 'Bjt': return Bjt(*args, **kwargs, channel='PNP') def __init__(self, collector_voltage: RangeLike, collector_current: RangeLike, *, @@ -68,7 +68,7 @@ def __init__(self, collector_voltage: RangeLike, collector_current: RangeLike, * self.actual_power_rating = self.Parameter(RangeExpr()) self.actual_gain = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -90,7 +90,7 @@ class TableBjt(PartsTableSelector, Bjt): POWER_RATING = PartsTableColumn(Range) CHANNEL = PartsTableColumn(str) # either 'PNP' or 'NPN' - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.collector_voltage, self.collector_current, self.gain, self.power, self.channel) diff --git a/edg/abstract_parts/AbstractCapacitor.py b/edg/abstract_parts/AbstractCapacitor.py index 419257324..e8f420beb 100644 --- a/edg/abstract_parts/AbstractCapacitor.py +++ b/edg/abstract_parts/AbstractCapacitor.py @@ -106,7 +106,7 @@ def __init__(self, capacitance: RangeLike, voltage: RangeLike, *, self.actual_capacitance = self.Parameter(RangeExpr()) self.actual_voltage_rating = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -149,7 +149,7 @@ def parse_capacitor(cls, value: str) -> Tuple[Range, Range]: def block_from_symbol(cls, symbol_name: str, properties: Mapping[str, str]) -> 'Capacitor': return Capacitor(*cls.parse_capacitor(properties['Value'])) - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.pos = self.Port(Passive.empty()) @@ -176,7 +176,7 @@ class TableCapacitor(PartsTableSelector, Capacitor): NOMINAL_CAPACITANCE = PartsTableColumn(float) # nominal capacitance, even with asymmetrical tolerances VOLTAGE_RATING = PartsTableColumn(Range) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.capacitance, self.voltage, self.voltage_rating_derating, self.exact_capacitance) @@ -217,7 +217,7 @@ class TableDeratingCapacitor(TableCapacitor): DERATE_LOWEST = 0.2 # floor for maximum derating factor # LOOSELY approximated from https://www.maximintegrated.com/en/design/technical-documents/tutorials/5/5527.html - def __init__(self, *args, single_nominal_capacitance: RangeLike = (0, 22)*uFarad, **kwargs): + def __init__(self, *args: Any, single_nominal_capacitance: RangeLike = (0, 22)*uFarad, **kwargs: Any): super().__init__(*args, **kwargs) self.single_nominal_capacitance = self.ArgParameter(single_nominal_capacitance) self.generator_param(self.single_nominal_capacitance) @@ -290,7 +290,7 @@ class DummyCapacitorFootprint(DummyDevice, Capacitor, FootprintBlock): """ def __init__(self, footprint: StringLike = "", manufacturer: StringLike = "", part_number: StringLike = "", value: StringLike = "", - *args, **kwargs): + *args: Any, **kwargs: Any): super().__init__(*args, **kwargs) self.footprint( @@ -363,7 +363,7 @@ def connected(self, gnd: Optional[Port[GroundLink]] = None, io: Optional[Port[An class CombinedCapacitorElement(Capacitor): # to avoid an abstract part error - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_capacitance, self.capacitance) # fake it, since a combined capacitance is handwavey @@ -391,7 +391,7 @@ def __init__(self, *, extend_upper: BoolLike = False) -> None: self.generator_param(self.pos.requested(), self.neg.requested(), self.extend_upper) - def generate(self): + def generate(self) -> None: super().generate() capacitance = self.capacitances.sum() if self.get(self.extend_upper): diff --git a/edg/abstract_parts/AbstractComparator.py b/edg/abstract_parts/AbstractComparator.py index a8913117f..88a673d4b 100644 --- a/edg/abstract_parts/AbstractComparator.py +++ b/edg/abstract_parts/AbstractComparator.py @@ -55,7 +55,7 @@ def __init__(self, trip_voltage: RangeLike, *, invert: BoolLike = False, self.actual_trip_voltage = self.Parameter(RangeExpr()) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.ref.is_connected()): diff --git a/edg/abstract_parts/AbstractConnector.py b/edg/abstract_parts/AbstractConnector.py index cc5a3c7b6..ae5b9e79f 100644 --- a/edg/abstract_parts/AbstractConnector.py +++ b/edg/abstract_parts/AbstractConnector.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .Categories import Connector from .AbstractAntenna import Antenna @@ -35,7 +37,7 @@ def __init__(self, name: StringLike): class RfConnectorAntenna(Antenna): """RF connector used as an antenna""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.conn = self.Block(RfConnector()) self.connect(self.conn.sig, self.a) diff --git a/edg/abstract_parts/AbstractCrystal.py b/edg/abstract_parts/AbstractCrystal.py index efbf91d5e..74c24f24c 100644 --- a/edg/abstract_parts/AbstractCrystal.py +++ b/edg/abstract_parts/AbstractCrystal.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from . import PartsTableSelector, PartsTableColumn, Capacitor, PartsTableRow from .Categories import * @@ -44,7 +46,7 @@ def __init__(self, frequency: RangeLike) -> None: self.crystal = self.Port(CrystalPort(self.actual_frequency), [InOut]) # set by subclass self.gnd = self.Port(Ground(), [Common]) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -59,7 +61,7 @@ class TableCrystal(PartsTableSelector, Crystal): FREQUENCY = PartsTableColumn(Range) CAPACITANCE = PartsTableColumn(float) - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: """Discrete crystal component.""" super().__init__(*args, **kwargs) self.generator_param(self.frequency) diff --git a/edg/abstract_parts/AbstractDebugHeaders.py b/edg/abstract_parts/AbstractDebugHeaders.py index 86aaae2cc..485a05e71 100644 --- a/edg/abstract_parts/AbstractDebugHeaders.py +++ b/edg/abstract_parts/AbstractDebugHeaders.py @@ -1,3 +1,5 @@ +from typing import Any + from .Categories import ProgrammingConnector from ..electronics_model import * @@ -15,20 +17,20 @@ def __init__(self) -> None: class SwdCortexTargetConnectorReset(BlockInterfaceMixin[SwdCortexTargetConnector]): """Mixin for SWD connectors with adding the optional reset pin""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.reset = self.Port(DigitalSource.empty(), optional=True) # as open-drain class SwdCortexTargetConnectorSwo(BlockInterfaceMixin[SwdCortexTargetConnector]): """Mixin for SWD connectors with adding the optional SWO pin""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.swo = self.Port(DigitalBidir.empty(), optional=True) class SwdCortexTargetConnectorTdi(BlockInterfaceMixin[SwdCortexTargetConnector]): """Mixin for SWD connectors with adding the NONSTANDARD TDI pin (where pins are shared with JTAG)""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.tdi = self.Port(DigitalBidir.empty(), optional=True) diff --git a/edg/abstract_parts/AbstractDiodes.py b/edg/abstract_parts/AbstractDiodes.py index 3f2d8a601..ff892ee72 100644 --- a/edg/abstract_parts/AbstractDiodes.py +++ b/edg/abstract_parts/AbstractDiodes.py @@ -1,4 +1,4 @@ -from typing import Dict +from typing import Dict, Any from deprecated import deprecated from ..electronics_model import * @@ -73,7 +73,7 @@ def __init__(self, reverse_voltage: RangeLike, current: RangeLike, *, self.actual_voltage_drop = self.Parameter(RangeExpr()) self.actual_reverse_recovery_time = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -93,7 +93,7 @@ class TableDiode(PartsTableSelector, Diode): FORWARD_VOLTAGE = PartsTableColumn(Range) # possible forward voltage range REVERSE_RECOVERY = PartsTableColumn(Range) # possible reverse recovery time - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.reverse_voltage, self.current, self.voltage_drop, self.reverse_recovery_time) @@ -130,7 +130,7 @@ def __init__(self, zener_voltage: RangeLike) -> None: self.actual_zener_voltage = self.Parameter(RangeExpr()) self.actual_power_rating = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -145,7 +145,7 @@ class TableZenerDiode(PartsTableSelector, ZenerDiode): ZENER_VOLTAGE = PartsTableColumn(Range) POWER_RATING = PartsTableColumn(Range) # tolerable power - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.zener_voltage) @@ -170,7 +170,7 @@ def __init__(self, voltage: RangeLike): self.voltage = self.ArgParameter(voltage) - def contents(self): + def contents(self) -> None: super().contents() self.diode = self.Block(ZenerDiode(zener_voltage=self.voltage)) self.connect(self.diode.cathode.adapt_to(VoltageSink( @@ -191,7 +191,7 @@ def __init__(self, voltage: RangeLike): self.voltage = self.ArgParameter(voltage) - def contents(self): + def contents(self) -> None: super().contents() self.diode = self.Block(ZenerDiode(zener_voltage=self.voltage)) diff --git a/edg/abstract_parts/AbstractFerriteBead.py b/edg/abstract_parts/AbstractFerriteBead.py index ac07aa2e5..a72c1169b 100644 --- a/edg/abstract_parts/AbstractFerriteBead.py +++ b/edg/abstract_parts/AbstractFerriteBead.py @@ -1,4 +1,4 @@ -from typing import Optional, cast, Dict +from typing import Optional, cast, Dict, Any from ..electronics_model import * from .PartsTable import PartsTableColumn, PartsTableRow @@ -51,7 +51,7 @@ def __init__(self, *, current: RangeLike = RangeExpr.ZERO, self.actual_hf_impedance = self.Parameter(RangeExpr()) self.actual_dc_resistance = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -72,7 +72,7 @@ class TableFerriteBead(PartsTableSelector, FerriteBead): HF_IMPEDANCE = PartsTableColumn(Range) DC_RESISTANCE = PartsTableColumn(Range) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.current, self.hf_impedance, self.dc_resistance) diff --git a/edg/abstract_parts/AbstractFets.py b/edg/abstract_parts/AbstractFets.py index d3ce186f7..544228ded 100644 --- a/edg/abstract_parts/AbstractFets.py +++ b/edg/abstract_parts/AbstractFets.py @@ -90,11 +90,11 @@ def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]: return {'D': self.drain, 'G': self.gate, 'S': self.source} @staticmethod - def NFet(*args, **kwargs) -> 'Fet': + def NFet(*args: Any, **kwargs: Any) -> 'Fet': return Fet(*args, **kwargs, channel='N') @staticmethod - def PFet(*args, **kwargs) -> 'Fet': + def PFet(*args: Any, **kwargs: Any) -> 'Fet': return Fet(*args, **kwargs, channel='P') def __init__(self, drain_voltage: RangeLike, drain_current: RangeLike, *, @@ -125,7 +125,7 @@ def __init__(self, drain_voltage: RangeLike, drain_current: RangeLike, *, self.actual_rds_on = self.Parameter(RangeExpr()) self.actual_gate_charge = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -158,7 +158,7 @@ class BaseTableFet(Fet): @non_library class TableFet(PartsTableSelector, BaseTableFet): - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.drain_voltage, self.drain_current, self.gate_voltage, self.gate_threshold_voltage, self.rds_on, self.gate_charge, self.power, self.channel) @@ -194,15 +194,15 @@ class SwitchFet(Fet): # TODO ideally this would just instantaite a Fet internally, but the parts selection becomes more complex b/c # parameters are cross-dependent @staticmethod - def NFet(*args, **kwargs): + def NFet(*args: Any, **kwargs: Any) -> 'SwitchFet': return SwitchFet(*args, **kwargs, channel='N') @staticmethod - def PFet(*args, **kwargs): + def PFet(*args: Any, **kwargs: Any) -> 'SwitchFet': return SwitchFet(*args, **kwargs, channel='P') - def __init__(self, *, frequency: RangeLike = 0*Hertz(tol=0), drive_current: RangeLike = Range.all(), **kwargs) -> None: + def __init__(self, *, frequency: RangeLike = 0*Hertz(tol=0), drive_current: RangeLike = Range.all(), **kwargs: Any) -> None: super().__init__(**kwargs) self.frequency = self.ArgParameter(frequency) @@ -215,7 +215,7 @@ class TableSwitchFet(PartsTableSelector, SwitchFet, BaseTableFet): STATIC_POWER = PartsTableColumn(Range) TOTAL_POWER = PartsTableColumn(Range) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.frequency, self.drain_voltage, self.drain_current, self.gate_voltage, self.gate_threshold_voltage, diff --git a/edg/abstract_parts/AbstractFuse.py b/edg/abstract_parts/AbstractFuse.py index da4958d14..e93718d62 100644 --- a/edg/abstract_parts/AbstractFuse.py +++ b/edg/abstract_parts/AbstractFuse.py @@ -1,4 +1,4 @@ -from typing import Optional, cast +from typing import Optional, cast, Any from deprecated import deprecated @@ -49,7 +49,7 @@ def __init__(self, trip_current: RangeLike, *, hold_current: RangeLike = RangeEx self.voltage = self.ArgParameter(voltage) # operating voltage self.actual_voltage_rating = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -114,7 +114,7 @@ class TableFuse(PartsTableSelector, Fuse): HOLD_CURRENT = PartsTableColumn(Range) VOLTAGE_RATING = PartsTableColumn(Range) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.trip_current, self.hold_current, self.voltage) diff --git a/edg/abstract_parts/AbstractInductor.py b/edg/abstract_parts/AbstractInductor.py index 2daf424d8..b58ef5d8d 100644 --- a/edg/abstract_parts/AbstractInductor.py +++ b/edg/abstract_parts/AbstractInductor.py @@ -113,7 +113,7 @@ def __init__(self, inductance: RangeLike, self.actual_frequency_rating = self.Parameter(RangeExpr()) self.actual_resistance_dc = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -135,7 +135,7 @@ class TableInductor(PartsTableSelector, Inductor): CURRENT_RATING = PartsTableColumn(Range) # tolerable current DC_RESISTANCE = PartsTableColumn(Range) # actual DCR - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.inductance, self.current, self.frequency, self.resistance_dc, self.experimental_filter_fn) diff --git a/edg/abstract_parts/AbstractJumper.py b/edg/abstract_parts/AbstractJumper.py index 133ebe3e2..3ca2421dc 100644 --- a/edg/abstract_parts/AbstractJumper.py +++ b/edg/abstract_parts/AbstractJumper.py @@ -8,19 +8,19 @@ class Jumper(DiscreteComponent, Block): as always connected for model purposes. Wrapping blocks can add typed port and parameter propagation semantics.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.a = self.Port(Passive()) self.b = self.Port(Passive()) class DigitalJumper(TypedJumper, Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.input = self.Port(DigitalSink.empty(), [Input]) self.output = self.Port(DigitalSource.empty(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.device = self.Block(Jumper()) self.connect(self.input, self.device.a.adapt_to(DigitalSink( diff --git a/edg/abstract_parts/AbstractLed.py b/edg/abstract_parts/AbstractLed.py index 06586b9ab..ead6ddcfd 100644 --- a/edg/abstract_parts/AbstractLed.py +++ b/edg/abstract_parts/AbstractLed.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .Categories import * from .AbstractResistor import Resistor @@ -54,7 +56,7 @@ def __init__(self, color: LedColorLike = Any): class TableLed(PartsTableSelector, Led): COLOR = PartsTableColumn(str) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.color) @@ -69,7 +71,7 @@ def _row_generate(self, row: PartsTableRow) -> None: @abstract_block class RgbLedCommonAnode(DiscreteSemiconductor): - def __init__(self): + def __init__(self) -> None: super().__init__() self.a = self.Port(Passive.empty()) @@ -123,7 +125,7 @@ def __init__(self, count: IntLike, color: LedColorLike = Led.Any, *, self.count = self.ArgParameter(count) self.generator_param(self.count) - def generate(self): + def generate(self) -> None: super().generate() self.led = ElementDict[IndicatorLed]() for led_i in range(self.get(self.count)): @@ -150,7 +152,7 @@ def __init__(self, color: LedColorLike = Led.Any, *, current_draw: RangeLike = ( class IndicatorSinkLedResistor(IndicatorSinkLed): """TODO: should the resistor sided-ness be configurable, eg as a generator? Similar for IndicatorLed""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.require(self.signal.current_draw.within((-self.current_draw.upper(), 0))) @@ -183,7 +185,7 @@ def __init__(self, count: IntLike, color: LedColorLike = Led.Any, *, self.count = self.ArgParameter(count) self.generator_param(self.count) - def generate(self): + def generate(self) -> None: super().generate() self.led = ElementDict[IndicatorSinkLed]() for led_i in range(self.get(self.count)): @@ -274,12 +276,12 @@ def __init__(self, current_draw: RangeLike = (1, 10)*mAmp) -> None: class IndicatorSinkPackedRgbLedElement(IndicatorSinkLed): - def __init__(self): + def __init__(self) -> None: super().__init__(current_draw=RangeExpr()) class IndicatorSinkPackedRgbLed(MultipackDevice, MultipackBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() # Optional multipack definition diff --git a/edg/abstract_parts/AbstractLedDriver.py b/edg/abstract_parts/AbstractLedDriver.py index d7ab12448..0e4b97a8c 100644 --- a/edg/abstract_parts/AbstractLedDriver.py +++ b/edg/abstract_parts/AbstractLedDriver.py @@ -1,3 +1,5 @@ +from typing import Any + from ..abstract_parts import * from deprecated import deprecated @@ -6,7 +8,7 @@ class LedDriver(PowerConditioner, Interface): """Abstract current-regulated high-power LED driver. LED ports are passive and should be directly connected to the LED (or LED string).""" - def __init__(self, max_current: RangeLike): + def __init__(self, max_current: RangeLike) -> None: super().__init__() self.pwr = self.Port(VoltageSink.empty(), [Power]) @@ -21,13 +23,13 @@ def __init__(self, max_current: RangeLike): @deprecated("ripple should be an internal parameter") class LedDriverSwitchingConverter(BlockInterfaceMixin[LedDriver]): """LED driver mixin indicating that the LED driver is a switching converter and with a peak-peak ripple limit.""" - def __init__(self, *args, ripple_limit: FloatLike = float('inf'), **kwargs): + def __init__(self, *args: Any, ripple_limit: FloatLike = float('inf'), **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.ripple_limit = self.ArgParameter(ripple_limit) class LedDriverPwm(BlockInterfaceMixin[LedDriver]): """LED driver mixin with PWM input for dimming control.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.pwm = self.Port(DigitalSink.empty(), optional=True) diff --git a/edg/abstract_parts/AbstractOpamp.py b/edg/abstract_parts/AbstractOpamp.py index 697a4ef71..3feafab42 100644 --- a/edg/abstract_parts/AbstractOpamp.py +++ b/edg/abstract_parts/AbstractOpamp.py @@ -36,7 +36,7 @@ class MultipackOpamp(MultipackDevice, MultipackBlock): """Base class for packed opamps - devices that have multiple opamps in a single package, with shared power and ground connections. Typically used with the multipack feature to fit individual opamps across the design hierarchy into one of these.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.elements = self.PackedPart(PackedBlockArray(OpampElement())) self.pwr = self.PackedExport(self.elements.ports_array(lambda x: x.pwr)) @@ -54,7 +54,7 @@ class OpampPorts(NamedTuple): pwr: VoltageSink amps: List[Tuple[AnalogSink, AnalogSink, AnalogSource]] # amp-, amp+, out - def __init__(self): + def __init__(self) -> None: super().__init__() self.generator_param(self.pwr.requested(), self.gnd.requested(), self.inn.requested(), self.inp.requested(), self.out.requested()) @@ -64,7 +64,7 @@ def _make_multipack_opamp(self) -> OpampPorts: Returns (gnd, pwr, [(in-, in+, out)]).""" raise NotImplementedError # implement me - def generate(self): + def generate(self) -> None: super().generate() amp_ports = self._make_multipack_opamp() diff --git a/edg/abstract_parts/AbstractOscillator.py b/edg/abstract_parts/AbstractOscillator.py index 40017b9c1..87c73355a 100644 --- a/edg/abstract_parts/AbstractOscillator.py +++ b/edg/abstract_parts/AbstractOscillator.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from . import PartsTableColumn, PartsTableRow, PartsTableSelector from .Categories import * @@ -16,7 +18,7 @@ def __init__(self, frequency: RangeLike) -> None: self.pwr = self.Port(VoltageSink.empty(), [Power]) self.out = self.Port(DigitalSource.empty(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -32,7 +34,7 @@ class TableOscillator(PartsTableSelector, Oscillator): No default footprints are provided since these may be non-standard.""" FREQUENCY = PartsTableColumn(Range) - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.frequency) diff --git a/edg/abstract_parts/AbstractPowerConverters.py b/edg/abstract_parts/AbstractPowerConverters.py index a8efeb32c..eab3dcf23 100644 --- a/edg/abstract_parts/AbstractPowerConverters.py +++ b/edg/abstract_parts/AbstractPowerConverters.py @@ -1,5 +1,5 @@ from abc import abstractmethod -from typing import Optional, NamedTuple +from typing import Optional, NamedTuple, Any, Callable from deprecated import deprecated @@ -29,7 +29,7 @@ def __init__(self, output_voltage: RangeLike) -> None: self.pwr_out = self.Port(VoltageSource.empty(), [Output]) self.gnd = self.Port(Ground.empty(), [Common]) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -52,11 +52,11 @@ def _generator_inner_reset_pin(self) -> Port[DigitalLink]: """Returns the inner device's reset pin, to be connected in the generator. Only called within a generator.""" - def contents(self): + def contents(self) -> None: super().contents() self.generator_param(self.reset.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): self.connect(self.reset, self._generator_inner_reset_pin()) @@ -81,7 +81,7 @@ class VoltageReference(LinearRegulator): class IdealLinearRegulator(Resettable, LinearRegulator, IdealModel): """Ideal linear regulator, draws the output current and produces spec output voltage limited by input voltage""" - def contents(self): + def contents(self) -> None: super().contents() effective_output_voltage = self.output_voltage.intersect((0, self.pwr_in.link().voltage.upper())) self.gnd.init_from(Ground()) @@ -148,10 +148,10 @@ def _calculate_ripple(output_current: RangeLike, ripple_ratio: RangeLike, *, ripple_ratio_range.lower() * output_current_range.upper(), upper_ripple_limit)) - def __init__(self, *args, + def __init__(self, *args: Any, input_ripple_limit: FloatLike = 75 * mVolt, output_ripple_limit: FloatLike = 25 * mVolt, - **kwargs) -> None: + **kwargs: Any) -> None: """https://www.ti.com/lit/an/slta055/slta055.pdf: recommends 75mV for maximum peak-peak ripple voltage """ super().__init__(*args, **kwargs) @@ -165,7 +165,7 @@ def __init__(self, *args, @abstract_block_default(lambda: IdealBuckConverter) class BuckConverter(SwitchingVoltageRegulator): """Step-down switching converter""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.require(self.pwr_out.voltage_out.upper() <= self.pwr_in.voltage_limits.upper()) @@ -178,7 +178,7 @@ class DiscreteBuckConverter(BuckConverter): class IdealBuckConverter(Resettable, DiscreteBuckConverter, IdealModel): """Ideal buck converter producing the spec output voltage (buck-boost) limited by input voltage and drawing input current from conversation of power""" - def contents(self): + def contents(self) -> None: super().contents() effective_output_voltage = self.output_voltage.intersect((0, self.pwr_in.link().voltage.upper())) self.gnd.init_from(Ground()) @@ -304,7 +304,7 @@ def _calculate_parameters(cls, input_voltage: Range, output_voltage: Range, freq @staticmethod @ExperimentalUserFnPartsTable.user_fn([float, float, float]) - def _buck_inductor_filter(max_avg_current: float, ripple_scale: float, min_ripple: float): + def _buck_inductor_filter(max_avg_current: float, ripple_scale: float, min_ripple: float) -> Callable[[PartsTableRow], bool]: """Applies further filtering to inductors using the trade-off between inductance and peak-peak current. max_avg_current is the maximum average current (not accounting for ripple) seen by the inductor ripple_scale is the scaling factor from 1/L to ripple @@ -316,7 +316,7 @@ def filter_fn(row: PartsTableRow) -> bool: return filter_fn @staticmethod - def _ilim_expr(inductor_ilim: RangeExpr, sw_ilim: RangeExpr, inductor_iripple: RangeExpr): + def _ilim_expr(inductor_ilim: RangeExpr, sw_ilim: RangeExpr, inductor_iripple: RangeExpr) -> RangeExpr: """Returns the average current limit, as an expression, derived from the inductor and switch (instantaneous) current limits.""" iout_limit_inductor = inductor_ilim - (inductor_iripple.upper() / 2) @@ -360,7 +360,7 @@ def __init__(self, input_voltage: RangeLike, output_voltage: RangeLike, frequenc self.actual_inductor_current_ripple = self.Parameter(RangeExpr()) self.actual_inductor_current_peak = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -415,7 +415,7 @@ def generate(self) -> None: @abstract_block_default(lambda: IdealBoostConverter) class BoostConverter(SwitchingVoltageRegulator): """Step-up switching converter""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.require(self.pwr_out.voltage_out.lower() >= self.pwr_in.voltage_limits.lower()) @@ -428,7 +428,7 @@ class DiscreteBoostConverter(BoostConverter): class IdealBoostConverter(Resettable, DiscreteBoostConverter, IdealModel): """Ideal boost converter producing the spec output voltage (buck-boost) limited by input voltage and drawing input current from conversation of power""" - def contents(self): + def contents(self) -> None: super().contents() effective_output_voltage = self.output_voltage.intersect((self.pwr_in.link().voltage.lower(), float('inf'))) self.gnd.init_from(Ground()) @@ -553,7 +553,7 @@ def __init__(self, input_voltage: RangeLike, output_voltage: RangeLike, frequenc self.actual_inductor_current_ripple = self.Parameter(RangeExpr()) self.actual_inductor_current_peak = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -620,7 +620,7 @@ class DiscreteBuckBoostConverter(BuckBoostConverter): class IdealVoltageRegulator(Resettable, DiscreteBuckBoostConverter, IdealModel): """Ideal buck-boost / general DC-DC converter producing the spec output voltage and drawing input current from conversation of power""" - def contents(self): + def contents(self) -> None: super().contents() self.gnd.init_from(Ground()) self.pwr_in.init_from(VoltageSink( @@ -675,7 +675,7 @@ def __init__(self, input_voltage: RangeLike, output_voltage: RangeLike, frequenc self.actual_inductor_current_ripple = self.Parameter(RangeExpr()) self.actual_inductor_current_peak = self.Parameter(RangeExpr()) # inductor current accounting for ripple (upper is peak) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( diff --git a/edg/abstract_parts/AbstractResistor.py b/edg/abstract_parts/AbstractResistor.py index 16637a655..523825da4 100644 --- a/edg/abstract_parts/AbstractResistor.py +++ b/edg/abstract_parts/AbstractResistor.py @@ -84,7 +84,7 @@ def __init__(self, resistance: RangeLike, power: RangeLike = RangeExpr.ZERO, self.actual_power_rating = self.Parameter(RangeExpr()) self.actual_voltage_rating = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -103,7 +103,7 @@ class TableResistor(PartsTableSelector, Resistor): POWER_RATING = PartsTableColumn(Range) VOLTAGE_RATING = PartsTableColumn(Range) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.resistance, self.power, self.voltage) @@ -132,12 +132,12 @@ class SeriesResistor(Resistor, GeneratorBlock): Generally used as a refinement to break up a single (logical) resistor that is dissipating too much power or has an excessive voltage across it. Accounts for tolerance stackup for power and voltage distribution using specified (not actual) resistor tolerance - is a pessimistic calculation.""" - def __init__(self, *args, count: IntLike = 2, **kwargs): + def __init__(self, *args: Any, count: IntLike = 2, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.count = self.ArgParameter(count) self.generator_param(self.count, self.resistance) - def generate(self): + def generate(self) -> None: super().generate() count = self.get(self.count) last_port = self.a @@ -225,7 +225,7 @@ def __init__(self, resistance: RangeLike): self.generator_param(self.io.requested()) self.resistance = self.ArgParameter(resistance) - def generate(self): + def generate(self) -> None: super().generate() self.res = ElementDict[PullupResistor]() for requested in self.get(self.io.requested()): @@ -243,7 +243,7 @@ def __init__(self, resistance: RangeLike): self.generator_param(self.io.requested()) self.resistance = self.ArgParameter(resistance) - def generate(self): + def generate(self) -> None: super().generate() self.res = ElementDict[PulldownResistor]() for requested in self.get(self.io.requested()): @@ -314,7 +314,7 @@ def __init__(self, resistance: RangeLike, sense_in_reqd: BoolLike = True) -> Non self.actual_resistance = self.Parameter(RangeExpr(self.res.actual_resistance)) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.sense_in.is_connected()): @@ -357,7 +357,7 @@ def __init__(self, clamp_target: RangeLike = (0, 3)*Volt, clamp_current: RangeLi self.protection_voltage = self.ArgParameter(protection_voltage) self.zero_out = self.ArgParameter(zero_out) - def contents(self): + def contents(self) -> None: super().contents() # TODO bidirectional clamping calcs? @@ -399,7 +399,7 @@ def __init__(self, clamp_target: RangeLike = (0, 3)*Volt, clamp_current: RangeLi self.protection_voltage = self.ArgParameter(protection_voltage) self.zero_out = self.ArgParameter(zero_out) - def contents(self): + def contents(self) -> None: super().contents() # TODO bidirectional clamping calcs? diff --git a/edg/abstract_parts/AbstractResistorArray.py b/edg/abstract_parts/AbstractResistorArray.py index ecde310fc..f2a28164f 100644 --- a/edg/abstract_parts/AbstractResistorArray.py +++ b/edg/abstract_parts/AbstractResistorArray.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .AbstractResistor import Resistor from .PartsTable import PartsTableColumn, PartsTableRow @@ -44,7 +46,7 @@ class ResistorArrayStandardFootprint(StandardFootprint['ResistorArray']): class ResistorArrayElement(Resistor): # to avoid an abstract part error - def __init__(self): + def __init__(self) -> None: super().__init__(resistance=RangeExpr(), power=RangeExpr()) @@ -71,7 +73,7 @@ def __init__(self, count: IntLike = 0) -> None: # 0 means 'size automatically' self.unpacked_assign(self.elements.params(lambda x: x.actual_resistance), self.actual_resistance) self.unpacked_assign(self.elements.params(lambda x: x.actual_power_rating), self.actual_power_rating) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( # TODO better support for array typed @@ -90,7 +92,7 @@ class TableResistorArray(PartsTableSelector, ResistorArray): POWER_RATING = PartsTableColumn(Range) COUNT = PartsTableColumn(int) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.count, self.a.requested(), self.b.requested(), self.resistances, self.powers) diff --git a/edg/abstract_parts/AbstractSpiMemory.py b/edg/abstract_parts/AbstractSpiMemory.py index a71e5df6d..975fae1df 100644 --- a/edg/abstract_parts/AbstractSpiMemory.py +++ b/edg/abstract_parts/AbstractSpiMemory.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .Categories import * @@ -24,7 +26,7 @@ class SpiMemoryQspi(BlockInterfaceMixin[SpiMemory]): Vanilla SPI SDI maps to IO0, and SDO maps to IO1. EXPERIMENTAL - interface subject to change. May prevent the use of some chip functions that conflict with QSPI lines.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.io2 = self.Port(DigitalBidir.empty(), optional=True) self.io3 = self.Port(DigitalBidir.empty(), optional=True) diff --git a/edg/abstract_parts/AbstractSwitch.py b/edg/abstract_parts/AbstractSwitch.py index 71c779c63..e1c86aa0a 100644 --- a/edg/abstract_parts/AbstractSwitch.py +++ b/edg/abstract_parts/AbstractSwitch.py @@ -1,4 +1,4 @@ -from typing import Dict +from typing import Dict, Any from ..electronics_model import * from .Categories import * @@ -49,7 +49,7 @@ def __init__(self, voltage: RangeLike, current: RangeLike = 0*Amp(tol=0)) -> Non class RotaryEncoderSwitch(BlockInterfaceMixin[RotaryEncoder]): """Rotary encoder mixin adding a switch pin (sharing a common with the encoder), with ratings assumed to be the same between the switch and encoder.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.sw = self.Port(Passive.empty(), optional=True) @@ -74,7 +74,7 @@ def __init__(self, voltage: RangeLike, current: RangeLike = 0*Amp(tol=0)) -> Non class DirectionSwitchCenter(BlockInterfaceMixin[DirectionSwitch]): """DirectionSwitch mixin adding center switch pin (sharing a common with the encoder), with ratings assumed to be the same between the switch and encoder.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.center = self.Port(Passive.empty(), optional=True) @@ -88,7 +88,7 @@ def __init__(self) -> None: self.gnd = self.Port(Ground.empty(), [Common]) self.out = self.Port(DigitalSource.empty(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.package = self.Block(Switch(current=self.out.link().current_drawn, voltage=self.out.link().voltage)) @@ -110,7 +110,7 @@ def __init__(self) -> None: class DigitalWrapperRotaryEncoder(DigitalRotaryEncoder): """Basic implementation for DigitalRotaryEncoder as a wrapper around a passive-typed RotaryEncoder.""" - def contents(self): + def contents(self) -> None: super().contents() self.package = self.Block(RotaryEncoder(current=self.a.link().current_drawn.hull(self.b.link().current_drawn), voltage=self.a.link().voltage.hull(self.b.link().voltage))) @@ -124,18 +124,18 @@ def contents(self): @abstract_block_default(lambda: DigitalWrapperRotaryEncoderWithSwitch) class DigitalRotaryEncoderSwitch(BlockInterfaceMixin[DigitalRotaryEncoder]): """DigitalRotaryEncoder mixin adding a switch pin.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.sw = self.Port(DigitalSource.empty(), optional=True) class DigitalWrapperRotaryEncoderWithSwitch(DigitalRotaryEncoderSwitch, DigitalWrapperRotaryEncoder, GeneratorBlock): - def contents(self): + def contents(self) -> None: super().contents() self.generator_param(self.sw.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.sw.is_connected()): package_sw = self.package.with_mixin(RotaryEncoderSwitch()) @@ -158,7 +158,7 @@ def __init__(self) -> None: class DigitalWrapperDirectionSwitch(DigitalDirectionSwitch): """Basic implementation for DigitalDirectionSwitch as a wrapper around a passive-typed DirectionSwitch.""" - def contents(self): + def contents(self) -> None: super().contents() self.package = self.Block(DirectionSwitch(current=self.a.link().current_drawn.hull(self.b.link().current_drawn), voltage=self.a.link().voltage.hull(self.b.link().voltage))) @@ -174,7 +174,7 @@ def contents(self): @abstract_block_default(lambda: DigitalWrapperDirectionSwitchWithCenter) class DigitalDirectionSwitchCenter(BlockInterfaceMixin[DigitalDirectionSwitch]): """DigitalRotaryEncoder mixin adding a switch pin.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.center = self.Port(DigitalSource.empty(), optional=True) @@ -182,11 +182,11 @@ def __init__(self, *args, **kwargs) -> None: class DigitalWrapperDirectionSwitchWithCenter(DigitalDirectionSwitchCenter, DigitalWrapperDirectionSwitch, GeneratorBlock): - def contents(self): + def contents(self) -> None: super().contents() self.generator_param(self.center.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.center.is_connected()): package_sw = self.package.with_mixin(DirectionSwitchCenter()) diff --git a/edg/abstract_parts/AbstractTestPoint.py b/edg/abstract_parts/AbstractTestPoint.py index 2a2ae69e3..3c9c067be 100644 --- a/edg/abstract_parts/AbstractTestPoint.py +++ b/edg/abstract_parts/AbstractTestPoint.py @@ -1,4 +1,4 @@ -from typing import cast +from typing import cast, Any from ..electronics_model import * from ..electronics_model.CanPort import CanLogicLink @@ -27,7 +27,7 @@ def __init__(self, tp_name: StringLike = "") -> None: self.tp_name = self.ArgParameter(tp_name) self.tp = self.Block(TestPoint(tp_name=StringExpr())) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.tp.tp_name, (self.tp_name == "").then_else(self.io.link().name(), self.tp_name)) @@ -42,7 +42,7 @@ def __init__(self, tp_name: StringLike = "") -> None: self.gnd = self.Export(self.conn.gnd, [Common]) self.io: Port - def contents(self): + def contents(self) -> None: super().contents() conn_tp = self.conn.with_mixin(RfConnectorTestPoint(StringExpr())) self.assign(conn_tp.tp_name, (self.tp_name == "").then_else(self.io.link().name(), self.tp_name)) @@ -50,7 +50,7 @@ def contents(self): class GroundTestPoint(BaseTypedTestPoint, Block): """Test point with a VoltageSink port.""" - def __init__(self, *args): + def __init__(self, *args: Any) -> None: super().__init__(*args) self.io = self.Port(Ground.empty(), [InOut]) self.connect(self.io, self.tp.io.adapt_to(Ground())) @@ -62,7 +62,7 @@ def connected(self, io: Port[GroundLink]) -> 'GroundTestPoint': class VoltageTestPoint(BaseTypedTestPoint, Block): """Test point with a VoltageSink port.""" - def __init__(self, *args): + def __init__(self, *args: Any) -> None: super().__init__(*args) self.io = self.Port(VoltageSink.empty(), [InOut]) self.connect(self.io, self.tp.io.adapt_to(VoltageSink())) @@ -74,7 +74,7 @@ def connected(self, io: Port[VoltageLink]) -> 'VoltageTestPoint': class DigitalTestPoint(BaseTypedTestPoint, Block): """Test point with a DigitalSink port.""" - def __init__(self, *args): + def __init__(self, *args: Any) -> None: super().__init__(*args) self.io = self.Port(DigitalSink.empty(), [InOut]) self.connect(self.io, self.tp.io.adapt_to(DigitalSink())) @@ -86,13 +86,13 @@ def connected(self, io: Port[DigitalLink]) -> 'DigitalTestPoint': class DigitalArrayTestPoint(TypedTestPoint, GeneratorBlock): """Creates an array of Digital test points, sized from the port array's connections.""" - def __init__(self, tp_name: StringLike = ''): + def __init__(self, tp_name: StringLike = '') -> None: super().__init__() self.io = self.Port(Vector(DigitalSink.empty()), [InOut]) self.tp_name = self.ArgParameter(tp_name) self.generator_param(self.io.requested(), self.tp_name) - def generate(self): + def generate(self) -> None: super().generate() self.tp = ElementDict[DigitalTestPoint]() for requested in self.get(self.io.requested()): @@ -106,7 +106,7 @@ def generate(self): class AnalogTestPoint(BaseTypedTestPoint, Block): """Test point with a AnalogSink port""" - def __init__(self, *args): + def __init__(self, *args: Any) -> None: super().__init__(*args) self.io = self.Port(AnalogSink.empty(), [InOut]) self.connect(self.io, self.tp.io.adapt_to(AnalogSink())) @@ -120,7 +120,7 @@ class AnalogCoaxTestPoint(BaseRfTestPoint, Block): """Test point with a AnalogSink port and using a coax connector with shielding connected to gnd. No impedance matching, this is intended for lower frequency signals where the wavelength would be much longer than the test lead length""" - def __init__(self, *args): + def __init__(self, *args: Any) -> None: super().__init__(*args) self.io = self.Export(self.conn.sig.adapt_to(AnalogSink()), [InOut]) @@ -131,12 +131,12 @@ def connected(self, io: Port[AnalogLink]) -> 'AnalogCoaxTestPoint': class I2cTestPoint(TypedTestPoint, Block): """Two test points for I2C SDA and SCL""" - def __init__(self, tp_name: StringLike = ""): + def __init__(self, tp_name: StringLike = "") -> None: super().__init__() self.io = self.Port(I2cTarget(DigitalBidir.empty()), [InOut]) self.tp_name = self.ArgParameter(tp_name) - def contents(self): + def contents(self) -> None: super().contents() name_prefix = (self.tp_name == '').then_else(self.io.link().name(), self.tp_name) self.tp_scl = self.Block(DigitalTestPoint(name_prefix + '.scl')) @@ -151,12 +151,12 @@ def connected(self, io: Port[I2cLink]) -> 'I2cTestPoint': class SpiTestPoint(TypedTestPoint, Block): """Test points for SPI""" - def __init__(self, tp_name: StringLike = ""): + def __init__(self, tp_name: StringLike = "") -> None: super().__init__() self.io = self.Port(SpiPeripheral(DigitalBidir.empty()), [InOut]) self.tp_name = self.ArgParameter(tp_name) - def contents(self): + def contents(self) -> None: super().contents() name_prefix = (self.tp_name == '').then_else(self.io.link().name(), self.tp_name) self.tp_sck = self.Block(DigitalTestPoint(name_prefix + '.sck')) @@ -173,12 +173,12 @@ def connected(self, io: Port[SpiLink]) -> 'SpiTestPoint': class CanControllerTestPoint(TypedTestPoint, Block): """Two test points for CAN controller-side TXD and RXD""" - def __init__(self, tp_name: StringLike = ""): + def __init__(self, tp_name: StringLike = "") -> None: super().__init__() self.io = self.Port(CanPassivePort(DigitalBidir.empty()), [InOut]) self.tp_name = self.ArgParameter(tp_name) - def contents(self): + def contents(self) -> None: super().contents() name_prefix = (self.tp_name == '').then_else(self.io.link().name(), self.tp_name) self.tp_txd = self.Block(DigitalTestPoint(name_prefix + '.txd')) @@ -193,12 +193,12 @@ def connected(self, io: Port[CanLogicLink]) -> 'CanControllerTestPoint': class CanDiffTestPoint(TypedTestPoint, Block): """Two test points for CAN differential-side canh and canl""" - def __init__(self, tp_name: StringLike = ""): + def __init__(self, tp_name: StringLike = "") -> None: super().__init__() self.io = self.Port(CanDiffPort(DigitalBidir.empty()), [InOut]) self.tp_name = self.ArgParameter(tp_name) - def contents(self): + def contents(self) -> None: super().contents() name_prefix = (self.tp_name == '').then_else(self.io.link().name(), self.tp_name) self.tp_canh = self.Block(DigitalTestPoint(name_prefix + '.canh')) diff --git a/edg/abstract_parts/AbstractTvsDiode.py b/edg/abstract_parts/AbstractTvsDiode.py index 7376150ba..bcc018ad6 100644 --- a/edg/abstract_parts/AbstractTvsDiode.py +++ b/edg/abstract_parts/AbstractTvsDiode.py @@ -39,7 +39,7 @@ def __init__(self, working_voltage: RangeLike): self.working_voltage = self.ArgParameter(working_voltage) - def contents(self): + def contents(self) -> None: super().contents() self.diode = self.Block(TvsDiode(working_voltage=self.working_voltage)) self.connect(self.diode.cathode.adapt_to(VoltageSink( @@ -59,7 +59,7 @@ def __init__(self, working_voltage: RangeLike, *, capacitance: RangeLike = Range self.working_voltage = self.ArgParameter(working_voltage) self.capacitance = self.ArgParameter(capacitance) - def contents(self): + def contents(self) -> None: super().contents() self.diode = self.Block(TvsDiode(working_voltage=self.working_voltage, capacitance=self.capacitance)) self.connect(self.diode.cathode.adapt_to(DigitalSink( diff --git a/edg/abstract_parts/Categories.py b/edg/abstract_parts/Categories.py index cfe2e33ab..fb5c8e38e 100644 --- a/edg/abstract_parts/Categories.py +++ b/edg/abstract_parts/Categories.py @@ -1,3 +1,5 @@ +from typing import Any + from ..core import BoolLike, init_in_parent from ..electronics_model import Block, abstract_block, InternalBlock @@ -347,11 +349,11 @@ class DummyDevice(InternalBlock): class IdealModel(InternalBlock): """Ideal model device that can be used as a placeholder to get a design compiling but has no physical implementation.""" - def __init__(self, *args, allow_ideal: BoolLike = False, **kwargs): + def __init__(self, *args: Any, allow_ideal: BoolLike = False, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.allow_ideal = self.ArgParameter(allow_ideal) - def contents(self): + def contents(self) -> None: super().contents() self.require(self.allow_ideal, "ideal model") diff --git a/edg/abstract_parts/CustomDiode.py b/edg/abstract_parts/CustomDiode.py index 407a31842..5926403e8 100644 --- a/edg/abstract_parts/CustomDiode.py +++ b/edg/abstract_parts/CustomDiode.py @@ -1,10 +1,12 @@ +from typing import Any + from ..electronics_model import * from .AbstractDiodes import Diode class CustomDiode(Diode, FootprintBlock, GeneratorBlock): - def __init__(self, *args, footprint_spec: StringLike = "", - manufacturer_spec: StringLike = "", part_spec: StringLike = "", **kwargs): + def __init__(self, *args: Any, footprint_spec: StringLike = "", + manufacturer_spec: StringLike = "", part_spec: StringLike = "", **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.footprint_spec = self.ArgParameter(footprint_spec) # actual_footprint left to the actual footprint self.manufacturer_spec = self.ArgParameter(manufacturer_spec) diff --git a/edg/abstract_parts/CustomFet.py b/edg/abstract_parts/CustomFet.py index bf6de3df0..98c1770af 100644 --- a/edg/abstract_parts/CustomFet.py +++ b/edg/abstract_parts/CustomFet.py @@ -1,10 +1,12 @@ +from typing import Any + from ..electronics_model import * from .AbstractFets import SwitchFet class CustomFet(SwitchFet, FootprintBlock, GeneratorBlock): - def __init__(self, *args, footprint_spec: StringLike = "", - manufacturer_spec: StringLike = "", part_spec: StringLike = "", **kwargs): + def __init__(self, *args: Any, footprint_spec: StringLike = "", + manufacturer_spec: StringLike = "", part_spec: StringLike = "", **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.footprint_spec = self.ArgParameter(footprint_spec) # actual_footprint left to the actual footprint self.manufacturer_spec = self.ArgParameter(manufacturer_spec) diff --git a/edg/abstract_parts/DigitalAmplifiers.py b/edg/abstract_parts/DigitalAmplifiers.py index 5ff14ab15..b9fc3c185 100644 --- a/edg/abstract_parts/DigitalAmplifiers.py +++ b/edg/abstract_parts/DigitalAmplifiers.py @@ -33,7 +33,7 @@ def __init__(self, pull_resistance: RangeLike = 10*kOhm(tol=0.05), max_rds: Floa self.clamp_resistance_ratio = self.ArgParameter(clamp_resistance_ratio) self.generator_param(self.clamp_voltage) - def generate(self): + def generate(self) -> None: super().generate() pwr_voltage = self.pwr.link().voltage @@ -114,7 +114,7 @@ def __init__(self, max_rds: FloatLike = 1*Ohm, frequency: RangeLike = RangeExpr. self.max_rds = self.ArgParameter(max_rds) self.frequency = self.ArgParameter(frequency) - def contents(self): + def contents(self) -> None: super().contents() self.drv = self.Block(SwitchFet.NFet( diff --git a/edg/abstract_parts/DigitalIsolator.py b/edg/abstract_parts/DigitalIsolator.py index 4f626a89f..f4333c3de 100644 --- a/edg/abstract_parts/DigitalIsolator.py +++ b/edg/abstract_parts/DigitalIsolator.py @@ -9,7 +9,7 @@ class DigitalIsolator(Interface, GeneratorBlock): map down to a single chip (or be multipacked). in_a -> out_b, and in_b -> out_a must each have the same array elements, which is how channels will be matched to pins.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr_a = self.Port(VoltageSink.empty()) self.gnd_a = self.Port(Ground.empty()) @@ -23,7 +23,7 @@ def __init__(self): self.generator_param(self.in_a.requested(), self.out_b.requested(), self.in_b.requested(), self.out_a.requested()) - def generate(self): # validity checks + def generate(self) -> None: # validity checks super().generate() assert self.get(self.in_a.requested()) == self.get(self.out_b.requested()), \ "in_a requested and out_b requested must be equal" diff --git a/edg/abstract_parts/ESeriesUtil.py b/edg/abstract_parts/ESeriesUtil.py index ab632a72b..aa2123fb9 100644 --- a/edg/abstract_parts/ESeriesUtil.py +++ b/edg/abstract_parts/ESeriesUtil.py @@ -239,8 +239,7 @@ def find(self, target: ESeriesRatioValueType) -> Tuple[float, float]: # if it gets here, the search queue has been exhausted without a result assert best is not None - # mypy 0.950 breaks without the type: ignore - raise self._no_result_error(best[0], best[1], target) # type: ignore + raise self._no_result_error(best[0], best[1], target) def _get_next_decades(self, decade: Tuple[int, int], target: ESeriesRatioValueType) -> List[Tuple[int, int]]: """If the target was not found scanning the entire decade, this is called to determine next decades to search. diff --git a/edg/abstract_parts/GateDrivers.py b/edg/abstract_parts/GateDrivers.py index 6cb624268..9b96ff89e 100644 --- a/edg/abstract_parts/GateDrivers.py +++ b/edg/abstract_parts/GateDrivers.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .Categories import PowerSwitch @@ -34,7 +36,7 @@ def __init__(self, has_boot_diode: BoolLike): class HalfBridgeDriverIndependent(BlockInterfaceMixin[HalfBridgeDriver]): """Mixin that specifies a half-bridge driver with independent inputs""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.low_in = self.Port(DigitalSink.empty()) self.high_in = self.Port(DigitalSink.empty()) @@ -43,6 +45,6 @@ def __init__(self, *args, **kwargs): class HalfBridgeDriverPwm(BlockInterfaceMixin[HalfBridgeDriver]): """Mixin that specifies a half-bridge driver with PWM input. If an enable pin is provided, it should use the optional Resettable mixin""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.pwm_in = self.Port(DigitalSink.empty()) diff --git a/edg/abstract_parts/GenericCapacitor.py b/edg/abstract_parts/GenericCapacitor.py index 32d801b2a..598acc084 100644 --- a/edg/abstract_parts/GenericCapacitor.py +++ b/edg/abstract_parts/GenericCapacitor.py @@ -1,4 +1,4 @@ -from typing import NamedTuple, Dict, Optional +from typing import NamedTuple, Dict, Optional, Any import math from ..electronics_model import * @@ -36,7 +36,7 @@ class GenericMlcc(Capacitor, SelectorArea, FootprintBlock, GeneratorBlock): SINGLE_CAP_MAX = 22e-6 # maximum capacitance in a single part MAX_CAP_PACKAGE = 'Capacitor_SMD:C_1206_3216Metric' # default package for largest possible capacitor - def __init__(self, *args, footprint_spec: StringLike = "", derating_coeff: FloatLike = 1.0, **kwargs): + def __init__(self, *args: Any, footprint_spec: StringLike = "", derating_coeff: FloatLike = 1.0, **kwargs: Any) -> None: """ footprint specifies an optional constraint on footprint derating_coeff specifies an optional derating coefficient (1.0 = no derating), that does not scale with package. diff --git a/edg/abstract_parts/GenericResistor.py b/edg/abstract_parts/GenericResistor.py index cebd3d246..94316977f 100644 --- a/edg/abstract_parts/GenericResistor.py +++ b/edg/abstract_parts/GenericResistor.py @@ -1,4 +1,4 @@ -from typing import List, Tuple +from typing import List, Tuple, Any from ..electronics_model import * from .AbstractResistor import Resistor @@ -17,8 +17,8 @@ class ESeriesResistor(SelectorArea, Resistor, FootprintBlock, GeneratorBlock): """ PACKAGE_POWER: List[Tuple[float, str]] - def __init__(self, *args, series: IntLike = 24, tolerance: FloatLike = 0.01, - footprint_spec: StringLike = "", **kwargs): + def __init__(self, *args: Any, series: IntLike = 24, tolerance: FloatLike = 0.01, + footprint_spec: StringLike = "", **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.series = self.ArgParameter(series) self.tolerance = self.ArgParameter(tolerance) diff --git a/edg/abstract_parts/IoController.py b/edg/abstract_parts/IoController.py index 0d08b40ba..cc4613416 100644 --- a/edg/abstract_parts/IoController.py +++ b/edg/abstract_parts/IoController.py @@ -1,5 +1,5 @@ from itertools import chain -from typing import List, Dict, Tuple, Type, Optional +from typing import List, Dict, Tuple, Type, Optional, Any from deprecated import deprecated @@ -16,7 +16,7 @@ class BaseIoController(PinMappable, Block): Pin assignments are handled via refinements and can be assigned to pins' allocated names. This should not be instantiated as a generic block.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.gpio = self.Port(Vector(DigitalBidir.empty()), optional=True, @@ -46,7 +46,7 @@ def __init__(self, *args, **kwargs) -> None: self._io_ports: List[BasePort] = [ # ordered by assignment order, most restrictive should be first self.adc, self.spi, self.i2c, self.uart, self.usb, self.gpio] - def __getattr__(self, item): + def __getattr__(self, item: str) -> Any: # automatically materialize some mixins on abstract classes, only if this is IoController # note, getattr ONLY called when the field does not exist, and hasattr is implemented via getattr if self.__class__ is IoController and item == 'can': @@ -146,11 +146,11 @@ def _instantiate_from(ios: List[BasePort], allocations: List[AllocatedResource]) @non_library class BaseIoControllerPinmapGenerator(BaseIoController, GeneratorBlock): """BaseIoController with generator code to set pin mappings""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.pin_assigns) - def contents(self): + def contents(self) -> None: super().contents() for io_port in self._io_ports: # defined in contents() so subclass __init__ can define additional _io_ports if isinstance(io_port, Vector): @@ -190,7 +190,7 @@ def _make_pinning(self) -> Dict[str, CircuitPort]: return dict(chain(self._system_pinmap().items(), io_pins.items())) -def makeIdealIoController(): # needed to avoid circular import +def makeIdealIoController() -> Type[Block]: # needed to avoid circular import from .IdealIoController import IdealIoController return IdealIoController @@ -208,8 +208,8 @@ class IoController(ProgrammableController, BaseIoController): This defines a power input port that powers the device, though the IoControllerPowerOut mixin can be used for a controller that provides power (like USB-powered dev boards). """ - def __init__(self, *awgs, **kwargs) -> None: - super().__init__(*awgs, **kwargs) + def __init__(self, *args: Any, **kwargs: Any) -> None: + super().__init__(*args, **kwargs) self.gnd = self.Port(Ground.empty(), [Common], optional=True) self.pwr = self.Port(VoltageSink.empty(), [Power], optional=True) @@ -218,7 +218,7 @@ def __init__(self, *awgs, **kwargs) -> None: @non_library class IoControllerPowerRequired(IoController): """IO controller with required power pins.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.require(self.gnd.is_connected()) self.require(self.pwr.is_connected()) diff --git a/edg/abstract_parts/IoControllerExportable.py b/edg/abstract_parts/IoControllerExportable.py index ed7de36e9..22a9f1174 100644 --- a/edg/abstract_parts/IoControllerExportable.py +++ b/edg/abstract_parts/IoControllerExportable.py @@ -1,4 +1,4 @@ -from typing import List, Optional, TypeVar, cast +from typing import List, Optional, TypeVar, cast, Any from ..electronics_model import * from .IoController import BaseIoController @@ -12,12 +12,12 @@ class BaseIoControllerExportable(BaseIoController, GeneratorBlock): The export is also customizable, e.g. if additional subcircuits are needed for some connection. Also defines a function for adding additional internal pin assignments. The internal device (self.ic) must have been created (e.g., in contents()) before this generate() is called.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.ic: BaseIoController self.generator_param(self.pin_assigns) - def contents(self): # TODO can this be deduplicated w/ BaseIoControllerPinmapGenerator? + def contents(self) -> None: # TODO can this be deduplicated w/ BaseIoControllerPinmapGenerator? super().contents() for io_port in self._io_ports: # defined in contents() so subclass __init__ can define additional _io_ports if isinstance(io_port, Vector): @@ -48,12 +48,12 @@ def _inner_pin_assigns(self, assigns: List[str]) -> List[str]: Called within generate (has access to generator params), and after modifications from make_export_*.""" return assigns - def generate(self): + def generate(self) -> None: super().generate() inner_ios_by_type = {self._type_of_io(io_port): io_port for io_port in self.ic._io_ports} # mutated in-place during _make_export_* - assigns_raw = self.get(self.pin_assigns).copy() # type: ignore + assigns_raw = self.get(self.pin_assigns).copy() assigns = cast(List[Optional[str]], assigns_raw) assign_index_by_name = {assign.split('=')[0]: i for i, assign in enumerate(assigns_raw)} diff --git a/edg/abstract_parts/IoControllerInterfaceMixins.py b/edg/abstract_parts/IoControllerInterfaceMixins.py index c19638d0b..abee9bcf3 100644 --- a/edg/abstract_parts/IoControllerInterfaceMixins.py +++ b/edg/abstract_parts/IoControllerInterfaceMixins.py @@ -1,9 +1,11 @@ +from typing import Any + from ..electronics_model import * from .IoController import BaseIoController, IoController class IoControllerSpiPeripheral(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.spi_peripheral = self.Port(Vector(SpiPeripheral.empty()), optional=True, @@ -12,7 +14,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerI2cTarget(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.i2c_target = self.Port(Vector(I2cTarget.empty()), optional=True, @@ -21,7 +23,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerTouchDriver(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.touch = self.Port(Vector(TouchDriver.empty()), optional=True, @@ -30,7 +32,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerDac(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.dac = self.Port(Vector(AnalogSource.empty()), optional=True, @@ -39,7 +41,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerCan(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.can = self.Port(Vector(CanControllerPort.empty()), optional=True, @@ -56,7 +58,7 @@ class IoControllerUsb(BlockInterfaceMixin[BaseIoController]): pass class IoControllerUsbCc(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.cc = self.Port(Vector(UsbCcPort.empty()), optional=True, @@ -65,7 +67,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerI2s(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.i2s = self.Port(Vector(I2sController.empty()), optional=True, @@ -74,7 +76,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerDvp8(BlockInterfaceMixin[BaseIoController]): - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.dvp8 = self.Port(Vector(Dvp8Host.empty()), optional=True, @@ -96,7 +98,7 @@ class IoControllerBle(BlockInterfaceMixin[BaseIoController]): class IoControllerPowerOut(BlockInterfaceMixin[IoController]): """IO controller mixin that provides an output of the IO controller's VddIO rail, commonly 3.3v.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.pwr_out = self.Port(VoltageSource.empty(), optional=True, doc="Power output port, typically of the device's Vdd or VddIO rail at 3.3v") @@ -104,7 +106,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerUsbOut(BlockInterfaceMixin[IoController]): """IO controller mixin that provides an output of the IO controller's USB Vbus.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.vusb_out = self.Port(VoltageSource.empty(), optional=True, doc="Power output port of the device's Vbus, typically 5v") @@ -112,7 +114,7 @@ def __init__(self, *args, **kwargs) -> None: class IoControllerVin(BlockInterfaceMixin[IoController]): """IO controller mixin that provides a >=5v input to the device, typically upstream of the Vbus-to-3.3 regulator.""" - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.pwr_vin = self.Port(VoltageSink.empty(), optional=True, doc="Power input pin, typically rated for 5v or a bit beyond.") diff --git a/edg/abstract_parts/IoControllerMixins.py b/edg/abstract_parts/IoControllerMixins.py index 1a387f5d0..a2592081c 100644 --- a/edg/abstract_parts/IoControllerMixins.py +++ b/edg/abstract_parts/IoControllerMixins.py @@ -6,9 +6,9 @@ @non_library class WithCrystalGenerator(IoController, GeneratorBlock): """A Block generator mixin that checks if a crystal oscillator is needed, and if so generates it.""" - DEFAULT_CRYSTAL_FREQUENCY: Range + DEFAULT_CRYSTAL_FREQUENCY: RangeLike - def __init__(self): + def __init__(self) -> None: super().__init__() self.xtal_node = self.connect() # connect this internal node to the microcontroller; this may be empty @@ -17,7 +17,7 @@ def _crystal_required(self) -> bool: Called within generate, has access to generator params.""" return False - def generate(self): + def generate(self) -> None: super().generate() if self._crystal_required(): self.crystal = self.Block(OscillatorReference(self.DEFAULT_CRYSTAL_FREQUENCY)) diff --git a/edg/abstract_parts/IoControllerProgramming.py b/edg/abstract_parts/IoControllerProgramming.py index cebfc6908..1fd6d40b5 100644 --- a/edg/abstract_parts/IoControllerProgramming.py +++ b/edg/abstract_parts/IoControllerProgramming.py @@ -24,7 +24,7 @@ def __init__(self, swd_swo_pin: StringLike = "NC", swd_tdi_pin: StringLike = "NC self.swd_node = self.connect() # connect this internal node to the microcontroller self.reset_node = self.connect() # connect this internal node to the microcontroller - def contents(self): + def contents(self) -> None: super().contents() self.swd = self.Block(SwdCortexTargetConnector()) self.connect(self.swd.gnd, self.gnd) @@ -39,7 +39,7 @@ def _inner_pin_assigns(self, assigns: List[str]) -> List[str]: assigns.append(f'swd_tdi={self.get(self.swd_tdi_pin)}') return assigns - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.swd_swo_pin) != 'NC': self.connect(self.ic.gpio.request('swd_swo'), self.swd.with_mixin(SwdCortexTargetConnectorSwo()).swo) diff --git a/edg/abstract_parts/MergedBlocks.py b/edg/abstract_parts/MergedBlocks.py index 4f2014a56..f4cdddf60 100644 --- a/edg/abstract_parts/MergedBlocks.py +++ b/edg/abstract_parts/MergedBlocks.py @@ -15,7 +15,7 @@ def __init__(self) -> None: )) self.generator_param(self.pwr_ins.requested()) - def generate(self): + def generate(self) -> None: super().generate() self.pwr_ins.defined() for in_request in self.get(self.pwr_ins.requested()): @@ -45,7 +45,7 @@ def __init__(self) -> None: )) self.generator_param(self.ins.requested()) - def generate(self): + def generate(self) -> None: super().generate() self.ins.defined() for in_request in self.get(self.ins.requested()): @@ -86,7 +86,7 @@ def __init__(self) -> None: self.inputs = self.Port(Vector(AnalogSink.empty())) self.generator_param(self.inputs.requested()) - def generate(self): + def generate(self) -> None: super().generate() self.inputs.defined() for in_request in self.get(self.inputs.requested()): @@ -114,7 +114,7 @@ def __init__(self) -> None: self.out = self.Port(SpiController.empty()) self.generator_param(self.ins.requested()) - def generate(self): + def generate(self) -> None: super().generate() self.sck_merge = self.Block(MergedDigitalSource()) self.connect(self.sck_merge.out, self.out.sck) diff --git a/edg/abstract_parts/Nonstrict3v3Compatible.py b/edg/abstract_parts/Nonstrict3v3Compatible.py index ab75f486b..d6f2f3798 100644 --- a/edg/abstract_parts/Nonstrict3v3Compatible.py +++ b/edg/abstract_parts/Nonstrict3v3Compatible.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * @@ -6,6 +8,6 @@ class Nonstrict3v3Compatible(BlockInterfaceMixin[Block]): within the absolute maximum, setting the nonstrict_3v3_compatible parameter to True extends the modeled voltage range to 3.6v or the absolute maximum, whichever is lower. Occurs in displays.""" - def __init__(self, *args, nonstrict_3v3_compatible: BoolLike = False, **kwargs): + def __init__(self, *args: Any, nonstrict_3v3_compatible: BoolLike = False, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.nonstrict_3v3_compatible = self.ArgParameter(nonstrict_3v3_compatible) diff --git a/edg/abstract_parts/OpampCircuits.py b/edg/abstract_parts/OpampCircuits.py index 905029595..8ae0236f6 100644 --- a/edg/abstract_parts/OpampCircuits.py +++ b/edg/abstract_parts/OpampCircuits.py @@ -19,7 +19,7 @@ def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]: '1': self.input, '3': self.output, 'V+': self.pwr, 'V-': self.gnd } - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink.empty(), [Power]) self.gnd = self.Port(Ground.empty(), [Common]) @@ -27,7 +27,7 @@ def __init__(self): self.input = self.Port(AnalogSink.empty(), [Input]) self.output = self.Port(AnalogSource.empty(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.amp = self.Block(Opamp()) @@ -106,7 +106,7 @@ def __init__(self, amplification: RangeLike, impedance: RangeLike = (10, 100)*kO self.actual_amplification = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -241,7 +241,7 @@ def __init__(self, ratio: RangeLike, input_impedance: RangeLike, *, self.actual_ratio = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( diff --git a/edg/abstract_parts/OpampCurrentSensor.py b/edg/abstract_parts/OpampCurrentSensor.py index a58be0277..566dd1f51 100644 --- a/edg/abstract_parts/OpampCurrentSensor.py +++ b/edg/abstract_parts/OpampCurrentSensor.py @@ -34,7 +34,7 @@ def __init__(self, resistance: RangeLike, ratio: RangeLike, input_impedance: Ran self.out = self.Port(AnalogSource.empty()) - def contents(self): + def contents(self) -> None: self.connect(self.amp.input_positive, self.sense.sense_in) self.connect(self.amp.input_negative, self.sense.sense_out) diff --git a/edg/abstract_parts/PartsTable.py b/edg/abstract_parts/PartsTable.py index 211097c86..9808d2602 100644 --- a/edg/abstract_parts/PartsTable.py +++ b/edg/abstract_parts/PartsTable.py @@ -7,7 +7,7 @@ from typing_extensions import ParamSpec -from ..core import Range +from ..core.Range import Range # from https://stackoverflow.com/questions/47965083/comparable-types-with-mypy @@ -31,7 +31,7 @@ class PartsTableRow: Internal type, does not do any error checking (so data should be checked before being passed into this object).""" def __init__(self, value: Dict[Any, Any]): # TODO Dict not covariant so we can't check key types - self.value = value + self.values = value @overload def __getitem__(self, item: str) -> str: ... @@ -40,7 +40,15 @@ def __getitem__(self, item: PartsTableColumn[PartsTableColumnType]) -> PartsTabl def __getitem__(self, item: Union[str, PartsTableColumn[PartsTableColumnType]]) -> \ Union[str, PartsTableColumnType]: - return self.value[item] + value = self.values[item] + if isinstance(item, str): + assert isinstance(value, str) + return value + elif isinstance(item, PartsTableColumn): + assert isinstance(value, item.value_type) + return value + else: + raise TypeError() class PartsTable: @@ -66,7 +74,7 @@ def with_source_dir(filenames: List[str], subdir: Optional[str] = None) -> List[ return [os.path.join(prefix_dir, filename) for filename in filenames] @classmethod - def from_csv_files(cls, csv_names: List[str], encoding='utf-8') -> 'PartsTable': + def from_csv_files(cls, csv_names: List[str], encoding: str='utf-8') -> 'PartsTable': dict_rows = [] for filename in csv_names: with open(filename, newline='', encoding=encoding) as csvfile: @@ -116,8 +124,8 @@ def map_new_columns(self, fn: Callable[[PartsTableRow], Optional[Dict[PartsTable if first_keys is None: first_keys = new_columns.keys() - assert first_keys.isdisjoint(row.value.keys()) or overwrite, \ - f"new columns {new_columns} overwrites existing row keys {row.value.keys()} without overwrite=True" + assert first_keys.isdisjoint(row.values.keys()) or overwrite, \ + f"new columns {new_columns} overwrites existing row keys {row.values.keys()} without overwrite=True" else: assert first_keys == new_columns.keys(), \ f"new columns {new_columns} in row {row} has different keys than first row keys {first_keys}" @@ -127,7 +135,7 @@ def map_new_columns(self, fn: Callable[[PartsTableRow], Optional[Dict[PartsTable assert isinstance(new_col_val, new_col_key.value_type), \ f"new column elt {new_col_key}={new_col_val} in {row} not of expected type {new_col_key.value_type}" new_row_dict = {} - new_row_dict.update(row.value) + new_row_dict.update(row.values) new_row_dict.update(new_columns) new_rows.append(PartsTableRow(new_row_dict)) return PartsTable(new_rows) @@ -149,7 +157,7 @@ def sort_by(self, fn: Callable[[PartsTableRow], ComparableType], reverse: bool = new_rows = sorted(self.rows, key=fn, reverse=reverse) return PartsTable(new_rows) - def first(self, err="no elements in list") -> PartsTableRow: + def first(self, err: str="no elements in list") -> PartsTableRow: if not self.rows: raise IndexError(err) return self.rows[0] @@ -219,8 +227,8 @@ def serialize_arg(tpe: Type, val: Any) -> str: return cls._FN_SERIALIZATION_SEPARATOR.join([fn.__name__] + serialized_args) @classmethod - def deserialize_fn(cls, serialized: str) -> Callable: - """Deserializes a user function from a string.""" + def deserialize_fn(cls, serialized: str) -> Any: + """Deserializes and applies a user function from a string.""" split = serialized.split(cls._FN_SERIALIZATION_SEPARATOR) if split[0] not in cls._user_fns: raise ValueError(f"Function {serialized} not registered.") @@ -235,7 +243,7 @@ def deserialize_arg(tpe: Type, val: str) -> Any: return float(val) elif tpe is Range: parts = val[1:-1].split(",") - return Range(float(parts[0]), float(parts[1])) # type: ignore + return Range(float(parts[0]), float(parts[1])) else: raise TypeError(f"cannot deserialize type {tpe} in user function serialization") deserialized_args = [deserialize_arg(tpe, arg) for tpe, arg in zip(fn_argtypes, split[1:])] diff --git a/edg/abstract_parts/PartsTablePart.py b/edg/abstract_parts/PartsTablePart.py index 6c00aee5d..e1163d18b 100644 --- a/edg/abstract_parts/PartsTablePart.py +++ b/edg/abstract_parts/PartsTablePart.py @@ -37,7 +37,7 @@ def _get_table(cls) -> PartsTable: class PartsTablePart(Block): """An interface mixin for a part that is selected from a table, defining parameters to allow manual part selection as well as matching parts.""" - def __init__(self, *args, part: StringLike = "", **kwargs): + def __init__(self, *args: Any, part: StringLike = "", **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.part = self.ArgParameter(part) self.actual_part = self.Parameter(StringExpr()) @@ -48,7 +48,7 @@ def __init__(self, *args, part: StringLike = "", **kwargs): class PartsTableSelector(PartsTablePart, GeneratorBlock, PartsTableBase): """PartsTablePart that includes the parts selection framework logic. Subclasses only need to extend _row_filter and _row_generate with part-specific logic.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.part) @@ -75,7 +75,7 @@ def _row_generate(self, row: PartsTableRow) -> None: If there is no matching row, this is not called.""" self.assign(self.actual_part, row[self.PART_NUMBER_COL]) - def generate(self): + def generate(self) -> None: matching_table = self._get_table().filter(lambda row: self._row_filter(row)) postprocessed_table = self._table_postprocess(matching_table) postprocessed_table = postprocessed_table.sort_by(self._row_sort_by) @@ -88,7 +88,7 @@ def generate(self): @abstract_block class SelectorFootprint(PartsTablePart): """Mixin that allows a specified footprint, for Blocks that automatically select a part.""" - def __init__(self, *args, footprint_spec: StringLike = "", **kwargs): + def __init__(self, *args: Any, footprint_spec: StringLike = "", **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.footprint_spec = self.ArgParameter(footprint_spec) # actual_footprint left to the actual footprint @@ -100,7 +100,7 @@ class PartsTableFootprintFilter(PartsTableSelector, SelectorFootprint): but an internal block is created instead.""" KICAD_FOOTPRINT = PartsTableColumn(str) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.footprint_spec) diff --git a/edg/abstract_parts/PassiveConnector.py b/edg/abstract_parts/PassiveConnector.py index 1f4ccc66e..5f1a94e03 100644 --- a/edg/abstract_parts/PassiveConnector.py +++ b/edg/abstract_parts/PassiveConnector.py @@ -26,7 +26,7 @@ class FootprintPassiveConnector(PassiveConnector, GeneratorBlock, FootprintBlock """PassiveConnector that is a footprint and provides some base functionality for generation.""" allowed_pins: Iterable[int] - def contents(self): + def contents(self) -> None: super().contents() self.generator_param(self.length, self.pins.requested()) @@ -35,7 +35,7 @@ def part_footprint_mfr_name(self, length: int) -> Tuple[str, str, str]: Implementing classes must implement this method.""" raise NotImplementedError - def generate(self): + def generate(self) -> None: super().generate() max_pin_index = 0 for pin in self.get(self.pins.requested()): diff --git a/edg/abstract_parts/PassiveFilters.py b/edg/abstract_parts/PassiveFilters.py index f65818578..1acb7a96f 100644 --- a/edg/abstract_parts/PassiveFilters.py +++ b/edg/abstract_parts/PassiveFilters.py @@ -116,7 +116,7 @@ def __init__(self, impedance: RangeLike, cutoff_freq: RangeLike): self.generator_param(self.output.requested()) - def generate(self): + def generate(self) -> None: super().generate() self.elts = ElementDict[DigitalLowPassRc]() model = DigitalLowPassRc(self.impedance, self.cutoff_freq) diff --git a/edg/abstract_parts/PinMappable.py b/edg/abstract_parts/PinMappable.py index 1ca94e34c..cd048e78f 100644 --- a/edg/abstract_parts/PinMappable.py +++ b/edg/abstract_parts/PinMappable.py @@ -1,6 +1,6 @@ import itertools from abc import ABCMeta -from typing import List, Type, Tuple, Optional, Union, NamedTuple, Callable, Dict, Set +from typing import List, Type, Tuple, Optional, Union, NamedTuple, Callable, Dict, Set, Any from ..electronics_model import * @@ -17,7 +17,7 @@ def __init__(self, pin_assigns: ArrayStringLike = []) -> None: self.pin_assigns = self.ArgParameter(pin_assigns) self.actual_pin_assigns = self.Parameter(ArrayStringExpr()) - def generator_set_allocation(self, allocations: List['AllocatedResource']): + def generator_set_allocation(self, allocations: List['AllocatedResource']) -> None: allocation_strs = [] for allocation in allocations: if allocation.pin is None: @@ -56,10 +56,10 @@ def __init__(self, pin: str, name_models: Dict[str, CircuitPort]): self.pin = pin self.name_models = name_models - def __repr__(self): + def __repr__(self) -> str: return f"PinResource({self.pin}, {self.name_models})" - def __eq__(self, other): + def __eq__(self, other: Any) -> bool: # TODO avoid using is if we can compare port model equality return isinstance(other, PinResource) and self.pin == other.pin and self.name_models is other.name_models @@ -78,10 +78,10 @@ def __init__(self, name: str, port_model: Bundle, inner_allowed_pins: Dict[str, self.port_model = port_model self.inner_allowed_pins = inner_allowed_pins - def __repr__(self): + def __repr__(self) -> str: return f"PeripheralFixedPin({self.name}, {self.port_model.__class__.__name__} {self.inner_allowed_pins})" - def __eq__(self, other): + def __eq__(self, other: Any) -> bool: # TODO avoid using is if we can compare port model equality return isinstance(other, PeripheralFixedPin) and self.name == other.name and \ self.port_model is other.port_model and self.inner_allowed_pins == other.inner_allowed_pins @@ -96,10 +96,10 @@ def __init__(self, name: str, port_model: Bundle): self.name = name self.port_model = port_model - def __repr__(self): + def __repr__(self) -> str: return f"PeripheralAnyResource({self.name}, {self.port_model.__class__.__name__})" - def __eq__(self, other): + def __eq__(self, other: Any) -> bool: # TODO avoid using is if we can compare port model equality return isinstance(other, PeripheralAnyResource) and self.name == other.name and \ self.port_model is other.port_model @@ -116,10 +116,10 @@ def __init__(self, name: str, port_model: Bundle, inner_allowed_names: Dict[str, self.port_model = port_model self.inner_allowed_names = inner_allowed_names - def __repr__(self): + def __repr__(self) -> str: return f"PeripheralFixedResource({self.name}, {self.port_model.__class__.__name__}, {self.inner_allowed_names})" - def __eq__(self, other): + def __eq__(self, other: Any) -> bool: # TODO avoid using is if we can compare port model equality return isinstance(other, PeripheralFixedResource) and self.name == other.name and \ self.port_model is other.port_model and self.inner_allowed_names == other.inner_allowed_names @@ -133,7 +133,7 @@ class AllocatedResource(NamedTuple): pin: Union[str, None, Dict[str, Tuple[str, Optional[str]]]] # pin number if port is leaf, or # recursive definition for bundles (pin, resource) - def __eq__(self, other): + def __eq__(self, other: Any) -> bool: # TODO better port model check, perhaps by initializer return self.port_model is other.port_model and self.name == other.name and \ self.resource_name is other.resource_name and self.pin == other.pin @@ -302,7 +302,7 @@ def allocate(self, port_types_names: List[Tuple[Type[Port], List[str]]], assignm for supported_type in self._resource_port_types(resource): free_resources_by_type.setdefault(supported_type, []).append(resource) - def mark_resource_used(resource: BasePinMapResource): + def mark_resource_used(resource: BasePinMapResource) -> None: for supported_type in self._resource_port_types(resource): free_resources_by_type[supported_type].remove(resource) diff --git a/edg/abstract_parts/PowerCircuits.py b/edg/abstract_parts/PowerCircuits.py index 899a40fa5..4795ed1f0 100644 --- a/edg/abstract_parts/PowerCircuits.py +++ b/edg/abstract_parts/PowerCircuits.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .Resettable import Resettable from .AbstractResistor import Resistor, SeriesPowerResistor @@ -15,7 +17,7 @@ class HalfBridge(PowerConditioner, Block): """Half bridge circuit with logic-level inputs and current draw calculated from the output node. Two power rails: logic power (which can be used to power gate drivers), and the power rail.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground.empty()) @@ -27,7 +29,7 @@ def __init__(self): @abstract_block_default(lambda: FetHalfBridgeIndependent) class HalfBridgeIndependent(BlockInterfaceMixin[HalfBridge]): - def __init__(self): + def __init__(self) -> None: super().__init__() self.low_ctl = self.Port(DigitalSink.empty()) self.high_ctl = self.Port(DigitalSink.empty()) @@ -35,7 +37,7 @@ def __init__(self): @abstract_block_default(lambda: FetHalfBridgePwmReset) class HalfBridgePwm(BlockInterfaceMixin[HalfBridge]): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwm_ctl = self.Port(DigitalSink.empty()) @@ -52,7 +54,7 @@ def __init__(self, frequency: RangeLike, fet_rds: RangeLike = (0, 1)*Ohm, self.actual_current_limits = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.driver = self.Block(HalfBridgeDriver(has_boot_diode=True)) self.connect(self.driver.gnd, self.gnd) @@ -105,7 +107,7 @@ def contents(self): class FetHalfBridgeIndependent(FetHalfBridge, HalfBridgeIndependent): - def contents(self): + def contents(self) -> None: super().contents() driver_mixin = self.driver.with_mixin(HalfBridgeDriverIndependent()) self.connect(self.low_ctl, driver_mixin.low_in) @@ -113,11 +115,11 @@ def contents(self): class FetHalfBridgePwmReset(FetHalfBridge, HalfBridgePwm, Resettable, GeneratorBlock): - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.reset.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() self.connect(self.pwm_ctl, self.driver.with_mixin(HalfBridgeDriverPwm()).pwm_in) if self.get(self.reset.is_connected()): @@ -176,7 +178,7 @@ def __init__(self, *, cgd: RangeLike = 10*nFarad(tol=0.5), target_ramp: RangeLik self.max_rds = self.ArgParameter(max_rds) self._cdiv_vgs_factor = self.ArgParameter(_cdiv_vgs_factor) - def contents(self): + def contents(self) -> None: super().contents() pwr_voltage = self.pwr_in.link().voltage diff --git a/edg/abstract_parts/Resettable.py b/edg/abstract_parts/Resettable.py index 4befbf40d..97e4a3794 100644 --- a/edg/abstract_parts/Resettable.py +++ b/edg/abstract_parts/Resettable.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * @@ -17,6 +19,6 @@ class Resettable(BlockInterfaceMixin[Block]): Microcontrollers may generate internal programming connectors that drive this signal, and system designers must connect microcontroller resets with this in mind - for example, only driving them in open-drain mode. """ - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.reset = self.Port(DigitalSink.empty(), optional=True) diff --git a/edg/abstract_parts/RfNetworks.py b/edg/abstract_parts/RfNetworks.py index 6e38c071a..c6bdf8ca9 100644 --- a/edg/abstract_parts/RfNetworks.py +++ b/edg/abstract_parts/RfNetworks.py @@ -1,5 +1,5 @@ from math import pi, sqrt -from typing import Tuple +from typing import Tuple, Any from ..electronics_model import * from .AbstractCapacitor import Capacitor @@ -13,11 +13,11 @@ class DiscreteRfWarning(BlockInterfaceMixin[Block]): parasitics of real devices. The discrete RF library components / generators are also experimental and subject to change. They also do not adhere to the tolerance conventions of non-RF parts.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.discrete_rf_warning = self.Parameter(BoolExpr(False)) - def contents(self): + def contents(self) -> None: super().contents() self.require(self.discrete_rf_warning == False, "warning: discrete RF circuit, design may be tricky") diff --git a/edg/abstract_parts/SelectorArea.py b/edg/abstract_parts/SelectorArea.py index 767721edb..6b0da220e 100644 --- a/edg/abstract_parts/SelectorArea.py +++ b/edg/abstract_parts/SelectorArea.py @@ -1,3 +1,5 @@ +from typing import Any + from ..electronics_model import * from .PartsTable import PartsTableRow from .PartsTablePart import PartsTableFootprintFilter, PartsTablePart @@ -18,7 +20,7 @@ class SelectorArea(PartsTablePart): 1812 R=23.01 C=23.4 D=23.01 2512 R=29.3376 D=29.3376 """ - def __init__(self, *args, footprint_area: RangeLike = RangeExpr.ALL, **kwargs): + def __init__(self, *args: Any, footprint_area: RangeLike = RangeExpr.ALL, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.footprint_area = self.ArgParameter(footprint_area) @@ -30,7 +32,7 @@ def _footprint_area(cls, footprint_name: str) -> float: @non_library class PartsTableAreaSelector(PartsTableFootprintFilter, SelectorArea): """Defines an implementation for the area selector using parts tables and KICAD_FOOTPRINT.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.footprint_area) diff --git a/edg/abstract_parts/TouchPad.py b/edg/abstract_parts/TouchPad.py index ddf1dbcb8..a2709bb10 100644 --- a/edg/abstract_parts/TouchPad.py +++ b/edg/abstract_parts/TouchPad.py @@ -8,6 +8,6 @@ def __init__(self, touch_footprint: StringLike): self.pad = self.Port(TouchPadPort(), [Input]) self.touch_footprint = self.ArgParameter(touch_footprint) - def contents(self): + def contents(self) -> None: super().contents() self.footprint('U', self.touch_footprint, {'1': self.pad}) diff --git a/edg/abstract_parts/test_capacitor_generic.py b/edg/abstract_parts/test_capacitor_generic.py index f4aeada24..bdcaa2f21 100644 --- a/edg/abstract_parts/test_capacitor_generic.py +++ b/edg/abstract_parts/test_capacitor_generic.py @@ -4,7 +4,7 @@ class CapacitorGenericTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericMlcc( capacitance=0.1 * uFarad(tol=0.2), @@ -15,7 +15,7 @@ def __init__(self): class BigCapacitorGenericTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericMlcc( capacitance=(50, 1000) * uFarad, @@ -26,7 +26,7 @@ def __init__(self): class HighVoltageCapacitorGenericTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericMlcc( capacitance=0.2 * uFarad(tol=0.2), @@ -37,7 +37,7 @@ def __init__(self): class HighSingleCapacitorGenericTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericMlcc( capacitance=22 * uFarad(tol=0.2), @@ -48,7 +48,7 @@ def __init__(self): class MediumSingleCapacitorGenericTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericMlcc( capacitance=2 * uFarad(tol=0.2), @@ -58,7 +58,7 @@ def __init__(self): (self.dummyb, ), _ = self.chain(self.dut.neg, self.Block(DummyPassive())) class DeratedCapacitorGenericTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericMlcc( capacitance=1 * uFarad(tol=0.2), @@ -68,7 +68,7 @@ def __init__(self): (self.dummyb, ), _ = self.chain(self.dut.neg, self.Block(DummyPassive())) class BigMultiCapacitorGenericTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericMlcc( capacitance=(50, 1000) * uFarad, diff --git a/edg/abstract_parts/test_e_series.py b/edg/abstract_parts/test_e_series.py index 2e04b9146..6047bed2a 100644 --- a/edg/abstract_parts/test_e_series.py +++ b/edg/abstract_parts/test_e_series.py @@ -50,14 +50,14 @@ def test_preferred_number(self) -> None: class RatioTestCase(unittest.TestCase): - def test_ratio_product(self): + def test_ratio_product(self) -> None: self.assertEqual(ESeriesRatioUtil._generate_e_series_product([1, 2, 3, 4], 0, 0), [(1, 1), (2, 1), (1, 2), (2, 2), (3, 1), (1, 3), (3, 2), (2, 3), (3, 3), (4, 1), (1, 4), (4, 2), (2, 4), (4, 3), (3, 4), (4, 4)]) - def test_series_of(self): + def test_series_of(self) -> None: self.assertEqual(ESeriesUtil.series_of(1.0), 3) self.assertEqual(ESeriesUtil.series_of(2.2), 3) self.assertEqual(ESeriesUtil.series_of(6.8), 6) diff --git a/edg/abstract_parts/test_ideal_circuit.py b/edg/abstract_parts/test_ideal_circuit.py index 2d8c40074..4b8da1cb3 100644 --- a/edg/abstract_parts/test_ideal_circuit.py +++ b/edg/abstract_parts/test_ideal_circuit.py @@ -8,7 +8,7 @@ class IdealCircuitTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Block(DummyGround()) self.pwr = self.Block(DummyVoltageSource(5*Volt(tol=0))) diff --git a/edg/abstract_parts/test_kicad_import_netlist.py b/edg/abstract_parts/test_kicad_import_netlist.py index 1263904eb..8591a8756 100644 --- a/edg/abstract_parts/test_kicad_import_netlist.py +++ b/edg/abstract_parts/test_kicad_import_netlist.py @@ -10,13 +10,13 @@ class PassiveDummy(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(Passive(), [InOut]) class KiCadBlackboxTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(KiCadBlackboxBlock()) (self.dummypwr, ), _ = self.chain(self.dut.pwr, self.Block(PassiveDummy())) @@ -25,7 +25,7 @@ def __init__(self): class DummyResistor(Resistor, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__(Range.all()) self.footprint('R', 'Resistor_SMD:R_0603_1608Metric', {'1': self.a, @@ -34,7 +34,7 @@ def __init__(self): class KiCadImportBlackboxTestCase(unittest.TestCase): - def test_netlist(self): + def test_netlist(self) -> None: net = NetlistTestCase.generate_net(KiCadBlackboxTop, refinements=Refinements( class_refinements=[ (Resistor, DummyResistor), diff --git a/edg/abstract_parts/test_kicad_part_parsing.py b/edg/abstract_parts/test_kicad_part_parsing.py index afc5ea4d6..0355c747f 100644 --- a/edg/abstract_parts/test_kicad_part_parsing.py +++ b/edg/abstract_parts/test_kicad_part_parsing.py @@ -4,7 +4,7 @@ class KicadPartParsingTest(unittest.TestCase): - def test_resistor(self): + def test_resistor(self) -> None: self.assertEqual(Resistor.parse_resistor("51"), Range.from_tolerance(51, 0.05)) self.assertEqual(Resistor.parse_resistor("22kR"), Range.from_tolerance(22000, 0.05)) self.assertEqual(Resistor.parse_resistor("22k"), Range.from_tolerance(22000, 0.05)) @@ -18,7 +18,7 @@ def test_resistor(self): self.assertEqual(Resistor.parse_resistor("22k0 5%"), Range.from_tolerance(22000, 0.05)) self.assertEqual(Resistor.parse_resistor("2k2 5%"), Range.from_tolerance(2200, 0.05)) - def test_capacitor(self): + def test_capacitor(self) -> None: self.assertEqual(Capacitor.parse_capacitor("0.1uF 6.3V"), (Range.from_tolerance(0.1e-6, 0.20), Range.zero_to_upper(6.3))) self.assertEqual(Capacitor.parse_capacitor("4.7u 6.3V"), (Range.from_tolerance(4.7e-6, 0.20), diff --git a/edg/abstract_parts/test_opamp.py b/edg/abstract_parts/test_opamp.py index 286ebddd9..bee67a609 100644 --- a/edg/abstract_parts/test_opamp.py +++ b/edg/abstract_parts/test_opamp.py @@ -7,13 +7,14 @@ class AnalogSourceDummy(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(AnalogSource(), [InOut]) class TestOpamp(Opamp): - def contents(self): + def contents(self) -> None: + super().contents() self.pwr.init_from(VoltageSink()) self.gnd.init_from(Ground()) self.inp.init_from(AnalogSink()) @@ -22,13 +23,13 @@ def contents(self): class TestResistor(Resistor): - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_resistance, self.resistance) class AmplifierTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(Amplifier( amplification=Range.from_tolerance(2, 0.05) diff --git a/edg/abstract_parts/test_parts_table.py b/edg/abstract_parts/test_parts_table.py index 6c7408748..1aecec500 100644 --- a/edg/abstract_parts/test_parts_table.py +++ b/edg/abstract_parts/test_parts_table.py @@ -16,9 +16,9 @@ def setUp(self) -> None: def test_product_table(self) -> None: self.assertEqual(len(self.table.rows), 3) - self.assertEqual(self.table.rows[0].value, {'header1': '1', 'header2': 'foo', 'header3': '9'}) - self.assertEqual(self.table.rows[1].value, {'header1': '2', 'header2': 'bar', 'header3': '8'}) - self.assertEqual(self.table.rows[2].value, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) + self.assertEqual(self.table.rows[0].values, {'header1': '1', 'header2': 'foo', 'header3': '9'}) + self.assertEqual(self.table.rows[1].values, {'header1': '2', 'header2': 'bar', 'header3': '8'}) + self.assertEqual(self.table.rows[2].values, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) def test_multiple(self) -> None: path = os.path.join(os.path.dirname(__file__), 'resources', 'test_table.csv') @@ -28,18 +28,18 @@ def test_multiple(self) -> None: table = PartsTable.from_dict_rows(rows, rows) self.assertEqual(len(table.rows), 6) - self.assertEqual(table.rows[0].value, {'header1': '1', 'header2': 'foo', 'header3': '9'}) - self.assertEqual(table.rows[1].value, {'header1': '2', 'header2': 'bar', 'header3': '8'}) - self.assertEqual(table.rows[2].value, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) - self.assertEqual(table.rows[3].value, {'header1': '1', 'header2': 'foo', 'header3': '9'}) - self.assertEqual(table.rows[4].value, {'header1': '2', 'header2': 'bar', 'header3': '8'}) - self.assertEqual(table.rows[5].value, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) + self.assertEqual(table.rows[0].values, {'header1': '1', 'header2': 'foo', 'header3': '9'}) + self.assertEqual(table.rows[1].values, {'header1': '2', 'header2': 'bar', 'header3': '8'}) + self.assertEqual(table.rows[2].values, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) + self.assertEqual(table.rows[3].values, {'header1': '1', 'header2': 'foo', 'header3': '9'}) + self.assertEqual(table.rows[4].values, {'header1': '2', 'header2': 'bar', 'header3': '8'}) + self.assertEqual(table.rows[5].values, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) def test_derived_filter(self) -> None: table = self.table.filter(lambda row: row['header1'] != '2') self.assertEqual(len(table.rows), 2) - self.assertEqual(table.rows[0].value, {'header1': '1', 'header2': 'foo', 'header3': '9'}) - self.assertEqual(table.rows[1].value, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) + self.assertEqual(table.rows[0].values, {'header1': '1', 'header2': 'foo', 'header3': '9'}) + self.assertEqual(table.rows[1].values, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) def test_derived_column(self) -> None: def parse_int(row: PartsTableRow) -> Dict[PartsTableColumn, Any]: @@ -59,14 +59,14 @@ def parse_int(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]: return {} table = self.table.map_new_columns(parse_int) self.assertEqual(len(table.rows), 2) - self.assertEqual(table.rows[0].value, {'header1': '1', 'header2': 'foo', 'header3': '9'}) - self.assertEqual(table.rows[1].value, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) + self.assertEqual(table.rows[0].values, {'header1': '1', 'header2': 'foo', 'header3': '9'}) + self.assertEqual(table.rows[1].values, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) def test_sort(self) -> None: table = self.table.sort_by(lambda row: row['header3']) - self.assertEqual(table.rows[0].value, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) - self.assertEqual(table.rows[1].value, {'header1': '2', 'header2': 'bar', 'header3': '8'}) - self.assertEqual(table.rows[2].value, {'header1': '1', 'header2': 'foo', 'header3': '9'}) + self.assertEqual(table.rows[0].values, {'header1': '3', 'header2': 'ducks', 'header3': '7'}) + self.assertEqual(table.rows[1].values, {'header1': '2', 'header2': 'bar', 'header3': '8'}) + self.assertEqual(table.rows[2].values, {'header1': '1', 'header2': 'foo', 'header3': '9'}) def test_map(self) -> None: output = self.table.map(lambda row: float(row['header1'])) @@ -74,7 +74,7 @@ def test_map(self) -> None: self.assertEqual(sum(output), 6) def test_first(self) -> None: - self.assertEqual(self.table.first().value, {'header1': '1', 'header2': 'foo', 'header3': '9'}) + self.assertEqual(self.table.first().values, {'header1': '1', 'header2': 'foo', 'header3': '9'}) class UserFnPartsTableTest(unittest.TestCase): diff --git a/edg/abstract_parts/test_pinmappable.py b/edg/abstract_parts/test_pinmappable.py index ac6b29985..331fd8851 100644 --- a/edg/abstract_parts/test_pinmappable.py +++ b/edg/abstract_parts/test_pinmappable.py @@ -6,7 +6,7 @@ class PinMapUtilTest(unittest.TestCase): - def test_remap(self): + def test_remap(self) -> None: mapper = PinMapUtil([ PinResource('PIO1', {'PIO1': Passive()}), PinResource('PIO2', {'PIO2': Passive()}), # dropped @@ -32,7 +32,7 @@ def test_remap(self): self.assertTrue(remapped.resources[2] is mapper.resources[3]) # simple passthrough - def test_assign_assigned(self): # fully user-specified + def test_assign_assigned(self) -> None: # fully user-specified dio_model = DigitalBidir() ain_model = AnalogSink() allocated = PinMapUtil([ @@ -48,7 +48,7 @@ def test_assign_assigned(self): # fully user-specified self.assertIn(AllocatedResource(ain_model, 'AIO4', 'AIn4', '4'), allocated) self.assertIn(AllocatedResource(ain_model, 'AIO5', 'AIn5', '5'), allocated) - def test_assign_mixed(self): # mix of user-specified and automatic assignments, assuming greedy algo + def test_assign_mixed(self) -> None: # mix of user-specified and automatic assignments, assuming greedy algo dio_model = DigitalBidir() ain_model = AnalogSink() allocated = PinMapUtil([ @@ -64,7 +64,7 @@ def test_assign_mixed(self): # mix of user-specified and automatic assignments, self.assertIn(AllocatedResource(ain_model, 'AIO4', 'AIn4', '4'), allocated) self.assertIn(AllocatedResource(ain_model, 'AIO5', 'AIn5', '5'), allocated) - def test_assign_bad(self): # bad user-specified assignments + def test_assign_bad(self) -> None: # bad user-specified assignments dio_model = DigitalBidir() ain_model = AnalogSink() with self.assertRaises(BadUserAssignError): @@ -74,7 +74,7 @@ def test_assign_bad(self): # bad user-specified assignments ]).allocate([(AnalogSink, ['AIO'])], ["AIO=1"]) - def test_assign_duplicated(self): # duplicated (over-assigned resources) user-specified assignments + def test_assign_duplicated(self) -> None: # duplicated (over-assigned resources) user-specified assignments dio_model = DigitalBidir() ain_model = AnalogSink() with self.assertRaises(BadUserAssignError): @@ -84,7 +84,7 @@ def test_assign_duplicated(self): # duplicated (over-assigned resources) user-s ]).allocate([(AnalogSink, ['AIO1', 'AIO2'])], ["AIO1=3", "AIO2=3"]) - def test_assign_overflow(self): # more requested ports than available resources + def test_assign_overflow(self) -> None: # more requested ports than available resources dio_model = DigitalBidir() ain_model = AnalogSink() with self.assertRaises(AutomaticAllocationError): @@ -93,7 +93,7 @@ def test_assign_overflow(self): # more requested ports than available resources PinResource('3', {'PIO3': dio_model, 'AIn3': ain_model}), ]).allocate([(AnalogSink, ['AIO3', 'AIO4'])]) - def test_assign_bundle_fixed(self): + def test_assign_bundle_fixed(self) -> None: usb_model = UsbDevicePort() allocated = PinMapUtil([ PeripheralFixedPin('USB0', usb_model, {'dm': '2', 'dp': '3'}), @@ -101,14 +101,14 @@ def test_assign_bundle_fixed(self): ["usb.dm=2", "usb.dp=3"]) self.assertIn(AllocatedResource(usb_model, 'usb', 'USB0', {'dm': ('2', None), 'dp': ('3', None)}), allocated) - def test_assign_bundle_fixed_auto(self): + def test_assign_bundle_fixed_auto(self) -> None: usb_model = UsbDevicePort() allocated = PinMapUtil([ PeripheralFixedPin('USB0', usb_model, {'dm': '2', 'dp': '3'}), ]).allocate([(UsbDevicePort, ['usb'])]) self.assertIn(AllocatedResource(usb_model, 'usb', 'USB0', {'dm': ('2', None), 'dp': ('3', None)}), allocated) - def test_assign_bundle_fixed_badspec(self): + def test_assign_bundle_fixed_badspec(self) -> None: usb_model = UsbDevicePort() with self.assertRaises(BadUserAssignError): PinMapUtil([ @@ -121,7 +121,7 @@ def test_assign_bundle_fixed_badspec(self): ]).allocate([(UsbDevicePort, ['usb'])], ["usb.quack=1"]) - def test_assign_bundle_delegating(self): + def test_assign_bundle_delegating(self) -> None: dio_model = DigitalBidir() ain_model = AnalogSink() allocated = PinMapUtil([ @@ -136,7 +136,7 @@ def test_assign_bundle_delegating(self): self.assertEqual(allocated[0].resource_name, 'UART0') self.assertEqual(allocated[0].pin, {'tx': ('1', 'PIO1'), 'rx': ('3', 'PIO3')}) - def test_assign_bundle_delegating_auto(self): + def test_assign_bundle_delegating_auto(self) -> None: dio_model = DigitalBidir() ain_model = AnalogSink() allocated = PinMapUtil([ @@ -150,7 +150,7 @@ def test_assign_bundle_delegating_auto(self): self.assertEqual(allocated[0].resource_name, 'UART0') self.assertEqual(allocated[0].pin, {'tx': ('1', 'PIO1'), 'rx': ('2', 'PIO2')}) - def test_assign_bundle_delegating_badspec(self): + def test_assign_bundle_delegating_badspec(self) -> None: dio_model = DigitalBidir() ain_model = AnalogSink() with self.assertRaises(BadUserAssignError): @@ -172,7 +172,7 @@ def test_assign_bundle_delegating_badspec(self): ]).allocate([(UartPort, ['uart'])], ["uart.quack=1"]) - def test_assign_bundle_delegating_fixed(self): + def test_assign_bundle_delegating_fixed(self) -> None: dio_model = DigitalBidir() dio_model_tx = DigitalBidir( voltage_out=3.3 * Volt(tol=0.01), @@ -200,7 +200,7 @@ def test_assign_bundle_delegating_fixed(self): self.assertTrue(allocated[0].port_model.rx.current_draw.initializer is not None) self.assertTrue(allocated[0].port_model.rx.current_draw.initializer is dio_model_rx.current_draw.initializer) - def test_assign_bundle_delegating_notconnected(self): + def test_assign_bundle_delegating_notconnected(self) -> None: dio_model = DigitalBidir() allocated = PinMapUtil([ PinResource('1', {'PIO1': dio_model}), diff --git a/edg/abstract_parts/test_power_circuits.py b/edg/abstract_parts/test_power_circuits.py index 3f98bd2be..4d8f1bc16 100644 --- a/edg/abstract_parts/test_power_circuits.py +++ b/edg/abstract_parts/test_power_circuits.py @@ -6,7 +6,7 @@ class RampLimiterTestTop(DesignTop): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(RampLimiter()) diff --git a/edg/abstract_parts/test_resistor_generic.py b/edg/abstract_parts/test_resistor_generic.py index 6e372ed16..ed857f5b8 100644 --- a/edg/abstract_parts/test_resistor_generic.py +++ b/edg/abstract_parts/test_resistor_generic.py @@ -4,7 +4,7 @@ class ResistorTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericChipResistor( resistance=1 * kOhm(tol=0.1), @@ -14,7 +14,7 @@ def __init__(self): class PowerResistorTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericChipResistor( resistance=1 * kOhm(tol=0.1), @@ -25,7 +25,7 @@ def __init__(self): class NonE12ResistorTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(GenericChipResistor( resistance=8.06 * kOhm(tol=0.01), diff --git a/edg/abstract_parts/test_switching_converters.py b/edg/abstract_parts/test_switching_converters.py index f974d6f9d..15a71910f 100644 --- a/edg/abstract_parts/test_switching_converters.py +++ b/edg/abstract_parts/test_switching_converters.py @@ -8,7 +8,7 @@ class SwitchingConverterCalculationTest(unittest.TestCase): - def test_buck_converter(self): + def test_buck_converter(self) -> None: values_ref = BuckConverterPowerPath._calculate_parameters( Range.exact(5), Range.exact(2.5), Range.exact(100e3), Range.exact(1), Range.exact(1), Range.exact(0.1), 0.01, 0.001, @@ -28,7 +28,7 @@ def test_buck_converter(self): self.assertEqual(values_ref.input_capacitance, values.input_capacitance) self.assertEqual(values_ref.output_capacitance, values.output_capacitance) - def test_buck_converter_example(self): + def test_buck_converter_example(self) -> None: # using the example from https://passive-components.eu/buck-converter-design-and-calculation/ values = BuckConverterPowerPath._calculate_parameters( Range.exact(12 + 0.4), Range.exact(3.3 + 0.4), Range.exact(500e3), Range.exact(1), @@ -47,7 +47,7 @@ def test_buck_converter_example(self): self.assertAlmostEqual(values.inductor_peak_currents.upper, 1.173, places=3) self.assertAlmostEqual(values.output_capacitance.lower, 5.24e-6, places=7) - def test_boost_converter(self): + def test_boost_converter(self) -> None: values_ref = BoostConverterPowerPath._calculate_parameters( Range.exact(5), Range.exact(10), Range.exact(100e3), Range.exact(0.5), Range.exact(2), Range.exact(0.4), 0.01, 0.001, @@ -68,7 +68,7 @@ def test_boost_converter(self): self.assertEqual(values_ref.input_capacitance, values.input_capacitance) self.assertEqual(values_ref.output_capacitance, values.output_capacitance) - def test_boost_converter_example(self): + def test_boost_converter_example(self) -> None: # using the example from https://passive-components.eu/boost-converter-design-and-calculation/ values = BoostConverterPowerPath._calculate_parameters( Range.exact(5), Range.exact(12 + 0.4), Range.exact(500e3), Range.exact(0.5), @@ -93,14 +93,14 @@ def test_boost_converter_example(self): class TestCapacitor(Capacitor): - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_capacitance, self.capacitance) self.assign(self.actual_voltage_rating, Range.all()) class TestInductor(Inductor): - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_inductance, self.inductance) self.assign(self.actual_current_rating, (0, 1.5)*Amp) @@ -108,7 +108,7 @@ def contents(self): class BuckPowerPathTestTop(DesignTop): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(BuckConverterPowerPath( input_voltage=Range(4, 6), output_voltage=(2, 3), @@ -139,7 +139,7 @@ def refinements(self) -> Refinements: class BoostPowerPathTestTop(DesignTop): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(BoostConverterPowerPath( input_voltage=Range(4, 6), output_voltage=(10, 14), diff --git a/edg/core/Array.py b/edg/core/Array.py index 8a2b0e45b..5292e38de 100644 --- a/edg/core/Array.py +++ b/edg/core/Array.py @@ -5,12 +5,12 @@ from typing import * from deprecated import deprecated +from .HdlUserExceptions import EdgTypeError from .. import edgir from .Binding import LengthBinding, AllocatedBinding from .Builder import builder from .ConstraintExpr import BoolExpr, ConstraintExpr, FloatExpr, RangeExpr, StringExpr, IntExpr, Binding from .Core import Refable, non_library -from .IdentityDict import IdentityDict from .Ports import BaseContainerPort, BasePort, Port from .ArrayExpr import ArrayExpr, ArrayRangeExpr, ArrayStringExpr, ArrayBoolExpr, ArrayFloatExpr, ArrayIntExpr @@ -98,7 +98,7 @@ class Vector(BaseVector, Generic[VectorType]): # TODO: Library types need to be removed from the type hierarchy, because this does not generate into a library elt def __init__(self, tpe: VectorType) -> None: if not isinstance(tpe, BasePort): - raise TypeError(f"arg to Vector(...) must be BasePort, got {tpe} of type {type(tpe)}") + raise EdgTypeError(f"arg to Vector(...)", tpe, BasePort) super().__init__() @@ -292,7 +292,7 @@ def elt_type(self) -> Type[VectorType]: def validate_selector(expected: Type[SelectorType], result: ConstraintExpr) -> SelectorType: # TODO check returned type is child if not isinstance(result, expected): - raise TypeError(f"selector must return {expected.__name__}, got {result.__class__.__name__}") + raise EdgTypeError(f"selector return", result, expected) return result ExtractPortType = TypeVar('ExtractPortType', bound=Port) @@ -317,7 +317,7 @@ def map_extract(self, selector: Callable[[VectorType], Union[ConstraintExpr, Bas elif isinstance(param, BasePort): return DerivedVector(self, param) else: - raise TypeError(f"selector must return ConstraintExpr or BasePort, got {param} of type {type(param)}") + raise EdgTypeError(f"selector return", param, (ConstraintExpr, BasePort)) def any_connected(self) -> BoolExpr: return self.any(lambda port: port.is_connected()) @@ -345,7 +345,7 @@ def sum(self, selector: Callable[[VectorType], Union[RangeExpr, FloatExpr]]) -> elif isinstance(param, RangeExpr): return ArrayRangeExpr()._bind(MapExtractBinding(self, param)).sum() else: # TODO check that returned type is child - raise TypeError(f"selector must return Float/RangeExpr, got {param} of type {type(param)}") + raise EdgTypeError(f"selector return", param, (FloatExpr, RangeExpr)) def min(self, selector: Callable[[VectorType], FloatExpr]) -> FloatExpr: param = self.validate_selector(FloatExpr, selector(self._elt_sample)) diff --git a/edg/core/ArrayExpr.py b/edg/core/ArrayExpr.py index 26990f371..1880fc6ff 100644 --- a/edg/core/ArrayExpr.py +++ b/edg/core/ArrayExpr.py @@ -14,7 +14,7 @@ class SampleElementBinding(Binding): - def __init__(self): + def __init__(self) -> None: super().__init__() def get_subexprs(self) -> Iterable[Union[ConstraintExpr, BasePort]]: # element should be returned by the containing ConstraintExpr @@ -76,7 +76,7 @@ def array_of_elt(elt: ConstraintExpr) -> ArrayExpr: else: raise TypeError(f"unknown ConstraintExpr type for wrapped param {elt}") - def __init__(self, initializer=None): + def __init__(self: SelfType, initializer: Optional[Union[SelfType, ArrayCastableType]]=None) -> None: super().__init__(initializer) self._elt_sample: ArrayEltType = self._elt_type()._new_bind(SampleElementBinding()) diff --git a/edg/core/BaseBackend.py b/edg/core/BaseBackend.py index 9762e1b31..b6e7bf76b 100644 --- a/edg/core/BaseBackend.py +++ b/edg/core/BaseBackend.py @@ -10,4 +10,5 @@ class BaseBackend(metaclass=ABCMeta): of outputs associated with paths.""" # to be implemented per backend @abstractmethod - def run(self, design: CompiledDesign, args: Dict[str, str] = {}) -> List[Tuple[edgir.LocalPath, str]]: pass + def run(self, design: CompiledDesign, args: Dict[str, str] = {}) -> List[Tuple[edgir.LocalPath, str]]: + raise NotImplementedError() diff --git a/edg/core/BlockInterfaceMixin.py b/edg/core/BlockInterfaceMixin.py index ca9360565..7dc900582 100644 --- a/edg/core/BlockInterfaceMixin.py +++ b/edg/core/BlockInterfaceMixin.py @@ -1,4 +1,4 @@ -from typing import TypeVar, Generic, Type, List, Optional, get_args, get_origin, Tuple, Callable +from typing import TypeVar, Generic, Type, List, Optional, get_args, get_origin, Tuple, Callable, Any from .Core import non_library, HasMetadata from .Blocks import AbstractBlockProperty @@ -65,7 +65,7 @@ def _is_mixin(cls) -> bool: return BlockInterfaceMixin in cls.__bases__ or\ all(map(lambda bcls: issubclass(bcls, BlockInterfaceMixin) and bcls._is_mixin(), cls.__bases__)) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) if self._is_mixin(): # all mixins must be abstract if (self.__class__, AbstractBlockProperty) not in self._elt_properties: diff --git a/edg/core/Blocks.py b/edg/core/Blocks.py index dfcfd0445..19c92acfa 100644 --- a/edg/core/Blocks.py +++ b/edg/core/Blocks.py @@ -22,7 +22,7 @@ class BaseBlockMeta(type): """Adds a hook to set the post-init elaboration state""" - def __call__(cls, *args, **kwargs): + def __call__(cls, *args: Any, **kwargs: Any) -> Any: block_context = builder.get_enclosing_block() obj = super().__call__(*args, **kwargs) if isinstance(obj, BaseBlock): # ignore block prototypes @@ -81,7 +81,7 @@ def _is_export(self) -> Optional[Tuple[BasePort, BasePort]]: # returns (externa else: return None - def add_ports(self, ports: Iterable[BasePort]): + def add_ports(self, ports: Iterable[BasePort]) -> None: from .HierarchyBlock import Block from .Link import Link @@ -211,7 +211,7 @@ class BlockElaborationState(Enum): class DescriptionStringElts(): @abstractmethod - def set_elt_proto(self, pb, ref_map=None): + def set_elt_proto(self, pb: edgir.BlockLikeTypes, ref_map: Refable.RefMapType) -> None: raise NotImplementedError @@ -219,7 +219,7 @@ class DescriptionString(): def __init__(self, *elts: Union[str, DescriptionStringElts]): self.elts = elts - def add_to_proto(self, pb: edgir.BlockLikeTypes, ref_map: Refable.RefMapType): + def add_to_proto(self, pb: edgir.BlockLikeTypes, ref_map: Refable.RefMapType) -> None: for elt in self.elts: if isinstance(elt, DescriptionStringElts): elt.set_elt_proto(pb, ref_map) @@ -234,7 +234,7 @@ def __init__(self, ref: ConstraintExpr, units: str): self.ref = ref self.units = units - def set_elt_proto(self, pb, ref_map=None): + def set_elt_proto(self, pb: edgir.BlockLikeTypes, ref_map: Refable.RefMapType) -> None: new_phrase = pb.description.add() new_phrase.param.path.CopyFrom(ref_map[self.ref]) new_phrase.param.unit = self.units @@ -258,18 +258,17 @@ def __init__(self) -> None: self.description: Optional[DescriptionString] = None # additional string field to be displayed as part of the tooltip for blocks - # TODO delete type ignore after https://github.com/python/mypy/issues/5374 - self._parameters: SubElementDict[ConstraintExpr] = self.manager.new_dict(ConstraintExpr) # type: ignore + self._parameters: SubElementDict[ConstraintExpr] = self.manager.new_dict(ConstraintExpr) self._param_docs = IdentityDict[ConstraintExpr, str]() - self._ports: SubElementDict[BasePort] = self.manager.new_dict(BasePort) # type: ignore + self._ports: SubElementDict[BasePort] = self.manager.new_dict(BasePort) self._required_ports = IdentitySet[BasePort]() self._port_docs = IdentityDict[BasePort, str]() self._connects = self.manager.new_dict(Connection, anon_prefix='anon_link') self._connects_by_port = IdentityDict[BasePort, Connection]() # port -> connection self._connect_delegateds = IdentityDict[Connection, List[Connection]]() # for net joins, joined connect -> prior connects - self._constraints: SubElementDict[ConstraintExpr] = self.manager.new_dict(ConstraintExpr, anon_prefix='anon_constr') # type: ignore + self._constraints: SubElementDict[ConstraintExpr] = self.manager.new_dict(ConstraintExpr, anon_prefix='anon_constr') self._name = StringExpr()._bind(NameBinding(self)) @@ -294,7 +293,7 @@ def name(self) -> StringExpr: return self._name """Overload this method to define the contents of this block""" - def contents(self): + def contents(self) -> None: pass @abstractmethod @@ -403,7 +402,7 @@ def _build_ref_map(self, ref_map: Refable.RefMapType, prefix: edgir.LocalPath) - for name, port in self._ports.items(): port._build_ref_map(ref_map, edgir.localpath_concat(prefix, name)) - def _bind_in_place(self, parent: Union[BaseBlock, Port]): + def _bind_in_place(self, parent: Union[BaseBlock, Port]) -> None: self._parent = parent def _check_constraint(self, constraint: ConstraintExpr) -> None: @@ -435,7 +434,7 @@ def check_subexpr(expr: Union[ConstraintExpr, BasePort]) -> None: # TODO rewrit def require(self, constraint: BoolLike, name: Optional[str] = None, *, unchecked: bool=False) -> BoolExpr: constraint_typed = BoolExpr._to_expr_type(constraint) if not isinstance(name, (str, type(None))): - raise TypeError(f"name to constrain(...) must be str or None, got {name} of type {type(name)}") + raise EdgTypeError(f"require(...) name", name, (str, None)) if not unchecked: # before we have const prop need to manually set nested params self._check_constraint(constraint_typed) @@ -452,9 +451,9 @@ def assign(self, target: ConstraintExpr[ConstrType, Any], value: Union[ConstraintExpr[ConstrType, Any], ConstrType], name: Optional[str] = None) -> AssignExpr: if not isinstance(target, ConstraintExpr): - raise TypeError(f"target to assign(...) must be ConstraintExpr, got {target} of type {type(target)}") + raise EdgTypeError(f"assign(...) target", target, ConstraintExpr) if not isinstance(name, (str, type(None))): - raise TypeError(f"name to constrain(...) must be str or None, got {name} of type {type(name)}") + raise EdgTypeError(f"assign(...) name", name, (str, None)) self._check_constraint(target) expr_value = target._to_expr_type(value) @@ -472,10 +471,10 @@ def assign(self, target: ConstraintExpr[ConstrType, Any], def Port(self, tpe: T, *, optional: bool = False, doc: Optional[str] = None) -> T: """Registers a port for this Block""" if self._elaboration_state != BlockElaborationState.init: - raise BlockDefinitionError(self, "can't call Port(...) outside __init__", + raise BlockDefinitionError(type(self), "can't call Port(...) outside __init__", "call Port(...) inside __init__ only, and remember to call super().__init__()") if not isinstance(tpe, BasePort): - raise TypeError(f"param to Port(...) must be Port, got {tpe} of type {type(tpe)}") + raise EdgTypeError(f"param to Port(...)", tpe, BasePort) elt = tpe._bind(self) self._ports.register(elt) @@ -492,10 +491,10 @@ def Port(self, tpe: T, *, optional: bool = False, doc: Optional[str] = None) -> def Parameter(self, tpe: ConstraintType, *, doc: Optional[str] = None) -> ConstraintType: """Registers a parameter for this Block""" if self._elaboration_state != BlockElaborationState.init: - raise BlockDefinitionError(self, "can't call Parameter(...) outside __init__", + raise BlockDefinitionError(type(self), "can't call Parameter(...) outside __init__", "call Parameter(...) inside __init__ only, and remember to call super().__init__()") if not isinstance(tpe, ConstraintExpr): - raise TypeError(f"param to Parameter(...) must be ConstraintExpr, got {tpe} of type {type(tpe)}") + raise EdgTypeError(f"param to Parameter(...)", tpe, ConstraintExpr) elt = tpe._bind(ParamBinding(self)) self._parameters.register(elt) @@ -507,10 +506,10 @@ def Parameter(self, tpe: ConstraintType, *, doc: Optional[str] = None) -> Constr return elt - def connect(self, *connects: Union[BasePort, Connection], flatten=False) -> Connection: + def connect(self, *connects: Union[BasePort, Connection], flatten: bool=False) -> Connection: for connect in connects: if not isinstance(connect, (BasePort, Connection)): - raise TypeError(f"param to connect(...) must be BasePort or Connection, got {connect}") + raise EdgTypeError(f"param to connect(...)", connect, (BasePort, Connection)) connects_ports = [connect for connect in connects if isinstance(connect, BasePort)] connects_connects = [connect for connect in connects if isinstance(connect, Connection)] diff --git a/edg/core/Builder.py b/edg/core/Builder.py index 017cde21e..ff31499f0 100644 --- a/edg/core/Builder.py +++ b/edg/core/Builder.py @@ -46,7 +46,9 @@ def elaborate_toplevel(self, block: BaseBlock, *, generate_values: Iterable[Tuple[edgir.LocalPath, edgir.ValueLit]] = []) -> edgir.HierarchyBlock: try: if is_generator: # TODO this is kind of nasty =( - elaborated = block._generated_def_to_proto(generate_values) # type: ignore + from .Generator import GeneratorBlock + assert isinstance(block, GeneratorBlock) + elaborated = block._generated_def_to_proto(generate_values) else: # TODO check is a GeneratorBlock w/o circular imports? elaborated = block._elaborated_def_to_proto() diff --git a/edg/core/ConstraintExpr.py b/edg/core/ConstraintExpr.py index b3b76a5af..53da8710f 100644 --- a/edg/core/ConstraintExpr.py +++ b/edg/core/ConstraintExpr.py @@ -175,7 +175,7 @@ def then_else(self, then_val: IteType, else_val: Any) -> IteType: ... @overload def then_else(self, then_val: Any, else_val: IteType) -> IteType: ... - def then_else(self, then_val: Any, else_val: Any) -> ConstraintExpr: # type: ignore + def then_else(self, then_val: Any, else_val: Any) -> ConstraintExpr: if isinstance(then_val, ConstraintExpr): else_val = then_val._to_expr_type(else_val) elif isinstance(else_val, ConstraintExpr): @@ -183,7 +183,7 @@ def then_else(self, then_val: Any, else_val: Any) -> ConstraintExpr: # type: ig else: raise ValueError("either then_val or else_val must be ConstraintExpr, TODO support dual-casting") assert self._is_bound() and then_val._is_bound() and else_val._is_bound() - return then_val._new_bind(IfThenElseBinding(self, then_val, else_val)) + return then_val._new_bind(IfThenElseBinding(self, then_val, else_val)) # type: ignore NumLikeSelfType = TypeVar('NumLikeSelfType', bound='NumLikeExpr') @@ -283,22 +283,22 @@ def __ne__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: #type: i return self._create_bool_op(self, self._to_expr_type(other), EqOp.ne) return NotImplemented - def __gt__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: #type: ignore + def __gt__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: if isinstance(other, self._CASTABLE_TYPES) or isinstance(other, self.__class__): return self._create_bool_op(self, self._to_expr_type(other), OrdOp.gt) return NotImplemented - def __ge__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: #type: ignore + def __ge__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: if isinstance(other, self._CASTABLE_TYPES) or isinstance(other, self.__class__): return self._create_bool_op(self, self._to_expr_type(other), OrdOp.ge) return NotImplemented - def __lt__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: #type: ignore + def __lt__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: if isinstance(other, self._CASTABLE_TYPES) or isinstance(other, self.__class__): return self._create_bool_op(self, self._to_expr_type(other), OrdOp.lt) return NotImplemented - def __le__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: #type: ignore + def __le__(self: NumLikeSelfType, other: NumLikeCastable) -> BoolExpr: if isinstance(other, self._CASTABLE_TYPES) or isinstance(other, self.__class__): return self._create_bool_op(self, self._to_expr_type(other), OrdOp.le) return NotImplemented @@ -600,9 +600,10 @@ def __init__(self, scale: float = 1, units: str = ''): self.scale = scale self.units = units - def __call__(self, dummy=None, tol: Optional[float]=None): - if tol is not None: - return RangeConstructor(tol, self.scale, self.units) + def __call__(self, *, tol: Optional[float]=None) -> RangeConstructor: + if tol is None: + raise ValueError("requires tol, use without parens to create un-toleranced literal") + return RangeConstructor(tol, self.scale, self.units) @overload def __rmul__(self, other: float) -> FloatExpr: ... diff --git a/edg/core/Core.py b/edg/core/Core.py index 4041b7b15..6c3448a82 100644 --- a/edg/core/Core.py +++ b/edg/core/Core.py @@ -35,7 +35,7 @@ def add_element(self, name: str, item: Any) -> None: self.keys_list.append(name) # TODO should this be automatically called? - def finalize(self): + def finalize(self) -> None: if self.closed: return if self.anon_prefix is None: @@ -89,7 +89,7 @@ def new_dict(self, filter_type: Union[Type[ElementType], Tuple[Type[ElementType] self.dicts.append((filter_type, sub_dict)) return sub_dict - def add_alias(self, src: Any, target: Any): + def add_alias(self, src: Any, target: Any) -> None: self.aliases[src] = target def add_element(self, name: str, item: Any) -> None: @@ -256,7 +256,7 @@ class HasMetadata(LibraryElement): """A library element with the metadata dict-like field""" def __init__(self) -> None: super().__init__() - self._metadata: SubElementDict[Any] = self.manager.new_dict(Any) # type: ignore + self._metadata: SubElementDict[Any] = self.manager.new_dict(Any) MetadataType = TypeVar('MetadataType', bound=Union[StructuredMetadata, str, Mapping[str, Any], SubElementDict[Any], IdentityDict[Any, Any]]) def Metadata(self, value: MetadataType) -> MetadataType: @@ -275,7 +275,7 @@ def _get_bases_of(cls, base_type: Type[BaseType]) -> Tuple[List[Type[BaseType]], mypy currently does not allow passing in abstract types, so generally calls to this need type: ignore.""" direct_bases: Set[Type] = set() - def process_direct_base(bcls: Type[HasMetadata.BaseType]): + def process_direct_base(bcls: Type[HasMetadata.BaseType]) -> None: if not issubclass(bcls, base_type): return # ignore above base_type if (bcls, NonLibraryProperty) in bcls._elt_properties: # non-library, recurse into parents diff --git a/edg/core/DesignTop.py b/edg/core/DesignTop.py index 7f492d5e1..b94ff39b4 100644 --- a/edg/core/DesignTop.py +++ b/edg/core/DesignTop.py @@ -1,9 +1,9 @@ -from typing import TypeVar, Union, List, Tuple, Dict, Type +from typing import TypeVar, Union, List, Tuple, Dict, Type, Any from .Core import Refable from .. import edgir from .Builder import builder -from .Ports import Port +from .Ports import Port, BasePort from .ConstraintExpr import ConstraintExpr from .HdlUserExceptions import BlockDefinitionError from .IdentityDict import IdentityDict @@ -22,10 +22,10 @@ def __init__(self) -> None: self._packed_blocks = IdentityDict[ Union[Block, PackedBlockAllocate], DesignPath]() # multipack part -> packed block (as path) - def Port(self, *args, **kwargs): + def Port(self, *args: Any, **kwargs: Any) -> Any: raise ValueError("Can't create ports on design top") - def Export(self, *args, **kwargs): + def Export(self, *args: Any, **kwargs: Any) -> Any: raise ValueError("Can't create ports on design top") def refinements(self) -> Refinements: @@ -47,7 +47,7 @@ def make_packing_refinement(multipack_part: Union[Block, PackedBlockAllocate], p for multipack_part, path in self._packed_blocks.items()] ) - def multipack(self): + def multipack(self) -> None: """Defines multipack packing rules, by defining multipack devices and providing packing connections. Subclasses should define multipack by stacking on top of super().multipack().""" pass @@ -174,7 +174,7 @@ def pack(self, multipack_part: Union[Block, PackedBlockAllocate], path: DesignPa """Packs a block (arbitrarily deep in the design tree, specified as a path) into a PackedBlock multipack block.""" if self._elaboration_state not in \ [BlockElaborationState.init, BlockElaborationState.contents, BlockElaborationState.generate]: - raise BlockDefinitionError(self, "can only define multipack in init, contents, or generate") + raise BlockDefinitionError(type(self), "can only define multipack in init, contents, or generate") if isinstance(multipack_part, Block): multipack_block = multipack_part._parent elif isinstance(multipack_part, PackedBlockAllocate): diff --git a/edg/core/Generator.py b/edg/core/Generator.py index fb8165c92..44ddf48e6 100644 --- a/edg/core/Generator.py +++ b/edg/core/Generator.py @@ -23,7 +23,7 @@ class GeneratorBlock(Block): """Block which allows arbitrary Python code to generate its internal subcircuit, and unlike regular Blocks can rely on Python values of solved parameters. """ - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self._generator: Optional[GeneratorBlock.GeneratorRecord] = None self._generator_params_list: list[ConstraintExpr] = [] @@ -33,21 +33,21 @@ def generator_param(self, *params: ConstraintExpr) -> None: """Declares some parameter to be a generator, so in generate() it can be used in self.get(). Parameters that have not been called in generator_param will error out if used in self.get().""" if self._elaboration_state not in (BlockElaborationState.init, BlockElaborationState.contents): - raise BlockDefinitionError(self, "can't call generator_param(...) outside __init__ or contents", + raise BlockDefinitionError(type(self), "can't call generator_param(...) outside __init__ or contents", "call generator_param(...) inside __init__ or contents only, and remember to call super().__init__()") for param in params: if not isinstance(param, ConstraintExpr): - raise TypeError(f"param to generator_param(...) must be ConstraintExpr, got {param} of type {type(param)}") + raise EdgTypeError(f"generator_param(...) param", param, ConstraintExpr) if param.binding is None: - raise BlockDefinitionError(self, "generator_param(...) param must be bound") + raise BlockDefinitionError(type(self), "generator_param(...) param must be bound") if not isinstance(param.binding, (InitParamBinding, AllocatedBinding, IsConnectedBinding)): - raise BlockDefinitionError(self, "generator_param(...) param must be an __init__ param, port requested, or port is_connected") + raise BlockDefinitionError(type(self), "generator_param(...) param must be an __init__ param, port requested, or port is_connected") self._generator_params_list.append(param) WrappedType = TypeVar('WrappedType', bound=Any) def get(self, param: ConstraintExpr[WrappedType, Any]) -> WrappedType: - return self._generator_param_values[param] + return self._generator_param_values[param] # type: ignore # Generator dependency data # @@ -57,7 +57,7 @@ class GeneratorRecord(NamedTuple): fn_args: Tuple[ConstraintExpr, ...] # params to unpack for the generator function @deprecated(reason="implement self.generate() instead (using self.get(...), self.generator_param(...))") - def generator(self, fn: Callable[..., None], *reqs: Any) -> None: # type: ignore + def generator(self, fn: Callable[..., None], *reqs: Any) -> None: """ Registers a generator function :param fn: function (of self) to invoke, where the parameter list lines up with reqs @@ -76,7 +76,7 @@ def generator(self, fn: Callable[..., None], *reqs: Any) -> None: # type: ignor f"generator parameter {i} {req_param} not an __init__ parameter" self._generator = GeneratorBlock.GeneratorRecord(fn, reqs, reqs) - def generate(self): + def generate(self) -> None: """Generate function which has access to the value of generator params. Implement me.""" pass @@ -100,7 +100,7 @@ def _def_to_proto(self) -> edgir.HierarchyBlock: elif (self.__class__, AbstractBlockProperty) in self._elt_properties: pass # abstract blocks allowed to not define a generator else: - raise BlockDefinitionError(self, "Generator missing generate implementation", "define generate") + raise BlockDefinitionError(type(self), "Generator missing generate implementation", "define generate") return pb else: return super()._def_to_proto() @@ -130,7 +130,7 @@ def _generated_def_to_proto(self, generate_values: Iterable[Tuple[edgir.LocalPat for arg_param in self._generator.fn_args] self._generator.fn(*fn_args) else: - raise BlockDefinitionError(self, "Generator missing generate implementation", "define generate") + raise BlockDefinitionError(type(self), "Generator missing generate implementation", "define generate") self._elaboration_state = BlockElaborationState.post_generate finally: @@ -146,12 +146,12 @@ class DefaultExportBlock(GeneratorBlock): This encapsulates the common pattern of an optional export, which if not externally connected, connects the internal port to some other default port. TODO The default can be specified as a port, or a function that returns a port (e.g. to instantiate adapters).""" - def __init__(self): + def __init__(self) -> None: super().__init__() self._default_exports: List[Tuple[BasePort, Port, Port]] = [] # internal, exported, default ExportType = TypeVar('ExportType', bound=BasePort) - def Export(self, port: ExportType, *args, default: Optional[Port] = None, **kwargs) -> ExportType: + def Export(self, port: ExportType, *args: Any, default: Optional[Port] = None, **kwargs: Any) -> ExportType: """A generator-only variant of Export that supports an optional default (either internal or external) to connect the (internal) port being exported to, if the external exported port is not connected.""" if default is None: @@ -164,7 +164,7 @@ def Export(self, port: ExportType, *args, default: Optional[Port] = None, **kwar self._default_exports.append((port, new_port, default)) return new_port - def generate(self): + def generate(self) -> None: super().generate() for (internal, exported, default) in self._default_exports: if self.get(exported.is_connected()): diff --git a/edg/core/HdlUserExceptions.py b/edg/core/HdlUserExceptions.py index 0ab1e78f1..8b4ddcbda 100644 --- a/edg/core/HdlUserExceptions.py +++ b/edg/core/HdlUserExceptions.py @@ -1,4 +1,7 @@ -from typing import Any, Type, TypeVar, Union, Tuple +from typing import Any, Type, Union, Tuple, TYPE_CHECKING + +if TYPE_CHECKING: + from edg import BaseBlock class EdslUserError(Exception): @@ -7,18 +10,16 @@ def __init__(self, exc: str, resolution: str = ""): super().__init__(exc) -AssertedType = TypeVar('AssertedType') -def assert_cast(elt: Any, expected_type: Union[Type[AssertedType], Tuple[Type[AssertedType], ...]], item_desc: str) -> AssertedType: - if not isinstance(elt, expected_type): - raise EdgTypeError(item_desc, elt, expected_type) - return elt - - class EdgTypeError(EdslUserError): """Argument of the wrong type passed into a EDG core function.""" def __init__(self, item_desc: str, object: Any, expected_type: Union[Type, Tuple[Type, ...]]): - super().__init__(f"{item_desc} expected to be of type {expected_type}, got type {type(object)}", - f"make sure {item_desc} is of type {expected_type}") + if isinstance(expected_type, tuple): + expected_type_str = '/'.join([t.__name__ for t in expected_type]) + else: + expected_type_str = expected_type.__name__ + + super().__init__(f"{item_desc} expected to be of type {expected_type_str}, got {object} of type {type(object).__name__}", + f"ensure {item_desc} is of type {expected_type_str}") class EdgContextError(EdslUserError): @@ -44,8 +45,8 @@ class UnreachableParameterError(Exception): class BlockDefinitionError(EdslUserError): """Base error for likely mistakes when writing a block definition""" - def __init__(self, block, exc: str, resolution: str = ''): - super().__init__(f"invalid block definition for {type(block)}: {exc}", resolution) + def __init__(self, block_type: Type['BaseBlock'], exc: str, resolution: str = '') -> None: + super().__init__(f"invalid block definition for {block_type}: {exc}", resolution) class ChainError(BlockDefinitionError): diff --git a/edg/core/HierarchyBlock.py b/edg/core/HierarchyBlock.py index c7729059f..ccf8533bb 100644 --- a/edg/core/HierarchyBlock.py +++ b/edg/core/HierarchyBlock.py @@ -3,6 +3,7 @@ import functools import inspect import warnings +from types import TracebackType from typing import * from .. import edgir @@ -33,7 +34,7 @@ def init_in_parent(fn: Any) -> Any: ) @functools.wraps(fn) - def wrapped(self: Block, *args, **kwargs) -> Any: + def wrapped(self: Block, *args: Any, **kwargs: Any) -> Any: # in concept, the outer deprecation should fire, but it doesn't consistently, so this is added for redundancy warnings.warn( f"in {fn}, @init_in_parent is no longer needed, the annotation can be removed without replacement", @@ -83,7 +84,7 @@ def __enter__(self) -> ImplicitScope: self.open = True return self - def __exit__(self, exc_type, exc_val, exc_tb) -> None: + def __exit__(self, exc_type: Optional[Type[BaseException]], exc_val: Optional[BaseException], exc_tb: Optional[TracebackType]) -> None: self.open = False @@ -95,7 +96,7 @@ def __init__(self, blocks: List[Block], links: List[Connection]): self.blocks = blocks self.links = links - def __iter__(self): + def __iter__(self) -> Iterable[Union[Tuple[Block, ...], 'ChainConnect']]: return iter((tuple(self.blocks), self)) @@ -116,7 +117,7 @@ def __repr__(self) -> str: def _bind(self, parent: Union[BaseBlock, Port]) -> BlockPrototypeType: """Binds the prototype into an actual Block instance.""" Block._next_bind = self._tpe - block = self._tpe(*self._args, **self._kwargs) # type: ignore + block = self._tpe(*self._args, **self._kwargs) block._bind_in_place(parent) return block @@ -188,7 +189,7 @@ def __new__(cls, *args: Any, **kwargs: Any) -> Any: arg_data.append((arg_name, arg_param, param_expr_type)) - def wrapped_init(self, *args, **kwargs) -> None: + def wrapped_init(self: Any, *args: Any, **kwargs: Any) -> None: if not hasattr(self, '_init_params'): # used to communicate to the block the added init params self._init_params = {} @@ -294,7 +295,7 @@ def __init__(self) -> None: self._mixins: List['BlockInterfaceMixin'] = [] - self._blocks = self.manager.new_dict(Block) # type: ignore + self._blocks = self.manager.new_dict(Block) self._chains = self.manager.new_dict(ChainConnect, anon_prefix='anon_chain') self._port_tags = IdentityDict[BasePort, Set[PortTag[Any]]]() @@ -460,13 +461,13 @@ def with_mixin(self, tpe: MixinType) -> MixinType: tpe_cls = tpe.__class__ if not (issubclass(tpe_cls, BlockInterfaceMixin) and tpe_cls._is_mixin()): - raise TypeError("param to with_mixin must be a BlockInterfaceMixin") + raise EdgTypeError("with_mixin param", tpe, BlockInterfaceMixin) if isinstance(self, BlockInterfaceMixin) and self._is_mixin(): - raise BlockDefinitionError(self, "mixins can not have with_mixin") + raise BlockDefinitionError(type(self), "mixins can not have with_mixin") if (self.__class__, AbstractBlockProperty) not in self._elt_properties: - raise BlockDefinitionError(self, "mixins can only be added to abstract classes") + raise BlockDefinitionError(type(self), "mixins can only be added to abstract classes") if not isinstance(self, tpe_cls._get_mixin_base()): - raise TypeError(f"block {self.__class__.__name__} not an instance of mixin base {tpe_cls._get_mixin_base().__name__}") + raise EdgTypeError(f"block not an instance of mixin base", self, tpe_cls._get_mixin_base()) assert self._parent is not None elt = tpe._bind(self._parent) @@ -475,7 +476,7 @@ def with_mixin(self, tpe: MixinType) -> MixinType: return elt - def chain(self, *elts: Union[Connection, BasePort, Block]) -> ChainConnect: + def chain(self, *elts: Union[Connection, BasePort, Block]) -> Any: if not elts: return self._chains.register(ChainConnect([], [])) chain_blocks = [] @@ -486,39 +487,40 @@ def chain(self, *elts: Union[Connection, BasePort, Block]) -> ChainConnect: elif isinstance(elts[0], Block): outable_ports = elts[0]._get_ports_by_tag({Output}) + elts[0]._get_ports_by_tag({InOut}) if len(outable_ports) > 1: - raise BlockDefinitionError(elts[0], f"first element 0 to chain {type(elts[0])} does not have exactly one InOut or Output port: {outable_ports}") + raise BlockDefinitionError(type(self), f"first element 0 to chain {type(elts[0])} does not have exactly one InOut or Output port: {outable_ports}") current_port = outable_ports[0] chain_blocks.append(elts[0]) else: raise EdgTypeError(f"first element 0 to chain", elts[0], (BasePort, Connection, Block)) for i, elt in list(enumerate(elts))[1:-1]: - elt = assert_cast(elt, (Block), f"middle arguments elts[{i}] to chain") + if not isinstance(elt, Block): + raise EdgTypeError(f"middle arguments elts[{i}] in chain", elt, Block) if elt._get_ports_by_tag({Input}) and elt._get_ports_by_tag({Output}): in_ports = elt._get_ports_by_tag({Input}) out_ports = elt._get_ports_by_tag({Output}) if len(in_ports) != 1: - raise ChainError(self, f"element {i} to chain {type(elt)} does not have exactly one Input port: {in_ports}") + raise ChainError(type(self), f"element {i} to chain {type(elt)} does not have exactly one Input port: {in_ports}") elif len(out_ports) != 1: - raise ChainError(self, f"element {i} to chain {type(elt)} does not have exactly one Output port: {out_ports}") + raise ChainError(type(self), f"element {i} to chain {type(elt)} does not have exactly one Output port: {out_ports}") chain_links.append(self.connect(current_port, in_ports[0])) chain_blocks.append(elt) current_port = out_ports[0] elif elt._get_ports_by_tag({InOut}): ports = elt._get_ports_by_tag({InOut}) if len(ports) != 1: - raise ChainError(self, f"element {i} to chain {type(elt)} does not have exactly one InOut port: {ports}") + raise ChainError(type(self), f"element {i} to chain {type(elt)} does not have exactly one InOut port: {ports}") self.connect(current_port, ports[0]) chain_blocks.append(elt) else: - raise ChainError(self, f"element {i} to chain {type(elt)} has no Input and Output, or InOut ports") + raise ChainError(type(self), f"element {i} to chain {type(elt)} has no Input and Output, or InOut ports") if isinstance(elts[-1], (BasePort, Connection)): chain_links.append(self.connect(current_port, elts[-1])) elif isinstance(elts[-1], Block): inable_ports = elts[-1]._get_ports_by_tag({Input}) + elts[-1]._get_ports_by_tag({InOut}) if len(inable_ports) != 1: - raise BlockDefinitionError(elts[-1], f"last element {len(elts) - 1} to chain {type(elts[-1])} does not have exactly one InOut or Input port: {inable_ports}") + raise BlockDefinitionError(type(self), f"last element {len(elts) - 1} to chain {type(elts[-1])} does not have exactly one InOut or Input port: {inable_ports}") chain_blocks.append(elts[-1]) chain_links.append(self.connect(current_port, inable_ports[0])) else: @@ -529,12 +531,11 @@ def chain(self, *elts: Union[Connection, BasePort, Block]) -> ChainConnect: def implicit_connect(self, *implicits: ImplicitConnect) -> ImplicitScope: for implicit in implicits: if not isinstance(implicit, ImplicitConnect): - raise TypeError(f"param to implicit_connect(...) must be ImplicitConnect, " - f"got {implicit} of type {type(implicit)}") + raise EdgTypeError(f"implicit_connect(...) param", implicit, ImplicitConnect) return ImplicitScope(self, implicits) - def connect(self, *connects: Union[BasePort, Connection], flatten=False) -> Connection: + def connect(self, *connects: Union[BasePort, Connection], flatten: bool=False) -> Connection: assert not flatten, "flatten only allowed in links" return super().connect(*connects, flatten=flatten) @@ -546,7 +547,7 @@ def ArgParameter(self, param: BoolLike, *, doc: Optional[str] = None) -> BoolExp @overload def ArgParameter(self, param: IntLike, *, doc: Optional[str] = None) -> IntExpr: ... # type: ignore @overload - def ArgParameter(self, param: FloatLike, *, doc: Optional[str] = None) -> FloatExpr: ... # type: ignore + def ArgParameter(self, param: FloatLike, *, doc: Optional[str] = None) -> FloatExpr: ... @overload def ArgParameter(self, param: RangeLike, *, doc: Optional[str] = None) -> RangeExpr: ... # type: ignore @overload @@ -556,17 +557,17 @@ def ArgParameter(self, param: ArrayBoolLike, *, doc: Optional[str] = None) -> Ar @overload def ArgParameter(self, param: ArrayIntLike, *, doc: Optional[str] = None) -> ArrayIntExpr: ... # type: ignore @overload - def ArgParameter(self, param: ArrayFloatLike, *, doc: Optional[str] = None) -> ArrayFloatExpr: ... # type: ignore + def ArgParameter(self, param: ArrayFloatLike, *, doc: Optional[str] = None) -> ArrayFloatExpr: ... @overload - def ArgParameter(self, param: ArrayRangeLike, *, doc: Optional[str] = None) -> ArrayRangeExpr: ... # type: ignore + def ArgParameter(self, param: ArrayRangeLike, *, doc: Optional[str] = None) -> ArrayRangeExpr: ... @overload - def ArgParameter(self, param: ArrayStringLike, *, doc: Optional[str] = None) -> ArrayStringExpr: ... # type: ignore + def ArgParameter(self, param: ArrayStringLike, *, doc: Optional[str] = None) -> ArrayStringExpr: ... def ArgParameter(self, param: CastableType, *, doc: Optional[str] = None) -> ConstraintExpr[Any, CastableType]: """Registers a constructor argument parameter for this Block. This doesn't actually do anything, but is needed to help the type system converter the *Like to a *Expr.""" if not isinstance(param, ConstraintExpr): - raise TypeError(f"param to ArgParameter(...) must be ConstraintExpr, got {param} of type {type(param)}") + raise EdgTypeError(f"ArgParameter(...) param", param, ConstraintExpr) if param.binding is None: raise TypeError(f"param to ArgParameter(...) must have binding") if not isinstance(param.binding, InitParamBinding): @@ -583,16 +584,17 @@ def Port(self, tpe: T, tags: Iterable[PortTag]=[], *, optional: bool = False, do if not isinstance(tpe, (Port, Vector)): raise NotImplementedError("Non-Port (eg, Vector) ports not (yet?) supported") for tag in tags: - assert_cast(tag, PortTag, "tag for Port(...)") + if not isinstance(tag, PortTag): + raise EdgTypeError(f"Port(...) tag", tag, PortTag) port = super().Port(tpe, optional=optional, doc=doc) self._port_tags[port] = set(tags) - return port # type: ignore + return port ExportType = TypeVar('ExportType', bound=BasePort) def Export(self, port: ExportType, tags: Iterable[PortTag]=[], *, optional: bool = False, doc: Optional[str] = None, - _connect = True) -> ExportType: + _connect: bool = True) -> ExportType: """Exports a port of a child block, but does not propagate tags or optional.""" assert port._is_bound(), "can only export bound type" port_parent = port._block_parent() @@ -621,7 +623,7 @@ def Block(self, tpe: BlockType) -> BlockType: if self._elaboration_state not in \ [BlockElaborationState.init, BlockElaborationState.contents, BlockElaborationState.generate]: - raise BlockDefinitionError(self, "can only define blocks in init, contents, or generate") + raise BlockDefinitionError(type(self), "can only define blocks in init, contents, or generate") if isinstance(tpe, BlockPrototype): tpe_cls = tpe._tpe @@ -629,7 +631,7 @@ def Block(self, tpe: BlockType) -> BlockType: tpe_cls = tpe.__class__ if not issubclass(tpe_cls, Block): - raise TypeError(f"param to Block(...) must be Block, got {tpe_cls}") + raise EdgTypeError(f"Block(...) param", tpe_cls, Block) if issubclass(tpe_cls, BlockInterfaceMixin) and tpe_cls._is_mixin(): raise TypeError("param to Block(...) must not be BlockInterfaceMixin") if issubclass(tpe_cls, DesignTop): diff --git a/edg/core/IdentityDict.py b/edg/core/IdentityDict.py index d50590635..fc22ea7f1 100644 --- a/edg/core/IdentityDict.py +++ b/edg/core/IdentityDict.py @@ -41,13 +41,13 @@ def __repr__(self) -> str: def __add__(self, other: IdentityDict[KeyType, ValueType]) -> IdentityDict[KeyType, ValueType]: return self.extend(other.items()) - def __setitem__(self, key: KeyType, item: ValueType): + def __setitem__(self, key: KeyType, item: ValueType) -> None: key_id = id(key) assert key_id not in self.dict, f"attempted to overwrite {key}={self.dict[key_id]} with new {item}" self.dict[key_id] = item self.keys_dict[key_id] = key - def update(self, key: KeyType, item: ValueType): + def update(self, key: KeyType, item: ValueType) -> None: key_id = id(key) assert key_id in self.dict, f"attempted to update {key}={self.dict[key_id]} with no prior" self.dict[key_id] = item @@ -70,5 +70,5 @@ def values(self) -> Iterable[ValueType]: def __contains__(self, item: KeyType) -> bool: return id(item) in self.dict - def __bool__(self): + def __bool__(self) -> bool: return bool(self.dict) diff --git a/edg/core/Link.py b/edg/core/Link.py index b4d3e314b..b9727cb5b 100644 --- a/edg/core/Link.py +++ b/edg/core/Link.py @@ -19,7 +19,7 @@ def __new__(cls, *args: Any, **kwargs: Any) -> Any: if '__init__' in new_cls.__dict__: orig_init = new_cls.__dict__['__init__'] - def wrapped_init(self, *args, **kwargs) -> None: + def wrapped_init(self: Any, *args: Any, **kwargs: Any) -> None: builder_prev = builder.push_element(self) try: orig_init(self, *args, **kwargs) diff --git a/edg/core/MultiBiDict.py b/edg/core/MultiBiDict.py index a1e115ea4..7a2bd215c 100644 --- a/edg/core/MultiBiDict.py +++ b/edg/core/MultiBiDict.py @@ -6,11 +6,11 @@ ValueType = TypeVar('ValueType', bound=Hashable) class MultiBiDict(Generic[KeyType, ValueType]): - def __init__(self): + def __init__(self) -> None: self.dict: Dict[KeyType, Set[ValueType]] = {} self.inverse_dict: Dict[ValueType, Set[KeyType]] = {} - def add(self, key: KeyType, value: ValueType): + def add(self, key: KeyType, value: ValueType) -> None: self.dict.setdefault(key, set()).add(value) self.inverse_dict.setdefault(value, set()).add(key) @@ -40,6 +40,6 @@ def get_only_by_value(self, value: ValueType) -> KeyType: # TODO better name else: return key_set.copy().pop() - def clear(self): + def clear(self) -> None: self.dict = {} self.inverse_dict = {} diff --git a/edg/core/MultipackBlock.py b/edg/core/MultipackBlock.py index ee9aa9e87..bfe6d98fa 100644 --- a/edg/core/MultipackBlock.py +++ b/edg/core/MultipackBlock.py @@ -7,7 +7,7 @@ from .ArrayExpr import ArrayExpr, ArrayBoolExpr, ArrayStringExpr, ArrayRangeExpr, ArrayFloatExpr, ArrayIntExpr from .Binding import InitParamBinding from .Blocks import BlockElaborationState -from .HdlUserExceptions import BlockDefinitionError +from .HdlUserExceptions import BlockDefinitionError, EdgTypeError from .IdentityDict import IdentityDict from .Core import non_library, SubElementDict from .ConstraintExpr import ConstraintExpr, BoolExpr, IntExpr, FloatExpr, RangeExpr, StringExpr @@ -119,7 +119,7 @@ class MultipackBlock(Block): implement the application circuit, containing sub-blocks for both the decoupling cap and the chip) and the packing definition (specific to this class - but does not contribute to the block implementation). """ - def __init__(self): + def __init__(self) -> None: super().__init__() self._packed_blocks: SubElementDict[PackedBlockTypes] = self.manager.new_dict((Block, PackedBlockArray)) # TODO should these be defined in terms of Refs? @@ -140,9 +140,9 @@ def PackedPart(self, tpe: PackedPartType) -> PackedPartType: tpe_cls = tpe.__class__ if not issubclass(tpe_cls, (Block, PackedBlockArray)): - raise TypeError(f"param to PackedPart(...) must be Block, got {tpe} of type {type(tpe)}") + raise EdgTypeError(f"PackedPart(...) param", tpe, Block) if self._elaboration_state != BlockElaborationState.init: - raise BlockDefinitionError(self, "can only define multipack in init") + raise BlockDefinitionError(type(self), "can only define multipack in init") elt = tpe._bind(self) # TODO: does this actually need to be bound? self._packed_blocks.register(elt) @@ -155,7 +155,7 @@ def PackedPart(self, tpe: PackedPartType) -> PackedPartType: def packed_connect(self, exterior_port: BasePort, packed_port: PackedPortTypes) -> None: """Defines a packing rule specified as a virtual connection between an exterior port and a PackedBlock port.""" if self._elaboration_state != BlockElaborationState.init: - raise BlockDefinitionError(self, "can only define multipack in init") + raise BlockDefinitionError(type(self), "can only define multipack in init") if isinstance(packed_port, Port): assert type(exterior_port) == type(packed_port), "packed_connect ports must be of the same type" block_parent = packed_port._block_parent() @@ -190,7 +190,7 @@ def packed_assign(self, self_param: ConstraintExpr, packed_param: PackedParamTyp """Defines a packing rule assigning my parameter from a PackedBlock parameter. IMPORTANT: for packed arrays, no ordering on elements is guaranteed, and must be treated as an unordered set.""" if self._elaboration_state != BlockElaborationState.init: - raise BlockDefinitionError(self, "can only define multipack in init") + raise BlockDefinitionError(type(self), "can only define multipack in init") if isinstance(packed_param, ConstraintExpr): assert type(self_param) == type(packed_param), "packed_assign parameters must be of the same type" block_parent = packed_param._context @@ -236,7 +236,7 @@ def unpacked_assign(self, packed_param: UnpackedParamTypes, self_param: Constrai Only direct parameter-to-parameter assignment allowed, even for packed block arrays, """ if self._elaboration_state != BlockElaborationState.init: - raise BlockDefinitionError(self, "can only define multipack in init") + raise BlockDefinitionError(type(self), "can only define multipack in init") if isinstance(packed_param, ConstraintExpr): assert type(packed_param) == type(self_param), "unpacked_assign parameters must be of the same type" block_parent = packed_param._context diff --git a/edg/core/PortBlocks.py b/edg/core/PortBlocks.py index 4047d9446..996da8f28 100644 --- a/edg/core/PortBlocks.py +++ b/edg/core/PortBlocks.py @@ -20,20 +20,20 @@ class PortBridge(InternalBlock, Block): Example: a power sink internal port can connect to one power sink port on an internal block without a port bridge, but requires a port bridge to connect to a power link that serves multiple power sinks on internal blocks. """ - def __init__(self): + def __init__(self) -> None: super().__init__() # TODO these should be type Port[Any], but that seems to break type inference self.outer_port: Any self.inner_link: Any - def __setattr__(self, name: str, value): + def __setattr__(self, name: str, value: Any) -> None: if isinstance(value, Port): assert name == '_parent' or name == "outer_port" or name == "inner_link", \ "PortBridge can only have outer_port or inner_link ports, got %s" % name super().__setattr__(name, value) T = TypeVar('T', bound=BasePort) - def Port(self, tpe: T, *args, **kwargs) -> T: + def Port(self, tpe: T, *args: Any, **kwargs: Any) -> T: assert 'optional' not in kwargs, f"Ports in PortBridge are optional by default, required should be set by enclosing block, in {kwargs}" return super().Port(tpe, *args, optional=True, **kwargs) @@ -43,19 +43,19 @@ def Port(self, tpe: T, *args, **kwargs) -> T: class PortAdapter(InternalBlock, Block, Generic[AdapterDstType]): """Defines an adapter from one port type to another port type. This behaves as a normal block, and both the src and dst are connected with normal connect semantics. Should only be inferred on internal block ports.""" - def __init__(self): + def __init__(self) -> None: super().__init__() # TODO these should be type Port[Any], but that seems to break type inference self.src: Any self.dst: AdapterDstType - def __setattr__(self, name: str, value): + def __setattr__(self, name: str, value: Any) -> None: if isinstance(value, Port): assert name == '_parent' or name == "src" or name == "dst", \ "PortAdapter can only have src or dst ports, got %s" % name super().__setattr__(name, value) T = TypeVar('T', bound=BasePort) - def Port(self, tpe: T, *args, **kwargs) -> T: + def Port(self, tpe: T, *args: Any, **kwargs: Any) -> T: assert 'optional' not in kwargs, "Ports in PortBridge are optional by default, required should be set by enclosing block" return super().Port(tpe, *args, optional=True, **kwargs) diff --git a/edg/core/Ports.py b/edg/core/Ports.py index 5e3f1ac89..c83cd5376 100644 --- a/edg/core/Ports.py +++ b/edg/core/Ports.py @@ -19,7 +19,7 @@ class InitializerContextMeta(type): - def __call__(cls, *args, **kwargs): + def __call__(cls, *args: Any, **kwargs: Any) -> Any: """Hook on construction to store some metadata about its creation. This hooks the top-level __init__ only.""" obj = type.__call__(cls, *args, **kwargs) @@ -64,7 +64,7 @@ def _instance_to_proto(self) -> edgir.PortLike: """Returns the proto of an instance of this object""" raise NotImplementedError - def _bind_in_place(self, parent: PortParentTypes): + def _bind_in_place(self, parent: PortParentTypes) -> None: self._parent = parent def _clone(self: SelfType) -> SelfType: @@ -72,7 +72,7 @@ def _clone(self: SelfType) -> SelfType: parameter initializers.""" assert self._parent is None, "can't clone bound block" # TODO: this might be more efficient (but trickier) with copy.copy - cloned = type(self)(*self._initializer_args[0], **self._initializer_args[1]) # type: ignore + cloned = type(self)(*self._initializer_args[0], **self._initializer_args[1]) cloned._cloned_from(self) return cloned @@ -87,7 +87,7 @@ def _bind(self: SelfType, parent: PortParentTypes) -> SelfType: clone._bind_in_place(parent) return clone - def _is_bound(self): + def _is_bound(self) -> bool: def impl(elt: Optional[PortParentTypes]) -> bool: if elt is None: return False @@ -142,7 +142,7 @@ def __init__(self) -> None: self._adapter_count: int = 0 # TODO delete type ignore after https://github.com/python/mypy/issues/5374 - self._parameters: SubElementDict[ConstraintExpr] = self.manager.new_dict(ConstraintExpr) # type: ignore + self._parameters: SubElementDict[ConstraintExpr] = self.manager.new_dict(ConstraintExpr) self.manager_ignored.update(['_is_connected', '_name']) self._is_connected = BoolExpr()._bind(IsConnectedBinding(self)) @@ -161,7 +161,7 @@ def _cloned_from(self: SelfType, other: SelfType) -> None: assert isinstance(other_param, type(param)) param.initializer = other_param.initializer - def init_from(self: SelfType, other: SelfType): + def init_from(self: SelfType, other: SelfType) -> None: assert self._parent is not None, "may only init_from on an bound port" assert not self._get_initializers([]), "may only init_from an empty model" self._cloned_from(other) @@ -215,7 +215,7 @@ def _def_to_proto(self) -> edgir.PortTypes: pb.self_class.target.name = self._get_def_name() - direct_bases, indirect_bases = self._get_bases_of(Port) # type: ignore + direct_bases, indirect_bases = self._get_bases_of(Port) for cls in direct_bases: pb.superclasses.add().target.name = cls._static_def_name() for cls in indirect_bases: @@ -313,7 +313,7 @@ def _def_to_proto(self) -> edgir.Bundle: pb.self_class.target.name = self._get_def_name() - direct_bases, indirect_bases = self._get_bases_of(Bundle) # type: ignore + direct_bases, indirect_bases = self._get_bases_of(Bundle) for cls in direct_bases: pb.superclasses.add().target.name = cls._static_def_name() for cls in indirect_bases: @@ -345,7 +345,7 @@ def _get_initializers(self, path_prefix: List[str]) -> List[Tuple[ConstraintExpr def Port(self, tpe: T, *, desc: Optional[str] = None) -> T: """Registers a field for this Bundle""" if not isinstance(tpe, Port): - raise TypeError(f"param to Field(...) must be Port, got {tpe} of type {type(tpe)}") + raise EdgTypeError(f"param to Field(...)", tpe, Port) elt = tpe._bind(self) self._ports.register(elt) diff --git a/edg/core/Range.py b/edg/core/Range.py index 3624dd047..147562cff 100644 --- a/edg/core/Range.py +++ b/edg/core/Range.py @@ -1,5 +1,5 @@ import math -from typing import Tuple, Union +from typing import Tuple, Union, Any from deprecated import deprecated @@ -121,13 +121,13 @@ def all() -> 'Range': def __repr__(self) -> str: return f"Range({self.lower, self.upper})" - def __init__(self, lower: float, upper: float): + def __init__(self, lower: float, upper: float) -> None: assert lower <= upper or (math.isnan(lower) and math.isnan(upper)), \ f"invalid range with lower {lower} > upper {upper}" self.lower = float(lower) self.upper = float(upper) - def __eq__(self, other) -> bool: + def __eq__(self, other: Any) -> bool: if not isinstance(other, Range): return False return self.lower == other.lower and self.upper == other.upper diff --git a/edg/core/ScalaCompilerInterface.py b/edg/core/ScalaCompilerInterface.py index ff0327142..c4517dde1 100644 --- a/edg/core/ScalaCompilerInterface.py +++ b/edg/core/ScalaCompilerInterface.py @@ -55,7 +55,7 @@ def get_value(self, path: Union[edgir.LocalPath, Iterable[Union[str, 'edgir.Rese localpath = edgir.LocalPathList(path) return self._values.get(localpath.SerializeToString(), None) - def append_values(self, values: List[Tuple[edgir.LocalPath, edgir.ValueLit]]): + def append_values(self, values: List[Tuple[edgir.LocalPath, edgir.ValueLit]]) -> None: """Append solved values to this design, such as from a refinement pass""" for (value_path, value_value) in values: value_path_str = value_path.SerializeToString() @@ -67,7 +67,7 @@ class ScalaCompilerInstance: kDevRelpath = "../../compiler/target/scala-2.13/edg-compiler-assembly-0.1-SNAPSHOT.jar" kPrecompiledRelpath = "resources/edg-compiler-precompiled.jar" - def __init__(self): + def __init__(self) -> None: self.process: Optional[Any] = None def check_started(self) -> None: @@ -140,7 +140,7 @@ def compile(self, block: Type[Block], refinements: Refinements = Refinements(), raise CompilerCheckError(f"error during compilation:\n{design.errors_str()}") return design - def close(self): + def close(self) -> None: assert self.process is not None self.process.stdin.close() self.process.stdout.close() diff --git a/edg/core/TransformUtil.py b/edg/core/TransformUtil.py index 3876cb1a8..7cb5de39f 100644 --- a/edg/core/TransformUtil.py +++ b/edg/core/TransformUtil.py @@ -18,7 +18,7 @@ class Path(NamedTuple): # internal helper type def __hash__(self) -> int: return hash((self.blocks, self.links, self.ports, self.params)) - def __eq__(self, other) -> bool: + def __eq__(self, other: Any) -> bool: return isinstance(other, Path) and self.blocks == other.blocks and self.links == other.links and \ self.ports == other.ports and self.params == other.params @@ -72,7 +72,7 @@ def append_param(self, name: str) -> Path: def block_component(self) -> Path: return Path(self.blocks, (), (), ()) - def link_component(self, must_have_link=True) -> Path: + def link_component(self, must_have_link: bool=True) -> Path: if must_have_link: assert self.links return Path(self.blocks, self.links, (), ()) diff --git a/edg/core/test_block_description.py b/edg/core/test_block_description.py index 341b0d928..60d773df9 100644 --- a/edg/core/test_block_description.py +++ b/edg/core/test_block_description.py @@ -14,7 +14,7 @@ def __init__(self) -> None: class DescriptionBlockProtoTestCase(unittest.TestCase): - def test_description(self): + def test_description(self) -> None: pb = DescriptionBlock()._elaborated_def_to_proto() self.assertEqual(len(pb.description), 3) diff --git a/edg/core/test_block_eltdict.py b/edg/core/test_block_eltdict.py index ab6c551e3..13dac845d 100644 --- a/edg/core/test_block_eltdict.py +++ b/edg/core/test_block_eltdict.py @@ -6,7 +6,7 @@ class EltDictBlock(Block): """Block with an EltDict of sub-blocks""" - def contents(self): + def contents(self) -> None: super().contents() self.sink = ElementDict[Block]() self.sink[0] = self.Block(TestBlockSink()) @@ -19,7 +19,7 @@ def contents(self): class EltDictBlockProtoTestCase(unittest.TestCase): - def test_connectivity(self): + def test_connectivity(self) -> None: pb = EltDictBlock()._elaborated_def_to_proto() self.assertEqual(pb.blocks[0].name, 'sink[0]') self.assertEqual(pb.blocks[0].value.lib_elem.base.target.name, "edg.core.test_common.TestBlockSink") diff --git a/edg/core/test_connect_array.py b/edg/core/test_connect_array.py index 11759b328..3bce8eb6f 100644 --- a/edg/core/test_connect_array.py +++ b/edg/core/test_connect_array.py @@ -19,14 +19,14 @@ def __init__(self) -> None: self.sinks = self.Port(Vector(TestPortSink())) self.generator_param(self.sinks.requested()) - def generate(self): + def generate(self) -> None: super().generate() for request in self.get(self.sinks.requested()): self.sinks.append_elt(TestPortSink(), request) class ArrayConnectBlock(Block): - def contents(self): + def contents(self) -> None: super().contents() self.source = self.Block(TestBlockSourceFixedArray()) @@ -73,7 +73,7 @@ def test_connectivity(self) -> None: class ArrayAllocatedConnectBlock(Block): - def contents(self): + def contents(self) -> None: super().contents() self.source1 = self.Block(TestBlockSourceFixedArray()) diff --git a/edg/core/test_default.py b/edg/core/test_default.py index ff2582eb8..c097eda82 100644 --- a/edg/core/test_default.py +++ b/edg/core/test_default.py @@ -1,4 +1,5 @@ import unittest +from typing import Any from .. import edgir from . import * @@ -23,55 +24,55 @@ def __init__(self, nondefault_param: IntLike = IntExpr()) -> None: class DefaultParamSubClass(EmptyDefaultParamClass): # adds a default param on top of the inherited params - def __init__(self, default_param: IntLike = 42, **kwargs) -> None: + def __init__(self, default_param: IntLike = 42, **kwargs: Any) -> None: super().__init__(**kwargs) class OverrideDefaultSubClass(DefaultParamSubClass): # changes the default param of the parent - def __init__(self, default_param: IntLike = 16, **kwargs) -> None: + def __init__(self, default_param: IntLike = 16, **kwargs: Any) -> None: super().__init__(default_param, **kwargs) class CombinedParamSubClass(DefaultParamSubClass): # adds a default param on top of the inherited params def __init__(self, nondefault_param2: FloatLike = FloatExpr(), - default_param2: StringLike = "test", **kwargs) -> None: + default_param2: StringLike = "test", **kwargs: Any) -> None: super().__init__(**kwargs) class DefaultTestCase(unittest.TestCase): - def test_base(self): + def test_base(self) -> None: pb = BaseParamClass()._elaborated_def_to_proto() self.assertEqual(len(pb.param_defaults), 0) - def test_non_default(self): + def test_non_default(self) -> None: pb = NonDefaultParamClass()._elaborated_def_to_proto() # type: ignore self.assertEqual(len(pb.param_defaults), 0) - def test_non_default_subclass(self): + def test_non_default_subclass(self) -> None: pb = NonDefaultParamSubClass()._elaborated_def_to_proto() self.assertEqual(len(pb.param_defaults), 0) - def test_empty_default(self): + def test_empty_default(self) -> None: pb = EmptyDefaultParamClass()._elaborated_def_to_proto() self.assertEqual(len(pb.param_defaults), 0) - def test_default(self): + def test_default(self) -> None: pb = DefaultParamSubClass()._elaborated_def_to_proto() self.assertEqual(len(pb.param_defaults), 1) self.assertEqual(pb.param_defaults['default_param'], edgir.lit_to_expr(42)) - def test_override(self): + def test_override(self) -> None: pb = OverrideDefaultSubClass()._elaborated_def_to_proto() self.assertEqual(len(pb.param_defaults), 1) self.assertEqual(pb.param_defaults['default_param'], edgir.lit_to_expr(16)) - def test_combined(self): + def test_combined(self) -> None: pb = CombinedParamSubClass()._elaborated_def_to_proto() self.assertEqual(len(pb.param_defaults), 2) diff --git a/edg/core/test_design_inst.py b/edg/core/test_design_inst.py index c8ae39df9..83019ec98 100644 --- a/edg/core/test_design_inst.py +++ b/edg/core/test_design_inst.py @@ -21,7 +21,7 @@ def __init__(self) -> None: class DesignInstantiationTestCase(unittest.TestCase): - def test_single_hierarchy(self): + def test_single_hierarchy(self) -> None: """ Tests design instantiation with a single level of hierarchy blocks. Only tests that the contained blocks are instantiated and structurally correct, does not check internal constraints @@ -104,7 +104,7 @@ def test_single_hierarchy(self): expanded.block_port.ref.steps.add().name = 'sink' self.assertIn(expected_conn, constraints) - def test_exported_hierarchy(self): + def test_exported_hierarchy(self) -> None: compiled_design = ScalaCompiler.compile(ExportPortHierarchyBlockTop) self.assertEqual(compiled_design.contents.blocks[0].name, 'block') pb = compiled_design.contents.blocks[0].value.hierarchy @@ -134,7 +134,7 @@ def test_exported_hierarchy(self): expected_conn.exported.internal_block_port.ref.steps.add().name = 'sink' self.assertIn(expected_conn, constraints) - def test_bridge_hierarchy(self): + def test_bridge_hierarchy(self) -> None: compiled_design = ScalaCompiler.compile(PortBridgeHierarchyBlockTop) self.assertEqual(compiled_design.contents.blocks[0].name, 'block') pb = compiled_design.contents.blocks[0].value.hierarchy diff --git a/edg/core/test_generator.py b/edg/core/test_generator.py index d5734e34a..c386a4a1d 100644 --- a/edg/core/test_generator.py +++ b/edg/core/test_generator.py @@ -60,17 +60,17 @@ def generate(self) -> None: class TestGenerator(unittest.TestCase): - def test_generator_assign(self): + def test_generator_assign(self) -> None: compiled = ScalaCompiler.compile(TestGeneratorAssign) self.assertEqual(compiled.get_value(['block', 'float_param']), 2.0) - def test_generator_dependency(self): + def test_generator_dependency(self) -> None: compiled = ScalaCompiler.compile(TestGeneratorDependency) self.assertEqual(compiled.get_value(['block', 'float_param']), 6.0) - def test_generator_multi_dependency(self): + def test_generator_multi_dependency(self) -> None: compiled = ScalaCompiler.compile(TestGeneratorMultiParameter) self.assertEqual(compiled.get_value(['block', 'float_param1']), 15.0) @@ -130,7 +130,7 @@ def generate(self) -> None: class TestGeneratorConnectedTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.generator = self.Block(GeneratorIsConnected()) self.sink = self.Block(TestBlockSink((0.5, 2.5))) @@ -138,7 +138,7 @@ def __init__(self): class TestGeneratorNotConnectedTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.generator = self.Block(GeneratorIsConnected()) @@ -154,7 +154,7 @@ def generate(self) -> None: class TestGeneratorInnerConnectTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.generator = self.Block(GeneratorInnerConnect()) self.sink = self.Block(TestBlockSink((1.5, 3.5))) @@ -162,19 +162,19 @@ def __init__(self): class TestGeneratorConnect(unittest.TestCase): - def test_generator_connected(self): + def test_generator_connected(self) -> None: compiled = ScalaCompiler.compile(TestGeneratorConnectedTop) self.assertEqual(compiled.get_value(['generator', 'connected']), True) self.assertEqual(compiled.get_value(['link', 'source_float']), 2.0) self.assertEqual(compiled.get_value(['link', 'sinks_range']), Range(0.5, 2.5)) - def test_generator_not_connected(self): + def test_generator_not_connected(self) -> None: compiled = ScalaCompiler.compile(TestGeneratorNotConnectedTop) self.assertEqual(compiled.get_value(['generator', 'connected']), False) - def test_generator_inner_connect(self): + def test_generator_inner_connect(self) -> None: compiled = ScalaCompiler.compile(TestGeneratorInnerConnectTop) self.assertEqual(compiled.get_value(['link', 'source_float']), 4.5) diff --git a/edg/core/test_generator_portvector.py b/edg/core/test_generator_portvector.py index 3c57d0e6d..c11c48db8 100644 --- a/edg/core/test_generator_portvector.py +++ b/edg/core/test_generator_portvector.py @@ -33,10 +33,10 @@ def __init__(self) -> None: class TestGeneratorPortVector(unittest.TestCase): - def test_generator(self): + def test_generator(self) -> None: ScalaCompiler.compile(TestGeneratorElements) - def test_initializer(self): + def test_initializer(self) -> None: compiled = ScalaCompiler.compile(TestGeneratorElements) pb = compiled.contents.blocks[0].value.hierarchy self.assertEqual(pb.constraints[1].name, "(init)ports.0.range_param") @@ -64,7 +64,7 @@ def __init__(self) -> None: class TestPortVectorInvalid(unittest.TestCase): - def test_generator_error(self): + def test_generator_error(self) -> None: with self.assertRaises(CompilerCheckError): ScalaCompiler.compile(TestElementsInvalid) @@ -90,10 +90,10 @@ def __init__(self) -> None: class TestGeneratorWrapper(unittest.TestCase): - def test_generator(self): + def test_generator(self) -> None: ScalaCompiler.compile(GeneratorWrapperTest) - def test_exported_ports(self): + def test_exported_ports(self) -> None: compiled = ScalaCompiler.compile(GeneratorWrapperTest) pb = edgir.pair_get(compiled.contents.blocks, 'block').hierarchy @@ -136,5 +136,5 @@ def __init__(self) -> None: class TestGeneratorArrayParam(unittest.TestCase): - def test_generator(self): + def test_generator(self) -> None: ScalaCompiler.compile(GeneratorArrayParamTop) diff --git a/edg/core/test_hierarchy_block.py b/edg/core/test_hierarchy_block.py index d4885e609..a38f4758d 100644 --- a/edg/core/test_hierarchy_block.py +++ b/edg/core/test_hierarchy_block.py @@ -6,7 +6,7 @@ class TopHierarchyBlock(Block): - def contents(self): + def contents(self) -> None: super().contents() self.source = self.Block(TestBlockSource()) @@ -64,7 +64,7 @@ def test_connectivity(self) -> None: class MultiConnectBlock(Block): - def contents(self): + def contents(self) -> None: super().contents() self.source = self.Block(TestBlockSource()) @@ -118,7 +118,7 @@ def test_connectivity(self) -> None: class ConnectJoinBlock(Block): - def contents(self): + def contents(self) -> None: super().contents() self.source = self.Block(TestBlockSource()) @@ -213,7 +213,7 @@ def __init__(self) -> None: super().__init__() self.exported = self.Port(TestPortSink(), optional=True) # avoid required constraint - def contents(self): + def contents(self) -> None: super().contents() self.sink = self.Block(TestBlockSink()) self.test_net = self.connect(self.exported, self.sink.sink) @@ -244,7 +244,7 @@ def __init__(self) -> None: super().__init__() self.source_port = self.Port(TestPortSink(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.sink1 = self.Block(TestBlockSink()) self.sink2 = self.Block(TestBlockSink()) diff --git a/edg/core/test_initializer.py b/edg/core/test_initializer.py index 2eb7441e1..a28df5aa6 100644 --- a/edg/core/test_initializer.py +++ b/edg/core/test_initializer.py @@ -43,7 +43,7 @@ def contents(self) -> None: class InitializerTestCase(unittest.TestCase): - def test_initializer(self): + def test_initializer(self) -> None: pb = TestSingleInitializerBlock()._elaborated_def_to_proto() self.assertEqual(len(pb.constraints), 3) @@ -54,7 +54,7 @@ def test_initializer(self): self.assertEqual(pb.constraints[2].name, "(init)bundle_port.b.float_param") self.assertEqual(pb.constraints[2].value, edgir.AssignLit(['bundle_port', 'b', 'float_param'], -1.0)) - def test_nested_initializer(self): + def test_nested_initializer(self) -> None: pb = TestNestedBlock()._elaborated_def_to_proto() self.assertEqual(len(pb.constraints), 5) @@ -69,7 +69,7 @@ def test_nested_initializer(self): self.assertEqual(pb.constraints[4].name, "(init)inner.bundle_param") self.assertEqual(pb.constraints[4].value, edgir.AssignLit(['inner', 'bundle_param'], 31.0)) - def test_nested_inner(self): + def test_nested_inner(self) -> None: pb = TestInternalBlock()._elaborated_def_to_proto() self.assertEqual(len(pb.constraints), 3) # should not generate initializers for constructors @@ -79,14 +79,14 @@ def test_nested_inner(self): self.assertEqual(pb.constraints[1].name, "(init)inner_bundle.a.float_param") self.assertEqual(pb.constraints[2].name, "(init)inner_bundle.b.float_param") - def test_default_initializer(self): + def test_default_initializer(self) -> None: pb = TestDefaultBlock()._elaborated_def_to_proto() self.assertEqual(len(pb.constraints), 1) self.assertEqual(pb.constraints[0].name, "(init)inner.inner_param") self.assertEqual(pb.constraints[0].value, edgir.AssignLit(['inner', 'inner_param'], 3.0)) - def test_multiple_initializer(self): + def test_multiple_initializer(self) -> None: pb = TestMultipleInstantiationBlock()._elaborated_def_to_proto() self.assertEqual(len(pb.constraints), 2) diff --git a/edg/core/test_link.py b/edg/core/test_link.py index 57caaf747..9197db79c 100644 --- a/edg/core/test_link.py +++ b/edg/core/test_link.py @@ -6,18 +6,18 @@ class LinkTestCase(unittest.TestCase): - def setUp(self): + def setUp(self) -> None: self.pb = TestLink()._elaborated_def_to_proto() - def test_self_class(self): + def test_self_class(self) -> None: self.assertEqual(self.pb.self_class.target.name, "edg.core.test_elaboration_common.TestLink") - def test_superclasses(self): + def test_superclasses(self) -> None: self.assertEqual(len(self.pb.superclasses), 1) self.assertEqual(self.pb.superclasses[0].target.name, "edg.core.test_elaboration_common.TestLinkBase") self.assertEqual(len(self.pb.super_superclasses), 0) - def test_param_def(self): + def test_param_def(self) -> None: self.assertEqual(len(self.pb.params), 3) self.assertTrue(self.pb.params[0].name, 'float_param_sink_sum') self.assertTrue(self.pb.params[0].value.HasField('floating')) @@ -26,14 +26,14 @@ def test_param_def(self): self.assertTrue(self.pb.params[2].name, 'range_param_sink_common') self.assertTrue(self.pb.params[2].value.HasField('range')) - def test_port_def(self): + def test_port_def(self) -> None: self.assertEqual(len(self.pb.ports), 2) self.assertTrue(self.pb.ports[0].name, 'source') self.assertEqual(self.pb.ports[0].value.lib_elem.target.name, "edg.core.test_elaboration_common.TestPortSource") self.assertTrue(self.pb.ports[1].name, 'sinks') self.assertEqual(self.pb.ports[1].value.array.self_class.target.name, "edg.core.test_elaboration_common.TestPortSink") - def test_constraints(self): + def test_constraints(self) -> None: # partial test of constraints, only the ones that are more interesting than tested elsewhere # namely, ones that deal with map and reduce operations constraints = list(map(lambda pair: pair.value, self.pb.constraints)) diff --git a/edg/core/test_mixin.py b/edg/core/test_mixin.py index f998b65b2..7b9e75dac 100644 --- a/edg/core/test_mixin.py +++ b/edg/core/test_mixin.py @@ -1,4 +1,5 @@ import unittest +from typing import Any from .. import edgir from . import * @@ -13,7 +14,7 @@ def __init__(self) -> None: class TestMixin(BlockInterfaceMixin[TestMixinBase]): - def __init__(self, *args, mixin_float: FloatLike = 1.0, **kwargs) -> None: + def __init__(self, *args: Any, mixin_float: FloatLike = 1.0, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.mixin_port = self.Port(TestPortSink()) self.mixin_float = self.ArgParameter(mixin_float) diff --git a/edg/core/test_mixin_errors.py b/edg/core/test_mixin_errors.py index e946d4719..9834c6917 100644 --- a/edg/core/test_mixin_errors.py +++ b/edg/core/test_mixin_errors.py @@ -1,7 +1,7 @@ import unittest from . import * -from .HdlUserExceptions import BlockDefinitionError +from .HdlUserExceptions import BlockDefinitionError, EdgTypeError from .test_block import TestBlock from .test_mixin import TestMixin, TestMixinBase, TestMixinConcreteBlock @@ -57,5 +57,5 @@ def contents(self) -> None: self.mixin = self.block.with_mixin(TestMixin()) def test_bad_base_mixin(self) -> None: - with self.assertRaises(TypeError): + with self.assertRaises(EdgTypeError): self.BadBaseMixin()._elaborated_def_to_proto() diff --git a/edg/core/test_multipack.py b/edg/core/test_multipack.py index 29bb10763..bd561d7c1 100644 --- a/edg/core/test_multipack.py +++ b/edg/core/test_multipack.py @@ -15,7 +15,7 @@ def __init__(self) -> None: class MultipackBlockSink(MultipackBlock): """Unlike a real multipack block, this is simplified and has no implementation.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.sink1 = self.PackedPart(PartSink()) @@ -40,12 +40,12 @@ def __init__(self) -> None: class TopMultipackDesign(DesignTop): - def contents(self): + def contents(self) -> None: super().contents() self.sink1 = self.Block(PartSink()) self.sink2 = self.Block(TestBlockContainerSink()) - def multipack(self): + def multipack(self) -> None: self.packed = self.Block(MultipackBlockSink()) self.pack(self.packed.sink1, ['sink1']) self.pack(self.packed.sink2, ['sink2', 'inner']) @@ -110,7 +110,7 @@ def test_assign_unpacked_tunnel(self) -> None: class MultipackArrayBlockSink(MultipackBlock): """Same as above, but with array constructs.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.sinks = self.PackedPart(PackedBlockArray(PartSink())) self.sink_ports = self.PackedExport(self.sinks.ports_array(lambda x: x.sink)) @@ -121,12 +121,12 @@ def __init__(self): class TopMultipackArrayDesign(DesignTop): - def contents(self): + def contents(self) -> None: super().contents() self.sink1 = self.Block(PartSink()) self.sink2 = self.Block(TestBlockContainerSink()) - def multipack(self): + def multipack(self) -> None: self.packed = self.Block(MultipackArrayBlockSink()) self.pack(self.packed.sinks.request('1'), ['sink1']) self.pack(self.packed.sinks.request('2'), ['sink2', 'inner']) diff --git a/edg/core/test_port.py b/edg/core/test_port.py index e98929d87..a961d7ccf 100644 --- a/edg/core/test_port.py +++ b/edg/core/test_port.py @@ -6,27 +6,27 @@ class PortProtoTestCase(unittest.TestCase): - def setUp(self): + def setUp(self) -> None: self.pb = cast(edgir.Port, TestPortBase()._def_to_proto()) # TODO eliminate cast - def test_contains_param(self): + def test_contains_param(self) -> None: self.assertEqual(len(self.pb.params), 1) self.assertEqual(self.pb.params[0].name, 'float_param') self.assertTrue(self.pb.params[0].value.HasField('floating')) class PortSourceProtoTestCase(unittest.TestCase): - def setUp(self): + def setUp(self) -> None: self.pb = cast(edgir.Port, TestPortSource()._def_to_proto()) - def test_self_class(self): + def test_self_class(self) -> None: self.assertEqual(self.pb.self_class.target.name, "edg.core.test_elaboration_common.TestPortSource") - def test_superclasses(self): + def test_superclasses(self) -> None: self.assertEqual(len(self.pb.superclasses), 1) self.assertEqual(self.pb.superclasses[0].target.name, "edg.core.test_elaboration_common.TestPortBase") - def test_contains_param(self): + def test_contains_param(self) -> None: self.assertEqual(len(self.pb.params), 3) self.assertTrue(self.pb.params[0].name, 'float_param') self.assertTrue(self.pb.params[0].value.HasField('floating')) diff --git a/edg/core/test_port_adapter.py b/edg/core/test_port_adapter.py index 9b2e7082b..c3eb88fb1 100644 --- a/edg/core/test_port_adapter.py +++ b/edg/core/test_port_adapter.py @@ -6,14 +6,14 @@ class AdapterLink(Link): - def __init__(self): + def __init__(self) -> None: super().__init__() self.ports = self.Port(Vector(AdapterPort())) class AdapterPortAdapter(PortAdapter[TestPortSource]): - def __init__(self): + def __init__(self) -> None: super().__init__() self.src = self.Port(AdapterPort()) @@ -28,13 +28,13 @@ def as_test_src(self) -> TestPortSource: class AdapterBlock(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(AdapterPort()) class AdapterTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.adapter_src = self.Block(AdapterBlock()) diff --git a/edg/core/test_port_bridge.py b/edg/core/test_port_bridge.py index f7745fbf2..88de86b3c 100644 --- a/edg/core/test_port_bridge.py +++ b/edg/core/test_port_bridge.py @@ -6,16 +6,16 @@ class PortBridgeProtoTestCase(unittest.TestCase): - def setUp(self): + def setUp(self) -> None: self.pb = TestPortBridge()._elaborated_def_to_proto() - def test_contains_param(self): + def test_contains_param(self) -> None: self.assertEqual(self.pb.ports[0].name, 'outer_port') self.assertEqual(self.pb.ports[0].value.lib_elem.target.name, "edg.core.test_elaboration_common.TestPortSink") self.assertEqual(self.pb.ports[1].name, 'inner_link') self.assertEqual(self.pb.ports[1].value.lib_elem.target.name, "edg.core.test_elaboration_common.TestPortSource") - def test_constraints(self): + def test_constraints(self) -> None: self.assertEqual(len(self.pb.constraints), 2) constraints = list(map(lambda pair: pair.value, self.pb.constraints)) @@ -38,12 +38,12 @@ def test_constraints(self): class BadPortBridge(PortBridge): - def __init__(self): + def __init__(self) -> None: super().__init__() self.bad_port = self.Port(TestPortSink()) class PortBridgeBadPortsTestCase(unittest.TestCase): - def test_bad_ports(self): + def test_bad_ports(self) -> None: with self.assertRaises(AssertionError): BadPortBridge()._elaborated_def_to_proto() diff --git a/edg/core/test_range.py b/edg/core/test_range.py index b4cc31af6..62d622b1a 100644 --- a/edg/core/test_range.py +++ b/edg/core/test_range.py @@ -56,7 +56,7 @@ def test_intersects(self) -> None: self.assertFalse(Range(-1, 2).intersects(Range(3, 4))) self.assertFalse(Range(-1, 2).intersects(Range(-3, -2))) - def test_intersect(self): + def test_intersect(self) -> None: self.assertEqual(Range(-1, 2).intersect(Range(2, 3)), Range(2, 2)) self.assertEqual(Range(-1, 2).intersect(Range(0, 3)), Range(0, 2)) self.assertEqual(Range(-1, 2).intersect(Range(-2, -1)), Range(-1, -1)) @@ -65,7 +65,7 @@ def test_intersect(self): with self.assertRaises(ValueError): Range(-1, 2).intersect(Range(3, 4)) - def test_hull(self): + def test_hull(self) -> None: self.assertEqual(Range(-1, 2).hull(Range(2, 3)), Range(-1, 3)) self.assertEqual(Range(-1, 2).hull(Range(0, 3)), Range(-1, 3)) self.assertEqual(Range(-1, 2).hull(Range(-2, -1)), Range(-2, 2)) diff --git a/edg/core/test_simple_const_prop.py b/edg/core/test_simple_const_prop.py index cf0151e53..bc0411cd0 100644 --- a/edg/core/test_simple_const_prop.py +++ b/edg/core/test_simple_const_prop.py @@ -22,7 +22,7 @@ def __init__(self) -> None: self.range_const = self.Parameter(RangeExpr()) self.range_param = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: self.assign(self.float_const, 2.0) self.assign(self.float_param, self.float_const) diff --git a/edg/core/test_simple_expr_eval.py b/edg/core/test_simple_expr_eval.py index dbebfca0a..dc06211b1 100644 --- a/edg/core/test_simple_expr_eval.py +++ b/edg/core/test_simple_expr_eval.py @@ -11,7 +11,7 @@ def __init__(self) -> None: self.sum_float = self.Parameter(FloatExpr(2 * LiteralConstructor(1) + 3 * LiteralConstructor(1))) self.sum_range = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: self.assign(self.sum_range, (2, 6) * LiteralConstructor(1) + (7, 8) * LiteralConstructor(1)) diff --git a/edg/electronics_model/AnalogPort.py b/edg/electronics_model/AnalogPort.py index edaed2d37..18d10530d 100644 --- a/edg/electronics_model/AnalogPort.py +++ b/edg/electronics_model/AnalogPort.py @@ -128,7 +128,7 @@ def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink], *, signal_limit_bound: Optional[Tuple[FloatLike, FloatLike]] = None, signal_limit_abs: Optional[RangeLike] = None, current_draw: RangeLike = RangeExpr.ZERO, - impedance: RangeLike = RangeExpr.INF): + impedance: RangeLike = RangeExpr.INF) -> 'AnalogSink': supply_range = VoltageLink._supply_voltage_range(neg, pos) if voltage_limit_tolerance is not None: assert voltage_limit_abs is None @@ -174,7 +174,7 @@ def __init__(self, voltage_limits: RangeLike = RangeExpr.ALL, signal_limits: Ran class AnalogSourceAdapterVoltageSource(CircuitPortAdapter[VoltageSource]): - def __init__(self): + def __init__(self) -> None: super().__init__() self.src = self.Port(AnalogSink( # otherwise ideal current_draw=RangeExpr() @@ -193,7 +193,7 @@ def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink], *, signal_out_bound: Optional[Tuple[FloatLike, FloatLike]] = None, signal_out_abs: Optional[RangeLike] = None, current_limits: RangeLike = RangeExpr.ALL, - impedance: RangeLike = RangeExpr.ZERO): + impedance: RangeLike = RangeExpr.ZERO) -> 'AnalogSource': supply_range = VoltageLink._supply_voltage_range(neg, pos) if signal_out_bound is not None: assert signal_out_abs is None diff --git a/edg/electronics_model/BomBackend.py b/edg/electronics_model/BomBackend.py index 1278e0c55..36231ae84 100644 --- a/edg/electronics_model/BomBackend.py +++ b/edg/electronics_model/BomBackend.py @@ -16,9 +16,8 @@ class BomItem(NamedTuple): class GenerateBom(BaseBackend): # creates and populates .csv file - def run(self, design: CompiledDesign, args=None) -> List[Tuple[edgir.LocalPath, str]]: - if args is None: - args = {} + def run(self, design: CompiledDesign, args: Dict[str, str]= {}) -> List[Tuple[edgir.LocalPath, str]]: + assert not args bom_list = BomTransform(design).run() bom_string = io.StringIO() diff --git a/edg/electronics_model/CircuitBlock.py b/edg/electronics_model/CircuitBlock.py index 89809ff20..c2760aa72 100644 --- a/edg/electronics_model/CircuitBlock.py +++ b/edg/electronics_model/CircuitBlock.py @@ -7,7 +7,7 @@ from ..core import IdentityDict # TODO: this is ugly from ..core.ConstraintExpr import Refable from .KiCadImportableBlock import KiCadImportableBlock - +from ..core.HdlUserExceptions import EdgTypeError CircuitLinkType = TypeVar('CircuitLinkType', bound=Link, covariant=True) class CircuitPort(Port[CircuitLinkType], Generic[CircuitLinkType]): @@ -35,7 +35,7 @@ class FootprintBlock(Block): Provides interfaces that define footprints and copper connections and generates to appropriate metadata. """ # TODO perhaps don't allow part / package initializers since those shouldn't be used - def __init__(self, *args, **kwargs) -> None: + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.fp_footprint = self.Parameter(StringExpr()) self.fp_pinning = self.Parameter(ArrayStringExpr()) @@ -59,7 +59,7 @@ def footprint(self, refdes: StringLike, footprint: StringLike, pinning: Mapping[ if self._elaboration_state not in (BlockElaborationState.init, BlockElaborationState.contents, BlockElaborationState.generate): - raise BlockDefinitionError(self, "can't call Footprint(...) outside __init__, contents or generate", + raise BlockDefinitionError(type(self), "can't call Footprint(...) outside __init__, contents or generate", "call Footprint(...) inside those functions, and remember to make the super() call") self.fp_is_footprint = self.Metadata("") @@ -67,7 +67,7 @@ def footprint(self, refdes: StringLike, footprint: StringLike, pinning: Mapping[ pinning_array = [] for pin_name, pin_port in pinning.items(): if not isinstance(pin_port, CircuitPort): - raise TypeError(f"pin port to Footprint(...) must be CircuitPort, got {pin_port} of type {type(pin_port)}") + raise EdgTypeError(f"Footprint(...) pin", pin_port, CircuitPort) pinning_array.append(f'{pin_name}={pin_port._name_from(self)}') self.assign(self.fp_pinning, pinning_array) @@ -97,21 +97,21 @@ class WrapperFootprintBlock(FootprintBlock): Useful for, for example, a breakout board where the modelling details are provided by internal chip blocks, but needs to show up as only a carrier board footprint. EXPERIMENTAL - API SUBJECT TO CHANGE.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.fp_is_wrapper = self.Metadata("A") # TODO replace with not metadata, eg superclass inspection @abstract_block class NetBlock(InternalBlock, NetBaseBlock, Block): - def contents(self): + def contents(self) -> None: super().contents() self.net() @abstract_block class CircuitPortBridge(NetBaseBlock, PortBridge): - def contents(self): + def contents(self) -> None: super().contents() self.net() @@ -123,13 +123,13 @@ def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]: assert symbol_name == 'edg_importable:Adapter' return {'1': self.src, '2': self.dst} - def contents(self): + def contents(self) -> None: super().contents() self.net() @non_library # TODO make abstract instead? class CircuitLink(NetBaseBlock, Link): - def contents(self): + def contents(self) -> None: super().contents() self.net() diff --git a/edg/electronics_model/CircuitPackingBlock.py b/edg/electronics_model/CircuitPackingBlock.py index 17d449689..927a9205f 100644 --- a/edg/electronics_model/CircuitPackingBlock.py +++ b/edg/electronics_model/CircuitPackingBlock.py @@ -17,14 +17,14 @@ def packed(self, elts: BasePort, merged: BasePort) -> None: class PackedPassive(NetPackingBlock, GeneratorBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.elts = self.Port(Vector(Passive.empty())) self.merged = self.Port(Passive.empty()) self.generator_param(self.elts.requested()) self.packed(self.elts, self.merged) - def generate(self): + def generate(self) -> None: super().generate() self.elts.defined() for request in self.get(self.elts.requested()): @@ -34,7 +34,7 @@ def generate(self): class PackedGround(NetPackingBlock, GeneratorBlock): """Takes in several Ground connections that are of the same net (asserted in netlister), and provides a single Ground.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd_ins = self.Port(Vector(Ground.empty())) self.gnd_out = self.Port(GroundReference( @@ -43,7 +43,7 @@ def __init__(self): self.generator_param(self.gnd_ins.requested()) self.packed(self.gnd_ins, self.gnd_out) - def generate(self): + def generate(self) -> None: super().generate() self.gnd_ins.defined() for in_request in self.get(self.gnd_ins.requested()): @@ -57,7 +57,7 @@ class PackedVoltageSource(NetPackingBlock, GeneratorBlock): """Takes in several VoltageSink connections that are of the same net (asserted in netlister), and provides a single VoltageSource. Distributes the current draw from the VoltageSource equally among the inputs.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr_ins = self.Port(Vector(VoltageSink.empty())) self.pwr_out = self.Port(VoltageSource( @@ -67,7 +67,7 @@ def __init__(self): self.generator_param(self.pwr_ins.requested()) self.packed(self.pwr_ins, self.pwr_out) - def generate(self): + def generate(self) -> None: super().generate() self.pwr_ins.defined() for in_request in self.get(self.pwr_ins.requested()): diff --git a/edg/electronics_model/ConnectedGenerator.py b/edg/electronics_model/ConnectedGenerator.py index 3aa942121..f8f73d4e5 100644 --- a/edg/electronics_model/ConnectedGenerator.py +++ b/edg/electronics_model/ConnectedGenerator.py @@ -36,7 +36,7 @@ def __init__(self, in_is_connected: BoolLike = BoolExpr()) -> None: self.in_is_connected = self.ArgParameter(in_is_connected) self.generator_param(self.in_is_connected) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.in_is_connected): self.connect(self.out, self.in_connected) diff --git a/edg/electronics_model/DigitalPorts.py b/edg/electronics_model/DigitalPorts.py index ac1b235ef..0c344240c 100644 --- a/edg/electronics_model/DigitalPorts.py +++ b/edg/electronics_model/DigitalPorts.py @@ -51,7 +51,7 @@ def __init__(self) -> None: self._has_low_signal_driver = self.Parameter(BoolExpr()) self._has_high_signal_driver = self.Parameter(BoolExpr()) - def contents(self): + def contents(self) -> None: super().contents() self.description = DescriptionString( @@ -245,7 +245,7 @@ def contents(self) -> None: class DigitalSourceAdapterVoltageSource(CircuitPortAdapter[VoltageSource]): - def __init__(self): + def __init__(self) -> None: super().__init__() self.src = self.Port(DigitalSink( # otherwise ideal current_draw=RangeExpr() @@ -501,7 +501,7 @@ def __call__(self, voltage_out: RangeLike = RangeExpr.ZERO, high_driver=high_signal_driver ) - def empty(self): + def empty(self) -> DigitalSource: return DigitalSource.empty() diff --git a/edg/electronics_model/GroundPort.py b/edg/electronics_model/GroundPort.py index ff120e9d8..1e08a940c 100644 --- a/edg/electronics_model/GroundPort.py +++ b/edg/electronics_model/GroundPort.py @@ -1,6 +1,6 @@ from __future__ import annotations -from typing import TYPE_CHECKING +from typing import TYPE_CHECKING, Any from ..core import * from .CircuitBlock import CircuitPortBridge, CircuitPortAdapter, CircuitLink, CircuitPort from .Units import Volt, Ohm @@ -13,7 +13,7 @@ class GroundLink(CircuitLink): @classmethod - def _voltage_range(cls, port: Port[GroundLink]): + def _voltage_range(cls, port: Port[GroundLink]) -> RangeExpr: if isinstance(port, Ground): return port.is_connected().then_else(port.link().voltage, RangeExpr._to_expr_type(RangeExpr.ZERO)) @@ -59,7 +59,7 @@ def contents(self) -> None: class GroundAdapterVoltageSource(CircuitPortAdapter['VoltageSource']): - def __init__(self): + def __init__(self) -> None: from .VoltagePorts import VoltageSource super().__init__() self.src = self.Port(Ground()) @@ -69,7 +69,7 @@ def __init__(self): class GroundAdapterDigitalSource(CircuitPortAdapter['DigitalSource']): - def __init__(self): + def __init__(self) -> None: from .DigitalPorts import DigitalSource super().__init__() self.src = self.Port(Ground()) @@ -80,7 +80,7 @@ def __init__(self): class GroundAdapterAnalogSource(CircuitPortAdapter['AnalogSource']): - def __init__(self): + def __init__(self) -> None: from .AnalogPort import AnalogSource super().__init__() @@ -124,7 +124,7 @@ def __init__(self, voltage_out: RangeLike = RangeExpr.ZERO) -> None: from deprecated import deprecated @deprecated("Use Ground() or GroundReference(...), Ground is no longer directioned") -def GroundSource(*args, **kwargs): +def GroundSource(*args: Any, **kwargs: Any) -> Ground: return Ground() diff --git a/edg/electronics_model/KiCadSchematicBlock.py b/edg/electronics_model/KiCadSchematicBlock.py index af9030d8c..d3f0881cc 100644 --- a/edg/electronics_model/KiCadSchematicBlock.py +++ b/edg/electronics_model/KiCadSchematicBlock.py @@ -56,7 +56,7 @@ def __init__(self, kicad_pins: ArrayStringLike, kicad_refdes_prefix: StringLike, self.kicad_pins = self.ArgParameter(kicad_pins) self.generator_param(self.kicad_pins) - def generate(self): + def generate(self) -> None: super().generate() mapping = {pin_name: self.ports.append_elt(Passive(), pin_name) for pin_name in self.get(self.kicad_pins)} @@ -150,7 +150,7 @@ def inner(root: Any, components: List[str]) -> Optional[BasePort]: """ def import_kicad(self, filepath: str, locals: Mapping[str, Any] = {}, *, nodes: Mapping[str, Optional[BasePort]] = {}, conversions: Mapping[str, CircuitPort] = {}, - auto_adapt: bool = False): + auto_adapt: bool = False) -> None: # ideally SYMBOL_MAP would be a class variable, but this causes a import loop with Opamp, # so declaring it here causes it to reference Opamp lazily from ..abstract_parts import Resistor, Capacitor, Opamp diff --git a/edg/electronics_model/KiCadSchematicParser.py b/edg/electronics_model/KiCadSchematicParser.py index 1278ea792..afed1d01f 100644 --- a/edg/electronics_model/KiCadSchematicParser.py +++ b/edg/electronics_model/KiCadSchematicParser.py @@ -1,6 +1,6 @@ import itertools from enum import Enum -from typing import List, Any, Dict, Tuple, TypeVar, Type, Set, NamedTuple, Union, Iterable +from typing import List, Any, Dict, Tuple, TypeVar, Type, Set, NamedTuple, Union, Iterable, cast import math import sexpdata # type: ignore @@ -51,12 +51,12 @@ def parse_at(sexp: List[Any], expected_car: str = 'at') -> Tuple[float, float, f def parse_symbol(sexp: Any) -> str: """Asserts sexp is a Symbol and returns its value.""" assert isinstance(sexp, sexpdata.Symbol) - return sexp.value() + return cast(str, sexp.value()) class KiCadLibPin: """Pin in a library symbol""" - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.number} @ {self.pos})" def __init__(self, sexp: List[Any]): @@ -69,7 +69,7 @@ def __init__(self, sexp: List[Any]): class KiCadLibSymbol: """Symbol in a library""" - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.name})" def __init__(self, sexp: List[Any]): @@ -86,7 +86,7 @@ def __init__(self, sexp: List[Any]): class KiCadWire: - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.pt1}, {self.pt2})" def __init__(self, sexp: List[Any]): @@ -99,16 +99,16 @@ def __init__(self, sexp: List[Any]): class KiCadTunnel: - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.name} @ {self.pt})" - def __init__(self): + def __init__(self) -> None: self.name: str self.pt: PointType class KiCadBaseLabel(KiCadTunnel): - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.name} @ {self.pt})" def __init__(self, sexp: List[Any]): @@ -145,10 +145,10 @@ def __init__(self, name: str, pt: PointType): class KiCadMarker: - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.pt})" - def __init__(self): + def __init__(self) -> None: self.pt: PointType @@ -161,7 +161,7 @@ def __init__(self, sexp: List[Any]): class KiCadSymbol: - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.refdes}, {self.lib} @ {self.pos})" def __init__(self, sexp: List[Any]): @@ -186,7 +186,7 @@ def __init__(self, sexp: List[Any]): class KiCadPin: - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}({self.refdes}.{self.pin_number} @ {self.pt})" def __init__(self, symbol: KiCadSymbol, pin: KiCadLibPin): @@ -220,7 +220,7 @@ class ParsedNet(NamedTuple): labels: List[KiCadTunnel] pins: List[KiCadPin] - def __repr__(self): + def __repr__(self) -> str: return f"{self.__class__.__name__}(labels={self.labels}, pins={self.pins})" diff --git a/edg/electronics_model/NetlistGenerator.py b/edg/electronics_model/NetlistGenerator.py index 3698b5655..28a5ac512 100644 --- a/edg/electronics_model/NetlistGenerator.py +++ b/edg/electronics_model/NetlistGenerator.py @@ -49,7 +49,7 @@ class BoardScope(NamedTuple): assert_connected: List[Tuple[TransformUtil.Path, TransformUtil.Path]] @classmethod - def empty(cls, path: TransformUtil.Path): # returns a fresh, empty BordScope + def empty(cls, path: TransformUtil.Path) -> 'BoardScope': # returns a fresh, empty BordScope return BoardScope(path, {}, {}, {}, []) diff --git a/edg/electronics_model/PassivePort.py b/edg/electronics_model/PassivePort.py index 68d883de3..82566e85a 100644 --- a/edg/electronics_model/PassivePort.py +++ b/edg/electronics_model/PassivePort.py @@ -12,7 +12,7 @@ class PassiveLink(CircuitLink): """Copper-only connection""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.passives = self.Port(Vector(Passive())) @@ -158,4 +158,4 @@ def adapt_to(self, that: AdaptTargetType) -> AdaptTargetType: assert param.initializer is not None, f"missing initializer for {param_name}" adapter_init_kwargs[param_name] = param.initializer - return self._convert(adapter_cls(**adapter_init_kwargs)) + return self._convert(adapter_cls(**adapter_init_kwargs)) # type: ignore diff --git a/edg/electronics_model/SvgPcbBackend.py b/edg/electronics_model/SvgPcbBackend.py index 54f24aa0d..95015fc42 100644 --- a/edg/electronics_model/SvgPcbBackend.py +++ b/edg/electronics_model/SvgPcbBackend.py @@ -185,7 +185,7 @@ def run(self, design: CompiledDesign, args: Dict[str, str] = {}) -> List[Tuple[e def _generate(self, design: CompiledDesign, netlist: Netlist) -> str: """Generates SVBPCB fragments as a structured result""" - def block_matches_prefixes(block: NetBlock, prefixes: List[Tuple[str, ...]]): + def block_matches_prefixes(block: NetBlock, prefixes: List[Tuple[str, ...]]) -> bool: for prefix in prefixes: if block.full_path.blocks[0:min(len(block.full_path.blocks), len(prefix))] == prefix: return True diff --git a/edg/electronics_model/SvgPcbTemplateBlock.py b/edg/electronics_model/SvgPcbTemplateBlock.py index af50ef678..85e90180d 100644 --- a/edg/electronics_model/SvgPcbTemplateBlock.py +++ b/edg/electronics_model/SvgPcbTemplateBlock.py @@ -15,7 +15,7 @@ class SvgPcbTemplateBlock(Block): This defines the interface and supporting utilities only.""" @staticmethod - def _svgpcb_pathname_to_svgpcb(path: TransformUtil.Path): + def _svgpcb_pathname_to_svgpcb(path: TransformUtil.Path) -> str: return '_'.join(path.to_tuple()).replace('[', '_').replace(']', '_') @staticmethod diff --git a/edg/electronics_model/VoltagePorts.py b/edg/electronics_model/VoltagePorts.py index 39906cb40..77d33f0f0 100644 --- a/edg/electronics_model/VoltagePorts.py +++ b/edg/electronics_model/VoltagePorts.py @@ -13,7 +13,7 @@ class VoltageLink(CircuitLink): @classmethod - def _voltage_range(cls, port: Port[VoltageLink]): + def _voltage_range(cls, port: Port[VoltageLink]) -> RangeExpr: """Returns the voltage for a Voltage port, either sink or source""" if isinstance(port, VoltageSource): return port.voltage_out @@ -23,7 +23,7 @@ def _voltage_range(cls, port: Port[VoltageLink]): raise TypeError @classmethod - def _supply_voltage_range(cls, neg: Port[GroundLink], pos: Port[VoltageLink]): + def _supply_voltage_range(cls, neg: Port[GroundLink], pos: Port[VoltageLink]) -> RangeExpr: """For a negative and positive Voltage port (either sink or source), returns the voltage span.""" return GroundLink._voltage_range(neg).hull(cls._voltage_range(pos)) @@ -108,7 +108,7 @@ class VoltageBase(CircuitPort[VoltageLink]): # TODO: support isolation domains and offset grounds # these are here (instead of in VoltageSource) since the port may be on the other side of a bridge - def as_ground(self, current_draw) -> GroundReference: + def as_ground(self, current_draw: RangeLike) -> GroundReference: """Adapts this port to a ground. Current draw is the current drawn from this port, and is required since ground does not model current draw. """ @@ -153,7 +153,7 @@ def __init__(self, current_draw: RangeLike): class VoltageSinkAdapterDigitalSource(CircuitPortAdapter['DigitalSource']): - def __init__(self): + def __init__(self) -> None: from .DigitalPorts import DigitalSource super().__init__() self.src = self.Port(VoltageSink( @@ -168,7 +168,7 @@ def __init__(self): class VoltageSinkAdapterAnalogSource(CircuitPortAdapter['AnalogSource']): - def __init__(self): + def __init__(self) -> None: from .AnalogPort import AnalogSource super().__init__() @@ -182,9 +182,7 @@ def __init__(self): )) # TODO might be an overestimate - # TODO debug the type ignore. Seems to go away after poking, and reappears on a dmypy restart - # Perhaps a circular reference issue? - self.assign(self.src.current_draw, self.dst.link().current_drawn) # type: ignore + self.assign(self.src.current_draw, self.dst.link().current_drawn) class VoltageSource(VoltageBase): diff --git a/edg/electronics_model/test_analog_link.py b/edg/electronics_model/test_analog_link.py index 0799b76cb..73cb304c4 100644 --- a/edg/electronics_model/test_analog_link.py +++ b/edg/electronics_model/test_analog_link.py @@ -4,13 +4,13 @@ class AnalogSourceBlock(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(AnalogSource()) class AnalogSinkInfiniteBlock(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(AnalogSink( impedance=RangeExpr.INF, @@ -18,7 +18,7 @@ def __init__(self): class AnalogSinkOneOhmBlock(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(AnalogSink( impedance=(1, 1)*Ohm, @@ -26,7 +26,7 @@ def __init__(self): class AnalogTwoInfiniteTest(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.source = self.Block(AnalogSourceBlock()) self.sink1 = self.Block(AnalogSinkInfiniteBlock()) @@ -35,7 +35,7 @@ def __init__(self): class AnalogTwoOneOhmTest(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.source = self.Block(AnalogSourceBlock()) self.sink1 = self.Block(AnalogSinkOneOhmBlock()) @@ -44,7 +44,7 @@ def __init__(self): class AnalogMixedTest(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.source = self.Block(AnalogSourceBlock()) self.sink1 = self.Block(AnalogSinkInfiniteBlock()) diff --git a/edg/electronics_model/test_i2c_link.py b/edg/electronics_model/test_i2c_link.py index 25f267fdd..8a2363462 100644 --- a/edg/electronics_model/test_i2c_link.py +++ b/edg/electronics_model/test_i2c_link.py @@ -4,13 +4,13 @@ class I2cControllerBlock(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(I2cController()) class I2cPullupBlock(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.port = self.Port(I2cPullupPort()) @@ -22,7 +22,7 @@ def __init__(self, address: IntLike): class I2cTest(DesignTop): - def __init__(self): + def __init__(self) -> None: super().__init__() self.controller = self.Block(I2cControllerBlock()) self.pull = self.Block(I2cPullupBlock()) @@ -34,7 +34,7 @@ def __init__(self): class I2cNoPullTest(DesignTop): - def __init__(self): + def __init__(self) -> None: super().__init__() self.controller = self.Block(I2cControllerBlock()) self.device1 = self.Block(I2cTargetBlock(1)) @@ -42,7 +42,7 @@ def __init__(self): class I2cConflictTest(DesignTop): - def __init__(self): + def __init__(self) -> None: super().__init__() self.controller = self.Block(I2cControllerBlock()) self.pull = self.Block(I2cPullupBlock()) diff --git a/edg/electronics_model/test_kicad.py b/edg/electronics_model/test_kicad.py index 0dad35e1f..047c8d8ee 100644 --- a/edg/electronics_model/test_kicad.py +++ b/edg/electronics_model/test_kicad.py @@ -1,6 +1,6 @@ import os import unittest -from typing import Type +from typing import Type, Tuple from . import * from . import test_netlist @@ -9,27 +9,27 @@ class NetlistTestCase(unittest.TestCase): - def generate_net(self, design: Type[Block]): + def generate_net(self, design: Type[Block]) -> Tuple[str, str]: compiled = ScalaCompiler.compile(design) compiled.append_values(RefdesRefinementPass().run(compiled)) return NetlistBackend().run(compiled)[0][1], GenerateBom().run(compiled)[0][1] - def test_basic_kicad(self): + def test_basic_kicad(self) -> None: (net, bom) = self.generate_net(test_netlist.TestBasicCircuit) with open(os.path.splitext(os.path.basename(__file__))[0] + '_basic.net', 'w') as f: f.write(net) with open(os.path.splitext(os.path.basename(__file__))[0] + '_basic.csv', 'w') as f: f.write(bom) - def test_multisink_kicad(self): + def test_multisink_kicad(self) -> None: (net, bom) = self.generate_net(test_netlist.TestMultisinkCircuit) with open(os.path.splitext(os.path.basename(__file__))[0] + '_multisink.net', 'w') as f: f.write(net) with open(os.path.splitext(os.path.basename(__file__))[0] + '_multisink.csv', 'w') as f: f.write(bom) - def test_multinet_kicad(self): + def test_multinet_kicad(self) -> None: (net, bom) = self.generate_net(test_netlist.TestMultinetCircuit) with open(os.path.splitext(os.path.basename(__file__))[0] + '_multinet.net', 'w') as f: f.write(net) diff --git a/edg/electronics_model/test_kicad_fail.py b/edg/electronics_model/test_kicad_fail.py index e96c80450..c9cabc8e0 100644 --- a/edg/electronics_model/test_kicad_fail.py +++ b/edg/electronics_model/test_kicad_fail.py @@ -27,14 +27,14 @@ def __init__(self) -> None: class KiCadImportFailTestCase(unittest.TestCase): - def test_missing_port(self): + def test_missing_port(self) -> None: with self.assertRaises(Exception): KiCadMissingPort()._elaborated_def_to_proto() - def test_aliased_port(self): + def test_aliased_port(self) -> None: with self.assertRaises(Exception): KiCadAliasedPort()._elaborated_def_to_proto() - def test_aliased_link(self): + def test_aliased_link(self) -> None: with self.assertRaises(Exception): KiCadAliasedLink()._elaborated_def_to_proto() diff --git a/edg/electronics_model/test_kicad_import.py b/edg/electronics_model/test_kicad_import.py index 091b23f01..f902013c7 100644 --- a/edg/electronics_model/test_kicad_import.py +++ b/edg/electronics_model/test_kicad_import.py @@ -130,48 +130,48 @@ def __init__(self) -> None: class KiCadImportProtoTestCase(unittest.TestCase): - def test_block(self): + def test_block(self) -> None: self.check_connectivity(KiCadBlock) - def test_block_aliased_pin_name(self): + def test_block_aliased_pin_name(self) -> None: self.check_connectivity(KiCadBlockAliasedPinName) - def test_hierarchy_label_block(self): + def test_hierarchy_label_block(self) -> None: self.check_connectivity(KiCadHierarchyLabelBlock) - def test_tunnel_block(self): + def test_tunnel_block(self) -> None: self.check_connectivity(KiCadTunnelBlock) - def test_inline_block(self): + def test_inline_block(self) -> None: self.check_connectivity(KiCadInlineBlock) - def test_inline_badmultiline(self): + def test_inline_badmultiline(self) -> None: with self.assertRaises(AssertionError): self.check_connectivity(KiCadInlineBlockBadMultiline) - def test_inline_vars_block(self): + def test_inline_vars_block(self) -> None: self.check_connectivity(KiCadInlineVarsBlock) - def test_codeparts_block(self): + def test_codeparts_block(self) -> None: self.check_connectivity(KiCadCodePartsBock) - def test_node_block(self): + def test_node_block(self) -> None: self.check_connectivity(KiCadNodeBlock) - def test_power_block(self): + def test_power_block(self) -> None: self.check_connectivity(KiCadPowerBlock) - def test_modified_symbol_block(self): + def test_modified_symbol_block(self) -> None: self.check_connectivity(KiCadModifiedSymbolBlock) - def test_aliased_port(self): + def test_aliased_port(self) -> None: with self.assertRaises(AssertionError): self.check_connectivity(KiCadBlockAliasedPort) - def test_overlapped_port(self): + def test_overlapped_port(self) -> None: self.check_connectivity(KiCadBlockOverlappedPort) - def check_connectivity(self, cls: Type[KiCadSchematicBlock]): + def check_connectivity(self, cls: Type[KiCadSchematicBlock]) -> None: """Checks the connectivity of the generated proto, since the examples have similar structures.""" pb = cls()._elaborated_def_to_proto() constraints = list(map(lambda pair: pair.value, pb.constraints)) diff --git a/edg/electronics_model/test_kicad_import_blackbox.py b/edg/electronics_model/test_kicad_import_blackbox.py index 5f7ea5cff..3f676e22b 100644 --- a/edg/electronics_model/test_kicad_import_blackbox.py +++ b/edg/electronics_model/test_kicad_import_blackbox.py @@ -28,7 +28,7 @@ def __init__(self) -> None: class KiCadImportBlackboxTestCase(unittest.TestCase): - def test_import_blackbox(self): + def test_import_blackbox(self) -> None: # the elaborate_toplevel wrapper is needed since the inner block uses array ports pb = Builder.builder.elaborate_toplevel(KiCadBlackboxBlock()) constraints = list(map(lambda pair: pair.value, pb.constraints)) @@ -81,7 +81,7 @@ def test_import_blackbox(self): self.assertIn(edgir.AssignLit(['SYM1', 'kicad_refdes_prefix'], 'SYM'), constraints) self.assertIn(edgir.AssignLit(['SYM1', 'kicad_footprint'], 'Symbol:Symbol_ESD-Logo_CopperTop'), constraints) - def test_import_blackbox_autoadapt(self): + def test_import_blackbox_autoadapt(self) -> None: # the elaborate_toplevel wrapper is needed since the inner block uses array ports pb = Builder.builder.elaborate_toplevel(KiCadBlackboxBlockAutoadapt()) constraints = list(map(lambda pair: pair.value, pb.constraints)) diff --git a/edg/electronics_model/test_kicad_import_bundle.py b/edg/electronics_model/test_kicad_import_bundle.py index 7b661d5cf..364ac6b63 100644 --- a/edg/electronics_model/test_kicad_import_bundle.py +++ b/edg/electronics_model/test_kicad_import_bundle.py @@ -16,7 +16,7 @@ def __init__(self) -> None: class KiCadImportProtoTestCase(unittest.TestCase): - def test_conversion_block(self): + def test_conversion_block(self) -> None: # because this generates an adapter, the structure differs from the other KiCad import tests # this also doesn't re-check the other structure, only the conversions # (and that it doesn't connection-error out in the first place) diff --git a/edg/electronics_model/test_kicad_import_conversion.py b/edg/electronics_model/test_kicad_import_conversion.py index 704d9bdf6..e5bd71627 100644 --- a/edg/electronics_model/test_kicad_import_conversion.py +++ b/edg/electronics_model/test_kicad_import_conversion.py @@ -27,18 +27,18 @@ def __init__(self) -> None: class KiCadImportProtoTestCase(unittest.TestCase): - def test_conversion_block(self): + def test_conversion_block(self) -> None: # because this generates an adapter, the structure differs from the other KiCad import tests # this also doesn't re-check the other structure, only the conversions # (and that it doesn't connection-error out in the first place) pb = KiCadConversionBlock()._elaborated_def_to_proto() self.validate(pb) - def test_boundary_conversion_block(self): + def test_boundary_conversion_block(self) -> None: pb = KiCadBoundaryConversionBlock()._elaborated_def_to_proto() self.validate(pb) - def validate(self, pb: edgir.HierarchyBlock): + def validate(self, pb: edgir.HierarchyBlock) -> None: constraints = list(map(lambda pair: pair.value, pb.constraints)) expected_conn = edgir.ValueExpr() diff --git a/edg/electronics_model/test_kicad_schematic_parser.py b/edg/electronics_model/test_kicad_schematic_parser.py index 845b0d009..b57fdb27b 100644 --- a/edg/electronics_model/test_kicad_schematic_parser.py +++ b/edg/electronics_model/test_kicad_schematic_parser.py @@ -14,19 +14,19 @@ def net_to_tuple(net: ParsedNet) -> Tuple[Set[Tuple[Type, str]], Set[str]]: class KiCadSchematicParserTest(unittest.TestCase): - def test_kicad(self): + def test_kicad(self) -> None: self.check_schematic_rcs("test_kicad_import.kicad_sch") - def test_kicad_rot(self): + def test_kicad_rot(self) -> None: self.check_schematic_rcs("test_kicad_import_rot.kicad_sch") - def test_kicad_tunnel(self): + def test_kicad_tunnel(self) -> None: self.check_schematic_rcs("test_kicad_import_tunnel.kicad_sch") - def test_kicad_modified_symbol(self): + def test_kicad_modified_symbol(self) -> None: self.check_schematic_rcs("test_kicad_import_modified_symbol.kicad_sch") - def check_schematic_rcs(self, filename): + def check_schematic_rcs(self, filename: str) -> None: with open(os.path.join(os.path.dirname(__file__), "resources", filename), "r") as file: file_data = file.read() sch = KiCadSchematic(file_data) @@ -41,7 +41,7 @@ def check_schematic_rcs(self, filename): self.assertIn(('R2', 'Device:R'), symbols) self.assertIn(('C1', 'Device:C'), symbols) - def test_kicad_power(self): + def test_kicad_power(self) -> None: # this one differs because it has the additional power "labels" with open(os.path.join(os.path.dirname(__file__), "resources", "test_kicad_import_power.kicad_sch"), "r") as file: file_data = file.read() @@ -57,13 +57,13 @@ def test_kicad_power(self): self.assertIn(('R2', 'Device:R'), symbols) self.assertIn(('C1', 'Device:C'), symbols) - def test_degenerate_label(self): + def test_degenerate_label(self) -> None: with open(os.path.join(os.path.dirname(__file__), "resources", "test_kicad_import_badlabel.kicad_sch"), "r") as file: file_data = file.read() with self.assertRaises(ValueError): KiCadSchematic(file_data) - def test_noconnect(self): + def test_noconnect(self) -> None: with open(os.path.join(os.path.dirname(__file__), "resources", "test_kicad_import_nc.kicad_sch"), "r") as file: file_data = file.read() sch = KiCadSchematic(file_data) @@ -73,28 +73,28 @@ def test_noconnect(self): self.assertIn(({(KiCadLabel, 'node')}, {'R1.2', 'R2.1', 'C1.1'}), nets) self.assertIn(({(KiCadLabel, 'GND')}, {'R2.2', 'C1.2'}), nets) - def check_bad_noconnect(self, filename): + def check_bad_noconnect(self, filename: str) -> None: with open(os.path.join(os.path.dirname(__file__), "resources", filename), "r") as file: file_data = file.read() with self.assertRaises(ValueError): KiCadSchematic(file_data) - def test_kicad_noconnect_disconnected(self): + def test_kicad_noconnect_disconnected(self) -> None: self.check_bad_noconnect("test_kicad_import_nc_baddis.kicad_sch") - def test_kicad_noconnect_multiple(self): + def test_kicad_noconnect_multiple(self) -> None: self.check_bad_noconnect("test_kicad_import_nc_badmult.kicad_sch") - def test_kicad_mirrorx(self): + def test_kicad_mirrorx(self) -> None: self.check_schematic_fet("test_kicad_import_mirrorx.kicad_sch") - def test_kicad_mirrory(self): + def test_kicad_mirrory(self) -> None: self.check_schematic_fet("test_kicad_import_mirrory.kicad_sch") - def test_kicad_mirrory_rot(self): + def test_kicad_mirrory_rot(self) -> None: self.check_schematic_fet("test_kicad_import_mirrory_rot.kicad_sch") - def check_schematic_fet(self, filename): + def check_schematic_fet(self, filename: str) -> None: """R and Cs are symmetric and don't test for mirroring well.""" with open(os.path.join(os.path.dirname(__file__), "resources", filename), "r") as file: file_data = file.read() @@ -105,7 +105,7 @@ def check_schematic_fet(self, filename): self.assertIn(({(KiCadGlobalLabel, 'gate')}, {'Q1.2'}), nets) self.assertIn(({(KiCadGlobalLabel, 'source')}, {'Q1.3'}), nets) - def test_connectedports(self): + def test_connectedports(self) -> None: """Schematic with two connected ports without components.""" with open(os.path.join(os.path.dirname(__file__), "resources", "test_kicad_import_connectedports.kicad_sch"), "r") as file: file_data = file.read() diff --git a/edg/electronics_model/test_netlist.py b/edg/electronics_model/test_netlist.py index a961eea6f..896d5d189 100644 --- a/edg/electronics_model/test_netlist.py +++ b/edg/electronics_model/test_netlist.py @@ -6,7 +6,7 @@ from ..core import * from .VoltagePorts import VoltageSource, VoltageSink from .CircuitBlock import FootprintBlock -from .NetlistGenerator import NetlistTransform, NetPin as RawNetPin, NetBlock as RawNetBlock, Net +from .NetlistGenerator import NetlistTransform, NetPin as RawNetPin, NetBlock as RawNetBlock, Net, Netlist from .RefdesRefinementPass import RefdesRefinementPass @@ -185,7 +185,7 @@ def contents(self) -> None: class NetlistTestCase(unittest.TestCase): @staticmethod - def generate_net(design: Type[Block], refinements: Refinements = Refinements()): + def generate_net(design: Type[Block], refinements: Refinements = Refinements()) -> Netlist: compiled = ScalaCompiler.compile(design, refinements) compiled.append_values(RefdesRefinementPass().run(compiled)) return NetlistTransform(compiled).run() diff --git a/edg/electronics_model/test_partplacer.py b/edg/electronics_model/test_partplacer.py index b0a9838c8..7d781a744 100644 --- a/edg/electronics_model/test_partplacer.py +++ b/edg/electronics_model/test_partplacer.py @@ -6,7 +6,7 @@ class PartPlacerTestCase(unittest.TestCase): - def test_placement(self): + def test_placement(self) -> None: u1 = NetBlock( footprint="Package_QFP:LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm", refdes="U1", part="", value="", full_path=TransformUtil.Path.empty().append_block("U1"), path=[], class_path=[] @@ -30,7 +30,7 @@ def test_placement(self): self.assertAlmostEqual(arranged.elts[2][1][0], 12.78, places=2) self.assertAlmostEqual(arranged.elts[2][1][1], 3.19, places=2) - def test_placement_hierarchical(self): + def test_placement_hierarchical(self) -> None: u1 = NetBlock( footprint="Package_QFP:LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm", refdes="U1", part="", value="", full_path=TransformUtil.Path.empty().append_block('A').append_block("U1"), path=[], class_path=[] @@ -77,7 +77,7 @@ def test_placement_hierarchical(self): self.assertAlmostEqual(flattened[TransformUtil.Path.empty().append_block('B').append_block('R3')][0], 1.48, places=2) self.assertAlmostEqual(flattened[TransformUtil.Path.empty().append_block('B').append_block('R3')][1], 14.03, places=2) - def test_placement_bbox(self): + def test_placement_bbox(self) -> None: r1 = NetBlock( footprint="Resistor_SMD:R_0603_1608Metric", refdes="R1", part="", value="", full_path=TransformUtil.Path.empty().append_block("R1"), path=[], class_path=[] diff --git a/edg/electronics_model/test_units.py b/edg/electronics_model/test_units.py index 48e01d6ef..1eeb3ce84 100644 --- a/edg/electronics_model/test_units.py +++ b/edg/electronics_model/test_units.py @@ -4,7 +4,7 @@ class UnitsTestCase(unittest.TestCase): - def test_units(self): + def test_units(self) -> None: self.assertEqual(UnitUtils.num_to_prefix(1, 3), '1') self.assertEqual(UnitUtils.num_to_prefix(1000, 3), '1k') self.assertEqual(UnitUtils.num_to_prefix(0.001, 3), '1m') diff --git a/edg/electronics_model/test_voltage_bridge.py b/edg/electronics_model/test_voltage_bridge.py index c98948bb9..fb40a4d89 100644 --- a/edg/electronics_model/test_voltage_bridge.py +++ b/edg/electronics_model/test_voltage_bridge.py @@ -5,8 +5,8 @@ class VoltageBridgeTestCase(unittest.TestCase): - def setUp(self): + def setUp(self) -> None: self.pb = VoltageSinkBridge()._elaborated_def_to_proto() - def test_metadata(self): + def test_metadata(self) -> None: self.assertIn('nets', self.pb.meta.members.node) \ No newline at end of file diff --git a/edg/electronics_model/test_voltage_link.py b/edg/electronics_model/test_voltage_link.py index 234f811ce..e5d56d779 100644 --- a/edg/electronics_model/test_voltage_link.py +++ b/edg/electronics_model/test_voltage_link.py @@ -4,8 +4,8 @@ class VoltageLinkTestCase(unittest.TestCase): - def setUp(self): + def setUp(self) -> None: self.pb = VoltageLink()._elaborated_def_to_proto() - def test_metadata(self): + def test_metadata(self) -> None: self.assertIn('nets', self.pb.meta.members.node) diff --git a/edg/hdl_server/__main__.py b/edg/hdl_server/__main__.py index 253601d5e..9e737f5fe 100644 --- a/edg/hdl_server/__main__.py +++ b/edg/hdl_server/__main__.py @@ -15,7 +15,7 @@ class LibraryElementIndexer: """Indexer for libraries, recursively searches modules and their LibraryElements.""" - def __init__(self): + def __init__(self) -> None: self.seen_modules: Set[ModuleType] = set() self.seen_elements: Set[Type[LibraryElement]] = set() @@ -58,15 +58,15 @@ def elaborate_class(elt_cls: Type[LibraryElementType]) -> Tuple[LibraryElementTy if isinstance(obj, Block): block_proto = builder.elaborate_toplevel(obj) - return obj, edgir.Library.NS.Val(hierarchy_block=block_proto) # type: ignore + return obj, edgir.Library.NS.Val(hierarchy_block=block_proto) elif isinstance(obj, Link): link_proto = builder.elaborate_toplevel(obj) assert isinstance(link_proto, edgir.Link) # TODO this needs to be cleaned up - return obj, edgir.Library.NS.Val(link=link_proto) # type: ignore + return obj, edgir.Library.NS.Val(link=link_proto) elif isinstance(obj, Bundle): # TODO: note Bundle extends Port, so this must come first - return obj, edgir.Library.NS.Val(bundle=obj._def_to_proto()) # type: ignore + return obj, edgir.Library.NS.Val(bundle=obj._def_to_proto()) elif isinstance(obj, Port): - return obj, edgir.Library.NS.Val(port=cast(edgir.Port, obj._def_to_proto())) # type: ignore + return obj, edgir.Library.NS.Val(port=cast(edgir.Port, obj._def_to_proto())) else: raise RuntimeError(f"didn't match type of library element {elt_cls}") @@ -79,7 +79,7 @@ def class_from_library(elt: edgir.LibraryPath, expected_superclass: Type[Library assert inspect.ismodule(elt_module) cls = getattr(elt_module, elt_split[-1]) assert issubclass(cls, expected_superclass) - return cls + return cls # type: ignore def process_request(request: edgrpc.HdlRequest) -> Optional[edgrpc.HdlResponse]: @@ -147,7 +147,7 @@ def process_request(request: edgrpc.HdlRequest) -> Optional[edgrpc.HdlResponse]: traceback.print_exc() return response -def run_server(): +def run_server() -> None: stdin_deserializer = BufferDeserializer(edgrpc.HdlRequest, sys.stdin.buffer) stdout_serializer = BufferSerializer[edgrpc.HdlResponse](sys.stdout.buffer) diff --git a/edg/jlcparts/JlcPartsBase.py b/edg/jlcparts/JlcPartsBase.py index b0514bfae..09329b1a2 100644 --- a/edg/jlcparts/JlcPartsBase.py +++ b/edg/jlcparts/JlcPartsBase.py @@ -29,7 +29,7 @@ class JlcPartsAttributeEntry(BaseModel): class JlcPartsAttributes(RootModel): root: dict[str, JlcPartsAttributeEntry] - def get(self, key: str, expected_type: Type[ParsedType], default: Optional[ParsedType] = None, sub='default') -> ParsedType: + def get(self, key: str, expected_type: Type[ParsedType], default: Optional[ParsedType] = None, sub: str = 'default') -> ParsedType: """Utility function that gets an attribute of the specified name, checking that it is the expected type or returning some default (if specified).""" if key not in self.root: @@ -90,7 +90,7 @@ class JlcPartsBase(JlcPart, PartsTableAreaSelector, PartsTableFootprintFilter): COST_COL = PartsTableColumn(str) @staticmethod - def config_root_dir(root_dir: str): + def config_root_dir(root_dir: str) -> None: """Configures the root dir that contains the data files from jlcparts, eg CapacitorsMultilayer_Ceramic_Capacitors_MLCC___SMDakaSMT.json.gz This setting is on a JlcPartsBase-wide basis.""" diff --git a/edg/jlcparts/JlcPartsInductor.py b/edg/jlcparts/JlcPartsInductor.py index 8fd316478..d970a7609 100644 --- a/edg/jlcparts/JlcPartsInductor.py +++ b/edg/jlcparts/JlcPartsInductor.py @@ -37,7 +37,7 @@ def _entry_to_table_row(cls, row_dict: Dict[PartsTableColumn, Any], filename: st except (KeyError, TypeError, PartParserUtil.ParseError): return None - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) # because the table does not have frequency specs, the table filter can't enforce frequency ratings # so the user must add the actual frequency rating in refinements diff --git a/edg/jlcparts/JlcPartsMlcc.py b/edg/jlcparts/JlcPartsMlcc.py index 83ea64f98..4022bd96d 100644 --- a/edg/jlcparts/JlcPartsMlcc.py +++ b/edg/jlcparts/JlcPartsMlcc.py @@ -7,7 +7,7 @@ class JlcPartsMlcc(PartsTableSelectorFootprint, JlcPartsBase, TableDeratingCapacitor, CeramicCapacitor): _JLC_PARTS_FILE_NAMES = ["CapacitorsMultilayer_Ceramic_Capacitors_MLCC___SMDakaSMT"] - def __init__(self, *args, capacitance_minimum_size: BoolLike = True, **kwargs): + def __init__(self, *args: Any, capacitance_minimum_size: BoolLike = True, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.capacitance_minimum_size = self.ArgParameter(capacitance_minimum_size) self.generator_param(self.capacitance_minimum_size) diff --git a/edg/parts/AnalogSwitch_7400.py b/edg/parts/AnalogSwitch_7400.py index 9a3fd26e6..938351849 100644 --- a/edg/parts/AnalogSwitch_7400.py +++ b/edg/parts/AnalogSwitch_7400.py @@ -3,7 +3,7 @@ class Sn74lvc1g3157_Device(InternalSubcircuit, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground()) @@ -29,7 +29,7 @@ def __init__(self): self.b1 = self.Port(Passive(), optional=True) self.b0 = self.Port(Passive(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -52,7 +52,7 @@ def contents(self): class Sn74lvc1g3157(AnalogSwitch): """2:1 analog switch, 6ohm Ron(typ), in SOT-363. """ - def contents(self): + def contents(self) -> None: super().contents() self.require(~self.control_gnd.is_connected(), "device does not support control ground") diff --git a/edg/parts/AnalogSwitch_Dg468.py b/edg/parts/AnalogSwitch_Dg468.py index 73dba9222..9beab7765 100644 --- a/edg/parts/AnalogSwitch_Dg468.py +++ b/edg/parts/AnalogSwitch_Dg468.py @@ -3,7 +3,7 @@ class Dg468_Device(InternalSubcircuit, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vn = self.Port(Ground()) @@ -28,7 +28,7 @@ def __init__(self): self.com = self.Port(Passive()) self.no = self.Port(Passive(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -51,11 +51,11 @@ def contents(self): class Dg468(AnalogSwitch, GeneratorBlock): """DG468 36V 10ohm SPST switch in normally-open configuration """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.generator_param(self.control_gnd.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Dg468_Device()) @@ -74,7 +74,7 @@ def contents(self): capacitance=0.1*uFarad(tol=0.2), )).connected(self.gnd, self.pwr) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.control_gnd.is_connected()): self.connect(self.control_gnd, self.ic.gnd) diff --git a/edg/parts/AnalogSwitch_Nlas4157.py b/edg/parts/AnalogSwitch_Nlas4157.py index 29ef5a91b..4be0aa4bd 100644 --- a/edg/parts/AnalogSwitch_Nlas4157.py +++ b/edg/parts/AnalogSwitch_Nlas4157.py @@ -5,7 +5,7 @@ class Nlas4157_Device(InternalSubcircuit, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vcc = self.Port(VoltageSink( @@ -31,7 +31,7 @@ def __init__(self): self.b1 = self.Port(Passive(), optional=True) self.b0 = self.Port(Passive(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -58,7 +58,7 @@ class Nlas4157(AnalogSwitch): - TS5A3159: 5v tolerant, 1 ohm - TS5A3160: 5v tolerant, 1 ohm """ - def contents(self): + def contents(self) -> None: super().contents() self.require(~self.control_gnd.is_connected(), "device does not support control ground") diff --git a/edg/parts/Batteries.py b/edg/parts/Batteries.py index eb44d2be8..b22f425a7 100644 --- a/edg/parts/Batteries.py +++ b/edg/parts/Batteries.py @@ -1,11 +1,11 @@ -from typing import Optional, Union +from typing import Optional, Union, Any from ..abstract_parts import * class Cr2032(Battery, FootprintBlock): - def __init__(self, voltage: RangeLike = (2.0, 3.0)*Volt, *args, - actual_voltage: RangeLike = (2.0, 3.0)*Volt, **kwargs): + def __init__(self, voltage: RangeLike = (2.0, 3.0)*Volt, *args: Any, + actual_voltage: RangeLike = (2.0, 3.0)*Volt, **kwargs: Any) -> None: super().__init__(voltage, *args, **kwargs) self.pwr.init_from(VoltageSource( voltage_out=self.gnd.link().voltage + actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf @@ -13,7 +13,7 @@ def __init__(self, voltage: RangeLike = (2.0, 3.0)*Volt, *args, )) self.gnd.init_from(Ground()) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_capacity, (210, 210)*mAmp) # TODO bounds of a few CR2032 cells; should be A*h @@ -29,8 +29,8 @@ def contents(self): class Li18650(Battery, FootprintBlock): - def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args, - actual_voltage: RangeLike = (2.5, 4.2)*Volt, **kwargs): + def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args: Any, + actual_voltage: RangeLike = (2.5, 4.2)*Volt, **kwargs: Any) -> None: super().__init__(voltage, *args, **kwargs) self.pwr.init_from(VoltageSource( voltage_out=self.gnd.link().voltage + actual_voltage, @@ -38,7 +38,7 @@ def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args, )) self.gnd.init_from(Ground()) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_capacity, (2, 3.6)*Amp) # TODO should be A*h @@ -55,8 +55,8 @@ def contents(self): class AaBattery(Battery, FootprintBlock): """AA battery holder supporting alkaline and rechargeable chemistries.""" - def __init__(self, voltage: RangeLike = (1.0, 1.6)*Volt, *args, - actual_voltage: RangeLike = (1.0, 1.6)*Volt, **kwargs): + def __init__(self, voltage: RangeLike = (1.0, 1.6)*Volt, *args: Any, + actual_voltage: RangeLike = (1.0, 1.6)*Volt, **kwargs: Any) -> None: super().__init__(voltage, *args, **kwargs) self.gnd.init_from(Ground()) self.pwr.init_from(VoltageSource( @@ -64,7 +64,7 @@ def __init__(self, voltage: RangeLike = (1.0, 1.6)*Volt, *args, current_limits=(0, 1)*Amp, )) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_capacity, (2, 3)*Amp) # TODO should be A*h @@ -87,7 +87,7 @@ def __init__(self, count: IntLike = 1, *, cell_actual_voltage: RangeLike = (1.0, self.cell_actual_voltage = self.ArgParameter(cell_actual_voltage) self.generator_param(self.count) - def generate(self): + def generate(self) -> None: super().generate() prev_cell: Optional[AaBattery] = None prev_capacity_min: Union[FloatExpr, float] = float('inf') diff --git a/edg/parts/Bldc_Drv8313.py b/edg/parts/Bldc_Drv8313.py index b4fe7f85c..ab028c314 100644 --- a/edg/parts/Bldc_Drv8313.py +++ b/edg/parts/Bldc_Drv8313.py @@ -119,7 +119,7 @@ def __init__(self, *, risense_res: RangeLike = 100*mOhm(tol=0.05)) -> None: self.risense_res = self.ArgParameter(risense_res) self.generator_param(self.pgnd_sense.requested()) - def contents(self): + def contents(self) -> None: super().contents() self.vm_cap_bulk = self.Block(DecouplingCapacitor((10*0.8, 100)*uFarad)).connected(self.gnd, self.ic.vm) self.vm_cap1 = self.Block(DecouplingCapacitor((0.1*0.8, 100)*uFarad)).connected(self.gnd, self.ic.vm) @@ -140,7 +140,7 @@ def contents(self): self.nsleep_default = self.Block(DigitalSourceConnected()) \ .out_with_default(self.ic.nsleep, self.nsleep, self.ic.v3p3.as_digital_source()) - def generate(self): + def generate(self) -> None: super().generate() pgnd_requested = self.get(self.pgnd_sense.requested()) gnd_voltage_source: Optional[VoltageSource] = None # only create one, if needed diff --git a/edg/parts/BoostConverter_AnalogDevices.py b/edg/parts/BoostConverter_AnalogDevices.py index 65add58b0..2ccda2dc7 100644 --- a/edg/parts/BoostConverter_AnalogDevices.py +++ b/edg/parts/BoostConverter_AnalogDevices.py @@ -45,7 +45,7 @@ class Ltc3429(VoltageRegulatorEnableWrapper, DiscreteBoostConverter): """Low-input-voltage boost converter (starts as low as 0.85V). Pin-compatible with the less-expensive UM3429S""" NMOS_CURRENT_LIMIT = 0.6 - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_frequency, (380, 630)*kHertz) diff --git a/edg/parts/BoostConverter_DiodesInc.py b/edg/parts/BoostConverter_DiodesInc.py index d85b270cb..1f663917d 100644 --- a/edg/parts/BoostConverter_DiodesInc.py +++ b/edg/parts/BoostConverter_DiodesInc.py @@ -3,7 +3,7 @@ class Ap3012_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr_in = self.Port(VoltageSink( voltage_limits=(2.6, 16)*Volt, @@ -19,7 +19,7 @@ def __init__(self): input_thresholds=(0.4, 1.5)*Volt )) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23-5', @@ -42,7 +42,7 @@ class Ap3012(VoltageRegulatorEnableWrapper, DiscreteBoostConverter): def _generator_inner_reset_pin(self) -> Port[DigitalLink]: return self.ic.nshdn - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_frequency, (1.1, 1.9)*MHertz) diff --git a/edg/parts/BoostConverter_TexasInstruments.py b/edg/parts/BoostConverter_TexasInstruments.py index 282f7ae56..77f8afb6b 100644 --- a/edg/parts/BoostConverter_TexasInstruments.py +++ b/edg/parts/BoostConverter_TexasInstruments.py @@ -3,7 +3,7 @@ class Tps61040_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() vfb = Range(1.208, 1.258) self.vfb = self.Parameter(RangeExpr(vfb*Volt)) @@ -44,7 +44,7 @@ class Tps61040(VoltageRegulatorEnableWrapper, DiscreteBoostConverter): def _generator_inner_reset_pin(self) -> Port[DigitalLink]: return self.ic.en - def contents(self): + def contents(self) -> None: super().contents() self.require(self.output_voltage >= self.pwr_in.link().voltage) # it's a boost converter @@ -158,7 +158,7 @@ def contents(self): class Lm2733_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr_in = self.Port(VoltageSink( voltage_limits=(2.7, 14)*Volt, @@ -174,7 +174,7 @@ def __init__(self): input_threshold_abs=(0.5, 1.5)*Volt )) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23-5', @@ -197,7 +197,7 @@ class Lm2733(VoltageRegulatorEnableWrapper, DiscreteBoostConverter): def _generator_inner_reset_pin(self) -> Port[DigitalLink]: return self.ic.nshdn - def contents(self): + def contents(self) -> None: import math super().contents() diff --git a/edg/parts/BoostConverter_Torex.py b/edg/parts/BoostConverter_Torex.py index 1e0a4d8f8..8b006010d 100644 --- a/edg/parts/BoostConverter_Torex.py +++ b/edg/parts/BoostConverter_Torex.py @@ -73,7 +73,7 @@ class Xc9142(Resettable, DiscreteBoostConverter, GeneratorBlock): """Low-input-voltage boost converter (starts as low as 0.9V) with fixed output. XC9142 has PWM/PFM functionality, compared to PWM only for XC9141. Semi pin compatible with XC9140, LTC3525, MAX1724.""" - def contents(self): + def contents(self) -> None: super().contents() self.generator_param(self.reset.is_connected()) @@ -94,7 +94,7 @@ def contents(self): self.connect(self.power_path.pwr_out, self.pwr_out) self.connect(self.power_path.switch, self.ic.sw) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): self.connect(self.reset, self.ic.ce) diff --git a/edg/parts/BootstrapVoltageAdder.py b/edg/parts/BootstrapVoltageAdder.py index 7cfe9f412..4001ccfa1 100644 --- a/edg/parts/BootstrapVoltageAdder.py +++ b/edg/parts/BootstrapVoltageAdder.py @@ -19,7 +19,7 @@ def __init__(self, frequency: RangeLike = 250*kHertz(tol=0), ripple_limit: Float self.frequency = self.ArgParameter(frequency) self.ripple_limit = self.ArgParameter(ripple_limit) - def contents(self): + def contents(self) -> None: super().contents() # TODO model diode forward voltage drops diff --git a/edg/parts/BuckBoostConverter_Custom.py b/edg/parts/BuckBoostConverter_Custom.py index eb1408f24..c3351e396 100644 --- a/edg/parts/BuckBoostConverter_Custom.py +++ b/edg/parts/BuckBoostConverter_Custom.py @@ -1,3 +1,5 @@ +from typing import Any + from ..abstract_parts import * @@ -33,11 +35,11 @@ class CustomSyncBuckBoostConverterPwm(DiscreteBoostConverter, Resettable): """Custom synchronous buck-boost with four PWMs for the switches. Because of the MOSFET body diode, will probably be fine-ish if the buck low-side FET and the boost high-side FET are not driven""" - def __init__(self, *args, + def __init__(self, *args: Any, frequency: RangeLike = (100, 1000)*kHertz, ripple_ratio: RangeLike = (0.2, 0.5), rds_on: RangeLike = (0, 1.0)*Ohm, - **kwargs): + **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.pwr_logic = self.Port(VoltageSink.empty()) @@ -48,7 +50,7 @@ def __init__(self, *args, self.ripple_ratio = self.ArgParameter(ripple_ratio) self.rds_on = self.ArgParameter(rds_on) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_frequency, self.frequency) diff --git a/edg/parts/BuckConverter_Ap3418.py b/edg/parts/BuckConverter_Ap3418.py index 03e8eabca..4a43ef7f6 100644 --- a/edg/parts/BuckConverter_Ap3418.py +++ b/edg/parts/BuckConverter_Ap3418.py @@ -3,7 +3,7 @@ class Ap3418_Device(InternalSubcircuit, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.sw = self.Port(VoltageSource()) # internal switch specs not defined, only bulk current limit defined self.pwr_in = self.Port(VoltageSink( @@ -41,7 +41,7 @@ class Ap3418(VoltageRegulatorEnableWrapper, DiscreteBuckConverter): def _generator_inner_reset_pin(self) -> Port[DigitalLink]: return self.ic.en - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_frequency, (1.12, 1.68)*MHertz) diff --git a/edg/parts/BuckConverter_Custom.py b/edg/parts/BuckConverter_Custom.py index 5bc333c8d..9788669d5 100644 --- a/edg/parts/BuckConverter_Custom.py +++ b/edg/parts/BuckConverter_Custom.py @@ -1,14 +1,16 @@ +from typing import Any + from ..abstract_parts import * class CustomSyncBuckConverterIndependent(DiscreteBoostConverter): """Custom synchronous buck with two PWM inputs for the high and low side gate drivers. Because of the MOSFET body diode, will probably be fine-ish if the low side FET is not driven.""" - def __init__(self, *args, + def __init__(self, *args: Any, frequency: RangeLike = (100, 1000)*kHertz, ripple_ratio: RangeLike = (0.2, 0.5), voltage_drop: RangeLike = (0, 1)*Volt, rds_on: RangeLike = (0, 1.0)*Ohm, - **kwargs): + **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.pwr_logic = self.Port(VoltageSink.empty()) @@ -20,7 +22,7 @@ def __init__(self, *args, self.voltage_drop = self.ArgParameter(voltage_drop) self.rds_on = self.ArgParameter(rds_on) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_frequency, self.frequency) diff --git a/edg/parts/BuckConverter_Mps.py b/edg/parts/BuckConverter_Mps.py index f0a2d4034..6e4d92410 100644 --- a/edg/parts/BuckConverter_Mps.py +++ b/edg/parts/BuckConverter_Mps.py @@ -128,7 +128,7 @@ def __init__(self, *args: Any, frequency: RangeLike = (900, 1280)*kHertz, self.frequency = self.ArgParameter(frequency) - def contents(self): + def contents(self) -> None: super().contents() # TODO only allow subset of frequencies, based on SW_FREQ table diff --git a/edg/parts/BuckConverter_TexasInstruments.py b/edg/parts/BuckConverter_TexasInstruments.py index 50de095c9..cfd86bda8 100644 --- a/edg/parts/BuckConverter_TexasInstruments.py +++ b/edg/parts/BuckConverter_TexasInstruments.py @@ -3,7 +3,7 @@ class Tps561201_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.sw = self.Port(VoltageSource()) # internal switch specs not defined, only bulk current limit defined self.pwr_in = self.Port(VoltageSink( @@ -42,7 +42,7 @@ class Tps561201(VoltageRegulatorEnableWrapper, DiscreteBuckConverter): def _generator_inner_reset_pin(self) -> Port[DigitalLink]: return self.ic.en - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_frequency, 580*kHertz(tol=0)) @@ -83,7 +83,7 @@ def contents(self): class Tps54202h_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.sw = self.Port(VoltageSource( current_limits=(0, 2)*Amp # most conservative figures, low-side limited. TODO: better ones? @@ -124,7 +124,7 @@ class Tps54202h(Resettable, DiscreteBuckConverter, GeneratorBlock): Note: TPS54202 has frequency spread-spectrum operation and internal pull-up on EN TPS54202H has no internal EN pull-up but a Zener diode clamp to limit voltage. """ - def contents(self): + def contents(self) -> None: super().contents() self.generator_param(self.reset.is_connected()) @@ -163,7 +163,7 @@ def contents(self): self.pwr_out) self.connect(self.power_path.switch, self.ic.sw) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): self.connect(self.reset, self.ic.en) diff --git a/edg/parts/Camera_Ov2640_Fpc24.py b/edg/parts/Camera_Ov2640_Fpc24.py index 121c3aede..c507bd17f 100644 --- a/edg/parts/Camera_Ov2640_Fpc24.py +++ b/edg/parts/Camera_Ov2640_Fpc24.py @@ -88,7 +88,7 @@ def __init__(self) -> None: super().__init__() self.generator_param(self.pwdn.is_connected(), self.reset.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.dovdd_cap = self.Block(DecouplingCapacitor(capacitance=0.1*uFarad(tol=0.2)))\ .connected(self.device.dgnd, self.device.dovdd) @@ -112,7 +112,7 @@ def contents(self): self.connect(self.dvp8.y6, self.device.y.request('8')) self.connect(self.dvp8.y7, self.device.y.request('9')) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.pwdn.is_connected()): self.connect(self.pwdn, self.device.pwdn) diff --git a/edg/parts/CanBlocks.py b/edg/parts/CanBlocks.py index da8151557..5c8dc57b7 100644 --- a/edg/parts/CanBlocks.py +++ b/edg/parts/CanBlocks.py @@ -8,7 +8,7 @@ def __init__(self) -> None: self.gnd.init_from(Ground()) self.can.init_from(CanDiffPort()) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( diff --git a/edg/parts/CanTransceiver_Iso1050.py b/edg/parts/CanTransceiver_Iso1050.py index 5f1d0626b..209d40565 100644 --- a/edg/parts/CanTransceiver_Iso1050.py +++ b/edg/parts/CanTransceiver_Iso1050.py @@ -2,7 +2,7 @@ class Iso1050dub_Device(InternalSubcircuit, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() # Table 6.3, recommended operating conditions self.vcc1 = self.Port(VoltageSink( @@ -28,7 +28,7 @@ def __init__(self): current_draw=(-4, 4) * mAmp, current_limits=(-70, 70) * mAmp ))) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOP-8_6.62x9.15mm_P2.54mm', @@ -49,7 +49,7 @@ def contents(self): class Iso1050dub(IsolatedCanTransceiver): - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Iso1050dub_Device()) self.connect(self.ic.controller, self.controller) diff --git a/edg/parts/CanTransceiver_Sn65hvd230.py b/edg/parts/CanTransceiver_Sn65hvd230.py index 697598aec..74453fdc2 100644 --- a/edg/parts/CanTransceiver_Sn65hvd230.py +++ b/edg/parts/CanTransceiver_Sn65hvd230.py @@ -3,7 +3,7 @@ class Sn65hvd230_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vcc = self.Port(VoltageSink( voltage_limits=(3, 3.6) * Volt, current_draw=(0.370, 17) * mAmp @@ -24,7 +24,7 @@ def __init__(self): current_draw=(-30, 30) * uAmp, current_limits=(-250, 250) * mAmp ))) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', @@ -46,7 +46,7 @@ def contents(self): class Sn65hvd230(CanTransceiver): - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Sn65hvd230_Device()) self.connect(self.ic.controller, self.controller) diff --git a/edg/parts/CeramicResonator_Cstne.py b/edg/parts/CeramicResonator_Cstne.py index 6267dac72..906cc1d47 100644 --- a/edg/parts/CeramicResonator_Cstne.py +++ b/edg/parts/CeramicResonator_Cstne.py @@ -3,12 +3,12 @@ class Cstne(CeramicResonator, GeneratorBlock, JlcPart, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.gnd.init_from(Ground()) self.generator_param(self.frequency) - def generate(self): + def generate(self) -> None: super().generate() parts = [ # tolerance is total stackup: initial temperature, aging (Range.from_tolerance(8e6, 0.0007 + 0.0011 + 0.0007), 'CSTNE8M00GH5L000R0', 'C882602', diff --git a/edg/parts/Connector_Banana.py b/edg/parts/Connector_Banana.py index 7b017bfc4..bb95317b6 100644 --- a/edg/parts/Connector_Banana.py +++ b/edg/parts/Connector_Banana.py @@ -7,7 +7,7 @@ class Ct3151(BananaSafetyJack, FootprintBlock): TODO: automatically support color code generation? """ - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'J', 'Connector:CalTest_CT3151', @@ -26,7 +26,7 @@ class Fcr7350(BananaSafetyJack, FootprintBlock): TODO: automatically support color code generation? """ - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'J', 'edg:CLIFF_FCR7350', diff --git a/edg/parts/Connector_Rf.py b/edg/parts/Connector_Rf.py index 093e52c8f..4af93c49b 100644 --- a/edg/parts/Connector_Rf.py +++ b/edg/parts/Connector_Rf.py @@ -4,7 +4,7 @@ class Bwipx_1_001e(RfConnectorTestPoint, UflConnector, JlcPart, FootprintBlock): """BAT WIRELESS IPEX connector""" - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'J', 'Connector_Coaxial:U.FL_Hirose_U.FL-R-SMT-1_Vertical', @@ -22,7 +22,7 @@ def contents(self): class Amphenol901143(SmaFConnector, FootprintBlock): """PTH right-angle SMA-F connector""" - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'J', 'Connector_Coaxial:SMA_Amphenol_901-143_Horizontal', diff --git a/edg/parts/Connectors.py b/edg/parts/Connectors.py index 58550795d..54797c944 100644 --- a/edg/parts/Connectors.py +++ b/edg/parts/Connectors.py @@ -1,3 +1,5 @@ +from typing import Any + from ..abstract_parts import * from .PassiveConnector_Header import JstShSmHorizontal @@ -16,7 +18,7 @@ def __init__(self, class Pj_102ah(PowerBarrelJack, FootprintBlock): """Barrel jack for 2.1mm ID and 5.5mm OD""" - def contents(self): + def contents(self) -> None: super().contents() self.require(self.pwr.voltage_out.within((0, 24)*Volt)) # datasheet ratings for connector self.require(self.pwr.current_limits.within((0, 2.5)*Volt)) @@ -34,7 +36,7 @@ def contents(self): class Pj_036ah(PowerBarrelJack, FootprintBlock): """SMT Barrel jack for 2.1mm ID and 5.5mm OD""" - def contents(self): + def contents(self) -> None: super().contents() self.require(self.pwr.voltage_out.within((0, 24)*Volt)) # datasheet ratings for connector self.require(self.pwr.current_limits.within((0, 5)*Volt)) @@ -59,8 +61,8 @@ class LipoConnector(Connector, Battery): Default pinning has ground being pin 1, and power being pin 2. Connector type not specified, up to the user through a refinement.""" - def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args, - actual_voltage: RangeLike = (2.5, 4.2)*Volt, **kwargs): + def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args: Any, + actual_voltage: RangeLike = (2.5, 4.2)*Volt, **kwargs: Any) -> None: from ..electronics_model.PassivePort import PassiveAdapterVoltageSink super().__init__(voltage, *args, **kwargs) self.chg = self.Port(VoltageSink.empty(), optional=True) # ideal port for charging @@ -81,7 +83,7 @@ def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args, class QwiicTarget(Connector): """A Qwiic (https://www.sparkfun.com/qwiic) connector to a I2C target. This would be on a board with a host controller.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(JstShSmHorizontal(4)) self.gnd = self.Export(self.conn.pins.request('1').adapt_to(Ground()), [Common]) diff --git a/edg/parts/CurrentSense_Ad8418.py b/edg/parts/CurrentSense_Ad8418.py index 287748425..02d027fce 100644 --- a/edg/parts/CurrentSense_Ad8418.py +++ b/edg/parts/CurrentSense_Ad8418.py @@ -33,7 +33,7 @@ def __init__(self, in_diff_range: RangeLike): impedance=2*Ohm(tol=0) # range not specified )) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', @@ -75,7 +75,8 @@ def __init__(self, in_diff_range: RangeLike): self.ref = self.Export(self.amp.vref1) # TODO optional for grounded unidirectional self.out = self.Export(self.amp.out) - def contents(self): + def contents(self) -> None: + super().contents() self.connect(self.ref, self.amp.vref2) self.vdd_cap = self.Block(DecouplingCapacitor( capacitance=0.1*uFarad(tol=0.2), diff --git a/edg/parts/DebugHeaders.py b/edg/parts/DebugHeaders.py index f30193f9c..c2733e280 100644 --- a/edg/parts/DebugHeaders.py +++ b/edg/parts/DebugHeaders.py @@ -5,7 +5,7 @@ class SwdCortexTargetHeader(SwdCortexTargetConnector, SwdCortexTargetConnectorReset, SwdCortexTargetConnectorSwo, SwdCortexTargetConnectorTdi): - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(PinHeader127DualShrouded(10)) self.connect(self.pwr, self.conn.pins.request('1').adapt_to(VoltageSink())) @@ -23,7 +23,7 @@ def contents(self): class SwdCortexTargetTagConnect(SwdCortexTargetConnector, SwdCortexTargetConnectorReset, SwdCortexTargetConnectorSwo): """OFFICIAL tag connect SWD header using the TC2030 series cables. https://www.tag-connect.com/wp-content/uploads/bsk-pdf-manager/TC2030-CTX_1.pdf""" - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(TagConnect(6)) self.connect(self.pwr, self.conn.pins.request('1').adapt_to(VoltageSink())) @@ -38,7 +38,7 @@ def contents(self): class SwdCortexTargetTc2050(SwdCortexTargetConnector, SwdCortexTargetConnectorReset, SwdCortexTargetConnectorSwo, SwdCortexTargetConnectorTdi): """UNOFFICIAL tag connect SWD header, maintaining physical pin compatibility with the 2x05 1.27mm header.""" - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(TagConnect(10)) self.connect(self.pwr, self.conn.pins.request('1').adapt_to(VoltageSink())) diff --git a/edg/parts/Distance_Vl53l0x.py b/edg/parts/Distance_Vl53l0x.py index d23df7135..f48df0ad2 100644 --- a/edg/parts/Distance_Vl53l0x.py +++ b/edg/parts/Distance_Vl53l0x.py @@ -28,7 +28,7 @@ def __init__(self) -> None: input_threshold_abs=(0.6, 1.12), )), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'OptoDevice:ST_VL53L0X', @@ -55,7 +55,7 @@ def contents(self): class Vl53l0x(DistanceSensor, Resettable, GeneratorBlock): """Time-of-flight laser ranging sensor, up to 2m""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Vl53l0x_Device()) self.gnd = self.Export(self.ic.vss, [Common]) @@ -67,7 +67,7 @@ def __init__(self): doc="Interrupt output for new data available") self.generator_param(self.reset.is_connected(), self.int.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): self.connect(self.reset, self.ic.xshut) @@ -89,7 +89,7 @@ class Vl53l0xConnector(Vl53l0x, WrapperFootprintBlock): This has an onboard 2.8v regulator, but thankfully the IO tolerance is not referenced to Vdd TODO: not completely correct that this should extend the application circuit""" - def generate(self): + def generate(self) -> None: super().generate() self.footprint( 'J', 'Connector_PinSocket_2.54mm:PinSocket_1x06_P2.54mm_Vertical', @@ -119,7 +119,7 @@ def __init__(self, count: IntLike, *, first_reset_fixed: BoolLike = False): self.first_reset_fixed = self.ArgParameter(first_reset_fixed) self.generator_param(self.count, self.first_reset_fixed) - def generate(self): + def generate(self) -> None: super().generate() self.elt = ElementDict[Vl53l0x]() for elt_i in range(self.get(self.count)): diff --git a/edg/parts/EInkBoostPowerPath.py b/edg/parts/EInkBoostPowerPath.py index d0b52b356..164c385f4 100644 --- a/edg/parts/EInkBoostPowerPath.py +++ b/edg/parts/EInkBoostPowerPath.py @@ -25,7 +25,7 @@ def __init__(self, voltage_out: RangeLike, current: RangeLike, inductance: Range self.resistance = self.ArgParameter(resistance) self.diode_voltage_drop = self.ArgParameter(diode_voltage_drop) - def contents(self): + def contents(self) -> None: super().contents() self.fet = self.Block(Fet.NFet( diff --git a/edg/parts/EInk_Er_Epd027_2.py b/edg/parts/EInk_Er_Epd027_2.py index 916e9d634..dfe19222c 100644 --- a/edg/parts/EInk_Er_Epd027_2.py +++ b/edg/parts/EInk_Er_Epd027_2.py @@ -95,7 +95,7 @@ def __init__(self) -> None: self.generator_param(self.dc.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.lcd = self.Block(Er_Epd027_2_Outline()) # for device outline @@ -126,7 +126,7 @@ def contents(self): self.connect(self.boost.pos_out, self.device.vgh) self.connect(self.boost.neg_out, self.device.vgl) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.dc.is_connected()): # 4-line serial, BS low self.connect(self.gnd.as_digital_source(), self.device.bs) diff --git a/edg/parts/EInk_WaveshareDriver.py b/edg/parts/EInk_WaveshareDriver.py index 436056bd9..14593743b 100644 --- a/edg/parts/EInk_WaveshareDriver.py +++ b/edg/parts/EInk_WaveshareDriver.py @@ -91,7 +91,7 @@ def __init__(self) -> None: self.generator_param(self.dc.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.vdd_cap = self.Block(DecouplingCapacitor(capacitance=1*uFarad(tol=0.2)))\ @@ -125,7 +125,7 @@ def contents(self): self.connect(self.boost.pos_out, self.device.prevgh) self.connect(self.boost.neg_out, self.device.prevgl) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.dc.is_connected()): # 4-line serial, BS low self.connect(self.gnd.as_digital_source(), self.device.bs) diff --git a/edg/parts/EnvironmentalSensor_Bme680.py b/edg/parts/EnvironmentalSensor_Bme680.py index e183418df..422960cb4 100644 --- a/edg/parts/EnvironmentalSensor_Bme680.py +++ b/edg/parts/EnvironmentalSensor_Bme680.py @@ -44,7 +44,7 @@ def contents(self) -> None: class Bme680(TemperatureSensor, HumiditySensor, PressureSensor, GasSensor, DefaultExportBlock): """Gas (indoor air quality), pressure, temperature, and humidity sensor. Humidity accuracy /-3% RH, pressure noise 0.12 Pa, temperature accuracy +/-0.5 C @ 25C""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Bme680_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) @@ -52,7 +52,7 @@ def __init__(self): self.pwr_io = self.Export(self.ic.vddio, default=self.pwr, doc="IO supply voltage") self.i2c = self.Export(self.ic.i2c, [InOut]) - def contents(self): + def contents(self) -> None: super().contents() # capacitors from shuttle board example self.vdd_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) self.vddio_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vddio) diff --git a/edg/parts/EnvironmentalSensor_Sensirion.py b/edg/parts/EnvironmentalSensor_Sensirion.py index ae8c39d94..d04e6e3fd 100644 --- a/edg/parts/EnvironmentalSensor_Sensirion.py +++ b/edg/parts/EnvironmentalSensor_Sensirion.py @@ -36,13 +36,13 @@ def contents(self) -> None: class Shtc3(TemperatureSensor, HumiditySensor, Block): """Humidity and temperature sensor with +/-2% RH and +/-0.2C""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Shtc3_Device()) self.gnd = self.Export(self.ic.vss, [Common]) self.pwr = self.Export(self.ic.vdd, [Power]) self.i2c = self.Export(self.ic.i2c, [InOut]) - def contents(self): + def contents(self) -> None: super().contents() # capacitors from datasheet self.vdd_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) diff --git a/edg/parts/EnvironmentalSensor_Ti.py b/edg/parts/EnvironmentalSensor_Ti.py index ac0160e64..831ee93d2 100644 --- a/edg/parts/EnvironmentalSensor_Ti.py +++ b/edg/parts/EnvironmentalSensor_Ti.py @@ -38,14 +38,14 @@ def contents(self) -> None: class Hdc1080(TemperatureSensor, HumiditySensor, Block): """Temperature and humidity sensor with +/- 0.2C and +/- 2% RH typical accuracy""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Hdc1080_Device()) self.pwr = self.Export(self.ic.vdd, [Power]) self.gnd = self.Export(self.ic.gnd, [Common]) self.i2c = self.Export(self.ic.i2c, [InOut]) - def contents(self): + def contents(self) -> None: super().contents() # X7R capacitor recommended self.vdd_cap = self.Block(DecouplingCapacitor(0.1*uFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) @@ -105,6 +105,6 @@ def __init__(self, addr_lsb: IntLike = 0): self.i2c = self.Export(self.ic.i2c, [InOut]) self.alert = self.Export(self.ic.alert, optional=True, doc="Overtemperature SMBus alert") - def contents(self): + def contents(self) -> None: super().contents() self.vdd_cap = self.Block(DecouplingCapacitor(0.01*uFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) diff --git a/edg/parts/FanConnector.py b/edg/parts/FanConnector.py index e85bfffb9..70fdf91b7 100644 --- a/edg/parts/FanConnector.py +++ b/edg/parts/FanConnector.py @@ -4,7 +4,7 @@ @abstract_block_default(lambda: CpuFan3Pin) class CpuFanConnector(Connector, Block): """Abstract block for a 3-pin CPU fan connector.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) self.pwr = self.Port(VoltageSink( @@ -17,7 +17,7 @@ def __init__(self): @abstract_block_default(lambda: CpuFan4Pin) class CpuFanPwmControl(BlockInterfaceMixin[CpuFanConnector]): """Mixin that adds an PWM control pin (open-collector input) to a CpuFanConnector.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.control = self.Port(DigitalBidir( voltage_limits=(0, 5.25)*Volt, @@ -29,7 +29,7 @@ def __init__(self): class CpuFan3Pin(CpuFanConnector, FootprintBlock): """3-pin fan controller""" - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'J', 'Connector:FanPinHeader_1x03_P2.54mm_Vertical', @@ -44,7 +44,7 @@ def contents(self): class CpuFan4Pin(CpuFanConnector, CpuFanPwmControl, FootprintBlock): """3-pin fan controller""" - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'J', 'Connector:FanPinHeader_1x04_P2.54mm_Vertical', diff --git a/edg/parts/Fpga_Ice40up.py b/edg/parts/Fpga_Ice40up.py index f036d87d4..21ce08e19 100644 --- a/edg/parts/Fpga_Ice40up.py +++ b/edg/parts/Fpga_Ice40up.py @@ -7,7 +7,7 @@ class Ice40TargetHeader(ProgrammingConnector, FootprintBlock): """Custom programming header for iCE40 loosely based on the SWD pinning""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink.empty(), [Power]) # in practice this can power the target self.gnd = self.Port(Ground.empty(), [Common]) # TODO pin at 0v @@ -15,7 +15,7 @@ def __init__(self): self.cs = self.Port(DigitalSource.empty()) self.reset = self.Port(DigitalSource.empty()) - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(PinHeader127DualShrouded(10)) self.connect(self.pwr, self.conn.pins.request('1').adapt_to(VoltageSink())) @@ -41,7 +41,7 @@ class Ice40up_Device(BaseIoControllerPinmapGenerator, InternalSubcircuit, Genera BITSTREAM_BITS: int = 0 @staticmethod - def make_dio_model(gnd: Ground, vccio: VoltageSink): + def make_dio_model(gnd: Ground, vccio: VoltageSink) -> DigitalBidir: return DigitalBidir.from_supply( gnd, vccio, voltage_limit_tolerance=(-0.3, 0.2) * Volt, # table 4.13 @@ -50,7 +50,7 @@ def make_dio_model(gnd: Ground, vccio: VoltageSink): pullup_capable=True, pulldown_capable=False, ) - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.gnd = self.Port(Ground(), [Common]) @@ -253,11 +253,11 @@ class Ice40up(Fpga, IoController): """ DEVICE: Type[Ice40up_Device] = Ice40up_Device - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.cdone = self.Port(DigitalSource.empty(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() # schematics don't seem to be available for the official reference designs, diff --git a/edg/parts/Fuseholder_Nano2.py b/edg/parts/Fuseholder_Nano2.py index 5a94b4eee..b1c762c8d 100644 --- a/edg/parts/Fuseholder_Nano2.py +++ b/edg/parts/Fuseholder_Nano2.py @@ -6,7 +6,7 @@ class Nano2Fuseholder(Fuse, JlcPart, FootprintBlock): """Littelfuse Nano2 / 154 series fuseholder. Generic versions exist as 1808 fuses. TODO: generate fuse part numbers from a table, currently this only generates the holder""" - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'F', 'Fuse:Fuseholder_Littelfuse_Nano2_154x', diff --git a/edg/parts/GateDriver_Ir2301.py b/edg/parts/GateDriver_Ir2301.py index 45d5606db..1c85e0745 100644 --- a/edg/parts/GateDriver_Ir2301.py +++ b/edg/parts/GateDriver_Ir2301.py @@ -3,7 +3,7 @@ class Ir2301_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.com = self.Port(Ground(), [Common]) self.vcc = self.Port(VoltageSink.from_gnd( @@ -41,7 +41,7 @@ def __init__(self): )) self.assign(self.vb.current_draw, (50, 190)*uAmp + self.ho.link().current_drawn) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', { @@ -64,7 +64,7 @@ def contents(self): class Ir2301(HalfBridgeDriver, HalfBridgeDriverIndependent): """IR2301 half-bridge driver supporting 600V offset, 5-20v input, external boot diode, no shoot through protect, no deadtime.""" - def contents(self): + def contents(self) -> None: super().contents() self.require(~self.has_boot_diode, 'TODO: boot diode generator') diff --git a/edg/parts/GateDriver_Ncp3420.py b/edg/parts/GateDriver_Ncp3420.py index 9b8b46bc0..dbb7ca827 100644 --- a/edg/parts/GateDriver_Ncp3420.py +++ b/edg/parts/GateDriver_Ncp3420.py @@ -1,9 +1,11 @@ +from typing import Any + from ..abstract_parts import * from .JlcPart import JlcPart class Ncp3420_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pgnd = self.Port(Ground(), [Common]) self.vcc = self.Port(VoltageSink.from_gnd( @@ -41,7 +43,8 @@ def __init__(self): self.assign(self.vcc.current_draw, (0.7, 5.0)*mAmp + self.drvl.link().current_drawn + self.drvh.link().current_drawn) # only system supply given - def contents(self): + def contents(self) -> None: + super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', { @@ -63,11 +66,11 @@ def contents(self): class Ncp3420(HalfBridgeDriver, HalfBridgeDriverPwm, Resettable, GeneratorBlock): """Half-bridge driver supporting 35V offset, 4.6-13.2v input, external boot diode, auto-deadtime.""" - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.has_boot_diode, self.high_pwr.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Ncp3420_Device()) @@ -83,7 +86,7 @@ def contents(self): # serves as both boot cap and decoupling cap self.high_cap = self.Block(DecouplingCapacitor(0.1*uFarad(tol=0.2))).connected(self.high_gnd, self.ic.bst) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.high_pwr.is_connected()): diff --git a/edg/parts/GateDriver_Ucc27282.py b/edg/parts/GateDriver_Ucc27282.py index b40f54ea2..93d38a8c5 100644 --- a/edg/parts/GateDriver_Ucc27282.py +++ b/edg/parts/GateDriver_Ucc27282.py @@ -3,7 +3,7 @@ class Ucc27282_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vss = self.Port(Ground(), [Common]) self.vdd = self.Port(VoltageSink.from_gnd( @@ -41,7 +41,8 @@ def __init__(self): self.assign(self.vdd.current_draw, (0.3, 4.5)*mAmp + (0.2, 4)*mAmp + self.lo.link().current_drawn + self.ho.link().current_drawn) - def contents(self): + def contents(self) -> None: + super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', { @@ -64,7 +65,7 @@ def contents(self): class Ucc27282(HalfBridgeDriver, HalfBridgeDriverIndependent): """UCC27282 half-bridge driver supporting 100V offset, 5.5-16v input, internal boot diode, shoot through protect, no deadtime.""" - def contents(self): + def contents(self) -> None: super().contents() self.require(self.has_boot_diode) diff --git a/edg/parts/Imu_Lsm6ds3trc.py b/edg/parts/Imu_Lsm6ds3trc.py index a0bf84e08..7f5971b3a 100644 --- a/edg/parts/Imu_Lsm6ds3trc.py +++ b/edg/parts/Imu_Lsm6ds3trc.py @@ -56,7 +56,7 @@ def contents(self) -> None: class Lsm6ds3trc(Accelerometer, Gyroscope, DefaultExportBlock): """Integrated 3d accelerometer (ranging over +/- 2/4/8/16 g) and 3d gyroscope (ranging over +/- 125/250/500/1000/2000 dps).""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Lsm6ds3trc_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) @@ -67,7 +67,7 @@ def __init__(self): self.int1 = self.Export(self.ic.int1, optional=True, doc="Programmable interrupt") self.int2 = self.Export(self.ic.int2, optional=True, doc="Programmable interrupt") - def contents(self): + def contents(self) -> None: super().contents() self.vdd_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) self.vddio_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vddio) diff --git a/edg/parts/Ina219.py b/edg/parts/Ina219.py index cb452715d..0d3e850fc 100644 --- a/edg/parts/Ina219.py +++ b/edg/parts/Ina219.py @@ -29,7 +29,7 @@ def __init__(self, addr_lsb: IntLike): self.in_pos = self.Port(AnalogSink(voltage_limits=(-0.3, 26) * Volt)) self.in_neg = self.Port(AnalogSink(voltage_limits=(-0.3, 26) * Volt)) - def generate(self): + def generate(self) -> None: super().generate() sa1_pin, sa0_pin = { @@ -89,7 +89,7 @@ def __init__(self, shunt_resistor: RangeLike = 2.0 * mOhm(tol=0.05), *, addr_lsb self.sense_pos = self.Export(self.Rs.pwr_in) self.sense_neg = self.Export(self.Rs.pwr_out) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.Rs.sense_in, self.ic.in_pos) self.connect(self.Rs.sense_out, self.ic.in_neg) diff --git a/edg/parts/Inamp_Ina826.py b/edg/parts/Inamp_Ina826.py index a557c23ff..92040be1e 100644 --- a/edg/parts/Inamp_Ina826.py +++ b/edg/parts/Inamp_Ina826.py @@ -5,7 +5,7 @@ class Ina826_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vsp = self.Port(VoltageSink( voltage_limits=(3, 36)*Volt, current_draw=(200, 300)*uAmp # over temperature range, typ to max @@ -35,7 +35,7 @@ def __init__(self): self.rg2 = self.Port(Passive()) self.rg3 = self.Port(Passive()) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', @@ -89,7 +89,7 @@ def __init__(self, ratio: RangeLike = 10*Ratio(tol=0.05)): self.actual_ratio = self.Parameter(RangeExpr()) self.generator_param(self.ratio) - def generate(self): + def generate(self) -> None: super().generate() # Datasheet section 8.1: decoupling caps placed as close to device pins as possible diff --git a/edg/parts/IoExpander_Pca9554.py b/edg/parts/IoExpander_Pca9554.py index 3a6414f88..60a5dd039 100644 --- a/edg/parts/IoExpander_Pca9554.py +++ b/edg/parts/IoExpander_Pca9554.py @@ -1,13 +1,13 @@ from itertools import chain -from typing import Dict, List +from typing import Dict, List, Any from ..abstract_parts import * from .JlcPart import JlcPart class Pca9554_Device(PinMappable, InternalSubcircuit, FootprintBlock, JlcPart, GeneratorBlock): - def __init__(self, addr_lsb: IntLike, **kwags) -> None: - super().__init__(**kwags) + def __init__(self, addr_lsb: IntLike, **kwargs: Any) -> None: + super().__init__(**kwargs) self.gnd = self.Port(Ground()) self.vdd = self.Port(VoltageSink( voltage_limits=(2.3, 5.5)*Volt, diff --git a/edg/parts/IoExpander_Pcf8574.py b/edg/parts/IoExpander_Pcf8574.py index a75a0c9d5..8aaf2f167 100644 --- a/edg/parts/IoExpander_Pcf8574.py +++ b/edg/parts/IoExpander_Pcf8574.py @@ -1,13 +1,13 @@ from itertools import chain -from typing import Dict +from typing import Dict, Any from ..abstract_parts import * from .JlcPart import JlcPart class Pcf8574_Device(PinMappable, InternalSubcircuit, FootprintBlock, JlcPart, GeneratorBlock): - def __init__(self, addr_lsb: IntLike, **kwags) -> None: - super().__init__(**kwags) + def __init__(self, addr_lsb: IntLike, **kwargs: Any) -> None: + super().__init__(**kwargs) self.gnd = self.Port(Ground()) self.vdd = self.Port(VoltageSink( # same between TI and NXP versions voltage_limits=(2.5, 6)*Volt, diff --git a/edg/parts/Isolator_Cbmud1200.py b/edg/parts/Isolator_Cbmud1200.py index bba77217f..eadeb119e 100644 --- a/edg/parts/Isolator_Cbmud1200.py +++ b/edg/parts/Isolator_Cbmud1200.py @@ -5,7 +5,7 @@ class Cbmud1200l_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd1 = self.Port(Ground()) self.vdd1 = self.Port(VoltageSink.from_gnd( @@ -34,7 +34,7 @@ def __init__(self): self.voa = self.Port(out_model) self.vob = self.Port(out_model) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', { @@ -55,10 +55,10 @@ def contents(self): class Cbmud1200l(DigitalIsolator, GeneratorBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() - def generate(self): + def generate(self) -> None: super().generate() assert not self.get(self.in_b.requested()) and not self.get(self.out_a.requested()), f"device has no b->a channels" diff --git a/edg/parts/Jacdac.py b/edg/parts/Jacdac.py index d52f061b5..500ee59bc 100644 --- a/edg/parts/Jacdac.py +++ b/edg/parts/Jacdac.py @@ -80,13 +80,13 @@ def __init__(self, is_power_provider: BoolLike = False) -> None: self.generator_param(self.jd_pwr_src.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.require(self.jd_pwr_src.is_connected() | self.jd_pwr_sink.is_connected()) self.require(self.jd_pwr_src.is_connected().implies(~self.jd_pwr_sink.is_connected())) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.jd_pwr_src.is_connected()): @@ -106,7 +106,7 @@ def generate(self): class Rclamp0521p(TvsDiode, FootprintBlock, JlcPart): """RCLAMP0521P-N TVS diode in 0402 package, recommended in the Jacdac DDK.""" - def contents(self): + def contents(self) -> None: super().contents() self.require(self.working_voltage.within(self.actual_working_voltage)) self.require(self.actual_capacitance.within(self.capacitance)) @@ -148,7 +148,7 @@ def __init__(self, is_power_provider: BoolLike = False) -> None: self.generator_param(self.jd_pwr_src.is_connected(), self.jd_pwr_sink.is_connected()) - def generate(self): + def generate(self) -> None: super().contents() with self.implicit_connect( @@ -175,7 +175,7 @@ def generate(self): class JacdacDataInterface(JacdacSubcircuit, Block): """Interface from a Jacdac data bus to a device, including protection and EMI filtering. Does NOT include per-port circuitry like ESD diodes and status LEDs.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground.empty(), [Common]) self.pwr = self.Port(VoltageSink.empty(), [Power]) @@ -183,7 +183,7 @@ def __init__(self): self.signal = self.Port(DigitalBidir.empty(), [Input]) self.jd_data = self.Port(JacdacDataPort.empty(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.ferrite = self.Block(FerriteBead(hf_impedance=(1, float('inf'))*kOhm)) signal_level = self.signal.link().voltage @@ -210,11 +210,12 @@ def contents(self): class JacdacMountingData1(JacdacSubcircuit, FootprintBlock): """Jacdac mounting hole for data, with a passive-typed port so it doesn't count as a connection for validation purposes.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.jd_data = self.Port(JacdacPassivePort()) - def contents(self): + def contents(self) -> None: + super().contents() self.footprint( 'MH', 'Jacdac:jacdac_hole_DATA_notched_MH1', { @@ -224,11 +225,12 @@ def contents(self): class JacdacMountingGnd2(JacdacSubcircuit, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground()) - def contents(self): + def contents(self) -> None: + super().contents() self.footprint( 'MH', 'Jacdac:jacdac_hole_GND_MH2', { @@ -238,11 +240,12 @@ def contents(self): class JacdacMountingGnd4(JacdacSubcircuit, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground()) - def contents(self): + def contents(self) -> None: + super().contents() self.footprint( 'MH', 'Jacdac:jacdac_hole_GND_MH4', { @@ -252,11 +255,12 @@ def contents(self): class JacdacMountingPwr3(JacdacSubcircuit, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.jd_pwr = self.Port(VoltageSink()) - def contents(self): + def contents(self) -> None: + super().contents() self.footprint( 'MH', 'Jacdac:jacdac_hole_PWR_MH3', { @@ -271,7 +275,7 @@ class JacdacDeviceTop(DesignTop): Recommend connecting to the nets, instead of connecting directly to the created Blocks and their Ports.""" - def contents(self): + def contents(self) -> None: super().contents() self.edge = self.Block(JacdacEdgeConnector()) self.jd_mh1 = self.Block(JacdacMountingData1()) diff --git a/edg/parts/JlcBlackbox.py b/edg/parts/JlcBlackbox.py index c0759da68..3ea875a0d 100644 --- a/edg/parts/JlcBlackbox.py +++ b/edg/parts/JlcBlackbox.py @@ -38,7 +38,7 @@ def __init__(self, kicad_pins: ArrayStringLike, kicad_refdes_prefix: StringLike, self.kicad_pins = self.ArgParameter(kicad_pins) self.generator_param(self.kicad_pins) - def generate(self): + def generate(self) -> None: super().generate() mapping = {pin_name: self.ports.append_elt(Passive(), pin_name) for pin_name in self.get(self.kicad_pins)} diff --git a/edg/parts/JlcCapacitor.py b/edg/parts/JlcCapacitor.py index 83b35fea8..c700a06b7 100644 --- a/edg/parts/JlcCapacitor.py +++ b/edg/parts/JlcCapacitor.py @@ -32,7 +32,7 @@ class JlcCapacitor(JlcTableSelector, PartsTableSelectorFootprint, TableDeratingC 'Capacitor_SMD:C_1812_4532Metric': 0.04, # arbitrary, copy from 1206 } - def __init__(self, *args, capacitance_minimum_size: BoolLike = True, **kwargs): + def __init__(self, *args: Any, capacitance_minimum_size: BoolLike = True, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.capacitance_minimum_size = self.ArgParameter(capacitance_minimum_size) self.generator_param(self.capacitance_minimum_size) @@ -132,7 +132,7 @@ class JlcDummyCapacitor(JlcPart, DummyCapacitorFootprint): """ def __init__(self, set_lcsc_part: StringLike = "", set_basic_part: BoolLike = False, footprint: StringLike = "", manufacturer: StringLike = "", - part_number: StringLike = "", value: StringLike = "", *args, **kwargs) -> None: + part_number: StringLike = "", value: StringLike = "", *args: Any, **kwargs: Any) -> None: super().__init__(footprint=footprint, manufacturer=manufacturer, part_number=part_number, value=value, *args, **kwargs) diff --git a/edg/parts/JlcElectrolyticCapacitor.py b/edg/parts/JlcElectrolyticCapacitor.py index 17b08c810..0045f9957 100644 --- a/edg/parts/JlcElectrolyticCapacitor.py +++ b/edg/parts/JlcElectrolyticCapacitor.py @@ -19,7 +19,7 @@ class JlcAluminumCapacitor(PartsTableSelectorFootprint, JlcTableSelector, TableC }), ] - def __init__(self, *args, capacitance_minimum_size: BoolLike = True, **kwargs): + def __init__(self, *args: Any, capacitance_minimum_size: BoolLike = True, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.capacitance_minimum_size = self.ArgParameter(capacitance_minimum_size) self.generator_param(self.capacitance_minimum_size) diff --git a/edg/parts/JlcFet.py b/edg/parts/JlcFet.py index 7ddff80e3..dd2c7b8f9 100644 --- a/edg/parts/JlcFet.py +++ b/edg/parts/JlcFet.py @@ -10,7 +10,7 @@ class FetFallbackGateCharge(PartsTableSelector, BaseTableFet): """A TableFet that allows a fallback gate charge if not specified in the table. Unspecified entries must be Range.all(), which will be substituted with the fallback value in per-Block post-processing.""" - def __init__(self, *args, fallback_gate_charge: RangeLike = Range.from_tolerance(3000e-9, 0), **kwargs): + def __init__(self, *args: Any, fallback_gate_charge: RangeLike = Range.from_tolerance(3000e-9, 0), **kwargs: Any) -> None: super().__init__(*args, **kwargs) # allow the user to specify a gate charge self.fallback_gate_charge = self.ArgParameter(fallback_gate_charge) diff --git a/edg/parts/JlcInductor.py b/edg/parts/JlcInductor.py index ab8125b02..e1a711465 100644 --- a/edg/parts/JlcInductor.py +++ b/edg/parts/JlcInductor.py @@ -78,7 +78,7 @@ class JlcInductor(PartsTableSelectorFootprint, JlcTableSelector, TableInductor): }), ] - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) # because the table does not have frequency specs, the table filter can't enforce frequency ratings # so the user must add the actual frequency rating in refinements diff --git a/edg/parts/JlcOscillator.py b/edg/parts/JlcOscillator.py index 2c8956242..8cdb5d6da 100644 --- a/edg/parts/JlcOscillator.py +++ b/edg/parts/JlcOscillator.py @@ -28,7 +28,7 @@ def __init__(self, in_kicad_part: StringLike, in_kicad_value: StringLike, in_kic class Sg8101_Base_Device(JlcOscillator_Device, JlcPart, FootprintBlock): FOOTPRINT: str - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.gnd.init_from(Ground()) self.vcc.init_from(VoltageSink(voltage_limits=(1.62, 3.62)*Volt, diff --git a/edg/parts/JlcPart.py b/edg/parts/JlcPart.py index 879fdfc2c..54d1a6df9 100644 --- a/edg/parts/JlcPart.py +++ b/edg/parts/JlcPart.py @@ -9,7 +9,7 @@ class JlcPart(Block): """Provides additional data fields for JLCPCB parts for their SMT service. By default, this does not check for basic parts, but that can be changed in refinements. """ - def __init__(self, *args, require_basic_part: BoolLike = False, **kwargs): + def __init__(self, *args: Any, require_basic_part: BoolLike = False, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.lcsc_part = self.Parameter(StringExpr()) self.actual_basic_part = self.Parameter(BoolExpr()) @@ -63,7 +63,7 @@ def _parse_jlcpcb_common(cls, row: PartsTableRow) -> Dict[PartsTableColumn, Any] } @staticmethod - def parse(description: str, regex_dictionary: Dict[str, re.Pattern]): + def parse(description: str, regex_dictionary: Dict[str, re.Pattern]) -> Dict[str, str]: extraction_table = {} for key, pattern in regex_dictionary.items(): diff --git a/edg/parts/Joystick_Xbox.py b/edg/parts/Joystick_Xbox.py index eb623cf20..149913259 100644 --- a/edg/parts/Joystick_Xbox.py +++ b/edg/parts/Joystick_Xbox.py @@ -4,7 +4,7 @@ class XboxElite2Joystick(FootprintBlock, HumanInterface): """Joystick assembly (X/Y analog axes + switch) from the XBox Elite 2 controller. Proper polarity for compatibility with hall effect sensors.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) self.pwr = self.Port(VoltageSink( @@ -15,7 +15,7 @@ def __init__(self): self.ax1 = self.Port(AnalogSource.from_supply(self.gnd, self.pwr)) self.ax2 = self.Port(AnalogSource.from_supply(self.gnd, self.pwr)) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( diff --git a/edg/parts/Jumpers.py b/edg/parts/Jumpers.py index 54a067157..fc346c73e 100644 --- a/edg/parts/Jumpers.py +++ b/edg/parts/Jumpers.py @@ -2,7 +2,7 @@ class SolderJumperTriangular(Jumper, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'JP', 'Jumper:SolderJumper-2_P1.3mm_Open_TrianglePad1.0x1.5mm', diff --git a/edg/parts/Labels.py b/edg/parts/Labels.py index 63f8a834a..bfb93c35d 100644 --- a/edg/parts/Labels.py +++ b/edg/parts/Labels.py @@ -4,7 +4,7 @@ @deprecated("non-circuit footprints should be added in layout as non-schematic items") class LeadFreeIndicator(Label, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'edg:Indicator_LeadFree', @@ -15,7 +15,7 @@ def contents(self): @deprecated("non-circuit footprints should be added in layout as non-schematic items") class IdDots4(Label, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'edg:Indicator_IdDots_4', @@ -26,7 +26,7 @@ def contents(self): @deprecated("non-circuit footprints should be added in layout as non-schematic items") class DuckLogo(Label, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'edg:Symbol_Duckling', @@ -37,7 +37,7 @@ def contents(self): @deprecated("non-circuit footprints should be added in layout as non-schematic items") class LemurLogo(Label, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'edg:Symbol_LemurSmall', diff --git a/edg/parts/Lcd_Ch280qv10_Ct.py b/edg/parts/Lcd_Ch280qv10_Ct.py index 239af4d06..f8ec11018 100644 --- a/edg/parts/Lcd_Ch280qv10_Ct.py +++ b/edg/parts/Lcd_Ch280qv10_Ct.py @@ -107,7 +107,7 @@ def __init__(self) -> None: self.ctp_i2c = self.Export(self.device.ctp_i2c, optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.pwr, self.device.vci) self.connect(self.reset, self.device.reset, self.device.ctp_res) # combined LCD and CTP reset diff --git a/edg/parts/Lcd_Er_Tft1_28_3.py b/edg/parts/Lcd_Er_Tft1_28_3.py index 0b8c5dee6..63f530b96 100644 --- a/edg/parts/Lcd_Er_Tft1_28_3.py +++ b/edg/parts/Lcd_Er_Tft1_28_3.py @@ -83,7 +83,7 @@ def __init__(self) -> None: self.ctp_rst = self.Export(self.ic.ctp_rst, optional=True, doc='Touch panel interface') self.ctp_int = self.Export(self.ic.ctp_int, optional=True, doc='Touch panel interface') - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.reset, self.ic.rst) self.require(self.reset.is_connected()) diff --git a/edg/parts/Lcd_Qt096t_if09.py b/edg/parts/Lcd_Qt096t_if09.py index 4c0cde44b..b87bb4855 100644 --- a/edg/parts/Lcd_Qt096t_if09.py +++ b/edg/parts/Lcd_Qt096t_if09.py @@ -49,7 +49,7 @@ def __init__(self) -> None: self.spi = self.Export(self.device.spi) self.led = self.Port(DigitalSink.empty()) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.reset, self.device.reset) self.require(self.reset.is_connected()) diff --git a/edg/parts/LedDriver_Al8861.py b/edg/parts/LedDriver_Al8861.py index 8a3e5af59..f2b074576 100644 --- a/edg/parts/LedDriver_Al8861.py +++ b/edg/parts/LedDriver_Al8861.py @@ -21,7 +21,8 @@ def __init__(self, peak_output_current: FloatLike): self.peak_output_current = self.ArgParameter(peak_output_current) - def contents(self): + def contents(self) -> None: + super().contents() self.require(self.peak_output_current < 2*Amp) self.footprint( 'U', 'Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm_ThermalVias', @@ -59,8 +60,8 @@ def __init__(self, diode_voltage_drop: RangeLike = Range.all()): self.actual_ripple = self.Parameter(RangeExpr()) - def generate(self): - super().contents() + def generate(self) -> None: + super().generate() # TODO replace with BuckConverterPowerPath, though the 33uH minimum inductance is very high self.require(self.max_current.within((0, 1.5)*Amp)) # for MSOP and SOT89 packages diff --git a/edg/parts/LedDriver_Tps92200.py b/edg/parts/LedDriver_Tps92200.py index f5001977e..ee46a31bf 100644 --- a/edg/parts/LedDriver_Tps92200.py +++ b/edg/parts/LedDriver_Tps92200.py @@ -25,7 +25,8 @@ def __init__(self, peak_output_current: FloatLike): self.sw = self.Port(VoltageSource()) self.boot = self.Port(Passive()) - def contents(self): + def contents(self) -> None: + super().contents() self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23-6', { @@ -61,8 +62,8 @@ def __init__(self, led_voltage: RangeLike = (1, 4)*Volt, *, self.input_ripple_limit = self.ArgParameter(input_ripple_limit) self.output_ripple_limit = self.ArgParameter(output_ripple_limit) - def generate(self): - super().contents() + def generate(self) -> None: + super().generate() with self.implicit_connect( ImplicitConnect(self.pwr, [Power]), diff --git a/edg/parts/LedMatrix.py b/edg/parts/LedMatrix.py index 0dfef3173..d4dc106db 100644 --- a/edg/parts/LedMatrix.py +++ b/edg/parts/LedMatrix.py @@ -178,7 +178,7 @@ def __init__(self, nrows: IntLike, ncols: IntLike, self.ncols = self.ArgParameter(ncols) self.generator_param(self.nrows, self.ncols) - def generate(self): + def generate(self) -> None: super().generate() nrows = self.get(self.nrows) ncols = self.get(self.ncols) @@ -190,7 +190,7 @@ def generate(self): # internally, this uses passive ports on all the components, and only casts to a DigitalSink at the end # which is necessary to account for that not all LEDs can be simultaneously on passive_ios: Dict[int, Passive] = {} # keeps the passive-side port for each boundary IO - def connect_passive_io(index: int, io: Passive): + def connect_passive_io(index: int, io: Passive) -> None: # connects a Passive-typed IO to the index, handling the first and subsequent case if index in passive_ios: self.connect(passive_ios[index], io) # subsequent case, actually do the connection diff --git a/edg/parts/Leds.py b/edg/parts/Leds.py index 82120f561..f29b2af49 100644 --- a/edg/parts/Leds.py +++ b/edg/parts/Leds.py @@ -3,7 +3,7 @@ class SmtLed(Led, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'D', 'LED_SMD:LED_0603_1608Metric', @@ -16,7 +16,7 @@ def contents(self): class ThtLed(Led, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'D', 'LED_THT:LED_D5.0mm', @@ -29,7 +29,7 @@ def contents(self): class Smt0606RgbLed(RgbLedCommonAnode, JlcPart, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'D', 'LED_SMD:LED_LiteOn_LTST-C19HE1WT', @@ -46,7 +46,7 @@ def contents(self): class Smt0404RgbLed(RgbLedCommonAnode, JlcPart, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'D', 'LED_SMD:LED_Lumex_SML-LX0404SIUPGUSB', @@ -63,7 +63,7 @@ def contents(self): class ThtRgbLed(RgbLedCommonAnode, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'D', 'LED_THT:LED_D5.0mm-4_RGB_Staggered_Pins', diff --git a/edg/parts/LightSensor_As7341.py b/edg/parts/LightSensor_As7341.py index ced3800f2..2ee4fedaa 100644 --- a/edg/parts/LightSensor_As7341.py +++ b/edg/parts/LightSensor_As7341.py @@ -42,14 +42,14 @@ def contents(self) -> None: class As7341(LightSensor, Block): """11-channel spectral sensor, from 350nm to 1000nm, with 8 visible light channels, a NIR channel, a non-filtered ("clear" wideband) channel, and a flicker detection channel""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(As7341_Device()) self.pwr = self.Export(self.ic.vdd, [Power]) self.gnd = self.Export(self.ic.gnd, [Common]) self.i2c = self.Export(self.ic.i2c) - def contents(self): + def contents(self) -> None: super().contents() # capacitance value assumed, same value as on Adafruit's breakout self.vdd_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) diff --git a/edg/parts/LightSensor_Bh1750.py b/edg/parts/LightSensor_Bh1750.py index 0b85ed607..6a74c1c14 100644 --- a/edg/parts/LightSensor_Bh1750.py +++ b/edg/parts/LightSensor_Bh1750.py @@ -38,14 +38,14 @@ def contents(self) -> None: class Bh1750(LightSensor, Block): """16-bit ambient light sensor, 1-65535 lx""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Bh1750_Device()) self.pwr = self.Export(self.ic.vcc, [Power]) self.gnd = self.Export(self.ic.gnd, [Common]) self.i2c = self.Export(self.ic.i2c) - def contents(self): + def contents(self) -> None: super().contents() # capacitors from shuttle board example self.vcc_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vcc) self.dvi_res = self.Block(Resistor(1*kOhm(tol=0.05))) diff --git a/edg/parts/LinearRegulators.py b/edg/parts/LinearRegulators.py index 3a96282c5..49dc8e8d8 100644 --- a/edg/parts/LinearRegulators.py +++ b/edg/parts/LinearRegulators.py @@ -16,7 +16,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() parts = [ # output voltage (Range(1.140, 1.260), 'LD1117S12TR', 'C155612'), @@ -70,7 +70,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() TOLERANCE = 0.03 # worst-case -40 < Tj < 125C, slightly better at 25C parts = [ # output voltage @@ -137,7 +137,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() TOLERANCE = 0.02 @@ -179,7 +179,7 @@ class Ap2204k(VoltageRegulatorEnableWrapper, LinearRegulator): def _generator_inner_reset_pin(self) -> Port[DigitalLink]: return self.ic.en - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Ap2204k_Device(self.output_voltage)) self.connect(self.pwr_in, self.ic.pwr_in) @@ -218,7 +218,7 @@ def __init__(self, output_voltage: RangeLike): class Ap7215(LinearRegulator): """AP7215 fixed 3.3v LDO in SOT-89 providing the LinearRegulator interface. """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Ap7215_Device(self.output_voltage)) self.connect(self.pwr_in, self.ic.pwr_in) @@ -240,7 +240,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() parts = [ # output range, part number, (dropout typ @10mA, max @100mA), max current, lcsc, basic part # +/-0.03v tolerance for Vout < 1.5v @@ -318,7 +318,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() TOLERANCE = 0.02 # worst-case -40 < Tj < 125C, slightly better at 25C parts = [ # output voltage, part number, (dropout typ @ 30mA, dropout max @ 100mA), max current, lcsc @@ -387,7 +387,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() TOLERANCE = 0.02 # worst-case -40 < Tj < 125C, slightly better at 25C parts = [ # output voltage @@ -458,7 +458,7 @@ def __init__(self, output_voltage: RangeLike): input_thresholds=(0.4, 1.2)*Volt )) - def generate(self): + def generate(self) -> None: super().generate() parts = [ # output voltage, Table in 6.5 tolerance varies by output voltage (Range.from_tolerance(1.2, 0.03), 'LP5907MFX-1.2/NOPB', 'Package_TO_SOT_SMD:SOT-23-5', 'C73478'), @@ -559,7 +559,7 @@ def __init__(self, output_voltage: RangeLike): input_thresholds=(0.3, 1)*Volt )) - def generate(self): + def generate(self) -> None: super().generate() tolerance = 0.015 # over 125C range, Vout >= 1v parts = [ # output range, part, dropout voltage for non-DYD over 125C range, LCSC @@ -630,7 +630,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() parts = [ # output voltage, input max voltage, quiescent current, dropout @@ -672,7 +672,7 @@ def generate(self): class L78l(LinearRegulator): """L78Lxx high(er) input voltage linear regulator in SOT-89. """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(L78l_Device(self.output_voltage)) self.connect(self.pwr_in, self.ic.pwr_in) diff --git a/edg/parts/Lsm6dsv16x.py b/edg/parts/Lsm6dsv16x.py index bdc01f2f3..52ac3e495 100644 --- a/edg/parts/Lsm6dsv16x.py +++ b/edg/parts/Lsm6dsv16x.py @@ -61,7 +61,7 @@ class Lsm6dsv16x(Accelerometer, Gyroscope, DefaultExportBlock): (ranging over +/- 125/250/500/1000/2000 dps). Onboard sensor fusion for quaternion calculation. Supports external qvar for tap detections, etc.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Lsm6dsv16x_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) @@ -77,7 +77,7 @@ def __init__(self): self.qvar1 = self.Export(self.ic.qvar1, optional=True, doc="qvar input pin 1") self.qvar2 = self.Export(self.ic.qvar2, optional=True, doc="qvar input pin 2") - def contents(self): + def contents(self) -> None: super().contents() self.vdd_cap = self.Block(DecouplingCapacitor(100 * nFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) self.vddio_cap = self.Block(DecouplingCapacitor(100 * nFarad(tol=0.2))).connected(self.gnd, self.ic.vddio) diff --git a/edg/parts/Mag_Qmc5883l.py b/edg/parts/Mag_Qmc5883l.py index 71638c6d6..9d5ce533e 100644 --- a/edg/parts/Mag_Qmc5883l.py +++ b/edg/parts/Mag_Qmc5883l.py @@ -58,7 +58,7 @@ class Qmc5883l(Magnetometer, DefaultExportBlock): """3-axis magnetometer. This part seems to be a licensed semi-copy of the HMC5883L which is no longer in production. It might be hardware drop-in compatible though the firmware protocol differs.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Qmc5883l_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) @@ -67,7 +67,7 @@ def __init__(self): self.i2c = self.Export(self.ic.i2c) self.drdy = self.Export(self.ic.drdy, optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.vdd_cap = self.Block(DecouplingCapacitor(0.1*uFarad(tol=0.2))).connected(self.gnd, self.ic.vdd) self.set_cap = self.Block(Capacitor(0.22*uFarad(tol=0.2), voltage=self.pwr.link().voltage)) diff --git a/edg/parts/MagneticSensor_A1304.py b/edg/parts/MagneticSensor_A1304.py index 5eee00965..ae986a187 100644 --- a/edg/parts/MagneticSensor_A1304.py +++ b/edg/parts/MagneticSensor_A1304.py @@ -3,7 +3,7 @@ class A1304_Device(InternalBlock, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground()) self.vcc = self.Port(VoltageSink.from_gnd( @@ -16,7 +16,7 @@ def __init__(self): signal_out_abs=(0.38, 2.87) # output saturation limits @ Vcc=3.3v )) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23', { @@ -34,13 +34,13 @@ def contents(self): class A1304(Magnetometer, Block): """Linear hall-effect sensor with analog output, sometimes used in game controllers as trigger detectors. Typ 4 mV / Gauss with full scale range of +/-375 Gauss.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(A1304_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) self.pwr = self.Export(self.ic.vcc, [Power]) self.out = self.Export(self.ic.vout, [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.cbyp = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.pwr) diff --git a/edg/parts/MagneticSwitch_Ah1806.py b/edg/parts/MagneticSwitch_Ah1806.py index fa14bf817..d38366e0d 100644 --- a/edg/parts/MagneticSwitch_Ah1806.py +++ b/edg/parts/MagneticSwitch_Ah1806.py @@ -3,7 +3,7 @@ class Ah1806_Device(InternalBlock, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground()) self.vdd = self.Port(VoltageSink.from_gnd( @@ -15,7 +15,7 @@ def __init__(self): self.gnd, current_limits=(-1, 0)*mAmp )) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23', { @@ -36,13 +36,13 @@ class Ah1806(MagneticSwitch, Block): and 20 G (10-40 tolerance range) release point. 0.1% duty cycle, period of 75ms (typ). Pin-compatible with some others in the AH18xx series and DRV5032, which have different trip characteristics""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Ah1806_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) self.pwr = self.Export(self.ic.vdd, [Power]) self.out = self.Export(self.ic.output, [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.cin = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.pwr) diff --git a/edg/parts/Mechanicals.py b/edg/parts/Mechanicals.py index 81146d1a7..9f5e2d7e7 100644 --- a/edg/parts/Mechanicals.py +++ b/edg/parts/Mechanicals.py @@ -3,7 +3,7 @@ @deprecated("non-circuit footprints should be added in layout as non-schematic items") class Outline_Pn1332(Mechanical, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.footprint( '', 'calisco:Outline_150mm_70mm_PNX-91432', @@ -18,11 +18,11 @@ def contents(self): class MountingHole(Mechanical, FootprintBlock): FOOTPRINT: str = '' VALUE: str = '' - def __init__(self): + def __init__(self) -> None: super().__init__() self.pad = self.Port(Passive(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'H', self.FOOTPRINT, diff --git a/edg/parts/Microcontroller_Esp.py b/edg/parts/Microcontroller_Esp.py index 1a679f5ca..eb0f9d4c8 100644 --- a/edg/parts/Microcontroller_Esp.py +++ b/edg/parts/Microcontroller_Esp.py @@ -1,3 +1,5 @@ +from typing import Any + from ..abstract_parts import * from .PassiveConnector_Header import PinHeader254 from .PassiveConnector_TagConnect import TagConnect @@ -22,7 +24,7 @@ class EspProgrammingAutoReset(BlockInterfaceMixin[EspProgrammingHeader]): """Mixin for ESP programming header with auto-reset and auto-boot pins. By default, these are required to be connected (since it doesn't make sense to instantiate this without connecting the additional pins to the micro), but can be disabled with parameters.""" - def __init__(self, *args, require_auto_reset: BoolLike = True, **kwargs) -> None: + def __init__(self, *args: Any, require_auto_reset: BoolLike = True, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.en = self.Port(DigitalSource.empty(), optional=True) # effectively a reset pin @@ -86,7 +88,7 @@ def __init__(self, programming: StringLike = "uart-button"): self.program_en_node = self.connect() self.program_boot_node = self.connect() - def generate(self): + def generate(self) -> None: super().generate() programming = self.get(self.programming) @@ -115,7 +117,7 @@ def generate(self): class EspAutoProgram(Interface, KiCadSchematicBlock): """Auto-programming circuit for the ESP series, to drive the target EN (reset) and BOOT (e.g., IO0) pins.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.dtr = self.Port(DigitalSink.empty()) self.rts = self.Port(DigitalSink.empty()) @@ -123,7 +125,7 @@ def __init__(self): self.en = self.Port(DigitalSource.empty()) self.boot = self.Port(DigitalSource.empty()) - def contents(self): + def contents(self) -> None: super().contents() signal_voltage = self.dtr.link().voltage.hull(self.rts.link().voltage) signal_thresholds = self.dtr.link().output_thresholds.hull(self.rts.link().output_thresholds) diff --git a/edg/parts/Microcontroller_Esp32.py b/edg/parts/Microcontroller_Esp32.py index 3cb1b88a7..384b1d4b2 100644 --- a/edg/parts/Microcontroller_Esp32.py +++ b/edg/parts/Microcontroller_Esp32.py @@ -145,7 +145,7 @@ class Esp32_Base(Esp32_Ios, GeneratorBlock): """ SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s) - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.pwr = self.Port(self._vdd_model(), [Power]) @@ -241,7 +241,7 @@ class Esp32_Wroom_32(Microcontroller, Radiofrequency, HasEspProgramming, Resetta """Wrapper around Esp32c3_Wroom02 with external capacitors and UART programming header. NOT COMPATIBLE WITH QSPI PSRAM VARIANTS - for those, GPIO16 needs to be pulled up. """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic: Esp32_Wroom_32_Device self.generator_param(self.reset.is_connected()) @@ -348,8 +348,8 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]: 'GPIO2': self.io2, }).remap(self.SYSTEM_PIN_REMAP) - def __init__(self, **kawrgs) -> None: - super().__init__(**kawrgs) + def __init__(self, **kwargs: Any) -> None: + super().__init__(**kwargs) self.gnd.init_from(Ground()) self.pwr.init_from(self._vdd_model()) diff --git a/edg/parts/Microcontroller_Esp32c3.py b/edg/parts/Microcontroller_Esp32c3.py index 11a6319a1..1001b44c9 100644 --- a/edg/parts/Microcontroller_Esp32c3.py +++ b/edg/parts/Microcontroller_Esp32c3.py @@ -110,7 +110,7 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]: 'RXD': self.uart0.rx, } - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.pwr = self.Port(self._vdd_model(), [Power]) @@ -173,7 +173,7 @@ def generate(self) -> None: class Esp32c3_Wroom02(Microcontroller, Radiofrequency, HasEspProgramming, Resettable, Esp32c3_Interfaces, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): """Wrapper around Esp32c3_Wroom02 with external capacitors and UART programming header.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic: Esp32c3_Wroom02_Device self.generator_param(self.reset.is_connected()) @@ -265,7 +265,7 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]: 'TXD': '28', # U0TXD, GPIO21 }) - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.lna_in = self.Port(Passive()) @@ -320,7 +320,7 @@ class Esp32c3(Microcontroller, Radiofrequency, HasEspProgramming, Resettable, Es DEFAULT_CRYSTAL_FREQUENCY = 40*MHertz(tol=10e-6) - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic: Esp32c3_Device self.generator_param(self.reset.is_connected()) diff --git a/edg/parts/Microcontroller_Esp32s3.py b/edg/parts/Microcontroller_Esp32s3.py index 6b7c60f4b..5b7613807 100644 --- a/edg/parts/Microcontroller_Esp32s3.py +++ b/edg/parts/Microcontroller_Esp32s3.py @@ -168,7 +168,7 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]: 'U0TXD': self.uart0.tx, }).remap(self.SYSTEM_PIN_REMAP) - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.pwr = self.Port(self._vdd_model(), [Power]) @@ -245,7 +245,7 @@ class Esp32s3_Wroom_1(Microcontroller, Radiofrequency, HasEspProgramming, Resett IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): """ESP32-S3-WROOM-1 module """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic: Esp32s3_Wroom_1_Device self.generator_param(self.reset.is_connected()) diff --git a/edg/parts/Microcontroller_Lpc1549.py b/edg/parts/Microcontroller_Lpc1549.py index fad6c4473..38ac7fe70 100644 --- a/edg/parts/Microcontroller_Lpc1549.py +++ b/edg/parts/Microcontroller_Lpc1549.py @@ -15,7 +15,7 @@ class Lpc1549Base_Device(IoControllerSpiPeripheral, IoControllerI2cTarget, IoCon SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s) RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) # Ports with shared references @@ -321,13 +321,13 @@ class Lpc1549_64_Device(Lpc1549Base_Device): class Lpc1549SwdPull(InternalSubcircuit, Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink.empty(), [Power]) self.gnd = self.Port(Ground.empty(), [Common]) self.swd = self.Port(SwdPullPort(DigitalSource.empty()), [InOut]) - def contents(self): + def contents(self) -> None: super().contents() self.swdio = self.Block(PullupResistor((10, 100) * kOhm(tol=0.05))).connected(self.pwr, self.swd.swdio) self.swclk = self.Block(PulldownResistor((10, 100) * kOhm(tol=0.05))).connected(self.gnd, self.swd.swclk) @@ -337,15 +337,15 @@ def contents(self): class Lpc1549Base(Resettable, IoControllerSpiPeripheral, IoControllerI2cTarget, IoControllerDac, IoControllerCan, IoControllerUsb, Microcontroller, IoControllerWithSwdTargetConnector, WithCrystalGenerator, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): - DEVICE: Type[Lpc1549Base_Device] = Lpc1549Base_Device # type: ignore + DEVICE: Type[Lpc1549Base_Device] = Lpc1549Base_Device DEFAULT_CRYSTAL_FREQUENCY = 12*MHertz(tol=0.005) - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Lpc1549Base_Device self.generator_param(self.reset.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() with self.implicit_connect( @@ -376,7 +376,7 @@ def contents(self): self.vref_cap[1] = imp.Block(DecouplingCapacitor(0.1 * uFarad(tol=0.2))) self.vref_cap[2] = imp.Block(DecouplingCapacitor(10 * uFarad(tol=0.2))) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): diff --git a/edg/parts/Microcontroller_Rp2040.py b/edg/parts/Microcontroller_Rp2040.py index b3b0bc5ae..ca3ed57eb 100644 --- a/edg/parts/Microcontroller_Rp2040.py +++ b/edg/parts/Microcontroller_Rp2040.py @@ -20,7 +20,7 @@ def _vddio(self) -> Port[VoltageLink]: """Returns VDDIO (can be VoltageSink or VoltageSource).""" ... - def _iovdd_model(self): + def _iovdd_model(self) -> VoltageSink: return VoltageSink( voltage_limits=(1.62, 3.63)*Volt, # Table 628 current_draw=(1.2, 4.3)*mAmp + self.io_current_draw.upper() # Table 629 @@ -180,7 +180,7 @@ class Rp2040_Device(Rp2040_Ios, BaseIoControllerPinmapGenerator, InternalSubcirc def _vddio(self) -> Port[VoltageLink]: return self.iovdd - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.gnd = self.Port(Ground(), [Common]) @@ -312,7 +312,7 @@ class Rp2040(Resettable, Rp2040_Interfaces, Microcontroller, IoControllerWithSwd WithCrystalGenerator, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): DEFAULT_CRYSTAL_FREQUENCY = 12*MHertz(tol=0.005) - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Rp2040_Device self.generator_param(self.reset.is_connected()) @@ -353,7 +353,7 @@ def contents(self) -> None: self.vreg_out_cap = self.Block(DecouplingCapacitor(1 * uFarad(tol=0.2))).connected(self.gnd, self.ic.dvdd) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): diff --git a/edg/parts/Microcontroller_Stm32f103.py b/edg/parts/Microcontroller_Stm32f103.py index 35c31b0ec..359228dbd 100644 --- a/edg/parts/Microcontroller_Stm32f103.py +++ b/edg/parts/Microcontroller_Stm32f103.py @@ -15,7 +15,7 @@ class Stm32f103Base_Device(IoControllerI2cTarget, IoControllerCan, IoControllerU SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s) RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) # Additional ports (on top of BaseIoController) @@ -265,15 +265,15 @@ def __init__(self, resistance: RangeLike): class Stm32f103Base(Resettable, IoControllerI2cTarget, IoControllerCan, IoControllerUsb, Microcontroller, IoControllerWithSwdTargetConnector, WithCrystalGenerator, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): - DEVICE: Type[Stm32f103Base_Device] = Stm32f103Base_Device # type: ignore + DEVICE: Type[Stm32f103Base_Device] = Stm32f103Base_Device DEFAULT_CRYSTAL_FREQUENCY = 12*MHertz(tol=0.005) - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Stm32f103Base_Device self.generator_param(self.reset.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() with self.implicit_connect( @@ -295,7 +295,7 @@ def contents(self): self.vdda_cap_0 = imp.Block(DecouplingCapacitor(10 * nFarad(tol=0.2))) self.vdda_cap_1 = imp.Block(DecouplingCapacitor(1 * uFarad(tol=0.2))) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): diff --git a/edg/parts/Microcontroller_Stm32f303.py b/edg/parts/Microcontroller_Stm32f303.py index 0e78f7974..b7d7d0670 100644 --- a/edg/parts/Microcontroller_Stm32f303.py +++ b/edg/parts/Microcontroller_Stm32f303.py @@ -238,7 +238,7 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]: 'Vusb': self.vusb_out, }).remap(self.SYSTEM_PIN_REMAP) - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd.init_from(Ground()) diff --git a/edg/parts/Microcontroller_Stm32g031.py b/edg/parts/Microcontroller_Stm32g031.py index a0a82c163..fff3a0c2c 100644 --- a/edg/parts/Microcontroller_Stm32g031.py +++ b/edg/parts/Microcontroller_Stm32g031.py @@ -15,7 +15,7 @@ class Stm32g031Base_Device(IoControllerI2cTarget, IoControllerCan, IoControllerU SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s) RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) # Additional ports (on top of BaseIoController) @@ -199,14 +199,14 @@ class Stm32g031_G_Device(Stm32g031Base_Device): @abstract_block class Stm32g031Base(Resettable, IoControllerI2cTarget, Microcontroller, IoControllerWithSwdTargetConnector, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): - DEVICE: Type[Stm32g031Base_Device] = Stm32g031Base_Device # type: ignore + DEVICE: Type[Stm32g031Base_Device] = Stm32g031Base_Device - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Stm32g031Base_Device self.generator_param(self.reset.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() with self.implicit_connect( @@ -221,7 +221,7 @@ def contents(self): self.pwr_cap0 = imp.Block(DecouplingCapacitor(4.7 * uFarad(tol=0.2))) self.pwr_cap1 = imp.Block(DecouplingCapacitor(0.1 * uFarad(tol=0.2))) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): diff --git a/edg/parts/Microcontroller_Stm32g431.py b/edg/parts/Microcontroller_Stm32g431.py index f429cad50..3bf0e95b7 100644 --- a/edg/parts/Microcontroller_Stm32g431.py +++ b/edg/parts/Microcontroller_Stm32g431.py @@ -16,7 +16,7 @@ class Stm32g431Base_Device(IoControllerI2cTarget, IoControllerCan, IoControllerU SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s) RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) # Power and ground @@ -240,12 +240,12 @@ class Stm32g431Base(Resettable, IoControllerI2cTarget, Microcontroller, IoContro IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): DEVICE: Type[Stm32g431Base_Device] = Stm32g431Base_Device - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Stm32g431Base_Device self.generator_param(self.reset.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() with self.implicit_connect( ImplicitConnect(self.pwr, [Power]), @@ -263,7 +263,7 @@ def contents(self): self.pwr_cap3 = imp.Block(DecouplingCapacitor(100 * nFarad(tol=0.2))) self.pwr_cap4 = imp.Block(DecouplingCapacitor(1 * uFarad(tol=0.2))) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): self.connect(self.reset, self.ic.nrst) # otherwise NRST has internal pull-up diff --git a/edg/parts/Microcontroller_Stm32l432.py b/edg/parts/Microcontroller_Stm32l432.py index 2d047e7c5..19b16d402 100644 --- a/edg/parts/Microcontroller_Stm32l432.py +++ b/edg/parts/Microcontroller_Stm32l432.py @@ -15,7 +15,7 @@ class Stm32l432Base_Device(IoControllerI2cTarget, IoControllerDac, IoControllerC SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s) RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) # Additional ports (on top of BaseIoController) @@ -217,14 +217,14 @@ class Stm32l432k_Device(Stm32l432Base_Device): class Stm32l432Base(Resettable, IoControllerDac, IoControllerCan, IoControllerUsb, IoControllerI2cTarget, Microcontroller, IoControllerWithSwdTargetConnector, WithCrystalGenerator, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): - DEVICE: Type[Stm32l432Base_Device] = Stm32l432Base_Device # type: ignore + DEVICE: Type[Stm32l432Base_Device] = Stm32l432Base_Device - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Stm32l432Base_Device self.generator_param(self.reset.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() with self.implicit_connect( @@ -243,7 +243,7 @@ def contents(self): self.vdda_cap0 = imp.Block(DecouplingCapacitor(10*nFarad(tol=0.2))) self.vdda_cap1 = imp.Block(DecouplingCapacitor(1*uFarad(tol=0.2))) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): diff --git a/edg/parts/Microcontroller_nRF52840.py b/edg/parts/Microcontroller_nRF52840.py index 44bd589f1..96b8c95e9 100644 --- a/edg/parts/Microcontroller_nRF52840.py +++ b/edg/parts/Microcontroller_nRF52840.py @@ -183,7 +183,7 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]: 'nRESET': self.nreset, }).remap(self.SYSTEM_PIN_REMAP) - def __init__(self, **kwargs) -> None: + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.gnd = self.Port(Ground(), [Common]) @@ -266,14 +266,14 @@ def generate(self) -> None: class Holyiot_18010(Microcontroller, Radiofrequency, Resettable, Nrf52840_Interfaces, IoControllerWithSwdTargetConnector, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): """Wrapper around the Holyiot 18010 that includes supporting components (programming port)""" - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Holyiot_18010_Device self.ic = self.Block(Holyiot_18010_Device(pin_assigns=ArrayStringExpr())) self.pwr_usb = self.Export(self.ic.pwr_usb, optional=True) self.generator_param(self.reset.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.pwr, self.ic.pwr) self.connect(self.gnd, self.ic.gnd) @@ -281,7 +281,7 @@ def contents(self): self.connect(self.swd_node, self.ic.swd) self.connect(self.reset_node, self.ic.nreset) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): self.connect(self.reset, self.ic.nreset) @@ -364,7 +364,7 @@ def generate(self) -> None: class Mdbt50q_UsbSeriesResistor(InternalSubcircuit, Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.usb_inner = self.Port(UsbHostPort.empty(), [Input]) self.usb_outer = self.Port(UsbDevicePort.empty(), [Output]) @@ -379,7 +379,7 @@ def __init__(self): class Mdbt50q_1mv2(Microcontroller, Radiofrequency, Resettable, Nrf52840_Interfaces, IoControllerWithSwdTargetConnector, IoControllerPowerRequired, BaseIoControllerExportable, GeneratorBlock): """Wrapper around the Mdbt50q_1mv2 that includes the reference schematic""" - def __init__(self, **kwargs): + def __init__(self, **kwargs: Any) -> None: super().__init__(**kwargs) self.ic: Mdbt50q_1mv2_Device self.ic = self.Block(Mdbt50q_1mv2_Device(pin_assigns=ArrayStringExpr())) # defined in generator to mix in SWO/TDI @@ -400,7 +400,7 @@ def contents(self) -> None: ) as imp: self.vcc_cap = imp.Block(DecouplingCapacitor(10 * uFarad(tol=0.2))) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.reset.is_connected()): @@ -482,7 +482,7 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]: 'Vbus': self.vusb_out, }).remap(self.SYSTEM_PIN_REMAP) - def contents(self): + def contents(self) -> None: super().contents() self.gnd.init_from(Ground()) diff --git a/edg/parts/Microphone_Sd18ob261.py b/edg/parts/Microphone_Sd18ob261.py index 4aacd59eb..03976b9fc 100644 --- a/edg/parts/Microphone_Sd18ob261.py +++ b/edg/parts/Microphone_Sd18ob261.py @@ -3,7 +3,7 @@ class Sd18ob261_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vdd = self.Port(VoltageSink( @@ -27,7 +27,7 @@ def __init__(self): current_limits=(-20, 20)*mAmp # short circuit current for data pin )) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Sensor_Audio:Knowles_LGA-5_3.5x2.65mm', { @@ -48,7 +48,7 @@ class Sd18ob261(Microphone, GeneratorBlock): """SD18OB261-060 PDM microphone, probably footprint-compatible with similar Knowles devices. Application circuit is not specified in the datasheet, this uses the one from SPH0655LM4H (single 0.1uF decap).""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Sd18ob261_Device()) @@ -61,7 +61,7 @@ def __init__(self): self.generator_param(self.lr.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() self.pwr_cap = self.Block(DecouplingCapacitor(0.1*uFarad(tol=0.2))).connected(self.gnd, self.pwr) diff --git a/edg/parts/Neopixel.py b/edg/parts/Neopixel.py index 99ad6384f..9b852c215 100644 --- a/edg/parts/Neopixel.py +++ b/edg/parts/Neopixel.py @@ -254,7 +254,7 @@ def __init__(self, count: IntLike): self.count = self.ArgParameter(count) self.generator_param(self.count) - def generate(self): + def generate(self) -> None: super().generate() self.led = ElementDict[Neopixel]() diff --git a/edg/parts/Oled_Er_Oled_022.py b/edg/parts/Oled_Er_Oled_022.py index 70886e5b0..71723ee33 100644 --- a/edg/parts/Oled_Er_Oled_022.py +++ b/edg/parts/Oled_Er_Oled_022.py @@ -74,7 +74,7 @@ def __init__(self) -> None: self.i2c = self.Port(I2cTarget.empty(), optional=True) self.generator_param(self.spi.is_connected(), self.i2c.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.reset, self.device.res) self.require(self.reset.is_connected()) @@ -96,7 +96,7 @@ def contents(self): self.vcc_cap2 = self.Block(DecouplingCapacitor(capacitance=10*uFarad(tol=0.2)))\ .connected(self.gnd, self.device.vcc) - def generate(self): + def generate(self) -> None: super().generate() gnd_digital = self.gnd.as_digital_source() diff --git a/edg/parts/Oled_Er_Oled_028.py b/edg/parts/Oled_Er_Oled_028.py index 2aec6fca3..0eb2605b8 100644 --- a/edg/parts/Oled_Er_Oled_028.py +++ b/edg/parts/Oled_Er_Oled_028.py @@ -88,7 +88,7 @@ def __init__(self) -> None: self.generator_param(self.dc.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.pwr, self.device.vci) self.connect(self.reset, self.device.res) @@ -123,7 +123,7 @@ def contents(self): self.connect(self.vsl_d1.cathode, self.vsl_d2.anode) self.connect(self.vsl_d2.cathode.adapt_to(Ground()), self.gnd) - def generate(self): + def generate(self) -> None: super().generate() if self.get(self.dc.is_connected()): # 4-line serial self.connect(self.gnd.as_digital_source(), self.device.bs0) diff --git a/edg/parts/Oled_Er_Oled_091_3.py b/edg/parts/Oled_Er_Oled_091_3.py index 1e255e1cf..cba39e969 100644 --- a/edg/parts/Oled_Er_Oled_091_3.py +++ b/edg/parts/Oled_Er_Oled_091_3.py @@ -77,7 +77,7 @@ def __init__(self) -> None: self.cs = self.Export(self.device.cs) self.dc = self.Export(self.device.dc) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.pwr, self.device.vbat) self.connect(self.reset, self.device.res) diff --git a/edg/parts/Oled_Er_Oled_096_1_1.py b/edg/parts/Oled_Er_Oled_096_1_1.py index 479039fb8..93e99b2a9 100644 --- a/edg/parts/Oled_Er_Oled_096_1_1.py +++ b/edg/parts/Oled_Er_Oled_096_1_1.py @@ -87,7 +87,7 @@ def __init__(self) -> None: self.i2c = self.Port(I2cTarget.empty(), optional=True) self.generator_param(self.spi.is_connected(), self.dc.is_connected(), self.i2c.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.pwr, self.device.vbat) self.connect(self.reset, self.device.res) @@ -113,7 +113,7 @@ def contents(self): self.vcc_cap = self.Block(DecouplingCapacitor(capacitance=(2.2*0.8, 10)*uFarad))\ .connected(self.gnd, self.device.vcc) - def generate(self): + def generate(self) -> None: super().generate() gnd_digital = self.gnd.as_digital_source() diff --git a/edg/parts/Oled_Er_Oled_096_1c.py b/edg/parts/Oled_Er_Oled_096_1c.py index 174b9b03a..3fc81f9df 100644 --- a/edg/parts/Oled_Er_Oled_096_1c.py +++ b/edg/parts/Oled_Er_Oled_096_1c.py @@ -88,7 +88,7 @@ def __init__(self) -> None: self.i2c = self.Port(I2cSlave.empty(), optional=True) self.generator_param(self.spi.is_connected(), self.dc.is_connected(), self.i2c.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.reset, self.device.res) self.require(self.reset.is_connected()) @@ -116,7 +116,7 @@ def contents(self): self.connect(self.vsl_d1.cathode, self.vsl_d2.anode) self.connect(self.vsl_d2.cathode.adapt_to(Ground()), self.gnd) - def generate(self): + def generate(self) -> None: super().generate() gnd_digital = self.gnd.as_digital_source() diff --git a/edg/parts/Oled_Nhd_312_25664uc.py b/edg/parts/Oled_Nhd_312_25664uc.py index a0c4ec234..6c9d53003 100644 --- a/edg/parts/Oled_Nhd_312_25664uc.py +++ b/edg/parts/Oled_Nhd_312_25664uc.py @@ -27,7 +27,7 @@ def __init__(self) -> None: self.nres = self.Port(DigitalSink.from_bidir(io_model)) self.ncs = self.Port(DigitalSink.from_bidir(io_model)) - def contents(self): + def contents(self) -> None: super().contents() pinning: Dict[str, CircuitPort] = { @@ -73,7 +73,7 @@ def __init__(self) -> None: self.cs = self.Export(self.device.ncs) self.spi = self.Port(SpiPeripheral(DigitalBidir.empty())) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.spi.sck, self.device.sclk) diff --git a/edg/parts/Opamp_Lmv321.py b/edg/parts/Opamp_Lmv321.py index 7ca13a946..6145f849b 100644 --- a/edg/parts/Opamp_Lmv321.py +++ b/edg/parts/Opamp_Lmv321.py @@ -3,7 +3,7 @@ class Lmv321_Device(InternalSubcircuit, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vcc = self.Port(VoltageSink( voltage_limits=(2.7, 5.5)*Volt, current_draw=(80, 170)*uAmp # quiescent current @@ -23,7 +23,7 @@ def __init__(self): current_limits=(-40, 40)*mAmp, # output short circuit current )) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23-5', @@ -44,7 +44,7 @@ def contents(self): class Lmv321(Opamp): """RRO op-amp in SOT-23-5. """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Lmv321_Device()) diff --git a/edg/parts/Opamp_Mcp6001.py b/edg/parts/Opamp_Mcp6001.py index 2294418ad..2c6d73e84 100644 --- a/edg/parts/Opamp_Mcp6001.py +++ b/edg/parts/Opamp_Mcp6001.py @@ -3,7 +3,7 @@ class Mcp6001_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vcc = self.Port(VoltageSink( voltage_limits=(1.8, 6.0)*Volt, current_draw=(50, 170)*uAmp @@ -25,7 +25,7 @@ def __init__(self): impedance=300*Ohm(tol=0) # no tolerance bounds given on datasheet )) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23-5', @@ -46,7 +46,7 @@ def contents(self): class Mcp6001(Opamp): """MCP6001 RRO op-amp in SOT-23-5 """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Mcp6001_Device()) diff --git a/edg/parts/Opamp_Opax171.py b/edg/parts/Opamp_Opax171.py index 94f1d4c79..2f960302d 100644 --- a/edg/parts/Opamp_Opax171.py +++ b/edg/parts/Opamp_Opax171.py @@ -6,7 +6,7 @@ class Opa171_Base_Device(InternalSubcircuit): DEVICES: int - def _analog_in_model(self): + def _analog_in_model(self) -> AnalogSink: return AnalogSink.from_supply( self.vn, self.vp, voltage_limit_tolerance=(-0.5, 0.5)*Volt, # input common mode absolute maximum ratings @@ -14,7 +14,7 @@ def _analog_in_model(self): impedance=100e6*Ohm(tol=0) # no tolerance specified; differential impedance ) - def _analog_out_model(self): + def _analog_out_model(self) -> AnalogSource: return AnalogSource.from_supply( self.vn, self.vp, signal_out_bound=(0.350*Volt, -0.350*Volt), # output swing from rail, 10k load, over temperature @@ -22,7 +22,7 @@ def _analog_out_model(self): impedance=150*Ohm(tol=0) # open-loop resistance ) - def __init__(self): + def __init__(self) -> None: super().__init__() self.vn = self.Port(Ground(), [Common]) self.vp = self.Port(VoltageSink( @@ -34,7 +34,7 @@ def __init__(self): class Opa2171_Device(Opa171_Base_Device, JlcPart, FootprintBlock): DEVICES = 2 - def __init__(self): + def __init__(self) -> None: super().__init__() analog_in_model = self._analog_in_model() @@ -46,7 +46,7 @@ def __init__(self): self.innb = self.Port(analog_in_model) self.outb = self.Port(analog_out_model) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', diff --git a/edg/parts/Opamp_Opax189.py b/edg/parts/Opamp_Opax189.py index 694de5861..532272144 100644 --- a/edg/parts/Opamp_Opax189.py +++ b/edg/parts/Opamp_Opax189.py @@ -6,7 +6,7 @@ class Opax189_Base_Device(InternalSubcircuit): DEVICES: int - def _analog_in_model(self): + def _analog_in_model(self) -> AnalogSink: return AnalogSink.from_supply( self.vn, self.vp, voltage_limit_tolerance=(-0.5, 0.5)*Volt, # input common mode absolute maximum ratings @@ -14,7 +14,7 @@ def _analog_in_model(self): impedance=100*MOhm(tol=0), # differential input impedance; no tolerance bounds specified ) - def _analog_out_model(self): + def _analog_out_model(self) -> AnalogSource: return AnalogSource.from_supply( self.vn, self.vp, signal_out_bound=(0.110*Volt, -0.111*Volt), # output swing from rail, assumed at 10k load @@ -22,7 +22,7 @@ def _analog_out_model(self): impedance=380*Ohm(tol=0) # open-loop impedance; no tolerance bounds specified ) - def __init__(self): + def __init__(self) -> None: super().__init__() self.vn = self.Port(Ground(), [Common]) self.vp = self.Port(VoltageSink( @@ -34,14 +34,14 @@ def __init__(self): class Opa189_Device(Opax189_Base_Device, JlcPart, FootprintBlock): DEVICES = 1 - def __init__(self): + def __init__(self) -> None: super().__init__() analog_in_model = self._analog_in_model() self.vinp = self.Port(analog_in_model) self.vinn = self.Port(analog_in_model) self.vout = self.Port(self._analog_out_model()) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', @@ -65,7 +65,7 @@ def contents(self): class Opa189(Opamp): """High voltage (4.5-36V), low-noise opamp in SOIC-8. """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Opa189_Device()) @@ -84,7 +84,7 @@ def contents(self): class Opa2189_Device(Opax189_Base_Device, JlcPart, FootprintBlock): DEVICES = 2 - def __init__(self): + def __init__(self) -> None: super().__init__() analog_in_model = self._analog_in_model() analog_out_model = self._analog_out_model() @@ -95,7 +95,7 @@ def __init__(self): self.innb = self.Port(analog_in_model) self.outb = self.Port(analog_out_model) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', diff --git a/edg/parts/Opamp_Opax197.py b/edg/parts/Opamp_Opax197.py index 10acd62dd..ae2182af4 100644 --- a/edg/parts/Opamp_Opax197.py +++ b/edg/parts/Opamp_Opax197.py @@ -6,7 +6,7 @@ class Opa197_Base_Device(InternalSubcircuit): DEVICES: int - def _analog_in_model(self): + def _analog_in_model(self) -> AnalogSink: return AnalogSink.from_supply( self.vn, self.vp, voltage_limit_tolerance=(-0.5, 0.5)*Volt, # input common mode absolute maximum ratings @@ -14,7 +14,7 @@ def _analog_in_model(self): impedance=1e13*Ohm(tol=0) # no tolerance bounds given on datasheet ) - def _analog_out_model(self): + def _analog_out_model(self) -> AnalogSource: return AnalogSource.from_supply( self.vn, self.vp, signal_out_bound=(0.125*Volt, -0.125*Volt), # output swing from rail, assumed at 10k load @@ -22,7 +22,7 @@ def _analog_out_model(self): impedance=375*Ohm(tol=0) # no tolerance bounds given on datasheet; open-loop impedance ) - def __init__(self): + def __init__(self) -> None: super().__init__() self.vn = self.Port(Ground(), [Common]) self.vp = self.Port(VoltageSink( @@ -34,14 +34,14 @@ def __init__(self): class Opa197_Device(Opa197_Base_Device, JlcPart, FootprintBlock): DEVICES = 1 - def __init__(self): + def __init__(self) -> None: super().__init__() analog_in_model = self._analog_in_model() self.vinp = self.Port(analog_in_model) self.vinn = self.Port(analog_in_model) self.vout = self.Port(self._analog_out_model()) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', @@ -66,7 +66,7 @@ class Opa197(Opamp): """High voltage opamp (4.5-36V) in SOIC-8. (part also available in SOT-23-5) """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Opa197_Device()) @@ -85,7 +85,7 @@ def contents(self): class Opa2197_Device(Opa197_Base_Device, JlcPart, FootprintBlock): DEVICES = 2 - def __init__(self): + def __init__(self) -> None: super().__init__() analog_in_model = self._analog_in_model() @@ -97,7 +97,7 @@ def __init__(self): self.innb = self.Port(analog_in_model) self.outb = self.Port(analog_out_model) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', diff --git a/edg/parts/Opamp_Opax333.py b/edg/parts/Opamp_Opax333.py index dd7613e74..0e05f3d58 100644 --- a/edg/parts/Opamp_Opax333.py +++ b/edg/parts/Opamp_Opax333.py @@ -3,7 +3,7 @@ class Opa2333_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vp = self.Port(VoltageSink( voltage_limits=(1.8, 5.5)*Volt, current_draw=(17*2, 28*2)*uAmp # quiescent current for both amps @@ -29,7 +29,7 @@ def __init__(self): self.innb = self.Port(analog_in_model) self.outb = self.Port(analog_out_model) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', diff --git a/edg/parts/Opamp_Tlv9061.py b/edg/parts/Opamp_Tlv9061.py index 755048d02..73c66c8e2 100644 --- a/edg/parts/Opamp_Tlv9061.py +++ b/edg/parts/Opamp_Tlv9061.py @@ -3,7 +3,7 @@ class Tlv9061_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vcc = self.Port(VoltageSink( voltage_limits=(1.8, 5.5)*Volt, current_draw=(538, 800)*uAmp # quiescent current @@ -24,7 +24,7 @@ def __init__(self): impedance=100*Ohm(tol=0) # no tolerance bounds given on datasheet; open-loop impedance )) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23-6', @@ -46,7 +46,7 @@ def contents(self): class Tlv9061(Opamp): """RRIO op-amp in SOT-23-6. """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(Tlv9061_Device()) diff --git a/edg/parts/Opamp_Tlv915x.py b/edg/parts/Opamp_Tlv915x.py index a3a5b18cb..c0b9fe1be 100644 --- a/edg/parts/Opamp_Tlv915x.py +++ b/edg/parts/Opamp_Tlv915x.py @@ -3,7 +3,7 @@ class Tlv9152_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vp = self.Port(VoltageSink( voltage_limits=(2.7, 16)*Volt, current_draw=(560*2, 750*2)*uAmp # quiescent current for both amps @@ -29,7 +29,7 @@ def __init__(self): self.innb = self.Port(analog_in_model) self.outb = self.Port(analog_out_model) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', diff --git a/edg/parts/PassiveConnector_Fpc.py b/edg/parts/PassiveConnector_Fpc.py index 959e7134e..02f41a3bc 100644 --- a/edg/parts/PassiveConnector_Fpc.py +++ b/edg/parts/PassiveConnector_Fpc.py @@ -23,11 +23,11 @@ class Fpc050Bottom(Fpc050): class Fpc050BottomFlip(Fpc050Bottom, GeneratorBlock): """Flipped FPC connector - bottom entry connector is top entry on the opposite board side. Reverses the pin ordering to reflect the mirroring.""" - def contents(self): + def contents(self) -> None: super().contents() self.generator_param(self.length, self.pins.requested()) - def generate(self): + def generate(self) -> None: super().generate() self.conn = self.Block(Fpc050Top(self.length)) length = self.get(self.length) diff --git a/edg/parts/PowerConditioning.py b/edg/parts/PowerConditioning.py index c4fc5a3b1..fdbdb7ddb 100644 --- a/edg/parts/PowerConditioning.py +++ b/edg/parts/PowerConditioning.py @@ -10,7 +10,7 @@ def __init__(self) -> None: self.pos = self.Port(VoltageSink()) self.neg = self.Port(Ground()) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'C', 'Capacitor_THT:CP_Radial_D14.0mm_P5.00mm', # actually 13.5 @@ -203,7 +203,7 @@ def __init__(self, diode_voltage_drop: RangeLike, fet_rds_on: RangeLike) -> None self.diode_voltage_drop = self.ArgParameter(diode_voltage_drop) self.fet_rds_on = self.ArgParameter(fet_rds_on) - def contents(self): + def contents(self) -> None: super().contents() # FET behavior requires the high priority path to be higher voltage @@ -269,7 +269,7 @@ def __init__(self, gate_resistor: RangeLike = 10 * kOhm(tol=0.05), rds_on: Range self.gate_resistor = self.ArgParameter(gate_resistor) self.rds_on = self.ArgParameter(rds_on) - def contents(self): + def contents(self) -> None: super().contents() output_current_draw = self.pwr_out.link().current_drawn self.fet = self.Block(Fet.PFet( @@ -315,7 +315,7 @@ def __init__(self, r1_val: RangeLike = 100 * kOhm(tol=0.01), r2_val: RangeLike = self.r2_val = self.ArgParameter(r2_val) self.rds_on = self.ArgParameter(rds_on) - def contents(self): + def contents(self) -> None: super().contents() self.r1 = self.Block(Resistor(resistance=self.r1_val)) self.r2 = self.Block(Resistor(resistance=self.r2_val)) @@ -383,7 +383,7 @@ def __init__(self, pull_resistance: RangeLike = 10 * kOhm(tol=0.05), amp_resista self.amp_resistance = self.ArgParameter(amp_resistance) self.diode_drop = self.ArgParameter(diode_drop) - def contents(self): + def contents(self) -> None: super().contents() control_voltage = self.btn_in.link().voltage.hull(self.gnd.link().voltage) pwr_voltage = self.pwr_out.link().voltage.hull(self.gnd.link().voltage) @@ -455,7 +455,7 @@ def __init__(self, pull_resistance: RangeLike = 10 * kOhm(tol=0.05), amp_resista self.btn_out = self.Export(self.pwr_gate.btn_out) self.control = self.Export(self.pwr_gate.control) - def contents(self): + def contents(self) -> None: super().contents() with self.implicit_connect( ImplicitConnect(self.gnd, [Common]), diff --git a/edg/parts/PriceGetter.py b/edg/parts/PriceGetter.py index f6a040eb2..ec4105f72 100644 --- a/edg/parts/PriceGetter.py +++ b/edg/parts/PriceGetter.py @@ -87,7 +87,7 @@ def generate_price(self, lcsc_part_number: str, quantity: int) -> Optional[float temp_price = price return quantity * temp_price - def run(self, design: CompiledDesign, args=None) -> List[Tuple[edgir.LocalPath, str]]: + def run(self, design: CompiledDesign, args: Dict[str, str]={}) -> List[Tuple[edgir.LocalPath, str]]: assert not args price_list = PartQuantityTransform(design).run() total_price: float = 0 diff --git a/edg/parts/ResistiveSensor.py b/edg/parts/ResistiveSensor.py index 133850403..90127eb42 100644 --- a/edg/parts/ResistiveSensor.py +++ b/edg/parts/ResistiveSensor.py @@ -20,7 +20,7 @@ def __init__(self, resistance_range: RangeLike, fixed_resistance: RangeLike) -> self.actual_impedance = self.Parameter(RangeExpr()) self.actual_series_impedance = self.Parameter(RangeExpr()) - def contents(self): + def contents(self) -> None: self.top = self.Block(Resistor(self.fixed_resistance, voltage=self.input.link().voltage)) self.bot = self.Block(PassiveConnector(2)) self.connect(self.input, self.top.a.adapt_to(VoltageSink( diff --git a/edg/parts/RfModules.py b/edg/parts/RfModules.py index b54d701e3..c73141b9b 100644 --- a/edg/parts/RfModules.py +++ b/edg/parts/RfModules.py @@ -2,7 +2,7 @@ class Xbee_S3b_Device(InternalSubcircuit, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() # only required pins are Vcc, GND, DOUT, DIN @@ -27,7 +27,7 @@ def __init__(self): self.rssi = self.Port(DigitalSource.from_bidir(digital_model), optional=True) self.associate = self.Port(DigitalSource.from_bidir(digital_model), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Sparkfun_RF:XBEE', @@ -70,7 +70,7 @@ def __init__(self) -> None: self.rssi = self.Export(self.ic.rssi, optional=True) self.associate = self.Export(self.ic.associate, optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.vdd_cap_0 = self.Block(DecouplingCapacitor( @@ -102,7 +102,7 @@ def __init__(self) -> None: self.cts = self.Port(DigitalSink.from_bidir(digital_model), optional=True) self.rts = self.Port(DigitalSource.from_bidir(digital_model), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical', diff --git a/edg/parts/Rf_Pn7160.py b/edg/parts/Rf_Pn7160.py index 7e4a9a695..52465b417 100644 --- a/edg/parts/Rf_Pn7160.py +++ b/edg/parts/Rf_Pn7160.py @@ -42,7 +42,7 @@ def __init__(self, ant_footprint: StringLike, freq: FloatLike, inductance: Float self.z_real = self.Parameter(FloatExpr()) self.z_imag = self.Parameter(FloatExpr()) - def generate(self): + def generate(self) -> None: super().generate() impedance = NfcAntenna.impedance_from_lrc(self.get(self.freq), self.get(self.inductance), @@ -76,7 +76,7 @@ def __init__(self, target_q: FloatLike, ant_r: FloatLike, ant_x: FloatLike): self.z_real = self.Parameter(FloatExpr()) self.z_imag = self.Parameter(FloatExpr()) - def generate(self): + def generate(self) -> None: super().generate() res_value = self.damp_res_from_impedance(complex(self.get(self.ant_r), self.get(self.ant_x)), @@ -119,7 +119,7 @@ def __init__(self, freq_cutoff: FloatLike, inductance: FloatLike, input_res: Flo self.out2 = self.Port(Passive()) self.gnd = self.Port(Ground.empty(), [Common]) - def generate(self): + def generate(self) -> None: super().generate() inductor_model = Inductor(self.get(self.inductance)*Henry(tol=0.1), @@ -168,7 +168,7 @@ def __init__(self, freq: FloatLike, src_r: FloatLike, src_x: FloatLike, snk_r: F self.out2 = self.Port(Passive()) self.gnd = self.Port(Ground.empty(), [Common]) - def generate(self): + def generate(self) -> None: super().generate() diff_cs, diff_cp = self._calculate_se_values(self.get(self.freq), @@ -198,7 +198,7 @@ def __init__(self, resistance: RangeLike, capacitance: RangeLike, voltage: Range self.out1 = self.Port(Passive()) self.out2 = self.Port(Passive()) - def contents(self): + def contents(self) -> None: super().contents() rrx_model = Resistor(resistance=self.resistance) self.rrx1 = self.Block(rrx_model) @@ -318,7 +318,7 @@ def contents(self) -> None: class Pn7160(Resettable, DiscreteRfWarning, Block): """Multi-protocol NFC controller, up to 1.3W output power, in I2C ('A' suffix) """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Pn7160_Device()) self.gnd = self.Export(self.ic.vss, [Common]) @@ -327,7 +327,7 @@ def __init__(self): self.i2c = self.Export(self.ic.i2c) self.irq = self.Export(self.ic.irq) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.reset, self.ic.ven) diff --git a/edg/parts/Rf_Sx1262.py b/edg/parts/Rf_Sx1262.py index 206e6620d..87cba6c8f 100644 --- a/edg/parts/Rf_Sx1262.py +++ b/edg/parts/Rf_Sx1262.py @@ -6,7 +6,7 @@ class Pe4259_Device(InternalSubcircuit, FootprintBlock, JlcPart): - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground()) @@ -25,7 +25,7 @@ def __init__(self): # note that most other comparable RF switches do not have single-pin control # a future revision so the application circuit will replace this part with a dual-pin control circuit - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -50,7 +50,7 @@ class Pe4259(Nonstrict3v3Compatible, Block): Requires all RF pins be held at 0v or are DC-blocked with a series cap. TODO: perhaps a RfSwitch base class? maybe some relation to AnalogSwitch? (though not valid at DC) """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Pe4259_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) @@ -60,7 +60,7 @@ def __init__(self): self.ctrl = self.Port(DigitalSink.empty()) self.vdd = self.Port(VoltageSink.empty(), [Power]) - def contents(self): + def contents(self) -> None: super().contents() self.vdd_res = self.Block(Resistor(1*kOhm(tol=0.05))) @@ -225,7 +225,7 @@ class Sx1262(Resettable, DiscreteRfWarning, Block): Up to 62.5kb/s in LoRa mode and 300kb/s in FSK mode. TODO: RF frequency parameterization """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Sx1262_Device()) self.pwr = self.Export(self.ic.vbat, [Power]) diff --git a/edg/parts/Rtc_Pcf2129.py b/edg/parts/Rtc_Pcf2129.py index cda7c22a0..75d641196 100644 --- a/edg/parts/Rtc_Pcf2129.py +++ b/edg/parts/Rtc_Pcf2129.py @@ -36,7 +36,7 @@ def __init__(self) -> None: voltage_out=self.pwr_bat.link().voltage )) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm', @@ -74,7 +74,7 @@ def __init__(self) -> None: self.clkout = self.Export(self.ic.clkout, optional=True) self.int = self.Export(self.ic.int, optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.vdd_res = self.Block(SeriesPowerResistor( diff --git a/edg/parts/SdCards.py b/edg/parts/SdCards.py index 9a9f8efd2..27c294958 100644 --- a/edg/parts/SdCards.py +++ b/edg/parts/SdCards.py @@ -66,7 +66,7 @@ class MicroSdSocket(SdCard): class Dm3btDsfPejs(MicroSdSocket, Connector, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() # TODO add pull up resistors and capacitors and w/e? self.footprint( @@ -89,7 +89,7 @@ def contents(self): class Molex1040310811(MicroSdSocket, Connector, JlcPart, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() # TODO add pull up resistors and capacitors and w/e? self.footprint( diff --git a/edg/parts/SolidStateRelay_G3VM_61GR2.py b/edg/parts/SolidStateRelay_G3VM_61GR2.py index 1f9622293..c5d368cc3 100644 --- a/edg/parts/SolidStateRelay_G3VM_61GR2.py +++ b/edg/parts/SolidStateRelay_G3VM_61GR2.py @@ -2,7 +2,7 @@ class G3VM_61GR2(SolidStateRelay, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.led_forward_voltage, (1.18, 1.48)*Volt) self.assign(self.led_current_limit, (3, 30)*mAmp) diff --git a/edg/parts/SolidStateRelay_Toshiba.py b/edg/parts/SolidStateRelay_Toshiba.py index db0fb6b4e..c3c2cb3d0 100644 --- a/edg/parts/SolidStateRelay_Toshiba.py +++ b/edg/parts/SolidStateRelay_Toshiba.py @@ -2,7 +2,7 @@ class Tlp3545a(SolidStateRelay, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.led_forward_voltage, (1.50, 1.80)*Volt) self.assign(self.led_current_limit, (5, 30)*mAmp) @@ -27,7 +27,7 @@ def contents(self): class Tlp170am(SolidStateRelay, FootprintBlock): - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.led_forward_voltage, (1.1, 1.4)*Volt) # 1.27 nominal self.assign(self.led_current_limit, (2, 30)*mAmp) diff --git a/edg/parts/SpeakerDriver_Analog.py b/edg/parts/SpeakerDriver_Analog.py index 0ffce861f..7ce1f910c 100644 --- a/edg/parts/SpeakerDriver_Analog.py +++ b/edg/parts/SpeakerDriver_Analog.py @@ -3,7 +3,7 @@ class Lm4871_Device(InternalSubcircuit, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink( @@ -21,7 +21,7 @@ def __init__(self): self.byp = self.Port(Passive()) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', { @@ -40,7 +40,7 @@ def contents(self): class Lm4871(SpeakerDriver, Block): - def __init__(self): + def __init__(self) -> None: super().__init__() # TODO should be a SpeakerDriver abstract part @@ -51,7 +51,7 @@ def __init__(self): self.sig = self.Port(AnalogSink.empty(), [Input]) self.spk = self.Port(SpeakerDriverPort(AnalogSource.empty()), [Output]) - def contents(self): + def contents(self) -> None: super().contents() # TODO size component based on higher level input? @@ -85,7 +85,7 @@ def contents(self): class Tpa2005d1_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink( @@ -107,7 +107,7 @@ def __init__(self): self.vo1 = self.Port(speaker_port) self.vo2 = self.Port(speaker_port) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm_ThermalVias', { @@ -144,7 +144,7 @@ def __init__(self, gain: RangeLike = Range.from_tolerance(20, 0.2)): self.gain = self.ArgParameter(gain) - def contents(self): + def contents(self) -> None: import math super().contents() @@ -185,7 +185,7 @@ def contents(self): class Pam8302a_Device(InternalSubcircuit, JlcPart, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink( @@ -206,7 +206,7 @@ def __init__(self): self.vop = self.Port(speaker_port) self.von = self.Port(speaker_port) - def contents(self): + def contents(self) -> None: self.footprint( 'U', 'Package_SO:MSOP-8_3x3mm_P0.65mm', { @@ -228,7 +228,7 @@ def contents(self): class Pam8302a(SpeakerDriver, Block): """PAM8302A configured in single-ended input mode.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Pam8302a_Device()) @@ -238,7 +238,7 @@ def __init__(self): self.sig = self.Port(AnalogSink.empty(), [Input]) self.spk = self.Port(SpeakerDriverPort(AnalogSource.empty()), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.pwr_cap0 = self.Block(DecouplingCapacitor( diff --git a/edg/parts/SpeakerDriver_Max98357a.py b/edg/parts/SpeakerDriver_Max98357a.py index 9e6353e1d..f0f060034 100644 --- a/edg/parts/SpeakerDriver_Max98357a.py +++ b/edg/parts/SpeakerDriver_Max98357a.py @@ -5,7 +5,7 @@ class Max98357a_Device(InternalSubcircuit, JlcPart, SelectorFootprint, PartsTablePart, GeneratorBlock, FootprintBlock): - def __init__(self): + def __init__(self) -> None: super().__init__() self.vdd = self.Port(VoltageSink( @@ -24,7 +24,7 @@ def __init__(self): self.generator_param(self.part, self.footprint_spec) - def generate(self): + def generate(self) -> None: super().generate() if not self.get(self.footprint_spec) or \ self.get(self.footprint_spec) == 'Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm': @@ -75,7 +75,7 @@ def generate(self): class Max98357a(SpeakerDriver, Block): """MAX98357A I2S speaker driver with default gain.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Max98357a_Device()) @@ -85,7 +85,7 @@ def __init__(self): self.i2s = self.Export(self.ic.i2s, [Input]) self.out = self.Export(self.ic.out, [Output]) - def contents(self): + def contents(self) -> None: super().contents() with self.implicit_connect( diff --git a/edg/parts/Speakers.py b/edg/parts/Speakers.py index 0bb704e57..2d7ee13bf 100644 --- a/edg/parts/Speakers.py +++ b/edg/parts/Speakers.py @@ -5,7 +5,7 @@ @abstract_block class Speaker(HumanInterface): """Abstract speaker part with speaker input port.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.input = self.Port(SpeakerPort.empty(), [Input]) diff --git a/edg/parts/SpiMemory_93Lc.py b/edg/parts/SpiMemory_93Lc.py index 0b1db327e..116f0da4b 100644 --- a/edg/parts/SpiMemory_93Lc.py +++ b/edg/parts/SpiMemory_93Lc.py @@ -40,7 +40,7 @@ def __init__(self, size: RangeLike): self.size = self.ArgParameter(size) self.generator_param(self.size) - def generate(self): + def generate(self) -> None: super().generate() suitable_parts = [part for part in self.PARTS if part[0] in self.get(self.size)] assert suitable_parts, "no memory in requested size range" @@ -68,7 +68,7 @@ class E93Lc_B(SpiMemory): """93LCxxB series of SPI EEPROMs. The E prefix is because Python identifiers can't start with numbers Note, A variant is 8-bit word, B variant is 16-bit word """ - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(E93Lc_B_Device(self.size)) diff --git a/edg/parts/SpiMemory_W25q.py b/edg/parts/SpiMemory_W25q.py index 615ba3d61..07a841e4e 100644 --- a/edg/parts/SpiMemory_W25q.py +++ b/edg/parts/SpiMemory_W25q.py @@ -1,3 +1,5 @@ +from typing import Any + from ..abstract_parts import * from .JlcPart import JlcPart @@ -40,7 +42,7 @@ def __init__(self, size: RangeLike): self.size = self.ArgParameter(size) self.generator_param(self.size) - def generate(self): + def generate(self) -> None: super().generate() suitable_parts = [part for part in self.PARTS if part[0] in self.get(self.size)] assert suitable_parts, "no memory in requested size range" @@ -69,11 +71,11 @@ def generate(self): class W25q(SpiMemory, SpiMemoryQspi, GeneratorBlock): """Winbond W25Q series of SPI memory devices """ - def __init__(self, *args, **kwargs): + def __init__(self, *args: Any, **kwargs: Any) -> None: super().__init__(*args, **kwargs) self.generator_param(self.io2.is_connected(), self.io3.is_connected()) - def contents(self): + def contents(self) -> None: super().contents() self.ic = self.Block(W25q_Device(self.size)) @@ -87,7 +89,7 @@ def contents(self): capacitance=0.1*uFarad(tol=0.2) )).connected(self.gnd, self.pwr) - def generate(self): + def generate(self) -> None: super().generate() self.require(self.io2.is_connected() == self.io3.is_connected()) diff --git a/edg/parts/SwitchMatrix.py b/edg/parts/SwitchMatrix.py index e4610e099..8f70896d3 100644 --- a/edg/parts/SwitchMatrix.py +++ b/edg/parts/SwitchMatrix.py @@ -118,7 +118,7 @@ def __init__(self, nrows: IntLike, ncols: IntLike, voltage_drop: RangeLike = (0, self.ncols = self.ArgParameter(ncols) self.generator_param(self.nrows, self.ncols) - def generate(self): + def generate(self) -> None: super().generate() row_ports = {} for row in range(self.get(self.nrows)): @@ -127,7 +127,7 @@ def generate(self): self.sw = ElementDict[Switch]() self.d = ElementDict[Diode]() for col in range(self.get(self.ncols)): - col_port = cast(DigitalSink, self.cols.append_elt(DigitalSink.empty(), str(col))) + col_port = self.cols.append_elt(DigitalSink.empty(), str(col)) col_port_model = DigitalSink() # ideal, negligible current draw (assumed) and thresholds checked at other side for (row, row_port) in row_ports.items(): sw = self.sw[f"{col},{row}"] = self.Block(Switch( diff --git a/edg/parts/SwitchedCap_TexasInstruments.py b/edg/parts/SwitchedCap_TexasInstruments.py index a01903a9b..aba203f43 100644 --- a/edg/parts/SwitchedCap_TexasInstruments.py +++ b/edg/parts/SwitchedCap_TexasInstruments.py @@ -5,7 +5,7 @@ class Lm2664_Device(InternalSubcircuit, JlcPart, FootprintBlock): FREQUENCY = Range(40000, 80000) # Hz SWITCH_RESISTANCE = Range(4, 8) # Ohm - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground(), [Common]) self.vp = self.Port(VoltageSink( @@ -27,7 +27,7 @@ def __init__(self): # input_threshold_abs=(0.8, 2)*Volt # ), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'U', 'Package_TO_SOT_SMD:SOT-23-6', @@ -58,7 +58,7 @@ def __init__(self, output_resistance_limit: FloatLike = 25 * Ohm, self.output_resistance_limit = self.ArgParameter(output_resistance_limit) self.output_ripple_limit = self.ArgParameter(output_ripple_limit) - def contents(self): + def contents(self) -> None: super().contents() self.require(self.output_resistance_limit >= 2 * self.ic.SWITCH_RESISTANCE.upper, "min output resistance spec below switch resistance") diff --git a/edg/parts/ThermalSensor_FlirLepton.py b/edg/parts/ThermalSensor_FlirLepton.py index 09e944608..d98f27fa4 100644 --- a/edg/parts/ThermalSensor_FlirLepton.py +++ b/edg/parts/ThermalSensor_FlirLepton.py @@ -87,7 +87,7 @@ class FlirLepton(Sensor, Resettable, Block): <50mK (35mK typical) NETD. Only the part number for the socket is generated, the sensor (a $100+ part) must be purchased separately. """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(FlirLepton_Device()) self.gnd = self.Export(self.ic.gnd, [Common]) @@ -105,7 +105,7 @@ def __init__(self): self.cci = self.Export(self.ic.cci, doc="I2C-like Command and Control Interface") self.vsync = self.Export(self.ic.vsync, optional=True, doc="Optional frame-sync output") - def contents(self): + def contents(self) -> None: super().contents() self.vddc_cap = self.Block(DecouplingCapacitor(100*nFarad(tol=0.2))).connected(self.gnd, self.ic.vddc) diff --git a/edg/parts/UsbInterface_Ft232h.py b/edg/parts/UsbInterface_Ft232h.py index ea28f1361..1530e04b9 100644 --- a/edg/parts/UsbInterface_Ft232h.py +++ b/edg/parts/UsbInterface_Ft232h.py @@ -59,7 +59,7 @@ def __init__(self) -> None: self.adbus = self.Port(Vector(DigitalBidir.empty())) self.acbus = self.Port(Vector(DigitalBidir.empty())) - def contents(self): + def contents(self) -> None: super().contents() for i in range(8): @@ -132,14 +132,15 @@ def contents(self): class Ft232EepromDriver(InternalSubcircuit, Block): """Adapts the EECLK and EEDATA pins of the FT232 to the SPI of the EEPROM""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink.empty()) self.eeclk = self.Port(DigitalSink.empty()) self.eedata = self.Port(DigitalBidir.empty()) self.spi = self.Port(SpiController.empty()) - def contents(self): + def contents(self) -> None: + super().contents() self.connect(self.eeclk, self.spi.sck) self.connect(self.eedata, self.spi.mosi) self.do_pull = self.Block(PullupResistor(10*kOhm(tol=0.05))).connected(self.pwr, self.spi.miso) diff --git a/edg/parts/UsbPorts.py b/edg/parts/UsbPorts.py index 2bfbb8dd5..c7aec1669 100644 --- a/edg/parts/UsbPorts.py +++ b/edg/parts/UsbPorts.py @@ -13,7 +13,7 @@ def __init__(self) -> None: self.usb.init_from(UsbDevicePort()) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( 'J', 'Connector_USB:USB_A_Molex_105057_Vertical', @@ -47,7 +47,7 @@ def __init__(self, voltage_out: RangeLike = UsbConnector.USB2_VOLTAGE_RANGE, # self.cc = self.Port(UsbCcPort(pullup_capable=cc_pullup_capable), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.lcsc_part, 'C165948') # note, many other pin-compatible parts also available @@ -118,7 +118,7 @@ class UsbAPlugPads(UsbDeviceConnector, FootprintBlock): def __init__(self) -> None: super().__init__() - def contents(self): + def contents(self) -> None: super().contents() self.pwr.init_from(VoltageSource( voltage_out=self.USB2_VOLTAGE_RANGE, @@ -143,7 +143,7 @@ class UsbMicroBReceptacle(UsbDeviceConnector, FootprintBlock): def __init__(self) -> None: super().__init__() - def contents(self): + def contents(self) -> None: super().contents() self.pwr.init_from(VoltageSource( voltage_out=self.USB2_VOLTAGE_RANGE, @@ -186,7 +186,7 @@ def contents(self) -> None: class Tpd2e009(UsbEsdDiode, FootprintBlock, JlcPart): - def contents(self): + def contents(self) -> None: # Note, also compatible: https://www.diodes.com/assets/Datasheets/DT1452-02SO.pdf # PESD5V0X1BT,215 (different architecture, but USB listed as application) super().contents() @@ -206,7 +206,7 @@ def contents(self): class Pesd5v0x1bt(UsbEsdDiode, FootprintBlock, JlcPart): """Ultra low capacitance ESD protection diode (0.9pF typ), suitable for USB and GbE""" - def contents(self): + def contents(self) -> None: super().contents() self.gnd.init_from(Ground()) self.usb.init_from(UsbPassivePort()) @@ -226,7 +226,7 @@ def contents(self): class Pgb102st23(UsbEsdDiode, FootprintBlock, JlcPart): """ESD suppressor, suitable for high speed protocols including USB2.0, 0.12pF typ""" - def contents(self): + def contents(self) -> None: super().contents() self.gnd.init_from(Ground()) self.usb.init_from(UsbPassivePort()) diff --git a/edg/parts/VoltageReferences.py b/edg/parts/VoltageReferences.py index 0f1e15a9d..2c311fa3c 100644 --- a/edg/parts/VoltageReferences.py +++ b/edg/parts/VoltageReferences.py @@ -14,7 +14,7 @@ def __init__(self, output_voltage: RangeLike): self.output_voltage = self.ArgParameter(output_voltage) self.generator_param(self.output_voltage) - def generate(self): + def generate(self) -> None: super().generate() parts = [ # output voltage, table 7.5 (Range(1.2475, 1.2525), 'REF3012', 'C34674'), # REF3012AIDBZR diff --git a/edg/parts/test_JlcCapacitor.py b/edg/parts/test_JlcCapacitor.py index edf660b46..380878b7c 100644 --- a/edg/parts/test_JlcCapacitor.py +++ b/edg/parts/test_JlcCapacitor.py @@ -3,7 +3,7 @@ class JlcCapacitorTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(JlcCapacitor( capacitance=10 * nFarad(tol=0.1), @@ -14,7 +14,7 @@ def __init__(self): class JlcBigCapacitorTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(JlcCapacitor( capacitance=(50, 1000) * uFarad, diff --git a/edg/parts/test_JlcResistor.py b/edg/parts/test_JlcResistor.py index ff851c63a..44fddcb9e 100644 --- a/edg/parts/test_JlcResistor.py +++ b/edg/parts/test_JlcResistor.py @@ -3,7 +3,7 @@ class JlcResistorTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(JlcResistor( resistance=750 * Ohm(tol=0.10), diff --git a/edg/parts/test_inductor.py b/edg/parts/test_inductor.py index e23db2095..8fc3521a2 100644 --- a/edg/parts/test_inductor.py +++ b/edg/parts/test_inductor.py @@ -4,7 +4,7 @@ class JlcInductorTestTop(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.dut = self.Block(JlcInductor( inductance=2.2 * uHenry(tol=0.2), diff --git a/edg/parts/test_kicad_import_jlc.py b/edg/parts/test_kicad_import_jlc.py index 5deb51f3b..64986d047 100644 --- a/edg/parts/test_kicad_import_jlc.py +++ b/edg/parts/test_kicad_import_jlc.py @@ -17,7 +17,7 @@ def __init__(self) -> None: class JlcImportBlackboxTestCase(unittest.TestCase): - def test_import_blackbox(self): + def test_import_blackbox(self) -> None: # the elaborate_toplevel wrapper is needed since the inner block uses array ports pb = Builder.builder.elaborate_toplevel(JlcBlackboxBlock()) constraints = list(map(lambda pair: pair.value, pb.constraints)) diff --git a/examples/test_bldc_controller.py b/examples/test_bldc_controller.py index 397fd6c9f..eda73bf43 100644 --- a/examples/test_bldc_controller.py +++ b/examples/test_bldc_controller.py @@ -22,7 +22,7 @@ def __init__(self, max_current: FloatLike): class MagneticEncoder(Connector, Magnetometer, Block): """Connector to AS5600 mangetic encoder, https://ams.com/documents/20143/36005/AS5600_DS000365_5-00.pdf""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(PassiveConnector()) @@ -39,7 +39,7 @@ def __init__(self): class I2cConnector(Connector, Block): """Generic I2C connector, QWIIC pinning (gnd/vcc/sda/scl)""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(PassiveConnector()) @@ -55,7 +55,7 @@ def __init__(self): class BldcHallSensor(Connector, Block): """Generic BLDC hall sensor, as +5v, U, V, W, GND""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(PassiveConnector()) diff --git a/examples/test_deskcontroller.py b/examples/test_deskcontroller.py index ff2eb6dfe..08c91967c 100644 --- a/examples/test_deskcontroller.py +++ b/examples/test_deskcontroller.py @@ -6,7 +6,7 @@ class JiecangConnector(Block): """RJ-12 connector for (some?) Jiecang standing desk controllers https://github.com/phord/Jarvis?tab=readme-ov-file#physical-interface-rj-12""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(PassiveConnector(length=6)) self.gnd = self.Export(self.conn.pins.request('2').adapt_to(Ground()), [Common]) diff --git a/examples/test_fcml.py b/examples/test_fcml.py index 94aa637e3..551d138e0 100644 --- a/examples/test_fcml.py +++ b/examples/test_fcml.py @@ -84,7 +84,7 @@ def __init__(self, is_first: BoolLike = False, *, self.is_first = self.ArgParameter(is_first) self.generator_param(self.is_first, self.high_boot_out.is_connected()) - def generate(self): + def generate(self) -> None: super().generate() # control path is still defined in HDL if self.get(self.is_first): @@ -291,7 +291,7 @@ def __init__(self, levels: IntLike, ratios: RangeLike, frequency: RangeLike, *, self.ratios = self.ArgParameter(ratios) self.generator_param(self.levels, self.ratios) - def generate(self): + def generate(self) -> None: super().generate() levels = self.get(self.levels) assert levels >= 2, "levels must be 2 or more" diff --git a/examples/test_high_switch.py b/examples/test_high_switch.py index 64c62f7b8..cdd14cd22 100644 --- a/examples/test_high_switch.py +++ b/examples/test_high_switch.py @@ -22,7 +22,7 @@ def __init__(self) -> None: self.controller = self.Port(CanTransceiverPort.empty(), [Input]) self.can = self.Port(CanDiffPort.empty(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(CalSolCanConnector()) @@ -55,7 +55,7 @@ class CanFuse(PptcFuse, FootprintBlock): def __init__(self, trip_current: RangeLike = (100, 200)*mAmp): super().__init__(trip_current) - def contents(self): + def contents(self) -> None: super().contents() self.assign(self.actual_trip_current, 150*mAmp(tol=0)) @@ -82,7 +82,7 @@ def __init__(self) -> None: )) self.gnd = self.Port(Ground()) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -107,7 +107,7 @@ def __init__(self) -> None: self.gnd = self.Port(Ground()) self.differential = self.Port(CanDiffPort(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -134,7 +134,7 @@ def __init__(self) -> None: self.gnd = self.Port(Ground()) self.differential = self.Port(CanDiffPort(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -161,7 +161,7 @@ def __init__(self) -> None: self.gnd = self.Port(Ground()) self.differential = self.Port(CanDiffPort(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( @@ -187,7 +187,7 @@ def __init__(self, current_draw: RangeLike = RangeExpr()) -> None: for i in range(2): self.out[i] = self.Port(VoltageSink(current_draw=current_draw)) - def contents(self): + def contents(self) -> None: super().contents() self.footprint( diff --git a/examples/test_iot_blinds.py b/examples/test_iot_blinds.py index d46c2a8fa..b3c49c38b 100644 --- a/examples/test_iot_blinds.py +++ b/examples/test_iot_blinds.py @@ -4,7 +4,7 @@ class IotRollerBlindsConnector(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(JstXh(length=6)) self.gnd = self.Export(self.conn.pins.request('4').adapt_to(Ground())) @@ -19,7 +19,7 @@ def __init__(self): class PowerInConnector(Connector): - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(JstPh()) self.gnd = self.Export(self.conn.pins.request('1').adapt_to(Ground())) @@ -30,7 +30,7 @@ def __init__(self): class PowerOutConnector(Connector): - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(JstPh()) self.gnd = self.Export(self.conn.pins.request('1').adapt_to(Ground())) @@ -162,7 +162,7 @@ def refinements(self) -> Refinements: class MotorConnector(Block): - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(Picoblade(length=2)) self.motor1 = self.Export(self.conn.pins.request('1').adapt_to(DigitalSink(current_draw=(0, 0.5)*Amp))) diff --git a/examples/test_iot_display.py b/examples/test_iot_display.py index 4c78e3f40..0df59c07a 100644 --- a/examples/test_iot_display.py +++ b/examples/test_iot_display.py @@ -19,7 +19,7 @@ def __init__(self, frequency: RangeLike = RangeExpr.ZERO, max_rds: FloatLike = 1 self.frequency = self.ArgParameter(frequency) self.max_rds = self.ArgParameter(max_rds) - def contents(self): + def contents(self) -> None: super().contents() self.drv = self.Block(SwitchFet.PFet( diff --git a/examples/test_iot_led_driver.py b/examples/test_iot_led_driver.py index 3af1c79e9..05ecb926c 100644 --- a/examples/test_iot_led_driver.py +++ b/examples/test_iot_led_driver.py @@ -4,7 +4,7 @@ class PowerInConnector(Connector): - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(JstShSmHorizontal()) self.gnd = self.Export(self.conn.pins.request('1').adapt_to(Ground())) diff --git a/examples/test_multimeter.py b/examples/test_multimeter.py index aae15d72c..6cc702505 100644 --- a/examples/test_multimeter.py +++ b/examples/test_multimeter.py @@ -29,7 +29,7 @@ def __init__(self, resistances: ArrayRangeLike): self.resistances = self.ArgParameter(resistances) self.generator_param(self.resistances) - def generate(self): + def generate(self) -> None: super().generate() self.res = ElementDict[Resistor]() for i, resistance in enumerate(self.get(self.resistances)): @@ -49,7 +49,7 @@ class MultimeterAnalog(KiCadSchematicBlock, Block): TODO: support wider ranges, to be implemented with port array support """ - def __init__(self): + def __init__(self) -> None: super().__init__() # TODO: separate Vref? @@ -62,7 +62,7 @@ def __init__(self): self.select = self.Port(Vector(DigitalSink.empty())) - def contents(self): + def contents(self) -> None: super().contents() self.res = self.Block(Resistor(1*MOhm(tol=0.01), voltage=self.input_positive.link().voltage)) @@ -104,7 +104,7 @@ def __init__(self, voltage_rating: RangeLike = RangeExpr()): self.voltage_rating = self.ArgParameter(voltage_rating) - def contents(self): + def contents(self) -> None: super().contents() max_in_voltage = self.control.link().voltage.upper() diff --git a/examples/test_robotcrawler.py b/examples/test_robotcrawler.py index 277200d34..58ceab71b 100644 --- a/examples/test_robotcrawler.py +++ b/examples/test_robotcrawler.py @@ -7,7 +7,7 @@ class ServoFeedbackConnector(Connector, Block): """4-pin connector modeling the FS90-FB micro servo with positional feedback, https://www.pololu.com/product/3436 """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(PinHeader254(4)) diff --git a/examples/test_robotowl.py b/examples/test_robotowl.py index ff0cb5a46..6711f30b3 100644 --- a/examples/test_robotowl.py +++ b/examples/test_robotowl.py @@ -13,7 +13,7 @@ def __init__(self) -> None: self.pwr = self.Port(VoltageSink.empty(), [Power]) self.out = self.Port(AnalogSource.empty(), [Output]) - def contents(self): + def contents(self) -> None: super().contents() self.import_kicad( self.file_path("resources", f"{self.__class__.__name__}.kicad_sch"), diff --git a/examples/test_swd_debugger.py b/examples/test_swd_debugger.py index 6d5d3a055..c11e2150e 100644 --- a/examples/test_swd_debugger.py +++ b/examples/test_swd_debugger.py @@ -14,7 +14,7 @@ def __init__(self) -> None: self.swo = self.Port(DigitalBidir.empty(), optional=True) self.tdi = self.Port(DigitalBidir.empty(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(PinHeader127DualShrouded(10)) @@ -39,7 +39,7 @@ def __init__(self) -> None: self.reset = self.Port(DigitalSink.empty(), optional=True) self.swo = self.Port(DigitalBidir.empty(), optional=True) - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(PinHeader254DualShroudedInline(6)) diff --git a/examples/test_tofarray.py b/examples/test_tofarray.py index 806c145fd..79bc7b241 100644 --- a/examples/test_tofarray.py +++ b/examples/test_tofarray.py @@ -24,7 +24,7 @@ def __init__(self) -> None: class TofArray(JlcBoardTop): """A ToF LiDAR array with application as emulating a laser harp and demonstrating another array topology. """ - def __init__(self): + def __init__(self) -> None: super().__init__() # design configuration variables diff --git a/examples/test_usb_fpga_programmer.py b/examples/test_usb_fpga_programmer.py index 7bafc9191..3f3763aa9 100644 --- a/examples/test_usb_fpga_programmer.py +++ b/examples/test_usb_fpga_programmer.py @@ -5,7 +5,7 @@ class FpgaProgrammingHeader(Connector, Block): """Custom programming header for iCE40 loosely based on the SWD pinning""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.pwr = self.Port(VoltageSink.empty(), optional=True) self.gnd = self.Port(Ground.empty(), [Common]) @@ -13,7 +13,7 @@ def __init__(self): self.cs = self.Port(DigitalSink.empty()) self.reset = self.Port(DigitalSink.empty()) - def contents(self): + def contents(self) -> None: super().contents() self.conn = self.Block(PinHeader127DualShrouded(10)) self.connect(self.pwr, self.conn.pins.request('1').adapt_to(VoltageSink())) diff --git a/examples/test_usb_key.py b/examples/test_usb_key.py index ff836b85a..d4eed6707 100644 --- a/examples/test_usb_key.py +++ b/examples/test_usb_key.py @@ -5,11 +5,11 @@ class StTscSenseChannel(Block): """Sense channel for STM micros' TSC peripheral.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.io = self.Port(DigitalBidir.empty(), [Input]) - def contents(self): + def contents(self) -> None: super().contents() self.res = self.Block(Resistor(resistance=10*kOhm(tol=0.05))) # recommended by ST self.connect(self.io, self.res.a.adapt_to(DigitalBidir())) # ideal @@ -19,12 +19,12 @@ def contents(self): class StTscReference(Block): """Reference capacitor for STM micros' TSC peripheral.""" - def __init__(self): + def __init__(self) -> None: super().__init__() self.gnd = self.Port(Ground.empty(), [Common]) self.io = self.Port(DigitalBidir.empty(), [Input]) - def contents(self): + def contents(self) -> None: super().contents() self.cap = self.Block(Capacitor(10*nFarad(tol=0.2), voltage=self.io.link().voltage)) self.connect(self.cap.pos.adapt_to(DigitalBidir()), self.io) diff --git a/examples/test_usb_source_measure.py b/examples/test_usb_source_measure.py index 2c9e54431..265589b74 100644 --- a/examples/test_usb_source_measure.py +++ b/examples/test_usb_source_measure.py @@ -9,7 +9,7 @@ class SourceMeasureDutConnector(Connector): - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(PinHeader254Horizontal(3)) self.gnd = self.Export(self.conn.pins.request('1').adapt_to(Ground()), [Common]) @@ -18,7 +18,7 @@ def __init__(self): class SourceMeasureFan(Connector): - def __init__(self): + def __init__(self) -> None: super().__init__() self.conn = self.Block(JstPhKVertical(2)) self.gnd = self.Export(self.conn.pins.request('1').adapt_to(Ground()), [Common]) @@ -44,7 +44,7 @@ def __init__(self, resistance: RangeLike): self.sense_in = self.Port(AnalogSource.empty()) self.sense_out = self.Port(AnalogSource.empty()) - def contents(self): + def contents(self) -> None: super().contents() self.import_kicad(self.file_path("UsbSourceMeasure", f"{self.__class__.__name__}.kicad_sch"), locals={ @@ -95,7 +95,7 @@ def __init__(self, resistances: ArrayRangeLike, currents: ArrayRangeLike): self.out_range = self.Parameter(RangeExpr()) - def generate(self): + def generate(self) -> None: super().generate() self.ranges = ElementDict[SourceMeasureRangingCell]() @@ -370,7 +370,7 @@ class SrLatchInverted(Block): and NOR2 output is high, which feeds back into a NOR1 input to keep NOR1 low. NOR2 handles reset without priority, when the input goes high, its output goes low which clears the latch. """ - def __init__(self): + def __init__(self) -> None: super().__init__() self.ic = self.Block(Sn74lvc2g02()) self.gnd = self.Export(self.ic.gnd, [Common]) @@ -380,7 +380,7 @@ def __init__(self): self.rst = self.Export(self.ic.in2a) # any in2 self.out = self.Export(self.ic.out1) - def contents(self): + def contents(self) -> None: super().contents() self.connect(self.ic.out1, self.ic.in2b) self.connect(self.ic.out2, self.ic.in1b) @@ -421,7 +421,7 @@ def __init__(self, current: RangeLike, rds_on: RangeLike): self.current = self.ArgParameter(current) self.rds_on = self.ArgParameter(rds_on) - def contents(self): + def contents(self) -> None: super().contents() self.import_kicad(self.file_path("UsbSourceMeasure", f"{self.__class__.__name__}.kicad_sch"), diff --git a/mypy.ini b/mypy.ini deleted file mode 100644 index 31671bdcc..000000000 --- a/mypy.ini +++ /dev/null @@ -1,2 +0,0 @@ -[mypy] -check_untyped_defs = True diff --git a/pyproject.toml b/pyproject.toml index 6ae378361..0defa0066 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -30,5 +30,12 @@ packages = ["edg.edgir", "edg.edgrpc", "edg.core", "edg.hdl_server", "edg.electr [tool.setuptools.package-data] edg = ["core/resources/edg-compiler-precompiled.jar", "electronics_model/resources/kicad_footprints.json", "abstract_parts/resources/*.kicad_sch", "parts/resources/Pruned_JLCPCB SMT Parts Library(20220419).csv", "parts/resources/*.kicad_sch"] +[tool.mypy] +# enable_error_code = ["explicit-override"] +strict = true + +implicit_reexport = true +disallow_any_generics = false + [project.urls] Homepage = "https://github.com/BerkeleyHCI/PolymorphicBlocks"