From 84f04c85a2423e7a75f02ac99ebfd7b09d2e3711 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Thu, 18 Dec 2025 02:16:26 +0530 Subject: [PATCH 1/2] fix: Include segment number during bdf check Include segment number as well while checking for the root port's bdf in the API val_pcie_parent_is_rootport(). Signed-off-by: Vidya Sagar --- val/src/acs_pcie.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/val/src/acs_pcie.c b/val/src/acs_pcie.c index 8f50018..795325e 100644 --- a/val/src/acs_pcie.c +++ b/val/src/acs_pcie.c @@ -2263,7 +2263,8 @@ val_pcie_parent_is_rootport(uint32_t dsf_bdf, uint32_t *rp_bdf) /* Check if device is a direct child of this root port */ val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); if ((dsf_bus == ((reg_value >> SECBN_SHIFT) & SECBN_MASK)) && - (dsf_bus <= ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK))) + (dsf_bus <= ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK)) && + (PCIE_EXTRACT_BDF_SEG(bdf) == PCIE_EXTRACT_BDF_SEG(dsf_bdf))) { *rp_bdf = bdf; return 0; From 3c2f1f65619e316408f981fb29353ee986e01c3f Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Thu, 18 Dec 2025 02:12:45 +0530 Subject: [PATCH 2/2] chore: Add support to disable & re-enable DPC Add support to disable & re-enable DPC during the execution of rule PCI_IN_19. This avoids unwanted DPC trigger and hence avoids link down event. Signed-off-by: Vidya Sagar --- test_pool/pcie/p030.c | 24 +++++++++++++++- val/include/val_interface.h | 2 ++ val/src/acs_pcie.c | 57 +++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/test_pool/pcie/p030.c b/test_pool/pcie/p030.c index e43a861..ec16590 100644 --- a/test_pool/pcie/p030.c +++ b/test_pool/pcie/p030.c @@ -48,6 +48,7 @@ payload(void) uint32_t bdf; uint32_t dp_type; uint32_t dsf_bdf; + uint32_t parent_bdf; uint32_t pe_index; uint32_t tbl_index; uint32_t bar_data; @@ -56,6 +57,7 @@ payload(void) uint64_t bar_base; uint32_t status; uint32_t timeout; + uint32_t dpc_trig_val = 0; pcie_device_bdf_table *bdf_tbl_ptr; @@ -104,13 +106,24 @@ payload(void) val_pcie_get_mmio_bar(bdf, &bar_base); /* Skip this function if it doesn't have mmio BAR */ - val_print(ACS_PRINT_DEBUG, " Bar Base %x", bar_base); + val_print(ACS_PRINT_DEBUG, " Bar Base %x\n", bar_base); if (!bar_base) continue; /* Disable error reporting of this function to the Upstream */ val_pcie_disable_eru(bdf); + if ((dp_type == RP) || (dp_type == DP)) + { + /* Disable DPC for the rootport / Dowstream port */ + dpc_trig_val = val_pcie_disable_dpc(bdf); + } else if (!val_pcie_parent_is_rootport(bdf, &parent_bdf)) + { + /* Disable DPC for the parent rootport */ + val_print(ACS_PRINT_DEBUG, "RP BDF = 0x%08x\n", parent_bdf); + dpc_trig_val = val_pcie_disable_dpc(parent_bdf); + } + /* * Clear unsupported request detected bit in Device * Status Register to clear any pending urd status. @@ -158,6 +171,15 @@ payload(void) /* Enable memory space access to decode BAR addresses */ val_pcie_enable_msa(bdf); + /* Enable DPC trigger if it was disabled */ + if (dpc_trig_val) + { + if ((dp_type == RP) || (dp_type == DP)) + val_pcie_enable_dpc(bdf, dpc_trig_val); + else + val_pcie_enable_dpc(parent_bdf, dpc_trig_val); + } + /* Reset the loop variables */ bar_data = 0; } diff --git a/val/include/val_interface.h b/val/include/val_interface.h index deb40d2..d482555 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -270,6 +270,8 @@ void val_pcie_enable_msa(uint32_t bdf); void val_pcie_clear_urd(uint32_t bdf); void val_pcie_enable_eru(uint32_t bdf); void val_pcie_disable_eru(uint32_t bdf); +uint32_t val_pcie_disable_dpc(uint32_t bdf); +void val_pcie_enable_dpc(uint32_t bdf, uint32_t dpc_trig_val); void val_pcie_get_mmio_bar(uint32_t bdf, void *base); void val_pcie_read_acsctrl(uint32_t arr[][1]); void val_pcie_write_acsctrl(uint32_t arr[][1]); diff --git a/val/src/acs_pcie.c b/val/src/acs_pcie.c index 795325e..f48afff 100644 --- a/val/src/acs_pcie.c +++ b/val/src/acs_pcie.c @@ -1225,6 +1225,63 @@ val_pcie_disable_eru(uint32_t bdf) val_pcie_write_cfg(bdf, pciecs_base + DCTLR_OFFSET, reg_value & dis_mask); } +/** + @brief Disable DPC trigger enable bits + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return DPC trigger enable bits value +**/ +uint32_t +val_pcie_disable_dpc(uint32_t bdf) +{ + uint32_t dpc_cap_base; + uint32_t reg_value; + uint32_t status; + uint8_t dpc_trig_val; + + /* Check DPC capability */ + status = val_pcie_find_capability(bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base); + if (status == PCIE_CAP_NOT_FOUND) + { + val_print(ACS_PRINT_DEBUG, "ECID_DPC not found\n", 0); + return 0; + } + + /* Disable DPC trigger enable bits */ + val_pcie_read_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, ®_value); + dpc_trig_val = (reg_value >> DPC_CTRL_TRG_EN_SHIFT) & DPC_CTRL_TRG_EN_MASK; + reg_value &= ~(DPC_CTRL_TRG_EN_MASK << DPC_CTRL_TRG_EN_SHIFT); + val_pcie_write_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, reg_value); + return dpc_trig_val; +} + +/** + @brief Enable DPC trigger enable bits + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @param dpc_trig_val - DPC trigger enable bits value + @return None +**/ +void +val_pcie_enable_dpc(uint32_t bdf, uint32_t dpc_trig_val) +{ + uint32_t dpc_cap_base; + uint32_t reg_value; + uint32_t status; + + /* Check DPC capability */ + status = val_pcie_find_capability(bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base); + if (status == PCIE_CAP_NOT_FOUND) + { + val_print(ACS_PRINT_DEBUG, "ECID_DPC not found\n", 0); + return; + } + + /* Enable DPC trigger enable bits */ + val_pcie_read_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, ®_value); + reg_value &= ~(DPC_CTRL_TRG_EN_MASK << DPC_CTRL_TRG_EN_SHIFT); + reg_value |= ((dpc_trig_val & DPC_CTRL_TRG_EN_MASK) << DPC_CTRL_TRG_EN_SHIFT); + val_pcie_write_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, reg_value); +} + /** @brief Returns whether a device's bit-field passed the compliance check or not. The device under test is indicated by input bdf.